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Add MCF52259 demo.

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This commit is contained in:
Richard Barry 2009-02-07 17:52:41 +00:00
parent 8981a8539a
commit fe73d24184
60 changed files with 10188 additions and 0 deletions
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81
Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.c Normal file
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/*
* File: mcf52xx.c
* Purpose: Source to select CF derivative
*
* Notes:
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
/********************************************************************/
#include "common.h"
/********************************************************************/
/*
* Pause for the specified number of micro-seconds.
* Uses DTIM3 as a timer
*/
void
cpu_pause(int usecs)
{
/* Enable the DMA Timer 3 */
MCF_DTIM3_DTRR = (vuint32)(usecs - 1);
MCF_DTIM3_DTER = MCF_DTIM_DTER_REF;
MCF_DTIM3_DTMR = 0
| MCF_DTIM_DTMR_PS(SYSTEM_CLOCK)
| MCF_DTIM_DTMR_FRR
| MCF_DTIM_DTMR_CLK_DIV1
| MCF_DTIM_DTMR_RST;
while ((MCF_DTIM3_DTER & MCF_DTIM_DTER_REF) == 0)
{};
/* Disable the timer */
MCF_DTIM3_DTMR = 0;
}
/********************************************************************/
void
board_handle_interrupt (int vector)
{
switch (vector)
{
case 65: /* Eport Interrupt 1 */
printf("SW2\n");
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF1;
break;
case 69: /* Eport Interrupt 5 */
printf("SW1\n");
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF5;
break;
case 71: /* Eport Interrupt 7 */
printf("ABORT\n");
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF7;
break;
case 66: /* Eport Interrupt 2 */
case 67: /* Eport Interrupt 3 */
case 68: /* Eport Interrupt 4 */
case 70: /* Eport Interrupt 6 */
default:
MCF_EPORT_EPFR = (uint8)(0x01 << (vector - 64));
printf("Edge Port Interrupt #%d\n",vector - 64);
break;
}
}
/********************************************************************/
/********************************************************************/
void
cpu_handle_interrupt (int vector)
{
if (vector < 64 || vector > 192)
return;
if (vector >= 64 && vector <= 71)
board_handle_interrupt(vector);
else
printf("User Defined Vector #%d\n",vector);
}
/********************************************************************/

48
Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x.h Normal file
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/*
* File: mcf5225x.h
* Purpose: Register and bit definitions
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#ifndef __MCF5225x_H__
#define __MCF5225x_H__
/********************************************************************/
/*
* 5225x includes
*/
#include "MCF52259_SCM.h"
#include "MCF52259_DMA.h"
#include "MCF52259_UART.h"
#include "MCF52259_I2C.h"
#include "MCF52259_QSPI.h"
#include "MCF52259_TMR.h"
#include "MCF52259_INTC.h"
#include "MCF52259_FEC.h"
#include "MCF52259_GPIO.h"
#include "MCF52259_PAD.h"
#include "MCF52259_RCM.h"
#include "MCF52259_CCM.h"
#include "MCF52259_PMM.h"
#include "MCF52259_CLOCK.h"
#include "MCF52259_EPORT.h"
#include "MCF52259_BWT.h"
#include "MCF52259_PIT.h"
#include "MCF52259_FlexCAN.h"
#include "MCF52259_RTC.h"
#include "MCF52259_ADC.h"
#include "MCF52259_GPT.h"
#include "MCF52259_PWM.h"
#include "MCF52259_USB_OTG.h"
#include "MCF52259_CFM.h"
#include "MCF52259_RNGA.h"
#include "MCF52259_fbcs.h"
#include "mcf52259_dtim.h"
/********************************************************************/
#endif /* __MCF5225x_H__ */

153
Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_lo.s Normal file
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/*
* File: mcf5225x_lo.s
* Purpose: Low-level routines for the MCF5225x.
*
* Notes:
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#define mcf5225x_init _mcf5225x_init
#define common_startup _common_startup
#define cpu_startup _cpu_startup
#define main _main
#define __IPSBAR ___IPSBAR
#define __SRAM ___SRAM
#define __FLASH ___FLASH
#define __SP_INIT ___SP_INIT
.extern __IPSBAR
.extern __SRAM
.extern __FLASH
.extern __SP_INIT
.extern mcf5225x_init
.extern common_startup
.extern cpu_startup
.extern main
.global asm_startmeup
.global _asm_startmeup
.global d0_reset
.global _d0_reset
.global d1_reset
.global _d1_reset
.data
d0_reset:
_d0_reset: .long 0
d1_reset:
_d1_reset: .long 0
.text
/********************************************************************
*
* This is the main entry point upon hard reset. The memory map is
* setup based on linker file definitions, then the higher level
* system initialization routine is called. Finally, we jump to the
* "main" process.
*/
asm_startmeup:
_asm_startmeup:
move.w #0x2700,sr
/* Save off reset values of D0 and D1 */
move.l d0,d6
move.l d1,d7
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #__SRAM,d0
andi.l #0xFFFF0000,d0
add.l #0x21,d0
movec d0,RAMBAR1
/* Locate Stack Pointer */
move.l #__SP_INIT,sp
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASH,d0
cmp.l #0x00000000,d0
bne change_flashbar
add.l #0x61,d0
movec d0,RAMBAR0
_continue_startup:
/* Locate Stack Pointer */
move.l #__SP_INIT,sp
/* Initialize the system */
jsr mcf5225x_init
/* Common startup code */
//jsr common_startup
/* Save off intial D0 and D1 to RAM */
move.l d6,d0_reset
move.l d7,d1_reset
/* CPU specific startup code */
//jsr cpu_startup
/* Jump to the main process */
jsr main
bra .
nop
nop
halt
change_flashbar:
/*
* The following sequence is used to set FLASHBAR. Since we may
* be executing from Flash, we must put the routine into SRAM for
* execution and then jump back to Flash using the new address.
*
* The following instructions are coded into the SRAM:
*
* move.l #(__FLASH + 0x21),d0
* movec d0, RAMBAR0
* jmp _continue_startup
*
* An arbitrary SRAM address is chosen until the real address
* can be loaded.
*
* This routine is not necessary if the default Flash address
* (0x00000000) is used.
*
* If running in SRAM, change_flashbar should not be executed
*/
move.l #__SRAM,a0
/* Code "move.l #(__FLASH + 0x21),d0" into SRAM */
move.w #0x203C,d0
move.w d0,(a0)+
move.l #__FLASH,d0
add.l #0x21,d0
move.l d0,(a0)+
/* Code "movec d0,FLASHBAR" into SRAM */
move.l #0x4e7b0C04,d0
move.l d0,(a0)+
/* Code "jmp _continue_startup" into SRAM */
move.w #0x4EF9,d0
move.w d0,(a0)+
move.l #_continue_startup,d0
move.l d0,(a0)+
/* Jump to code segment in internal SRAM */
jmp __SRAM
/********************************************************************/
.end

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Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_sysinit.c Normal file
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/*
* File: sysinit.c
* Purpose: Reset configuration of the M52259EVB
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#include "common.h"
/********************************************************************/
void mcf5225x_init(void);
void mcf5225x_wtm_init(void);
void mcf5225x_pll_init(void);
void mcf5225x_uart_init(void);
void mcf5225x_scm_init(void);
void mcf5225x_gpio_init(void);
/********************************************************************/
void
mcf5225x_init(void)
{
register uint32 n;
register uint8 *dp, *sp;
/*
* Allow interrupts from ABORT, SW1, SW2 (IRQ[1,5,7])
* and USB (IRQ[2,6])
*/
/* Enable IRQ signals on the port */
MCF_GPIO_PNQPAR = 0
| MCF_GPIO_PNQPAR_IRQ1_IRQ1
| MCF_GPIO_PNQPAR_IRQ5_IRQ5
| MCF_GPIO_PNQPAR_IRQ7_IRQ7;
/* Set EPORT to look for falling edges */
MCF_EPORT_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA1_FALLING
| MCF_EPORT_EPPAR_EPPA2_FALLING
| MCF_EPORT_EPPAR_EPPA5_FALLING
| MCF_EPORT_EPPAR_EPPA6_FALLING
| MCF_EPORT_EPPAR_EPPA7_FALLING;
/* Clear any currently triggered events on the EPORT */
MCF_EPORT_EPIER = 0
| MCF_EPORT_EPIER_EPIE1
| MCF_EPORT_EPIER_EPIE2
| MCF_EPORT_EPIER_EPIE5
| MCF_EPORT_EPIER_EPIE6
| MCF_EPORT_EPIER_EPIE7;
/* Enable interrupts in the interrupt controller */
MCF_INTC0_IMRL &= ~(0
| MCF_INTC_IMRL_INT_MASK1
| MCF_INTC_IMRL_INT_MASK2
| MCF_INTC_IMRL_INT_MASK5
| MCF_INTC_IMRL_INT_MASK6
| MCF_INTC_IMRL_INT_MASK7
| MCF_INTC_IMRL_MASKALL);
/* Enable debug */
MCF_GPIO_PDDPAR = 0x0F;
/* Set real time clock freq */
MCF_CLOCK_RTCCR = 48000000;
/* Copy the vector table to RAM */
if (__VECTOR_RAM != VECTOR_TABLE)
{
for (n = 0; n < 256; n++)
__VECTOR_RAM[n] = VECTOR_TABLE[n];
mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);
}
/*
* Move initialized data from ROM to RAM.
*/
if (__DATA_ROM != __DATA_RAM)
{
dp = (uint8 *)__DATA_RAM;
sp = (uint8 *)__DATA_ROM;
n = (uint32)(__DATA_END - __DATA_RAM);
while (n--)
*dp++ = *sp++;
}
/*
* Zero uninitialized data
*/
if (__BSS_START != __BSS_END)
{
sp = (uint8 *)__BSS_START;
n = (uint32)(__BSS_END - __BSS_START);
while (n--)
*sp++ = 0;
}
mcf5225x_wtm_init();
mcf5225x_pll_init();
mcf5225x_scm_init();
mcf5225x_uart_init();
}
/********************************************************************/
void
mcf5225x_wtm_init(void)
{
/*
* Disable Software Watchdog Timer
*/
MCF_SCM_CWCR = 0;
}
/********************************************************************/
void
mcf5225x_pll_init(void)
{
/*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */
#ifndef OMIT_OCLR_CONFIGURATION
MCF_CLOCK_OCLR = 0xC0; //turn on crystal
MCF_CLOCK_CCLR = 0x00; //switch to crystal
MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc
#endif
/* The PLL pre divider - 48MHz / 6 = 8MHz */
MCF_CLOCK_CCHR =0x05;
/* The PLL pre-divider affects this!!!
* Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
*/
MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);
MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;
//80
MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);
//64
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);
//16
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);
//8
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);
//1
//MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);
MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
{
}
}
/********************************************************************/
void
mcf5225x_scm_init(void)
{
/*
* Enable on-chip modules to access internal SRAM
*/
MCF_SCM_RAMBAR = (0
| MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)
| MCF_SCM_RAMBAR_BDE);
}
/********************************************************************/
void
mcf5225x_gpio_init(void)
{
/*
* Initialize Port TA to enable Axcel control
*/
MCF_GPIO_PTAPAR = 0x00;
MCF_GPIO_DDRTA = 0x0F;
MCF_GPIO_PORTTA = 0x04;
}
/********************************************************************/
void
mcf5225x_uart_init(void)
{
/*
* Initialize all three UARTs for serial communications
*/
register uint16 ubgs;
/*
* Set Port UA to initialize URXD0/UTXD0
*/
MCF_GPIO_PUAPAR = 0
| MCF_GPIO_PUAPAR_URXD0_URXD0
| MCF_GPIO_PUAPAR_UTXD0_UTXD0;
MCF_GPIO_PUBPAR = 0
| MCF_GPIO_PUBPAR_URXD1_URXD1
| MCF_GPIO_PUBPAR_UTXD1_UTXD1;
MCF_GPIO_PUCPAR = 0
| MCF_GPIO_PUCPAR_URXD2_URXD2
| MCF_GPIO_PUCPAR_UTXD2_UTXD2;
/*
* Reset Transmitter
*/
MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;
MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;
/*
* Reset Receiver
*/
MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;
MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;
/*
* Reset Mode Register
*/
MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;
MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;
MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;
/*
* No parity, 8-bits per character
*/
MCF_UART0_UMR1 = (0
| MCF_UART_UMR_PM_NONE
| MCF_UART_UMR_BC_8 );
MCF_UART1_UMR1 = (0
| MCF_UART_UMR_PM_NONE
| MCF_UART_UMR_BC_8 );
MCF_UART2_UMR1 = (0
| MCF_UART_UMR_PM_NONE
| MCF_UART_UMR_BC_8 );
/*
* No echo or loopback, 1 stop bit
*/
MCF_UART0_UMR2 = (0
| MCF_UART_UMR_CM_NORMAL
| MCF_UART_UMR_SB_STOP_BITS_1);
MCF_UART1_UMR2 = (0
| MCF_UART_UMR_CM_NORMAL
| MCF_UART_UMR_SB_STOP_BITS_1);
MCF_UART2_UMR2 = (0
| MCF_UART_UMR_CM_NORMAL
| MCF_UART_UMR_SB_STOP_BITS_1);
/*
* Set Rx and Tx baud by SYSTEM CLOCK
*/
MCF_UART0_UCSR = (0
| MCF_UART_UCSR_RCS_SYS_CLK
| MCF_UART_UCSR_TCS_SYS_CLK);
MCF_UART1_UCSR = (0
| MCF_UART_UCSR_RCS_SYS_CLK
| MCF_UART_UCSR_TCS_SYS_CLK);
MCF_UART2_UCSR = (0
| MCF_UART_UCSR_RCS_SYS_CLK
| MCF_UART_UCSR_TCS_SYS_CLK);
/*
* Mask all UART interrupts
*/
MCF_UART0_UIMR = 0;
MCF_UART1_UIMR = 0;
MCF_UART2_UIMR = 0;
/*
* Calculate baud settings
*/
ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));
MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);
/*
* Enable receiver and transmitter
*/
MCF_UART0_UCR = (0
| MCF_UART_UCR_TX_ENABLED
| MCF_UART_UCR_RX_ENABLED);
MCF_UART1_UCR = (0
| MCF_UART_UCR_TX_ENABLED
| MCF_UART_UCR_RX_ENABLED);
MCF_UART2_UCR = (0
| MCF_UART_UCR_TX_ENABLED
| MCF_UART_UCR_RX_ENABLED);
}
/********************************************************************/

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Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x_vectors.s Normal file
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/*
* File: vectors.s
* Purpose: MCF5225x vector table
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#ifdef __GNUC__ /* { */
#define sr %sr
#define _asm_exception_handler irq_handler
#define _timer_handler timer_handler
#endif /* } __GNUC__ */
.global VECTOR_TABLE
.global _VECTOR_TABLE
.global start
.extern ___SP_INIT
.extern _asm_startmeup
.extern _asm_exception_handler
.extern _vPIT0InterruptHandler
.extern vPortYieldISR
.extern _vFECISRHandler
.text
/*
* Exception Vector Table
*/
VECTOR_TABLE:
_VECTOR_TABLE:
INITSP: .long ___SP_INIT /* Initial SP */
INITPC: .long _asm_startmeup /* Initial PC */
vector02: .long _asm_exception_handler /* Access Error */
vector03: .long _asm_exception_handler /* Address Error */
vector04: .long _asm_exception_handler /* Illegal Instruction */
vector05: .long _asm_exception_handler /* Reserved */
vector06: .long _asm_exception_handler /* Reserved */
vector07: .long _asm_exception_handler /* Reserved */
vector08: .long _asm_exception_handler /* Privilege Violation */
vector09: .long _asm_exception_handler /* Trace */
vector0A: .long _asm_exception_handler /* Unimplemented A-Line */
vector0B: .long _asm_exception_handler /* Unimplemented F-Line */
vector0C: .long _asm_exception_handler /* Debug Interrupt */
vector0D: .long _asm_exception_handler /* Reserved */
vector0E: .long _asm_exception_handler /* Format Error */
vector0F: .long _asm_exception_handler /* Unitialized Int. */
vector10: .long _asm_exception_handler /* Reserved */
vector11: .long _asm_exception_handler /* Reserved */
vector12: .long _asm_exception_handler /* Reserved */
vector13: .long _asm_exception_handler /* Reserved */
vector14: .long _asm_exception_handler /* Reserved */
vector15: .long _asm_exception_handler /* Reserved */
vector16: .long _asm_exception_handler /* Reserved */
vector17: .long _asm_exception_handler /* Reserved */
vector18: .long _asm_exception_handler /* Spurious Interrupt */
vector19: .long _asm_exception_handler /* Autovector Level 1 */
vector1A: .long _asm_exception_handler /* Autovector Level 2 */
vector1B: .long _asm_exception_handler /* Autovector Level 3 */
vector1C: .long _asm_exception_handler /* Autovector Level 4 */
vector1D: .long _asm_exception_handler /* Autovector Level 5 */
vector1E: .long _asm_exception_handler /* Autovector Level 6 */
vector1F: .long _asm_exception_handler /* Autovector Level 7 */
vector20: .long _asm_exception_handler /* TRAP #0 */
vector21: .long _asm_exception_handler /* TRAP #1 */
vector22: .long _asm_exception_handler /* TRAP #2 */
vector23: .long _asm_exception_handler /* TRAP #3 */
vector24: .long _asm_exception_handler /* TRAP #4 */
vector25: .long _asm_exception_handler /* TRAP #5 */
vector26: .long _asm_exception_handler /* TRAP #6 */
vector27: .long _asm_exception_handler /* TRAP #7 */
vector28: .long _asm_exception_handler /* TRAP #8 */
vector29: .long _asm_exception_handler /* TRAP #9 */
vector2A: .long _asm_exception_handler /* TRAP #10 */
vector2B: .long _asm_exception_handler /* TRAP #11 */
vector2C: .long _asm_exception_handler /* TRAP #12 */
vector2D: .long _asm_exception_handler /* TRAP #13 */
vector2E: .long _asm_exception_handler /* TRAP #14 */
vector2F: .long _asm_exception_handler /* TRAP #15 */
vector30: .long _asm_exception_handler /* Reserved */
vector31: .long _asm_exception_handler /* Reserved */
vector32: .long _asm_exception_handler /* Reserved */
vector33: .long _asm_exception_handler /* Reserved */
vector34: .long _asm_exception_handler /* Reserved */
vector35: .long _asm_exception_handler /* Reserved */
vector36: .long _asm_exception_handler /* Reserved */
vector37: .long _asm_exception_handler /* Reserved */
vector38: .long _asm_exception_handler /* Reserved */
vector39: .long _asm_exception_handler /* Reserved */
vector3A: .long _asm_exception_handler /* Reserved */
vector3B: .long _asm_exception_handler /* Reserved */
vector3C: .long _asm_exception_handler /* Reserved */
vector3D: .long _asm_exception_handler /* Reserved */
vector3E: .long _asm_exception_handler /* Reserved */
vector3F: .long _asm_exception_handler /* Reserved */
vector40: .long _asm_exception_handler
vector41: .long _asm_exception_handler
vector42: .long _asm_exception_handler
vector43: .long _asm_exception_handler
vector44: .long _asm_exception_handler
vector45: .long _asm_exception_handler
vector46: .long _asm_exception_handler
vector47: .long _asm_exception_handler
vector48: .long _asm_exception_handler
vector49: .long _asm_exception_handler
vector4A: .long _asm_exception_handler
vector4B: .long _asm_exception_handler
vector4C: .long _asm_exception_handler
vector4D: .long _asm_exception_handler
vector4E: .long _asm_exception_handler
vector4F: .long _asm_exception_handler
vector50: .long vPortYieldISR
vector51: .long _asm_exception_handler
vector52: .long _asm_exception_handler
vector53: .long _asm_exception_handler
vector54: .long _asm_exception_handler
vector55: .long _asm_exception_handler
vector56: .long _asm_exception_handler
vector57: .long _asm_exception_handler
vector58: .long _asm_exception_handler
vector59: .long _vFECISRHandler
vector5A: .long _vFECISRHandler
vector5B: .long _vFECISRHandler
vector5C: .long _vFECISRHandler
vector5D: .long _vFECISRHandler
vector5E: .long _vFECISRHandler
vector5F: .long _vFECISRHandler
vector60: .long _asm_exception_handler
vector61: .long _vFECISRHandler
vector62: .long _vFECISRHandler
vector63: .long _vFECISRHandler
vector64: .long _asm_exception_handler
vector65: .long _asm_exception_handler
vector66: .long _asm_exception_handler
vector67: .long _asm_exception_handler
vector68: .long _asm_exception_handler
vector69: .long _asm_exception_handler
vector6A: .long _asm_exception_handler
vector6B: .long _asm_exception_handler
vector6C: .long _asm_exception_handler
vector6D: .long _asm_exception_handler
vector6E: .long _asm_exception_handler
vector6F: .long _asm_exception_handler
vector70: .long _asm_exception_handler
vector71: .long _asm_exception_handler
vector72: .long _asm_exception_handler
vector73: .long _asm_exception_handler
vector74: .long _asm_exception_handler
vector75: .long _asm_exception_handler
vector76: .long _asm_exception_handler
vector77: .long _vPIT0InterruptHandler
vector78: .long _asm_exception_handler
vector79: .long _asm_exception_handler
vector7A: .long _asm_exception_handler
vector7B: .long _asm_exception_handler
vector7C: .long _asm_exception_handler
vector7D: .long _asm_exception_handler
vector7E: .long _asm_exception_handler
vector7F: .long _asm_exception_handler
vector80: .long _asm_exception_handler
vector81: .long _asm_exception_handler
vector82: .long _asm_exception_handler
vector83: .long _asm_exception_handler
vector84: .long _asm_exception_handler
vector85: .long _asm_exception_handler
vector86: .long _asm_exception_handler
vector87: .long _asm_exception_handler
vector88: .long _asm_exception_handler
vector89: .long _asm_exception_handler
vector8A: .long _asm_exception_handler
vector8B: .long _asm_exception_handler
vector8C: .long _asm_exception_handler
vector8D: .long _asm_exception_handler
vector8E: .long _asm_exception_handler
vector8F: .long _asm_exception_handler
vector90: .long _asm_exception_handler
vector91: .long _asm_exception_handler
vector92: .long _asm_exception_handler
vector93: .long _asm_exception_handler
vector94: .long _asm_exception_handler
vector95: .long _asm_exception_handler
vector96: .long _asm_exception_handler
vector97: .long _asm_exception_handler
vector98: .long _asm_exception_handler
vector99: .long _asm_exception_handler
vector9A: .long _asm_exception_handler
vector9B: .long _asm_exception_handler
vector9C: .long _asm_exception_handler
vector9D: .long _asm_exception_handler
vector9E: .long _asm_exception_handler
vector9F: .long _asm_exception_handler
vectorA0: .long _asm_exception_handler
vectorA1: .long _asm_exception_handler
vectorA2: .long _asm_exception_handler
vectorA3: .long _asm_exception_handler
vectorA4: .long _asm_exception_handler
vectorA5: .long _asm_exception_handler
vectorA6: .long _asm_exception_handler
vectorA7: .long _asm_exception_handler
vectorA8: .long _asm_exception_handler
vectorA9: .long _asm_exception_handler
vectorAA: .long _asm_exception_handler
vectorAB: .long _asm_exception_handler
vectorAC: .long _asm_exception_handler
vectorAD: .long _asm_exception_handler
vectorAE: .long _asm_exception_handler
vectorAF: .long _asm_exception_handler
vectorB0: .long _asm_exception_handler
vectorB1: .long _asm_exception_handler
vectorB2: .long _asm_exception_handler
vectorB3: .long _asm_exception_handler
vectorB4: .long _asm_exception_handler
vectorB5: .long _asm_exception_handler
vectorB6: .long _asm_exception_handler
vectorB7: .long _asm_exception_handler
vectorB8: .long _asm_exception_handler
vectorB9: .long _asm_exception_handler
vectorBA: .long _asm_exception_handler
vectorBB: .long _asm_exception_handler
vectorBC: .long _asm_exception_handler
vectorBD: .long _asm_exception_handler
vectorBE: .long _asm_exception_handler
vectorBF: .long _asm_exception_handler
.org 0x400
/*
* CFM Flash Configuration Field
*/
KEY_UPPER: .long 0x00000000
KEY_LOWER: .long 0x00000000
CFMPROT: .long 0x00000000
CFMSACC: .long 0x00000000
CFMDACC: .long 0x00000000
CFMSEC: .long 0x00000000
/********************************************************************/
.end

516
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/*
* File: mcf5xxx.c
* Purpose: Generic high-level routines for generic ColdFire processors
*
* Notes:
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#include "common.h"
/********************************************************************/
#define EXCEPTFMT "%s -- PC = %#08X\n"
/********************************************************************/
/*
* This is the exception handler for all defined exceptions. Most
* exceptions do nothing, but some of the more important ones are
* handled to some extent.
*
* Called by asm_exception_handler
*/
void
mcf5xxx_exception_handler (void *framep)
{
switch (MCF5XXX_RD_SF_FORMAT(framep))
{
case 4:
case 5:
case 6:
case 7:
break;
default:
printf(EXCEPTFMT,"Illegal stack type", MCF5XXX_SF_PC(framep));
break;
}
switch (MCF5XXX_RD_SF_VECTOR(framep))
{
case 2:
printf(EXCEPTFMT, "Access Error", MCF5XXX_SF_PC(framep));
switch (MCF5XXX_RD_SF_FS(framep))
{
case 4:
printf("Error on instruction fetch\n");
break;
case 8:
printf("Error on operand write\n");
break;
case 9:
printf("Attempted write to write-protected space\n");
break;
case 12:
printf("Error on operand read\n");
break;
default:
printf("Reserved Fault Status Encoding\n");
break;
}
break;
case 3:
printf(EXCEPTFMT, "Address Error", MCF5XXX_SF_PC(framep));
switch (MCF5XXX_RD_SF_FS(framep))
{
case 4:
printf("Error on instruction fetch\n");
break;
case 8:
printf("Error on operand write\n");
break;
case 9:
printf("Attempted write to write-protected space\n");
break;
case 12:
printf("Error on operand read\n");
break;
default:
printf("Reserved Fault Status Encoding\n");
break;
}
break;
case 4:
printf(EXCEPTFMT, "Illegal instruction", MCF5XXX_SF_PC(framep));
break;
case 8:
printf(EXCEPTFMT, "Privilege violation", MCF5XXX_SF_PC(framep));
break;
case 9:
printf(EXCEPTFMT, "Trace Exception", MCF5XXX_SF_PC(framep));
break;
case 10:
printf(EXCEPTFMT, "Unimplemented A-Line Instruction", \
MCF5XXX_SF_PC(framep));
break;
case 11:
printf(EXCEPTFMT, "Unimplemented F-Line Instruction", \
MCF5XXX_SF_PC(framep));
break;
case 12:
printf(EXCEPTFMT, "Debug Interrupt", MCF5XXX_SF_PC(framep));
break;
case 14:
printf(EXCEPTFMT, "Format Error", MCF5XXX_SF_PC(framep));
break;
case 15:
printf(EXCEPTFMT, "Unitialized Interrupt", MCF5XXX_SF_PC(framep));
break;
case 24:
printf(EXCEPTFMT, "Spurious Interrupt", MCF5XXX_SF_PC(framep));
break;
case 25:
case 26:
case 27:
case 28:
case 29:
case 30:
case 31:
printf("Autovector interrupt level %d\n",
MCF5XXX_RD_SF_VECTOR(framep) - 24);
break;
case 32:
case 33:
case 34:
case 35:
case 36:
case 37:
case 38:
case 39:
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
printf("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);
break;
case 5:
case 6:
case 7:
case 13:
case 16:
case 17:
case 18:
case 19:
case 20:
case 21:
case 22:
case 23:
case 48:
case 49:
case 50:
case 51:
case 52:
case 53:
case 54:
case 55:
case 56:
case 57:
case 58:
case 59:
case 60:
case 61:
case 62:
case 63:
printf("Reserved: #%d\n", MCF5XXX_RD_SF_VECTOR(framep));
break;
default:
cpu_handle_interrupt(MCF5XXX_RD_SF_VECTOR(framep));
break;
}
}
/********************************************************************/
/*
* Interpret the reset values of D0 and D1
*
* Parameters:
* d0 - the reset value of data register zero
* d1 - the reset value of data register one
*/
void
mcf5xxx_interpret_d0d1(int d0, int d1)
{
#ifdef DEBUG_PRINT
printf("\nColdFire Core Configuration:\n");
printf("----------------------------\n");
printf("Processor Family %#02x\n",MCF5XXX_D0_PF(d0));
printf("ColdFire Core Version: %d\n",MCF5XXX_D0_VER(d0));
printf("Processor Revision: %d\n",MCF5XXX_D0_REV(d1));
printf("Bus Width: ");
switch (MCF5XXX_D1_BUSW(d1))
{
case 0:
printf("32-bit\n");
break;
default:
printf("Reserved\n");
}
printf("ISA Version: ");
switch (MCF5XXX_D0_ISA(d0))
{
case 0:
printf("A\n");
break;
case 1:
printf("B\n");
break;
case 2:
printf("C\n");
break;
case 8:
printf("A+\n");
break;
default:
printf("Reserved\n");
}
printf("Debug Version: ");
switch (MCF5XXX_D0_DEBUG(d0))
{
case 0:
printf("A\n");
break;
case 1:
printf("B\n");
break;
case 2:
printf("C\n");
break;
case 3:
printf("D\n");
break;
case 4:
printf("E\n");
break;
case 9:
printf("B+\n");
break;
default :
printf("Reserved\n");
}
printf("MAC: %s\n", MCF5XXX_D0_MAC(d0) ? "Yes" : "No");
printf("DIV: %s\n", MCF5XXX_D0_DIV(d0) ? "Yes" : "No");
printf("EMAC: %s\n", MCF5XXX_D0_EMAC(d0) ? "Yes" : "No");
printf("FPU: %s\n", MCF5XXX_D0_FPU(d0) ? "Yes" : "No");
printf("MMU: %s\n", MCF5XXX_D0_MMU(d0) ? "Yes" : "No");
printf("RAM Bank 0 Size: ");
switch (MCF5XXX_D1_RAM0SIZ(d1))
{
case 0:
case 1:
case 2:
case 3:
printf("None\n");
break;
case 4:
printf("4KB\n");
break;
case 5:
printf("8KB\n");
break;
case 6:
printf("16KB\n");
break;
case 7:
printf("32KB\n");
break;
case 8:
printf("64KB\n");
break;
case 9:
printf("128KB\n");
break;
case 10:
printf("256KB\n");
break;
case 11:
printf("512KB\n");
break;
default:
printf("Reserved\n");
}
printf("RAM Bank 1 Size: ");
switch (MCF5XXX_D1_RAM1SIZ(d1))
{
case 0:
case 1:
case 2:
case 3:
printf("None\n");
break;
case 4:
printf("4KB\n");
break;
case 5:
printf("8KB\n");
break;
case 6:
printf("16KB\n");
break;
case 7:
printf("32KB\n");
break;
case 8:
printf("64KB\n");
break;
case 9:
printf("128KB\n");
break;
case 10:
printf("256KB\n");
break;
case 11:
printf("512KB\n");
break;
default:
printf("Reserved\n");
}
printf("ROM Bank 0 Size: ");
switch (MCF5XXX_D1_ROM0SIZ(d1))
{
case 0:
case 1:
case 2:
case 3:
printf("None\n");
break;
case 4:
printf("4KB\n");
break;
case 5:
printf("8KB\n");
break;
case 6:
printf("16KB\n");
break;
case 7:
printf("32KB\n");
break;
case 8:
printf("64KB\n");
break;
case 9:
printf("128KB\n");
default:
printf("Reserved\n");
}
printf("ROM Bank 1 Size: ");
switch (MCF5XXX_D1_ROM1SIZ(d1))
{
case 0:
case 1:
case 2:
case 3:
printf("None\n");
break;
case 4:
printf("4KB\n");
break;
case 5:
printf("8KB\n");
break;
case 6:
printf("16KB\n");
break;
case 7:
printf("32KB\n");
break;
case 8:
printf("64KB\n");
break;
case 9:
printf("128KB\n");
default:
printf("Reserved\n");
}
printf("Cache Line Size: ");
switch (MCF5XXX_D1_CL(d1))
{
case 0:
printf("16-byte\n");
break;
default:
printf("Reserved\n");
}
printf("I-Cache Associativity: ");
switch (MCF5XXX_D1_ICA(d1))
{
case 0:
printf("Four-way\n");
break;
case 1:
printf("Direct mapped\n");
break;
default:
printf("Reserved\n");
}
printf("D-Cache Associativity: ");
switch (MCF5XXX_D1_DCA(d1))
{
case 0:
printf("Four-way\n");
break;
case 1:
printf("Direct mapped\n");
break;
default:
printf("Reserved\n");
}
printf("I-Cache Size: ");
switch (MCF5XXX_D1_ICSIZ(d1))
{
case 0:
printf("None\n");
break;
case 1:
printf("512B\n");
break;
case 2:
printf("1KB\n");
break;
case 3:
printf("2KB\n");
break;
case 4:
printf("4KB\n");
break;
case 5:
printf("8KB\n");
break;
case 6:
printf("16KB\n");
break;
case 7:
printf("32KB\n");
break;
case 8:
printf("64KB\n");
break;
default:
printf("Reserved\n");
}
printf("D-Cache Size: ");
switch (MCF5XXX_D1_DCSIZ(d1))
{
case 0:
printf("None\n");
break;
case 1:
printf("512B\n");
break;
case 2:
printf("1KB\n");
break;
case 3:
printf("2KB\n");
break;
case 4:
printf("4KB\n");
break;
case 5:
printf("8KB\n");
break;
case 6:
printf("16KB\n");
break;
case 7:
printf("32KB\n");
break;
case 8:
printf("64KB\n");
break;
default:
printf("Reserved\n");
}
printf("\n");
#else
/* Remove compiler warnings. */
( void ) d0;
( void ) d1;
#endif
}
/********************************************************************/
void
mcf5xxx_irq_enable (void)
{
asm_set_ipl(0);
}
/********************************************************************/
void
mcf5xxx_irq_disable (void)
{
asm_set_ipl(7);
}
/********************************************************************/
/*
* Write new interrupt vector handler into the vector table
* Return previous handler address
*/
ADDRESS
mcf5xxx_set_handler (int vector, ADDRESS new_handler)
{
ADDRESS old_handler;
extern uint32 __VECTOR_RAM[];
old_handler = (ADDRESS) __VECTOR_RAM[vector];
__VECTOR_RAM[vector] = (uint32)new_handler;
return old_handler;
}
/********************************************************************/

283
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/*
* File: mcf5xxx.h
* Purpose: Definitions common to all ColdFire processors
*
* Notes:
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#ifndef _CPU_MCF5XXX_H
#define _CPU_MCF5XXX_H
/***********************************************************************/
/*
* Misc. Defines
*/
#ifdef FALSE
#undef FALSE
#endif
#define FALSE (0)
#ifdef TRUE
#undef TRUE
#endif
#define TRUE (1)
#ifdef NULL
#undef NULL
#endif
#define NULL (0)
#ifdef ON
#undef ON
#endif
#define ON (1)
#ifdef OFF
#undef OFF
#endif
#define OFF (0)
/***********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef char int8; /* 8 bits */
typedef short int int16; /* 16 bits */
typedef int int32; /* 32 bits */
typedef volatile int8 vint8; /* 8 bits */
typedef volatile int16 vint16; /* 16 bits */
typedef volatile int32 vint32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
/***********************************************************************/
/*
* Common M68K & ColdFire definitions
*/
#define ADDRESS uint32
#define INSTRUCTION uint16
#define ILLEGAL 0x4AFC
#define CPU_WORD_SIZE 16
/* Status Register */
#define MCF5XXX_SR_T (0x8000)
#define MCF5XXX_SR_S (0x2000)
#define MCF5XXX_SR_M (0x1000)
#define MCF5XXX_SR_IPL (0x0700)
#define MCF5XXX_SR_IPL_0 (0x0000)
#define MCF5XXX_SR_IPL_1 (0x0100)
#define MCF5XXX_SR_IPL_2 (0x0200)
#define MCF5XXX_SR_IPL_3 (0x0300)
#define MCF5XXX_SR_IPL_4 (0x0400)
#define MCF5XXX_SR_IPL_5 (0x0500)
#define MCF5XXX_SR_IPL_6 (0x0600)
#define MCF5XXX_SR_IPL_7 (0x0700)
#define MCF5XXX_SR_X (0x0010)
#define MCF5XXX_SR_N (0x0008)
#define MCF5XXX_SR_Z (0x0004)
#define MCF5XXX_SR_V (0x0002)
#define MCF5XXX_SR_C (0x0001)
/* Cache Control Register */
#define MCF5XXX_CACR_CENB (0x80000000)
#define MCF5XXX_CACR_DEC (0x80000000)
#define MCF5XXX_CACR_DW (0x40000000)
#define MCF5XXX_CACR_DESB (0x20000000)
#define MCF5XXX_CACR_CPDI (0x10000000)
#define MCF5XXX_CACR_DDPI (0x10000000)
#define MCF5XXX_CACR_CPD (0x10000000)
#define MCF5XXX_CACR_CFRZ (0x08000000)
#define MCF5XXX_CACR_DHLCK (0x08000000)
#define MCF5XXX_CACR_DDCM_WT (0x00000000)
#define MCF5XXX_CACR_DDCM_CB (0x02000000)
#define MCF5XXX_CACR_DDCM_IP (0x04000000)
#define MCF5XXX_CACR_DDCM_II (0x06000000)
#define MCF5XXX_CACR_CINV (0x01000000)
#define MCF5XXX_CACR_DCINVA (0x01000000)
#define MCF5XXX_CACR_DIDI (0x00800000)
#define MCF5XXX_CACR_DDSP (0x00800000)
#define MCF5XXX_CACR_DISD (0x00400000)
#define MCF5XXX_CACR_INVI (0x00200000)
#define MCF5XXX_CACR_INVD (0x00100000)
#define MCF5XXX_CACR_BEC (0x00080000)
#define MCF5XXX_CACR_BCINVA (0x00040000)
#define MCF5XXX_CACR_IEC (0x00008000)
#define MCF5XXX_CACR_DNFB (0x00002000)
#define MCF5XXX_CACR_IDPI (0x00001000)
#define MCF5XXX_CACR_IHLCK (0x00000800)
#define MCF5XXX_CACR_CEIB (0x00000400)
#define MCF5XXX_CACR_IDCM (0x00000400)
#define MCF5XXX_CACR_DCM_WR (0x00000000)
#define MCF5XXX_CACR_DCM_CB (0x00000100)
#define MCF5XXX_CACR_DCM_IP (0x00000200)
#define MCF5XXX_CACR_DCM (0x00000200)
#define MCF5XXX_CACR_DCM_II (0x00000300)
#define MCF5XXX_CACR_DBWE (0x00000100)
#define MCF5XXX_CACR_ICINVA (0x00000100)
#define MCF5XXX_CACR_IDSP (0x00000080)
#define MCF5XXX_CACR_DWP (0x00000020)
#define MCF5XXX_CACR_EUSP (0x00000020)
#define MCF5XXX_CACR_EUST (0x00000020)
#define MCF5XXX_CACR_DF (0x00000010)
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
/* Access Control Register */
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
#define MCF5XXX_ACR_AM_4G (0x00FF0000)
#define MCF5XXX_ACR_AM_2G (0x007F0000)
#define MCF5XXX_ACR_AM_1G (0x003F0000)
#define MCF5XXX_ACR_AM_1024M (0x003F0000)
#define MCF5XXX_ACR_AM_512M (0x001F0000)
#define MCF5XXX_ACR_AM_256M (0x000F0000)
#define MCF5XXX_ACR_AM_128M (0x00070000)
#define MCF5XXX_ACR_AM_64M (0x00030000)
#define MCF5XXX_ACR_AM_32M (0x00010000)
#define MCF5XXX_ACR_AM_16M (0x00000000)
#define MCF5XXX_ACR_EN (0x00008000)
#define MCF5XXX_ACR_SM_USER (0x00000000)
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
#define MCF5XXX_ACR_ENIB (0x00000080)
#define MCF5XXX_ACR_CM (0x00000040)
#define MCF5XXX_ACR_DCM_WR (0x00000000)
#define MCF5XXX_ACR_DCM_CB (0x00000020)
#define MCF5XXX_ACR_DCM_IP (0x00000040)
#define MCF5XXX_ACR_DCM_II (0x00000060)
#define MCF5XXX_ACR_CM (0x00000040)
#define MCF5XXX_ACR_BWE (0x00000020)
#define MCF5XXX_ACR_WP (0x00000004)
/* RAM Base Address Register */
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
#define MCF5XXX_RAMBAR_WP (0x00000100)
#define MCF5XXX_RAMBAR_CI (0x00000020)
#define MCF5XXX_RAMBAR_SC (0x00000010)
#define MCF5XXX_RAMBAR_SD (0x00000008)
#define MCF5XXX_RAMBAR_UC (0x00000004)
#define MCF5XXX_RAMBAR_UD (0x00000002)
#define MCF5XXX_RAMBAR_V (0x00000001)
/* Read macros for D0/D1 reset values */
#define MCF5XXX_D0_PF(x) (((x)&0xFF000000)>>24)
#define MCF5XXX_D0_VER(x) (((x)&0x00F00000)>>20)
#define MCF5XXX_D0_REV(x) (((x)&0x000F0000)>>16)
#define MCF5XXX_D0_MAC(x) ((x)&0x00008000)
#define MCF5XXX_D0_DIV(x) ((x)&0x00004000)
#define MCF5XXX_D0_EMAC(x) ((x)&0x00002000)
#define MCF5XXX_D0_FPU(x) ((x)&0x00001000)
#define MCF5XXX_D0_MMU(x) ((x)&0x00000800)
#define MCF5XXX_D0_ISA(x) (((x)&0x000000F0)>>4)
#define MCF5XXX_D0_DEBUG(x) (((x)&0x0000000F)>>0)
#define MCF5XXX_D1_CL(x) (((x)&0xC0000000)>>30)
#define MCF5XXX_D1_ICA(x) (((x)&0x30000000)>>28)
#define MCF5XXX_D1_ICSIZ(x) (((x)&0x0F000000)>>24)
#define MCF5XXX_D1_RAM0SIZ(x) (((x)&0x00F00000)>>20)
#define MCF5XXX_D1_ROM0SIZ(x) (((x)&0x000F0000)>>16)
#define MCF5XXX_D1_BUSW(x) (((x)&0x0000C000)>>14)
#define MCF5XXX_D1_DCA(x) (((x)&0x00003000)>>12)
#define MCF5XXX_D1_DCSIZ(x) (((x)&0x00000F00)>>8)
#define MCF5XXX_D1_RAM1SIZ(x) (((x)&0x000000F0)>>4)
#define MCF5XXX_D1_ROM1SIZ(x) (((x)&0x0000000F)>>0)
/***********************************************************************/
/*
* The ColdFire family of processors has a simplified exception stack
* frame that looks like the following:
*
* 3322222222221111 111111
* 1098765432109876 5432109876543210
* 8 +----------------+----------------+
* | Program Counter |
* 4 +----------------+----------------+
* |FS/Fmt/Vector/FS| SR |
* SP --> 0 +----------------+----------------+
*
* The stack self-aligns to a 4-byte boundary at an exception, with
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
* (SP += 0,1,2,3 bytes).
*/
#define MCF5XXX_RD_SF_FORMAT(PTR) \
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
#define MCF5XXX_RD_SF_VECTOR(PTR) \
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
#define MCF5XXX_RD_SF_FS(PTR) \
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
/********************************************************************/
/*
* Functions provided in mcf5xxx.s
*/
int asm_set_ipl (uint32);
void mcf5xxx_exe_wdebug (void *);
void mcf5xxx_wr_sr (uint32);
void mcf5xxx_wr_cacr (uint32);
void mcf5xxx_wr_asid (uint32);
void mcf5xxx_wr_acr0 (uint32);
void mcf5xxx_wr_acr1 (uint32);
void mcf5xxx_wr_acr2 (uint32);
void mcf5xxx_wr_acr3 (uint32);
void mcf5xxx_wr_mmubar (uint32);
void mcf5xxx_wr_other_a7 (uint32);
void mcf5xxx_wr_other_sp (uint32);
void mcf5xxx_wr_vbr (uint32);
void mcf5xxx_wr_macsr (uint32);
void mcf5xxx_wr_mask (uint32);
void mcf5xxx_wr_acc0 (uint32);
void mcf5xxx_wr_accext01 (uint32);
void mcf5xxx_wr_accext23 (uint32);
void mcf5xxx_wr_acc1 (uint32);
void mcf5xxx_wr_acc2 (uint32);
void mcf5xxx_wr_acc3 (uint32);
void mcf5xxx_wr_pc (uint32);
void mcf5xxx_wr_rombar0 (uint32);
void mcf5xxx_wr_rombar1 (uint32);
void mcf5xxx_wr_rambar0 (uint32);
void mcf5xxx_wr_rambar1 (uint32);
void mcf5xxx_wr_mpcr (uint32);
void mcf5xxx_wr_secmbar (uint32);
void mcf5xxx_wr_mbar1 (uint32);
void mcf5xxx_wr_mbar (uint32);
void mcf5xxx_wr_mbar0 (uint32);
void mcf5xxx_move_line (ADDRESS, ADDRESS);
/*
* Functions provided in mcf5xxx.c
*/
void mcf5xxx_exception_handler (void *);
void mcf5xxx_interpret_d0d1 (int, int);
void mcf5xxx_irq_enable (void);
void mcf5xxx_irq_disable (void);
ADDRESS mcf5xxx_set_handler (int, ADDRESS);
/*
* Functions provided by processor specific C file
*/
void cpu_handle_interrupt (int);
/********************************************************************/
#endif /* _CPU_MCF5XXX_H */

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/*
* File: mcf5xxx.s
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* License: All software covered by license agreement in -
* docs/Freescale_Software_License.pdf
*/
#define mcf5xxx_exception_handler _mcf5xxx_exception_handler
.extern mcf5xxx_exception_handler
.global asm_exception_handler
.global _asm_exception_handler
.global asm_set_ipl
.global _asm_set_ipl
.global mcf5xxx_exe_wdebug
.global _mcf5xxx_exe_wdebug
.global mcf5xxx_move_line //added by Mac
.global _mcf5xxx_move_line //added by Mac
.global mcf5xxx_wr_cacr
.global _mcf5xxx_wr_cacr
.global mcf5xxx_wr_asid
.global _mcf5xxx_wr_asid
.global mcf5xxx_wr_acr0
.global _mcf5xxx_wr_acr0
.global mcf5xxx_wr_acr1
.global _mcf5xxx_wr_acr1
.global mcf5xxx_wr_acr2
.global _mcf5xxx_wr_acr2
.global mcf5xxx_wr_acr3
.global _mcf5xxx_wr_acr3
.global mcf5xxx_wr_mmubar
.global _mcf5xxx_wr_mmubar
.global mcf5xxx_wr_other_a7
.global _mcf5xxx_wr_other_a7
.global mcf5xxx_wr_vbr
.global _mcf5xxx_wr_vbr
.global mcf5xxx_wr_macsr
.global _mcf5xxx_wr_macsr
.global mcf5xxx_wr_mask
.global _mcf5xxx_wr_mask
.global mcf5xxx_wr_acc0
.global _mcf5xxx_wr_acc0
.global mcf5xxx_wr_accext01
.global _mcf5xxx_wr_accext01
.global mcf5xxx_wr_accext23
.global _mcf5xxx_wr_accext23
.global mcf5xxx_wr_acc1
.global _mcf5xxx_wr_acc1
.global mcf5xxx_wr_acc2
.global _mcf5xxx_wr_acc2
.global mcf5xxx_wr_acc3
.global _mcf5xxx_wr_acc3
.global mcf5xxx_wr_sr
.global _mcf5xxx_wr_sr
.global mcf5xxx_wr_pc
.global _mcf5xxx_wr_pc
.global mcf5xxx_wr_rombar0
.global _mcf5xxx_wr_rombar0
.global mcf5xxx_wr_rombar1
.global _mcf5xxx_wr_rombar1
.global mcf5xxx_wr_rambar0
.global _mcf5xxx_wr_rambar0
.global mcf5xxx_wr_rambar1
.global _mcf5xxx_wr_rambar1
.global mcf5xxx_wr_mpcr
.global _mcf5xxx_wr_mpcr
.global mcf5xxx_wr_secmbar
.global _mcf5xxx_wr_secmbar
.global mcf5xxx_wr_mbar
.global _mcf5xxx_wr_mbar
.text
/********************************************************************
* This routine is the lowest-level exception handler.
*/
asm_exception_handler:
_asm_exception_handler:
lea -16(SP),SP
movem.l D0-D1/A0-A1,(SP)
lea 16(SP),A1
move.l A1,-(SP)
jsr mcf5xxx_exception_handler
lea 4(SP),SP
movem.l (SP),D0-D1/A0-A1
lea 16(SP),SP
rte
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
asm_set_ipl:
_asm_set_ipl:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
/*
* These routines execute special ColdFire instructions
*/
mcf5xxx_exe_wdebug:
_mcf5xxx_exe_wdebug:
move.l 4(sp),a0
wdebug.l (a0)
rts
mcf5xxx_move_line:
_mcf5xxx_move_line:
lea.l -24(sp),sp
movem.l d0-d3/a0-a1,(sp)
movea.l 28(sp),a0 /* source in a0 */
movea.l 32(sp),a1 /* destination in a1 */
movem.l (a0),d0-d3 /* move line from source */
movem.l d0-d3,(a1) /* move line to destination */
movem.l (sp),d0-d3/a0-a1
lea.l 24(sp),sp
rts
/********************************************************************/
/*
* These routines write to the special purpose registers in the ColdFire
* core. Since these registers are write-only in the supervisor model,
* no corresponding read routines exist.
*/
mcf5xxx_wr_sr:
_mcf5xxx_wr_sr:
move.l 4(SP),D0
move.w D0,SR
rts
mcf5xxx_wr_cacr:
_mcf5xxx_wr_cacr:
move.l 4(SP),D0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
mcf5xxx_wr_asid:
_mcf5xxx_wr_asid:
move.l 4(SP),D0
.long 0x4e7b0003 /* movec d0,asid */
nop
rts
mcf5xxx_wr_acr0:
_mcf5xxx_wr_acr0:
move.l 4(SP),D0
.long 0x4e7b0004 /* movec d0,ACR0 */
nop
rts
mcf5xxx_wr_acr1:
_mcf5xxx_wr_acr1:
move.l 4(SP),D0
.long 0x4e7b0005 /* movec d0,ACR1 */
nop
rts
mcf5xxx_wr_acr2:
_mcf5xxx_wr_acr2:
move.l 4(SP),D0
.long 0x4e7b0006 /* movec d0,ACR2 */
nop
rts
mcf5xxx_wr_acr3:
_mcf5xxx_wr_acr3:
move.l 4(SP),D0
.long 0x4e7b0007 /* movec d0,ACR3 */
nop
rts
mcf5xxx_wr_mmubar:
_mcf5xxx_wr_mmubar:
move.l 4(SP),D0
.long 0x4e7b0008 /* movec d0,MBAR */
nop
rts
mcf5xxx_wr_other_a7:
_mcf5xxx_wr_other_a7:
move.l 4(SP),D0
.long 0x4e7b0800 /* movec d0,OTHER_A7 */
nop
rts
mcf5xxx_wr_vbr:
_mcf5xxx_wr_vbr:
move.l 4(SP),D0
.long 0x4e7b0801 /* movec d0,VBR */
nop
rts
mcf5xxx_wr_macsr:
_mcf5xxx_wr_macsr:
move.l 4(SP),D0
.long 0x4e7b0804 /* movec d0,MACSR */
nop
rts
mcf5xxx_wr_mask:
_mcf5xxx_wr_mask:
move.l 4(SP),D0
.long 0x4e7b0805 /* movec d0,MASK */
nop
rts
mcf5xxx_wr_acc0:
_mcf5xxx_wr_acc0:
move.l 4(SP),D0
.long 0x4e7b0806 /* movec d0,ACC0 */
nop
rts
mcf5xxx_wr_accext01:
_mcf5xxx_wr_accext01:
move.l 4(SP),D0
.long 0x4e7b0807 /* movec d0,ACCEXT01 */
nop
rts
mcf5xxx_wr_accext23:
_mcf5xxx_wr_accext23:
move.l 4(SP),D0
.long 0x4e7b0808 /* movec d0,ACCEXT23 */
nop
rts
mcf5xxx_wr_acc1:
_mcf5xxx_wr_acc1:
move.l 4(SP),D0
.long 0x4e7b0809 /* movec d0,ACC1 */
nop
rts
mcf5xxx_wr_acc2:
_mcf5xxx_wr_acc2:
move.l 4(SP),D0
.long 0x4e7b080A /* movec d0,ACC2 */
nop
rts
mcf5xxx_wr_acc3:
_mcf5xxx_wr_acc3:
move.l 4(SP),D0
.long 0x4e7b080B /* movec d0,ACC3 */
nop
rts
mcf5xxx_wr_pc:
_mcf5xxx_wr_pc:
move.l 4(SP),D0
.long 0x4e7b080F /* movec d0,PC */
nop
rts
mcf5xxx_wr_rombar0:
_mcf5xxx_wr_rombar0:
move.l 4(SP),D0
.long 0x4e7b0C00 /* movec d0,ROMBAR0 */
nop
rts
mcf5xxx_wr_rombar1:
_mcf5xxx_wr_rombar1:
move.l 4(SP),D0
.long 0x4e7b0C01 /* movec d0,ROMBAR1 */
nop
rts
mcf5xxx_wr_rambar0:
_mcf5xxx_wr_rambar0:
move.l 4(SP),D0
.long 0x4e7b0C04 /* movec d0,RAMBAR0 */
nop
rts
mcf5xxx_wr_rambar1:
_mcf5xxx_wr_rambar1:
move.l 4(SP),D0
.long 0x4e7b0C05 /* movec d0,RAMBAR1 */
nop
rts
mcf5xxx_wr_mpcr:
_mcf5xxx_wr_mpcr:
move.l 4(SP),D0
.long 0x4e7b0C0C /* movec d0,MPCR */
nop
rts
mcf5xxx_wr_secmbar:
_mcf5xxx_wr_secmbar:
move.l 4(SP),D0
.long 0x4e7b0C0E /* movec d0,MBAR1 */
nop
rts
mcf5xxx_wr_mbar:
_mcf5xxx_wr_mbar:
move.l 4(SP),D0
.long 0x4e7b0C0F /* movec d0,MBAR0 */
nop
rts
/********************************************************************/
.end