len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-20 10:08:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add MCF52259 demo.

Browse source
This commit is contained in:
Richard Barry 2009-02-07 17:52:41 +00:00
parent 8981a8539a
commit fe73d24184
60 changed files with 10188 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

14
Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.cfg Normal file
View file

@ -0,0 +1,14 @@
ResetHalt
; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000
; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021
; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061
; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F

31
Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTERNAL_FLASH.mem Normal file
View file

@ -0,0 +1,31 @@
// Memory Configuration File
//
// Description:
// A memory configuration file contains commands that define the legally accessible
// areas of memory for your specific board. Useful for example when the debugger
// tries to display the content of a "char *" variable, that has not yet been initialized.
// In this case the debugger may try to read from a bogus address, which could cause a
// bus error.
//
// Board:
// Freescale MCF52259
//
// Reference:
//
// All reserved ranges read back 0xBABA...
reservedchar 0xBA
address IPSBAR_BASE 0x40000000
usederivative "MCF52259"
// Memory Map:
// ----------------------------------------------------------------------
range 0x00000000 0x0007FFFF 4 Read // 512 KByte Internal Flash Memory
reserved 0x00080000 0x1FFFFFFF
range 0x20000000 0x2000FFFF 4 ReadWrite // 64 Kbytes Internal SRAM
reserved 0x20010000 0x3FFFFFFF
// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
reserved $IPSBAR_BASE + 0x200000 0xFFFFFFFF

48
Demo/ColdFire_MCF52259_CodeWarrior/cfg/MCF52259_INTFLASH.xml Normal file
View file

@ -0,0 +1,48 @@
<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
<fpconfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="fp_config.xsd">
<targetconfwindow>
<usecustomsettings>false</usecustomsettings>
<targetprocessor>52259</targetprocessor>
<connection></connection>
<usetargetinit>true</usetargetinit>
<targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF52259.cfg</targetinitfile>
<targetmembuffaddr>0x20000000</targetmembuffaddr>
<targetmembuffsize>0x00008000</targetmembuffsize>
<enablelogging>true</enablelogging>
<verifywrites>false</verifywrites>
</targetconfwindow>
<flashconfwindow>
<membaseaddr>0x00000000</membaseaddr>
<device>CFM_MCF5225X_512</device>
<organization>32Kx16x1</organization>
<flashstart>0x00000000</flashstart>
<flashend>0x0007FFFF</flashend>
</flashconfwindow>
<programverifywindow>
<useselectedfile>false</useselectedfile>
<projbuildtargetfile>nofile</projbuildtargetfile>
<fileiotype>Auto Detect</fileiotype>
<restrictaddrrange>false</restrictaddrrange>
<restrictaddrrangestart>0x00000000</restrictaddrrangestart>
<restrictaddrrangeend>0x0007FFFF</restrictaddrrangeend>
<applyaddroffset>false</applyaddroffset>
<addroffset>0x00000000</addroffset>
</programverifywindow>
<eraseblankcheckwindow>
<eraseallsectors>true</eraseallsectors>
<sector/>
<processsectorsindividually>false</processsectorsindividually>
</eraseblankcheckwindow>
<checksumwindow>
<computechecksumover>FileOnTarg</computechecksumover>
<addrstart>0x00000000</addrstart>
<addrsize>0x0000FFFF</addrsize>
</checksumwindow>
</fpconfig>

14
Demo/ColdFire_MCF52259_CodeWarrior/cfg/mcf5225xEVB_PnE.cfg Normal file
View file

@ -0,0 +1,14 @@
ResetHalt
; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000
; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021
; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061
; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F