mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-06 06:07:45 -04:00
RM48 port layer without FPU saving completed.
This commit is contained in:
Richard Barry
parent
1112439c58
commit
fe2163ede4
8 changed files with 219 additions and 849 deletions
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@ -1,6 +1,6 @@
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/*
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FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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***************************************************************************
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* *
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@ -40,7 +40,7 @@
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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@ -50,184 +50,208 @@
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, training, latest information,
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http://www.FreeRTOS.org - Documentation, training, latest information,
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license and contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool.
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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the code with commercial support, indemnification, and middleware, under
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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the code with commercial support, indemnification, and middleware, under
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the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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provide a safety engineered and independently SIL3 certified version under
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provide a safety engineered and independently SIL3 certified version under
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the SafeRTOS brand: http://www.SafeRTOS.com.
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*/
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/*----------------------------------------------------------------------------*/
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/* Include Files */
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/*----------------------------------------------------------------------------*/
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/* Global Variables */
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/*-----------------------------------------------------------*/
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/* Count of the critical section nesting depth. */
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unsigned portLONG ulCriticalNesting = 9999;
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/*----------------------------------------------------------------------------*/
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/* Macros */
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/*-----------------------------------------------------------*/
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#define portINITIAL_SPSR ((portSTACK_TYPE) 0x1F)
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#define portINITIAL_FPSCR ((portSTACK_TYPE) 0x00)
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#define portINSTRUCTION_SIZE ((portSTACK_TYPE) 0x04)
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#define portTHUMB_MODE_BIT ((portSTACK_TYPE) 0x20)
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/* Registers required to configure the RTI. */
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#define portRTI_GCTRL_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC00 ) )
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#define portRTI_TBCTRL_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC04 ) )
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#define portRTI_COMPCTRL_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC0C ) )
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#define portRTI_CNT0_FRC0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC10 ) )
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#define portRTI_CNT0_UC0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC14 ) )
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#define portRTI_CNT0_CPUC0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC18 ) )
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#define portRTI_CNT0_COMP0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC50 ) )
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#define portRTI_CNT0_UDCP0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC54 ) )
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#define portRTI_SETINTENA_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC80 ) )
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#define portRTI_CLEARINTENA_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC84 ) )
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#define portRTI_INTFLAG_REG ( * ( ( volatile unsigned long * ) 0xFFFFFC88 ) )
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/*----------------------------------------------------------------------------*/
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/* pxPortInitialiseStack */
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portSTACK_TYPE * pxPortInitialiseStack(portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters)
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/* Constants required to set up the initial stack of each task. */
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#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1F )
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#define portINITIAL_FPSCR ( ( portSTACK_TYPE ) 0x00 )
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#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0x04 )
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#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
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/* The number of words on the stack frame between the saved Top Of Stack and
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R0 (in which the parameters are passed. */
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#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 )
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/*-----------------------------------------------------------*/
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/* vPortStartFirstSTask() is defined in portASM.asm */
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extern void vPortStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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{
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portSTACK_TYPE *pxOriginalTOS = pxTopOfStack;
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*pxTopOfStack-- = (portSTACK_TYPE) pxCode + portINSTRUCTION_SIZE;
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*pxTopOfStack-- = (portSTACK_TYPE) 0xaaaaaaaa;
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*pxTopOfStack-- = (portSTACK_TYPE) pxOriginalTOS;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x12121212;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x11111111;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x10101010;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x09090909;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x08080808;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x07070707;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x06060606;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x05050505;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x04040404;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x03030303;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x02020202;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x01010101;
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*pxTopOfStack-- = (portSTACK_TYPE) pvParameters;
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portSTACK_TYPE *pxOriginalTOS;
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#if __TI_VFPV3D16_SUPPORT__
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*pxTopOfStack-- = (portSTACK_TYPE) 0x3F3F3F3F;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x3E3E3E3E;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x3D3D3D3D;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x3C3C3C3C;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x3B3B3B3B;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x3A3A3A3A;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x39393939;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x38383838;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x37373737;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x36363636;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x35353535;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x34343434;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x33333333;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x32323232;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x31313131;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x30303030;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x2F2F2F2F;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x2E2E2E2E;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x2D2D2D2D;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x2C2C2C2C;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x2B2B2B2B;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x2A2A2A2A;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x29292929;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x28282828;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x27272727;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x26262626;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x25252525;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x24242424;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x23232323;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x22222222;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x21212121;
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*pxTopOfStack-- = (portSTACK_TYPE) 0x20202020;
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*pxTopOfStack-- = (portSTACK_TYPE) portINITIAL_FPSCR;
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#endif
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pxOriginalTOS = pxTopOfStack;
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/* Setup the initial stack of the task. The stack is set exactly as
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expected by the portRESTORE_CONTEXT() macro. */
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*pxTopOfStack = (portSTACK_TYPE) ((_get_CPSR() & ~0xFF) | portINITIAL_SPSR);
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/* First on the stack is the return address - which is the start of the as
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the task has not executed yet. The offset is added to make the return
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address appear as it would within an IRQ ISR. */
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*pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
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pxTopOfStack--;
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if (((unsigned long) pxCode & 0x01UL) != 0x00)
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{
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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*pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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pxTopOfStack--;
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return pxTopOfStack;
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#ifdef portPRELOAD_TASK_REGISTERS
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{
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*pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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pxTopOfStack--;
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}
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#else
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{
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pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
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}
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#endif
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/* Function parameters are passed in R0. */
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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pxTopOfStack--;
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/* The last thing onto the stack is the status register, which is set for
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system mode, with interrupts enabled. */
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*pxTopOfStack = ( portSTACK_TYPE ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
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if( ( ( unsigned long ) pxCode & 0x01UL ) != 0x00 )
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{
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/* The task will start in thumb mode. */
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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return pxTopOfStack;
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}
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/*----------------------------------------------------------------------------*/
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/* prvSetupTimerInterrupt */
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt(void)
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{
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#if (configGENERATE_RUN_TIME_STATS == 1)
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RTI->GCTRL &= ~0x00000001U;
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#else
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RTI->GCTRL = 0x00000000U;
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#endif
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RTI->TBCTRL = 0x00000000U;
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RTI->COMPCTRL = 0x00000000U;
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RTI->CNT[0U].UCx = 0x00000000U;
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RTI->CNT[0U].FRCx = 0x00000000U;
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RTI->CNT[0U].CPUCx = 0x00000001U;
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RTI->CMP[0U].COMPx = configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ;
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RTI->CMP[0U].UDCPx = configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ;
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RTI->INTFLAG = 0x0007000FU;
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RTI->CLEARINT = 0x00070F0FU;
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RTI->SETINT = 0x00000001U;
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RTI->GCTRL |= 0x00000001U;
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/* Disable timer 0. */
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portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
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/* Use the internal counter. */
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portRTI_TBCTRL_REG = 0x00000000U;
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/* COMPSEL0 will use the RTIFRC0 counter. */
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portRTI_COMPCTRL_REG = 0x00000000U;
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/* Initialise the counter and the prescale counter registers. */
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portRTI_CNT0_UC0_REG = 0x00000000U;
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portRTI_CNT0_FRC0_REG = 0x00000000U;
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/* Set Prescalar for RTI clock. */
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portRTI_CNT0_CPUC0_REG = 0x00000001U;
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portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
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/* Clear interrupts. */
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portRTI_INTFLAG_REG = 0x0007000FU;
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portRTI_CLEARINTENA_REG = 0x00070F0FU;
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/* Enable the compare 0 interrupt. */
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portRTI_SETINTENA_REG = 0x00000001U;
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portRTI_GCTRL_REG |= 0x00000001U;
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}
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/*-----------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* vPortStartFirstTask */
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/* vPortStartFirstSTask() is defined in portASM.asm */
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extern void vPortStartFirstTask(void);
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/*----------------------------------------------------------------------------*/
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/* xPortStartScheduler */
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/*
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* See header file for description.
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*/
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portBASE_TYPE xPortStartScheduler(void)
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{
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/* Start the timer that generates the tick ISR. */
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prvSetupTimerInterrupt();
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/* Enable critical sections */
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ulCriticalNesting = 0;
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prvSetupTimerInterrupt();
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/* Reset the critical section nesting count read to execute the first task. */
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ulCriticalNesting = 0;
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/* Start the first task. This is done from portASM.asm as ARM mode must be
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used. */
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vPortStartFirstTask();
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vPortStartFirstTask();
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/* Should not get here! */
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return 0;
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return pdFAIL;
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}
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/*-----------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* vPortEndScheduler */
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/*
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* See header file for description.
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*/
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void vPortEndScheduler(void)
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{
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/* It is unlikely that the ARM port will require this function as there
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is nothing to return to. If this is required - stop the tick ISR then
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return back to main. */
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/* It is unlikely that the port will require this function as there
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is nothing to return to. */
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}
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/*----------------------------------------------------------------------------*/
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/* vNonPreemptiveTick / vPreemptiveTick */
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/*-----------------------------------------------------------*/
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#if configUSE_PREEMPTION == 0
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/* The cooperative scheduler requires a normal IRQ service routine to
|
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/* The cooperative scheduler requires a normal IRQ service routine to
|
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* simply increment the system tick. */
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__interrupt void vNonPreemptiveTick( void )
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__interrupt void vPortNonPreemptiveTick( void )
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{
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/* clear clock interrupt flag */
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RTI->INTFLAG = 0x00000001;
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/* clear clock interrupt flag */
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RTI->INTFLAG = 0x00000001;
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/* Increment the tick count - this may make a delaying task ready
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to run - but a context switch is not performed. */
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to run - but a context switch is not performed. */
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vTaskIncrementTick();
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}
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@ -235,49 +259,51 @@ void vPortEndScheduler(void)
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/*
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**************************************************************************
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* The preemptive scheduler ISR is written in assembler and can be found
|
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* The preemptive scheduler ISR is written in assembler and can be found
|
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* in the portASM.asm file. This will only get used if portUSE_PREEMPTION
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* is set to 1 in portmacro.h
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**************************************************************************
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**************************************************************************
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*/
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void vPreemptiveTick(void);
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void vPortPreemptiveTick( void );
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#endif
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/*-----------------------------------------------------------*/
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|
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/*----------------------------------------------------------------------------*/
|
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/* vPortEnterCritical */
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void vPortEnterCritical(void)
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/*
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* Disable interrupts, and keep a count of the nesting depth.
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*/
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void vPortEnterCritical( void )
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||||
{
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/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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portDISABLE_INTERRUPTS();
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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portDISABLE_INTERRUPTS();
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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||||
directly. Increment ulCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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ulCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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|
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/*----------------------------------------------------------------------------*/
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/* vPortExitCritical */
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void vPortExitCritical(void)
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/*
|
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* Decrement the critical nesting count, and if it has reached zero, re-enable
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* interrupts.
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*/
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||||
void vPortExitCritical( void )
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||||
{
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if(ulCriticalNesting > 0)
|
||||
{
|
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if( ulCriticalNesting > 0 )
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{
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/* Decrement the nesting count as we are leaving a critical section. */
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ulCriticalNesting--;
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ulCriticalNesting--;
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|
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/* If the nesting level has reached zero then interrupts should be
|
||||
re-enabled. */
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if(ulCriticalNesting == 0)
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||||
{
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/* If the nesting level has reached zero then interrupts should be
|
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re-enabled. */
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if( ulCriticalNesting == 0 )
|
||||
{
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/* Enable interrupts as per portENABLE_INTERRUPTS(). */
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portENABLE_INTERRUPTS();
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}
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}
|
||||
portENABLE_INTERRUPTS();
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -144,10 +144,10 @@ vPortYeildWithinAPI
|
|||
;-------------------------------------------------------------------------------
|
||||
; Preemptive Tick
|
||||
|
||||
.def vPreemptiveTick
|
||||
.def vPortPreemptiveTick
|
||||
.ref vTaskIncrementTick
|
||||
|
||||
vPreemptiveTick
|
||||
vPortPreemptiveTick
|
||||
portSAVE_CONTEXT
|
||||
; clear interrupt flag
|
||||
movw r0, #0xFC88
|
||||
|
|
|
|||
|
|
@ -64,55 +64,20 @@
|
|||
the SafeRTOS brand: http://www.SafeRTOS.com.
|
||||
*/
|
||||
|
||||
#ifndef __OS_PORTMACRO_H__
|
||||
#define __OS_PORTMACRO_H__
|
||||
#ifndef __PORTMACRO_H__
|
||||
#define __PORTMACRO_H__
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* RTI Register Frame Definition */
|
||||
|
||||
struct rti
|
||||
{
|
||||
unsigned GCTRL;
|
||||
unsigned TBCTRL;
|
||||
unsigned CAPCTRL;
|
||||
unsigned COMPCTRL;
|
||||
struct
|
||||
{
|
||||
unsigned FRCx;
|
||||
unsigned UCx;
|
||||
unsigned CPUCx;
|
||||
unsigned : 32;
|
||||
unsigned CAFRCx;
|
||||
unsigned CAUCx;
|
||||
unsigned : 32;
|
||||
unsigned : 32;
|
||||
} CNT[2U];
|
||||
struct
|
||||
{
|
||||
unsigned COMPx;
|
||||
unsigned UDCPx;
|
||||
} CMP[4U];
|
||||
unsigned TBLCOMP;
|
||||
unsigned TBHCOMP;
|
||||
unsigned : 32;
|
||||
unsigned : 32;
|
||||
unsigned SETINT;
|
||||
unsigned CLEARINT;
|
||||
unsigned INTFLAG;
|
||||
unsigned : 32;
|
||||
unsigned DWDCTRL;
|
||||
unsigned DWDPRLD;
|
||||
unsigned WDSTATUS;
|
||||
unsigned WDKEY;
|
||||
unsigned WDCNTR;
|
||||
};
|
||||
|
||||
#define RTI ((volatile struct rti *)0xFFFFFC00U)
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Type Definitions */
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
|
|
@ -130,48 +95,29 @@ struct rti
|
|||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Architecture Definitions */
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH (-1)
|
||||
#define portTICK_RATE_MS ((portTickType) 1000 / configTICK_RATE_HZ)
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* External Functions */
|
||||
|
||||
/* Critical section handling. */
|
||||
extern void vPortEnterCritical(void);
|
||||
extern void vPortExitCritical(void);
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
#define portDISABLE_INTERRUPTS() asm( " CPSID I" )
|
||||
#define portENABLE_INTERRUPTS() asm( " CPSIE I" )
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Functions Macros */
|
||||
|
||||
#define portYIELD() _call_swi(0)
|
||||
#define portYIELD_WITHIN_API() { *(volatile unsigned *)0xFFFFFFB0 = 0x7500; *(volatile unsigned *)0xFFFFFFB0; }
|
||||
#define portYIELD_FROM_ISR() { *(volatile unsigned *)0xFFFFFFB0 = 0x7500; *(volatile unsigned *)0xFFFFFFB0; }
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
#define portDISABLE_INTERRUPTS() asm(" CPSID I")
|
||||
#define portENABLE_INTERRUPTS() asm(" CPSIE I")
|
||||
/* Scheduler utilities. */
|
||||
#define portYIELD() _call_swi( 0 )
|
||||
#define portSYS_SSIR1_REG ( * ( ( volatile unsigned long * ) 0xFFFFFFB0 ) )
|
||||
#define portSYS_SSIR1_SSKEY ( 0x7500UL )
|
||||
#define portYIELD_WITHIN_API() { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; ( void ) portSYS_SSIR1_REG; }
|
||||
#define portYIELD_FROM_ISR() { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; ( void ) portSYS_SSIR1_REG; }
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
|
||||
#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
|
||||
|
||||
#if (configGENERATE_RUN_TIME_STATS == 1)
|
||||
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() \
|
||||
{ \
|
||||
RTI->GCTRL = 0x00000000U; \
|
||||
RTI->TBCTRL = 0x00000000U; \
|
||||
RTI->COMPCTRL = 0x00000000U; \
|
||||
RTI->CNT[1U].UCx = 0x00000000U; \
|
||||
RTI->CNT[1U].FRCx = 0x00000000U; \
|
||||
RTI->CNT[1U].CPUCx = (configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ) / 16; \
|
||||
RTI->CMP[1U].UDCPx = (configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ) / 16; \
|
||||
RTI->GCTRL = 0x00000002U; \
|
||||
}
|
||||
#define portGET_RUN_TIME_COUNTER_VALUE() (RTI->CNT[1].FRCx)
|
||||
#endif
|
||||
#endif /* __PORTMACRO_H__ */
|
||||
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue