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Adding SMP coverity example (#1039)
* Adding SMP coverity example * Add coverity scan flow * Fix format * Update README.md * Code review suggestions Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> --------- Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
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39
.github/workflows/coverity_scan.yml
vendored
39
.github/workflows/coverity_scan.yml
vendored
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@ -86,3 +86,42 @@ jobs:
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echo "::endgroup::"
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echo "::endgroup::"
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echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
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echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
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echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
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echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
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- env:
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stepName: Coverity Build for SMP FreeRTOS
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COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
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COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
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shell: bash
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run: |
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# ${{ env.stepName }}
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echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
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export PATH="$PATH:${{env.cov_scan_path}}"
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cmake -S ./examples/cmake_example/ -B build -DFREERTOS_SMP_EXAMPLE=1
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cd build
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cov-build --dir cov-int make -j
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# Move the report out of the build directory
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tar czvf ../gcc_freertos_kernel_smp_sample_build.tgz cov-int
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echo "::endgroup::"
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echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
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- env:
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stepName: Upload FreeRTOS SMP Coverity Report for Scan
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COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
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COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
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shell: bash
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run: |
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# ${{ env.stepName }}
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echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
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COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
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--form email=${COVERITY_EMAIL} \
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--form file=@gcc_freertos_kernel_smp_sample_build.tgz \
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--form version="Mainline" \
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--form description="FreeRTOS Kernel SMP Commit Scan" \
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https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
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echo "::endgroup::"
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echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
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echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
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8
MISRA.md
8
MISRA.md
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@ -18,6 +18,14 @@ with ( Assuming rule 8.4 violation; with justification in point 1 ):
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grep 'MISRA Ref 8.4.1' . -rI
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grep 'MISRA Ref 8.4.1' . -rI
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```
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```
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#### Dir 4.7
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MISRA C:2012 Dir 4.7: If a function returns error information, then that error
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information shall be tested.
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_Ref 4.7.1_
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- `taskENTER_CRITICAL_FROM_ISR` returns the interrupt mask and not any error
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information. Therefore, there is no need test the return value.
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#### Rule 8.4
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#### Rule 8.4
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MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
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MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
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@ -529,6 +529,9 @@
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traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
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traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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{
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{
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uxReturn = pxEventBits->uxEventBits;
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uxReturn = pxEventBits->uxEventBits;
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@ -23,6 +23,12 @@ target_include_directories(freertos_config
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INTERFACE
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INTERFACE
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./)
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./)
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if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
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message(STATUS "Build FreeRTOS SMP example")
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# Adding the following configurations to build SMP template port
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add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 )
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endif()
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# Select the heap. Values between 1-5 will pick a heap.
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# Select the heap. Values between 1-5 will pick a heap.
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set(FREERTOS_HEAP "3" CACHE STRING "" FORCE)
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set(FREERTOS_HEAP "3" CACHE STRING "" FORCE)
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@ -34,9 +34,16 @@ commands in a terminal:
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cov-configure --force --compiler cc --comptype gcc
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cov-configure --force --compiler cc --comptype gcc
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~~~
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~~~
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2. Create the build files using CMake in a `build` directory:
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2. Create the build files using CMake in a `build` directory:
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Singe core FreeRTOS:
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~~~
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~~~
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cmake -B build -S examples/coverity
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cmake -B build -S examples/coverity
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~~~
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~~~
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SMP FreeRTOS:
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~~~
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cmake -B build -S examples/coverity -DFREERTOS_SMP_EXAMPLE=1
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~~~
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3. Build the (pseudo) application:
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3. Build the (pseudo) application:
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~~~
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~~~
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cd build/
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cd build/
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@ -47,7 +54,7 @@ commands in a terminal:
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~~~
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~~~
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cov-analyze --dir ./cov-out \
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cov-analyze --dir ./cov-out \
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--coding-standard-config ../examples/coverity/coverity_misra.config \
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--coding-standard-config ../examples/coverity/coverity_misra.config \
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--tu-pattern "file('[A-Za-z_]+\.c')"
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--tu-pattern "file('[A-Za-z_]+\.c') && ( ! file('main.c') ) && ( ! file('port.c') )"
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~~~
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~~~
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5. Generate the HTML report:
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5. Generate the HTML report:
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~~~
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~~~
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12
queue.c
12
queue.c
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@ -1190,6 +1190,9 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
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* read, instead return a flag to say whether a context switch is required or
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* read, instead return a flag to say whether a context switch is required or
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* not (i.e. has a task with a higher priority than us been woken by this
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* not (i.e. has a task with a higher priority than us been woken by this
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* post). */
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* post). */
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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{
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if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
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if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
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@ -1365,6 +1368,9 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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{
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const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
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const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
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@ -2055,6 +2061,9 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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{
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const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
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const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
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@ -2153,6 +2162,9 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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{
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/* Cannot block in an ISR, so check there is data available. */
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/* Cannot block in an ISR, so check there is data available. */
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@ -676,6 +676,9 @@ BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer )
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#endif
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#endif
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/* Can only reset a message buffer if there are no tasks blocked on it. */
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/* Can only reset a message buffer if there are no tasks blocked on it. */
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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{
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{
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if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
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if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
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@ -972,6 +975,9 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
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/* Was a task waiting for the data? */
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/* Was a task waiting for the data? */
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if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
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if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
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{
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{
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
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prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
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}
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}
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else
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else
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@ -1245,6 +1251,9 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
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/* Was a task waiting for space in the buffer? */
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/* Was a task waiting for space in the buffer? */
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if( xReceivedLength != ( size_t ) 0 )
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if( xReceivedLength != ( size_t ) 0 )
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{
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{
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
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prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
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}
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}
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else
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else
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@ -1397,6 +1406,9 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
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configASSERT( pxStreamBuffer );
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configASSERT( pxStreamBuffer );
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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{
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{
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if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
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if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
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@ -1433,6 +1445,9 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
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configASSERT( pxStreamBuffer );
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configASSERT( pxStreamBuffer );
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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{
|
{
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if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
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if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
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18
tasks.c
18
tasks.c
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@ -2666,6 +2666,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
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* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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|
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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{
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/* If null is passed in here then it is the priority of the calling
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/* If null is passed in here then it is the priority of the calling
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@ -2737,6 +2740,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
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* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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|
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|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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|
/* coverity[misra_c_2012_directive_4_7_violation] */
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
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{
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{
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/* If null is passed in here then it is the base priority of the calling
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/* If null is passed in here then it is the base priority of the calling
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@ -3433,6 +3439,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
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* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
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|
|
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|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
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|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
|
uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
|
||||||
{
|
{
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||||||
if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
|
if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
|
||||||
|
@ -4989,6 +4998,9 @@ BaseType_t xTaskIncrementTick( void )
|
||||||
|
|
||||||
/* Save the hook function in the TCB. A critical section is required as
|
/* Save the hook function in the TCB. A critical section is required as
|
||||||
* the value can be accessed from an interrupt. */
|
* the value can be accessed from an interrupt. */
|
||||||
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
|
uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
|
||||||
{
|
{
|
||||||
xReturn = pxTCB->pxTaskTag;
|
xReturn = pxTCB->pxTaskTag;
|
||||||
|
@ -7974,6 +7986,9 @@ TickType_t uxTaskResetEventItemValue( void )
|
||||||
|
|
||||||
pxTCB = xTaskToNotify;
|
pxTCB = xTaskToNotify;
|
||||||
|
|
||||||
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
|
uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
|
||||||
{
|
{
|
||||||
if( pulPreviousNotificationValue != NULL )
|
if( pulPreviousNotificationValue != NULL )
|
||||||
|
@ -8133,6 +8148,9 @@ TickType_t uxTaskResetEventItemValue( void )
|
||||||
|
|
||||||
pxTCB = xTaskToNotify;
|
pxTCB = xTaskToNotify;
|
||||||
|
|
||||||
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
|
uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
|
||||||
{
|
{
|
||||||
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
|
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
|
||||||
|
|
Loading…
Reference in a new issue