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Kernel changes:

Browse source 
+ Made xTaskNotifyGiveFromISR() its own function, rather than a macro that calls xTaskNotifyFromISR() (minor performance improvement).
+ GCC and Keil Cortex-M4F ports now use vPortRaiseBASEPRI() in place of ulPortRaiseBASEPRI() where the return value is not required (minor performance improvement).

Demo changes:
Change the [very basic] FreeRTOS+UDP SAM4E driver to use task notifications rather than a semaphore (execution time now 55% what it was in FreeRTOS V8.1.2!).
Robustness improvements to IntQueue.c standard demo task.h.
Added the latest standard demo tasks, reg test tasks and int q  tasks to the SAM4E demo.
This commit is contained in:
Richard Barry 2014-12-21 10:26:36 +00:00
parent 2de32c0141
commit fd02010886
24 changed files with 1899 additions and 323 deletions
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BIN
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/RTOSDemo.atsuo
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40
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/RTOSDemo.cproj
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@ -15,8 +15,9 @@
<option id="sam.components.display.aat31xx" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.components.display.ili93xx" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.components.ethernet_phy.ksz8051mnl" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.drivers.gmac" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.drivers.smc" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.drivers.gmac" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.drivers.tc" value="Add" config="" content-id="Atmel.ASF" />
<option id="common.applications.user_application" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.utils.cmsis.sam4e.source.template" value="Add" config="" content-id="Atmel.ASF" />
</options>
@ -173,6 +174,8 @@
<file path="src/Config/conf_ili93xx.h" framework="" version="3.11.0" source="sam\components\display\ili93xx\module_config\conf_ili93xx.h" changed="False" content-id="Atmel.ASF" />
<file path="src/ASF/sam/drivers/ebi/smc/smc.c" framework="" version="3.11.0" source="sam\drivers\ebi\smc\smc.c" changed="False" content-id="Atmel.ASF" />
<file path="src/ASF/sam/drivers/ebi/smc/smc.h" framework="" version="3.11.0" source="sam\drivers\ebi\smc\smc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/ASF/sam/drivers/tc/tc.c" framework="" version="3.11.0" source="sam\drivers\tc\tc.c" changed="False" content-id="Atmel.ASF" />
<file path="src/ASF/sam/drivers/tc/tc.h" framework="" version="3.11.0" source="sam\drivers\tc\tc.h" changed="False" content-id="Atmel.ASF" />
</files>
<documentation help="http://asf.atmel.com/docs/3.11.0/common.applications.user_application.sam4e_ek/html/index.html" />
<offline-documentation help="" />
@ -207,12 +210,12 @@
<ToolOptions>
<InterfaceProperties>
<JtagEnableExtResetOnStartSession>false</JtagEnableExtResetOnStartSession>
<SwdClock>12000000</SwdClock>
<SwdClock>7020000</SwdClock>
</InterfaceProperties>
<InterfaceName>SWD</InterfaceName>
</ToolOptions>
<ToolType>com.atmel.avrdbg.tool.samice</ToolType>
<ToolNumber>000158000789</ToolNumber>
<ToolNumber>158000789</ToolNumber>
<ToolName>J-Link</ToolName>
</com_atmel_avrdbg_tool_samice>
<avrtoolinterface>SWD</avrtoolinterface>
@ -261,6 +264,7 @@
<Value>../src/ASF/sam/components/display/aat31xx</Value>
<Value>../src/ASF/sam/components/display/ili93xx</Value>
<Value>../src/ASF/sam/drivers/ebi/smc</Value>
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
@ -310,6 +314,7 @@
<Value>../src/ASF/sam/components/display/aat31xx</Value>
<Value>../src/ASF/sam/components/display/ili93xx</Value>
<Value>../src/ASF/sam/drivers/ebi/smc</Value>
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.preprocessingassembler.general.IncludePaths>
</ArmGcc>
@ -372,6 +377,7 @@
<Value>../src/ASF/sam/components/display/ili93xx</Value>
<Value>../src/ASF/sam/drivers/ebi/smc</Value>
<Value>../../../../FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients</Value>
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
@ -391,6 +397,7 @@
</ListValues>
</armgcc.linker.libraries.LibrarySearchPaths>
<armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
<armgcc.linker.memorysettings.ExternalRAM />
<armgcc.linker.miscellaneous.LinkerFlags>-Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam4e/sam4e16e/gcc/flash.ld</armgcc.linker.miscellaneous.LinkerFlags>
<armgcc.assembler.debugging.DebugLevel>Default (-g)</armgcc.assembler.debugging.DebugLevel>
<armgcc.preprocessingassembler.general.AssemblerFlags>-DARM_MATH_CM4=true -DBOARD=SAM4E_EK -D__SAM4E16E__ -Dprintf=iprintf</armgcc.preprocessingassembler.general.AssemblerFlags>
@ -422,6 +429,7 @@
<Value>../src/ASF/sam/components/display/aat31xx</Value>
<Value>../src/ASF/sam/components/display/ili93xx</Value>
<Value>../src/ASF/sam/drivers/ebi/smc</Value>
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.preprocessingassembler.general.IncludePaths>
<armgcc.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcc.preprocessingassembler.debugging.DebugLevel>
@ -525,6 +533,14 @@
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\GenQTest.c</Link>
</Compile>
<Compile Include="..\Common\Minimal\IntQueue.c">
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\IntQueue.c</Link>
</Compile>
<Compile Include="..\Common\Minimal\IntSemTest.c">
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\IntSemTest.c</Link>
</Compile>
<Compile Include="..\Common\Minimal\QPeek.c">
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\QPeek.c</Link>
@ -545,6 +561,14 @@
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\semtest.c</Link>
</Compile>
<Compile Include="..\Common\Minimal\TaskNotify.c">
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\TaskNotify.c</Link>
</Compile>
<Compile Include="..\Common\Minimal\TimerDemo.c">
<SubType>compile</SubType>
<Link>src\Common Demo Tasks\TimerDemo.c</Link>
</Compile>
<Compile Include="src\ASF\sam\components\display\aat31xx\aat31xx.c">
<SubType>compile</SubType>
</Compile>
@ -569,6 +593,12 @@
<None Include="src\ASF\sam\drivers\ebi\smc\smc.h">
<SubType>compile</SubType>
</None>
<Compile Include="src\ASF\sam\drivers\tc\tc.c">
<SubType>compile</SubType>
</Compile>
<None Include="src\ASF\sam\drivers\tc\tc.h">
<SubType>compile</SubType>
</None>
<Compile Include="src\ASF\sam\utils\syscalls\gcc\syscalls.c">
<SubType>compile</SubType>
</Compile>
@ -590,6 +620,9 @@
<Compile Include="src\FreeRTOS+\FreeRTOS+FAT SL\API\fat_sl.h">
<SubType>compile</SubType>
</Compile>
<Compile Include="src\IntQueueTimer.c">
<SubType>compile</SubType>
</Compile>
<Compile Include="src\LCDUtils.c">
<SubType>compile</SubType>
</Compile>
@ -1102,6 +1135,7 @@
<Folder Include="src\ASF\sam\drivers\ebi\smc\" />
<Folder Include="src\ASF\sam\drivers\gmac\" />
<Folder Include="src\ASF\sam\drivers\pmc\" />
<Folder Include="src\ASF\sam\drivers\tc\" />
<Folder Include="src\ASF\sam\utils\" />
<Folder Include="src\ASF\sam\utils\cmsis\" />
<Folder Include="src\ASF\sam\utils\cmsis\sam4e\" />

596
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.c Normal file
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@ -0,0 +1,596 @@
/**
* \file
*
* \brief Timer Counter (TC) driver for SAM.
*
* Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <assert.h>
#include "tc.h"
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond
#define TC_WPMR_WPKEY_VALUE TC_WPMR_WPKEY((uint32_t)0x54494D)
/**
* \defgroup sam_drivers_tc_group Timer Counter (TC)
*
* The Timer Counter (TC) includes three identical 32-bit Timer Counter
* channels. Each channel can be independently programmed to perform a wide
* range of functions including frequency measurement, event counting,
* interval measurement, pulse generation, delay timing and pulse width
* modulation.
*
* @{
*/
/**
* \brief Configure TC for timer, waveform generation or capture.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_mode Control mode register value to set.
*
* \attention If the TC is configured for waveform generation, the external
* event selection (EEVT) should only be set to \c TC_CMR_EEVT_TIOB or the
* equivalent value \c 0 if it really is the intention to use TIOB as an
* external event trigger.\n
* This is because the setting forces TIOB to be an input even if the
* external event trigger has not been enabled with \c TC_CMR_ENETRG, and
* thus prevents normal operation of TIOB.
*/
void tc_init(Tc *p_tc, uint32_t ul_channel, uint32_t ul_mode)
{
TcChannel *tc_channel;
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
tc_channel = p_tc->TC_CHANNEL + ul_channel;
/* Disable TC clock. */
tc_channel->TC_CCR = TC_CCR_CLKDIS;
/* Disable interrupts. */
tc_channel->TC_IDR = 0xFFFFFFFF;
/* Clear status register. */
tc_channel->TC_SR;
/* Set mode. */
tc_channel->TC_CMR = ul_mode;
}
/**
* \brief Asserts a SYNC signal to generate a software trigger to
* all channels.
*
* \param p_tc Pointer to a TC instance.
*
*/
void tc_sync_trigger(Tc *p_tc)
{
p_tc->TC_BCR = TC_BCR_SYNC;
}
/**
* \brief Configure TC Block mode.
* \note tc_init() must be called first.
*
* \param p_tc Pointer to a TC instance.
* \param ul_blockmode Block mode register value to set.
*
*/
void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode)
{
p_tc->TC_BMR = ul_blockmode;
}
#if (!SAM3U)
/**
* \brief Configure TC for 2-bit Gray Counter for Stepper Motor.
* \note tc_init() must be called first.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_steppermode Stepper motor mode register value to set.
*
* \return 0 for OK.
*/
uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_steppermode)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
p_tc->TC_CHANNEL[ul_channel].TC_SMMR = ul_steppermode;
return 0;
}
#endif
/**
* \brief Start TC clock counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*/
void tc_start(Tc *p_tc, uint32_t ul_channel)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
}
/**
* \brief Stop TC clock counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*/
void tc_stop(Tc *p_tc, uint32_t ul_channel)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKDIS;
}
/**
* \brief Read counter value on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*
* \return Counter value.
*/
uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
return p_tc->TC_CHANNEL[ul_channel].TC_CV;
}
/**
* \brief Read RA TC counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*
* \return RA value.
*/
uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
return p_tc->TC_CHANNEL[ul_channel].TC_RA;
}
/**
* \brief Read RB TC counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*
* \return RB value.
*/
uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
return p_tc->TC_CHANNEL[ul_channel].TC_RB;
}
/**
* \brief Read RC TC counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*
* \return RC value.
*/
uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
return p_tc->TC_CHANNEL[ul_channel].TC_RC;
}
/**
* \brief Write RA TC counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_value Value to set in register.
*/
void tc_write_ra(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_value)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
p_tc->TC_CHANNEL[ul_channel].TC_RA = ul_value;
}
/**
* \brief Write RB TC counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_value Value to set in register.
*/
void tc_write_rb(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_value)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
p_tc->TC_CHANNEL[ul_channel].TC_RB = ul_value;
}
/**
* \brief Write RC TC counter on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_value Value to set in register.
*/
void tc_write_rc(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_value)
{
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
p_tc->TC_CHANNEL[ul_channel].TC_RC = ul_value;
}
/**
* \brief Enable TC interrupts on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_sources Interrupt sources bit map.
*/
void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_sources)
{
TcChannel *tc_channel;
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
tc_channel = p_tc->TC_CHANNEL + ul_channel;
tc_channel->TC_IER = ul_sources;
}
/**
* \brief Disable TC interrupts on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
* \param ul_sources Interrupt sources bit map.
*/
void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_sources)
{
TcChannel *tc_channel;
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
tc_channel = p_tc->TC_CHANNEL + ul_channel;
tc_channel->TC_IDR = ul_sources;
}
/**
* \brief Read TC interrupt mask on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*
* \return The interrupt mask value.
*/
uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel)
{
TcChannel *tc_channel;
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
tc_channel = p_tc->TC_CHANNEL + ul_channel;
return tc_channel->TC_IMR;
}
/**
* \brief Get current status on the selected channel.
*
* \param p_tc Pointer to a TC instance.
* \param ul_channel Channel to configure.
*
* \return The current TC status.
*/
uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel)
{
TcChannel *tc_channel;
Assert(ul_channel <
(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
tc_channel = p_tc->TC_CHANNEL + ul_channel;
return tc_channel->TC_SR;
}
/* TC divisor used to find the lowest acceptable timer frequency */
#define TC_DIV_FACTOR 65536
#if (!SAM4L)
#ifndef FREQ_SLOW_CLOCK_EXT
#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */
#endif
/**
* \brief Find the best MCK divisor.
*
* Finds the best MCK divisor given the timer frequency and MCK. The result
* is guaranteed to satisfy the following equation:
* \code
* (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
* \endcode
* with DIV being the lowest possible value,
* to maximize timing adjust resolution.
*
* \param ul_freq Desired timer frequency.
* \param ul_mck Master clock frequency.
* \param p_uldiv Divisor value.
* \param p_ultcclks TCCLKS field value for divisor.
* \param ul_boardmck Board clock frequency.
*
* \return 1 if a proper divisor has been found, otherwise 0.
*/
uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck,
uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck)
{
const uint32_t divisors[5] = { 2, 8, 32, 128,
ul_boardmck / FREQ_SLOW_CLOCK_EXT };
uint32_t ul_index;
uint32_t ul_high, ul_low;
/* Satisfy frequency bound. */
for (ul_index = 0;
ul_index < (sizeof(divisors) / sizeof(divisors[0]));
ul_index++) {
ul_high = ul_mck / divisors[ul_index];
ul_low = ul_high / TC_DIV_FACTOR;
if (ul_freq > ul_high) {
return 0;
} else if (ul_freq >= ul_low) {
break;
}
}
if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) {
return 0;
}
/* Store results. */
if (p_uldiv) {
*p_uldiv = divisors[ul_index];
}
if (p_ultcclks) {
*p_ultcclks = ul_index;
}
return 1;
}
#endif
#if (SAM4L)
/**
* \brief Find the best PBA clock divisor.
*
* Finds the best divisor given the timer frequency and PBA clock. The result
* is guaranteed to satisfy the following equation:
* \code
* (ul_pbaclk / (2* DIV * 65536)) <= freq <= (ul_pbaclk / (2* DIV))
* \endcode
* with DIV being the lowest possible value,
* to maximize timing adjust resolution.
*
* \param ul_freq Desired timer frequency.
* \param ul_mck PBA clock frequency.
* \param p_uldiv Divisor value.
* \param p_ultcclks TCCLKS field value for divisor.
* \param ul_boardmck useless here.
*
* \return 1 if a proper divisor has been found, otherwise 0.
*/
uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck,
uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck)
{
const uint32_t divisors[5] = { 0, 2, 8, 32, 128};
uint32_t ul_index;
uint32_t ul_high, ul_low;
UNUSED(ul_boardmck);
/* Satisfy frequency bound. */
for (ul_index = 1;
ul_index < (sizeof(divisors) / sizeof(divisors[0]));
ul_index++) {
ul_high = ul_mck / divisors[ul_index];
ul_low = ul_high / TC_DIV_FACTOR;
if (ul_freq > ul_high) {
return 0;
} else if (ul_freq >= ul_low) {
break;
}
}
if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) {
return 0;
}
/* Store results. */
if (p_uldiv) {
*p_uldiv = divisors[ul_index];
}
if (p_ultcclks) {
*p_ultcclks = ul_index;
}
return 1;
}
#endif
#if (!SAM4L)
/**
* \brief Enable TC QDEC interrupts.
*
* \param p_tc Pointer to a TC instance.
* \param ul_sources Interrupts to be enabled.
*/
void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
{
p_tc->TC_QIER = ul_sources;
}
/**
* \brief Disable TC QDEC interrupts.
*
* \param p_tc Pointer to a TC instance.
* \param ul_sources Interrupts to be disabled.
*/
void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
{
p_tc->TC_QIDR = ul_sources;
}
/**
* \brief Read TC QDEC interrupt mask.
*
* \param p_tc Pointer to a TC instance.
*
* \return The interrupt mask value.
*/
uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc)
{
return p_tc->TC_QIMR;
}
/**
* \brief Get current QDEC status.
*
* \param p_tc Pointer to a TC instance.
*
* \return The current TC status.
*/
uint32_t tc_get_qdec_interrupt_status(Tc *p_tc)
{
return p_tc->TC_QISR;
}
#endif
#if (!SAM3U)
/**
* \brief Enable or disable write protection of TC registers.
*
* \param p_tc Pointer to a TC instance.
* \param ul_enable 1 to enable, 0 to disable.
*/
void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable)
{
if (ul_enable) {
p_tc->TC_WPMR = TC_WPMR_WPKEY_VALUE | TC_WPMR_WPEN;
} else {
p_tc->TC_WPMR = TC_WPMR_WPKEY_VALUE;
}
}
#endif
#if SAM4L
/**
* \brief Indicate features.
*
* \param p_tc Pointer to a TC instance.
*
* \return TC_FEATURES value.
*/
uint32_t tc_get_feature(Tc *p_tc)
{
return p_tc->TC_FEATURES;
}
/**
* \brief Indicate version.
*
* \param p_tc Pointer to a TC instance.
*
* \return TC_VERSION value.
*/
uint32_t tc_get_version(Tc *p_tc)
{
return p_tc->TC_VERSION;
}
#endif
//@}
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond

114
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/ASF/sam/drivers/tc/tc.h Normal file
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@ -0,0 +1,114 @@
/**
* \file
*
* \brief Timer Counter (TC) driver for SAM.
*
* Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef TC_H_INCLUDED
#define TC_H_INCLUDED
#include "compiler.h"
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond
void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode);
void tc_sync_trigger(Tc *p_tc);
void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode);
#if (!SAM3U)
uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_steppermode);
#endif
void tc_start(Tc *p_tc, uint32_t ul_channel);
void tc_stop(Tc *p_tc, uint32_t ul_channel);
uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel);
uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel);
uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel);
uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel);
void tc_write_ra(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_value);
void tc_write_rb(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_value);
void tc_write_rc(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_value);
uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck,
uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck);
void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_sources);
void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel,
uint32_t ul_sources);
uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel);
uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel);
#if (!SAM4L)
void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources);
void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources);
uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc);
uint32_t tc_get_qdec_interrupt_status(Tc *p_tc);
#endif
#if (!SAM3U)
void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable);
#endif
#if SAM4L
uint32_t tc_get_feature(Tc *p_tc);
uint32_t tc_get_version(Tc *p_tc);
#endif
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond
#endif /* TC_H_INCLUDED */

198
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/IntQueueTimer.c Normal file
View file

@ -0,0 +1,198 @@
/*
FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
* Provides the two timers sources for the standard demo IntQueue test. Also
* includes a high frequency timer to maximise the interrupt nesting achieved.
*/
/* Standard includes. */
#include <limits.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo includes. */
#include "IntQueueTimer.h"
#include "IntQueue.h"
/* System includes. */
#include "board.h"
#include "asf.h"
/* The frequencies at which the first two timers expire are slightly offset to
ensure they don't remain synchronised. The frequency of the highest priority
interrupt is 20 times faster so really hammers the interrupt entry and exit
code. */
#define tmrTIMER_0_FREQUENCY ( 2000UL )
#define tmrTIMER_1_FREQUENCY ( 1003UL )
#define tmrTIMER_2_FREQUENCY ( 20000UL )
/* Priorities used by the timer interrupts - these are set differently to make
nesting likely/common. The high frequency timer operates above the max
system call interrupt priority, but does not use the RTOS API. */
#define tmrTIMER_0_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY )
#define tmrTIMER_1_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
#define tmrTIMER_2_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
/* The channels used within the TC0 timer. */
#define tmrTIMER_0_CHANNEL ( 0 )
#define tmrTIMER_1_CHANNEL ( 1 )
#define tmrTIMER_2_CHANNEL ( 2 )
/* TC register bit specifics. */
#define tmrTRIGGER_ON_RC ( 1UL << 4UL )
#define trmDIVIDER ( 128 )
/*-----------------------------------------------------------*/
/* Handers for the timer interrupts. */
void TC0_Handler( void );
void TC1_Handler( void );
void TC2_Handler( void );
/*-----------------------------------------------------------*/
/* Incremented by the high frequency timer, which operates above the max
syscall interrupt priority. This is just for inspection. */
volatile uint32_t ulHighFrequencyTimerInterrupts = 0;
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulInputFrequency;
/* Calculate the frequency of the clock that feeds the TC. */
ulInputFrequency = configCPU_CLOCK_HZ;
ulInputFrequency /= trmDIVIDER;
/* Three channels are used - two that run at or under
configMAX_SYSCALL_INTERRUPT_PRIORITY, and one that runs over
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
sysclk_enable_peripheral_clock( ID_TC0 );
sysclk_enable_peripheral_clock( ID_TC1 );
sysclk_enable_peripheral_clock( ID_TC2 );
/* Init TC channels to waveform mode - up mode clean on RC match. */
tc_init( TC0, tmrTIMER_0_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
tc_init( TC0, tmrTIMER_1_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
tc_init( TC0, tmrTIMER_2_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
tc_enable_interrupt( TC0, tmrTIMER_0_CHANNEL, tmrTRIGGER_ON_RC );
tc_enable_interrupt( TC0, tmrTIMER_1_CHANNEL, tmrTRIGGER_ON_RC );
tc_enable_interrupt( TC0, tmrTIMER_2_CHANNEL, tmrTRIGGER_ON_RC );
tc_write_rc( TC0, tmrTIMER_0_CHANNEL, ( ulInputFrequency / tmrTIMER_0_FREQUENCY ) );
tc_write_rc( TC0, tmrTIMER_1_CHANNEL, ( ulInputFrequency / tmrTIMER_1_FREQUENCY ) );
tc_write_rc( TC0, tmrTIMER_2_CHANNEL, ( ulInputFrequency / tmrTIMER_2_FREQUENCY ) );
NVIC_SetPriority( TC0_IRQn, tmrTIMER_0_PRIORITY );
NVIC_SetPriority( TC1_IRQn, tmrTIMER_1_PRIORITY );
NVIC_SetPriority( TC2_IRQn, tmrTIMER_2_PRIORITY );
NVIC_EnableIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC1_IRQn );
NVIC_EnableIRQ( TC2_IRQn );
tc_start( TC0, tmrTIMER_0_CHANNEL );
tc_start( TC0, tmrTIMER_1_CHANNEL );
tc_start( TC0, tmrTIMER_2_CHANNEL );
}
/*-----------------------------------------------------------*/
void TC0_Handler( void )
{
/* Handler for the first timer in the IntQueue test. Was the interrupt
caused by a compare on RC? */
if( ( tc_get_status( TC0, tmrTIMER_0_CHANNEL ) & ~TC_SR_CPCS ) != 0 )
{
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
}
/*-----------------------------------------------------------*/
void TC1_Handler( void )
{
/* Handler for the second timer in the IntQueue test. Was the interrupt
caused by a compare on RC? */
if( ( tc_get_status( TC0, tmrTIMER_1_CHANNEL ) & ~TC_SR_CPCS ) != 0 )
{
portYIELD_FROM_ISR( xSecondTimerHandler() );
}
}
/*-----------------------------------------------------------*/
void TC2_Handler( void )
{
/* Handler for the high frequency timer that does nothing but increment a
variable to give an indication that it is running. Was the interrupt caused
by a compare on RC? */
if( ( tc_get_status( TC0, tmrTIMER_2_CHANNEL ) & ~TC_SR_CPCS ) != 0 )
{
ulHighFrequencyTimerInterrupts++;
}
}

74
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/IntQueueTimer.h Normal file
View file

@ -0,0 +1,74 @@
/*
FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef INT_QUEUE_TIMER_H
#define INT_QUEUE_TIMER_H
void vInitialiseTimerForIntQueueTest( void );
BaseType_t xTimer0Handler( void );
BaseType_t xTimer1Handler( void );
#endif

3
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/asf.h
View file

@ -101,4 +101,7 @@
// From module: System Clock Control - SAM4E implementation
#include <sysclk.h>
// From module: TC - Timer Counter
#include <tc.h>
#endif // ASF_H

30
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/config/FreeRTOSConfig.h
View file

@ -87,13 +87,13 @@ extern uint32_t SystemCoreClock;
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_QUEUE_SETS 1
#define configUSE_IDLE_HOOK 0
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 46 * 1024 ) )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 47 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
@ -132,7 +132,7 @@ FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
@ -194,17 +194,17 @@ each node on the network has a unique MAC address. */
/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or
ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR0 172
#define configIP_ADDR1 25
#define configIP_ADDR2 218
#define configIP_ADDR3 200
/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to
0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
#define configGATEWAY_ADDR0 192
#define configGATEWAY_ADDR1 168
#define configGATEWAY_ADDR2 0
#define configGATEWAY_ADDR3 1
#define configGATEWAY_ADDR0 172
#define configGATEWAY_ADDR1 25
#define configGATEWAY_ADDR2 218
#define configGATEWAY_ADDR3 2
/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and
208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set
@ -225,10 +225,10 @@ ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
UDP echo tasks (when mainINCLUDE_ECHO_CLIENT_TASKS is set to 1 in
FreeRTOSConfig.h.
http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
#define configECHO_SERVER_ADDR0 192
#define configECHO_SERVER_ADDR1 168
#define configECHO_SERVER_ADDR2 0
#define configECHO_SERVER_ADDR3 2
#define configECHO_SERVER_ADDR0 172
#define configECHO_SERVER_ADDR1 25
#define configECHO_SERVER_ADDR2 218
#define configECHO_SERVER_ADDR3 100
/* The priority used by the Ethernet MAC driver interrupt. */

10
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/main.c
View file

@ -141,6 +141,8 @@ static void prvSetupHardware( void )
void vApplicationMallocFailedHook( void )
{
static volatile uint32_t ulCount = 0;
/* vApplicationMallocFailedHook() will only be called if
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
function that will get called if a call to pvPortMalloc() fails.
@ -150,8 +152,12 @@ void vApplicationMallocFailedHook( void )
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
vAssertCalled( __LINE__, __FILE__ );
provide information on how the remaining heap might be fragmented).
Just count the number of malloc fails as some failures may occur simply
because the network load is very high, resulting in the consumption of a
lot of network buffers. */
ulCount++;
}
/*-----------------------------------------------------------*/

494
FreeRTOS/Demo/CORTEX_M4_ATSAM4E_Atmel_Studio/src/main_full.c
View file

@ -136,6 +136,10 @@
#include "QueueSet.h"
#include "recmutex.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
#include "TimerDemo.h"
#include "IntQueue.h"
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
@ -182,7 +186,7 @@ http://www.FreeRTOS.org/udp */
/* UDP command server and echo task parameters. */
#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUDP_CLI_PORT_NUMBER ( 5001UL )
#define mainUDP_CLI_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2U )
#define mainUDP_CLI_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 90 )
#define mainECHO_CLIENT_STACK_SIZE ( configMINIMAL_STACK_SIZE + 30 )
/* Set to 1 to include the UDP echo client tasks in the build. The echo clients
@ -191,6 +195,9 @@ configECHO_SERVER_ADDR0 to configECHO_SERVER_ADDR3 constants in
FreeRTOSConfig.h. */
#define mainINCLUDE_ECHO_CLIENT_TASKS 1
/* Used by the standard demo timer tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
/*-----------------------------------------------------------*/
/*
@ -225,6 +232,14 @@ extern void vRegisterUDPCLICommands( void );
*/
extern void vInitialiseLCD( void );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file.
*/
static void prvRegTest1Task( void *pvParameters ) __attribute__((naked));
static void prvRegTest2Task( void *pvParameters ) __attribute__((naked));
/*-----------------------------------------------------------*/
/* The default IP and MAC address used by the demo. The address configuration
@ -241,12 +256,16 @@ probably be read from flash memory or an EEPROM. Here it is just hard coded.
Note each node on a network must have a unique MAC address. */
const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };
/* The following two variables are used to communicate the status of the
register check tasks to the check software timer. If the variables keep
incrementing, then the register check tasks has not discovered any errors. If
a variable stops incrementing, then an error has been found. */
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/
int main_full( void )
{
TimerHandle_t xTimer = NULL;
/* Usage instructions on http://www.FreeRTOS.org/Atmel_SAM4E_RTOS_Demo.html */
/* Initialise the LCD and output a bitmap. The IP address will also be
@ -284,8 +303,7 @@ TimerHandle_t xTimer = NULL;
has completed if DHCP is used). */
FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress );
/* Create all the other standard demo tasks. */
vStartLEDFlashTimers( mainNUM_FLASH_TIMER_LEDS );
/* Create all the other standard demo tasks. */
vCreateBlockTimeTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
@ -296,19 +314,15 @@ TimerHandle_t xTimer = NULL;
vStartQueueSetTasks();
vStartRecursiveMutexTasks();
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
vStartInterruptQueueTasks();
/* Create the software timer that performs the 'check' functionality, as
described at the top of this file. */
xTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback ); /* The callback function that inspects the status of all the other tasks. */
if( xTimer != NULL )
{
xTimerStart( xTimer, mainDONT_BLOCK );
}
/* Create the register check tasks, as described at the top of this
file */
xTaskCreate( prvRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
/* Start the scheduler itself. */
vTaskStartScheduler();
@ -325,6 +339,7 @@ TimerHandle_t xTimer = NULL;
static void prvCheckTimerCallback( TimerHandle_t xTimer )
{
static long lChangedTimerPeriodAlready = pdFALSE;
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
unsigned long ulErrorOccurred = pdFALSE;
/* Avoid compiler warnings. */
@ -372,6 +387,37 @@ unsigned long ulErrorOccurred = pdFALSE;
{
ulErrorOccurred |= ( 0x01UL << 13UL );
}
else if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 14UL );
}
else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= ( 0x01UL << 15UL );
}
else if( xAreTimerDemoTasksStillRunning( mainCHECK_TIMER_PERIOD_MS ) != pdTRUE )
{
ulErrorOccurred |= 1UL << 16UL;
}
else if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ulErrorOccurred |= 1UL << 17UL;
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
ulErrorOccurred |= 1UL << 18UL;
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
ulErrorOccurred |= 1UL << 19UL;
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
if( ulErrorOccurred != pdFALSE )
{
@ -464,6 +510,30 @@ char cIPAddress[ 20 ];
void vFullDemoIdleHook( void )
{
static TimerHandle_t xCheckTimer = NULL;
if( xCheckTimer == NULL )
{
/* Create the software timer that performs the 'check'
functionality, in the full demo. This is not done before the
scheduler is started as to do so would prevent the standard demo
timer tasks from passing their tests (they expect the timer
command queue to be empty. */
xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback ); /* The callback function that inspects the status of all the other tasks. */
if( xCheckTimer != NULL )
{
xTimerStart( xCheckTimer, mainDONT_BLOCK );
}
/* Also start some timers that just flash LEDs. */
vStartLEDFlashTimers( mainNUM_FLASH_TIMER_LEDS );
}
/* If the file system is only going to be accessed from one task then
F_FS_THREAD_AWARE can be set to 0 and the set of example files is created
before the RTOS scheduler is started. If the file system is going to be
@ -497,6 +567,15 @@ void vFullDemoTickHook( void )
/* Call the event group ISR tests. */
vPeriodicEventGroupsProcessing();
/* Exercise task notifications from interrupts. */
xNotifyTaskFromISR();
/* Use mutexes from interrupts. */
vInterruptSemaphorePeriodicTest();
/* Use timers from an interrupt. */
vTimerPeriodicISRTests();
}
/*-----------------------------------------------------------*/
@ -510,3 +589,384 @@ void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifie
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void prvRegTest1Task( void *pvParameters )
{
__asm volatile
(
" /* Fill the core registers with known values. */ \n"
" mov r0, #100 \n"
" mov r1, #101 \n"
" mov r2, #102 \n"
" mov r3, #103 \n"
" mov r4, #104 \n"
" mov r5, #105 \n"
" mov r6, #106 \n"
" mov r7, #107 \n"
" mov r8, #108 \n"
" mov r9, #109 \n"
" mov r10, #110 \n"
" mov r11, #111 \n"
" mov r12, #112 \n"
" \n"
" /* Fill the VFP registers with known values. */ \n"
" vmov d0, r0, r1 \n"
" vmov d1, r2, r3 \n"
" vmov d2, r4, r5 \n"
" vmov d3, r6, r7 \n"
" vmov d4, r8, r9 \n"
" vmov d5, r10, r11 \n"
" vmov d6, r0, r1 \n"
" vmov d7, r2, r3 \n"
" vmov d8, r4, r5 \n"
" vmov d9, r6, r7 \n"
" vmov d10, r8, r9 \n"
" vmov d11, r10, r11 \n"
" vmov d12, r0, r1 \n"
" vmov d13, r2, r3 \n"
" vmov d14, r4, r5 \n"
" vmov d15, r6, r7 \n"
" \n"
"reg1_loop: \n"
" /* Check all the VFP registers still contain the values set above.\n"
" First save registers that are clobbered by the test. */ \n"
" push { r0-r1 } \n"
" \n"
" vmov r0, r1, d0 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d1 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d2 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d3 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d4 \n"
" cmp r0, #108 \n"
" bne reg1_error_loopf \n"
" cmp r1, #109 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d5 \n"
" cmp r0, #110 \n"
" bne reg1_error_loopf \n"
" cmp r1, #111 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d6 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d7 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d8 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d9 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d10 \n"
" cmp r0, #108 \n"
" bne reg1_error_loopf \n"
" cmp r1, #109 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d11 \n"
" cmp r0, #110 \n"
" bne reg1_error_loopf \n"
" cmp r1, #111 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d12 \n"
" cmp r0, #100 \n"
" bne reg1_error_loopf \n"
" cmp r1, #101 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d13 \n"
" cmp r0, #102 \n"
" bne reg1_error_loopf \n"
" cmp r1, #103 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d14 \n"
" cmp r0, #104 \n"
" bne reg1_error_loopf \n"
" cmp r1, #105 \n"
" bne reg1_error_loopf \n"
" vmov r0, r1, d15 \n"
" cmp r0, #106 \n"
" bne reg1_error_loopf \n"
" cmp r1, #107 \n"
" bne reg1_error_loopf \n"
" \n"
" /* Restore the registers that were clobbered by the test. */\n"
" pop {r0-r1} \n"
" \n"
" /* VFP register test passed. Jump to the core register test. */\n"
" b reg1_loopf_pass \n"
" \n"
"reg1_error_loopf: \n"
" /* If this line is hit then a VFP register value was found to be\n"
" incorrect. */ \n"
" b reg1_error_loopf \n"
" \n"
"reg1_loopf_pass: \n"
" \n"
" cmp r0, #100 \n"
" bne reg1_error_loop \n"
" cmp r1, #101 \n"
" bne reg1_error_loop \n"
" cmp r2, #102 \n"
" bne reg1_error_loop \n"
" cmp r3, #103 \n"
" bne reg1_error_loop \n"
" cmp r4, #104 \n"
" bne reg1_error_loop \n"
" cmp r5, #105 \n"
" bne reg1_error_loop \n"
" cmp r6, #106 \n"
" bne reg1_error_loop \n"
" cmp r7, #107 \n"
" bne reg1_error_loop \n"
" cmp r8, #108 \n"
" bne reg1_error_loop \n"
" cmp r9, #109 \n"
" bne reg1_error_loop \n"
" cmp r10, #110 \n"
" bne reg1_error_loop \n"
" cmp r11, #111 \n"
" bne reg1_error_loop \n"
" cmp r12, #112 \n"
" bne reg1_error_loop \n"
" \n"
" /* Everything passed, increment the loop counter. */ \n"
" push { r0-r1 } \n"
" ldr r0, =ulRegTest1LoopCounter \n"
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"
" b reg1_loop \n"
" \n"
"reg1_error_loop: \n"
" /* If this line is hit then there was an error in a core register value.\n"
" The loop ensures the loop counter stops incrementing. */\n"
" b reg1_error_loop \n"
" nop "
);
/* Remove compiler warnings about unused parameters. */
( void ) pvParameters;
}
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void prvRegTest2Task( void *pvParameters )
{
__asm volatile
(
" /* Set all the core registers to known values. */ \n"
" mov r0, #-1 \n"
" mov r1, #1 \n"
" mov r2, #2 \n"
" mov r3, #3 \n"
" mov r4, #4 \n"
" mov r5, #5 \n"
" mov r6, #6 \n"
" mov r7, #7 \n"
" mov r8, #8 \n"
" mov r9, #9 \n"
" mov r10, #10 \n"
" mov r11, #11 \n"
" mov r12, #12 \n"
" \n"
" /* Set all the VFP to known values. */ \n"
" vmov d0, r0, r1 \n"
" vmov d1, r2, r3 \n"
" vmov d2, r4, r5 \n"
" vmov d3, r6, r7 \n"
" vmov d4, r8, r9 \n"
" vmov d5, r10, r11 \n"
" vmov d6, r0, r1 \n"
" vmov d7, r2, r3 \n"
" vmov d8, r4, r5 \n"
" vmov d9, r6, r7 \n"
" vmov d10, r8, r9 \n"
" vmov d11, r10, r11 \n"
" vmov d12, r0, r1 \n"
" vmov d13, r2, r3 \n"
" vmov d14, r4, r5 \n"
" vmov d15, r6, r7 \n"
" \n"
"reg2_loop: \n"
" \n"
" /* Check all the VFP registers still contain the values set above.\n"
" First save registers that are clobbered by the test. */ \n"
" push { r0-r1 } \n"
" \n"
" vmov r0, r1, d0 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d1 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d2 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d3 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d4 \n"
" cmp r0, #8 \n"
" bne reg2_error_loopf \n"
" cmp r1, #9 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d5 \n"
" cmp r0, #10 \n"
" bne reg2_error_loopf \n"
" cmp r1, #11 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d6 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d7 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d8 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d9 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d10 \n"
" cmp r0, #8 \n"
" bne reg2_error_loopf \n"
" cmp r1, #9 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d11 \n"
" cmp r0, #10 \n"
" bne reg2_error_loopf \n"
" cmp r1, #11 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d12 \n"
" cmp r0, #-1 \n"
" bne reg2_error_loopf \n"
" cmp r1, #1 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d13 \n"
" cmp r0, #2 \n"
" bne reg2_error_loopf \n"
" cmp r1, #3 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d14 \n"
" cmp r0, #4 \n"
" bne reg2_error_loopf \n"
" cmp r1, #5 \n"
" bne reg2_error_loopf \n"
" vmov r0, r1, d15 \n"
" cmp r0, #6 \n"
" bne reg2_error_loopf \n"
" cmp r1, #7 \n"
" bne reg2_error_loopf \n"
" \n"
" /* Restore the registers that were clobbered by the test. */\n"
" pop {r0-r1} \n"
" \n"
" /* VFP register test passed. Jump to the core register test. */\n"
" b reg2_loopf_pass \n"
" \n"
"reg2_error_loopf: \n"
" /* If this line is hit then a VFP register value was found to be\n"
" incorrect. */ \n"
" b reg2_error_loopf \n"
" \n"
"reg2_loopf_pass: \n"
" \n"
" cmp r0, #-1 \n"
" bne reg2_error_loop \n"
" cmp r1, #1 \n"
" bne reg2_error_loop \n"
" cmp r2, #2 \n"
" bne reg2_error_loop \n"
" cmp r3, #3 \n"
" bne reg2_error_loop \n"
" cmp r4, #4 \n"
" bne reg2_error_loop \n"
" cmp r5, #5 \n"
" bne reg2_error_loop \n"
" cmp r6, #6 \n"
" bne reg2_error_loop \n"
" cmp r7, #7 \n"
" bne reg2_error_loop \n"
" cmp r8, #8 \n"
" bne reg2_error_loop \n"
" cmp r9, #9 \n"
" bne reg2_error_loop \n"
" cmp r10, #10 \n"
" bne reg2_error_loop \n"
" cmp r11, #11 \n"
" bne reg2_error_loop \n"
" cmp r12, #12 \n"
" bne reg2_error_loop \n"
" \n"
" /* Increment the loop counter to indicate this test is still functioning\n"
" correctly. */ \n"
" push { r0-r1 } \n"
" ldr r0, =ulRegTest2LoopCounter \n"
" ldr r1, [r0] \n"
" adds r1, r1, #1 \n"
" str r1, [r0] \n"
" \n"
" /* Yield to increase test coverage. */ \n"
" movs r0, #0x01 \n"
" ldr r1, =0xe000ed04 \n" /* NVIC_INT_CTRL */
" lsl r0, #28 \n" /* Shift to PendSV bit */
" str r0, [r1] \n"
" dsb \n"
" pop { r0-r1 } \n"
" \n"
" /* Start again. */ \n"
" b reg2_loop \n"
" \n"
"reg2_error_loop: \n"
" /* If this line is hit then there was an error in a core register value.\n"
" This loop ensures the loop counter variable stops incrementing. */\n"
" b reg2_error_loop \n"
" nop \n"
);
/* Remove compiler warnings about unused parameters. */
( void ) pvParameters;
}