mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
Merge branch 'main' into xmos_fix_freertos_port
This commit is contained in:
commit
fbc3a7a1e1
|
@ -65,6 +65,9 @@
|
|||
#define tskMPU_REGION_EXECUTE_NEVER ( 1U << 2U )
|
||||
#define tskMPU_REGION_NORMAL_MEMORY ( 1U << 3U )
|
||||
#define tskMPU_REGION_DEVICE_MEMORY ( 1U << 4U )
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
#define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* MPU region permissions stored in MPU settings to
|
||||
* authorize access requests. */
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,12 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory
|
||||
* region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if ( portARMV8M_MINOR_VERSION >= 1 )
|
||||
{
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
}
|
||||
#endif /* portARMV8M_MINOR_VERSION >= 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
2
portable/ThirdParty/GCC/RP2040/README.md
vendored
2
portable/ThirdParty/GCC/RP2040/README.md
vendored
|
@ -26,7 +26,7 @@ This will locate the FreeRTOS kernel if it is a direct sub-module of your projec
|
|||
version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the
|
||||
FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support.
|
||||
|
||||
As an alternative to the `import` statement above, you can just add this directory directly via thw following (with
|
||||
As an alternative to the `import` statement above, you can just add this directory directly via the following (with
|
||||
the same placement restrictions related to the Raspberry Pi Pico SDK version above):
|
||||
|
||||
```cmake
|
||||
|
|
Loading…
Reference in a new issue