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Update MSP432 projects to use updated driver library files.

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Remove references to INCLUDE_pcTaskGetTaskName and INCLUDE_xTimerGetTimerDaemonTaskHandle, which are no longer required.
This commit is contained in:
Richard Barry 2016-03-30 11:12:06 +00:00
parent b9b64c0889
commit f9c02d09c3
111 changed files with 16550 additions and 23297 deletions
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476
FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/RTOSDemo.cproj
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@ -2,7 +2,7 @@
<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">
<PropertyGroup>
<SchemaVersion>2.0</SchemaVersion>
<ProjectVersion>6.0</ProjectVersion>
<ProjectVersion>7.0</ProjectVersion>
<ProjectGuid>{4c68ca75-30f2-4325-8b61-35952638d586}</ProjectGuid>
<Name>$(MSBuildProjectName)</Name>
<AssemblyName>$(MSBuildProjectName)</AssemblyName>
@ -10,138 +10,142 @@
<AsfVersion>3.3.0</AsfVersion>
<AsfFrameworkConfig>
<framework-data>
<options>
<option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
<option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />
<option id="common.services.basic.clock" value="Add" config="" content-id="Atmel.ASF" />
<option id="sam.drivers.usart" value="Add" config="" content-id="Atmel.ASF" />
</options>
<configurations>
<configuration key="config.sam.pio.pio_handler" value="yes" default="yes" content-id="Atmel.ASF" />
</configurations>
<files>
<file path="src/asf.h" framework="" version="3.3.0" source="./common/applications/user_application/sam3sd8c_sam3s_ek2/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />
<file path="src/main.c" framework="" version="3.3.0" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />
<file path="src/config/conf_board.h" framework="" version="3.3.0" source="common/applications/user_application/sam3sd8c_sam3s_ek2/conf_board.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/boards/board.h" framework="" version="3.3.0" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/services/gpio/gpio.h" framework="" version="3.3.0" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" framework="" version="3.3.0" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/utils/interrupt.h" framework="" version="3.3.0" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/utils/parts.h" framework="" version="3.3.0" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/boards/sam3s_ek2/init.c" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/init.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/boards/sam3s_ek2/led.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/led.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/boards/sam3s_ek2/sam3s_ek2.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/sam3s_ek2.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/drivers/pio/pio.c" framework="" version="3.3.0" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/drivers/pio/pio.h" framework="" version="3.3.0" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/drivers/pio/pio_handler.c" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/drivers/pio/pio_handler.h" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pdc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pio.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_tc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_twi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_uart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_usart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3s8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3s8.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3sd8c.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/exceptions.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/exceptions.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.c" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/compiler.h" framework="" version="3.3.0" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/header_files/io.h" framework="" version="3.3.0" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld" framework="" version="3.3.0" source="sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/make/Makefile.in" framework="" version="3.3.0" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/preprocessor/mrepeat.h" framework="" version="3.3.0" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/preprocessor/preprocessor.h" framework="" version="3.3.0" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/preprocessor/stringz.h" framework="" version="3.3.0" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/preprocessor/tpaste.h" framework="" version="3.3.0" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/sam/utils/status_codes.h" framework="" version="3.3.0" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" framework="" version="3.3.0" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/thirdparty/CMSIS/Include/core_cm3.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cm3.h" changed="False" content-id="Atmel.ASF" />
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<file path="src/asf/common/services/clock/sam3s/genclk.h" framework="" version="" source="common\services\clock\sam3s\genclk.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/services/clock/sysclk.h" framework="" version="" source="common\services\clock\sysclk.h" changed="False" content-id="Atmel.ASF" />
<file path="src/asf/common/services/clock/pll.h" framework="" version="" source="common\services\clock\pll.h" changed="False" content-id="Atmel.ASF" />
<file path="src/config/conf_clock.h" framework="" version="" source="common\services\clock\sam3s\module_config\conf_clock.h" changed="False" content-id="Atmel.ASF" />
</files>
<documentation help="" />
<offline-documentation help="" />
<dependencies>
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.20.1" />
</dependencies>
</framework-data>
</AsfFrameworkConfig>
<avrdevice>ATSAM3SD8C</avrdevice>
<avrdeviceseries>sam3sd</avrdeviceseries>
<Language>C</Language>
<ToolchainName>com.Atmel.ARMGCC</ToolchainName>
<ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
<ArmGccProjectExtensions />
<OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
<OutputFileName>$(MSBuildProjectName)</OutputFileName>
@ -182,117 +186,105 @@
</InterfaceProperties>
</ToolOptions>
</com_atmel_avrdbg_tool_samice>
<CacheFlash>true</CacheFlash>
<ProgFlashFromRam>true</ProgFlashFromRam>
<RamSnippetAddress />
<UncachedRange />
<preserveEEPROM>true</preserveEEPROM>
<BootSegment>2</BootSegment>
</PropertyGroup>
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<ToolchainSettings>
<ArmGcc>
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@ -335,28 +327,6 @@
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@ -382,10 +352,6 @@
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<Compile Include="src\asf\thirdparty\FreeRTOS\include\croutine.h">

3
FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h
View file

@ -173,7 +173,7 @@ extern "C" {
#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
#define configTOTAL_HEAP_SIZE (( size_t )(25000))
#define configTOTAL_HEAP_SIZE (( size_t )(24000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
@ -237,7 +237,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
#define INCLUDE_pcTaskGetTaskName ( 0 )
#define INCLUDE_eTaskGetState ( 1 )
#define INCLUDE_xTimerPendFunctionCall ( 1 )

5
FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h
View file

@ -98,7 +98,7 @@ extern "C" {
* See the comments at the top of main.c, main_full.c and main_low_power.c for
* more information.
*/
#define configCREATE_LOW_POWER_DEMO 0
#define configCREATE_LOW_POWER_DEMO 1
/* Some configuration is dependent on the demo being built. */
#if( configCREATE_LOW_POWER_DEMO == 0 )
@ -150,7 +150,7 @@ extern "C" {
#define configCPU_CLOCK_HZ ( CMU_ClockFreqGet( cmuClock_CORE ) )
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
#define configTOTAL_HEAP_SIZE (( size_t )(25000))
#define configTOTAL_HEAP_SIZE (( size_t )(24000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
@ -214,7 +214,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
#define INCLUDE_pcTaskGetTaskName ( 0 )
#define INCLUDE_eTaskGetState ( 1 )
#define INCLUDE_xTimerPendFunctionCall ( 1 )

1
FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h
View file

@ -124,7 +124,6 @@ to exclude the API function. */
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1

8
FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj
View file

@ -2,7 +2,7 @@
<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">
<PropertyGroup>
<SchemaVersion>2.0</SchemaVersion>
<ProjectVersion>6.2</ProjectVersion>
<ProjectVersion>7.0</ProjectVersion>
<ProjectGuid>{257fe152-8d54-41ca-afe7-777de72fe329}</ProjectGuid>
<Name>$(MSBuildProjectName)</Name>
<AssemblyName>$(MSBuildProjectName)</AssemblyName>
@ -180,7 +180,7 @@
<documentation help="http://asf.atmel.com/docs/3.11.0/common.applications.user_application.sam4e_ek/html/index.html" />
<offline-documentation help="" />
<dependencies>
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.11.0" />
<content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.20.1" />
</dependencies>
<project id="common.applications.user_application.sam4e_ek" value="Add" config="" content-id="Atmel.ASF" />
<board id="board.sam4e_ek" value="Add" config="" content-id="Atmel.ASF" />
@ -219,6 +219,7 @@
<ToolName>J-Link</ToolName>
</com_atmel_avrdbg_tool_samice>
<avrtoolinterface>SWD</avrtoolinterface>
<preserveEEPROM>true</preserveEEPROM>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
<ToolchainSettings>
@ -380,12 +381,13 @@
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
<armgcc.compiler.optimization.level>Optimize (-O1)</armgcc.compiler.optimization.level>
<armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
<armgcc.compiler.warnings.ExtraWarnings>True</armgcc.compiler.warnings.ExtraWarnings>
<armgcc.compiler.miscellaneous.OtherFlags>-pipe -fno-strict-aliasing -Wall -Wextra -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.compiler.miscellaneous.OtherFlags>-pipe -fno-strict-aliasing -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4 -Wno-attributes -Wno-unused-function</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.linker.libraries.Libraries>
<ListValues>
<Value>m</Value>

14
FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h
View file

@ -153,12 +153,14 @@
* heuristics and inline the function no matter how big it thinks it
* becomes.
*/
#if defined(__CC_ARM)
# define __always_inline __forceinline
#elif (defined __GNUC__)
# define __always_inline inline __attribute__((__always_inline__))
#elif (defined __ICCARM__)
# define __always_inline _Pragma("inline=forced")
#ifndef __always_inline
#if defined(__CC_ARM)
# define __always_inline __forceinline
#elif (defined __GNUC__)
# define __always_inline inline __attribute__((__always_inline__))
#elif (defined __ICCARM__)
# define __always_inline _Pragma("inline=forced")
#endif
#endif
/*! \brief This macro is used to test fatal errors.

12
FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c
View file

@ -109,15 +109,15 @@ resolution and low resolution respectively. */
/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate
interrupts at a low frequency. The purpose being to bring the CPU out of its
sleep mode by an interrupt other than the tick interrupt, and therefore
allowing an additional past through the code to be tested. */
allowing an additional paths through the code to be tested. */
#define lpINCLUDE_TEST_TIMER 0
/* Some registers are accessed directly as the library is not compatible with
all the compilers used. */
#define lpHTIMER_PRELOAD_REGISTER ( * ( uint16_t * ) 0x40009800 )
#define lpHTIMER_CONTROL_REGISTER ( * ( uint16_t * ) 0x40009804 )
#define lpHTIMER_COUNT_REGISTER ( * ( uint16_t * ) 0x40009808 )
#define lpEC_GIRQ17_ENABLE_SET ( * ( uint32_t * ) 0x4000C0B8 )
#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )
#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )
#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )
#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )
#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )
/*
@ -378,7 +378,7 @@ TickType_t xModifiableIdleTime;
/* Undo the adjustment that was made to the reload value to account
for the fact that a time slice was part way through when this
function was called before working out how many complete tick
periods this represents. (could have used [ulExpectedIdleTime *
periods this represents. (could have used [ulExpectedIdleTime *
ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on
the previous line, but this way avoids the multiplication). */
ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep );

27
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
View file

@ -166,7 +166,7 @@
</matcher>
</filter>
<filter>
<id>1424443780710</id>
<id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -175,7 +175,7 @@
</matcher>
</filter>
<filter>
<id>1424443780715</id>
<id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -184,7 +184,7 @@
</matcher>
</filter>
<filter>
<id>1424443780721</id>
<id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -193,7 +193,7 @@
</matcher>
</filter>
<filter>
<id>1424443780726</id>
<id>1458999824895</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -202,7 +202,7 @@
</matcher>
</filter>
<filter>
<id>1424443780730</id>
<id>1458999824895</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -211,7 +211,7 @@
</matcher>
</filter>
<filter>
<id>1424443780734</id>
<id>1458999824905</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -220,7 +220,7 @@
</matcher>
</filter>
<filter>
<id>1424443780739</id>
<id>1458999824905</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -229,7 +229,7 @@
</matcher>
</filter>
<filter>
<id>1424443780744</id>
<id>1458999824915</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -238,7 +238,7 @@
</matcher>
</filter>
<filter>
<id>1424443780748</id>
<id>1458999824915</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@ -246,6 +246,15 @@
<arguments>1.0-name-matches-false-false-timer32.c</arguments>
</matcher>
</filter>
<filter>
<id>1458999824925</id>
<name>driverlib</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-sysctl.c</arguments>
</matcher>
</filter>
<filter>
<id>1423578948112</id>
<name>system</name>

1
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
View file

@ -124,7 +124,6 @@ referenced anyway. */
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0

20
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
View file

@ -104,17 +104,17 @@ void vT32_1_Handler( void );
void vInitialiseTimerForIntQueueTest( void )
{
/* Configure the timer channels. */
MAP_Timer32_initModule( TIMER32_0_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( TIMER32_0_MODULE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
MAP_Timer32_enableInterrupt( TIMER32_0_MODULE );
MAP_Timer32_startTimer( TIMER32_0_MODULE, false );
MAP_Timer32_initModule( (uint32_t)TIMER32_0_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( (uint32_t)TIMER32_0_BASE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_0_BASE );
MAP_Timer32_startTimer( (uint32_t)TIMER32_0_BASE, false );
MAP_Interrupt_setPriority( INT_T32_INT1, tmrLOWER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT1 );
MAP_Timer32_initModule( TIMER32_1_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( TIMER32_1_MODULE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
MAP_Timer32_enableInterrupt( TIMER32_1_MODULE );
MAP_Timer32_startTimer( TIMER32_1_MODULE, false );
MAP_Timer32_initModule( (uint32_t)TIMER32_1_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
MAP_Timer32_setCount( (uint32_t)TIMER32_1_BASE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_1_BASE );
MAP_Timer32_startTimer( (uint32_t)TIMER32_1_BASE, false );
MAP_Interrupt_setPriority( INT_T32_INT2, tmrHIGHER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT2 );
}
@ -122,14 +122,14 @@ void vInitialiseTimerForIntQueueTest( void )
void vT32_0_Handler( void )
{
MAP_Timer32_clearInterruptFlag( TIMER32_0_MODULE );
MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_0_BASE );
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
/*-----------------------------------------------------------*/
void vT32_1_Handler( void )
{
MAP_Timer32_clearInterruptFlag( TIMER32_1_MODULE );
MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_1_BASE );
portYIELD_FROM_ISR( xSecondTimerHandler() );
}

8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
View file

@ -68,7 +68,7 @@
*/
__asm vRegTest1Implementation( void )
__asm void vRegTest1Implementation( void )
{
PRESERVE8
IMPORT ulRegTest1LoopCounter
@ -251,7 +251,7 @@ reg1_error_loop
}
/*-----------------------------------------------------------*/
__asm vRegTest2Implementation( void )
__asm void vRegTest2Implementation( void )
{
PRESERVE8
IMPORT ulRegTest2LoopCounter
@ -443,7 +443,7 @@ reg2_error_loop
}
/*-----------------------------------------------------------*/
__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
__asm void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
{
PRESERVE8
@ -460,7 +460,7 @@ __asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
}
/*-----------------------------------------------------------*/
__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
__asm void ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
{
PRESERVE8

26
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
View file

@ -107,7 +107,7 @@ static QueueHandle_t xRxQueue = NULL;
static volatile const signed char *pcStringStart = NULL, *pcStringEnd = NULL;
static volatile TaskHandle_t xTransmittingTask = NULL;
static EUSCI_A0_Type * const pxUARTA0 = ( EUSCI_A0_Type * ) EUSCI_A0_MODULE;
static EUSCI_A_Type * const pxUARTA0 = ( EUSCI_A_Type * ) EUSCI_A0_BASE;
/* UART Configuration for 19200 baud. Value generated using the tool provided
on the following page:
@ -137,10 +137,10 @@ xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned long
configASSERT( xRxQueue );
/* Use the library functions to initialise and enable the UART. */
MAP_UART_initModule( EUSCI_A0_MODULE, &xUARTConfig );
MAP_UART_enableModule( EUSCI_A0_MODULE );
MAP_UART_clearInterruptFlag( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT );
MAP_UART_initModule( EUSCI_A0_BASE, &xUARTConfig );
MAP_UART_enableModule( EUSCI_A0_BASE );
MAP_UART_clearInterruptFlag( EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT );
/* The interrupt handler uses the FreeRTOS API function so its priority must
be at or below the configured maximum system call interrupt priority.
@ -191,11 +191,11 @@ const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL * ( uint32_t ) usStringLengt
pcStringEnd = pcStringStart + usStringLength;
/* Start to send the first byte. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcString;
pxUARTA0->TXBUF = ( uint_fast8_t ) *pcString;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
}
/*-----------------------------------------------------------*/
@ -223,11 +223,11 @@ const TickType_t xMaxWaitTime = pdMS_TO_TICKS( 20UL );
pcStringEnd = pcStringStart + sizeof( cOutChar );
/* Start to send the byte. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) cOutChar;
pxUARTA0->TXBUF = ( uint_fast8_t ) cOutChar;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
return pdPASS;
@ -247,12 +247,12 @@ uint8_t ucChar;
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
uint_fast8_t xInterruptStatus;
xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_MODULE );
xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_BASE );
if( ( xInterruptStatus & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG ) != 0x00 )
{
/* Obtain the character. */
ucChar = MAP_UART_receiveData( EUSCI_A0_MODULE );
ucChar = MAP_UART_receiveData( EUSCI_A0_BASE );
/* Send the character to the queue. Note the comments at the top of this
file with regards to the inefficiency of this method for anything other than
@ -277,13 +277,13 @@ uint_fast8_t xInterruptStatus;
/* This is probably quite a heavy wait function just for writing to
the Tx register. An optimised design would probably replace this
with a simple register write. */
pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcStringStart;
pxUARTA0->TXBUF = ( uint_fast8_t ) *pcStringStart;
}
else
{
/* No more characters to send. Disable the interrupt and notify the
task, if the task is waiting. */
MAP_UART_disableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
MAP_UART_disableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
if( xTransmittingTask != NULL )
{
vTaskNotifyGiveFromISR( xTransmittingTask, &xHigherPriorityTaskWoken );

510
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
View file

@ -12,7 +12,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>26</version>
<version>27</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -45,7 +45,7 @@
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\MSP432P401R.svd</state>
<state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\MSP432P401R.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@ -85,11 +85,11 @@
</option>
<option>
<name>OCDynDriverList</name>
<state>IJET_ID</state>
<state>CMSISDAP_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>7.40.1.8463</state>
<state>7.50.3.10745</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
@ -207,6 +207,10 @@
<name>OCMulticoreSlaveConfiguration</name>
<state></state>
</option>
<option>
<name>OCDownloadExtraImage</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
@ -1064,7 +1068,7 @@
<name>PEMICRO_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -1075,19 +1079,6 @@
<name>OCPEMicroAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCPEMicroInterfaceList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCPEMicroResetDelay</name>
<state></state>
</option>
<option>
<name>CCPEMicroJtagSpeed</name>
<state>#UNINITIALIZED#</state>
</option>
<option>
<name>CCJPEMicroShowSettings</name>
<state>0</state>
@ -1100,36 +1091,6 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCPEMicroUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCPEMicroSerialPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCJPEMicroTCPIPAutoScanNetwork</name>
<state>1</state>
</option>
<option>
<name>CCPEMicroTCPIP</name>
<state>10.0.0.1</state>
</option>
<option>
<name>CCPEMicroCommCmdLineProducer</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkInterfaceCmdLine</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1193,7 +1154,7 @@
<name>STLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<version>3</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -1225,6 +1186,71 @@
<name>CCSwoClockEdit</name>
<state>2000</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCSTLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkUpdateBreakpoints</name>
<state>_call_main</state>
</option>
<option>
<name>CCSTLinkCatchCORERESET</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchMMERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchNOCPERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchCHRERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchSTATERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchBUSERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchINTERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchHARDERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchDummy</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkUsbSerialNo</name>
<state></state>
</option>
<option>
<name>CCSTLinkUsbSerialNoSelect</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkJtagSpeedList</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1256,7 +1282,7 @@
<name>XDS100_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<version>4</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -1275,11 +1301,6 @@
<name>TIPackage</name>
<state>C:\ti\ccs_base</state>
</option>
<option>
<name>CCXds100InterfaceList</name>
<version>2</version>
<state>9</state>
</option>
<option>
<name>BoardFile</name>
<state>Browse to your board file</state>
@ -1292,6 +1313,129 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCXds100BreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCXds100DoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCXds100UpdateBreakpoints</name>
<state>_call_main</state>
</option>
<option>
<name>CCXds100CatchReset</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchData</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchCORERESET</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchMMERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchNOCPERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchCHRERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchSTATERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchBUSERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchINTERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchHARDERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchDummy</name>
<state>0</state>
</option>
<option>
<name>CCXds100CpuClockEdit</name>
<state>72.0</state>
</option>
<option>
<name>CCXds100SwoClockAuto</name>
<state>0</state>
</option>
<option>
<name>CCXds100SwoClockEdit</name>
<state>1000</state>
</option>
<option>
<name>CCXds100HWResetDelay</name>
<state>0</state>
</option>
<option>
<name>CCXds100ResetList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCXds100UsbSerialNo</name>
<state></state>
</option>
<option>
<name>CCXds100UsbSerialNoSelect</name>
<state>0</state>
</option>
<option>
<name>CCXds100JtagSpeedList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCXds100InterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCXds100InterfaceCmdLine</name>
<state>0</state>
</option>
<option>
<name>CCXds100ProbeList</name>
<version>0</version>
<state>4</state>
</option>
</data>
</settings>
<debuggerPlugins>
@ -1299,6 +1443,10 @@
<file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
@ -1379,7 +1527,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>26</version>
<version>27</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1574,6 +1722,10 @@
<name>OCMulticoreSlaveConfiguration</name>
<state></state>
</option>
<option>
<name>OCDownloadExtraImage</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
@ -2431,7 +2583,7 @@
<name>PEMICRO_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -2442,19 +2594,6 @@
<name>OCPEMicroAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCPEMicroInterfaceList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCPEMicroResetDelay</name>
<state></state>
</option>
<option>
<name>CCPEMicroJtagSpeed</name>
<state>#UNINITIALIZED#</state>
</option>
<option>
<name>CCJPEMicroShowSettings</name>
<state>0</state>
@ -2467,36 +2606,6 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCPEMicroUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCPEMicroSerialPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCJPEMicroTCPIPAutoScanNetwork</name>
<state>1</state>
</option>
<option>
<name>CCPEMicroTCPIP</name>
<state>10.0.0.1</state>
</option>
<option>
<name>CCPEMicroCommCmdLineProducer</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkInterfaceCmdLine</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -2560,7 +2669,7 @@
<name>STLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<version>3</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -2592,6 +2701,71 @@
<name>CCSwoClockEdit</name>
<state>2000</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCSTLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkUpdateBreakpoints</name>
<state>_call_main</state>
</option>
<option>
<name>CCSTLinkCatchCORERESET</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchMMERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchNOCPERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchCHRERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchSTATERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchBUSERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchINTERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchHARDERR</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkCatchDummy</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkUsbSerialNo</name>
<state></state>
</option>
<option>
<name>CCSTLinkUsbSerialNoSelect</name>
<state>0</state>
</option>
<option>
<name>CCSTLinkJtagSpeedList</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -2623,7 +2797,7 @@
<name>XDS100_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<version>4</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -2642,11 +2816,6 @@
<name>TIPackage</name>
<state></state>
</option>
<option>
<name>CCXds100InterfaceList</name>
<version>2</version>
<state>0</state>
</option>
<option>
<name>BoardFile</name>
<state></state>
@ -2659,6 +2828,129 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCXds100BreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCXds100DoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCXds100UpdateBreakpoints</name>
<state>_call_main</state>
</option>
<option>
<name>CCXds100CatchReset</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchData</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchCORERESET</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchMMERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchNOCPERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchCHRERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchSTATERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchBUSERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchINTERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchHARDERR</name>
<state>0</state>
</option>
<option>
<name>CCXds100CatchDummy</name>
<state>0</state>
</option>
<option>
<name>CCXds100CpuClockEdit</name>
<state>72.0</state>
</option>
<option>
<name>CCXds100SwoClockAuto</name>
<state>0</state>
</option>
<option>
<name>CCXds100SwoClockEdit</name>
<state>1000</state>
</option>
<option>
<name>CCXds100HWResetDelay</name>
<state>0</state>
</option>
<option>
<name>CCXds100ResetList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCXds100UsbSerialNo</name>
<state></state>
</option>
<option>
<name>CCXds100UsbSerialNoSelect</name>
<state>0</state>
</option>
<option>
<name>CCXds100JtagSpeedList</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCXds100InterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>CCXds100InterfaceCmdLine</name>
<state>0</state>
</option>
<option>
<name>CCXds100ProbeList</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<debuggerPlugins>
@ -2666,6 +2958,10 @@
<file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
<loadFlag>0</loadFlag>

124
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
View file

@ -12,7 +12,7 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>22</version>
<version>24</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -27,11 +27,6 @@
<name>ListPath</name>
<state>IAR_Debug\List</state>
</option>
<option>
<name>Variant</name>
<version>21</version>
<state>40</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
@ -58,11 +53,6 @@
<name>GOutputBinary</name>
<state>0</state>
</option>
<option>
<name>FPU</name>
<version>3</version>
<state>5</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
@ -87,7 +77,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>7.30.4.8186</state>
<state>7.50.3.10745</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@ -135,14 +125,9 @@
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GFPUCoreSlave</name>
<version>21</version>
<state>40</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>21</version>
<version>22</version>
<state>40</state>
</option>
<option>
@ -157,6 +142,34 @@
<name>GRuntimeLibThreads</name>
<state>0</state>
</option>
<option>
<name>CoreVariant</name>
<version>22</version>
<state>39</state>
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>MSP432P401R TexasInstruments MSP432P401R</state>
</option>
<option>
<name>FPU2</name>
<version>0</version>
<state>4</state>
</option>
<option>
<name>NrRegs</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>NEON</name>
<state>0</state>
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>22</version>
<state>39</state>
</option>
</data>
</settings>
<settings>
@ -594,7 +607,7 @@
<debug>1</debug>
<option>
<name>OOCOutputFormat</name>
<version>2</version>
<version>3</version>
<state>0</state>
</option>
<option>
@ -641,7 +654,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>16</version>
<version>17</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -722,7 +735,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$TOOLKIT_DIR$\config\linker\TexasInstruments\MSP432P401R.icf</state>
<state>$TOOLKIT_DIR$\config\linker\TexasInstruments\msp432p401r.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@ -925,6 +938,10 @@
<name>IlinkThreadsSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkLogCallGraph</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -964,7 +981,7 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>22</version>
<version>24</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -979,11 +996,6 @@
<name>ListPath</name>
<state>Release\List</state>
</option>
<option>
<name>Variant</name>
<version>21</version>
<state>0</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
@ -1010,11 +1022,6 @@
<name>GOutputBinary</name>
<state>0</state>
</option>
<option>
<name>FPU</name>
<version>3</version>
<state>0</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
@ -1039,7 +1046,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>6.30.1.53141</state>
<state>7.50.3.10745</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@ -1051,7 +1058,7 @@
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>TM4L2001H8PZI TexasInstruments TM4L2001H8PZI</state>
<state>Default None</state>
</option>
<option>
<name>GenLowLevelInterface</name>
@ -1087,14 +1094,9 @@
<name>RTConfigPath2</name>
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
<name>GFPUCoreSlave</name>
<version>21</version>
<state>0</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>21</version>
<version>22</version>
<state>0</state>
</option>
<option>
@ -1109,6 +1111,34 @@
<name>GRuntimeLibThreads</name>
<state>0</state>
</option>
<option>
<name>CoreVariant</name>
<version>22</version>
<state>0</state>
</option>
<option>
<name>GFPUDeviceSlave</name>
<state>Default None</state>
</option>
<option>
<name>FPU2</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>NrRegs</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>NEON</name>
<state>0</state>
</option>
<option>
<name>GFPUCoreSlave2</name>
<version>22</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1538,7 +1568,7 @@
<debug>0</debug>
<option>
<name>OOCOutputFormat</name>
<version>2</version>
<version>3</version>
<state>0</state>
</option>
<option>
@ -1585,7 +1615,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>16</version>
<version>17</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1869,6 +1899,10 @@
<name>IlinkThreadsSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkLogCallGraph</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1918,6 +1952,9 @@
<file>
<name>$PROJ_DIR$\driverlib\pcm.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\sysctl.c</name>
</file>
<file>
<name>$PROJ_DIR$\driverlib\timer32.c</name>
</file>
@ -2074,6 +2111,9 @@
<file>
<name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
</file>
<file>
<name>$PROJ_DIR$\system\IAR\system_msp432p401r.c</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\FreeRTOSConfig.h</name>

1932
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
View file

File diff suppressed because it is too large Load diff

93
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
View file

@ -73,11 +73,33 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>4</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>MSP432 Hardware Tools User's Guide (MSP-TS432PZ100)</Title>
<Path>http://www.ti.com/lit/pdf/slau571</Path>
</Book>
<Book>
<Number>1</Number>
<Title>MSP432 Quick Start Guide (MSP-EXP432P401R)</Title>
<Path>http://www.ti.com/lit/pdf/slau596</Path>
</Book>
<Book>
<Number>2</Number>
<Title>LaunchPad Development Kit User's Guide (MSP-EXP432P401R)</Title>
<Path>http://www.ti.com/lit/pdf/slau597</Path>
</Book>
<Book>
<Number>3</Number>
<Title>MSP432P401R LaunchPad Web page (MSP-EXP432P401R)</Title>
<Path>http://www.ti.com/tool/msp-exp432p401r</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@ -147,7 +169,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UM0149MEE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
<Name>-UM0356BUE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
@ -174,7 +196,7 @@
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
@ -199,6 +221,10 @@
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<Lin2Executable></Lin2Executable>
<Lin2ConfigFile></Lin2ConfigFile>
<bLin2Auto>0</bLin2Auto>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
@ -219,7 +245,6 @@
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\startup_MSP432P4.s</PathWithFileName>
@ -231,12 +256,11 @@
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<Focus>0</Focus>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\system_MSP432P4.c</PathWithFileName>
<FilenameWithoutPath>system_MSP432P4.c</FilenameWithoutPath>
<PathWithFileName>.\system\Keil\system_msp432p401r.c</PathWithFileName>
<FilenameWithoutPath>system_msp432p401r.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@ -244,7 +268,7 @@
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -253,7 +277,6 @@
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
@ -266,7 +289,6 @@
<FileNumber>4</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
@ -287,7 +309,6 @@
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\SimplyBlinkyDemo\main_blinky.c</PathWithFileName>
@ -308,7 +329,6 @@
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\event_groups.c</PathWithFileName>
@ -321,7 +341,6 @@
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\list.c</PathWithFileName>
@ -334,7 +353,6 @@
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\queue.c</PathWithFileName>
@ -347,7 +365,6 @@
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
@ -360,7 +377,6 @@
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\timers.c</PathWithFileName>
@ -373,7 +389,6 @@
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\MemMang\heap_4.c</PathWithFileName>
@ -386,7 +401,6 @@
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName>
@ -407,7 +421,6 @@
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\main_full.c</PathWithFileName>
@ -420,7 +433,6 @@
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RunTimeStatsTimer.c</PathWithFileName>
@ -433,7 +445,6 @@
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\serial.c</PathWithFileName>
@ -446,7 +457,6 @@
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName>
@ -459,7 +469,6 @@
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\countsem.c</PathWithFileName>
@ -472,7 +481,6 @@
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\EventGroupsDemo.c</PathWithFileName>
@ -485,7 +493,6 @@
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\GenQTest.c</PathWithFileName>
@ -498,7 +505,6 @@
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntSemTest.c</PathWithFileName>
@ -511,7 +517,6 @@
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\recmutex.c</PathWithFileName>
@ -524,7 +529,6 @@
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName>
@ -537,7 +541,6 @@
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\sp_flop.c</PathWithFileName>
@ -550,7 +553,6 @@
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TaskNotify.c</PathWithFileName>
@ -563,7 +565,6 @@
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TimerDemo.c</PathWithFileName>
@ -576,7 +577,6 @@
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</PathWithFileName>
@ -589,7 +589,6 @@
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</PathWithFileName>
@ -602,7 +601,6 @@
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</PathWithFileName>
@ -615,7 +613,6 @@
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RegTest.c</PathWithFileName>
@ -628,7 +625,6 @@
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\IntQueueTimer.c</PathWithFileName>
@ -641,7 +637,6 @@
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntQueue.c</PathWithFileName>
@ -662,7 +657,6 @@
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cpu.c</PathWithFileName>
@ -675,7 +669,6 @@
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cs.c</PathWithFileName>
@ -688,7 +681,6 @@
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\gpio.c</PathWithFileName>
@ -701,7 +693,6 @@
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\interrupt.c</PathWithFileName>
@ -714,7 +705,6 @@
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\pcm.c</PathWithFileName>
@ -727,7 +717,6 @@
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\uart.c</PathWithFileName>
@ -740,7 +729,6 @@
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\wdt_a.c</PathWithFileName>
@ -753,7 +741,6 @@
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\sysctl.c</PathWithFileName>
@ -766,7 +753,6 @@
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\fpu.c</PathWithFileName>
@ -779,7 +765,6 @@
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\timer32.c</PathWithFileName>
@ -787,6 +772,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\rtc_c.c</PathWithFileName>
<FilenameWithoutPath>rtc_c.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>

67
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
View file

@ -10,11 +10,13 @@
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>MSP432P401R</Device>
<Vendor>Texas Instruments</Vendor>
<PackID>TI.MSP432.1.0.0</PackID>
<PackID>TexasInstruments.MSP432.1.0.3</PackID>
<PackURL>http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/mspkeil/latest/exports</PackURL>
<Cpu>IROM(0x00000000,0x00040000) IROM2(0x00200000,0x00004000) IRAM(0x20000000,0x00010000) IRAM2(0x01000000,0x00010000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -83,6 +85,8 @@
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
@ -121,47 +125,6 @@
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
@ -226,6 +189,7 @@
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
@ -358,13 +322,17 @@
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<VariousControls>
<MiscControls></MiscControls>
<Define>keil __MSP432P401R__</Define>
<Define>keil __MSP432P401R__ NO_MSP_CLASSIC_DEFINES</Define>
<Undefine></Undefine>
<IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F</IncludePath>
<IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;.\driverlib\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -413,9 +381,9 @@
<FilePath>.\system\Keil\startup_MSP432P4.s</FilePath>
</File>
<File>
<FileName>system_MSP432P4.c</FileName>
<FileName>system_msp432p401r.c</FileName>
<FileType>1</FileType>
<FilePath>.\system\Keil\system_MSP432P4.c</FilePath>
<FilePath>.\system\Keil\system_msp432p401r.c</FilePath>
</File>
</Files>
</Group>
@ -637,6 +605,11 @@
<FileType>1</FileType>
<FilePath>.\driverlib\timer32.c</FilePath>
</File>
<File>
<FileName>rtc_c.c</FileName>
<FileType>1</FileType>
<FilePath>.\driverlib\rtc_c.c</FilePath>
</File>
</Files>
</Group>
<Group>

181
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,16 +45,16 @@
/* Statics */
static volatile uint32_t* const _ctlRegs[32] =
{ &ADC14->rMCTL0.r, &ADC14->rMCTL1.r, &ADC14->rMCTL2.r, &ADC14->rMCTL3.r,
&ADC14->rMCTL4.r, &ADC14->rMCTL5.r, &ADC14->rMCTL6.r, &ADC14->rMCTL7.r,
&ADC14->rMCTL8.r, &ADC14->rMCTL9.r, &ADC14->rMCTL10.r,
&ADC14->rMCTL11.r, &ADC14->rMCTL12.r, &ADC14->rMCTL13.r,
&ADC14->rMCTL14.r, &ADC14->rMCTL15.r, &ADC14->rMCTL16.r,
&ADC14->rMCTL17.r, &ADC14->rMCTL18.r, &ADC14->rMCTL19.r,
&ADC14->rMCTL20.r, &ADC14->rMCTL21.r, &ADC14->rMCTL22.r,
&ADC14->rMCTL23.r, &ADC14->rMCTL24.r, &ADC14->rMCTL25.r,
&ADC14->rMCTL26.r, &ADC14->rMCTL27.r, &ADC14->rMCTL28.r,
&ADC14->rMCTL29.r, &ADC14->rMCTL30.r, &ADC14->rMCTL31.r };
{ &ADC14->MCTL[0], &ADC14->MCTL[1], &ADC14->MCTL[2], &ADC14->MCTL[3],
&ADC14->MCTL[4], &ADC14->MCTL[5], &ADC14->MCTL[6], &ADC14->MCTL[7],
&ADC14->MCTL[8], &ADC14->MCTL[9], &ADC14->MCTL[10],
&ADC14->MCTL[11], &ADC14->MCTL[12], &ADC14->MCTL[13],
&ADC14->MCTL[14], &ADC14->MCTL[15], &ADC14->MCTL[16],
&ADC14->MCTL[17], &ADC14->MCTL[18], &ADC14->MCTL[19],
&ADC14->MCTL[20], &ADC14->MCTL[21], &ADC14->MCTL[22],
&ADC14->MCTL[23], &ADC14->MCTL[24], &ADC14->MCTL[25],
&ADC14->MCTL[26], &ADC14->MCTL[27], &ADC14->MCTL[28],
&ADC14->MCTL[29], &ADC14->MCTL[30], &ADC14->MCTL[31] };
static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
{
@ -145,12 +145,12 @@ static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
//*****************************************************************************
static bool ADCIsConversionRunning(void)
{
return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
}
void ADC14_enableModule(void)
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 1;
}
bool ADC14_disableModule(void)
@ -158,7 +158,7 @@ bool ADC14_disableModule(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 0;
return true;
}
@ -168,14 +168,14 @@ bool ADC14_enableSampleTimer(uint32_t multiSampleConvert)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 1;
if (multiSampleConvert == ADC_MANUAL_ITERATION)
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 0;
} else
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 1;
}
return true;
@ -186,7 +186,7 @@ bool ADC14_disableSampleTimer(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 0;
return true;
}
@ -225,11 +225,11 @@ bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider,
if (ADCIsConversionRunning())
return false;
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14PDIV_M | ADC14DIV_M | ADC14SSEL_M))
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_PDIV_MASK | ADC14_CTL0_DIV_MASK | ADC14_CTL0_SSEL_MASK))
| clockDivider | clockPredivider | clockSource;
ADC14->rCTL1.r = (ADC14->rCTL1.r
ADC14->CTL1 = (ADC14->CTL1
& ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0
| ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask;
@ -242,12 +242,12 @@ void ADC14_setResolution(uint32_t resolution)
resolution == ADC_8BIT || resolution == ADC_10BIT
|| resolution == ADC_12BIT || resolution == ADC_14BIT);
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~ADC14RES_M) | resolution;
ADC14->CTL1 = (ADC14->CTL1 & ~ADC14_CTL1_RES_MASK) | resolution;
}
uint_fast32_t ADC14_getResolution(void)
{
return ADC14->rCTL1.r & ADC14RES_M;
return ADC14->CTL1 & ADC14_CTL1_RES_MASK;
}
bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
@ -267,13 +267,13 @@ bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
if (invertSignal)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14ISSH | ADC14SHS_M)) | source
| ADC14ISSH;
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source
| ADC14_CTL0_ISSH;
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14ISSH | ADC14SHS_M)) | source;
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source;
}
return true;
@ -305,8 +305,8 @@ bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth,
if (ADCIsConversionRunning())
return false;
ADC14->rCTL0.r = (ADC14->rCTL0.r
& ~(ADC14SHT0_M | ADC14SHT1_M)) | secondPulseWidth
ADC14->CTL0 = (ADC14->CTL0
& ~(ADC14_CTL0_SHT0_MASK | ADC14_CTL0_SHT1_MASK)) | secondPulseWidth
| (firstPulseWidth >> 4);
return true;
@ -327,26 +327,26 @@ bool repeatMode)
/* Clearing out any lingering EOS */
for (ii = 0; ii < 32; ii++)
{
BITBAND_PERI(*(_ctlRegs[ii]), ADC14EOS_OFS) = 0;
BITBAND_PERI(*(_ctlRegs[ii]), ADC14_MCTLN_EOS_OFS) = 0;
}
/* Setting Start/Stop locations */
BITBAND_PERI(
(*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
ADC14EOS_OFS) = 1;
ADC14_MCTLN_EOS_OFS) = 1;
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryStart) << 16);
/* Setting multiple sample mode */
if (!repeatMode)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_1);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_1);
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_3);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_3);
}
return true;
@ -361,18 +361,18 @@ bool repeatMode)
return false;
/* Setting the destination register */
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryDestination) << 16);
/* Setting single sample mode */
if (!repeatMode)
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_0);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_0);
} else
{
ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
| (ADC14CONSEQ_2);
ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
| (ADC14_CTL0_CONSEQ_2);
}
return true;
@ -380,25 +380,25 @@ bool repeatMode)
bool ADC14_enableConversion(void)
{
if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
return false;
ADC14->rCTL0.r |= (ADC14ENC);
ADC14->CTL0 |= (ADC14_CTL0_ENC);
return true;
}
bool ADC14_toggleConversionTrigger(void)
{
if (!BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
if (!BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
return false;
if (BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS))
if (BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS))
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 0;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 0;
} else
{
BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 1;
BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 1;
}
return true;
@ -406,12 +406,12 @@ bool ADC14_toggleConversionTrigger(void)
void ADC14_disableConversion(void)
{
ADC14->rCTL0.r &= ~(ADC14SC | ADC14ENC);
ADC14->CTL0 &= ~(ADC14_CTL0_SC | ADC14_CTL0_ENC);
}
bool ADC14_isBusy(void)
{
return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
}
bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
@ -444,14 +444,14 @@ bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
if (differntialMode)
{
(*curReg) = ((*curReg)
& ~(ADC14VRSEL_M | ADC14INCH_M
| ADC14DIF))
| (channelSelect | refSelect | ADC14DIF);
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF))
| (channelSelect | refSelect | ADC14_MCTLN_DIF);
} else
{
(*curReg) = ((*curReg)
& ~(ADC14VRSEL_M | ADC14INCH_M
| ADC14DIF)) | (channelSelect | refSelect);
& ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
| ADC14_MCTLN_DIF)) | (channelSelect | refSelect);
}
}
@ -489,11 +489,11 @@ bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect)
if (windowSelect == ADC_COMP_WINDOW0)
{
(*curRegPoint) = ((*curRegPoint)
& ~(ADC14WINC | ADC14WINCTH))
| (ADC14WINC);
& ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH))
| (ADC14_MCTLN_WINC);
} else if (windowSelect == ADC_COMP_WINDOW1)
{
(*curRegPoint) |= ADC14WINC | ADC14WINCTH;
(*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH;
}
}
@ -525,7 +525,7 @@ bool ADC14_disableComparatorWindow(uint32_t memorySelect)
ii = ii << 1;
(*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &=
~ADC14WINC;
~ADC14_MCTLN_WINC;
}
@ -536,20 +536,27 @@ bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high)
{
if (ADCIsConversionRunning())
return false;
if(BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS))
{
low = ((low << 2) | (0x8000 & low)) & 0xFFFC;
high = ((high << 2) | (0x8000 & high)) & 0xFFFC;
}
if (window == ADC_COMP_WINDOW0)
{
ADC14->rHI0.r = (high);
ADC14->rLO0.r = (low);
ADC14->HI0 = (high);
ADC14->LO0 = (low);
} else if (window == ADC_COMP_WINDOW1)
{
ADC14->rHI1.r = (high);
ADC14->rLO1.r = (low);
ADC14->HI1 = (high);
ADC14->LO1 = (low);
} else
{
ASSERT(false);
return false;
}
return true;
@ -562,10 +569,10 @@ bool ADC14_setResultFormat(uint32_t resultFormat)
if (resultFormat == ADC_UNSIGNED_BINARY)
{
BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 0;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 0;
} else if (resultFormat == ADC_SIGNED_BINARY)
{
BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 1;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 1;
} else
{
ASSERT(false);
@ -577,7 +584,7 @@ bool ADC14_setResultFormat(uint32_t resultFormat)
uint_fast16_t ADC14_getResult(uint32_t memorySelect)
{
return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
+ 0x80));
+ 0x20));
}
void ADC14_getMultiSequenceResult(uint16_t* res)
@ -585,16 +592,16 @@ void ADC14_getMultiSequenceResult(uint16_t* res)
uint32_t *startAddr, *curAddr;
uint32_t ii;
startAddr = (uint32_t*) _ctlRegs[(ADC14->rCTL1.r & ADC14CSTARTADD_M)
startAddr = (uint32_t*) _ctlRegs[(ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK)
>> 16];
curAddr = startAddr;
for (ii = 0; ii < 32; ii++)
{
res[ii] = *(((uint16_t*) curAddr) + 0x80);
res[ii] = *(((uint16_t*) curAddr) + 0x40);
if (BITBAND_PERI((*curAddr), ADC14EOS_OFS))
if (BITBAND_PERI((*curAddr), ADC14_MCTLN_EOS_OFS))
break;
if (curAddr == _ctlRegs[31])
@ -627,7 +634,7 @@ void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
foundEnd = true;
}
res[ii] = *(((uint16_t*) firstPoint) + 0x80);
res[ii] = *(((uint16_t*) firstPoint) + 0x40);
if (firstPoint == _ctlRegs[31])
firstPoint = (uint32_t*) _ctlRegs[0];
@ -641,7 +648,7 @@ bool ADC14_enableReferenceBurst(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 1;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 1;
return true;
}
@ -651,7 +658,7 @@ bool ADC14_disableReferenceBurst(void)
if (ADCIsConversionRunning())
return false;
BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 0;
BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 0;
return true;
}
@ -664,12 +671,12 @@ bool ADC14_setPowerMode(uint32_t adcPowerMode)
switch (adcPowerMode)
{
case ADC_UNRESTRICTED_POWER_MODE:
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
| (ADC14PWRMD_0);
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
| (ADC14_CTL1_PWRMD_0);
break;
case ADC_ULTRA_LOW_POWER_MODE:
ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
| (ADC14PWRMD_2);
ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
| (ADC14_CTL1_PWRMD_2);
break;
default:
ASSERT(false);
@ -683,31 +690,31 @@ void ADC14_enableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rIER0.r |= stat;
ADC14->IER0 |= stat;
stat = (mask >> 32);
ADC14->rIER1.r |= (stat);
ADC14->IER1 |= (stat);
}
void ADC14_disableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rIER0.r &= ~stat;
ADC14->IER0 &= ~stat;
stat = (mask >> 32);
ADC14->rIER1.r &= ~(stat);
ADC14->IER1 &= ~(stat);
}
uint_fast64_t ADC14_getInterruptStatus(void)
{
uint_fast64_t status = ADC14->rIFGR1.r;
return ((status << 32) | ADC14->rIFGR0.r);
uint_fast64_t status = ADC14->IFGR1;
return ((status << 32) | ADC14->IFGR0);
}
uint_fast64_t ADC14_getEnabledInterruptStatus(void)
{
uint_fast64_t stat = ADC14->rIER1.r;
uint_fast64_t stat = ADC14->IER1;
return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->rIER0.r);
return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->IER0);
}
@ -715,9 +722,9 @@ void ADC14_clearInterruptFlag(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
ADC14->rCLRIFGR0.r |= stat;
ADC14->CLRIFGR0 |= stat;
stat = (mask >> 32);
ADC14->rCLRIFGR1.r |= (stat);
ADC14->CLRIFGR1 |= (stat);
}
void ADC14_registerInterrupt(void (*intHandler)(void))

243
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -71,57 +71,57 @@ extern "C"
//The following are values that can be passed to ADC14_initModule
//
//*****************************************************************************
#define ADC_CLOCKSOURCE_ADCOSC (ADC14SSEL_0)
#define ADC_CLOCKSOURCE_SYSOSC (ADC14SSEL_1)
#define ADC_CLOCKSOURCE_ACLK (ADC14SSEL_2)
#define ADC_CLOCKSOURCE_MCLK (ADC14SSEL_3)
#define ADC_CLOCKSOURCE_SMCLK (ADC14SSEL_4)
#define ADC_CLOCKSOURCE_HSMCLK (ADC14SSEL_5)
#define ADC_CLOCKSOURCE_ADCOSC (ADC14_CTL0_SSEL_0)
#define ADC_CLOCKSOURCE_SYSOSC (ADC14_CTL0_SSEL_1)
#define ADC_CLOCKSOURCE_ACLK (ADC14_CTL0_SSEL_2)
#define ADC_CLOCKSOURCE_MCLK (ADC14_CTL0_SSEL_3)
#define ADC_CLOCKSOURCE_SMCLK (ADC14_CTL0_SSEL_4)
#define ADC_CLOCKSOURCE_HSMCLK (ADC14_CTL0_SSEL_5)
#define ADC_PREDIVIDER_1 (ADC14PDIV_0)
#define ADC_PREDIVIDER_4 (ADC14PDIV_1)
#define ADC_PREDIVIDER_32 (ADC14PDIV_2)
#define ADC_PREDIVIDER_64 (ADC14PDIV_3)
#define ADC_PREDIVIDER_1 (ADC14_CTL0_PDIV_0)
#define ADC_PREDIVIDER_4 (ADC14_CTL0_PDIV_1)
#define ADC_PREDIVIDER_32 (ADC14_CTL0_PDIV_2)
#define ADC_PREDIVIDER_64 (ADC14_CTL0_PDIV_3)
#define ADC_DIVIDER_1 (ADC14DIV_0)
#define ADC_DIVIDER_2 (ADC14DIV_1)
#define ADC_DIVIDER_3 (ADC14DIV_2)
#define ADC_DIVIDER_4 (ADC14DIV_3)
#define ADC_DIVIDER_5 (ADC14DIV_4)
#define ADC_DIVIDER_6 (ADC14DIV_5)
#define ADC_DIVIDER_7 (ADC14DIV_6)
#define ADC_DIVIDER_8 (ADC14DIV_7)
#define ADC_DIVIDER_1 (ADC14_CTL0_DIV_0)
#define ADC_DIVIDER_2 (ADC14_CTL0_DIV_1)
#define ADC_DIVIDER_3 (ADC14_CTL0_DIV_2)
#define ADC_DIVIDER_4 (ADC14_CTL0_DIV_3)
#define ADC_DIVIDER_5 (ADC14_CTL0_DIV_4)
#define ADC_DIVIDER_6 (ADC14_CTL0_DIV_5)
#define ADC_DIVIDER_7 (ADC14_CTL0_DIV_6)
#define ADC_DIVIDER_8 (ADC14_CTL0_DIV_7)
#define ADC_MAPINTCH3 (ADC14CH3MAP)
#define ADC_MAPINTCH2 (ADC14CH2MAP)
#define ADC_MAPINTCH1 (ADC14CH1MAP)
#define ADC_MAPINTCH0 (ADC14CH0MAP)
#define ADC_TEMPSENSEMAP (ADC14TCMAP)
#define ADC_BATTMAP (ADC14BATMAP)
#define ADC_MAPINTCH3 (ADC14_CTL1_CH3MAP)
#define ADC_MAPINTCH2 (ADC14_CTL1_CH2MAP)
#define ADC_MAPINTCH1 (ADC14_CTL1_CH1MAP)
#define ADC_MAPINTCH0 (ADC14_CTL1_CH0MAP)
#define ADC_TEMPSENSEMAP (ADC14_CTL1_TCMAP)
#define ADC_BATTMAP (ADC14_CTL1_BATMAP)
#define ADC_NOROUTE 0
#define ADC_8BIT ADC14RES_0
#define ADC_10BIT ADC14RES_1
#define ADC_12BIT ADC14RES_2
#define ADC_14BIT ADC14RES_3
#define ADC_8BIT ADC14_CTL1_RES_0
#define ADC_10BIT ADC14_CTL1_RES_1
#define ADC_12BIT ADC14_CTL1_RES_2
#define ADC_14BIT ADC14_CTL1_RES_3
#define ADC_TRIGGER_ADCSC ADC14SHS_0
#define ADC_TRIGGER_SOURCE1 ADC14SHS_1
#define ADC_TRIGGER_SOURCE2 ADC14SHS_2
#define ADC_TRIGGER_SOURCE3 ADC14SHS_3
#define ADC_TRIGGER_SOURCE4 ADC14SHS_4
#define ADC_TRIGGER_SOURCE5 ADC14SHS_5
#define ADC_TRIGGER_SOURCE6 ADC14SHS_6
#define ADC_TRIGGER_SOURCE7 ADC14SHS_7
#define ADC_TRIGGER_ADCSC ADC14_CTL0_SHS_0
#define ADC_TRIGGER_SOURCE1 ADC14_CTL0_SHS_1
#define ADC_TRIGGER_SOURCE2 ADC14_CTL0_SHS_2
#define ADC_TRIGGER_SOURCE3 ADC14_CTL0_SHS_3
#define ADC_TRIGGER_SOURCE4 ADC14_CTL0_SHS_4
#define ADC_TRIGGER_SOURCE5 ADC14_CTL0_SHS_5
#define ADC_TRIGGER_SOURCE6 ADC14_CTL0_SHS_6
#define ADC_TRIGGER_SOURCE7 ADC14_CTL0_SHS_7
#define ADC_PULSE_WIDTH_4 ADC14SHT1_0
#define ADC_PULSE_WIDTH_8 ADC14SHT1_1
#define ADC_PULSE_WIDTH_16 ADC14SHT1_2
#define ADC_PULSE_WIDTH_32 ADC14SHT1_3
#define ADC_PULSE_WIDTH_64 ADC14SHT1_4
#define ADC_PULSE_WIDTH_96 ADC14SHT1_5
#define ADC_PULSE_WIDTH_128 ADC14SHT1_6
#define ADC_PULSE_WIDTH_192 ADC14SHT1_7
#define ADC_PULSE_WIDTH_4 ADC14_CTL0_SHT1_0
#define ADC_PULSE_WIDTH_8 ADC14_CTL0_SHT1_1
#define ADC_PULSE_WIDTH_16 ADC14_CTL0_SHT1_2
#define ADC_PULSE_WIDTH_32 ADC14_CTL0_SHT1_3
#define ADC_PULSE_WIDTH_64 ADC14_CTL0_SHT1_4
#define ADC_PULSE_WIDTH_96 ADC14_CTL0_SHT1_5
#define ADC_PULSE_WIDTH_128 ADC14_CTL0_SHT1_6
#define ADC_PULSE_WIDTH_192 ADC14_CTL0_SHT1_7
#define ADC_NONDIFFERENTIAL_INPUTS false
#define ADC_DIFFERENTIAL_INPUTS true
@ -159,43 +159,43 @@ extern "C"
#define ADC_MEM30 0x40000000
#define ADC_MEM31 0x80000000
#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14VRSEL_0)
#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14VRSEL_1)
#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14VRSEL_14)
#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14VRSEL_15)
#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14_MCTLN_VRSEL_0)
#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14_MCTLN_VRSEL_1)
#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_14)
#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_15)
#define ADC_INPUT_A0 (ADC14INCH_0)
#define ADC_INPUT_A1 (ADC14INCH_1)
#define ADC_INPUT_A2 (ADC14INCH_2)
#define ADC_INPUT_A3 (ADC14INCH_3)
#define ADC_INPUT_A4 (ADC14INCH_4)
#define ADC_INPUT_A5 (ADC14INCH_5)
#define ADC_INPUT_A6 (ADC14INCH_6)
#define ADC_INPUT_A7 (ADC14INCH_7)
#define ADC_INPUT_A8 (ADC14INCH_8)
#define ADC_INPUT_A9 (ADC14INCH_9)
#define ADC_INPUT_A10 (ADC14INCH_10)
#define ADC_INPUT_A11 (ADC14INCH_11)
#define ADC_INPUT_A12 (ADC14INCH_12)
#define ADC_INPUT_A13 (ADC14INCH_13)
#define ADC_INPUT_A14 (ADC14INCH_14)
#define ADC_INPUT_A15 (ADC14INCH_15)
#define ADC_INPUT_A16 (ADC14INCH_16)
#define ADC_INPUT_A17 (ADC14INCH_17)
#define ADC_INPUT_A18 (ADC14INCH_18)
#define ADC_INPUT_A19 (ADC14INCH_19)
#define ADC_INPUT_A20 (ADC14INCH_20)
#define ADC_INPUT_A21 (ADC14INCH_21)
#define ADC_INPUT_A22 (ADC14INCH_22)
#define ADC_INPUT_A23 (ADC14INCH_23)
#define ADC_INPUT_A24 (ADC14INCH_24)
#define ADC_INPUT_A25 (ADC14INCH_25)
#define ADC_INPUT_A26 (ADC14INCH_26)
#define ADC_INPUT_A27 (ADC14INCH_27)
#define ADC_INPUT_A28 (ADC14INCH_28)
#define ADC_INPUT_A29 (ADC14INCH_29)
#define ADC_INPUT_A30 (ADC14INCH_30)
#define ADC_INPUT_A31 (ADC14INCH_31)
#define ADC_INPUT_A0 (ADC14_MCTLN_INCH_0)
#define ADC_INPUT_A1 (ADC14_MCTLN_INCH_1)
#define ADC_INPUT_A2 (ADC14_MCTLN_INCH_2)
#define ADC_INPUT_A3 (ADC14_MCTLN_INCH_3)
#define ADC_INPUT_A4 (ADC14_MCTLN_INCH_4)
#define ADC_INPUT_A5 (ADC14_MCTLN_INCH_5)
#define ADC_INPUT_A6 (ADC14_MCTLN_INCH_6)
#define ADC_INPUT_A7 (ADC14_MCTLN_INCH_7)
#define ADC_INPUT_A8 (ADC14_MCTLN_INCH_8)
#define ADC_INPUT_A9 (ADC14_MCTLN_INCH_9)
#define ADC_INPUT_A10 (ADC14_MCTLN_INCH_10)
#define ADC_INPUT_A11 (ADC14_MCTLN_INCH_11)
#define ADC_INPUT_A12 (ADC14_MCTLN_INCH_12)
#define ADC_INPUT_A13 (ADC14_MCTLN_INCH_13)
#define ADC_INPUT_A14 (ADC14_MCTLN_INCH_14)
#define ADC_INPUT_A15 (ADC14_MCTLN_INCH_15)
#define ADC_INPUT_A16 (ADC14_MCTLN_INCH_16)
#define ADC_INPUT_A17 (ADC14_MCTLN_INCH_17)
#define ADC_INPUT_A18 (ADC14_MCTLN_INCH_18)
#define ADC_INPUT_A19 (ADC14_MCTLN_INCH_19)
#define ADC_INPUT_A20 (ADC14_MCTLN_INCH_20)
#define ADC_INPUT_A21 (ADC14_MCTLN_INCH_21)
#define ADC_INPUT_A22 (ADC14_MCTLN_INCH_22)
#define ADC_INPUT_A23 (ADC14_MCTLN_INCH_23)
#define ADC_INPUT_A24 (ADC14_MCTLN_INCH_24)
#define ADC_INPUT_A25 (ADC14_MCTLN_INCH_25)
#define ADC_INPUT_A26 (ADC14_MCTLN_INCH_26)
#define ADC_INPUT_A27 (ADC14_MCTLN_INCH_27)
#define ADC_INPUT_A28 (ADC14_MCTLN_INCH_28)
#define ADC_INPUT_A29 (ADC14_MCTLN_INCH_29)
#define ADC_INPUT_A30 (ADC14_MCTLN_INCH_30)
#define ADC_INPUT_A31 (ADC14_MCTLN_INCH_31)
#define ADC_COMP_WINDOW0 0x00
#define ADC_COMP_WINDOW1 0x01
@ -204,44 +204,44 @@ extern "C"
#define ADC_UNSIGNED_BINARY 0x01
#define ADC_MANUAL_ITERATION 0x00
#define ADC_AUTOMATIC_ITERATION ADC14MSC
#define ADC_AUTOMATIC_ITERATION ADC14_CTL0_MSC
#define ADC_UNRESTRICTED_POWER_MODE ADC14PWRMD_0
#define ADC_ULTRA_LOW_POWER_MODE ADC14PWRMD_2
#define ADC_UNRESTRICTED_POWER_MODE ADC14_CTL1_PWRMD_0
#define ADC_ULTRA_LOW_POWER_MODE ADC14_CTL1_PWRMD_2
#define ADC_INT0 ADC14IE0
#define ADC_INT1 ADC14IE1
#define ADC_INT2 ADC14IE2
#define ADC_INT3 ADC14IE3
#define ADC_INT4 ADC14IE4
#define ADC_INT5 ADC14IE5
#define ADC_INT6 ADC14IE6
#define ADC_INT7 ADC14IE7
#define ADC_INT8 ADC14IE8
#define ADC_INT9 ADC14IE9
#define ADC_INT10 ADC14IE10
#define ADC_INT11 ADC14IE11
#define ADC_INT12 ADC14IE12
#define ADC_INT13 ADC14IE13
#define ADC_INT14 ADC14IE14
#define ADC_INT15 ADC14IE15
#define ADC_INT16 ADC14IE16
#define ADC_INT17 ADC14IE17
#define ADC_INT18 ADC14IE18
#define ADC_INT19 ADC14IE19
#define ADC_INT20 ADC14IE20
#define ADC_INT21 ADC14IE21
#define ADC_INT22 ADC14IE22
#define ADC_INT23 ADC14IE23
#define ADC_INT24 ADC14IE24
#define ADC_INT25 ADC14IE25
#define ADC_INT26 ADC14IE26
#define ADC_INT27 ADC14IE27
#define ADC_INT28 ADC14IE28
#define ADC_INT29 ADC14IE29
#define ADC_INT30 ADC14IE30
#define ADC_INT31 ADC14IE31
#define ADC_INT0 ADC14_IER0_IE0
#define ADC_INT1 ADC14_IER0_IE1
#define ADC_INT2 ADC14_IER0_IE2
#define ADC_INT3 ADC14_IER0_IE3
#define ADC_INT4 ADC14_IER0_IE4
#define ADC_INT5 ADC14_IER0_IE5
#define ADC_INT6 ADC14_IER0_IE6
#define ADC_INT7 ADC14_IER0_IE7
#define ADC_INT8 ADC14_IER0_IE8
#define ADC_INT9 ADC14_IER0_IE9
#define ADC_INT10 ADC14_IER0_IE10
#define ADC_INT11 ADC14_IER0_IE11
#define ADC_INT12 ADC14_IER0_IE12
#define ADC_INT13 ADC14_IER0_IE13
#define ADC_INT14 ADC14_IER0_IE14
#define ADC_INT15 ADC14_IER0_IE15
#define ADC_INT16 ADC14_IER0_IE16
#define ADC_INT17 ADC14_IER0_IE17
#define ADC_INT18 ADC14_IER0_IE18
#define ADC_INT19 ADC14_IER0_IE19
#define ADC_INT20 ADC14_IER0_IE20
#define ADC_INT21 ADC14_IER0_IE21
#define ADC_INT22 ADC14_IER0_IE22
#define ADC_INT23 ADC14_IER0_IE23
#define ADC_INT24 ADC14_IER0_IE24
#define ADC_INT25 ADC14_IER0_IE25
#define ADC_INT26 ADC14_IER0_IE26
#define ADC_INT27 ADC14_IER0_IE27
#define ADC_INT28 ADC14_IER0_IE28
#define ADC_INT29 ADC14_IER0_IE29
#define ADC_INT30 ADC14_IER0_IE30
#define ADC_INT31 ADC14_IER0_IE31
#define ADC_IN_INT 0x0000000200000000
#define ADC_LO_INT 0x0000000400000000
#define ADC_HI_INT 0x0000000800000000
@ -542,9 +542,6 @@ extern bool ADC14_toggleConversionTrigger(void);
//!
//! Returns a boolean value that tells if a conversion/sample is in progress
//!
//! Originally a public function, but moved to static. External customers should
//! use the ADC14_isBusy function.
//!
//! \return true if conversion is active, false otherwise
//
//*****************************************************************************
@ -1026,8 +1023,8 @@ extern void ADC14_unregisterInterrupt(void);
#define ADC14_enableModuleMultipleInstance(a) ADC14_enableModule()
#define ADC14_disableModuleMultipleInstance(a) ADC14_disableModule()
#define ADC14_initModuleMultipleInstance(a,b,c,d,e) ADC14_initModule(b,c,d,e)
#define ADC14_setResolutionMutlipleInstance(a,b) ADC14_setResolution(b)
#define ADC14_getResolutionMutlipleInstance(a) ADC14_getResolution()
#define ADC14_setResolutionMultipleInstance(a,b) ADC14_setResolution(b)
#define ADC14_getResolutionMultipleInstance(a) ADC14_getResolution()
#define ADC14_setSampleHoldTriggerMultipleInstance(a,b,c) ADC14_setSampleHoldTrigger(b,c)
#define ADC14_setSampleHoldTimeMultipleInstance(a,b,c) ADC14_setSampleHoldTime(b,c)
#define ADC14_configureMultiSequenceModeMultipleInstance(a,b,c,d) ADC14_configureMultiSequenceMode(b,c,d)
@ -1036,7 +1033,7 @@ extern void ADC14_unregisterInterrupt(void);
#define ADC14_disableConversionMultipleInstance(a) ADC14_disableConversion()
#define ADC14_toggleConversionTriggerMultipleInstance(a) ADC14_toggleConversionTrigger()
#define ADC14_isBusyMultipleInstance(a) ADC14_isBusy()
#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_enableModule(b,c,d,e)
#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_configureConversionMemory(b,c,d,e)
#define ADC14_enableComparatorWindowMultipleInstance(a,b,c) ADC14_enableComparatorWindow(b,c)
#define ADC14_disableComparatorWindowMultipleInstance(a,b) ADC14_disableComparatorWindow(b)
#define ADC14_setComparatorWindowValueMultipleInstance(a,b,c,d) ADC14_setComparatorWindowValue(b,c,d)

108
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,23 +41,23 @@
bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint_fast16_t keyLength)
{
uint8_t i;
uint_fast8_t i;
uint16_t sCipherKey;
AES256_CMSIS(moduleInstance)->rCTL0.r |= 0;
AES256_CMSIS(moduleInstance)->CTL0 |= 0;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
return false;
@ -69,11 +69,11 @@ bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
{
sCipherKey = (uint16_t) (cipherKey[i]);
sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = sCipherKey;
AES256_CMSIS(moduleInstance)->KEY = sCipherKey;
}
// Wait until key is written
while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS))
while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS))
;
return true;
@ -82,33 +82,33 @@ bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * encryptedData)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to encrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Encryption is initialized by setting AESKEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
// Encryption is initialized by setting AES256_STAT_KEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(encryptedData + i) = (uint8_t) tempData;
*(encryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
@ -117,33 +117,33 @@ void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * decryptedData)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(decryptedData + i) = (uint8_t) tempData;
*(decryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
@ -156,21 +156,21 @@ bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r =
(AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
AES256_CMSIS(moduleInstance)->CTL0 =
(AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
@ -184,11 +184,11 @@ bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
AES256_CMSIS(moduleInstance)->KEY = tempVariable;
}
// Wait until key is processed ~52 MCLK
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
return true;
@ -196,27 +196,27 @@ bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
void AES256_clearInterruptFlag(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIFG_OFS) = 0;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIFG_OFS) = 0;
}
uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESRDYIFG_OFS);
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_RDYIFG_OFS);
}
void AES256_enableInterrupt(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 1;
}
void AES256_disableInterrupt(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 0;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 0;
}
void AES256_reset(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESSWRST_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_SWRST_OFS) = 1;
}
void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
@ -225,63 +225,63 @@ void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
uint16_t tempVariable = 0;
// Set module to encrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Encryption is initialized by setting AESKEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
// Encryption is initialized by setting AES256_STAT_KEYWR to 1
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
}
void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempVariable = 0;
// Set module to decrypt mode
AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
}
bool AES256_startSetDecipherKey(uint32_t moduleInstance,
const uint8_t * cipherKey, uint_fast16_t keyLength)
{
uint8_t i;
uint_fast8_t i;
uint16_t tempVariable = 0;
AES256_CMSIS(moduleInstance)->rCTL0.r =
(AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
AES256_CMSIS(moduleInstance)->CTL0 =
(AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
@ -295,7 +295,7 @@ bool AES256_startSetDecipherKey(uint32_t moduleInstance,
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
AES256_CMSIS(moduleInstance)->KEY = tempVariable;
}
return true;
@ -307,13 +307,13 @@ bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
uint16_t tempData = 0;
// If module is busy, exit and return failure
if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
return false;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(outputData + i) = (uint8_t) tempData;
*(outputData + i + 1) = (uint8_t) (tempData >> 8);
}
@ -323,17 +323,17 @@ bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
bool AES256_isBusy(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS);
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS);
}
void AES256_clearErrorFlag(uint32_t moduleInstance)
{
BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS) = 0;
BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS) = 0;
}
uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance)
{
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS);
return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS);
}
void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))

8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -89,7 +89,7 @@ extern "C"
// can be returned by the AES256_getErrorFlagStatus() function.
//
//*****************************************************************************
#define AES256_ERROR_OCCURRED AESERRFG
#define AES256_ERROR_OCCURRED AES256_CTL0_ERRFG
#define AES256_NO_ERROR 0x00
//*****************************************************************************
@ -98,7 +98,7 @@ extern "C"
// can be returned by the AES256_isBusy() function.
//
//*****************************************************************************
#define AES256_BUSY AESBUSY
#define AES256_BUSY AES256_STAT_BUSY
#define AES256_NOT_BUSY 0x00
//*****************************************************************************

115
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -43,37 +43,37 @@ static uint16_t __getRegisterSettingForInput(uint32_t input)
switch (input)
{
case COMP_E_INPUT0:
return CEIPSEL_0;
return COMP_E_CTL0_IPSEL_0;
case COMP_E_INPUT1:
return CEIPSEL_1;
return COMP_E_CTL0_IPSEL_1;
case COMP_E_INPUT2:
return CEIPSEL_2;
return COMP_E_CTL0_IPSEL_2;
case COMP_E_INPUT3:
return CEIPSEL_3;
return COMP_E_CTL0_IPSEL_3;
case COMP_E_INPUT4:
return CEIPSEL_4;
return COMP_E_CTL0_IPSEL_4;
case COMP_E_INPUT5:
return CEIPSEL_5;
return COMP_E_CTL0_IPSEL_5;
case COMP_E_INPUT6:
return CEIPSEL_6;
return COMP_E_CTL0_IPSEL_6;
case COMP_E_INPUT7:
return CEIPSEL_7;
return COMP_E_CTL0_IPSEL_7;
case COMP_E_INPUT8:
return CEIPSEL_8;
return COMP_E_CTL0_IPSEL_8;
case COMP_E_INPUT9:
return CEIPSEL_9;
return COMP_E_CTL0_IPSEL_9;
case COMP_E_INPUT10:
return CEIPSEL_10;
return COMP_E_CTL0_IPSEL_10;
case COMP_E_INPUT11:
return CEIPSEL_11;
return COMP_E_CTL0_IPSEL_11;
case COMP_E_INPUT12:
return CEIPSEL_12;
return COMP_E_CTL0_IPSEL_12;
case COMP_E_INPUT13:
return CEIPSEL_13;
return COMP_E_CTL0_IPSEL_13;
case COMP_E_INPUT14:
return CEIPSEL_14;
return COMP_E_CTL0_IPSEL_14;
case COMP_E_INPUT15:
return CEIPSEL_15;
return COMP_E_CTL0_IPSEL_15;
case COMP_E_VREF:
return COMP_E_VREF;
default:
@ -98,40 +98,41 @@ bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
<= COMP_E_FILTEROUTPUT_DLYLVL4);
/* Reset COMPE Control 1 & Interrupt Registers for initialization */
COMP_E_CMSIS(comparator)->rCTL0.r = 0;
COMP_E_CMSIS(comparator)->rINT.r = 0;
COMP_E_CMSIS(comparator)->CTL0 = 0;
COMP_E_CMSIS(comparator)->INT = 0;
// Set the Positive Terminal
if (COMP_E_VREF != positiveTerminalInput)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->rCTL0.r |= CEIPEN + positiveTerminalInput;
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+ positiveTerminalInput;
// Disable the input buffer
COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << positiveTerminalInput);
COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r,CERSEL_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0;
}
// Set the Negative Terminal
if (COMP_E_VREF != negativeTerminalInput)
{
// Enable Negative Terminal Input Mux and Set to the appropriate input
COMP_E_CMSIS(comparator)->rCTL0.r |= CEIMEN
COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN
+ (negativeTerminalInput << 8);
// Disable the input buffer
COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << negativeTerminalInput);
COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CERSEL_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1;
}
// Reset and Set COMPE Control 1 Register
COMP_E_CMSIS(comparator)->rCTL1.r = config->powerMode
COMP_E_CMSIS(comparator)->CTL1 = config->powerMode
+ config->outputFilterEnableAndDelayLevel
+ config->invertedOutputPolarity;
@ -149,23 +150,23 @@ void COMP_E_setReferenceVoltage(uint32_t comparator,
upperLimitSupplyVoltageFractionOf32
>= lowerLimitSupplyVoltageFractionOf32);
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEMRVS_OFS) = 0;
COMP_E_CMSIS(comparator)->rCTL2.r &= CERSEL;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_MRVS_OFS) = 0;
COMP_E_CMSIS(comparator)->CTL2 &= COMP_E_CTL2_RSEL;
// Set Voltage Source(Vcc | Vref, resistor ladder or not)
if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_1;
COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_1;
} else if (lowerLimitSupplyVoltageFractionOf32 == 32)
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_3;
COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_3;
} else
{
COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_2;
COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_2;
}
// Set COMPE Control 2 Register
COMP_E_CMSIS(comparator)->rCTL2.r |= supplyVoltageReferenceBase
COMP_E_CMSIS(comparator)->CTL2 |= supplyVoltageReferenceBase
+ ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+ (lowerLimitSupplyVoltageFractionOf32 - 1);
}
@ -178,87 +179,87 @@ void COMP_E_setReferenceAccuracy(uint32_t comparator,
|| (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
if (referenceAccuracy)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 1;
else
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 0;
}
void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode)
{
COMP_E_CMSIS(comparator)->rCTL1.r = (COMP_E_CMSIS(comparator)->rCTL1.r
& ~(CEPWRMD_M)) | powerMode;
COMP_E_CMSIS(comparator)->CTL1 = (COMP_E_CMSIS(comparator)->CTL1
& ~(COMP_E_CTL1_PWRMD_MASK)) | powerMode;
}
void COMP_E_enableModule(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 1;
}
void COMP_E_disableModule(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 0;
}
void COMP_E_shortInputs(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 1;
}
void COMP_E_unshortInputs(uint32_t comparator)
{
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 0;
}
void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
COMP_E_CMSIS(comparator)->rCTL3.r |= (inputPort);
COMP_E_CMSIS(comparator)->CTL3 |= (inputPort);
}
void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
COMP_E_CMSIS(comparator)->rCTL3.r &= ~(inputPort);
COMP_E_CMSIS(comparator)->CTL3 &= ~(inputPort);
}
void COMP_E_swapIO(uint32_t comparator)
{
COMP_E_CMSIS(comparator)->rCTL1.r ^= CEEX; // Toggle CEEX bit
COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_EX; // Toggle CEEX bit
}
uint8_t COMP_E_outputValue(uint32_t comparator)
{
return COMP_E_CMSIS(comparator)->rCTL1.r & CEOUT;
return COMP_E_CMSIS(comparator)->CTL1 & COMP_E_CTL1_OUT;
}
void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
// Set the Interrupt enable bit
COMP_E_CMSIS(comparator)->rINT.r |= mask;
COMP_E_CMSIS(comparator)->INT |= mask;
}
uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator)
{
return COMP_E_getInterruptStatus(comparator) &
COMP_E_CMSIS(comparator)->rINT.r;
COMP_E_CMSIS(comparator)->INT;
}
void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
COMP_E_CMSIS(comparator)->INT &= ~(mask);
}
void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask)
{
COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
COMP_E_CMSIS(comparator)->INT &= ~(mask);
}
uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator)
{
return (COMP_E_CMSIS(comparator)->rINT.r & (COMP_E_OUTPUT_INTERRUPT_FLAG |
return (COMP_E_CMSIS(comparator)->INT & (COMP_E_OUTPUT_INTERRUPT_FLAG |
COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY |
COMP_E_INTERRUPT_FLAG_READY));
}
@ -270,25 +271,25 @@ void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
// Set the edge direction that will trigger an interrupt
if (COMP_E_RISINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 1;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1;
else if (COMP_E_FALLINGEDGE == edgeDirection)
BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 0;
BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 0;
}
void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)
{
COMP_E_CMSIS(comparator)->rCTL1.r ^= CEIES;
COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_IES;
}
void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void))
{
switch (comparator)
{
case COMP_E0_MODULE:
case COMP_E0_BASE:
Interrupt_registerInterrupt(INT_COMP_E0, intHandler);
Interrupt_enableInterrupt(INT_COMP_E0);
break;
case COMP_E1_MODULE:
case COMP_E1_BASE:
Interrupt_registerInterrupt(INT_COMP_E1, intHandler);
Interrupt_enableInterrupt(INT_COMP_E1);
break;
@ -301,11 +302,11 @@ void COMP_E_unregisterInterrupt(uint32_t comparator)
{
switch (comparator)
{
case COMP_E0_MODULE:
case COMP_E0_BASE:
Interrupt_disableInterrupt(INT_COMP_E0);
Interrupt_unregisterInterrupt(INT_COMP_E0);
break;
case COMP_E1_MODULE:
case COMP_E1_BASE:
Interrupt_disableInterrupt(INT_COMP_E1);
Interrupt_unregisterInterrupt(INT_COMP_E1);
break;

138
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -60,13 +60,13 @@ extern "C"
#include <msp.h>
/* Module defines for Comp */
#define COMP_E_CMSIS(x) ((COMP_E0_Type *) x)
#define COMP_E_CMSIS(x) ((COMP_E_Type *) x)
#define COMP_E_FILTEROUTPUT_OFF 0x00
#define COMP_E_FILTEROUTPUT_DLYLVL1 (CEF + CEFDLY_0)
#define COMP_E_FILTEROUTPUT_DLYLVL2 (CEF + CEFDLY_1)
#define COMP_E_FILTEROUTPUT_DLYLVL3 (CEF + CEFDLY_2)
#define COMP_E_FILTEROUTPUT_DLYLVL4 (CEF + CEFDLY_3)
#define COMP_E_FILTEROUTPUT_DLYLVL1 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_0)
#define COMP_E_FILTEROUTPUT_DLYLVL2 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_1)
#define COMP_E_FILTEROUTPUT_DLYLVL3 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_2)
#define COMP_E_FILTEROUTPUT_DLYLVL4 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_3)
#define COMP_E_INPUT0 (0x01)
#define COMP_E_INPUT1 (0x02)
@ -86,38 +86,38 @@ extern "C"
#define COMP_E_INPUT15 (0x8000)
#define COMP_E_VREF (0x9F)
#define COMP_E_NORMALOUTPUTPOLARITY (!(CEOUTPOL))
#define COMP_E_INVERTEDOUTPUTPOLARITY (CEOUTPOL)
#define COMP_E_NORMALOUTPUTPOLARITY (!(COMP_E_CTL1_OUTPOL))
#define COMP_E_INVERTEDOUTPUTPOLARITY (COMP_E_CTL1_OUTPOL)
#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (CEREFL_0)
#define COMP_E_VREFBASE1_2V (CEREFL_1)
#define COMP_E_VREFBASE2_0V (CEREFL_2)
#define COMP_E_VREFBASE2_5V (CEREFL_3)
#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (COMP_E_CTL2_CEREFL_0)
#define COMP_E_VREFBASE1_2V (COMP_E_CTL2_CEREFL_1)
#define COMP_E_VREFBASE2_0V (COMP_E_CTL2_CEREFL_2)
#define COMP_E_VREFBASE2_5V (COMP_E_CTL2_CEREFL_3)
#define COMP_E_ACCURACY_STATIC (!CEREFACC)
#define COMP_E_ACCURACY_CLOCKED (CEREFACC)
#define COMP_E_ACCURACY_STATIC (!COMP_E_CTL2_REFACC)
#define COMP_E_ACCURACY_CLOCKED (COMP_E_CTL2_REFACC)
#define COMP_E_HIGH_SPEED_MODE (CEPWRMD_0)
#define COMP_E_NORMAL_MODE (CEPWRMD_1)
#define COMP_E_ULTRA_LOW_POWER_MODE (CEPWRMD_2)
#define COMP_E_HIGH_SPEED_MODE (COMP_E_CTL1_PWRMD_0)
#define COMP_E_NORMAL_MODE (COMP_E_CTL1_PWRMD_1)
#define COMP_E_ULTRA_LOW_POWER_MODE (COMP_E_CTL1_PWRMD_2)
#define COMP_E_OUTPUT_INTERRUPT (CEIE)
#define COMP_E_INVERTED_POLARITY_INTERRUPT (CEIIE)
#define COMP_E_READY_INTERRUPT (CERDYIE)
#define COMP_E_OUTPUT_INTERRUPT (COMP_E_INT_IE)
#define COMP_E_INVERTED_POLARITY_INTERRUPT (COMP_E_INT_IIE)
#define COMP_E_READY_INTERRUPT (COMP_E_INT_RDYIE)
#define COMP_E_OUTPUT_INTERRUPT_FLAG (CEIFG)
#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (CEIIFG)
#define COMP_E_INTERRUPT_FLAG_READY (CERDYIFG)
#define COMP_E_OUTPUT_INTERRUPT_FLAG (COMP_E_INT_IFG)
#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (COMP_E_INT_IIFG)
#define COMP_E_INTERRUPT_FLAG_READY (COMP_E_INT_RDYIFG)
#define COMP_E_FALLINGEDGE (!(CEIES))
#define COMP_E_RISINGEDGE (CEIES)
#define COMP_E_FALLINGEDGE (!(COMP_E_CTL1_IES))
#define COMP_E_RISINGEDGE (COMP_E_CTL1_IES)
#define COMP_E_LOW (0x0)
#define COMP_E_HIGH (CEOUT)
#define COMP_E_LOW (0x0)
#define COMP_E_HIGH (COMP_E_CTL1_OUT)
//*****************************************************************************
//
//! \typedef COMP_E_Config
//! ypedef COMP_E_Config
//! \brief Type definition for \link _COMP_E_Config \endlink structure
//!
//! \struct _COMP_E_Config
@ -140,8 +140,8 @@ typedef struct _COMP_E_Config
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param config Configuration structure for the Comparator module
//!
//! <hr>
@ -230,8 +230,8 @@ extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param supplyVoltageReferenceBase decides the source and max amount of
//! Voltage that can be used as a reference.
//! Valid values are
@ -267,8 +267,8 @@ extern void COMP_E_setReferenceVoltage(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param referenceAccuracy is the reference accuracy setting of the
//! comparator. Clocked is for low power/low accuracy.
//! Valid values are
@ -291,8 +291,8 @@ extern void COMP_E_setReferenceAccuracy(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param powerMode decides the power mode
//! Valid values are
//! - \b COMP_E_HIGH_SPEED_MODE
@ -311,8 +311,8 @@ extern void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function sets the bit that enables the operation of the
//! Comparator module.
@ -328,8 +328,8 @@ extern void COMP_E_enableModule(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function clears the CEON bit disabling the operation of the Comparator
//! module, saving from excess power consumption.
@ -346,8 +346,8 @@ extern void COMP_E_disableModule(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function sets the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
@ -364,8 +364,8 @@ extern void COMP_E_shortInputs(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function clears the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
@ -383,8 +383,8 @@ extern void COMP_E_unshortInputs(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param inputPort is the port in which the input buffer will be disabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
@ -425,8 +425,8 @@ extern void COMP_E_disableInputBuffer(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param inputPort is the port in which the input buffer will be enabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
@ -484,8 +484,8 @@ extern void COMP_E_swapIO(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid parameters
//! vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! Returns the output value of the Comparator module.
//!
@ -501,8 +501,8 @@ extern uint8_t COMP_E_outputValue(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param mask is the bit mask of the interrupt sources to be enabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
@ -527,8 +527,8 @@ extern void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param mask is the bit mask of the interrupt sources to be disabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
@ -551,8 +551,8 @@ extern void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param mask is a bit mask of the interrupt sources to be cleared.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag
@ -575,8 +575,8 @@ extern void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This returns the interrupt status for the Comparator module based on which
//! flag is passed.
@ -595,8 +595,8 @@ extern uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! Enables the indicated Comparator interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
@ -615,8 +615,8 @@ extern uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//! \param edgeDirection determines which direction the edge would have to go
//! to generate an interrupt based on the non-inverted interrupt flag.
//! Valid values are
@ -646,8 +646,8 @@ extern void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function will toggle which direction the output will have to go,
//! whether rising or falling, to generate an interrupt based on a non-inverted
@ -670,8 +670,8 @@ extern void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator);
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function registers the handler to be called when a Comparator
//! interrupt occurs. This function enables the global interrupt in the
@ -691,8 +691,8 @@ extern void COMP_E_registerInterrupt(uint32_t comparator,
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
//! - \b COMP_E0
//! - \b COMP_E1
//! - \b COMP_E0_BASE
//! - \b COMP_E1_BASE
//!
//! This function unregisters the handler to be called when Comparator E
//! interrupt occurs. This function also masks off the interrupt in the

52
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -44,7 +44,7 @@
// on entry.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_cpsid(void)
{
uint32_t ret;
@ -66,7 +66,7 @@ uint32_t __attribute__((naked)) CPU_cpsid(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_cpsid(void)
{
//
@ -84,7 +84,7 @@ uint32_t CPU_cpsid(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_cpsid(void)
{
//
@ -95,7 +95,7 @@ __asm uint32_t CPU_cpsid(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_cpsid(void)
{
//
@ -122,7 +122,7 @@ uint32_t CPU_cpsid(void)
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_primask(void)
{
uint32_t ret;
@ -143,7 +143,7 @@ uint32_t __attribute__((naked)) CPU_primask(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_primask(void)
{
//
@ -160,7 +160,7 @@ uint32_t CPU_primask(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_primask(void)
{
//
@ -170,7 +170,7 @@ __asm uint32_t CPU_primask(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_primask(void)
{
//
@ -196,7 +196,7 @@ uint32_t CPU_primask(void)
// on entry.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_cpsie(void)
{
uint32_t ret;
@ -218,7 +218,7 @@ uint32_t __attribute__((naked)) CPU_cpsie(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_cpsie(void)
{
//
@ -236,7 +236,7 @@ uint32_t CPU_cpsie(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_cpsie(void)
{
//
@ -247,7 +247,7 @@ __asm uint32_t CPU_cpsie(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_cpsie(void)
{
//
@ -273,7 +273,7 @@ uint32_t CPU_cpsie(void)
// Wrapper function for the CPUWFI instruction.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
void __attribute__((naked)) CPU_wfi(void)
{
//
@ -283,7 +283,7 @@ void __attribute__((naked)) CPU_wfi(void)
" bx lr\n");
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
void CPU_wfi(void)
{
//
@ -292,7 +292,7 @@ void CPU_wfi(void)
__asm(" wfi\n");
}
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm void CPU_wfi(void)
{
//
@ -302,7 +302,7 @@ __asm void CPU_wfi(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
void CPU_wfi(void)
{
//
@ -317,7 +317,7 @@ void CPU_wfi(void)
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
{
//
@ -327,7 +327,7 @@ void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
" bx lr\n");
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
void CPU_basepriSet(uint32_t newBasepri)
{
//
@ -336,7 +336,7 @@ void CPU_basepriSet(uint32_t newBasepri)
__asm(" msr BASEPRI, r0\n");
}
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm void CPU_basepriSet(uint32_t newBasepri)
{
//
@ -346,7 +346,7 @@ __asm void CPU_basepriSet(uint32_t newBasepri)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
void CPU_basepriSet(uint32_t newBasepri)
{
//
@ -361,7 +361,7 @@ void CPU_basepriSet(uint32_t newBasepri)
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_basepriGet(void)
{
uint32_t ret;
@ -382,7 +382,7 @@ uint32_t __attribute__((naked)) CPU_basepriGet(void)
return(ret);
}
#endif
#if defined(ewarm)
#if defined(__ICCARM__)
uint32_t CPU_basepriGet(void)
{
//
@ -399,7 +399,7 @@ uint32_t CPU_basepriGet(void)
}
#pragma diag_default=Pe940
#endif
#if defined(keil)
#if defined(__CC_ARM)
__asm uint32_t CPU_basepriGet(void)
{
//
@ -409,7 +409,7 @@ __asm uint32_t CPU_basepriGet(void)
bx lr
}
#endif
#if defined(ccs)
#if defined(__TI_ARM__)
uint32_t CPU_basepriGet(void)
{
//

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

57
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,17 +37,18 @@
#include "crc32.h"
#include <msp.h>
#include <debug.h>
#include <hw_memmap.h>
void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16INIRES = seed;
CRC32->INIRES16 = seed;
else
{
CRC32->rCRC32INIRES_HI = ((seed & 0xFFFF0000) >> 16);
CRC32->rCRC32INIRES_LO = (seed & 0xFFFF);
CRC32->INIRES32_HI = ((seed & 0xFFFF0000) >> 16);
CRC32->INIRES32_LO = (seed & 0xFFFF);
}
}
@ -56,9 +57,9 @@ void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
HWREG8(CRC32_BASE + OFS_CRC16DI) = dataIn;
HWREG8(&(CRC32->DI16)) = dataIn;
else
HWREG8(CRC32_BASE + OFS_CRC32DI) = dataIn;
HWREG8(&(CRC32->DI32)) = dataIn;
}
void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
@ -66,18 +67,18 @@ void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16DI = dataIn;
CRC32->DI16 = dataIn;
else
CRC32->rCRC32DI = dataIn;
CRC32->DI32 = dataIn;
}
void CRC32_set32BitData(uint32_t dataIn)
{
//CRC32->rCRC32DI = dataIn & 0xFFFF;
//CRC32->rCRC32DI = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
//CRC32->DI32 = dataIn & 0xFFFF;
//CRC32->DI32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
HWREG16(CRC32_BASE + OFS_CRC32DI) = dataIn & 0xFFFF;
HWREG16(CRC32_BASE + OFS_CRC32DI) = (uint16_t)(
HWREG16(&(CRC32->DI32)) = dataIn & 0xFFFF;
HWREG16(&(CRC32->DI32)) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
}
@ -86,9 +87,9 @@ void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
HWREG8(CRC32_BASE + OFS_CRC16DIRB) = dataIn;
HWREG8(&(CRC32->DIRB16)) = dataIn;
else
HWREG8(CRC32_BASE + OFS_CRC32DIRB) = dataIn;
HWREG8(&(CRC32->DIRB32)) = dataIn;
}
void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
@ -96,18 +97,20 @@ void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
CRC32->rCRC16DIRB = dataIn;
CRC32->DIRB16 = dataIn;
else
CRC32->rCRC32DIRB = dataIn;
CRC32->DIRB32 = dataIn;
}
void CRC32_set32BitDataReversed(uint32_t dataIn)
{
HWREG16(CRC32_BASE + OFS_CRC32DIRB) = dataIn & 0xFFFF;
HWREG16(CRC32_BASE + OFS_CRC32DIRB) = (uint16_t)(
//CRC32->DIRB32 = dataIn & 0xFFFF;
//CRC32->DIRB32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
HWREG16(&(CRC32->DIRB32)) = dataIn & 0xFFFF;
HWREG16(&(CRC32->DIRB32)) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
//CRC32->rCRC32DIRB = dataIn & 0xFFFF;
//CRC32->rCRC32DIRB = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
}
uint32_t CRC32_getResult(uint_fast8_t crcType)
@ -116,12 +119,12 @@ uint32_t CRC32_getResult(uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
return CRC32->rCRC16INIRES;
return CRC32->INIRES16;
else
{
result = CRC32->rCRC32INIRES_HI;
result = CRC32->INIRES32_HI;
result = (result << 16);
result |= CRC32->rCRC32INIRES_LO;
result |= CRC32->INIRES32_LO;
return (result);
}
}
@ -132,12 +135,12 @@ uint32_t CRC32_getResultReversed(uint_fast8_t crcType)
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
return CRC32->rCRC16RESR;
return CRC32->RESR16;
else
{
result = CRC32->rCRC32RESR_HI;
result = CRC32->RESR32_HI;
result = (result << 16);
result |= CRC32->rCRC32RESR_LO;
result |= CRC32->RESR32_LO;
return (result);
}
}

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

499
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -62,19 +62,19 @@ bool _CSIsClockDividerValid(uint8_t divider)
static uint32_t _CSGetHFXTFrequency()
{
if (hfxtFreq >= CS_1MHZ && hfxtFreq <= CS_4MHZ)
return HFXTFREQ_0;
return CS_CTL2_HFXTFREQ_0;
else if (hfxtFreq > CS_4MHZ && hfxtFreq <= CS_8MHZ)
return HFXTFREQ_1;
return CS_CTL2_HFXTFREQ_1;
else if (hfxtFreq > CS_8MHZ && hfxtFreq <= CS_16MHZ)
return HFXTFREQ_2;
return CS_CTL2_HFXTFREQ_2;
else if (hfxtFreq > CS_16MHZ && hfxtFreq <= CS_24MHZ)
return HFXTFREQ_3;
return CS_CTL2_HFXTFREQ_3;
else if (hfxtFreq > CS_24MHZ && hfxtFreq <= CS_32MHZ)
return HFXTFREQ_4;
return CS_CTL2_HFXTFREQ_4;
else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ)
return HFXTFREQ_5;
return CS_CTL2_HFXTFREQ_5;
else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ)
return HFXTFREQ_5;
return CS_CTL2_HFXTFREQ_5;
else
{
ASSERT(false);
@ -111,7 +111,7 @@ static uint32_t _CSGetDividerValue(uint32_t wDivider)
static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
{
uint8_t bDivider;
uint_fast8_t bDivider;
bDivider = _CSGetDividerValue(wDivider);
@ -119,32 +119,32 @@ static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
{
case CS_LFXTCLK_SELECT:
{
if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
CS_clearInterruptFlag(CS_LFXT_FAULT);
if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
return (128000 / bDivider);
else
return (32000 / bDivider);
return (32768 / bDivider);
}
}
return lfxtFreq / bDivider;
}
case CS_HFXTCLK_SELECT:
{
if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
CS_clearInterruptFlag(CS_HFXT_FAULT);
if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
return (128000 / bDivider);
else
return (32000 / bDivider);
return (32768 / bDivider);
}
}
return hfxtFreq / bDivider;
@ -153,10 +153,10 @@ static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
return CS_VLOCLK_FREQUENCY / bDivider;
case CS_REFOCLK_SELECT:
{
if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
return (128000 / bDivider);
else
return (32000 / bDivider);
return (32768 / bDivider);
}
case CS_DCOCLK_SELECT:
return (CS_getDCOFrequency() / bDivider);
@ -175,24 +175,24 @@ static uint32_t _CSGetDOCFrequency(void)
{
uint32_t dcoFreq;
switch (CS->rCTL0.r & DCORSEL_M)
switch (CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
case DCORSEL_0:
case CS_CTL0_DCORSEL_0:
dcoFreq = 1500000;
break;
case DCORSEL_1:
case CS_CTL0_DCORSEL_1:
dcoFreq = 3000000;
break;
case DCORSEL_2:
case CS_CTL0_DCORSEL_2:
dcoFreq = 6000000;
break;
case DCORSEL_3:
case CS_CTL0_DCORSEL_3:
dcoFreq = 12000000;
break;
case DCORSEL_4:
case CS_CTL0_DCORSEL_4:
dcoFreq = 24000000;
break;
case DCORSEL_5:
case CS_CTL0_DCORSEL_5:
dcoFreq = 48000000;
break;
default:
@ -215,7 +215,7 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
ASSERT(_CSIsClockDividerValid(clockSourceDivider));
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
switch (selectedClockSignal)
{
@ -231,16 +231,16 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS))
;
/* Setting the divider and source */
CS->rCTL1.r = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
CS->CTL1 = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
| (clockSource << CS_ACLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(SELA_M | DIVA_M));
| (CS->CTL1 & ~(CS_CTL1_SELA_MASK | CS_CTL1_DIVA_MASK));
/* Waiting for ACLK to be ready again */
while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS))
;
break;
@ -250,15 +250,15 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS))
;
CS->rCTL1.r = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
CS->CTL1 = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
| (clockSource << CS_MCLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(SELM_M | DIVM_M));
| (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK));
/* Waiting for MCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS))
;
break;
@ -267,15 +267,15 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
{
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS))
;
CS->rCTL1.r = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
CS->CTL1 = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
| (clockSource << CS_HSMCLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(DIVS_M | SELS_M));
| (CS->CTL1 & ~(CS_CTL1_DIVS_MASK | CS_CTL1_SELS_MASK));
/* Waiting for SMCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS))
;
break;
@ -284,15 +284,15 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
{
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS))
;
CS->rCTL1.r = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
CS->CTL1 = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
| (clockSource << CS_HSMCLK_SRC_BITPOS))
| (CS->rCTL1.r & ~(DIVHS_M | SELS_M));
| (CS->CTL1 & ~(CS_CTL1_DIVHS_MASK | CS_CTL1_SELS_MASK));
/* Waiting for HSMCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS))
;
break;
@ -302,21 +302,21 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
/* Waiting for the clock source ready bit to be valid before
* changing */
while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS))
;
/* Setting the clock source and then returning
* (cannot divide CLK)
*/
if (clockSource == CS_LFXTCLK_SELECT)
BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 0;
BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 0;
else if (clockSource == CS_REFOCLK_SELECT)
BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 1;
BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 1;
else
ASSERT(false);
/* Waiting for BCLK to be ready */
while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS))
;
break;
@ -329,22 +329,22 @@ void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_startHFXT(bool bypassMode)
bool CS_startHFXT(bool bypassMode)
{
CS_startHFXTWithTimeout(bypassMode, 0);
return CS_startHFXTWithTimeout(bypassMode, 0);
}
void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
{
uint32_t wHFFreqRange;
uint8_t bNMIStatus;
uint_fast8_t bNMIStatus;
bool boolTimeout;
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
@ -355,50 +355,54 @@ void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
boolTimeout = (timeout == 0) ? false : true;
/* Setting to maximum drive strength */
BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
CS->rCTL2.r = (CS->rCTL2.r & (~HFXTFREQ_M)) | (wHFFreqRange);
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
CS->CTL2 = (CS->CTL2 & (~CS_CTL2_HFXTFREQ_MASK)) | (wHFFreqRange);
if (bypassMode)
{
BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 1;
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 1;
} else
{
BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 0;
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 0;
}
/* Starting and Waiting for frequency stabilization */
BITBAND_PERI(CS->rCTL2.r, HFXT_EN_OFS) = 1;
while (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXT_EN_OFS) = 1;
while (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
BITBAND_PERI(CS->rCLRIFG.r,CLR_HFXTIFG_OFS) = 1;
BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_HFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!bypassMode)
{
if (wHFFreqRange != HFXTFREQ_0)
BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
if (wHFFreqRange != CS_CTL2_HFXTFREQ_0)
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
else
BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 0;
BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 0;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
if(boolTimeout && timeout == 0)
return false;
return true;
}
void CS_startLFXT(uint32_t xtDrive)
bool CS_startLFXT(uint32_t xtDrive)
{
CS_startLFXTWithTimeout(xtDrive, 0);
return CS_startLFXTWithTimeout(xtDrive, 0);
}
void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
{
uint8_t bNMIStatus;
bool boolBypassMode, boolTimeout;
@ -411,7 +415,7 @@ void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
|| (xtDrive == CS_LFXT_BYPASS));
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
@ -422,35 +426,40 @@ void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
/* Setting to maximum drive strength */
if (boolBypassMode)
{
BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 1;
BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 1;
} else
{
CS->rCTL2.r |= (CS_LFXT_DRIVE3);
BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 0;
CS->CTL2 |= (CS_LFXT_DRIVE3);
BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 0;
}
/* Waiting for frequency stabilization */
BITBAND_PERI(CS->rCTL2.r, LFXT_EN_OFS) = 1;
BITBAND_PERI(CS->CTL2, CS_CTL2_LFXT_EN_OFS) = 1;
while (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
while (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
BITBAND_PERI(CS->rCLRIFG.r,CLR_LFXTIFG_OFS) = 1;
BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_LFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!boolBypassMode)
{
CS->rCTL2.r = ((CS->rCTL2.r & ~CS_LFXT_DRIVE3) | xtDrive);
CS->CTL2 = ((CS->CTL2 & ~CS_LFXT_DRIVE3) | xtDrive);
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
if(boolTimeout && timeout == 0)
return false;
return true;
}
void CS_enableClockRequest(uint32_t selectClock)
@ -460,12 +469,12 @@ void CS_enableClockRequest(uint32_t selectClock)
|| selectClock == CS_SMCLK || selectClock == CS_MCLK);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
CS->rCLKEN.r |= selectClock;
CS->CLKEN |= selectClock;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableClockRequest(uint32_t selectClock)
@ -475,12 +484,12 @@ void CS_disableClockRequest(uint32_t selectClock)
|| selectClock == CS_SMCLK || selectClock == CS_MCLK);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
CS->rCLKEN.r &= ~selectClock;
CS->CLKEN &= ~selectClock;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
@ -490,39 +499,64 @@ void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
|| referenceFrequency == CS_REFO_128KHZ);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS) = referenceFrequency;
BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS) = referenceFrequency;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_enableDCOExternalResistor(void)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 1;
BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 1;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData)
void CS_setDCOExternalResistorCalibration(uint_fast8_t calData,
uint_fast8_t freqRange)
{
CS->rDCOERCAL.r = (uiCalData);
uint_fast8_t rselVal;
/* Unlocking the module */
CS->KEY = CS_KEY;
rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK)>>CS_CTL0_DCORSEL_OFS;
CS->CTL0 &= ~CS_CTL0_DCORSEL_MASK;
if( (freqRange == CS_OVER32MHZ) && ( TLV->HWREV > DEVICE_PG1_1))
{
CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK;
CS->DCOERCAL1 |= (calData);
}
else
{
CS->DCOERCAL0 &= ~CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK;
CS->DCOERCAL0 |= (calData)<<CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS;
}
CS->CTL0 |= (rselVal)<<CS_CTL0_DCORSEL_OFS;
/* Locking the module */
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableDCOExternalResistor(void)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 0;
BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 0;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_setDCOCenteredFrequency(uint32_t dcoFreq)
@ -535,32 +569,39 @@ void CS_setDCOCenteredFrequency(uint32_t dcoFreq)
|| dcoFreq == CS_DCO_FREQUENCY_48);
/* Unlocking the CS Module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
/* Resetting Tuning Parameters and Setting the frequency */
CS->rCTL0.r = ((CS->rCTL0.r & ~DCORSEL_M) | dcoFreq);
CS->CTL0 = ((CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dcoFreq);
/* Locking the CS Module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_tuneDCOFrequency(int16_t tuneParameter)
{
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
uint16_t dcoTuneMask = 0x1FFF;
uint16_t dcoTuneSigned = 0x1000;
if (TLV->HWREV > DEVICE_PG1_1) {
dcoTuneMask = 0x3FF;
dcoTuneSigned = 0x200;
}
if (tuneParameter < 0)
{
CS->rCTL0.r = ((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M)
| 0x1000);
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
& dcoTuneMask) | dcoTuneSigned);
}
else
{
CS->rCTL0.r =
((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M));
CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
& dcoTuneMask));
}
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
uint32_t CS_getDCOFrequency(void)
@ -569,57 +610,87 @@ uint32_t CS_getDCOFrequency(void)
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
uint_fast8_t tlvLength;
SysCtl_CSCalTLV_Info *csInfo;
uint32_t retVal;
dcoTune = CS->rCTL0.b.bDCOTUNE;
centeredFreq = _CSGetDOCFrequency();
/* Parsing the TLV and getting the maximum erase pulses */
SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**)&csInfo);
if(tlvLength == 0)
{
return centeredFreq;
}
/* Checking to see if we need to do signed conversion */
if ( TLV->HWREV > DEVICE_PG1_1)
{
dcoTune = CS->CTL0 & 0x3FF;
if (dcoTune & 0x200)
{
dcoTune = dcoTune | 0xFE00;
}
}
else
{
dcoTune = CS->CTL0 & 0x1FFF;
if (dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
}
if (dcoTune == 0)
return (uint32_t) centeredFreq;
/* Checking to see if we need to do signed conversion */
if (dcoTune & 0x1000)
/* DCORSEL = 5 */
if ((centeredFreq == 48000000) && ( TLV->HWREV > DEVICE_PG1_1))
{
dcoTune = dcoTune | 0xF000;
}
/* DCORSEL = 5, in final silicon this will have a different calibration
value, but currently DCORSEL5 calibration is not populated
if (centeredFreq == 48000000)
{
External Resistor
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
/* External Resistor */
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
calVal = TLV->rDCOER_FCAL_RSEL5;
}
Internal Resistor
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
calVal = TLV->rDCOIR_FCAL_RSEL5;
}
}
DCORSEL = 4
else
{*/
/* External Resistor */
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
calVal = TLV->rDCOER_FCAL_RSEL04;
dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
calVal = csInfo->rDCOER_FCAL_RSEL5;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
calVal = TLV->rDCOIR_FCAL_RSEL04;
dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5);
calVal = csInfo->rDCOIR_FCAL_RSEL5;
}
/*}*/
}
/* DCORSEL = 4 */
else
{
/* External Resistor */
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04);
calVal = csInfo->rDCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04);
calVal = csInfo->rDCOIR_FCAL_RSEL04;
}
}
return (uint32_t) ((centeredFreq)
/ (1
- ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal))))));
if( TLV->HWREV > DEVICE_PG1_1 )
{
retVal = (uint32_t) (centeredFreq)
/ (1 - ((dcoConst * dcoTune)
/ ((1 + dcoConst * (768 - calVal)))));
}
else
{
retVal = (uint32_t) (centeredFreq)
/ (1 - ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal)))));
}
return retVal;
}
void CS_setDCOFrequency(uint32_t dcoFrequency)
@ -627,8 +698,10 @@ void CS_setDCOFrequency(uint32_t dcoFrequency)
int32_t nomFreq, calVal, dcoSigned;
int16_t dcoTune;
float dcoConst;
// bool rsel5 = false;
bool rsel5 = false;
dcoSigned = (int32_t) dcoFrequency;
uint_fast8_t tlvLength;
SysCtl_CSCalTLV_Info *csInfo;
if (dcoFrequency < 2000000)
{
@ -654,56 +727,62 @@ void CS_setDCOFrequency(uint32_t dcoFrequency)
{
nomFreq = CS_48MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
// rsel5 = true;
rsel5 = true;
} else
{
ASSERT(false);
return;
}
if(dcoFrequency == nomFreq)
/* Parsing the TLV and getting the maximum erase pulses */
SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**)&csInfo);
if(dcoFrequency == nomFreq || tlvLength == 0)
{
CS_tuneDCOFrequency(0);
return;
}
/* DCORSEL = 5, in final silicon this will have a different calibration
value, but currently DCORSEL5 calibration is not populated
if (rsel5)
if ((rsel5) && ( TLV->HWREV > DEVICE_PG1_1))
{
External Resistor
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
/* External Resistor*/
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
calVal = TLV->rDCOER_FCAL_RSEL5;
}
Internal Resistor
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
calVal = TLV->rDCOIR_FCAL_RSEL5;
}
}
DCORSEL = 4
else
{*/
/* External Resistor */
if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
{
dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
calVal = TLV->rDCOER_FCAL_RSEL04;
dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
calVal = csInfo->rDCOER_FCAL_RSEL5;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
calVal = TLV->rDCOIR_FCAL_RSEL04;
dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5);
calVal = csInfo->rDCOIR_FCAL_RSEL5;
}
/*}*/
}
/* DCORSEL = 4 */
else
{
/* External Resistor */
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04);
calVal = csInfo->rDCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04);
calVal = csInfo->rDCOIR_FCAL_RSEL04;
}
}
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0 + dcoConst * (768.0 - calVal)) * 8.0)
/ (dcoSigned * dcoConst));
if ( TLV->HWREV > DEVICE_PG1_1)
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0f + dcoConst * (768.0f - calVal)))
/ (dcoSigned * dcoConst));
else
dcoTune = (int16_t) (((dcoSigned - nomFreq)
* (1.0f + dcoConst * (768.0f - calVal)) * 8.0f)
/ (dcoSigned * dcoConst));
CS_tuneDCOFrequency(dcoTune);
@ -711,7 +790,7 @@ void CS_setDCOFrequency(uint32_t dcoFrequency)
uint32_t CS_getBCLK(void)
{
if (BITBAND_PERI(CS->rCTL1.r, SELB_OFS))
if (BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS))
return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
else
return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
@ -721,8 +800,8 @@ uint32_t CS_getHSMCLK(void)
{
uint32_t wSource, wDivider;
wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVHS_M) << CS_HSMCLK_DIV_BITPOS);
wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS;
wDivider = ((CS->CTL1 & CS_CTL1_DIVHS_MASK) << CS_HSMCLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
@ -731,8 +810,8 @@ uint32_t CS_getACLK(void)
{
uint32_t wSource, wDivider;
wSource = (CS->rCTL1.r & SELA_M) >> CS_ACLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVA_M) << CS_ACLK_DIV_BITPOS);
wSource = (CS->CTL1 & CS_CTL1_SELA_MASK) >> CS_ACLK_SRC_BITPOS;
wDivider = ((CS->CTL1 & CS_CTL1_DIVA_MASK) << CS_ACLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
@ -741,8 +820,8 @@ uint32_t CS_getSMCLK(void)
{
uint32_t wDivider, wSource;
wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVS_M));
wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS;
wDivider = ((CS->CTL1 & CS_CTL1_DIVS_MASK));
return _CSComputeCLKFrequency(wSource, wDivider);
@ -752,8 +831,8 @@ uint32_t CS_getMCLK(void)
{
uint32_t wSource, wDivider;
wSource = (CS->rCTL1.r & SELM_M) << CS_MCLK_SRC_BITPOS;
wDivider = ((CS->rCTL1.r & DIVM_M) << CS_MCLK_DIV_BITPOS);
wSource = (CS->CTL1 & CS_CTL1_SELM_MASK) << CS_MCLK_SRC_BITPOS;
wDivider = ((CS->CTL1 & CS_CTL1_DIVM_MASK) << CS_MCLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
@ -764,18 +843,18 @@ void CS_enableFaultCounter(uint_fast8_t counterSelect)
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 1;
BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 1;
} else
{
BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 1;
BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 1;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableFaultCounter(uint_fast8_t counterSelect)
@ -784,18 +863,18 @@ void CS_disableFaultCounter(uint_fast8_t counterSelect)
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 0;
BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 0;
} else
{
BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 0;
BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 0;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_resetFaultCounter(uint_fast8_t counterSelect)
@ -804,18 +883,18 @@ void CS_resetFaultCounter(uint_fast8_t counterSelect)
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
BITBAND_PERI(CS->rCTL3.r, RFCNTHF_OFS) = 1;
BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTHF_OFS) = 1;
} else
{
BITBAND_PERI(CS->rCTL3.r, RFCNTLF_OFS) = 1;
BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTLF_OFS) = 1;
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue)
@ -829,61 +908,61 @@ void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue)
countValue == CS_FAULT_COUNTER_32768_CYCLES);
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTHF_M) | (countValue << 4));
CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTHF_MASK) | (countValue << 4));
} else
{
CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTLF_M) | (countValue));
CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTLF_MASK) | (countValue));
}
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_enableInterrupt(uint32_t flags)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
CS->rIE.r |= flags;
CS->IE |= flags;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableInterrupt(uint32_t flags)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
CS->rIE.r &= ~flags;
CS->IE &= ~flags;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
uint32_t CS_getInterruptStatus(void)
{
return CS->rIFG.r;
return CS->IFG;
}
uint32_t CS_getEnabledInterruptStatus(void)
{
return CS_getInterruptStatus() & CS->rIE.r;
return CS_getInterruptStatus() & CS->IE;
}
void CS_clearInterruptFlag(uint32_t flags)
{
/* Unlocking the module */
CS->rKEY.r = CS_KEY;
CS->KEY = CS_KEY;
CS->rCLRIFG.r |= flags;
CS->CLRIFG |= flags;
/* Locking the module */
BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_registerInterrupt(void (*intHandler)(void))

170
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -64,21 +64,21 @@ extern "C"
// Control specific variables
//
//*****************************************************************************
#define CS_CLOCK_DIVIDER_1 DIVS_0
#define CS_CLOCK_DIVIDER_2 DIVS_1
#define CS_CLOCK_DIVIDER_4 DIVS_2
#define CS_CLOCK_DIVIDER_8 DIVS_3
#define CS_CLOCK_DIVIDER_16 DIVS_4
#define CS_CLOCK_DIVIDER_32 DIVS_5
#define CS_CLOCK_DIVIDER_64 DIVS_6
#define CS_CLOCK_DIVIDER_128 DIVS_7
#define CS_CLOCK_DIVIDER_1 CS_CTL1_DIVS_0
#define CS_CLOCK_DIVIDER_2 CS_CTL1_DIVS_1
#define CS_CLOCK_DIVIDER_4 CS_CTL1_DIVS_2
#define CS_CLOCK_DIVIDER_8 CS_CTL1_DIVS_3
#define CS_CLOCK_DIVIDER_16 CS_CTL1_DIVS_4
#define CS_CLOCK_DIVIDER_32 CS_CTL1_DIVS_5
#define CS_CLOCK_DIVIDER_64 CS_CTL1_DIVS_6
#define CS_CLOCK_DIVIDER_128 CS_CTL1_DIVS_7
#define CS_LFXTCLK_SELECT SELM_0
#define CS_HFXTCLK_SELECT SELM_5
#define CS_VLOCLK_SELECT SELM_1
#define CS_REFOCLK_SELECT SELM_2
#define CS_DCOCLK_SELECT SELM_3
#define CS_MODOSC_SELECT SELM_4
#define CS_LFXTCLK_SELECT CS_CTL1_SELM_0
#define CS_HFXTCLK_SELECT CS_CTL1_SELM_5
#define CS_VLOCLK_SELECT CS_CTL1_SELM_1
#define CS_REFOCLK_SELECT CS_CTL1_SELM_2
#define CS_DCOCLK_SELECT CS_CTL1_SELM_3
#define CS_MODOSC_SELECT CS_CTL1_SELM_4
#define CS_KEY 0x695A
@ -103,33 +103,29 @@ extern "C"
#define CS_MODCLK_FREQUENCY 24000000
/* Interrupts */
#define CS_LFXT_FAULT LFXTIE
#define CS_HFXT_FAULT HFXTIE
#define CS_DCOMIN_FAULT DCOMINIE
#define CS_DCOMAX_FAULT DCOMAXIE
#define CS_DCORESISTOR_FAULT DCORIE
#define CS_STARTCOUNT_LFXT_FAULT FCNTLFIE
#define CS_STARTCOUNT_HFXT_FAULT FCNTHFIE
#define CS_PLL_OUTOFLOCK PLLOOLIE
#define CS_PLL_OUTOFSIGNAL PLLLOSIE
#define CS_PLL_OUTOFRANGE PLLOORIE
#define CS_REFCNT_PERIOD_COUNTER CALIE
#define CS_LFXT_FAULT CS_IE_LFXTIE
#define CS_HFXT_FAULT CS_IE_HFXTIE
#define CS_DCO_OPEN_FAULT CS_IE_DCOR_OPNIE
#define CS_STARTCOUNT_LFXT_FAULT CS_IE_FCNTLFIE
#define CS_STARTCOUNT_HFXT_FAULT CS_IE_FCNTHFIE
#define CS_DCO_SHORT_FAULT CS_IFG_DCOR_SHTIFG
#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
//#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
//#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
#define CS_HFXT_DRIVE CS_CTL2_HFXTDRIVE
#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
#define CS_LFXT_DRIVE0 LFXTDRIVE_0
#define CS_LFXT_DRIVE1 LFXTDRIVE_1
#define CS_LFXT_DRIVE2 LFXTDRIVE_2
#define CS_LFXT_DRIVE3 LFXTDRIVE_3
#define CS_LFXT_BYPASS LFXTBYPASS
#define CS_LFXT_DRIVE0 CS_CTL2_LFXTDRIVE_0
#define CS_LFXT_DRIVE1 CS_CTL2_LFXTDRIVE_1
#define CS_LFXT_DRIVE2 CS_CTL2_LFXTDRIVE_2
#define CS_LFXT_DRIVE3 CS_CTL2_LFXTDRIVE_3
#define CS_LFXT_BYPASS CS_CTL2_LFXTBYPASS
#define CS_ACLK ACLK_EN
#define CS_MCLK MCLK_EN
#define CS_SMCLK SMCLK_EN
#define CS_HSMCLK HSMCLK_EN
#define CS_BCLK BCLK_READY
#define CS_ACLK CS_CLKEN_ACLK_EN
#define CS_MCLK CS_CLKEN_MCLK_EN
#define CS_SMCLK CS_CLKEN_SMCLK_EN
#define CS_HSMCLK CS_CLKEN_HSMCLK_EN
#define CS_BCLK CS_STAT_BCLK_READY
#define CS_LFXTCLK 0x01
@ -146,20 +142,25 @@ extern "C"
#define CS_40MHZ 40000000
#define CS_48MHZ 48000000
#define CS_DCO_FREQUENCY_1_5 DCORSEL_0
#define CS_DCO_FREQUENCY_3 DCORSEL_1
#define CS_DCO_FREQUENCY_6 DCORSEL_2
#define CS_DCO_FREQUENCY_12 DCORSEL_3
#define CS_DCO_FREQUENCY_24 DCORSEL_4
#define CS_DCO_FREQUENCY_48 DCORSEL_5
#define CS_DCO_FREQUENCY_1_5 CS_CTL0_DCORSEL_0
#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1
#define CS_DCO_FREQUENCY_6 CS_CTL0_DCORSEL_2
#define CS_DCO_FREQUENCY_12 CS_CTL0_DCORSEL_3
#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
#define CS_DCO_FREQUENCY_48 CS_CTL0_DCORSEL_5
#define CS_HFXT_FAULT_COUNTER 0x01
#define CS_LFXT_FAULT_COUNTER 0x02
#define CS_FAULT_COUNTER_4096_CYCLES FCNTLF_0
#define CS_FAULT_COUNTER_8192_CYCLES FCNTLF_1
#define CS_FAULT_COUNTER_16384_CYCLES FCNTLF_2
#define CS_FAULT_COUNTER_32768_CYCLES FCNTLF_3
#define CS_FAULT_COUNTER_4096_CYCLES CS_CTL3_FCNTLF_0
#define CS_FAULT_COUNTER_8192_CYCLES CS_CTL3_FCNTLF_1
#define CS_FAULT_COUNTER_16384_CYCLES CS_CTL3_FCNTLF_2
#define CS_FAULT_COUNTER_32768_CYCLES CS_CTL3_FCNTLF_3
#define CS_OVER32MHZ 0x01
#define CS_UNDER32MHZ 0x02
#define DEVICE_PG1_1 0x42
//******************************************************************************
//
@ -188,7 +189,11 @@ extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
//!
//! Note that this function is blocking and will wait on the appropriate bit
//! to be set in the CSSTAT READY register to be set before setting the clock
//! source
//! source.
//!
//! Also note that when HSMCLK and SMCLK share the same clock signal. If you
//! change the clock signal for HSMCLK, the clock signal for SMCLK will change
//! also (and vice-versa).
//!
//! HFXTCLK is not available for BCLK or ACLK.
//!
@ -235,11 +240,10 @@ extern void CS_initClockSignal(uint32_t selectedClockSignal,
//! \param bypassMode When this variable is set, the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startHFXT(bool bypassMode);
extern bool CS_startHFXT(bool bypassMode);
//******************************************************************************
//
@ -257,10 +261,10 @@ extern void CS_startHFXT(bool bypassMode);
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
extern bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
//******************************************************************************
//
@ -283,11 +287,10 @@ extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startLFXT(uint32_t xtDrive);
extern bool CS_startLFXT(uint32_t xtDrive);
//******************************************************************************
//
@ -315,10 +318,10 @@ extern void CS_startLFXT(uint32_t xtDrive);
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
//! \return NONE
//! \return true if started correctly, false otherwise
//
//******************************************************************************
extern void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
extern bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
//******************************************************************************
//
@ -524,12 +527,17 @@ extern void CS_disableDCOExternalResistor(void);
//! default, the value in the CS module is populated by the calibration
//! data of the suggested external resistor (see device datasheet).
//!
//! \param uiCalData is the calibration data constant for the external resistor.
//! \param calData is the calibration data constant for the external resistor.
//!
//! \param freqRange is the range of the DCO to set the external calibration
//! for. Frequencies above 32MHZ have a different calibration value
//! than frequencies below 32MHZ.
//!
//! \return None
//
//******************************************************************************
extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData);
extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData,
uint_fast8_t freqRange);
//******************************************************************************
//
@ -647,13 +655,9 @@ extern void CS_startFaultCounter(uint_fast8_t counterSelect,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! This function enables the indicated clock system interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
@ -678,13 +682,9 @@ extern void CS_enableInterrupt(uint32_t flags);
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@ -704,15 +704,10 @@ extern void CS_disableInterrupt(uint32_t flags);
//! \return The current interrupt status, enumerated as a bit field of
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_DCO_SHORT_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@ -728,15 +723,10 @@ extern uint32_t CS_getEnabledInterruptStatus(void);
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_DCO_SHORT_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@ -753,15 +743,9 @@ extern uint32_t CS_getInterruptStatus(void);
//! be a logical OR of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
//! - \b CS_DCORESISTOR_FAULT,
//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
//! - \b CS_PLL_OUTOFLOCK,
//! - \b CS_PLL_OUTOFSIGNAL,
//! - \b CS_PLL_OUTOFRANGE,
//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! The specified clock system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

120
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,7 +45,7 @@ void DMA_enableModule(void)
//
// Set the master enable bit in the config register.
//
DMA->rCFG.r = DMA_CFG_;
DMA_Control->CFG = DMA_CFG_MASTEN;
}
void DMA_disableModule(void)
@ -53,7 +53,7 @@ void DMA_disableModule(void)
//
// Clear the master enable bit in the config register.
//
DMA->rCFG.r = 0;
DMA_Control->CFG = 0;
}
uint32_t DMA_getErrorStatus(void)
@ -61,7 +61,7 @@ uint32_t DMA_getErrorStatus(void)
//
// Return the DMA error status.
//
return DMA->rERRCLR.r;
return DMA_Control->ERRCLR;
}
void DMA_clearErrorStatus(void)
@ -69,7 +69,7 @@ void DMA_clearErrorStatus(void)
//
// Clear the DMA error interrupt.
//
DMA->rERRCLR.r = 1;
DMA_Control->ERRCLR = 1;
}
void DMA_enableChannel(uint32_t channelNum)
@ -82,7 +82,7 @@ void DMA_enableChannel(uint32_t channelNum)
//
// Set the bit for this channel in the enable set register.
//
DMA->rENASET = 1 << (channelNum & 0x0F);
DMA_Control->ENASET = 1 << (channelNum & 0x0F);
}
void DMA_disableChannel(uint32_t channelNum)
@ -95,7 +95,7 @@ void DMA_disableChannel(uint32_t channelNum)
//
// Set the bit for this channel in the enable clear register.
//
DMA->rENACLR = 1 << (channelNum & 0x0F);
DMA_Control->ENACLR = 1 << (channelNum & 0x0F);
}
bool DMA_isChannelEnabled(uint32_t channelNum)
@ -109,7 +109,7 @@ bool DMA_isChannelEnabled(uint32_t channelNum)
// AND the specified channel bit with the enable register and return the
// result.
//
return ((DMA->rENASET & (1 << (channelNum & 0x0F))) ? true : false);
return ((DMA_Control->ENASET & (1 << (channelNum & 0x0F))) ? true : false);
}
void DMA_setControlBase(void *controlTable)
@ -123,7 +123,7 @@ void DMA_setControlBase(void *controlTable)
//
// Program the base address into the register.
//
DMA->rCTLBASE.r = (uint32_t) controlTable;
DMA_Control->CTLBASE = (uint32_t) controlTable;
}
void* DMA_getControlBase(void)
@ -132,7 +132,7 @@ void* DMA_getControlBase(void)
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA->rCTLBASE.r);
return ((void *) DMA_Control->CTLBASE);
}
void* DMA_getControlAlternateBase(void)
@ -141,7 +141,7 @@ void* DMA_getControlAlternateBase(void)
// Read the current value of the control base register and return it to
// the caller.
//
return ((void *) DMA->rATLBASE);
return ((void *) DMA_Control->ATLBASE);
}
void DMA_requestChannel(uint32_t channelNum)
@ -154,7 +154,7 @@ void DMA_requestChannel(uint32_t channelNum)
//
// Set the bit for this channel in the software DMA request register.
//
DMA->rSWREQ = 1 << (channelNum & 0x0F);
DMA_Control->SWREQ = 1 << (channelNum & 0x0F);
}
void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
@ -181,7 +181,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA->rUSEBURSTSET = 1 << channelNum;
DMA_Control->USEBURSTSET = 1 << channelNum;
}
//
@ -190,7 +190,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA->rALTSET = 1 << channelNum;
DMA_Control->ALTSET = 1 << channelNum;
}
//
@ -198,7 +198,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA->rPRIOSET = 1 << channelNum;
DMA_Control->PRIOSET = 1 << channelNum;
}
//
@ -206,7 +206,7 @@ void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA->rREQMASKSET = 1 << channelNum;
DMA_Control->REQMASKSET = 1 << channelNum;
}
}
@ -234,7 +234,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_USEBURST)
{
DMA->rUSEBURSTCLR = 1 << channelNum;
DMA_Control->USEBURSTCLR = 1 << channelNum;
}
//
@ -243,7 +243,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_ALTSELECT)
{
DMA->rALTCLR = 1 << channelNum;
DMA_Control->ALTCLR = 1 << channelNum;
}
//
@ -251,7 +251,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
DMA->rPRIOCLR = 1 << channelNum;
DMA_Control->PRIOCLR = 1 << channelNum;
}
//
@ -259,7 +259,7 @@ void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
//
if (attr & UDMA_ATTR_REQMASK)
{
DMA->rREQMASKCLR = 1 << channelNum;
DMA_Control->REQMASKCLR = 1 << channelNum;
}
}
@ -282,7 +282,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if useburst bit is set for this channel.
//
if (DMA->rUSEBURSTSET & (1 << channelNum))
if (DMA_Control->USEBURSTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_USEBURST;
}
@ -290,7 +290,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if the alternate control bit is set for this channel.
//
if (DMA->rALTSET & (1 << channelNum))
if (DMA_Control->ALTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_ALTSELECT;
}
@ -298,7 +298,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if the high priority bit is set for this channel.
//
if (DMA->rPRIOSET & (1 << channelNum))
if (DMA_Control->PRIOSET & (1 << channelNum))
{
attr |= UDMA_ATTR_HIGH_PRIORITY;
}
@ -306,7 +306,7 @@ uint32_t DMA_getChannelAttribute(uint32_t channelNum)
//
// Check to see if the request mask bit is set for this channel.
//
if (DMA->rREQMASKSET & (1 << channelNum))
if (DMA_Control->REQMASKSET & (1 << channelNum))
{
attr |= UDMA_ATTR_REQMASK;
}
@ -325,7 +325,7 @@ void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA_Control->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@ -337,7 +337,7 @@ void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
//
// Get the base address of the control table.
//
pCtl = (DMA_ControlTable *) DMA->rCTLBASE.r;
pCtl = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off the fields to be
@ -361,7 +361,7 @@ void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
ASSERT((transferSize != 0) && (transferSize <= 1024));
@ -375,7 +375,7 @@ void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off the mode and size
@ -481,7 +481,7 @@ void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
// Check the parameters
//
ASSERT((channelNum & 0xffff) < 8);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
ASSERT(taskList != 0);
ASSERT(taskCount <= 1024);
ASSERT(taskCount != 0);
@ -496,7 +496,7 @@ void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get a handy pointer to the task list
@ -537,7 +537,7 @@ void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
// alt bit here to ensure that it is always cleared before a new SG
// transfer is started.
//
DMA->rALTCLR = 1 << channelNum;
DMA_Control->ALTCLR = 1 << channelNum;
}
uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
@ -549,7 +549,7 @@ uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 16);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@ -561,7 +561,7 @@ uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off all but the size field
@ -601,7 +601,7 @@ uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
ASSERT(DMA->rCTLBASE != 0);
ASSERT(DMA->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@ -613,7 +613,7 @@ uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
//
// Get the base address of the control table.
//
controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off all but the mode field.
@ -649,7 +649,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH0_EUSCIB1TX3:
case DMA_CH0_TIMERA0CCR0:
case DMA_CH0_AESTRIGGER0:
DMA->rCH0_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F;
break;
case DMA_CH1_RESERVED0:
case DMA_CH1_EUSCIA0RX:
@ -659,7 +659,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH1_EUSCIB1RX3:
case DMA_CH1_TIMERA0CCR2:
case DMA_CH1_AESTRIGGER1:
DMA->rCH1_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F;
break;
case DMA_CH2_RESERVED0:
case DMA_CH2_EUSCIA1TX:
@ -669,7 +669,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH2_EUSCIB2TX3:
case DMA_CH2_TIMERA1CCR0:
case DMA_CH2_AESTRIGGER2:
DMA->rCH2_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F;
break;
case DMA_CH3_RESERVED0:
case DMA_CH3_EUSCIA1RX:
@ -679,7 +679,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH3_EUSCIB2RX3:
case DMA_CH3_TIMERA1CCR2:
case DMA_CH3_RESERVED1:
DMA->rCH3_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F;
break;
case DMA_CH4_RESERVED0:
case DMA_CH4_EUSCIA2TX:
@ -689,7 +689,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH4_EUSCIB3TX3:
case DMA_CH4_TIMERA2CCR0:
case DMA_CH4_RESERVED1:
DMA->rCH4_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F;
break;
case DMA_CH5_RESERVED0:
case DMA_CH5_EUSCIA2RX:
@ -699,7 +699,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH5_EUSCIB3RX3:
case DMA_CH5_TIMERA2CCR2:
case DMA_CH5_RESERVED1:
DMA->rCH5_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F;
break;
case DMA_CH6_RESERVED0:
case DMA_CH6_EUSCIA3TX:
@ -709,7 +709,7 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH6_EUSCIB0TX3:
case DMA_CH6_TIMERA3CCR0:
case DMA_CH6_EXTERNALPIN:
DMA->rCH6_SRCCFG.r = (mapping >> 24) & 0x1F;
DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F;
break;
case DMA_CH7_RESERVED0:
case DMA_CH7_EUSCIA3RX:
@ -718,8 +718,8 @@ void DMA_assignChannel(uint32_t mapping)
case DMA_CH7_EUSCIB1RX2:
case DMA_CH7_EUSCIB0RX3:
case DMA_CH7_TIMERA3CCR2:
case DMA_CH7_ADC12C:
DMA->rCH7_SRCCFG.r = (mapping >> 24) & 0x1F;
case DMA_CH7_ADC14:
DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F;
break;
default:
ASSERT(false);
@ -735,16 +735,16 @@ void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r = (DMA->rINT1_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r = (DMA->rINT2_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r = (DMA->rINT3_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
| channel;
DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG
& ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
}
/* Enabling the assigned interrupt */
@ -753,17 +753,17 @@ void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
void DMA_requestSoftwareTransfer(uint32_t channel)
{
DMA->rSW_CHTRIG.r |= (1 << channel);
DMA_Channel->SW_CHTRIG |= (1 << channel);
}
uint32_t DMA_getInterruptStatus(void)
{
return DMA->rINT0_SRCFLG.r;
return DMA_Channel->INT0_SRCFLG;
}
void DMA_clearInterruptFlag(uint32_t channel)
{
DMA->rINT0_CLRFLG.r |= (1 << channel);
DMA_Channel->INT0_CLRFLG |= (1 << channel);
}
void DMA_enableInterrupt(uint32_t interruptNumber)
@ -775,13 +775,13 @@ void DMA_enableInterrupt(uint32_t interruptNumber)
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r |= DMA_INT1_SRCCFG_EN;
DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r |= DMA_INT2_SRCCFG_EN;
DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r |= DMA_INT3_SRCCFG_EN;
DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN;
}
}
@ -795,13 +795,13 @@ void DMA_disableInterrupt(uint32_t interruptNumber)
if (interruptNumber == DMA_INT1)
{
DMA->rINT1_SRCCFG.r &= ~DMA_INT1_SRCCFG_EN;
DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
DMA->rINT2_SRCCFG.r &= ~DMA_INT2_SRCCFG_EN;
DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
DMA->rINT3_SRCCFG.r &= ~DMA_INT3_SRCCFG_EN;
DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN;
}
}

6
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -348,7 +348,7 @@ typedef struct _DMA_ControlTable
#define DMA_CH7_EUSCIB1RX2 0x04000007
#define DMA_CH7_EUSCIB0RX3 0x05000007
#define DMA_CH7_TIMERA3CCR2 0x06000007
#define DMA_CH7_ADC12C 0x07000007
#define DMA_CH7_ADC14 0x07000007
//
// Different interrupt handlers to pass into DMA_registerInterrupt and

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -39,7 +39,7 @@
#include <msp.h>
#define EUSCI_A_CMSIS(x) ((EUSCI_A0_Type *) x)
#define EUSCI_B_CMSIS(x) ((EUSCI_B0_Type *) x)
#define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x)
#define EUSCI_B_CMSIS(x) ((EUSCI_B_Type *) x)
#endif /* EUSCI_H_ */

1195
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
View file

File diff suppressed because it is too large Load diff

168
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -84,7 +84,7 @@ extern "C"
#define FLASH_MARGIN0B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_9
#define FLASH_MARGIN1B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_10
#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE 0x70000
#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7
#define FLASH_BANK0 0x00
#define FLASH_BANK1 0x01
@ -146,13 +146,8 @@ extern "C"
#define FLASH_COLLATED_WRITE_MODE 0x01
#define FLASH_IMMEDIATE_WRITE_MODE 0x02
#define FlashInternal_eraseSector \
((bool (*)(uint32_t addr, \
bool verify))ROM_FLASHCTLTABLE[9])
#define FlashInternal_performMassErase \
((bool (*)(bool verify))ROM_FLASHCTLTABLE[8])
#define __INFO_FLASH_TECH_START__ 0x00200000
#define __INFO_FLASH_TECH_MIDDLE__ 0x00202000
//*****************************************************************************
@ -160,6 +155,32 @@ extern "C"
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Calculates the flash bank and sector number given an address. Stores the
//! results into the two pointers given as parameters. The user must provide
//! a valid memory address (an address in SRAM for example will give an invalid
//! result).
//!
//! \param addr Address to calculate the bank/sector information for
//!
//! \param sectorNum The sector number will be stored in here after the function
//! completes.
//!
//! \param sectorNum The bank number will be stored in here after the function
//! completes.
//!
//! \note For simplicity, this API only works with address in MAIN flash memory.
//! For calculating the sector/bank number of an address in info memory,
//! please refer to your device datasheet/
//!
//! \return None.
//
//*****************************************************************************
extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
uint32_t *bankNum);
//*****************************************************************************
//
//! Enables read buffering on accesses to a specified bank of flash memory
@ -251,6 +272,11 @@ extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection disabled false otherwise.
//
//*****************************************************************************
@ -308,6 +334,11 @@ extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace,
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
@ -364,6 +395,11 @@ extern bool FlashCtl_protectSector(uint_fast8_t memorySpace,
//! depending on the specific device. Also, for INFO memory space, only sectors
//! FLASH_SECTOR0 and FLASH_SECTOR1 will exist.
//!
//! \note Not all devices will contain a dedicated INFO memory. Please check the
//! device datasheet to see if your device has INFO memory available for use.
//! For devices without INFO memory, any operation related to the INFO memory
//! will be ignored by the hardware.
//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
@ -384,13 +420,25 @@ extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace,
//! of 32 zeros, or a high pattern (each register will be checked versus a
//! pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN
//!
//! Note that there are no sector/boundary restrictions for this function,
//! \note There are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot verify a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if memory verification is successful, false otherwise.
//
@ -403,14 +451,38 @@ extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
//! Performs a mass erase on all unprotected flash sectors. Protected sectors
//! are ignored.
//!
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if mass erase completes successfully, false otherwise
//
//*****************************************************************************
extern bool FlashCtl_performMassErase(void);
//*****************************************************************************
//
//! Initiates a mass erase and returns control back to the program. This is a
//! non-blocking function, however it is the user's responsibility to perform
//! the necessary verification requirements after the interrupt is set to
//! signify completion.
//!
//! \return None
//
//*****************************************************************************
extern void FlashCtl_initiateMassErase(void);
//*****************************************************************************
//
//! Erases a sector of MAIN or INFO flash memory.
@ -421,8 +493,20 @@ extern bool FlashCtl_performMassErase(void);
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot erase a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return true if sector erase is successful, false otherwise.
//
@ -444,8 +528,20 @@ extern bool FlashCtl_eraseSector(uint32_t addr);
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
//! Note that this function is blocking and will not exit until operation has
//! either completed or failed due to an error.
//! \note This function is blocking and will not exit until operation has
//! either completed or failed due to an error. Furthermore, given the
//! complex verification requirements of the flash controller, master
//! interrupts are disabled throughout execution of this function. The original
//! interrupt context is saved at the start of execution and restored prior
//! to exit of the API.
//!
//! \note Due to the hardware limitations of the flash controller, this
//! function cannot program a memory adress in the same flash bank that it
//! is executing from. If using the ROM version of this API (by using the
//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
//! in flash then special care needs to be taken to ensure no code execution
//! or reads happen in the flash bank being programmed while this API is
//! being executed.
//!
//! \return Whether or not the program succeeded
//
@ -794,6 +890,40 @@ extern void FlashCtl_registerInterrupt(void (*intHandler)(void));
//*****************************************************************************
extern void FlashCtl_unregisterInterrupt(void);
//*****************************************************************************
//
//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
//! function simply initaites the sector erase, but does no verification
//! which is required by the flash controller. The user must manually set
//! and enable interrupts on the flash controller to fire on erase completion
//! and then use the FlashCtl_verifyMemory function to verify that the sector
//! was actually erased
//!
//! \param addr The start of the sector to erase. Note that with flash,
//! the minimum allowed size that can be erased is a flash sector
//! (which is 4KB on the MSP432 family). If an address is provided to
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
//! \return None
//
//*****************************************************************************
extern void FlashCtl_initiateSectorErase(uint32_t addr);
/* The following functions are advanced functions that are used by the flash
* driver to remask a failed bit in the event of a post or pre verification
* failure. They are meant to be advanced functions and should not be used
* by the majority of users (unless you are writing your own flash driver).
*/
extern uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr);
extern uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr);
extern uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr);
extern uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr);
extern void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size);
extern void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.

16
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,8 +41,8 @@ void FPU_enableModule(void)
//
// Enable the coprocessors used by the floating-point unit.
//
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_M | SCB_CPACR_CP10_M))
| SCB_CPACR_CP11_M | SCB_CPACR_CP10_M);
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK))
| SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK);
}
void FPU_disableModule(void)
@ -50,7 +50,7 @@ void FPU_disableModule(void)
//
// Disable the coprocessors used by the floating-point unit.
//
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_M | SCB_CPACR_CP11_M)));
SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK)));
}
void FPU_enableStacking(void)
@ -60,7 +60,7 @@ void FPU_enableStacking(void)
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN) | FPU_FPCCR_ASPEN;
FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN_Msk) | FPU_FPCCR_ASPEN_Msk;
}
void FPU_enableLazyStacking(void)
@ -69,7 +69,7 @@ void FPU_enableLazyStacking(void)
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
FPU->FPCCR |= FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN;
FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
}
void FPU_disableStacking(void)
@ -78,7 +78,7 @@ void FPU_disableStacking(void)
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
FPU->FPCCR &= ~(FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN);
FPU->FPCCR &= ~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk);
}
void FPU_setHalfPrecisionMode(uint32_t mode)

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

141
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,6 +41,21 @@
#include <gpio.h>
#include <debug.h>
#include <interrupt.h>
#include <hw_memmap.h>
/* DriverLib internal GPIO register offset for optimized performace */
#define OFS_LIB_PAIN ((uint32_t)&P1->IN - (uint32_t)P1)
#define OFS_LIB_PAOUT ((uint32_t)&P1->OUT - (uint32_t)P1)
#define OFS_LIB_PADIR ((uint32_t)&P1->DIR - (uint32_t)P1)
#define OFS_LIB_PAREN ((uint32_t)&P1->REN - (uint32_t)P1)
#define OFS_LIB_PADS ((uint32_t)&P1->DS - (uint32_t)P1)
#define OFS_LIB_PASEL0 ((uint32_t)&P1->SEL0 - (uint32_t)P1)
#define OFS_LIB_PASEL1 ((uint32_t)&P1->SEL1 - (uint32_t)P1)
#define OFS_LIB_PAIE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_PAIES ((uint32_t)&P1->IES - (uint32_t)P1)
#define OFS_LIB_PAIFG ((uint32_t)&P1->IFG - (uint32_t)P1)
#define OFS_LIB_P1IE ((uint32_t)&P1->IE - (uint32_t)P1)
#define OFS_LIB_P2IE ((uint32_t)&P2->IE - (uint32_t)P2)
static const uint32_t GPIO_PORT_TO_INT[] =
{ 0x00,
@ -51,41 +66,39 @@ INT_PORT4,
INT_PORT5,
INT_PORT6 };
static const uint32_t GPIO_PORT_TO_BASE[] =
static uint32_t GPIO_PORT_TO_BASE[] =
{ 0x00,
0x40004C00,
0x40004C01,
0x40004C20,
0x40004C21,
0x40004C40,
0x40004C41,
0x40004C60,
0x40004C61,
0x40004C80,
0x40004C81,
0x40004D20
(uint32_t)P1,
(uint32_t)P1+1,
(uint32_t)P3,
(uint32_t)P3+1,
(uint32_t)P5,
(uint32_t)P5+1,
(uint32_t)P7,
(uint32_t)P7+1,
(uint32_t)P9,
(uint32_t)P9+1,
(uint32_t)PJ
};
void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
return;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
}
void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAREN) &= ~selectedPins;
}
@ -95,20 +108,20 @@ void GPIO_setAsPeripheralModuleFunctionOutputPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
}
}
@ -119,20 +132,20 @@ void GPIO_setAsPeripheralModuleFunctionInputPin(uint_fast8_t selectedPort,
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
}
}
@ -144,7 +157,7 @@ void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
}
@ -154,7 +167,7 @@ void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
}
@ -164,7 +177,7 @@ void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) ^= selectedPins;
}
@ -174,12 +187,12 @@ void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
}
@ -189,21 +202,21 @@ void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
}
uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
uint16_t inputPinValue;
uint_fast16_t inputPinValue;
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins);
inputPinValue = HWREG16(baseAddress + OFS_LIB_PAIN) & (selectedPins);
if (inputPinValue > 0)
return GPIO_INPUT_PIN_HIGH;
@ -216,7 +229,7 @@ void GPIO_enableInterrupt(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIE) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIE) |= selectedPins;
}
@ -226,7 +239,7 @@ void GPIO_disableInterrupt(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIE) &= ~selectedPins;
}
@ -236,7 +249,7 @@ uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
return HWREG16(baseAddress + OFS_PAIFG) & selectedPins;
return HWREG16(baseAddress + OFS_LIB_PAIFG) & selectedPins;
}
@ -247,7 +260,7 @@ void GPIO_clearInterruptFlag(uint_fast8_t selectedPort,
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIFG) &= ~selectedPins;
}
@ -259,9 +272,9 @@ void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort,
if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)
HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIES) &= ~selectedPins;
else
HWREG16(baseAddress + OFS_PAIES) |= selectedPins;
HWREG16(baseAddress + OFS_LIB_PAIES) |= selectedPins;
}
uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
@ -281,15 +294,15 @@ uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
case GPIO_PORT_P5:
case GPIO_PORT_P7:
case GPIO_PORT_P9:
return (HWREG8(baseAddr + OFS_P1IE) & pendingInts);
return (HWREG8(baseAddr + OFS_LIB_P1IE) & pendingInts);
case GPIO_PORT_P2:
case GPIO_PORT_P4:
case GPIO_PORT_P6:
case GPIO_PORT_P8:
case GPIO_PORT_P10:
return (HWREG8(baseAddr + OFS_P2IE) & pendingInts);
return (HWREG8(baseAddr + OFS_LIB_P2IE) & pendingInts);
case GPIO_PORT_PJ:
return (HWREG16(baseAddr + OFS_PAIE) & pendingInts);
return (HWREG16(baseAddr + OFS_LIB_PAIE) & pendingInts);
default:
return 0;
}
@ -303,7 +316,7 @@ void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
HWREG8(baseAddr + OFS_PADS) |= selectedPins;
HWREG8(baseAddr + OFS_LIB_PADS) |= selectedPins;
}
@ -314,7 +327,7 @@ void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
HWREG8(baseAddr + OFS_PADS) &= ~selectedPins;
HWREG8(baseAddr + OFS_LIB_PADS) &= ~selectedPins;
}

20
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -68,8 +68,14 @@ extern "C"
#define GPIO_PORT_P8 8
#define GPIO_PORT_P9 9
#define GPIO_PORT_P10 10
#define GPIO_PORT_PJ 11
#define GPIO_PORT_PA 1
#define GPIO_PORT_PB 3
#define GPIO_PORT_PC 5
#define GPIO_PORT_PD 7
#define GPIO_PORT_PE 9
#define GPIO_PORT_PJ 11
#define GPIO_PIN0 (0x0001)
#define GPIO_PIN1 (0x0002)
#define GPIO_PIN2 (0x0004)
@ -406,8 +412,6 @@ extern void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
//! - \b GPIO_PIN14
//! - \b GPIO_PIN15
//!
//! Modified bits of \b PxOUT register.
//!
//! \return None
//
//*****************************************************************************
@ -998,7 +1002,11 @@ extern void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
//*****************************************************************************
extern void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
uint_fast8_t selectedPins);
/* Backwards Compatibility Layer */
#define GPIO_selectInterruptEdge GPIO_interruptEdgeSelect
#define GPIO_clearInterrupt GPIO_clearInterruptFlag
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.

87
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/hw_memmap.h Normal file
View file

@ -0,0 +1,87 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
#ifndef __HW_MEMMAP__
#define __HW_MEMMAP__
#define __DRIVERLIB_MSP432P4XX_FAMILY__
//*****************************************************************************
//
// Include device specific header file
//
//*****************************************************************************
//*****************************************************************************
//
// SUCCESS and FAILURE for API return value
//
//*****************************************************************************
#define STATUS_SUCCESS 0x01
#define STATUS_FAIL 0x00
//*****************************************************************************
//
// Macros for hardware access
//
//*****************************************************************************
#define HWREG8(x) (*((volatile uint8_t *)(x)))
#define HWREG16(x) (*((volatile uint16_t *)(x)))
#define HWREG32(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (HWREG16(x))
#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
/******************************************************************************
* Device memory map *
******************************************************************************/
#define __MAIN_MEMORY_START__ (0x00000000) /**< Main Flash memory start address */
#define __MAIN_MEMORY_END__ (0x0003FFFF) /**< Main Flash memory end address */
#define __BSL_MEMORY_START__ (0x00202000) /**< BSL memory start address */
#define __BSL_MEMORY_END__ (0x00203FFF) /**< BSL memory end address */
#define __SRAM_START__ (0x20000000) /**< SRAM memory start address */
#define __SRAM_END__ (0x2000FFFF) /**< SRAM memory end address */
/******************************************************************************
* Definitions for 8/16/32-bit wide bit band access *
******************************************************************************/
#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#endif // #ifndef __HW_MEMMAP__

283
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,10 +37,11 @@
#include <i2c.h>
#include <interrupt.h>
#include <debug.h>
#include <hw_memmap.h>
void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
{
uint16_t preScalarValue;
uint_fast16_t preScalarValue;
ASSERT(
(EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
@ -49,7 +50,8 @@ void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *confi
ASSERT(
(EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
|| (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate));
|| (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)
|| (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate));
ASSERT(
(EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
@ -59,15 +61,16 @@ void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *confi
== config->autoSTOPGeneration));
/* Disable the USCI module and clears the other bits of control register */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
/* Configure Automatic STOP condition generation */
EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r & ~UCASTP_M)
EUSCI_B_CMSIS(moduleInstance)->CTLW1 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW1 & ~EUSCI_B_CTLW1_ASTP_MASK)
| (config->autoSTOPGeneration);
/* Byte Count Threshold */
EUSCI_B_CMSIS(moduleInstance)->rTBCNT.r = config->byteCounterThreshold;
EUSCI_B_CMSIS(moduleInstance)->TBCNT = config->byteCounterThreshold;
/*
* Configure as I2C master mode.
@ -75,10 +78,11 @@ void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *confi
* UCMODE_3 = I2C mode
* UCSYNC = Synchronous mode
*/
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_M)
| (config->selectClockSource | UCMST | UCMODE_3 | UCSYNC
| UCSWRST);
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_B_CTLW0_SSEL_MASK)
| (config->selectClockSource | EUSCI_B_CTLW0_MST
| EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC
| EUSCI_B_CTLW0_SWRST);
/*
* Compute the clock divider that achieves the fastest speed less than or
@ -88,7 +92,7 @@ void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *confi
*/
preScalarValue = (uint16_t) (config->i2cClk / config->dataRate);
EUSCI_B_CMSIS(moduleInstance)->rBRW = preScalarValue;
EUSCI_B_CMSIS(moduleInstance)->BRW = preScalarValue;
}
void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
@ -101,35 +105,38 @@ void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
/* Disable the USCI module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
/* Clear USCI master mode */
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCMST))
| (UCMODE_3 + UCSYNC);
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_MST))
| (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC);
/* Set up the slave address. */
HWREG16(moduleInstance + OFS_UCB0I2COA0 + slaveAddressOffset) = slaveAddress
+ slaveOwnAddressEnable;
HWREG16((uint32_t)&EUSCI_B_CMSIS(moduleInstance)->I2COA0 + slaveAddressOffset) =
slaveAddress + slaveOwnAddressEnable;
}
void I2C_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
0;
}
void I2C_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
;
}
void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress)
{
/* Set the address of the slave with which the master will communicate */
EUSCI_B_CMSIS(moduleInstance)->rI2CSA.r = (slaveAddress);
EUSCI_B_CMSIS(moduleInstance)->I2CSA = (slaveAddress);
}
void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
@ -138,8 +145,8 @@ void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
(EUSCI_B_I2C_TRANSMIT_MODE == mode)
|| (EUSCI_B_I2C_RECEIVE_MODE == mode));
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0
& (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
}
@ -147,88 +154,89 @@ void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
{
//Set USCI in Receive mode
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTR_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TR_OFS) = 0;
//Send start
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= (UCTXSTT + UCTXSTP);
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT + EUSCI_B_CTLW0_TXSTP);
//Poll for receive interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
;
//Send single byte data.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
{
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = transmitData;
}
uint8_t I2C_slaveGetData(uint32_t moduleInstance)
{
//Read a byte.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
uint8_t I2C_isBusBusy(uint32_t moduleInstance)
{
//Return the bus busy status.
return EUSCI_B_CMSIS(moduleInstance)->rSTATW.b.bBBUSY;
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->STATW,
EUSCI_B_STATW_BBUSY_OFS);
}
void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
{
//Store current TXIE status
uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
;
//Send stop condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTXSTP;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TXSTP;
//Clear transmit interrupt flag before enabling interrupt again
EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(UCTXIFG);
EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(EUSCI_B_IFG_TXIFG);
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
}
bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
uint16_t txieStatus;
uint_fast16_t txieStatus;
uint32_t timeout2 = timeout;
ASSERT(timeout > 0);
//Store current TXIE status
txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while ((!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) && --timeout)
while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) && --timeout)
;
//Check if transfer timed out
@ -236,10 +244,10 @@ bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
return false;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout2)
;
@ -248,13 +256,13 @@ bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
//Clear transmit interrupt flag before enabling interrupt again
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,UCTXIFG_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,EUSCI_B_IFG_TXIFG0_OFS) = 0;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
return true;
}
@ -262,43 +270,43 @@ bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
{
//Store current transmit interrupt enable
uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
}
bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
uint16_t txieStatus;
uint_fast16_t txieStatus;
ASSERT(timeout > 0);
//Store current transmit interrupt enable
txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout))
;
@ -307,10 +315,10 @@ bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
return false;
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Reinstate transmit interrupt enable
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
return true;
}
@ -318,16 +326,16 @@ bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
}
bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
@ -336,11 +344,11 @@ bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCTXIFG_OFS)) && --timeout)
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
;
//Check if transfer timed out
@ -349,7 +357,7 @@ bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
return true;
}
@ -357,23 +365,23 @@ bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
}
bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
@ -384,11 +392,11 @@ bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCTXIFG_OFS)) && --timeout)
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
;
//Check if transfer timed out
@ -397,10 +405,10 @@ bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
}
//Send single byte data.
EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout2)
;
@ -409,7 +417,7 @@ bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
return false;
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
return true;
}
@ -417,16 +425,16 @@ bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
{
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
(!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
}
bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
@ -435,11 +443,11 @@ bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCTXIFG_OFS)) && --timeout)
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
;
//Check if transfer timed out
@ -448,7 +456,7 @@ bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
}
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
return 0x01;
}
@ -456,31 +464,33 @@ bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
void I2C_masterReceiveStart(uint32_t moduleInstance)
{
//Set USCI in Receive mode
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCTR)) | UCTXSTT;
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_TR))
| EUSCI_B_CTLW0_TXSTT;
}
uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
{
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.a.bRXBUF;
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
{
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) =
1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS))
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS))
{
// Wait for RX buffer
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG, UCRXIFG_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
;
}
/* Capture data from receive buffer after setting stop bit due to
MSP430 I2C critical timing. */
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
@ -491,10 +501,10 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
ASSERT(timeout > 0);
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
//Wait for Stop to finish
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS)
while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS)
&& --timeout)
;
@ -503,7 +513,7 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
return false;
// Wait for RX buffer
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
&& --timeout2)
;
@ -513,7 +523,7 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
//Capture data from receive buffer after setting stop bit due to
//MSP430 I2C critical timing.
*txData = (EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF);
*txData = (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
return true;
}
@ -521,58 +531,63 @@ bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
{
//Send stop condition.
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
}
uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
{
//Polling RXIFG0 if RXIE is not enabled
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCRXIE0_OFS))
if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS))
{
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
UCRXIFG0_OFS))
while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
EUSCI_B_IFG_RXIFG0_OFS))
;
}
//Read a byte.
return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK) ;
}
uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCB0RXBUF;
return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->RXBUF;
}
uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCB0TXBUF;
return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
}
uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
{
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS);
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTP_OFS);
}
bool I2C_masterIsStartSent(uint32_t moduleInstance)
{
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTT_OFS);
return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
EUSCI_B_CTLW0_TXSTT_OFS);
}
void I2C_masterSendStart(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTT_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTT_OFS) =
1;
}
void I2C_enableMultiMasterMode(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 1;
}
void I2C_disableMultiMasterMode(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 0;
}
void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
@ -597,7 +612,7 @@ void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Enable the interrupt masked bit
EUSCI_B_CMSIS(moduleInstance)->rIE.r |= mask;
EUSCI_B_CMSIS(moduleInstance)->IE |= mask;
}
void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
@ -622,7 +637,7 @@ void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Disable the interrupt masked bit
EUSCI_B_CMSIS(moduleInstance)->rIE.r &= ~(mask);
EUSCI_B_CMSIS(moduleInstance)->IE &= ~(mask);
}
void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
@ -646,7 +661,7 @@ void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Clear the I2C interrupt source.
EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(mask);
}
uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
@ -670,41 +685,41 @@ uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Return the interrupt status of the request masked bit.
return EUSCI_B_CMSIS(moduleInstance)->rIFG.r & mask;
return EUSCI_B_CMSIS(moduleInstance)->IFG & mask;
}
uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
{
return I2C_getInterruptStatus(moduleInstance,
EUSCI_B_CMSIS(moduleInstance)->rIE.r);
EUSCI_B_CMSIS(moduleInstance)->IE);
}
uint_fast16_t I2C_getMode(uint32_t moduleInstance)
{
//Read the I2C mode.
return (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & UCTR);
return (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & EUSCI_B_CTLW0_TR);
}
void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
case EUSCI_B0_MODULE:
case EUSCI_B0_BASE:
Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB0);
break;
case EUSCI_B1_MODULE:
case EUSCI_B1_BASE:
Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_MODULE
case EUSCI_B2_MODULE:
#ifdef EUSCI_B2_BASE
case EUSCI_B2_BASE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_MODULE
case EUSCI_B3_MODULE:
#ifdef EUSCI_B3_BASE
case EUSCI_B3_BASE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
@ -718,22 +733,22 @@ void I2C_unregisterInterrupt(uint32_t moduleInstance)
{
switch (moduleInstance)
{
case EUSCI_B0_MODULE:
case EUSCI_B0_BASE:
Interrupt_disableInterrupt(INT_EUSCIB0);
Interrupt_unregisterInterrupt(INT_EUSCIB0);
break;
case EUSCI_B1_MODULE:
case EUSCI_B1_BASE:
Interrupt_disableInterrupt(INT_EUSCIB1);
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_MODULE
case EUSCI_B2_MODULE:
#ifdef EUSCI_B2_BASE
case EUSCI_B2_BASE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_MODULE
case EUSCI_B3_MODULE:
#ifdef EUSCI_B3_BASE
case EUSCI_B3_BASE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
@ -742,3 +757,9 @@ void I2C_unregisterInterrupt(uint32_t moduleInstance)
ASSERT(false);
}
}
void I2C_slaveSendNAK(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXNACK_OFS)
= 1;
}

417
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -60,15 +60,17 @@ extern "C"
#include <msp.h>
#include "eusci.h"
#define EUSCI_B_I2C_NO_AUTO_STOP UCASTP_0
#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG UCASTP_1
#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD UCASTP_2
#define EUSCI_B_I2C_NO_AUTO_STOP EUSCI_B_CTLW1_ASTP_0
#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG EUSCI_B_CTLW1_ASTP_1
#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD \
EUSCI_B_CTLW1_ASTP_2
#define EUSCI_B_I2C_SET_DATA_RATE_1MBPS 1000000
#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000
#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS 100000
#define EUSCI_B_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_B_I2C_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK
#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK
#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 0x00
#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 0x02
@ -76,39 +78,39 @@ extern "C"
#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 0x06
#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE 0x00
#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE UCOAEN
#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE EUSCI_B_I2COA0_OAEN
#define EUSCI_B_I2C_TRANSMIT_MODE UCTR
#define EUSCI_B_I2C_TRANSMIT_MODE EUSCI_B_CTLW0_TR
#define EUSCI_B_I2C_RECEIVE_MODE 0x00
#define EUSCI_B_I2C_NAK_INTERRUPT UCNACKIE
#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT UCALIE
#define EUSCI_B_I2C_STOP_INTERRUPT UCSTPIE
#define EUSCI_B_I2C_START_INTERRUPT UCSTTIE
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 UCTXIE0
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 UCTXIE1
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 UCTXIE2
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 UCTXIE3
#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 UCRXIE0
#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 UCRXIE1
#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 UCRXIE2
#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 UCRXIE3
#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT UCBIT9IE
#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT UCCLTOIE
#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT UCBCNTIE
#define EUSCI_B_I2C_NAK_INTERRUPT EUSCI_B_IE_NACKIE
#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT EUSCI_B_IE_ALIE
#define EUSCI_B_I2C_STOP_INTERRUPT EUSCI_B_IE_STPIE
#define EUSCI_B_I2C_START_INTERRUPT EUSCI_B_IE_STTIE
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 EUSCI_B_IE_TXIE0
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 EUSCI_B_IE_TXIE1
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 EUSCI_B_IE_TXIE2
#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 EUSCI_B_IE_TXIE3
#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 EUSCI_B_IE_RXIE0
#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 EUSCI_B_IE_RXIE1
#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 EUSCI_B_IE_RXIE2
#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 EUSCI_B_IE_RXIE3
#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT EUSCI_B_IE_BIT9IE
#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT EUSCI_B_IE_CLTOIE
#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT EUSCI_B_IE_BCNTIE
#define EUSCI_B_I2C_BUS_BUSY UCBBUSY
#define EUSCI_B_I2C_BUS_BUSY EUSCI_B_STATW_BBUSY
#define EUSCI_B_I2C_BUS_NOT_BUSY 0x00
#define EUSCI_B_I2C_STOP_SEND_COMPLETE 0x00
#define EUSCI_B_I2C_SENDING_STOP UCTXSTP
#define EUSCI_B_I2C_SENDING_STOP EUSCI_B_CTLW0_TXSTP
#define EUSCI_B_I2C_START_SEND_COMPLETE 0x00
#define EUSCI_B_I2C_SENDING_START UCTXSTT
#define EUSCI_B_I2C_SENDING_START EUSCI_B_CTLW0_TXSTT
//*****************************************************************************
//
//! \typedef eUSCI_I2C_MasterConfig
//! ypedef eUSCI_I2C_MasterConfig
//! \brief Type definition for \link _eUSCI_I2C_MasterConfig \endlink structure
//!
//! \struct _eUSCI_I2C_MasterConfig
@ -132,10 +134,10 @@ typedef struct
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -154,6 +156,7 @@ typedef struct
//! selectClockSource).
//! \param dataRate set up for selecting data transfer rate.
//! Valid values are
//! - \b EUSCI_B_I2C_SET_DATA_RATE_1MBPS
//! - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS
//! - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS
//! \param byteCounterThreshold sets threshold for automatic STOP or UCSTPIFG
@ -168,10 +171,6 @@ typedef struct
//! bus speed for the master; however I2C module is still disabled till
//! I2C_enableModule is invoked
//!
//! If the parameter \e dataRate is EUSCI_B_I2C_SET_DATA_RATE_400KBPS, then the
//! master block will be set up to transfer data at 400 kbps; otherwise, it will
//! be set up to transfer data at 100 kbps.
//!
//! Modified bits are \b UCMST,UCMODE_3,\b UCSYNC of \b UCBxCTL0 register
//! \b UCSSELx, \b UCSWRST, of \b UCBxCTL1 register
//! \b UCBxBR0 and \b UCBxBR1 registers
@ -187,15 +186,15 @@ extern void I2C_initMaster(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
//! \param slaveAddress 7-bit slave address
//! \param slaveAddress 7-bit or 10-bit slave address
//! \param slaveAddressOffset Own address Offset referred to- 'x' value of
//! UCBxI2COAx. Valid values are:
//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0,
@ -231,10 +230,10 @@ extern void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -253,10 +252,10 @@ extern void I2C_enableModule(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -275,15 +274,15 @@ extern void I2C_disableModule(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
//! \param slaveAddress 7-bit slave address
//! \param slaveAddress 7-bit or 10-bit slave address
//!
//! This function will set the address that the I2C Master will place on the
//! bus when initiating a transaction.
@ -301,10 +300,10 @@ extern void I2C_setSlaveAddress(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -328,10 +327,10 @@ extern void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -353,10 +352,10 @@ extern uint_fast8_t I2C_getMode(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -378,10 +377,10 @@ extern void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -401,10 +400,10 @@ extern uint8_t I2C_slaveGetData(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -426,10 +425,10 @@ extern uint8_t I2C_isBusBusy(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -456,10 +455,10 @@ extern void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -488,10 +487,10 @@ extern bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -518,10 +517,10 @@ extern void I2C_masterSendMultiByteStart(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -549,10 +548,10 @@ extern bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -577,10 +576,10 @@ extern void I2C_masterSendMultiByteNext(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -607,10 +606,10 @@ extern bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -637,10 +636,10 @@ extern void I2C_masterSendMultiByteFinish(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -668,10 +667,10 @@ extern bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -696,10 +695,10 @@ extern void I2C_masterSendMultiByteStop(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -725,10 +724,10 @@ extern bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -750,10 +749,10 @@ extern void I2C_masterReceiveStart(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -775,10 +774,10 @@ extern uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -802,10 +801,10 @@ extern uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -833,10 +832,10 @@ extern bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -857,10 +856,10 @@ extern void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -885,10 +884,10 @@ extern uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -908,10 +907,10 @@ extern uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -931,10 +930,10 @@ extern uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -954,10 +953,10 @@ extern uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -979,10 +978,10 @@ extern uint8_t I2C_masterIsStopSent(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1003,10 +1002,10 @@ extern bool I2C_masterIsStartSent(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1027,10 +1026,10 @@ extern void I2C_masterSendStart(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1053,10 +1052,10 @@ extern void I2C_enableMultiMasterMode(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1079,10 +1078,10 @@ extern void I2C_disableMultiMasterMode(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1126,10 +1125,10 @@ extern void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1173,10 +1172,10 @@ extern void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1203,10 +1202,10 @@ extern void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1250,7 +1249,7 @@ extern void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask);
//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable
//
//*****************************************************************************
uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask);
extern uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask);
//*****************************************************************************
//
@ -1260,10 +1259,10 @@ uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1295,10 +1294,10 @@ extern uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1327,10 +1326,10 @@ extern void I2C_registerInterrupt(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -1347,6 +1346,26 @@ extern void I2C_registerInterrupt(uint32_t moduleInstance,
//*****************************************************************************
extern void I2C_unregisterInterrupt(uint32_t moduleInstance);
//*****************************************************************************
//
//! This function is used by the slave to send a NAK out over the I2C line
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
//! \return None.
//
//*****************************************************************************
extern void I2C_slaveSendNAK(uint32_t moduleInstance);
/* Backwards Compatibility Layer */
#define EUSCI_B_I2C_slaveInit I2C_initSlave
#define EUSCI_B_I2C_enable I2C_enableModule

11
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
View file

@ -1,6 +1,6 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@ -41,12 +41,18 @@
// CMSIS-compatible instruction calls
//*****************************************************************************
#ifndef __cplusplus
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
__attribute__( ( always_inline ) ) static inline void __NOP(void)
{
__asm(" nop");
}
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
@ -58,6 +64,7 @@ __attribute__( ( always_inline ) ) static inline void __wfe(void)
{
__asm(" wfe");
}
#endif
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
@ -194,7 +201,7 @@ static inline void __set_PRIMASK(uint32_t priMask)
#define __SMUAD _smuad
#define __SMUADX _smuadx
#define __SMUSD _smusd
#define __SMUSDX _smusd
#define __SMUSDX _smusdx
#define __SSAT16 _ssat16
#define __SSUB16 _ssub16
#define __SSUB8 _ssub8

1367
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
View file

File diff suppressed because it is too large Load diff

610
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
View file

@ -1,13 +1,10 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -35,6 +32,12 @@
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
@ -45,592 +48,33 @@
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
/** \brief Get Control Register
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
This function returns the content of the Control Register.
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

662
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
View file

@ -1,13 +1,10 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -35,6 +32,12 @@
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
@ -45,641 +48,30 @@
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
/** \brief No Operation
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif

94
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmSimd.h Normal file
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@ -0,0 +1,94 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.20
* @date 02. July 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
#include <cmsis_armcc.h>
#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
#include <cmsis_armcc_V6.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
#include <cmsis_gcc.h>
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

2
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
View file

@ -32,7 +32,7 @@
//
// MSP432 Family Generic Include File
//
// File creation date: 2015-01-02
// File creation date: 2015-10-26
//
//*****************************************************************************

2
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
View file

@ -32,7 +32,7 @@
//
// MSP432 Family Generic Include File
//
// File creation date: 2015-01-05
// File creation date: 2015-10-26
//
//*****************************************************************************

24247
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
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File diff suppressed because it is too large Load diff

29
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
View file

@ -1,6 +1,6 @@
//*****************************************************************************
//
// Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com/
// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@ -34,8 +34,27 @@
//
//****************************************************************************
/******************************************************************************
* Definitions for 8/16/32-bit wide memory access *
******************************************************************************/
#define HWREG8(x) (*((volatile uint8_t *)(x)))
#define HWREG16(x) (*((volatile uint16_t *)(x)))
#define HWREG32(x) (*((volatile uint32_t *)(x)))
#define HWREG(x) (HWREG16(x))
#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
/******************************************************************************
* Definitions for 8/16/32-bit wide bit band access *
******************************************************************************/
#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
// Intrinsics with ARM equivalents
#if defined ( __TMS470__ ) /* TI CGT Compiler */
#if defined ( __TI_ARM__ ) /* TI CGT Compiler */
#include <cmsis_ccs.h>
@ -87,6 +106,7 @@
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#elif defined ( __CC_ARM ) /* ARM Compiler */
@ -118,9 +138,11 @@
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#elif defined ( __GNUC__ ) /* GCC Compiler */
#undef __wfi
#define __wfi() asm(" wfi")
#define __sleep() __wfi()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
@ -149,6 +171,7 @@
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#endif

159
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c → FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/system_msp432p401r.h
View file

@ -1,68 +1,91 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Startup File
//
// File creation date: 2014-07-08
//
//*****************************************************************************
#include <stdint.h>
#include "msp432.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __SYSTEM_CLOCK (2000000)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
Initialize the system
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
WDT_A->rCTL.r = WDTPW + WDTHOLD;
}
/**************************************************************************//**
* @file system_msp432p401r.h
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for
* MSP432P401R
* @version V1.00
* @date 20-Oct-2015
*
* @note View configuration instructions embedded in comments
*
******************************************************************************/
//*****************************************************************************
//
// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#ifndef SYSTEM_MSP432P401R_H
#define SYSTEM_MSP432P401R_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*
* Performs the following initialization steps:
* 1. Enables the FPU
* 2. Halts the WDT
* 3. Enables all SRAM banks
* 4. Sets up power __REGULATOR and VCORE
* 5. Enable Flash wait states if needed
* 6. Change MCLK to desired frequency
* 7. Enable Flash read buffering
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_MSP432P401R_H */

39
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,6 +41,7 @@
#include <debug.h>
#include <cpu.h>
#include <interrupt.h>
#include <hw_memmap.h>
//*****************************************************************************
//
@ -232,7 +233,7 @@ void Interrupt_setPriorityGrouping(uint32_t bits)
//
// Set the priority grouping.
//
SCB->AIRCR = SCB_AIRCR_VECTKEY_M | g_pulPriority[bits];
SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits];
}
uint32_t Interrupt_getPriorityGrouping(void)
@ -311,19 +312,19 @@ void Interrupt_enableInterrupt(uint32_t interruptNumber)
//
// Enable the MemManage interrupt.
//
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA;
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
} else if (interruptNumber == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA;
SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
} else if (interruptNumber == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA;
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
@ -355,19 +356,19 @@ void Interrupt_disableInterrupt(uint32_t interruptNumber)
//
// Disable the MemManage interrupt.
//
SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA);
SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk);
} else if (interruptNumber == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA);
SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA_Msk);
} else if (interruptNumber == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA);
SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA_Msk);
} else if (interruptNumber == FAULT_SYSTICK)
{
//
@ -406,19 +407,19 @@ bool Interrupt_isEnabled(uint32_t interruptNumber)
//
// Check the MemManage interrupt.
//
ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA;
ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA_Msk;
} else if (interruptNumber == FAULT_BUS)
{
//
// Check the bus fault interrupt.
//
ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA;
ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA_Msk;
} else if (interruptNumber == FAULT_USAGE)
{
//
// Check the usage fault interrupt.
//
ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA;
ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
@ -451,19 +452,19 @@ void Interrupt_pendInterrupt(uint32_t interruptNumber)
//
// Pend the NMI interrupt.
//
SCB->ICSR |= SCB_ICSR_NMIPENDSET;
SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk;
} else if (interruptNumber == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSVSET;
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSTSET;
SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk;
} else if (interruptNumber >= 16)
{
//
@ -489,13 +490,13 @@ void Interrupt_unpendInterrupt(uint32_t interruptNumber)
//
// Unpend the PendSV interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSVCLR;
SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
SCB->ICSR |= SCB_ICSR_PENDSTCLR;
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
} else if (interruptNumber >= 16)
{
//
@ -528,10 +529,10 @@ uint32_t Interrupt_getVectorTableAddress(void)
void Interrupt_enableSleepOnIsrExit(void)
{
SCB->SCR |= SCB_SCR_SLEEPONEXIT;
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
}
void Interrupt_disableSleepOnIsrExit(void)
{
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT;
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
}

75
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -60,6 +60,64 @@ extern "C"
#include <stdbool.h>
#include <msp.h>
/******************************************************************************
* NVIC interrupts *
******************************************************************************/
/* System exceptions */
#define FAULT_NMI ( 2) /* NMI fault */
#define FAULT_HARD ( 3) /* Hard fault */
#define FAULT_MPU ( 4) /* MPU fault */
#define FAULT_BUS ( 5) /* Bus fault */
#define FAULT_USAGE ( 6) /* Usage fault */
#define FAULT_SVCALL (11) /* SVCall */
#define FAULT_DEBUG (12) /* Debug monitor */
#define FAULT_PENDSV (14) /* PendSV */
#define FAULT_SYSTICK (15) /* System Tick */
/* External interrupts */
#define INT_PSS (16) /* PSS IRQ */
#define INT_CS (17) /* CS IRQ */
#define INT_PCM (18) /* PCM IRQ */
#define INT_WDT_A (19) /* WDT_A IRQ */
#define INT_FPU (20) /* FPU IRQ */
#define INT_FLCTL (21) /* FLCTL IRQ */
#define INT_COMP_E0 (22) /* COMP_E0 IRQ */
#define INT_COMP_E1 (23) /* COMP_E1 IRQ */
#define INT_TA0_0 (24) /* TA0_0 IRQ */
#define INT_TA0_N (25) /* TA0_N IRQ */
#define INT_TA1_0 (26) /* TA1_0 IRQ */
#define INT_TA1_N (27) /* TA1_N IRQ */
#define INT_TA2_0 (28) /* TA2_0 IRQ */
#define INT_TA2_N (29) /* TA2_N IRQ */
#define INT_TA3_0 (30) /* TA3_0 IRQ */
#define INT_TA3_N (31) /* TA3_N IRQ */
#define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */
#define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */
#define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */
#define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */
#define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */
#define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */
#define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */
#define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */
#define INT_ADC14 (40) /* ADC14 IRQ */
#define INT_T32_INT1 (41) /* T32_INT1 IRQ */
#define INT_T32_INT2 (42) /* T32_INT2 IRQ */
#define INT_T32_INTC (43) /* T32_INTC IRQ */
#define INT_AES256 (44) /* AES256 IRQ */
#define INT_RTC_C (45) /* RTC_C IRQ */
#define INT_DMA_ERR (46) /* DMA_ERR IRQ */
#define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */
#define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */
#define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */
#define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */
#define INT_PORT1 (51) /* PORT1 IRQ */
#define INT_PORT2 (52) /* PORT2 IRQ */
#define INT_PORT3 (53) /* PORT3 IRQ */
#define INT_PORT4 (54) /* PORT4 IRQ */
#define INT_PORT5 (55) /* PORT5 IRQ */
#define INT_PORT6 (56) /* PORT6 IRQ */
#define NUM_INTERRUPTS (56)
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
@ -157,6 +215,11 @@ extern bool Interrupt_disableMaster(void);
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
//! \note This function is only used if the customer wants to specify the
//! interrupt handler at run time. In most cases, this is done through means
//! of the user setting the ISR function pointer in the startup file. Refer
//! Refer to the Module Operation section for more details.
//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
@ -484,18 +547,16 @@ extern uint32_t Interrupt_getVectorTableAddress(void);
//! this is ideal as power cycles are not wasted with the processing required
//! for waking up from an ISR and going back to sleep.
//!
//! \return Address of the vector table.
//! \return None
//
//*****************************************************************************
extern void Interrupt_enableSleepOnIsrExit(void);
//*****************************************************************************
//
//! Enables the processor to sleep when exiting an ISR. For low power operation,
//! this is ideal as power cycles are not wasted with the processing required
//! for waking up from an ISR and going back to sleep.
//! Disables the processor to sleep when exiting an ISR.
//!
//! \return Address of the vector table.
//! \return None
//
//*****************************************************************************
extern void Interrupt_disableSleepOnIsrExit(void);

22
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -49,7 +49,7 @@ void MPU_enableModule(uint32_t mpuConfig)
// Set the MPU control bits according to the flags passed by the user,
// and also set the enable bit.
//
MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE;
MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE_Msk;
}
void MPU_disableModule(void)
@ -57,7 +57,7 @@ void MPU_disableModule(void)
//
// Turn off the MPU enable bit.
//
MPU->CTRL &= ~MPU_CTRL_ENABLE;
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
@ -67,7 +67,7 @@ uint32_t MPU_getRegionCount(void)
// Read the DREGION field of the MPU type register and mask off
// the bits of interest to get the count of regions.
//
return ((MPU->TYPE & MPU_TYPE_DREGION_M) >> NVIC_MPU_TYPE_DREGION_S);
return ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> NVIC_MPU_TYPE_DREGION_S);
}
void MPU_enableRegion(uint32_t region)
@ -85,7 +85,7 @@ void MPU_enableRegion(uint32_t region)
//
// Modify the enable bit in the region attributes.
//
MPU->RASR |= MPU_RASR_ENABLE;
MPU->RASR |= MPU_RASR_ENABLE_Msk;
}
void MPU_disableRegion(uint32_t region)
@ -103,7 +103,7 @@ void MPU_disableRegion(uint32_t region)
//
// Modify the enable bit in the region attributes.
//
MPU->RASR &= ~MPU_RASR_ENABLE;
MPU->RASR &= ~MPU_RASR_ENABLE_Msk;
}
void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags)
@ -117,15 +117,15 @@ void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags)
// Program the base address, use the region field to select the
// region at the same time.
//
MPU->RBAR = addr | region | MPU_RBAR_VALID;
MPU->RBAR = addr | region | MPU_RBAR_VALID_Msk;
//
// Program the region attributes. Set the TEX field and the S, C,
// and B bits to fixed values that are suitable for all Stellaris
// memory.
//
MPU->RASR = (flags & ~(MPU_RASR_TEX_M | MPU_RASR_C)) | MPU_RASR_S
| MPU_RASR_B;
MPU->RASR = (flags & ~(MPU_RASR_TEX_Msk | MPU_RASR_C_Msk)) | MPU_RASR_S_Msk
| MPU_RASR_B_Msk;
}
void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags)
@ -145,7 +145,7 @@ void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags)
//
// Read and store the base address for the region.
//
*addr = MPU->RBAR & MPU_RBAR_ADDR_M;
*addr = MPU->RBAR & MPU_RBAR_ADDR_Msk;
//
// Read and store the region attributes.

8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -64,8 +64,8 @@ extern "C"
// Flags that can be passed to MPU_enableModule.
//
//*****************************************************************************
#define MPU_CONFIG_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA
#define MPU_CONFIG_HARDFLT_NMI MPU_CTRL_HFNMIENA
#define MPU_CONFIG_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_CONFIG_HARDFLT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_CONFIG_NONE 0
//*****************************************************************************

264
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,15 +41,12 @@
#include <pcm.h>
#include <debug.h>
#include <interrupt.h>
#include <wdt_a.h>
#include <rtc_c.h>
#include <cpu.h>
bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
{
return PCM_setCoreVoltageLevelWithTimeout(voltageLevel, 0);
}
bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
uint32_t timeOut)
static bool __PCM_setCoreVoltageLevelAdvanced(uint_fast8_t voltageLevel,
uint32_t timeOut, bool blocking)
{
uint8_t powerMode, bCurrentVoltageLevel;
uint32_t regValue;
@ -69,31 +66,38 @@ bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
while (bCurrentVoltageLevel != voltageLevel)
{
regValue = PCM->rCTL0.r;
regValue = PCM->CTL0;
switch (PCM_getPowerState())
{
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
case PCM_AM_LDO_VCORE0:
PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE1)
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LF_VCORE0:
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LDO_VCORE1:
PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE0)
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
default:
ASSERT(false);
}
while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
if(blocking)
{
if (boolTimeout && !(--timeOut))
return false;
while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
{
if (boolTimeout && !(--timeOut))
return false;
}
}
else
{
return true;
}
bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
@ -112,9 +116,21 @@ bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
}
bool PCM_setPowerMode(uint_fast8_t powerMode)
bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
{
return PCM_setPowerModeWithTimeout(powerMode, 0);
return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, true);
}
bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
uint32_t timeOut)
{
return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, timeOut, true);
}
bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel)
{
return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, false);
}
uint8_t PCM_getPowerMode(void)
@ -176,7 +192,8 @@ uint8_t PCM_getCoreVoltageLevel(void)
}
}
bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
static bool __PCM_setPowerModeAdvanced(uint_fast8_t powerMode, uint32_t timeOut,
bool blocking)
{
uint8_t bCurrentPowerMode, bCurrentPowerState;
uint32_t regValue;
@ -200,30 +217,30 @@ bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
/* Go through the while loop while we haven't achieved the power mode */
while (bCurrentPowerMode != powerMode)
{
regValue = PCM->rCTL0.r;
regValue = PCM->CTL0;
switch (bCurrentPowerState)
{
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LF_VCORE0:
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE0
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE1
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LDO_VCORE1:
{
if (powerMode == PCM_DCDC_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE1
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else if (powerMode == PCM_LF_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE1
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else
ASSERT(false);
@ -233,12 +250,12 @@ bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
{
if (powerMode == PCM_DCDC_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE0
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else if (powerMode == PCM_LF_MODE)
{
PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE0
| (regValue & ~(PCMKEY_M | AMR_M)));
PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
| (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else
ASSERT(false);
@ -248,12 +265,16 @@ bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
ASSERT(false);
}
while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
if (blocking)
{
if (boolTimeout && !(--timeOut))
return false;
while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
{
if (boolTimeout && !(--timeOut))
return false;
}
}
} else
return true;
bCurrentPowerMode = PCM_getPowerMode();
bCurrentPowerState = PCM_getPowerState();
@ -263,12 +284,24 @@ bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
}
bool PCM_setPowerState(uint_fast8_t powerState)
bool PCM_setPowerMode(uint_fast8_t powerMode)
{
return PCM_setPowerStateWithTimeout(powerState, 0);
return __PCM_setPowerModeAdvanced(powerMode, 0, true);
}
bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode)
{
return __PCM_setPowerModeAdvanced(powerMode, 0, false);
}
bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
{
return __PCM_setPowerModeAdvanced(powerMode, timeOut, true);
}
static bool __PCM_setPowerStateAdvanced(uint_fast8_t powerState,
uint32_t timeout,
bool blocking)
{
uint8_t bCurrentPowerState;
bCurrentPowerState = PCM_getPowerState();
@ -280,7 +313,7 @@ bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
|| powerState == PCM_LPM0_LDO_VCORE0 || powerState == PCM_LPM0_LDO_VCORE1
|| powerState == PCM_LPM0_DCDC_VCORE0 || powerState == PCM_LPM0_DCDC_VCORE1
|| powerState == PCM_LPM3 || powerState == PCM_LPM35_VCORE0
|| powerState == PCM_LPM45);
|| powerState == PCM_LPM45 || powerState == PCM_LPM4);
if (bCurrentPowerState == powerState)
return true;
@ -288,55 +321,59 @@ bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
switch (powerState)
{
case PCM_AM_LDO_VCORE0:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
&& __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking));
case PCM_AM_LDO_VCORE1:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
&& __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking));
case PCM_AM_DCDC_VCORE0:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
&& PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
&& __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking));
case PCM_AM_DCDC_VCORE1:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
&& PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
&& __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking));
case PCM_AM_LF_VCORE0:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
&& __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking));
case PCM_AM_LF_VCORE1:
return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
&& PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
&& __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking));
case PCM_LPM0_LDO_VCORE0:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
|| !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LDO_VCORE1:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
|| !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_DCDC_VCORE0:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
|| !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout,
blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_DCDC_VCORE1:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
|| !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout,
blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LF_VCORE0:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
|| !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LF_VCORE1:
if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
|| !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
|| !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM3:
return PCM_gotoLPM3();
case PCM_LPM4:
return PCM_gotoLPM4();
case PCM_LPM45:
return PCM_shutdownDevice(PCM_LPM45);
case PCM_LPM35_VCORE0:
@ -350,36 +387,81 @@ bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
}
bool PCM_setPowerState(uint_fast8_t powerState)
{
return __PCM_setPowerStateAdvanced(powerState, 0, true);
}
bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
{
return __PCM_setPowerStateAdvanced(powerState, timeout, true);
}
bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState)
{
return __PCM_setPowerStateAdvanced(powerState, 0, false);
}
bool PCM_shutdownDevice(uint32_t shutdownMode)
{
uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ? LPMR_12 : LPMR_10;
uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ?
PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
ASSERT(
shutdownMode == PCM_SHUTDOWN_PARTIAL
|| shutdownMode == PCM_SHUTDOWN_COMPLETE);
/* If a power transition is occuring, return false */
if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* Initiating the shutdown */
HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
PCM->rCTL0.r = (PCM_KEY | shutdownModeBits
| (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)));
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PCM->CTL0 = (PCM_KEY | shutdownModeBits
| (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)));
CPU_wfi();
return true;
}
bool PCM_gotoLPM4(void)
{
/* Disabling RTC_C and WDT_A */
WDT_A_holdTimer();
RTC_C_holdClock();
/* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */
return PCM_gotoLPM3();
}
bool PCM_gotoLPM4InterruptSafe(void)
{
bool slHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
slHappenedCorrect = PCM_gotoLPM4();
/* Enabling and Disabling Interrupts very quickly so that the
processor catches any pending interrupts */
Interrupt_enableMaster();
Interrupt_disableMaster();
return slHappenedCorrect;
}
bool PCM_gotoLPM0(void)
{
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
CPU_wfi();
@ -388,7 +470,6 @@ bool PCM_gotoLPM0(void)
bool PCM_gotoLPM0InterruptSafe(void)
{
bool slHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
@ -412,11 +493,12 @@ bool PCM_gotoLPM3(void)
uint_fast8_t currentPowerMode;
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* If we are in the middle of a shutdown, return false */
if ((PCM->rCTL0.r & LPMR_M) == LPMR_10 || (PCM->rCTL0.r & LPMR_M) == LPMR_12)
if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
|| (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
return false;
currentPowerMode = PCM_getPowerMode();
@ -426,76 +508,78 @@ bool PCM_gotoLPM3(void)
PCM_setPowerMode(PCM_LDO_MODE);
/* Clearing the SDR */
PCM->rCTL0.r = (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)) | PCM_KEY;
PCM->CTL0 = (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY;
/* Setting the sleep deep bit */
HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
CPU_wfi();
HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
return PCM_setPowerState(bCurrentPowerState);
}
bool PCM_gotoLPM3InterruptSafe(void)
{
bool dslHappenedCorrect;
bool lpmHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
dslHappenedCorrect = PCM_gotoLPM3();
lpmHappenedCorrect = PCM_gotoLPM3();
/* Enabling and Disabling Interrupts very quickly so that the
processor catches any pending interrupts */
Interrupt_enableMaster();
Interrupt_disableMaster();
return dslHappenedCorrect;
return lpmHappenedCorrect;
}
uint8_t PCM_getPowerState(void)
{
return PCM->rCTL0.b.bCPM;
return (PCM->CTL0 | PCM_CTL0_CPM_MASK);
}
void PCM_enableRudeMode(void)
{
PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M)) | PCM_KEY | FORCE_LPM_ENTRY;
PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK)) | PCM_KEY
| PCM_CTL1_FORCE_LPM_ENTRY;
}
void PCM_disableRudeMode(void)
{
PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M | FORCE_LPM_ENTRY)) | PCM_KEY;
PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK | PCM_CTL1_FORCE_LPM_ENTRY))
| PCM_KEY;
}
void PCM_enableInterrupt(uint32_t flags)
{
PCM->rIE.r |= flags;
PCM->IE |= flags;
}
void PCM_disableInterrupt(uint32_t flags)
{
PCM->rIE.r &= ~flags;
PCM->IE &= ~flags;
}
uint32_t PCM_getInterruptStatus(void)
{
return PCM->rIFG.r;
return PCM->IFG;
}
uint32_t PCM_getEnabledInterruptStatus(void)
{
return PCM_getInterruptStatus() & PCM->rIE.r;
return PCM_getInterruptStatus() & PCM->IE;
}
void PCM_clearInterruptFlag(uint32_t flags)
{
PCM->rCLRIFG.r |= flags;
PCM->CLRIFG |= flags;
}
void PCM_registerInterrupt(void (*intHandler)(void))

140
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -80,6 +80,7 @@ extern "C"
#define PCM_LPM0_LF_VCORE0 0x18
#define PCM_LPM0_LF_VCORE1 0x19
#define PCM_LPM3 0x20
#define PCM_LPM4 0x21
#define PCM_LPM35_VCORE0 0xC0
#define PCM_LPM45 0xA0
@ -94,10 +95,10 @@ extern "C"
#define PCM_SHUTDOWN_PARTIAL PCM_LPM35_VCORE0
#define PCM_SHUTDOWN_COMPLETE PCM_LPM45
#define PCM_DCDCERROR PCM_INTEN_EN_DCDC_ERROR
#define PCM_AM_INVALIDTRANSITION PCM_INTEN_EN_AM_INVALID_TR
#define PCM_SM_INVALIDCLOCK PCM_INTEN_EN_SM_INVALID_CLK
#define PCM_SM_INVALIDTRANSITION PCM_INTEN_EN_SM_INVALID_TR
#define PCM_DCDCERROR PCM_IE_DCDC_ERROR_IE
#define PCM_AM_INVALIDTRANSITION PCM_IE_AM_INVALID_TR_IE
#define PCM_SM_INVALIDCLOCK PCM_IE_LPM_INVALID_CLK_IE
#define PCM_SM_INVALIDTRANSITION PCM_IE_LPM_INVALID_TR_IE
//*****************************************************************************
//
@ -172,6 +173,29 @@ extern uint8_t PCM_getCoreVoltageLevel(void);
extern bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
uint32_t timeOut);
//******************************************************************************
//
//! Sets the core voltage level (Vcore). This function is similar to
//! PCM_setCoreVoltageLevel, however there are no polling flags to ensure
//! a state has changed. Execution is returned back to the calling program
// and it is up to the user to ensure proper state transitions happen
//! correctly. For MSP432, changing into different power modes/states
//! require very specific logic. This function will initiate only one state
//! transition and then return. It is up to the user to keep calling this
//! function until the correct power state has been achieved.
//!
//! Refer to the device specific data sheet for specifics about core voltage
//! levels.
//!
//! \param voltageLevel The voltage level to be shifted to.
//! - \b PCM_VCORE0,
//! - \b PCM_VCORE1
//!
//! \return true if voltage level set, false otherwise.
//
//******************************************************************************
extern bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel);
//******************************************************************************
//
//! Switches between power modes. This function will take care of all
@ -217,6 +241,30 @@ extern bool PCM_setPowerMode(uint_fast8_t powerMode);
extern bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode,
uint32_t timeOut);
//******************************************************************************
//
//! Sets the core voltage level (Vcore). This function is similar to
//! PCM_setPowerMode, however there are no polling flags to ensure
//! a state has changed. Execution is returned back to the calling program
// and it is up to the user to ensure proper state transitions happen
//! correctly. For MSP432, changing into different power modes/states
//! require very specific logic. This function will initiate only one state
//! transition and then return. It is up to the user to keep calling this
//! function until the correct power state has been achieved.
//!
//! Refer to the device specific data sheet for specifics about core voltage
//! levels.
//!
//! \param powerMode The voltage modes to be shifted to. Valid values are:
//! - \b PCM_LDO_MODE,
//! - \b PCM_DCDC_MODE,
//! - \b PCM_LF_MODE
//!
//! \return true if power mode change was initiated, false otherwise
//
//******************************************************************************
extern bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode);
//******************************************************************************
//
//! Returns the current powers state of the system see the \b PCM_setPowerState
@ -231,8 +279,8 @@ extern uint8_t PCM_getPowerMode(void);
//******************************************************************************
//
//! Switches between power states. This is a convenience function that combines
//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
//! the sleep/LPM3/shutdown functions.
//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as
//! the LPM0/LPM3 functions.
//!
//! Refer to the device specific data sheet for specifics about power states.
//!
@ -251,6 +299,7 @@ extern uint8_t PCM_getPowerMode(void);
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
//! - \b PCM_LPM4, [LPM4]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \return true if power state is set, false otherwise.
@ -261,10 +310,10 @@ extern bool PCM_setPowerState(uint_fast8_t powerState);
//******************************************************************************
//
//! Switches between power states. This is a convenience function that combines
//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as
//! the LPM modes.
//!
//! This function is similar to PCMChangePowerState, however a timeout
//! This function is similar to PCM_setPowerState, however a timeout
//! mechanism is used.
//!
//! Refer to the device specific data sheet for specifics about power states.
@ -284,6 +333,7 @@ extern bool PCM_setPowerState(uint_fast8_t powerState);
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
//! - \b PCM_LPM4, [LPM4]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \param timeout Number of loop iterations to timeout when checking for
@ -312,6 +362,42 @@ extern bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState,
//******************************************************************************
extern uint8_t PCM_getPowerState(void);
//******************************************************************************
//
//! Sets the power state of the part. This function is similar to
//! PCM_getPowerState, however there are no polling flags to ensure
//! a state has changed. Execution is returned back to the calling program
// and it is up to the user to ensure proper state transitions happen
//! correctly. For MSP432, changing into different power modes/states
//! require very specific logic. This function will initiate only one state
//! transition and then return. It is up to the user to keep calling this
//! function until the correct power state has been achieved.
//!
//! Refer to the device specific data sheet for specifics about core voltage
//! levels.
//!
//! \param powerState The voltage modes to be shifted to. Valid values are:
//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0]
//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1]
//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0]
//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1]
//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0]
//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1]
//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0]
//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1]
//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0]
//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1]
//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0]
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \return true if power state change was initiated, false otherwise
//
//******************************************************************************
extern bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState);
//******************************************************************************
//
//! Transitions the device into LPM3.5/LPM4.5 mode.
@ -368,7 +454,7 @@ extern bool PCM_gotoLPM3(void);
//! Transitions the device into LPM0 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to sleep, however does not want
//! to go to "miss" any interrupts due to the fact that going to DSL is not
//! to go to "miss" any interrupts due to the fact that going to LPM0 is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
@ -384,7 +470,7 @@ extern bool PCM_gotoLPM0InterruptSafe(void);
//! Transitions the device into LPM3 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to LPM3, however does not want
//! to go to "miss" any interrupts due to the fact that going to DSL is not
//! to go to "miss" any interrupts due to the fact that going to LPM3 is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
@ -398,6 +484,36 @@ extern bool PCM_gotoLPM0InterruptSafe(void);
//******************************************************************************
extern bool PCM_gotoLPM3InterruptSafe(void);
//******************************************************************************
//
//! Transitions the device into LPM4. LPM4 is the exact same with LPM3, just
//! with RTC_C and WDT_A disabled. When waking up, RTC_C and WDT_A will remain
//! disabled until reconfigured by the user.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM4(void);
//******************************************************************************
//
//! Transitions the device into LPM4 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to LPM4, however does not want
//! to go to "miss" any interrupts due to the fact that going to LPM4 is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
//! Refer to the device specific data sheet for specifics about low power modes.
//! Note that since LPM3 cannot be entered from a DCDC power modes, the
//! power mode is first switched to LDO operation (if in DCDC mode), the deep
//! sleep is entered, and the DCDC mode is restored on wake up.
//!
//! \return false if sleep state cannot be entered, true otherwise.
//
//******************************************************************************
extern bool PCM_gotoLPM4InterruptSafe(void);
//******************************************************************************
//
//! Enables "rude mode" entry into LPM3 and shutdown modes. With this mode

13
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -36,21 +36,22 @@
* --/COPYRIGHT--*/
#include <debug.h>
#include <pmap.h>
#include <hw_memmap.h>
void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
uint8_t numberOfPorts, uint8_t portMapReconfigure)
{
uint16_t i;
uint_fast16_t i;
ASSERT(
(portMapReconfigure == PMAP_ENABLE_RECONFIGURATION)
|| (portMapReconfigure == PMAP_DISABLE_RECONFIGURATION));
//Get write-access to port mapping registers:
PMAP->rKEYID = PMAP_KEYID_VAL;
PMAP->KEYID = PMAP_KEYID_VAL;
//Enable/Disable reconfiguration during runtime
PMAP->rCTL.r = (PMAP->rCTL.r & ~PMAPRECFG) | portMapReconfigure;
PMAP->CTL = (PMAP->CTL & ~PMAP_CTL_PRECFG) | portMapReconfigure;
//Configure Port Mapping:
@ -60,6 +61,6 @@ void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
}
//Disable write-access to port mapping registers:
PMAP->rKEYID = 0;
PMAP->KEYID = 0;
}

20
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -64,7 +64,7 @@ extern "C"
//as the portMapReconfigure parameter.
//
//*****************************************************************************
#define PMAP_ENABLE_RECONFIGURATION PMAPRECFG
#define PMAP_ENABLE_RECONFIGURATION PMAP_CTL_PRECFG
#define PMAP_DISABLE_RECONFIGURATION 0x00
//*****************************************************************************
@ -73,13 +73,13 @@ extern "C"
//as the portMapReconfigure parameter.
//
//*****************************************************************************
#define P1MAP OFS_P1MAP01
#define P2MAP OFS_P2MAP01
#define P3MAP OFS_P3MAP01
#define P4MAP OFS_P4MAP01
#define P5MAP OFS_P5MAP01
#define P6MAP OFS_P6MAP01
#define P7MAP OFS_P7MAP01
#define PMAP_P1MAP ((uint32_t)P1MAP - PMAP_BASE)
#define PMAP_P2MAP ((uint32_t)P2MAP - PMAP_BASE)
#define PMAP_P3MAP ((uint32_t)P3MAP - PMAP_BASE)
#define PMAP_P4MAP ((uint32_t)P4MAP - PMAP_BASE)
#define PMAP_P5MAP ((uint32_t)P5MAP - PMAP_BASE)
#define PMAP_P6MAP ((uint32_t)P6MAP - PMAP_BASE)
#define PMAP_P7MAP ((uint32_t)P7MAP - PMAP_BASE)
//*****************************************************************************

105
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,12 +45,32 @@
static void __PSSUnlock()
{
PSS->rKEY.r = PSS_KEY_VALUE;
PSS->KEY = PSS_KEY_VALUE;
}
static void __PSSLock()
{
PSS->rKEY.r = 0;
PSS->KEY = 0;
}
void PSS_enableForcedDCDCOperation(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 1;
__PSSLock();
}
void PSS_disableForcedDCDCOperation(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 0;
__PSSLock();
}
void PSS_enableHighSidePinToggle(bool activeLow)
@ -58,11 +78,11 @@ void PSS_enableHighSidePinToggle(bool activeLow)
__PSSUnlock();
if (activeLow)
PSS->rCTL0.r |= (SVMHOE | SVMHOUTPOLAL);
PSS->CTL0 |= (PSS_CTL0_SVMHOE | PSS_CTL0_SVMHOUTPOLAL);
else
{
BITBAND_PERI(PSS->rCTL0.r, SVMHOUTPOLAL_OFS) = 0;
BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 1;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOUTPOLAL_OFS) = 0;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 1;
}
__PSSLock();
@ -72,7 +92,7 @@ void PSS_disableHighSidePinToggle(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 0;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 0;
__PSSLock();
}
@ -81,7 +101,7 @@ void PSS_enableHighSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 0;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 0;
__PSSLock();
}
@ -90,7 +110,7 @@ void PSS_disableHighSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 1;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 1;
__PSSLock();
}
@ -100,16 +120,16 @@ void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode)
__PSSUnlock();
if (powerMode == PSS_FULL_PERFORMANCE_MODE)
BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 0;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 0;
else
BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 1;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 1;
__PSSLock();
}
uint_fast8_t PSS_getHighSidePerformanceMode(void)
{
if (BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS))
if (BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS))
return PSS_NORMAL_PERFORMANCE_MODE;
else
return PSS_FULL_PERFORMANCE_MODE;
@ -119,7 +139,7 @@ void PSS_enableHighSideMonitor(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 1;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 1;
__PSSLock();
}
@ -128,7 +148,7 @@ void PSS_disableHighSideMonitor(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 0;
BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 0;
__PSSLock();
}
@ -139,80 +159,41 @@ void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage)
ASSERT(!(triggerVoltage & 0xF8))
PSS->rCTL0.b.bSVSMHTH = triggerVoltage & 0x07;
PSS->CTL0 &= ~PSS_CTL0_SVSMHTH_MASK;
PSS->CTL0 |= (triggerVoltage & 0x07) << PSS_CTL0_SVSMHTH_OFS;
__PSSLock();
}
uint_fast8_t PSS_getHighSideVoltageTrigger(void)
{
return PSS->rCTL0.b.bSVSMHTH;
return (uint_fast8_t)((PSS->CTL0 & PSS_CTL0_SVSMHTH_MASK)
>> PSS_CTL0_SVSMHTH_OFS);
}
void PSS_enableLowSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 0;
__PSSLock();
}
void PSS_disableLowSide(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 1;
__PSSLock();
}
void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode)
{
__PSSUnlock();
if (ui8PowerMode == PSS_FULL_PERFORMANCE_MODE)
BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 0;
else
BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 1;
__PSSLock();
}
uint_fast8_t PSS_getLowSidePerformanceMode(void)
{
if (BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS))
return PSS_NORMAL_PERFORMANCE_MODE;
else
return PSS_FULL_PERFORMANCE_MODE;
}
void PSS_enableInterrupt(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 1;
BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 1;
__PSSLock();
}
void PSS_disableInterrupt(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 0;
BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 0;
__PSSLock();
}
uint32_t PSS_getInterruptStatus(void)
{
return PSS->rIFG.r;
return PSS->IFG;
}
void PSS_clearInterruptFlag(void)
{
__PSSUnlock();
BITBAND_PERI(PSS->rCLRIFG.r,CLRSVSMHIFG_OFS) = 0;
BITBAND_PERI(PSS->CLRIFG,PSS_CLRIFG_CLRSVSMHIFG_OFS) = 0;
__PSSLock();
}

79
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -64,9 +64,9 @@ extern "C"
// Control specific variables
//
//*****************************************************************************
#define PSS_KEY_VALUE 0x0000695A
#define PSS_KEY_VALUE PSS_KEY_KEY_VAL
#define PSS_SVSMH SVSMHIE
#define PSS_SVSMH PSS_IE_SVSMHIE
#define PSS_FULL_PERFORMANCE_MODE 0x01
#define PSS_NORMAL_PERFORMANCE_MODE 0x00
@ -203,51 +203,6 @@ extern void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage);
//*****************************************************************************
extern uint_fast8_t PSS_getHighSideVoltageTrigger(void);
//*****************************************************************************
//
//! Enables low side voltage supervisor/monitor.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableLowSide(void);
//*****************************************************************************
//
//! Disables low side voltage supervisor/monitor.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableLowSide(void);
//*****************************************************************************
//
//! Sets the performance mode of the high side regulator. Full performance
//! mode allows for the best response times while normal performance mode is
//! optimized for the lowest possible current consumption.
//!
//! \param ui8PowerMode is the performance mode to set. Valid values are one of
//! the following:
//! - \b PSS_FULL_PERFORMANCE_MODE,
//! - \b PSS_NORMAL_PERFORMANCE_MODE
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode);
//*****************************************************************************
//
//! Gets the performance mode of the low side voltage regulator. Refer to the
//! user's guide for specific information about information about the different
//! performance modes.
//!
//! \return Performance mode of the voltage regulator
//
//*****************************************************************************
extern uint_fast8_t PSS_getLowSidePerformanceMode(void);
//*****************************************************************************
//
//! Enables the power supply system interrupt source.
@ -284,6 +239,32 @@ extern uint32_t PSS_getInterruptStatus(void);
//*****************************************************************************
extern void PSS_clearInterruptFlag(void);
//*****************************************************************************
//
//! Enables the "forced" mode of the DCDC regulator. In this mode, the fail
//! safe mechanism that disables the regulator to LDO mode when the supply
//! voltage falls below the minimum supply voltage required for DCDC operation
//! is turned off.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_enableForcedDCDCOperation(void);
//*****************************************************************************
//
//! Disables the "forced" mode of the DCDC regulator. In this mode, the fail
//! safe mechanism that disables the regulator to LDO mode when the supply
//! voltage falls below the minimum supply voltage required for DCDC operation
//! is turned on.
//!
//! \return None.
//
//*****************************************************************************
extern void PSS_disableForcedDCDCOperation(void);
//*****************************************************************************
//
//! Registers an interrupt handler for the power supply system interrupt.

34
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,76 +41,76 @@ void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect)
{
ASSERT(referenceVoltageSelect <= REF_A_VREF2_5V);
REF_A->rCTL0.r = (REF_A->rCTL0.r & ~REFVSEL_3) | referenceVoltageSelect;
REF_A->CTL0 = (REF_A->CTL0 & ~REF_A_CTL0_VSEL_3) | referenceVoltageSelect;
}
void REF_A_disableTempSensor(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 1;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 1;
}
void REF_A_enableTempSensor(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 0;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 0;
}
void REF_A_enableReferenceVoltageOutput(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 1;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 1;
}
void REF_A_disableReferenceVoltageOutput(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 0;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 0;
}
void REF_A_enableReferenceVoltage(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 1;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 1;
}
void REF_A_disableReferenceVoltage(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 0;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 0;
}
uint_fast8_t REF_A_getBandgapMode(void)
{
return (REF_A->rCTL0.r & BGMODE);
return (REF_A->CTL0 & REF_A_CTL0_BGMODE);
}
bool REF_A_isBandgapActive(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFBGACT_OFS);
return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGACT_OFS);
}
bool REF_A_isRefGenBusy(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFGENBUSY_OFS);
return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENBUSY_OFS);
}
bool REF_A_isRefGenActive(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFGENACT_OFS);
return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENACT_OFS);
}
bool REF_A_getBufferedBandgapVoltageStatus(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFBGRDY_OFS);
return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGRDY_OFS);
}
bool REF_A_getVariableReferenceVoltageStatus(void)
{
return BITBAND_PERI(REF_A->rCTL0.r,REFGENRDY_OFS);
return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENRDY_OFS);
}
void REF_A_setReferenceVoltageOneTimeTrigger(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFGENOT_OFS) = 1;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENOT_OFS) = 1;
}
void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void)
{
BITBAND_PERI(REF_A->rCTL0.r,REFBGOT_OFS) = 1;
BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGOT_OFS) = 1;
}

12
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -65,9 +65,9 @@ extern "C"
//in the referenceVoltageSelect parameter.
//
//*****************************************************************************
#define REF_A_VREF1_2V REFVSEL_0
#define REF_A_VREF1_45V REFVSEL_1
#define REF_A_VREF2_5V REFVSEL_3
#define REF_A_VREF1_2V REF_A_CTL0_VSEL_0
#define REF_A_VREF1_45V REF_A_CTL0_VSEL_1
#define REF_A_VREF2_5V REF_A_CTL0_VSEL_3
//*****************************************************************************
//
@ -75,7 +75,7 @@ extern "C"
//
//*****************************************************************************
#define REF_A_STATICMODE 0x0
#define REF_A_SAMPLEMODE BGMODE
#define REF_A_SAMPLEMODE REF_A_CTL0_BGMODE
//*****************************************************************************
//

28
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -39,61 +39,61 @@
void ResetCtl_initiateSoftReset(void)
{
RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_SOFT_RESET);
RSTCTL->RESET_REQ |= (RESET_KEY | RESET_SOFT_RESET);
}
void ResetCtl_initiateSoftResetWithSource(uint32_t source)
{
RSTCTL->rSOFTRESET_SET.r |= (source);
RSTCTL->SOFTRESET_SET |= (source);
}
uint32_t ResetCtl_getSoftResetSource(void)
{
return RSTCTL->rSOFTRESET_STAT.r;
return RSTCTL->SOFTRESET_STAT;
}
void ResetCtl_clearSoftResetSource(uint32_t mask)
{
RSTCTL->rSOFTRESET_CLR.r |= mask;
RSTCTL->SOFTRESET_CLR |= mask;
}
void ResetCtl_initiateHardReset(void)
{
RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_HARD_RESET);
RSTCTL->RESET_REQ |= (RESET_KEY | RESET_HARD_RESET);
}
void ResetCtl_initiateHardResetWithSource(uint32_t source)
{
RSTCTL->rHARDRESET_SET.r |= (source);
RSTCTL->HARDRESET_SET |= (source);
}
uint32_t ResetCtl_getHardResetSource(void)
{
return RSTCTL->rHARDRESET_STAT.r;
return RSTCTL->HARDRESET_STAT;
}
void ResetCtl_clearHardResetSource(uint32_t mask)
{
RSTCTL->rHARDRESET_CLR.r |= mask;
RSTCTL->HARDRESET_CLR |= mask;
}
uint32_t ResetCtl_getPSSSource(void)
{
return RSTCTL->rPSSRESET_STAT.r;
return RSTCTL->PSSRESET_STAT;
}
void ResetCtl_clearPSSFlags(void)
{
RSTCTL->rPSSRESET_CLR.r |= RSTCTL_PSSRESET_CLR_CLR;
RSTCTL->PSSRESET_CLR |= RSTCTL_PSSRESET_CLR_CLR;
}
uint32_t ResetCtl_getPCMSource(void)
{
return RSTCTL->rPCMRESET_STAT.r;
return RSTCTL->PCMRESET_STAT;
}
void ResetCtl_clearPCMFlags(void)
{
RSTCTL->rPCMRESET_CLR.r |= RSTCTL_PCMRESET_CLR_CLR;
RSTCTL->PCMRESET_CLR |= RSTCTL_PCMRESET_CLR_CLR;
}

14
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -86,11 +86,10 @@ extern "C"
#define RESET_VCCDET RSTCTL_PSSRESET_CLR_BGREF
#define RESET_SVSH_TRIP RSTCTL_PSSRESET_CLR_SVSMH
#define RESET_SVSL_TRIP RSTCTL_PSSRESET_CLR_SVSL
#define RESET_BGREF_BAD RSTCTL_PSSRESET_CLR_BGREF
#define RESET_SD0 RSTCTL_PCMRESET_CLR_LPM35
#define RESET_SD1 RSTCTL_PCMRESET_CLR_LPM45
#define RESET_LPM35 RSTCTL_PCMRESET_CLR_LPM35
#define RESET_LPM45 RSTCTL_PCMRESET_CLR_LPM45
//*****************************************************************************
//
@ -291,7 +290,6 @@ extern void ResetCtl_clearHardResetSource(uint32_t mask);
//! \return Bitwise OR of any of the following values:
//! - RESET_VCCDET,
//! - RESET_SVSH_TRIP,
//! - RESET_SVSL_TRIP,
//! - RESET_BGREF_BAD
//
//*****************************************************************************
@ -311,8 +309,8 @@ extern void ResetCtl_clearPSSFlags(void);
//! Indicates the last cause of a power-on reset (POR) due to PCM operation.
//!
//! \return Bitwise OR of any of the following values:
//! - RESET_SD0,
//! - RESET_SD1
//! - RESET_LPM35,
//! - RESET_LPM45
//
//*****************************************************************************
extern uint32_t ResetCtl_getPCMSource(void);

19
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,6 +34,16 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
//*****************************************************************************
//
// rom.h - Macros to facilitate calling functions in the ROM.
//
// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
// TI Information - Selective Disclosure
//
//*****************************************************************************
//
#ifndef __ROM_H__
#define __ROM_H__
@ -1631,8 +1641,9 @@
#endif
#if defined(TARGET_IS_MSP432P4XX)
#define ROM_Timer_A_getCaptureCompareInterruptStatus \
(( (*)(, \
))ROM_TIMER_ATABLE[22])
((uint32_t (*)(uint32_t timer, \
uint_fast16_t captureCompareRegister, \
uint_fast16_t mask))ROM_TIMER_ATABLE[22])
#endif
#if defined(TARGET_IS_MSP432P4XX)
#define ROM_Timer_A_getCaptureCompareEnabledInterruptStatus \

232
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -34,6 +34,17 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
//*****************************************************************************
//
// rom_map.h - Macros to facilitate calling functions in the ROM when they are
// available and in flash otherwise.
//
// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
// TI Information - Selective Disclosure
//
//
//*****************************************************************************
#ifndef __ROM_MAP_H__
#define __ROM_MAP_H__
@ -405,6 +416,13 @@
#define MAP_AES256_unregisterInterrupt \
AES256_unregisterInterrupt
#endif
#ifdef ROM_AES256_getInterruptFlagStatus
#define MAP_AES256_getInterruptFlagStatus \
ROM_AES256_getInterruptFlagStatus
#else
#define MAP_AES256_getInterruptFlagStatus \
AES256_getInterruptFlagStatus
#endif
//*****************************************************************************
//
@ -850,6 +868,13 @@
#define MAP_CS_setExternalClockSourceFrequency \
CS_setExternalClockSourceFrequency
#endif
#ifdef ROM_CS_setDCOExternalResistorCalibration
#define MAP_CS_setDCOExternalResistorCalibration \
ROM_CS_setDCOExternalResistorCalibration
#else
#define MAP_CS_setDCOExternalResistorCalibration \
CS_setDCOExternalResistorCalibration
#endif
//*****************************************************************************
//
@ -1240,6 +1265,69 @@
#define MAP_FlashCtl_unregisterInterrupt \
FlashCtl_unregisterInterrupt
#endif
#ifdef ROM___FlashCtl_remaskData8Post
#define MAP___FlashCtl_remaskData8Post \
ROM___FlashCtl_remaskData8Post
#else
#define MAP___FlashCtl_remaskData8Post \
__FlashCtl_remaskData8Post
#endif
#ifdef ROM___FlashCtl_remaskData8Pre
#define MAP___FlashCtl_remaskData8Pre \
ROM___FlashCtl_remaskData8Pre
#else
#define MAP___FlashCtl_remaskData8Pre \
__FlashCtl_remaskData8Pre
#endif
#ifdef ROM___FlashCtl_remaskData32Pre
#define MAP___FlashCtl_remaskData32Pre \
ROM___FlashCtl_remaskData32Pre
#else
#define MAP___FlashCtl_remaskData32Pre \
__FlashCtl_remaskData32Pre
#endif
#ifdef ROM___FlashCtl_remaskData32Post
#define MAP___FlashCtl_remaskData32Post \
ROM___FlashCtl_remaskData32Post
#else
#define MAP___FlashCtl_remaskData32Post \
__FlashCtl_remaskData32Post
#endif
#ifdef ROM___FlashCtl_remaskBurstDataPre
#define MAP___FlashCtl_remaskBurstDataPre \
ROM___FlashCtl_remaskBurstDataPre
#else
#define MAP___FlashCtl_remaskBurstDataPre \
__FlashCtl_remaskBurstDataPre
#endif
#ifdef ROM___FlashCtl_remaskBurstDataPost
#define MAP___FlashCtl_remaskBurstDataPost \
ROM___FlashCtl_remaskBurstDataPost
#else
#define MAP___FlashCtl_remaskBurstDataPost \
__FlashCtl_remaskBurstDataPost
#endif
#ifdef ROM_FlashCtl_initiateSectorErase
#define MAP_FlashCtl_initiateSectorErase \
ROM_FlashCtl_initiateSectorErase
#else
#define MAP_FlashCtl_initiateSectorErase \
FlashCtl_initiateSectorErase
#endif
#ifdef ROM_FlashCtl_initiateMassErase
#define MAP_FlashCtl_initiateMassErase \
ROM_FlashCtl_initiateMassErase
#else
#define MAP_FlashCtl_initiateMassErase \
FlashCtl_initiateMassErase
#endif
#ifdef ROM_FlashCtl_getMemoryInfo
#define MAP_FlashCtl_getMemoryInfo \
ROM_FlashCtl_getMemoryInfo
#else
#define MAP_FlashCtl_getMemoryInfo \
FlashCtl_getMemoryInfo
#endif
//*****************************************************************************
//
@ -1748,6 +1836,13 @@
#define MAP_I2C_unregisterInterrupt \
I2C_unregisterInterrupt
#endif
#ifdef ROM_I2C_slaveSendNAK
#define MAP_I2C_slaveSendNAK \
ROM_I2C_slaveSendNAK
#else
#define MAP_I2C_slaveSendNAK \
I2C_slaveSendNAK
#endif
//*****************************************************************************
//
@ -1873,6 +1968,20 @@
#define MAP_Interrupt_registerInterrupt \
Interrupt_registerInterrupt
#endif
#ifdef ROM_Interrupt_unregisterInterrupt
#define MAP_Interrupt_unregisterInterrupt \
ROM_Interrupt_unregisterInterrupt
#else
#define MAP_Interrupt_unregisterInterrupt \
Interrupt_unregisterInterrupt
#endif
#ifdef ROM_Interrupt_unpendInterrupt
#define MAP_Interrupt_unpendInterrupt \
ROM_Interrupt_unpendInterrupt
#else
#define MAP_Interrupt_unpendInterrupt \
Interrupt_unpendInterrupt
#endif
//*****************************************************************************
//
@ -2123,6 +2232,41 @@
#define MAP_PCM_unregisterInterrupt \
PCM_unregisterInterrupt
#endif
#ifdef ROM_PCM_setCoreVoltageLevelNonBlocking
#define MAP_PCM_setCoreVoltageLevelNonBlocking \
ROM_PCM_setCoreVoltageLevelNonBlocking
#else
#define MAP_PCM_setCoreVoltageLevelNonBlocking \
PCM_setCoreVoltageLevelNonBlocking
#endif
#ifdef ROM_PCM_setPowerModeNonBlocking
#define MAP_PCM_setPowerModeNonBlocking \
ROM_PCM_setPowerModeNonBlocking
#else
#define MAP_PCM_setPowerModeNonBlocking \
PCM_setPowerModeNonBlocking
#endif
#ifdef ROM_PCM_setPowerStateNonBlocking
#define MAP_PCM_setPowerStateNonBlocking \
ROM_PCM_setPowerStateNonBlocking
#else
#define MAP_PCM_setPowerStateNonBlocking \
PCM_setPowerStateNonBlocking
#endif
#ifdef ROM_PCM_gotoLPM4
#define MAP_PCM_gotoLPM4 \
ROM_PCM_gotoLPM4
#else
#define MAP_PCM_gotoLPM4 \
PCM_gotoLPM4
#endif
#ifdef ROM_PCM_gotoLPM4InterruptSafe
#define MAP_PCM_gotoLPM4InterruptSafe \
ROM_PCM_gotoLPM4InterruptSafe
#else
#define MAP_PCM_gotoLPM4InterruptSafe \
PCM_gotoLPM4InterruptSafe
#endif
//*****************************************************************************
//
@ -2156,34 +2300,6 @@
#define MAP_PSS_disableHighSidePinToggle \
PSS_disableHighSidePinToggle
#endif
#ifdef ROM_setLowSidePerformanceMode
#define MAP_PSS_setLowSidePerformanceMode \
ROM_PSS_setLowSidePerformanceMode
#else
#define MAP_PSS_setLowSidePerformanceMode \
PSS_setLowSidePerformanceMode
#endif
#ifdef ROM_getLowSidePerformanceMode
#define MAP_PSS_getLowSidePerformanceMode \
ROM_PSS_getLowSidePerformanceMode
#else
#define MAP_PSS_getLowSidePerformanceMode \
PSS_getLowSidePerformanceMode
#endif
#ifdef ROM_PSS_disableLowSide
#define MAP_PSS_disableLowSide \
ROM_PSS_disableLowSide
#else
#define MAP_PSS_disableLowSide \
PSS_disableLowSide
#endif
#ifdef ROM_PSS_enableLowSide
#define MAP_PSS_enableLowSide \
ROM_PSS_enableLowSide
#else
#define MAP_PSS_enableLowSide \
PSS_enableLowSide
#endif
#ifdef ROM_PSS_enableHighSide
#define MAP_PSS_enableHighSide \
ROM_PSS_enableHighSide
@ -2282,6 +2398,20 @@
#define MAP_PSS_unregisterInterrupt \
PSS_unregisterInterrupt
#endif
#ifdef ROM_PSS_enableForcedDCDCOperation
#define MAP_PSS_enableForcedDCDCOperation \
ROM_PSS_enableForcedDCDCOperation
#else
#define MAP_PSS_enableForcedDCDCOperation \
PSS_enableForcedDCDCOperation
#endif
#ifdef ROM_PSS_disableForcedDCDCOperation
#define MAP_PSS_disableForcedDCDCOperation \
ROM_PSS_disableForcedDCDCOperation
#else
#define MAP_PSS_disableForcedDCDCOperation \
PSS_disableForcedDCDCOperation
#endif
//*****************************************************************************
//
@ -2886,6 +3016,27 @@
#define MAP_SysCtl_getTempCalibrationConstant \
SysCtl_getTempCalibrationConstant
#endif
#ifdef ROM_SysCtl_enableGlitchFilter
#define MAP_SysCtl_enableGlitchFilter \
ROM_SysCtl_enableGlitchFilter
#else
#define MAP_SysCtl_enableGlitchFilter \
SysCtl_enableGlitchFilter
#endif
#ifdef ROM_SysCtl_disableGlitchFilter
#define MAP_SysCtl_disableGlitchFilter \
ROM_SysCtl_disableGlitchFilter
#else
#define MAP_SysCtl_disableGlitchFilter \
SysCtl_disableGlitchFilter
#endif
#ifdef ROM_SysCtl_getTLVInfo
#define MAP_SysCtl_getTLVInfo \
ROM_SysCtl_getTLVInfo
#else
#define MAP_SysCtl_getTLVInfo \
SysCtl_getTLVInfo
#endif
//*****************************************************************************
//
@ -3143,6 +3294,13 @@
#define MAP_Timer_A_unregisterInterrupt \
Timer_A_unregisterInterrupt
#endif
#ifdef ROM_Timer_A_getCounterValue
#define MAP_Timer_A_getCounterValue \
ROM_Timer_A_getCounterValue
#else
#define MAP_Timer_A_getCounterValue \
Timer_A_getCounterValue
#endif
//*****************************************************************************
//
@ -3434,5 +3592,19 @@
#define MAP_WDT_A_unregisterInterrupt \
WDT_A_unregisterInterrupt
#endif
#ifdef ROM_WDT_A_setPasswordViolationReset
#define MAP_WDT_A_setPasswordViolationReset \
ROM_WDT_A_setPasswordViolationReset
#else
#define MAP_WDT_A_setPasswordViolationReset \
WDT_A_setPasswordViolationReset
#endif
#ifdef ROM_WDT_A_setTimeoutReset
#define MAP_WDT_A_setTimeoutReset \
ROM_WDT_A_setTimeoutReset
#else
#define MAP_WDT_A_setTimeoutReset \
WDT_A_setTimeoutReset
#endif
#endif // __ROM_MAP_H__

168
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -37,45 +37,46 @@
#include <rtc_c.h>
#include <interrupt.h>
#include <debug.h>
#include <hw_memmap.h>
void RTC_C_startClock(void)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 0;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 0;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_holdClock(void)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCCALF_3)) | frequencySelect;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_CALF_3)) | frequencySelect;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
uint_fast8_t offsetValue)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->rOCAL.r = offsetValue + offsetDirection;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->OCAL = offsetValue + offsetDirection;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
uint_fast8_t offsetValue)
{
while (!BITBAND_PERI(RTC_C->rTCMP.r, RTCTCRDY_OFS))
while (!BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCRDY_OFS))
;
RTC_C->rTCMP.r = offsetValue + offsetDirection;
RTC_C->TCMP = offsetValue + offsetDirection;
if (BITBAND_PERI(RTC_C->rTCMP.r, RTCTCOK_OFS))
if (BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCOK_OFS))
return true;
else
return false;
@ -84,40 +85,37 @@ bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
uint_fast16_t formatSelect)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
if (formatSelect)
BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 1;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 1;
else
BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 0;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 0;
RTC_C->rTIM0.b.bSEC = calendarTime->seconds;
RTC_C->rTIM0.b.bMIN = calendarTime->minutes;
RTC_C->rTIM1.b.bHOUR = calendarTime->hours;
RTC_C->rTIM1.b.bDOW = calendarTime->dayOfWeek;
RTC_C->rDATE.b.bDAY = calendarTime->dayOfmonth;
RTC_C->rDATE.b.bMON = calendarTime->month;
RTC_C->rYEAR.r = calendarTime->year;
RTC_C->TIM0 = (calendarTime->minutes<<RTC_C_TIM0_MIN_OFS) | calendarTime->seconds;
RTC_C->TIM1 = (calendarTime->dayOfWeek<<RTC_C_TIM1_DOW_OFS) | calendarTime->hours;
RTC_C->DATE = (calendarTime->month<<RTC_C_DATE_MON_OFS) | calendarTime->dayOfmonth;
RTC_C->YEAR = calendarTime->year;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
RTC_C_Calendar RTC_C_getCalendarTime(void)
{
RTC_C_Calendar tempCal;
while (!(BITBAND_PERI(RTC_C->rCTL13.r, RTCRDY_OFS)))
while (!(BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_RDY_OFS)))
;
tempCal.seconds = RTC_C->rTIM0.b.bSEC;
tempCal.minutes = RTC_C->rTIM0.b.bMIN;
tempCal.hours = RTC_C->rTIM1.b.bHOUR;
tempCal.dayOfWeek = RTC_C->rTIM1.b.bDOW;
tempCal.dayOfmonth = RTC_C->rDATE.b.bDAY;
tempCal.month = RTC_C->rDATE.b.bMON;
tempCal.year = RTC_C->rYEAR.r;
tempCal.seconds = RTC_C->TIM0 & RTC_C_TIM0_SEC_MASK;
tempCal.minutes = (RTC_C->TIM0 & RTC_C_TIM0_MIN_MASK)>>RTC_C_TIM0_MIN_OFS;
tempCal.hours = RTC_C->TIM1 & RTC_C_TIM1_HOUR_MASK;
tempCal.dayOfWeek = (RTC_C->TIM1 & RTC_C_TIM1_DOW_MASK)>>RTC_C_TIM1_DOW_OFS;
tempCal.dayOfmonth = RTC_C->DATE & RTC_C_DATE_DAY_MASK;
tempCal.month = (RTC_C->DATE & RTC_C_DATE_MON_MASK)>>RTC_C_DATE_MON_OFS;
tempCal.year = RTC_C->YEAR;
return (tempCal);
}
@ -127,24 +125,22 @@ void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm,
{
//Each of these is XORed with 0x80 to turn on if an integer is passed,
//or turn OFF if RTC_ALARM_OFF (0x80) is passed.
HWREG8(RTC_C_BASE + OFS_RTCAMINHR) = (minutesAlarm ^ 0x80);
HWREG8(RTC_C_BASE + OFS_RTCAMINHR + 1) = (hoursAlarm ^ 0x80);
HWREG8(RTC_C_BASE + OFS_RTCADOWDAY) = (dayOfWeekAlarm ^ 0x80);
HWREG8(RTC_C_BASE + OFS_RTCADOWDAY + 1) = (dayOfmonthAlarm ^ 0x80);
RTC_C->AMINHR = ((hoursAlarm ^ 0x80) << 8 )| (minutesAlarm ^ 0x80);
RTC_C->ADOWDAY = ((dayOfmonthAlarm ^ 0x80) << 8 )| (dayOfWeekAlarm ^ 0x80);
}
void RTC_C_setCalendarEvent(uint_fast16_t eventSelect)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCTEV_3)) | eventSelect;
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_TEV_3)) | eventSelect;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleEventDivider)
{
HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) &= ~(RT0IP_7);
HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) |=
HWREG8(&RTC_C->PS0CTL + prescaleSelect) &= ~(RTC_C_PS0CTL_RT0IP_7);
HWREG8(&RTC_C->PS0CTL + prescaleSelect) |=
prescaleEventDivider;
}
@ -152,10 +148,10 @@ uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
{
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
return (RTC_C->rPS.b.bRT0PS);
return (RTC_C->PS & RTC_C_PS_RT0PS_MASK);
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
return (RTC_C->rPS.b.bRT1PS);
return (RTC_C->PS & RTC_C_PS_RT1PS_MASK)>>RTC_C_PS_RT1PS_OFS;
} else
{
return (0);
@ -165,70 +161,74 @@ uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleCounterValue)
{
RTC_C->rCTL0.b.bKEY = RTCKEY_H;
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
RTC_C->rPS.b.bRT0PS = prescaleCounterValue;
RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT0PS_MASK) | prescaleCounterValue;
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
RTC_C->rPS.b.bRT1PS = prescaleCounterValue;
RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT1PS_MASK)
| (prescaleCounterValue << RTC_C_PS_RT1PS_OFS);
}
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert)
{
RTC_C->rBCD2BIN = valueToConvert;
return (RTC_C->rBCD2BIN);
RTC_C->BCD2BIN = valueToConvert;
return (RTC_C->BCD2BIN);
}
uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert)
{
RTC_C->rBIN2BCD = valueToConvert;
return (RTC_C->rBIN2BCD);
RTC_C->BIN2BCD = valueToConvert;
return (RTC_C->BIN2BCD);
}
void RTC_C_enableInterrupt(uint8_t interruptMask)
{
if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE))
{
RTC_C->rCTL0.r = RTCKEY | (interruptMask
& (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = RTC_C_KEY | (interruptMask
& (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE));
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 1;
BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 1;
}
if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 1;
BITBAND_PERI(RTC_C->PS1CTL,RTC_C_PS1CTL_RT1PSIE_OFS) = 1;
}
}
void RTC_C_disableInterrupt(uint8_t interruptMask)
{
if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE))
{
RTC_C->rCTL0.r = RTCKEY
| (RTC_C->rCTL0.r
& ~((interruptMask | RTCKEY_M)
& (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)));
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = RTC_C_KEY
| (RTC_C->CTL0 & ~((interruptMask | RTC_C_CTL0_KEY_MASK)
& (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ RTC_C_CTL0_RDYIE)));
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 0;
BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 0;
BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS) = 0;
}
}
@ -240,13 +240,13 @@ uint_fast8_t RTC_C_getInterruptStatus(void)
| RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT
| RTC_C_OSCILLATOR_FAULT_INTERRUPT;
tempInterruptFlagMask |= (RTC_C->rCTL0.r & (interruptFlagMask >> 4));
tempInterruptFlagMask |= (RTC_C->CTL0 & (interruptFlagMask >> 4));
tempInterruptFlagMask = tempInterruptFlagMask << 4;
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
if (BITBAND_PERI(RTC_C->rPS0CTL.r, RT0PSIFG_OFS))
if (BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
@ -254,7 +254,7 @@ uint_fast8_t RTC_C_getInterruptStatus(void)
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
if (BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS))
if (BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
@ -268,32 +268,32 @@ uint_fast8_t RTC_C_getEnabledInterruptStatus(void)
uint32_t intStatus = RTC_C_getInterruptStatus();
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCOFIE_OFS))
if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_OFIE_OFS))
{
intStatus &= ~RTC_C_OSCILLATOR_FAULT_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCTEVIE_OFS))
if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_TEVIE_OFS))
{
intStatus &= ~RTC_C_TIME_EVENT_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCAIE_OFS))
if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_AIE_OFS))
{
intStatus &= ~RTC_C_CLOCK_ALARM_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCRDYIE_OFS))
if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_RDYIE_OFS))
{
intStatus &= ~RTC_C_CLOCK_READ_READY_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rPS0CTL, RT0PSIE_OFS))
if (!BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS))
{
intStatus &= ~RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
if (!BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIE_OFS))
if (!BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS))
{
intStatus &= ~RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
@ -308,19 +308,19 @@ void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask)
+ RTC_C_CLOCK_READ_READY_INTERRUPT
+ RTC_C_OSCILLATOR_FAULT_INTERRUPT))
{
RTC_C->rCTL0.r = RTCKEY
| (RTC_C->rCTL0.r & ~((interruptFlagMask >> 4) | RTCKEY_M));
BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
RTC_C->CTL0 = RTC_C_KEY
| (RTC_C->CTL0 & ~((interruptFlagMask >> 4) | RTC_C_CTL0_KEY_MASK));
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIFG_OFS) = 0;
BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS) = 0;
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS) = 0;
BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS) = 0;
}
}

56
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -82,18 +82,18 @@ typedef struct _RTC_C_Calendar
//The following are values that can be passed to RTC_setCalibrationData()
//
//*****************************************************************************
#define RTC_C_CALIBRATIONFREQ_OFF (RTCCALF_0)
#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1)
#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2)
#define RTC_C_CALIBRATIONFREQ_1HZ (RTCCALF_3)
#define RTC_C_CALIBRATIONFREQ_OFF (RTC_C_CTL13_CALF_0)
#define RTC_C_CALIBRATIONFREQ_512HZ (RTC_C_CTL13_CALF_1)
#define RTC_C_CALIBRATIONFREQ_256HZ (RTC_C_CTL13_CALF_2)
#define RTC_C_CALIBRATIONFREQ_1HZ (RTC_C_CTL13_CALF_3)
//*****************************************************************************
//
//The following are values that can be passed to RTC_setCalibrationData()
//
//*****************************************************************************
#define RTC_C_CALIBRATION_DOWN1PPM ( !(RTCOCALS) )
#define RTC_C_CALIBRATION_UP1PPM (RTCOCALS)
#define RTC_C_CALIBRATION_DOWN1PPM ( !(RTC_C_OCAL_OCALS) )
#define RTC_C_CALIBRATION_UP1PPM (RTC_C_OCAL_OCALS)
//*****************************************************************************
//
@ -101,16 +101,16 @@ typedef struct _RTC_C_Calendar
//RTC_setTemperatureCompensation()
//
//*****************************************************************************
#define RTC_C_COMPENSATION_DOWN1PPM ( !(RTCTCMPS) )
#define RTC_C_COMPENSATION_UP1PPM (RTCTCMPS)
#define RTC_C_COMPENSATION_DOWN1PPM ( !(RTC_C_TCMP_TCMPS) )
#define RTC_C_COMPENSATION_UP1PPM (RTC_C_TCMP_TCMPS)
//*****************************************************************************
//
//The following are values that can be passed to RTC_iniRTC_Calendar()
//
//*****************************************************************************
#define RTC_C_FORMAT_BINARY ( !(RTCBCD) )
#define RTC_C_FORMAT_BCD (RTCBCD)
#define RTC_C_FORMAT_BINARY ( !(RTC_C_CTL13_BCD) )
#define RTC_C_FORMAT_BCD (RTC_C_CTL13_BCD)
//*****************************************************************************
//
@ -125,10 +125,10 @@ typedef struct _RTC_C_Calendar
//in the eventSelect parameter.
//
//*****************************************************************************
#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTCTEV_0)
#define RTC_C_CALENDAREVENT_HOURCHANGE (RTCTEV_1)
#define RTC_C_CALENDAREVENT_NOON (RTCTEV_2)
#define RTC_C_CALENDAREVENT_MIDNIGHT (RTCTEV_3)
#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTC_C_CTL13_TEV_0)
#define RTC_C_CALENDAREVENT_HOURCHANGE (RTC_C_CTL13_TEV_1)
#define RTC_C_CALENDAREVENT_NOON (RTC_C_CTL13_TEV_2)
#define RTC_C_CALENDAREVENT_MIDNIGHT (RTC_C_CTL13_TEV_3)
//*****************************************************************************
//
@ -144,24 +144,24 @@ typedef struct _RTC_C_Calendar
//in the prescaleEventDivider parameter.
//
//*****************************************************************************
#define RTC_C_PSEVENTDIVIDER_2 (RT0IP_0)
#define RTC_C_PSEVENTDIVIDER_4 (RT0IP_1)
#define RTC_C_PSEVENTDIVIDER_8 (RT0IP_2)
#define RTC_C_PSEVENTDIVIDER_16 (RT0IP_3)
#define RTC_C_PSEVENTDIVIDER_32 (RT0IP_4)
#define RTC_C_PSEVENTDIVIDER_64 (RT0IP_5)
#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6)
#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7)
#define RTC_C_PSEVENTDIVIDER_2 (RTC_C_PS0CTL_RT0IP_0)
#define RTC_C_PSEVENTDIVIDER_4 (RTC_C_PS0CTL_RT0IP_1)
#define RTC_C_PSEVENTDIVIDER_8 (RTC_C_PS0CTL_RT0IP_2)
#define RTC_C_PSEVENTDIVIDER_16 (RTC_C_PS0CTL_RT0IP_3)
#define RTC_C_PSEVENTDIVIDER_32 (RTC_C_PS0CTL_RT0IP_4)
#define RTC_C_PSEVENTDIVIDER_64 (RTC_C_PS0CTL_RT0IP_5)
#define RTC_C_PSEVENTDIVIDER_128 (RTC_C_PS0CTL_RT0IP_6)
#define RTC_C_PSEVENTDIVIDER_256 (RTC_C_PS0CTL_RT0IP_7)
//*****************************************************************************
//
//The following are values that can be passed to the interrupt functions
//
//*****************************************************************************
#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTCOFIE
#define RTC_C_TIME_EVENT_INTERRUPT RTCTEVIE
#define RTC_C_CLOCK_ALARM_INTERRUPT RTCAIE
#define RTC_C_CLOCK_READ_READY_INTERRUPT RTCRDYIE
#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTC_C_CTL0_OFIE
#define RTC_C_TIME_EVENT_INTERRUPT RTC_C_CTL0_TEVIE
#define RTC_C_CLOCK_ALARM_INTERRUPT RTC_C_CTL0_AIE
#define RTC_C_CLOCK_READ_READY_INTERRUPT RTC_C_CTL0_RDYIE
#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02
#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01

240
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,12 +41,12 @@
static bool is_A_Module(uint32_t module)
{
if (module == EUSCI_A0_MODULE || module == EUSCI_A1_MODULE
#ifdef EUSCI_A2_MODULE
|| module == EUSCI_A2_MODULE
if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE
#ifdef EUSCI_A2_BASE
|| module == EUSCI_A2_BASE
#endif
#ifdef EUSCI_A3_MODULE
|| module == EUSCI_A3_MODULE
#ifdef EUSCI_A3_BASE
|| module == EUSCI_A3_BASE
#endif
)
return true;
@ -56,6 +56,13 @@ static bool is_A_Module(uint32_t module)
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
/* Returning false if we are not divisible */
if((config->clockSourceFrequency
% config->desiredSpiClock) != 0)
{
return false;
}
if (is_A_Module(moduleInstance))
{
ASSERT(
@ -85,31 +92,31 @@ bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *confi
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* UCMST = Master mode
* UCSYNC = Synchronous mode
* EUSCI_A_CTLW0_MST = Master mode
* EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+ UCMODE_3 + UCSYNC))
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ UCMST + UCSYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->rBRW =
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
return true;
} else
@ -143,24 +150,24 @@ bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *confi
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* UCMST = Master mode
* UCSYNC = Synchronous mode
* EUSCI_A_CTLW0_MST = Master mode
* EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+ UCMODE_3 + UCSYNC))
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ UCMST + UCSYNC + config->spiMode);
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_B_CMSIS(moduleInstance)->rBRW =
EUSCI_B_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
@ -227,14 +234,14 @@ bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
== config->spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (config->clockPhase + config->clockPolarity
+ config->msbFirst + UCSYNC + config->spiMode);
+ config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
return true;
} else
@ -263,14 +270,14 @@ bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
== config->spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (config->clockPhase + config->clockPolarity
+ config->msbFirst + UCSYNC + config->spiMode);
+ config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
return true;
}
@ -418,12 +425,13 @@ uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& HWREG16(moduleInstance + OFS_UCA0IE);
& EUSCI_A_CMSIS(moduleInstance)->IE;
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& HWREG16(moduleInstance + OFS_UCB0IE);
& EUSCI_B_CMSIS(moduleInstance)->IE;
}
}
@ -444,42 +452,42 @@ void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
case EUSCI_A0_MODULE:
case EUSCI_A0_BASE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
case EUSCI_A1_MODULE:
case EUSCI_A1_BASE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
#ifdef EUSCI_A2_MODULE
case EUSCI_A2_MODULE:
#ifdef EUSCI_A2_BASE
case EUSCI_A2_BASE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
#ifdef EUSCI_A3_MODULE
case EUSCI_A3_MODULE:
#ifdef EUSCI_A3_BASE
case EUSCI_A3_BASE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
#endif
case EUSCI_B0_MODULE:
case EUSCI_B0_BASE:
Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB0);
break;
case EUSCI_B1_MODULE:
case EUSCI_B1_BASE:
Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_MODULE
case EUSCI_B2_MODULE:
#ifdef EUSCI_B2_BASE
case EUSCI_B2_BASE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_MODULE
case EUSCI_B3_MODULE:
#ifdef EUSCI_B3_BASE
case EUSCI_B3_BASE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
@ -493,42 +501,42 @@ void SPI_unregisterInterrupt(uint32_t moduleInstance)
{
switch (moduleInstance)
{
case EUSCI_A0_MODULE:
case EUSCI_A0_BASE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
case EUSCI_A1_MODULE:
case EUSCI_A1_BASE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
#ifdef EUSCI_A2_MODULE
case EUSCI_A2_MODULE:
#ifdef EUSCI_A2_BASE
case EUSCI_A2_BASE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
#ifdef EUSCI_A3_MODULE
case EUSCI_A3_MODULE:
#ifdef EUSCI_A3_BASE
case EUSCI_A3_BASE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;
#endif
case EUSCI_B0_MODULE:
case EUSCI_B0_BASE:
Interrupt_disableInterrupt(INT_EUSCIB0);
Interrupt_unregisterInterrupt(INT_EUSCIB0);
break;
case EUSCI_B1_MODULE:
case EUSCI_B1_BASE:
Interrupt_disableInterrupt(INT_EUSCIB1);
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
#ifdef EUSCI_B2_MODULE
case EUSCI_B2_MODULE:
#ifdef EUSCI_B2_BASE
case EUSCI_B2_BASE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
#ifdef EUSCI_B3_MODULE
case EUSCI_B3_MODULE:
#ifdef EUSCI_B3_BASE
case EUSCI_B3_BASE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
@ -568,8 +576,8 @@ void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
|| (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
& ~UCSTEM) | select4PinFunctionality;
EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
& ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality;
}
//*****************************************************************************
@ -590,13 +598,13 @@ void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
EUSCI_B_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@ -628,7 +636,7 @@ void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
@ -658,12 +666,12 @@ bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
& ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
return true;
}
@ -684,7 +692,7 @@ bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
@ -706,13 +714,13 @@ void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
== clockPhase));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
& ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
& ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@ -730,7 +738,7 @@ void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
//*****************************************************************************
void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
EUSCI_B_CMSIS(baseAddress)->rTXBUF.r = transmitData;
EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData;
}
//*****************************************************************************
@ -747,7 +755,7 @@ void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
//*****************************************************************************
uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
{
return EUSCI_B_CMSIS(baseAddress)->rRXBUF.r;
return EUSCI_B_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
@ -776,7 +784,7 @@ void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
EUSCI_B_CMSIS(baseAddress)->rIE.r |= mask;
EUSCI_B_CMSIS(baseAddress)->IE |= mask;
}
//*****************************************************************************
@ -805,7 +813,7 @@ void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
EUSCI_B_CMSIS(baseAddress)->rIE.r &= ~mask;
EUSCI_B_CMSIS(baseAddress)->IE &= ~mask;
}
//*****************************************************************************
@ -834,7 +842,7 @@ uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
return EUSCI_B_CMSIS(baseAddress)->rIFG.r & mask;
return EUSCI_B_CMSIS(baseAddress)->IFG & mask;
}
//*****************************************************************************
@ -859,7 +867,7 @@ void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
EUSCI_B_CMSIS(baseAddress)->rIFG.r &= ~mask;
EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask;
}
//*****************************************************************************
@ -878,7 +886,7 @@ void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
void EUSCI_B_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@ -897,7 +905,7 @@ void EUSCI_B_SPI_enable(uint32_t baseAddress)
void EUSCI_B_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
//*****************************************************************************
@ -914,7 +922,7 @@ void EUSCI_B_SPI_disable(uint32_t baseAddress)
//*****************************************************************************
uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
{
return baseAddress + OFS_UCB0RXBUF;
return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF));
}
//*****************************************************************************
@ -931,7 +939,7 @@ uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
//*****************************************************************************
uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
{
return baseAddress + OFS_UCB0TXBUF;
return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF));
}
//*****************************************************************************
@ -949,7 +957,7 @@ uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
}
//*****************************************************************************
@ -979,8 +987,8 @@ void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
|| (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
& ~UCSTEM) | select4PinFunctionality;
EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
& ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality;
}
//*****************************************************************************
@ -1001,13 +1009,13 @@ void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@ -1039,7 +1047,7 @@ void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
@ -1069,12 +1077,12 @@ bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
& ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
return true;
}
@ -1095,7 +1103,7 @@ bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
@ -1117,13 +1125,13 @@ void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
== clockPhase));
//Disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
& ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
& ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@ -1141,7 +1149,7 @@ void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
//*****************************************************************************
void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
EUSCI_A_CMSIS(baseAddress)->rTXBUF.r = transmitData;
EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData;
}
//*****************************************************************************
@ -1158,7 +1166,7 @@ void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
//*****************************************************************************
uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
{
return EUSCI_A_CMSIS(baseAddress)->rRXBUF.r;
return EUSCI_A_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
@ -1187,7 +1195,7 @@ void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
EUSCI_A_CMSIS(baseAddress)->rIE.r |= mask;
EUSCI_A_CMSIS(baseAddress)->IE |= mask;
}
//*****************************************************************************
@ -1216,7 +1224,7 @@ void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
EUSCI_A_CMSIS(baseAddress)->rIE.r &= ~mask;
EUSCI_A_CMSIS(baseAddress)->IE &= ~mask;
}
//*****************************************************************************
@ -1245,7 +1253,7 @@ uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
return EUSCI_A_CMSIS(baseAddress)->rIFG.r & mask;
return EUSCI_A_CMSIS(baseAddress)->IFG & mask;
}
//*****************************************************************************
@ -1270,7 +1278,7 @@ void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
EUSCI_A_CMSIS(baseAddress)->rIFG.r &= ~mask;
EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask;
}
//*****************************************************************************
@ -1289,7 +1297,7 @@ void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
void EUSCI_A_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@ -1308,7 +1316,7 @@ void EUSCI_A_SPI_enable(uint32_t baseAddress)
void EUSCI_A_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
//*****************************************************************************
@ -1325,7 +1333,7 @@ void EUSCI_A_SPI_disable(uint32_t baseAddress)
//*****************************************************************************
uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
{
return baseAddress + OFS_UCA0RXBUF;
return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
@ -1342,7 +1350,7 @@ uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
//*****************************************************************************
uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
{
return baseAddress + OFS_UCA0TXBUF;
return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF;
}
//*****************************************************************************
@ -1359,5 +1367,5 @@ uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
}

336
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -61,34 +61,34 @@ extern "C"
#include "eusci.h"
/* Configuration Defines */
#define EUSCI_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK
#define EUSCI_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK
#define EUSCI_SPI_MSB_FIRST UCMSB
#define EUSCI_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB
#define EUSCI_SPI_LSB_FIRST 0x00
#define EUSCI_SPI_BUSY UCBUSY
#define EUSCI_SPI_BUSY EUSCI_A_STATW_BUSY
#define EUSCI_SPI_NOT_BUSY 0x00
#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH
#define EUSCI_SPI_3PIN UCMODE_0
#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
#define EUSCI_SPI_3PIN EUSCI_B_CTLW0_MODE_0
#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1
#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
#define EUSCI_SPI_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_SPI_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_SPI_TRANSMIT_INTERRUPT EUSCI_B__TXIE
#define EUSCI_SPI_RECEIVE_INTERRUPT EUSCI_B__RXIE
#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM
#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
//*****************************************************************************
//
//! \typedef eUSCI_SPI_MasterConfig
//! ypedef eUSCI_SPI_MasterConfig
//! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure
//!
//! \struct _eUSCI_SPI_MasterConfig
@ -109,7 +109,7 @@ typedef struct _eUSCI_SPI_MasterConfig
//*****************************************************************************
//
//! \typedef eUSCI_SPI_SlaveConfig
//! ypedef eUSCI_SPI_SlaveConfig
//! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure
//!
//! \struct _eUSCI_SPI_SlaveConfig
@ -131,14 +131,14 @@ typedef struct _eUSCI_SPI_SlaveConfig
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! \param config Configuration structure for SPI master mode
//!
//! <hr>
@ -187,14 +187,14 @@ extern bool SPI_initMaster(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param select4PinFunctionality selects Clock source. Valid values are
//! - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
@ -217,14 +217,14 @@ extern void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param clockSourceFrequency is the frequency of the selected clock source
//! \param desiredSpiClock is the desired clock rate for SPI communication.
@ -244,14 +244,14 @@ extern void SPI_changeMasterClock(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! \param config Configuration structure for SPI slave mode
//!
//! <hr>
@ -295,14 +295,14 @@ extern bool SPI_initSlave(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param clockPhase is clock phase select.
//! Valid values are:
@ -329,14 +329,14 @@ extern void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param transmitData data to be transmitted from the SPI module
//!
@ -357,14 +357,14 @@ extern void SPI_transmitData(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//!
//! This function reads a byte of data from the SPI receive data Register.
@ -381,14 +381,14 @@ extern uint8_t SPI_receiveData(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//!
//! This will enable operation of the SPI block.
@ -405,14 +405,14 @@ extern void SPI_enableModule(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//!
//! This will disable operation of the SPI block.
@ -430,14 +430,14 @@ extern void SPI_disableModule(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//!
//! Returns the address of the SPI RX Buffer. This can be used in conjunction
@ -454,14 +454,14 @@ extern uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//!
//! Returns the address of the SPI TX Buffer. This can be used in conjunction
@ -478,14 +478,14 @@ extern uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//!
//! This function returns an indication of whether or not the SPI bus is
@ -503,14 +503,14 @@ extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param mask is the bit mask of the interrupt sources to be enabled.
//!
@ -535,14 +535,14 @@ extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param mask is the bit mask of the interrupt sources to be
//! disabled.
@ -568,14 +568,14 @@ extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! \param mask Mask of interrupt to filter. This can include:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
@ -600,14 +600,14 @@ extern uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! Modified registers are \b UCAxIFG.
//!
@ -625,14 +625,14 @@ extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! \param mask is the masked interrupt flag to be cleared.
//!
@ -652,14 +652,14 @@ extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//! It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@ -685,14 +685,14 @@ extern void SPI_registerInterrupt(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_B0_MODULE
//! - \b EUSCI_B1_MODULE
//! - \b EUSCI_B2_MODULE
//! - \b EUSCI_B3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! - \b EUSCI_B0_BASE
//! - \b EUSCI_B1_BASE
//! - \b EUSCI_B2_BASE
//! - \b EUSCI_B3_BASE
//!
//! This function unregisters the handler to be called when timer
//! interrupt occurs. This function also masks off the interrupt in the

95
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -83,29 +83,70 @@ static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral)
}
#endif
void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
uint_fast8_t *length, uint32_t **data_address)
{
/* TLV Structure Start Address */
uint32_t *TLV_address = (uint32_t *) TLV_START;
while (((*TLV_address != tag)) // check for tag and instance
&& (*TLV_address != TLV_TAGEND)) // do range check first
{
if (*TLV_address == tag)
{
if(instance == 0)
{
break;
}
/* Repeat until requested instance is reached */
instance--;
}
TLV_address += (*(TLV_address + 1)) + 2;
}
/* Check if Tag match happened... */
if (*TLV_address == tag)
{
/* Return length = Address + 1 */
*length = (*(TLV_address + 1))*4;
/* Return address of first data/value info = Address + 2 */
*data_address = (uint32_t *) (TLV_address + 2);
}
// If there was no tag match and the end of TLV structure was reached..
else
{
// Return 0 for TAG not found
*length = 0;
// Return 0 for TAG not found
*data_address = 0;
}
}
uint_least32_t SysCtl_getSRAMSize(void)
{
return SYSCTL->rSRAM_SIZE;
return SYSCTL->SRAM_SIZE;
}
uint_least32_t SysCtl_getFlashSize(void)
{
return SYSCTL->rFLASH_SIZE;
return SYSCTL->FLASH_SIZE;
}
void SysCtl_disableNMISource(uint_fast8_t flags)
{
SYSCTL->rNMI_CTLSTAT.r &= ~(flags);
SYSCTL->NMI_CTLSTAT &= ~(flags);
}
void SysCtl_enableNMISource(uint_fast8_t flags)
{
SYSCTL->rNMI_CTLSTAT.r |= flags;
SYSCTL->NMI_CTLSTAT |= flags;
}
uint_fast8_t SysCtl_getNMISourceStatus(void)
{
return SYSCTL->rNMI_CTLSTAT.r;
return SYSCTL->NMI_CTLSTAT;
}
void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
@ -113,10 +154,10 @@ void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
ASSERT(SysCtlSRAMBankValid(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
;
SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
}
void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
@ -124,8 +165,8 @@ void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
ASSERT(SysCtlSRAMBankValid(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
;
while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
;
switch (sramBank)
{
@ -160,7 +201,7 @@ void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
return;
}
SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
}
void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
@ -168,10 +209,10 @@ void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
ASSERT(SysCtlSRAMBankValidRet(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
;
while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
;
SYSCTL->rSRAM_BANKRET.r |= sramBank;
SYSCTL->SRAM_BANKRET |= sramBank;
}
void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
@ -179,36 +220,36 @@ void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
ASSERT(SysCtlSRAMBankValidRet(sramBank));
/* Waiting for SRAM Ready Bit to be set */
while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
;
while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
;
SYSCTL->rSRAM_BANKRET.r &= ~sramBank;
SYSCTL->SRAM_BANKRET &= ~sramBank;
}
void SysCtl_rebootDevice(void)
{
SYSCTL->rREBOOT_CTL.r = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
SYSCTL->REBOOT_CTL = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
}
void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
{
ASSERT(SysCtlPeripheralIsValid(devices));
SYSCTL->rPERIHALT_CTL.r &= ~devices;
SYSCTL->PERIHALT_CTL &= ~devices;
}
void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
{
ASSERT(SysCtlPeripheralIsValid(devices));
SYSCTL->rPERIHALT_CTL.r |= devices;
SYSCTL->PERIHALT_CTL |= devices;
}
void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
{
if (resetType)
SYSCTL->rWDTRESET_CTL.r |=
SYSCTL->WDTRESET_CTL |=
SYSCTL_WDTRESET_CTL_TIMEOUT;
else
SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
}
void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
@ -216,20 +257,20 @@ void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
ASSERT(resetType <= SYSCTL_HARD_RESET);
if (resetType)
SYSCTL->rWDTRESET_CTL.r |=
SYSCTL->WDTRESET_CTL |=
SYSCTL_WDTRESET_CTL_VIOLATION;
else
SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
}
void SysCtl_enableGlitchFilter(void)
{
SYSCTL->rDIO_GLTFLT_CTL.r |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
SYSCTL->DIO_GLTFLT_CTL |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
}
void SysCtl_disableGlitchFilter(void)
{
SYSCTL->rDIO_GLTFLT_CTL.r &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
SYSCTL->DIO_GLTFLT_CTL &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
}
uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,

144
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -74,22 +74,22 @@ extern "C"
#define SYSCTL_HARD_RESET 1
#define SYSCTL_SOFT_RESET 0
#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_DMA
#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_WDT
#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_ADC
#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_EUB3
#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_EUB2
#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_EUB1
#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_EUB0
#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_EUA3
#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_EUA2
#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_EUA1
#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_EUA0
#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_T32_0
#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_T16_3
#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_T16_2
#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_T16_1
#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_T16_0
#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
@ -98,12 +98,63 @@ extern "C"
#define SYSCTL_REBOOT_KEY 0x6900
#define SYSCTL_1_2V_REF OFS_TLV_ADC14_REF1P2V_TS30C
#define SYSCTL_1_45V_REF OFS_TLV_ADC14_REF1P45V_TS30C
#define SYSCTL_2_5V_REF OFS_TLV_ADC14_REF2P5V_TS30C
#define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
#define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
#define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
#define SYSCTL_85_DEGREES_C 0
#define SYSCTL_30_DEGREES_C 16
#define SYSCTL_85_DEGREES_C 4
#define SYSCTL_30_DEGREES_C 0
#define TLV_START 0x00201004
#define TLV_TAG_RESERVED1 1
#define TLV_TAG_RESERVED2 2
#define TLV_TAG_CS 3
#define TLV_TAG_FLASHCTL 4
#define TLV_TAG_ADC14 5
#define TLV_TAG_RESERVED6 6
#define TLV_TAG_RESERVED7 7
#define TLV_TAG_REF 8
#define TLV_TAG_RESERVED9 9
#define TLV_TAG_RESERVED10 10
#define TLV_TAG_DEVINFO 11
#define TLV_TAG_DIEREC 12
#define TLV_TAG_RANDNUM 13
#define TLV_TAG_RESERVED14 14
#define TLV_TAG_BSL 15
#define TLV_TAGEND 0x0BD0E11D
//*****************************************************************************
//
// Structures for TLV definitions
//
//*****************************************************************************
typedef struct
{
uint32_t maxProgramPulses;
uint32_t maxErasePulses;
} SysCtl_FlashTLV_Info;
typedef struct
{
uint32_t rDCOIR_FCAL_RSEL04;
uint32_t rDCOIR_FCAL_RSEL5;
uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
uint32_t rDCOIR_CONSTK_RSEL04;
uint32_t rDCOIR_CONSTK_RSEL5;
uint32_t rDCOER_FCAL_RSEL04;
uint32_t rDCOER_FCAL_RSEL5;
uint32_t rDCOER_MAXPOSTUNE_RSEL04;
uint32_t rDCOER_MAXNEGTUNE_RSEL04;
uint32_t rDCOER_MAXPOSTUNE_RSEL5;
uint32_t rDCOER_MAXNEGTUNE_RSEL5;
uint32_t rDCOER_CONSTK_RSEL04;
uint32_t rDCOER_CONSTK_RSEL5;
} SysCtl_CSCalTLV_Info;
//*****************************************************************************
//
@ -138,6 +189,51 @@ extern uint_least32_t SysCtl_getFlashSize(void);
//*****************************************************************************
extern void SysCtl_rebootDevice(void);
//*****************************************************************************
//
//! The TLV structure uses a tag or base address to identify segments of the
//! table where information is stored. Some examples of TLV tags are Peripheral
//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
//! the value of a tag and the length of the tag.
//!
//! \param tag represents the tag for which the information needs to be
//! retrieved.
//! Valid values are:
//! - \b TLV_TAG_RESERVED1
//! - \b TLV_TAG_RESERVED2
//! - \b TLV_TAG_CS
//! - \b TLV_TAG_FLASHCTL
//! - \b TLV_TAG_ADC14
//! - \b TLV_TAG_RESERVED6
//! - \b TLV_TAG_RESERVED7
//! - \b TLV_TAG_REF
//! - \b TLV_TAG_RESERVED9
//! - \b TLV_TAG_RESERVED10
//! - \b TLV_TAG_DEVINFO
//! - \b TLV_TAG_DIEREC
//! - \b TLV_TAG_RANDNUM
//! - \b TLV_TAG_RESERVED14
//! \param instance In some cases a specific tag may have more than one
//! instance. For example there may be multiple instances of timer
//! calibration data present under a single Timer Cal tag. This variable
//! specifies the instance for which information is to be retrieved (0,
//! 1, etc.). When only one instance exists; 0 is passed.
//! \param length Acts as a return through indirect reference. The function
//! retrieves the value of the TLV tag length. This value is pointed to
//! by *length and can be used by the application level once the
//! function is called. If the specified tag is not found then the
//! pointer is null 0.
//! \param data_address acts as a return through indirect reference. Once the
//! function is called data_address points to the pointer that holds the
//! value retrieved from the specified TLV tag. If the specified tag is
//! not found then the pointer is null 0.
//!
//! \return None
//
//*****************************************************************************
extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
uint_fast8_t *length, uint32_t **data_address);
//*****************************************************************************
//
//! Enables a set of banks in the SRAM. This can be used to optimize power
@ -410,7 +506,7 @@ extern void SysCtl_disableGlitchFilter(void);
//!
//! \param refVoltage Reference voltage being used.
//!
//! The \e resetType parameter must be only one of the following values:
//! The \e refVoltage parameter must be only one of the following values:
//! - \b SYSCTL_1_2V_REF
//! - \b SYSCTL_1_45V_REF
//! - \b SYSCTL_2_5V_REF

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

59
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -43,17 +43,21 @@ void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
{
/* Setting up one shot or continuous mode */
if (mode == TIMER32_PERIODIC_MODE)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 1;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
= 1;
else if (mode == TIMER32_FREE_RUN_MODE)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 0;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
= 0;
else
ASSERT(false);
/* Setting the resolution of the timer */
if (resolution == TIMER32_1_MODULE6BIT)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 0;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 0;
else if (resolution == TIMER32_32BIT)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 1;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
= 1;
else
ASSERT(false);
@ -63,33 +67,32 @@ void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
|| resolution == TIMER32_PRESCALER_16
|| resolution == TIMER32_PRESCALER_256);
HWREG32(timer + OFS_TIMER32_CONTROL1) =
(HWREG32(timer + OFS_TIMER32_CONTROL1)
& ~TIMER32_CONTROL1_PRESCALE_M) | preScaler;
TIMER32_CMSIS(timer)->CONTROL = TIMER32_CMSIS(timer)->CONTROL
& (~TIMER32_CONTROL_PRESCALE_MASK) | preScaler;
}
void Timer32_setCount(uint32_t timer, uint32_t count)
{
if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
HWREG32(timer + OFS_TIMER32_LOAD1) = UINT16_MAX;
if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
&& (count > UINT16_MAX))
TIMER32_CMSIS(timer)->LOAD = UINT16_MAX;
else
HWREG32(timer + OFS_TIMER32_LOAD1) = count;
TIMER32_CMSIS(timer)->LOAD = count;
}
void Timer32_setCountInBackground(uint32_t timer, uint32_t count)
{
if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
HWREG32(timer + OFS_TIMER32_BGLOAD1) = UINT16_MAX;
if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
&& (count > UINT16_MAX))
TIMER32_CMSIS(timer)->BGLOAD = UINT16_MAX;
else
HWREG32(timer + OFS_TIMER32_BGLOAD1) = count;
TIMER32_CMSIS(timer)->BGLOAD = count;
}
uint32_t Timer32_getValue(uint32_t timer)
{
return HWREG32(timer + OFS_TIMER32_VALUE1);
return TIMER32_CMSIS(timer)->VALUE;
}
void Timer32_startTimer(uint32_t timer, bool oneShot)
@ -97,40 +100,40 @@ void Timer32_startTimer(uint32_t timer, bool oneShot)
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
if (oneShot)
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
1;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
= 1;
else
HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
0;
BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
= 0;
HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_ENABLE;
TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_ENABLE;
}
void Timer32_haltTimer(uint32_t timer)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_ENABLE;
TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_ENABLE;
}
void Timer32_enableInterrupt(uint32_t timer)
{
HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_IE;
TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_IE;
}
void Timer32_disableInterrupt(uint32_t timer)
{
HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_IE;
TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_IE;
}
void Timer32_clearInterruptFlag(uint32_t timer)
{
HWREG32(timer + OFS_TIMER32_INTCLR1) |= 0x01;
TIMER32_CMSIS(timer)->INTCLR |= 0x01;
}
uint32_t Timer32_getInterruptStatus(uint32_t timer)
{
return HWREG32(timer + OFS_TIMER32_MIS1);
return TIMER32_CMSIS(timer)->MIS;
}
void Timer32_registerInterrupt(uint32_t timerInterrupt,

50
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -63,10 +63,12 @@ extern "C"
// Control specific variables
//
//*****************************************************************************
#define TIMER32_CMSIS(x) ((Timer32_Type *) x)
#define TIMER_OFFSET 0x020
#define TIMER32_0_MODULE TIMER32_BASE
#define TIMER32_1_MODULE (TIMER32_BASE + OFS_TIMER32_LOAD2)
#define TIMER32_0_BASE TIMER32_1
#define TIMER32_1_BASE TIMER32_2
#define TIMER32_0_INTERRUPT INT_T32_INT1
#define TIMER32_1_INTERRUPT INT_T32_INT2
@ -94,8 +96,8 @@ extern "C"
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! \param preScaler is the prescaler (or divider) to apply to the clock
//! source given to the Timer32 module.
@ -130,8 +132,8 @@ extern void Timer32_initModule(uint32_t timer, uint32_t preScaler,
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//! \param count Value of the timer to set. Note that
//! if the timer is in 16-bit mode and a value is passed in that exceeds
//! UINT16_MAX, the value will be truncated to UINT16_MAX.
@ -153,8 +155,8 @@ extern void Timer32_setCount(uint32_t timer, uint32_t count);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//! \param count Value of the timer to set in the background. Note that
//! if the timer is in 16-bit mode and a value is passed in that exceeds
//! UINT16_MAX, the value will be truncated to UINT16_MAX.
@ -174,8 +176,8 @@ extern void Timer32_setCountInBackground(uint32_t timer, uint32_t count);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! \return The current count of the timer.
//
@ -190,8 +192,8 @@ extern uint32_t Timer32_getValue(uint32_t timer);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! \param oneShot sets whether the Timer32 module operates in one shot
//! or continuous mode. In one shot mode, the timer will halt when a zero is
@ -214,8 +216,8 @@ extern void Timer32_startTimer(uint32_t timer, bool oneShot);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! \return None
//
@ -228,8 +230,8 @@ extern void Timer32_haltTimer(uint32_t timer);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! Enables the indicated Timer32 interrupt source.
//!
@ -244,8 +246,8 @@ extern void Timer32_enableInterrupt(uint32_t timer);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! Disables the indicated Timer32 interrupt source.
//!
@ -260,8 +262,8 @@ extern void Timer32_disableInterrupt(uint32_t timer);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! The Timer32 interrupt source is cleared, so that it no longer asserts.
//!
@ -276,8 +278,8 @@ extern void Timer32_clearInterruptFlag(uint32_t timer);
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
//! - \b TIMER32_0_MODULE
//! - \b TIMER32_1_MODULE
//! - \b TIMER32_0_BASE
//! - \b TIMER32_1_BASE
//!
//! This returns the interrupt status for the Timer32 module. A positive value
//! will indicate that an interrupt is pending while a zero value will indicate

188
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -41,53 +41,53 @@
static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
uint16_t clockSourceDivider)
{
TIMER_A_CMSIS(timer)->rCTL.r &= ~ID__8;
TIMER_A_CMSIS(timer)->rEX0.r &= ~TAIDEX_7;
TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_ID__8;
TIMER_A_CMSIS(timer)->EX0 &= ~TIMER_A_EX0_IDEX_MASK;
switch (clockSourceDivider)
{
case TIMER_A_CLOCKSOURCE_DIVIDER_1:
case TIMER_A_CLOCKSOURCE_DIVIDER_2:
TIMER_A_CMSIS(timer)->rCTL.r |= ((clockSourceDivider - 1) << 6);
TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
TIMER_A_CMSIS(timer)->CTL |= ((clockSourceDivider - 1) << 6);
TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_4:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_8:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_3:
case TIMER_A_CLOCKSOURCE_DIVIDER_5:
case TIMER_A_CLOCKSOURCE_DIVIDER_6:
case TIMER_A_CLOCKSOURCE_DIVIDER_7:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__1;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider - 1);
TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__1;
TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_10:
case TIMER_A_CLOCKSOURCE_DIVIDER_12:
case TIMER_A_CLOCKSOURCE_DIVIDER_14:
case TIMER_A_CLOCKSOURCE_DIVIDER_16:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__2;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 2 - 1);
TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__2;
TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 2 - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_20:
case TIMER_A_CLOCKSOURCE_DIVIDER_24:
case TIMER_A_CLOCKSOURCE_DIVIDER_28:
case TIMER_A_CLOCKSOURCE_DIVIDER_32:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 4 - 1);
TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 4 - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_40:
case TIMER_A_CLOCKSOURCE_DIVIDER_48:
case TIMER_A_CLOCKSOURCE_DIVIDER_56:
case TIMER_A_CLOCKSOURCE_DIVIDER_64:
TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 8 - 1);
TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 8 - 1);
break;
}
}
@ -99,7 +99,7 @@ void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode)
|| (TIMER_A_CONTINUOUS_MODE == timerMode)
|| (TIMER_A_UP_MODE == timerMode));
TIMER_A_CMSIS(timer)->rCTL.r |= timerMode;
TIMER_A_CMSIS(timer)->CTL |= timerMode;
}
void Timer_A_configureContinuousMode(uint32_t timer,
@ -164,7 +164,7 @@ void Timer_A_configureContinuousMode(uint32_t timer,
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r = (TIMER_A_CMSIS(timer)->rCTL.r
TIMER_A_CMSIS(timer)->CTL = (TIMER_A_CMSIS(timer)->CTL
& ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+ TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR
+ TIMER_A_TAIE_INTERRUPT_ENABLE))
@ -191,20 +191,20 @@ void Timer_A_configureUpMode(uint32_t timer, const Timer_A_UpModeConfig *config)
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
TIMER_A_CMSIS(timer)->CTL &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + config->timerClear
TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + config->timerClear
+ config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
else
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
}
void Timer_A_configureUpDownMode(uint32_t timer,
@ -227,19 +227,19 @@ void Timer_A_configureUpDownMode(uint32_t timer,
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
TIMER_A_CMSIS(timer)->CTL &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_STOP_MODE
TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_STOP_MODE
+ config->timerClear + config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
else
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
}
void Timer_A_initCapture(uint32_t timer,
@ -312,17 +312,18 @@ void Timer_A_initCapture(uint32_t timer,
|| (TIMER_A_OUTPUTMODE_RESET
== config->captureOutputMode));
}
HWREG16(timer + config->captureRegister) =
(HWREG16(timer + config->captureRegister)
uint8_t idx = (config->captureRegister>>1)-1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
(TIMER_A_CMSIS(timer)->CCTL[idx]
& ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
| TIMER_A_CAPTURE_INPUTSELECT_Vcc
| TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
| TIMER_A_TAIE_INTERRUPT_ENABLE | CM_3))
| TIMER_A_TAIE_INTERRUPT_ENABLE | TIMER_A_CCTLN_CM_3))
| (config->captureMode | config->captureInputSelect
| config->synchronizeCaptureSource
| config->captureInterruptEnable
| config->captureOutputMode | CAP);
| config->captureOutputMode | TIMER_A_CCTLN_CAP);
}
void Timer_A_initCompare(uint32_t timer,
@ -375,26 +376,27 @@ void Timer_A_initCompare(uint32_t timer,
== config->compareOutputMode));
}
HWREG16(timer + config->compareRegister) =
(HWREG16(timer + config->compareRegister)
& ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
| TIMER_A_OUTPUTMODE_RESET_SET | CAP))
| (config->compareInterruptEnable
+ config->compareOutputMode);
uint8_t idx = (config->compareRegister>>1)-1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
(TIMER_A_CMSIS(timer)->CCTL[idx]
& ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
| TIMER_A_OUTPUTMODE_RESET_SET | TIMER_A_CCTLN_CAP))
| (config->compareInterruptEnable + config->compareOutputMode);
TIMER_A_CMSIS(timer)->CCR[idx] = config->compareValue;
HWREG16(timer + config->compareRegister + OFS_TA0R) = config->compareValue;
}
uint16_t Timer_A_getCounterValue(uint32_t timer)
{
uint16_t voteOne, voteTwo, res;
uint_fast16_t voteOne, voteTwo, res;
voteTwo = TIMER_A_CMSIS(timer)->rR;
voteTwo = TIMER_A_CMSIS(timer)->R;
do
{
voteOne = voteTwo;
voteTwo = TIMER_A_CMSIS(timer)->rR;
voteTwo = TIMER_A_CMSIS(timer)->R;
if (voteTwo > voteOne)
res = voteTwo - voteOne;
@ -411,7 +413,7 @@ uint16_t Timer_A_getCounterValue(uint32_t timer)
void Timer_A_clearTimer(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r , TACLR_OFS) = 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL , TIMER_A_CTL_CLR_OFS) = 1;
}
uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
@ -437,7 +439,8 @@ uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
|| (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
== synchronizedSetting));
if (HWREG16(timer + captureCompareRegister) & synchronizedSetting)
uint8_t idx = (captureCompareRegister>>1) - 1;
if (TIMER_A_CMSIS(timer)->CCTL[idx] & synchronizedSetting)
return TIMER_A_CAPTURECOMPARE_INPUT_HIGH;
else
return TIMER_A_CAPTURECOMPARE_INPUT_LOW;
@ -461,7 +464,8 @@ uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
if (HWREGBIT16(timer + captureCompareRegister, OUT_OFS))
uint8_t idx = (captureCompareRegister>>1) - 1;
if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_OUT_OFS))
return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH;
else
return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW;
@ -485,15 +489,19 @@ uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
return HWREG16(timer + OFS_TA0R + captureCompareRegister);
uint8_t idx = (captureCompareRegister>>1) - 1;
return (TIMER_A_CMSIS(timer)->CCR[idx]);
}
void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
uint_fast16_t captureCompareRegister,
uint_fast8_t outputModeOutBitValue)
{
TIMER_A_setOutputForOutputModeOutBitValue(timer, captureCompareRegister,
outputModeOutBitValue);
uint8_t idx = (captureCompareRegister>>1) - 1;
TIMER_A_CMSIS(timer)->CCTL[idx] =
((TIMER_A_CMSIS(timer)->CCTL[idx])
& ~(TIMER_A_OUTPUTMODE_RESET_SET))
| (outputModeOutBitValue);
}
void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
@ -536,25 +544,26 @@ void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
TIMER_A_CMSIS(timer)->rCTL.r &=
TIMER_A_CMSIS(timer)->CTL &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_UP_MODE
TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_UP_MODE
+ TIMER_A_DO_CLEAR);
TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
HWREG16(timer + OFS_TA0CCTL0) &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
TIMER_A_CMSIS(timer)->CCTL[0] &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+ TIMER_A_OUTPUTMODE_RESET_SET);
HWREG16(timer + config->compareRegister) |= config->compareOutputMode;
HWREG16(timer + config->compareRegister + OFS_TA0R) = config->dutyCycle;
uint8_t idx = (config->compareRegister>>1) - 1;
TIMER_A_CMSIS(timer)->CCTL[idx] |= config->compareOutputMode;
TIMER_A_CMSIS(timer)->CCR[idx] = config->dutyCycle;
}
void Timer_A_stopTimer(uint32_t timer)
{
TIMER_A_CMSIS(timer)->rCTL.r &= ~MC_3;
TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_MC_3;
}
void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
@ -569,12 +578,13 @@ void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister));
HWREG16(timer + compareRegister + OFS_TA0R) = compareValue;
uint8_t idx = (compareRegister>>1) - 1;
TIMER_A_CMSIS(timer)->CCR[idx] = compareValue;
}
void Timer_A_clearInterruptFlag(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIFG_OFS) = 0;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IFG_OFS) = 0;
}
void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
@ -595,22 +605,23 @@ void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
HWREGBIT16(timer + captureCompareRegister, CCIFG_OFS) = 0;
uint8_t idx = (captureCompareRegister>>1) - 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIFG_OFS) = 0;
}
void Timer_A_enableInterrupt(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 1;
}
void Timer_A_disableInterrupt(uint32_t timer)
{
BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 0;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 0;
}
uint32_t Timer_A_getInterruptStatus(uint32_t timer)
{
return TIMER_A_CMSIS(timer)->rCTL.b.bIFG;
return (TIMER_A_CMSIS(timer)->CTL) & TIMER_A_CTL_IFG;
}
void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
@ -631,7 +642,8 @@ void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 1;
uint8_t idx = (captureCompareRegister>>1) - 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 1;
}
void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
@ -652,18 +664,21 @@ void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 0;
uint8_t idx = (captureCompareRegister>>1) - 1;
BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 0;
}
uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister, uint_fast16_t mask)
{
return HWREG16(timer + captureCompareRegister) & mask;
uint8_t idx = (captureCompareRegister>>1) - 1;
return (TIMER_A_CMSIS(timer)->CCTL[idx]) & mask;
}
uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
{
if (TIMER_A_CMSIS(timer)->rCTL.r & TAIE)
if (TIMER_A_CMSIS(timer)->CTL & TIMER_A_CTL_IE)
{
return Timer_A_getInterruptStatus(timer);
} else
@ -676,8 +691,9 @@ uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
if (HWREGBIT16(timer + captureCompareRegister, CCIE_OFS))
return Timer_A_getCaptureCompareInterruptStatus(timer,
uint8_t idx = (captureCompareRegister>>1) - 1;
if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS))
return Timer_A_getCaptureCompareInterruptStatus(timer,
captureCompareRegister,
TIMER_A_CAPTURE_OVERFLOW |
TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);
@ -692,19 +708,19 @@ void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect,
{
switch (timer)
{
case TIMER_A0_MODULE:
case TIMER_A0_BASE:
Interrupt_registerInterrupt(INT_TA0_0, intHandler);
Interrupt_enableInterrupt(INT_TA0_0);
break;
case TIMER_A1_MODULE:
case TIMER_A1_BASE:
Interrupt_registerInterrupt(INT_TA1_0, intHandler);
Interrupt_enableInterrupt(INT_TA1_0);
break;
case TIMER_A2_MODULE:
case TIMER_A2_BASE:
Interrupt_registerInterrupt(INT_TA2_0, intHandler);
Interrupt_enableInterrupt(INT_TA2_0);
break;
case TIMER_A3_MODULE:
case TIMER_A3_BASE:
Interrupt_registerInterrupt(INT_TA3_0, intHandler);
Interrupt_enableInterrupt(INT_TA3_0);
break;
@ -715,19 +731,19 @@ void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect,
{
switch (timer)
{
case TIMER_A0_MODULE:
case TIMER_A0_BASE:
Interrupt_registerInterrupt(INT_TA0_N, intHandler);
Interrupt_enableInterrupt(INT_TA0_N);
break;
case TIMER_A1_MODULE:
case TIMER_A1_BASE:
Interrupt_registerInterrupt(INT_TA1_N, intHandler);
Interrupt_enableInterrupt(INT_TA1_N);
break;
case TIMER_A2_MODULE:
case TIMER_A2_BASE:
Interrupt_registerInterrupt(INT_TA2_N, intHandler);
Interrupt_enableInterrupt(INT_TA2_N);
break;
case TIMER_A3_MODULE:
case TIMER_A3_BASE:
Interrupt_registerInterrupt(INT_TA3_N, intHandler);
Interrupt_enableInterrupt(INT_TA3_N);
break;
@ -746,19 +762,19 @@ void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect)
{
switch (timer)
{
case TIMER_A0_MODULE:
case TIMER_A0_BASE:
Interrupt_disableInterrupt(INT_TA0_0);
Interrupt_unregisterInterrupt(INT_TA0_0);
break;
case TIMER_A1_MODULE:
case TIMER_A1_BASE:
Interrupt_disableInterrupt(INT_TA1_0);
Interrupt_unregisterInterrupt(INT_TA1_0);
break;
case TIMER_A2_MODULE:
case TIMER_A2_BASE:
Interrupt_disableInterrupt(INT_TA2_0);
Interrupt_unregisterInterrupt(INT_TA2_0);
break;
case TIMER_A3_MODULE:
case TIMER_A3_BASE:
Interrupt_disableInterrupt(INT_TA3_0);
Interrupt_unregisterInterrupt(INT_TA3_0);
break;
@ -769,19 +785,19 @@ void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect)
{
switch (timer)
{
case TIMER_A0_MODULE:
case TIMER_A0_BASE:
Interrupt_disableInterrupt(INT_TA0_N);
Interrupt_unregisterInterrupt(INT_TA0_N);
break;
case TIMER_A1_MODULE:
case TIMER_A1_BASE:
Interrupt_disableInterrupt(INT_TA1_N);
Interrupt_unregisterInterrupt(INT_TA1_N);
break;
case TIMER_A2_MODULE:
case TIMER_A2_BASE:
Interrupt_disableInterrupt(INT_TA2_N);
Interrupt_unregisterInterrupt(INT_TA2_N);
break;
case TIMER_A3_MODULE:
case TIMER_A3_BASE:
Interrupt_disableInterrupt(INT_TA3_N);
Interrupt_unregisterInterrupt(INT_TA3_N);
break;

329
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -63,14 +63,14 @@ extern "C"
// Timer_A Specific Parameters
//
//*****************************************************************************
#define TIMER_A_CMSIS(x) ((TIMER_A0_Type *) x)
#define TIMER_A_CMSIS(x) ((Timer_A_Type *) x)
#define TIMER_A_CCR0_INTERRUPT 0x00
#define TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT 0x01
//*****************************************************************************
//
//! \typedef Timer_A_ContinuousModeConfig
//! ypedef Timer_A_ContinuousModeConfig
//! \brief Type definition for \link _Timer_A_ContinuousModeConfig \endlink
//! structure
//!
@ -90,7 +90,7 @@ typedef struct _Timer_A_ContinuousModeConfig
//*****************************************************************************
//
//! \typedef Timer_A_UpModeConfig
//! ypedef Timer_A_UpModeConfig
//! \brief Type definition for \link _Timer_A_UpModeConfig \endlink
//! structure
//!
@ -112,7 +112,7 @@ typedef struct _Timer_A_UpModeConfig
//*****************************************************************************
//
//! \typedef Timer_A_UpDownModeConfig
//! ypedef Timer_A_UpDownModeConfig
//! \brief Type definition for \link _Timer_A_UpDownModeConfig \endlink
//! structure
//!
@ -134,7 +134,7 @@ typedef struct _Timer_A_UpDownModeConfig
//*****************************************************************************
//
//! \typedef Timer_A_CaptureModeConfig
//! ypedef Timer_A_CaptureModeConfig
//! \brief Type definition for \link _Timer_A_CaptureModeConfig \endlink
//! structure
//!
@ -156,7 +156,7 @@ typedef struct _Timer_A_CaptureModeConfig
//*****************************************************************************
//
//! \typedef Timer_A_CompareModeConfig
//! ypedef Timer_A_CompareModeConfig
//! \brief Type definition for \link _Timer_A_CompareModeConfig \endlink
//! structure
//!
@ -176,7 +176,7 @@ typedef struct _Timer_A_CompareModeConfig
//*****************************************************************************
//
//! \typedef Timer_A_PWMConfig
//! ypedef Timer_A_PWMConfig
//! \brief Type definition for \link _Timer_A_PWMConfig \endlink
//! structure
//!
@ -237,17 +237,17 @@ typedef struct _Timer_A_PWMConfig
// The following are values that can be passed to the timerMode parameter
//
//*****************************************************************************
#define TIMER_A_STOP_MODE MC_0
#define TIMER_A_UP_MODE MC_1
#define TIMER_A_CONTINUOUS_MODE MC_2
#define TIMER_A_UPDOWN_MODE MC_3
#define TIMER_A_STOP_MODE TIMER_A_CTL_MC_0
#define TIMER_A_UP_MODE TIMER_A_CTL_MC_1
#define TIMER_A_CONTINUOUS_MODE TIMER_A_CTL_MC_2
#define TIMER_A_UPDOWN_MODE TIMER_A_CTL_MC_3
//*****************************************************************************
//
// The following are values that can be passed to the timerClear parameter
//
//*****************************************************************************
#define TIMER_A_DO_CLEAR TACLR
#define TIMER_A_DO_CLEAR TIMER_A_CTL_CLR
#define TIMER_A_SKIP_CLEAR 0x00
//*****************************************************************************
@ -255,10 +255,10 @@ typedef struct _Timer_A_PWMConfig
// The following are values that can be passed to the clockSource parameter
//
//*****************************************************************************
#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TASSEL__TACLK
#define TIMER_A_CLOCKSOURCE_ACLK TASSEL__ACLK
#define TIMER_A_CLOCKSOURCE_SMCLK TASSEL__SMCLK
#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TASSEL__INCLK
#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TIMER_A_CTL_SSEL__TACLK
#define TIMER_A_CLOCKSOURCE_ACLK TIMER_A_CTL_SSEL__ACLK
#define TIMER_A_CLOCKSOURCE_SMCLK TIMER_A_CTL_SSEL__SMCLK
#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TIMER_A_CTL_SSEL__INCLK
//*****************************************************************************
//
@ -266,7 +266,7 @@ typedef struct _Timer_A_PWMConfig
// parameter
//
//*****************************************************************************
#define TIMER_A_TAIE_INTERRUPT_ENABLE TAIE
#define TIMER_A_TAIE_INTERRUPT_ENABLE TIMER_A_CTL_IE
#define TIMER_A_TAIE_INTERRUPT_DISABLE 0x00
//*****************************************************************************
@ -275,7 +275,7 @@ typedef struct _Timer_A_PWMConfig
// captureCompareInterruptEnable_CCR0_CCIE parameter
//
//*****************************************************************************
#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE CCIE
#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE TIMER_A_CCTLN_CCIE
#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE 0x00
//*****************************************************************************
@ -285,7 +285,7 @@ typedef struct _Timer_A_PWMConfig
//
//*****************************************************************************
#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00
#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE
#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE TIMER_A_CCTLN_CCIE
//*****************************************************************************
//
@ -293,10 +293,10 @@ typedef struct _Timer_A_PWMConfig
// parameter
//
//*****************************************************************************
#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA CCIS_0
#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB CCIS_1
#define TIMER_A_CAPTURE_INPUTSELECT_GND CCIS_2
#define TIMER_A_CAPTURE_INPUTSELECT_Vcc CCIS_3
#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA TIMER_A_CCTLN_CCIS_0
#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB TIMER_A_CCTLN_CCIS_1
#define TIMER_A_CAPTURE_INPUTSELECT_GND TIMER_A_CCTLN_CCIS_2
#define TIMER_A_CAPTURE_INPUTSELECT_Vcc TIMER_A_CCTLN_CCIS_3
//*****************************************************************************
//
@ -304,14 +304,14 @@ typedef struct _Timer_A_PWMConfig
// parameter
//
//*****************************************************************************
#define TIMER_A_OUTPUTMODE_OUTBITVALUE OUTMOD_0
#define TIMER_A_OUTPUTMODE_SET OUTMOD_1
#define TIMER_A_OUTPUTMODE_TOGGLE_RESET OUTMOD_2
#define TIMER_A_OUTPUTMODE_SET_RESET OUTMOD_3
#define TIMER_A_OUTPUTMODE_TOGGLE OUTMOD_4
#define TIMER_A_OUTPUTMODE_RESET OUTMOD_5
#define TIMER_A_OUTPUTMODE_TOGGLE_SET OUTMOD_6
#define TIMER_A_OUTPUTMODE_RESET_SET OUTMOD_7
#define TIMER_A_OUTPUTMODE_OUTBITVALUE TIMER_A_CCTLN_OUTMOD_0
#define TIMER_A_OUTPUTMODE_SET TIMER_A_CCTLN_OUTMOD_1
#define TIMER_A_OUTPUTMODE_TOGGLE_RESET TIMER_A_CCTLN_OUTMOD_2
#define TIMER_A_OUTPUTMODE_SET_RESET TIMER_A_CCTLN_OUTMOD_3
#define TIMER_A_OUTPUTMODE_TOGGLE TIMER_A_CCTLN_OUTMOD_4
#define TIMER_A_OUTPUTMODE_RESET TIMER_A_CCTLN_OUTMOD_5
#define TIMER_A_OUTPUTMODE_TOGGLE_SET TIMER_A_CCTLN_OUTMOD_6
#define TIMER_A_OUTPUTMODE_RESET_SET TIMER_A_CCTLN_OUTMOD_7
//*****************************************************************************
//
@ -331,10 +331,10 @@ typedef struct _Timer_A_PWMConfig
// The following are values that can be passed to the captureMode parameter
//
//*****************************************************************************
#define TIMER_A_CAPTUREMODE_NO_CAPTURE CM_0
#define TIMER_A_CAPTUREMODE_RISING_EDGE CM_1
#define TIMER_A_CAPTUREMODE_FALLING_EDGE CM_2
#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3
#define TIMER_A_CAPTUREMODE_NO_CAPTURE TIMER_A_CCTLN_CM_0
#define TIMER_A_CAPTUREMODE_RISING_EDGE TIMER_A_CCTLN_CM_1
#define TIMER_A_CAPTUREMODE_FALLING_EDGE TIMER_A_CCTLN_CM_2
#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE TIMER_A_CCTLN_CM_3
//*****************************************************************************
//
@ -343,23 +343,23 @@ typedef struct _Timer_A_PWMConfig
//
//*****************************************************************************
#define TIMER_A_CAPTURE_ASYNCHRONOUS 0x00
#define TIMER_A_CAPTURE_SYNCHRONOUS SCS
#define TIMER_A_CAPTURE_SYNCHRONOUS TIMER_A_CCTLN_SCS
//*****************************************************************************
//
// The following are values that can be passed to the mask parameter
//
//*****************************************************************************
#define TIMER_A_CAPTURE_OVERFLOW COV
#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG
#define TIMER_A_CAPTURE_OVERFLOW TIMER_A_CCTLN_COV
#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG TIMER_A_CCTLN_CCIFG
//*****************************************************************************
//
// The following are values that can be passed to the synchronized parameter
//
//*****************************************************************************
#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI
#define TIMER_A_READ_CAPTURE_COMPARE_INPUT CCI
#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT TIMER_A_CCTLN_SCCI
#define TIMER_A_READ_CAPTURE_COMPARE_INPUT TIMER_A_CCTLN_CCI
#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH 0x01
@ -371,7 +371,7 @@ typedef struct _Timer_A_PWMConfig
// parameter
//
//*****************************************************************************
#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH OUT
#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH TIMER_A_CCTLN_OUT
#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW 0x00
//*****************************************************************************
@ -400,10 +400,10 @@ typedef struct _Timer_A_PWMConfig
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param timerMode selects Clock source. Valid values are
//! - \b TIMER_A_CONTINUOUS_MODE [Default value]
//! - \b TIMER_A_UPDOWN_MODE
@ -424,10 +424,10 @@ extern void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A continuous mode
//!
//! <hr>
@ -486,10 +486,10 @@ extern void Timer_A_configureContinuousMode(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A Up mode
//!
//! <hr>
@ -553,10 +553,10 @@ extern void Timer_A_configureUpMode(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A UpDown mode
//!
//! <hr>
@ -620,10 +620,10 @@ extern void Timer_A_configureUpDownMode(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A capture mode
//!
//! <hr>
@ -682,10 +682,10 @@ extern void Timer_A_initCapture(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A compare mode
//!
//! <hr>
@ -730,10 +730,10 @@ extern void Timer_A_initCompare(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \returns None
//
@ -746,10 +746,10 @@ extern void Timer_A_clearTimer(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@ -780,10 +780,10 @@ extern uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@ -809,10 +809,10 @@ extern uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@ -837,10 +837,10 @@ extern uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@ -870,10 +870,10 @@ extern void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A PWM mode
//!
//! <hr>
@ -942,10 +942,10 @@ extern void Timer_A_generatePWM(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \returns None
//
@ -958,10 +958,10 @@ extern void Timer_A_stopTimer(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param compareRegister selects the Capture register being used. Valid
//! values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@ -993,10 +993,10 @@ extern void Timer_A_setCompareValue(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \returns The value of the specified timer
//
@ -1009,10 +1009,10 @@ extern uint16_t Timer_A_getCounterValue(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \return None
//
@ -1025,10 +1025,10 @@ extern void Timer_A_clearInterruptFlag(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture-compare register being
//! used. Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@ -1053,10 +1053,10 @@ extern void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \return None
//
@ -1069,10 +1069,10 @@ extern void Timer_A_enableInterrupt(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \return None
//
@ -1085,10 +1085,10 @@ extern void Timer_A_disableInterrupt(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \return uint32_t. Return interrupt status. Valid values are
//! - \b TIMER_A_INTERRUPT_PENDING
@ -1106,10 +1106,10 @@ extern uint32_t Timer_A_getInterruptStatus(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \return uint32_t. Return interrupt status. Valid values are
//! - \b TIMER_A_INTERRUPT_PENDING
@ -1124,10 +1124,10 @@ extern uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer);
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \return None
@ -1142,10 +1142,10 @@ extern void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \return None
@ -1160,10 +1160,10 @@ extern void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \param mask is the mask for the interrupt status
@ -1177,7 +1177,7 @@ extern void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG
//
//*****************************************************************************
uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
extern uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister, uint_fast16_t mask);
//*****************************************************************************
@ -1189,10 +1189,10 @@ uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \returns uint32_t. The mask of the set flags.
@ -1210,10 +1210,10 @@ extern uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \param interruptSelect Selects which timer interrupt handler to
//! register. For the timer module, there are two separate interrupt handlers
@ -1244,10 +1244,10 @@ extern void Timer_A_registerInterrupt(uint32_t timer,
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
//! - \b TIMER_A0_MODULE
//! - \b TIMER_A1_MODULE
//! - \b TIMER_A2_MODULE
//! - \b TIMER_A3_MODULE
//! - \b TIMER_A0_BASE
//! - \b TIMER_A1_BASE
//! - \b TIMER_A2_BASE
//! - \b TIMER_A3_BASE
//!
//! \param interruptSelect Selects which timer interrupt handler to
//! register. For the timer module, there are two separate interrupt handlers
@ -1270,22 +1270,15 @@ extern void Timer_A_unregisterInterrupt(uint32_t timer,
uint_fast8_t interruptSelect);
/* Backwards Compatibility Layer */
#define TIMER_A_startCounter Timer_A_startCounter
#define TIMER_A_clearTimerInterruptFlag Timer_A_clearInterruptFlag
#define TIMER_A_clearCaptureCompareInterruptFlag Timer_A_clearCaptureCompareInterrupt
#define TIMER_A_getCounterValue Timer_A_getCounterValue
#define TIMER_A_setCompareValue Timer_A_setCompareValue
#define TIMER_A_stop Timer_A_stopTimer
#define TIMER_A_setOutputForOutputModeOutBitValue Timer_A_setOutputForOutputModeOutBitValue
#define TIMER_A_enableInterrupt Timer_A_enableInterrupt
#define TIMER_A_disableInterrupt Timer_A_disableInterrupt
#define TIMER_A_getInterruptStatus Timer_A_getInterruptStatus
#define TIMER_A_enableCaptureCompareInterrupt Timer_A_enableCaptureCompareInterrupt
#define TIMER_A_disableCaptureCompareInterrupt Timer_A_disableCaptureCompareInterrupt
#define TIMER_A_getCaptureCompareInterruptStatus Timer_A_getCaptureCompareInterruptStatus
#define TIMER_A_clear Timer_A_clearTimer
#define TIMER_A_getSynchronizedCaptureCompareInput Timer_A_getSynchronizedCaptureCompareInput
#define TIMER_A_getCaptureCompareCount Timer_A_getCaptureCompareCount
#define Timer_A_clearTimerInterrupt Timer_A_clearInterruptFlag
#define Timer_A_clear Timer_A_clearTimer
#define Timer_A_initCaptureMode Timer_A_initCapture
#define Timer_A_initCompareMode Timer_A_initCompare
#define Timer_A_initContinuousMode Timer_A_configureContinuousMode
#define Timer_A_initUpDownMode Timer_A_configureUpDownMode
#define Timer_A_initUpMode Timer_A_configureUpMode
#define Timer_A_outputPWM Timer_A_generatePWM
#define Timer_A_stop Timer_A_stopTimer
//*****************************************************************************
//

130
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -71,51 +71,51 @@ bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
/* Disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/* Clock source select */
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_3)
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
| config->selectClockSource;
/* MSB, LSB select */
if (config->msborLsbFirst)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
/* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
if (config->numberofStopBits)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
/* Parity */
switch (config->parity)
{
case EUSCI_A_UART_NO_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
break;
case EUSCI_A_UART_ODD_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
break;
case EUSCI_A_UART_EVEN_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
break;
}
/* BaudRate Control Register */
EUSCI_A_CMSIS(moduleInstance)->rBRW = config->clockPrescalar;
EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = ((config->secondModReg << 8)
EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
+ (config->firstModReg << 4) + config->overSampling);
/* Asynchronous mode & 8 bit character select & clear mode */
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSYNC | UC7BIT | UCMODE_3 | UCRXEIE | UCBRKIE | UCDORM
| UCTXADDR | UCTXBRK)) | config->uartMode;
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
| EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
return retVal;
}
@ -123,33 +123,33 @@ bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
}
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCRXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
;
return EUSCI_A_CMSIS(moduleInstance)->rRXBUF.r;
return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
void UART_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
void UART_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
@ -164,56 +164,56 @@ uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
+ EUSCI_A_UART_ADDRESS_RECEIVED
+ EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
return EUSCI_A_CMSIS(moduleInstance)->rSTATW.r & mask;
return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
}
void UART_setDormant(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
}
void UART_resetDormant(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 0;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
}
void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
{
/* Set UCTXADDR bit */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXADDR_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
/* Place next byte to be sent into the transmit buffer */
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitAddress;
EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
}
void UART_transmitBreak(uint32_t moduleInstance)
{
/* Set UCTXADDR bit */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXBRK_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
/* If current mode is automatic baud-rate detection */
if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
== (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
== (EUSCI_A_CMSIS(moduleInstance)->CTLW0
& EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r =
EUSCI_A_CMSIS(moduleInstance)->TXBUF =
EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
else
EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = DEFAULT_SYNC;
EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
}
uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCA0RXBUF;
return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
return moduleInstance + OFS_UCA0TXBUF;
return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
}
void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
@ -224,15 +224,15 @@ void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r & ~(UCGLIT_M))
EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
| deglitchTime;
}
void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
uint8_t locMask;
uint_fast8_t locMask;
ASSERT(
!(mask
@ -248,17 +248,17 @@ void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rIE.r |= locMask;
EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r |= locMask;
EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
}
void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
uint8_t locMask;
uint_fast8_t locMask;
ASSERT(
!(mask
@ -273,12 +273,12 @@ void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rIE.r &= ~locMask;
EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r &= ~locMask;
EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
}
uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
@ -290,14 +290,14 @@ uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
return EUSCI_A_CMSIS(moduleInstance)->rIFG.r & mask;
return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
}
uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
{
uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->rIE.r;
uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
{
@ -309,7 +309,7 @@ uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
}
intEnabled = EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r;
intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
{
@ -334,29 +334,29 @@ void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
//Clear the UART interrupt source.
EUSCI_A_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
}
void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
case EUSCI_A0_MODULE:
case EUSCI_A0_BASE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
case EUSCI_A1_MODULE:
case EUSCI_A1_BASE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
#ifdef EUSCI_A2_MODULE
case EUSCI_A2_MODULE:
#ifdef EUSCI_A2_BASE
case EUSCI_A2_BASE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
#ifdef EUSCI_A3_MODULE
case EUSCI_A3_MODULE:
#ifdef EUSCI_A3_BASE
case EUSCI_A3_BASE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
@ -370,22 +370,22 @@ void UART_unregisterInterrupt(uint32_t moduleInstance)
{
switch (moduleInstance)
{
case EUSCI_A0_MODULE:
case EUSCI_A0_BASE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
case EUSCI_A1_MODULE:
case EUSCI_A1_BASE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
#ifdef EUSCI_A2_MODULE
case EUSCI_A2_MODULE:
#ifdef EUSCI_A2_BASE
case EUSCI_A2_BASE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
#ifdef EUSCI_A3_MODULE
case EUSCI_A3_MODULE:
#ifdef EUSCI_A3_BASE
case EUSCI_A3_BASE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;

246
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -61,60 +61,60 @@ extern "C"
#include <msp.h>
#include "eusci.h"
#define DEFAULT_SYNC 0x00
#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
#define DEFAULT_SYNC 0x00
#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
#define EUSCI_A_UART_NO_PARITY 0x00
#define EUSCI_A_UART_ODD_PARITY 0x01
#define EUSCI_A_UART_EVEN_PARITY 0x02
#define EUSCI_A_UART_NO_PARITY 0x00
#define EUSCI_A_UART_ODD_PARITY 0x01
#define EUSCI_A_UART_EVEN_PARITY 0x02
#define EUSCI_A_UART_MSB_FIRST UCMSB
#define EUSCI_A_UART_LSB_FIRST 0x00
#define EUSCI_A_UART_MSB_FIRST EUSCI_A_CTLW0_MSB
#define EUSCI_A_UART_LSB_FIRST 0x00
#define EUSCI_A_UART_MODE UCMODE_0
#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1
#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2
#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3
#define EUSCI_A_UART_MODE EUSCI_A_CTLW0_MODE_0
#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_1
#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_2
#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE EUSCI_A_CTLW0_MODE_3
#define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
#define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK
#define EUSCI_A_UART_CLOCKSOURCE_SMCLK EUSCI_A_CTLW0_SSEL__SMCLK
#define EUSCI_A_UART_CLOCKSOURCE_ACLK EUSCI_A_CTLW0_SSEL__ACLK
#define EUSCI_A_UART_ONE_STOP_BIT 0x00
#define EUSCI_A_UART_TWO_STOP_BITS UCSPB
#define EUSCI_A_UART_ONE_STOP_BIT 0x00
#define EUSCI_A_UART_TWO_STOP_BITS EUSCI_A_CTLW0_SPB
#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01
#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00
#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01
#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00
#define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE
#define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE
#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE
#define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE
#define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE
#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE
#define EUSCI_A_UART_RECEIVE_INTERRUPT EUSCI_A_IE_RXIE
#define EUSCI_A_UART_TRANSMIT_INTERRUPT EUSCI_A_IE_TXIE
#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT EUSCI_A_CTLW0_RXEIE
#define EUSCI_A_UART_BREAKCHAR_INTERRUPT EUSCI_A_CTLW0_BRKIE
#define EUSCI_A_UART_STARTBIT_INTERRUPT EUSCI_A_IE_STTIE
#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT EUSCI_B_IE_STPIE
#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG
#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG
#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG
#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG
#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG EUSCI_A_IFG_RXIFG
#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG EUSCI_A_IFG_TXIFG
#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG EUSCI_A_IFG_STTIFG
#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG EUSCI_A_IFG_TXCPTIFG
#define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN
#define EUSCI_A_UART_FRAMING_ERROR UCFE
#define EUSCI_A_UART_OVERRUN_ERROR UCOE
#define EUSCI_A_UART_PARITY_ERROR UCPE
#define EUSCI_A_UART_BREAK_DETECT UCBRK
#define EUSCI_A_UART_RECEIVE_ERROR UCRXERR
#define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR
#define EUSCI_A_UART_IDLELINE UCIDLE
#define EUSCI_A_UART_BUSY UCBUSY
#define EUSCI_A_UART_LISTEN_ENABLE EUSCI_A_STATW_LISTEN
#define EUSCI_A_UART_FRAMING_ERROR EUSCI_A_STATW_FE
#define EUSCI_A_UART_OVERRUN_ERROR EUSCI_A_STATW_OE
#define EUSCI_A_UART_PARITY_ERROR EUSCI_A_STATW_PE
#define EUSCI_A_UART_BREAK_DETECT EUSCI_A_STATW_BRK
#define EUSCI_A_UART_RECEIVE_ERROR EUSCI_A_STATW_RXERR
#define EUSCI_A_UART_ADDRESS_RECEIVED EUSCI_A_STATW_ADDR_IDLE
#define EUSCI_A_UART_IDLELINE EUSCI_A_STATW_ADDR_IDLE
#define EUSCI_A_UART_BUSY EUSCI_A_STATW_BUSY
#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00
#define EUSCI_A_UART_DEGLITCH_TIME_50ns 0x0001
#define EUSCI_A_UART_DEGLITCH_TIME_100ns 0x0002
#define EUSCI_A_UART_DEGLITCH_TIME_200ns (0x0001 + 0x0002)
#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00
#define EUSCI_A_UART_DEGLITCH_TIME_50ns 0x0001
#define EUSCI_A_UART_DEGLITCH_TIME_100ns 0x0002
#define EUSCI_A_UART_DEGLITCH_TIME_200ns (0x0001 + 0x0002)
//*****************************************************************************
//
//! \typedef eUSCI_eUSCI_UART_Config
//! ypedef eUSCI_eUSCI_UART_Config
//! \brief Type definition for \link _eUSCI_UART_Config \endlink
//! structure
//!
@ -145,10 +145,10 @@ typedef struct _eUSCI_eUSCI_UART_Config
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! \param config Configuration structure for the UART module
//!
//! <hr>
@ -218,10 +218,10 @@ extern bool UART_initModule(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -243,10 +243,10 @@ extern void UART_transmitData(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -267,10 +267,10 @@ extern uint8_t UART_receiveData(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -290,10 +290,10 @@ extern void UART_enableModule(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -313,10 +313,10 @@ extern void UART_disableModule(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -349,10 +349,10 @@ extern uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -375,10 +375,10 @@ extern void UART_setDormant(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -399,10 +399,10 @@ extern void UART_resetDormant(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -427,10 +427,10 @@ extern void UART_transmitAddress(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! asEUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -448,10 +448,10 @@ extern void UART_transmitBreak(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -470,10 +470,10 @@ extern uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -492,10 +492,10 @@ extern uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -522,10 +522,10 @@ extern void UART_selectDeglitchTime(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -557,10 +557,10 @@ extern void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -591,10 +591,10 @@ extern void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -624,10 +624,10 @@ extern uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -645,10 +645,10 @@ extern uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@ -674,10 +674,10 @@ extern void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.
@ -703,10 +703,10 @@ extern void UART_registerInterrupt(uint32_t moduleInstance,
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
//! - \b EUSCI_A0_MODULE
//! - \b EUSCI_A1_MODULE
//! - \b EUSCI_A2_MODULE
//! - \b EUSCI_A3_MODULE
//! - \b EUSCI_A0_BASE
//! - \b EUSCI_A1_BASE
//! - \b EUSCI_A2_BASE
//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.

20
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,31 +45,31 @@
void WDT_A_holdTimer(void)
{
//Set Hold bit
uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTHOLD);
uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_HOLD);
WDT_A->rCTL.r = WDTPW + newWDTStatus;
WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
}
void WDT_A_startTimer(void)
{
//Reset Hold bit
uint8_t newWDTStatus = (WDT_A->rCTL.r & ~(WDTHOLD));
uint8_t newWDTStatus = (WDT_A->CTL & ~(WDT_A_CTL_HOLD));
WDT_A->rCTL.r = WDTPW + newWDTStatus;
WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
}
void WDT_A_clearTimer(void)
{
//Set Counter Clear bit
uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTCNTCL);
uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_CNTCL);
WDT_A->rCTL.r = WDTPW + newWDTStatus;
WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
}
void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
uint_fast8_t clockIterations)
{
WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD +
WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD +
clockSelect + clockIterations;
}
@ -77,7 +77,7 @@ void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
uint_fast8_t clockIterations)
{
WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL
WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD + WDT_A_CTL_TMSEL
+ clockSelect + clockIterations;
}

35
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
View file

@ -1,10 +1,10 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v01_04_00_18
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2015, Texas Instruments Incorporated
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -68,10 +68,11 @@ extern "C"
// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
#define WDT_A_CLOCKSOURCE_SMCLK (WDTSSEL_0)
#define WDT_A_CLOCKSOURCE_ACLK (WDTSSEL_1)
#define WDT_A_CLOCKSOURCE_VLOCLK (WDTSSEL_2)
#define WDT_A_CLOCKSOURCE_XCLK (WDTSSEL_3)
#define WDT_A_CLOCKSOURCE_SMCLK (WDT_A_CTL_SSEL_0)
#define WDT_A_CLOCKSOURCE_ACLK (WDT_A_CTL_SSEL_1)
#define WDT_A_CLOCKSOURCE_VLOCLK (WDT_A_CTL_SSEL_2)
#define WDT_A_CLOCKSOURCE_XCLK (WDT_A_CTL_SSEL_3)
#define WDT_A_CLOCKSOURCE_BCLK (WDT_A_CTL_SSEL_4)
//*****************************************************************************
//
@ -79,14 +80,14 @@ extern "C"
// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
#define WDT_A_CLOCKDIVIDER_2G (WDTIS_0)
#define WDT_A_CLOCKDIVIDER_128M (WDTIS_1)
#define WDT_A_CLOCKDIVIDER_8192K (WDTIS_2)
#define WDT_A_CLOCKDIVIDER_512K (WDTIS_3)
#define WDT_A_CLOCKDIVIDER_32K (WDTIS_4)
#define WDT_A_CLOCKDIVIDER_8192 (WDTIS_5)
#define WDT_A_CLOCKDIVIDER_512 (WDTIS_6)
#define WDT_A_CLOCKDIVIDER_64 (WDTIS_7)
#define WDT_A_CLOCKDIVIDER_2G (WDT_A_CTL_IS_0)
#define WDT_A_CLOCKDIVIDER_128M (WDT_A_CTL_IS_1)
#define WDT_A_CLOCKDIVIDER_8192K (WDT_A_CTL_IS_2)
#define WDT_A_CLOCKDIVIDER_512K (WDT_A_CTL_IS_3)
#define WDT_A_CLOCKDIVIDER_32K (WDT_A_CTL_IS_4)
#define WDT_A_CLOCKDIVIDER_8192 (WDT_A_CTL_IS_5)
#define WDT_A_CLOCKDIVIDER_512 (WDT_A_CTL_IS_6)
#define WDT_A_CLOCKDIVIDER_64 (WDT_A_CTL_IS_7)
#define WDT_A_CLOCKITERATIONS_2G WDT_A_CLOCKDIVIDER_2G
#define WDT_A_CLOCKITERATIONS_128M WDT_A_CLOCKDIVIDER_128M
#define WDT_A_CLOCKITERATIONS_8192K WDT_A_CLOCKDIVIDER_8192K
@ -146,7 +147,7 @@ extern void WDT_A_clearTimer(void);
//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
//! - \b WDT_A_CLOCKSOURCE_ACLK
//! - \b WDT_A_CLOCKSOURCE_VLOCLK
//! - \b WDT_A_CLOCKSOURCE_XCLK
//! - \b WDT_A_CLOCKSOURCE_BCLK
//! \param clockIterations is the number of clock iterations for a watchdog
//! timeout.
//! Valid values are
@ -178,7 +179,7 @@ extern void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
//! - \b WDT_A_CLOCKSOURCE_ACLK
//! - \b WDT_A_CLOCKSOURCE_VLOCLK
//! - \b WDT_A_CLOCKSOURCE_XCLK
//! - \b WDT_A_CLOCKSOURCE_BCLK
//! \param clockIterations is the number of clock iterations for a watchdog
//! interval.
//! Valid values are
@ -264,7 +265,7 @@ extern void WDT_A_setTimeoutReset(uint_fast8_t resetType);
/* Defines for future devices that might have multiple instances */
#define WDT_A_holdTimerMultipleTimer(a) WDT_A_holdTimer()
#define WDT_A_startTimerMultipleTimer(a) WDT_A_startTimer()
#define WDT_A_resetTimerMultipleTimer(a) WDT_A_resetTimer()
#define WDT_A_resetTimerMultipleTimer(a) WDT_A_clearTimer()
#define WDT_A_initWatchdogTimerMultipleTimer(a,b,c) WDT_A_initWatchdogTimer(b,c)
#define WDT_A_initIntervalTimerMultipleTimer(a,b,c) WDT_A_initIntervalTimer(b,c)
#define WDT_A_registerInterruptMultipleTimer(a,b) WDT_A_registerInterrupt(b)

2
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
View file

@ -122,7 +122,7 @@ int main( void )
/* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top
of this file. */
#if configCREATE_SIMPLE_TICKLESS_DEMO == 1
#if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 )
{
main_blinky();
}

12
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
View file

@ -19,7 +19,7 @@
<Column0>233</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
<Column0>277</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<col-names>
@ -39,7 +39,7 @@
<Wnd1>
<Wnd3>
<Tabs>
<Tab>
<Identity>TabID-24437-20285</Identity>
@ -55,7 +55,7 @@
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd1><Wnd3>
<SelectedTab>0</SelectedTab></Wnd3><Wnd4>
<Tabs>
<Tab>
<Identity>TabID-2417-20288</Identity>
@ -67,20 +67,20 @@
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd3></Windows>
<SelectedTab>0</SelectedTab></Wnd4></Windows>
<Editor>
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</Desktop>
</Project>

63
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
View file

@ -9,17 +9,17 @@ TriggerName=main
LimitSize=0
ByteLimit=50
[PlDriver]
MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\TexasInstruments\MSP432P401R.svd
MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.3\arm\CONFIG\debugger\TexasInstruments\MSP432P401R.ddf
FirstRun=0
[Jet]
JetConnSerialNo=73866
JetConnSerialNo=59065
JetConnFoundProbes=
DisableInterrupts=0
MultiCoreRunAll=0
OnlineReset=Software
PrevWtdReset=System
[DebugChecksum]
Checksum=-1201177865
Checksum=-851533712
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0
@ -30,8 +30,8 @@ MixedMode=1
[SWOManager]
SamplingDivider=8192
OverrideClock=0
CpuClock=696008061
SwoClock=560889384
CpuClock=542261577
SwoClock=1953724755
DataLogMode=0
ItmPortsEnabled=63
ItmTermIOPorts=1
@ -64,31 +64,6 @@ ITMportsLogFile=0
ITMlogFile=$PROJ_DIR$\ITM.log
[Breakpoints]
Count=0
[PlCacheRanges]
CustomRanges0=0 0 536870912 1 0
CustomRangesText0=Code
CustomRanges1=0 536870912 33554432 0 0
CustomRangesText1=SRAM
CustomRanges2=0 570425344 33554432 0 0
CustomRangesText2=bit-banding
CustomRanges3=0 1073741824 33554432 2 0
CustomRangesText3=Peripheral
CustomRanges4=0 1107296256 33554432 2 0
CustomRangesText4=bit-banding
CustomRanges5=0 3758096384 536870912 2 0
CustomRangesText5=Private peripheral
[Trace2]
Enabled=0
ShowSource=0
[SWOTraceWindow]
ForcedPcSampling=0
ForcedInterruptLogs=0
ForcedItmLogs=0
EventCPI=0
EventEXC=0
EventFOLD=0
EventLSU=0
EventSLEEP=0
[PowerLog]
Title_0=I0
Symbol_0=0 4 1
@ -139,6 +114,34 @@ Exclusions=
Frequency=10000
Probe0=I0
ProbeSetup0=2 1 1 2 0 0
[XdsDriver]
CStepIntDis=_ 0
[Trace1]
Enabled=0
ShowSource=1
[ETMTraceWindow]
PortWidth=4
PortMode=0
CaptureDataValues=0
CaptureDataAddresses=0
CaptureDataRange=0
DataFirst=0
DataLast=-1
StopWhen=0
StallCPU=0
NoPCCapture=0
[Trace2]
Enabled=0
ShowSource=0
[SWOTraceWindow]
ForcedPcSampling=0
ForcedInterruptLogs=0
ForcedItmLogs=0
EventCPI=0
EventEXC=0
EventFOLD=0
EventLSU=0
EventSLEEP=0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""

8
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
View file

@ -12,7 +12,7 @@
<Column0>307</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
<Column0>362</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build>
@ -32,7 +32,7 @@
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source/tasks.c</ExpandedNode></NodeDict></Session>
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/DriverLibrary</ExpandedNode><ExpandedNode>RTOSDemo/Simply Blinky Demo</ExpandedNode><ExpandedNode>RTOSDemo/System</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
@ -52,14 +52,14 @@
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>67</YPos2><SelStart2>5615</SelStart2><SelEnd2>5615</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>63</YPos2><SelStart2>5983</SelStart2><SelEnd2>5983</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
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</Desktop>
</Workspace>

2
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
View file

@ -1,2 +1,2 @@
[MainWindow]
WindowPlacement=_ 515 5 1615 901 3
WindowPlacement=_ 290 75 1390 947 3

93
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
View file

@ -1,38 +1,38 @@
//*****************************************************************************
//
// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family Interrupt Vector Table for CGT
//
//****************************************************************************
/******************************************************************************
*
* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* MSP432P401R Interrupt Vector Table and startup code for CCS TI ARM
*
*****************************************************************************/
#include <stdint.h>
#include <driverlib.h>
@ -48,6 +48,8 @@ static void defaultISR(void);
/* processor is started */
extern void _c_int00(void);
/* External declaration for system initialization function */
extern void SystemInit(void);
/* Linker variable that marks the top of the stack. */
extern unsigned long __STACK_END;
@ -67,6 +69,7 @@ extern void vT32_1_Handler( void );
/* Intrrupt vector table. Note that the proper constructs must be placed on this to */
/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
/* the program if located at a start address other than 0. */
#pragma RETAIN(interruptVectors)
#pragma DATA_SECTION(interruptVectors, ".intvecs")
void (* const interruptVectors[])(void) =
{
@ -163,6 +166,8 @@ void (* const interruptVectors[])(void) =
/* application. */
void resetISR(void)
{
SystemInit();
/* Jump to the CCS C Initialization Routine. */
MAP_WDT_A_holdTimer();
__asm(" .global _c_int00\n"
@ -175,10 +180,16 @@ void resetISR(void)
/* by a debugger. */
static void nmiISR(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")
/* Enter an infinite loop. */
while(1)
{
}
#pragma diag_pop
}
@ -187,10 +198,16 @@ static void nmiISR(void)
/* for examination by a debugger. */
static void faultISR(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")
/* Enter an infinite loop. */
while(1)
{
}
#pragma diag_pop
}
@ -199,8 +216,14 @@ static void faultISR(void)
/* for examination by a debugger. */
static void defaultISR(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")
/* Enter an infinite loop. */
while(1)
{
}
#pragma diag_pop
}

399
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/system_msp432p401r.c Normal file
View file

@ -0,0 +1,399 @@
/**************************************************************************//**
* @file system_msp432p401r.c
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
* MSP432P401R
* @version V2.1.0
* @date 2016-01-26
*
* @note View configuration instructions embedded in comments
*
******************************************************************************/
//*****************************************************************************
//
// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include <stdint.h>
#include "msp.h"
/*--------------------- Configuration Instructions ----------------------------
1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
#define __HALT_WDT 1
2. Insert your desired CPU frequency in Hz at:
#define __SYSTEM_CLOCK 12000000
3. If you prefer the DC-DC power regulator (more efficient at higher
frequencies), set the __REGULATOR to 1:
#define __REGULATOR 1
*---------------------------------------------------------------------------*/
/*--------------------- Watchdog Timer Configuration ------------------------*/
// Halt the Watchdog Timer
// <0> Do not halt the WDT
// <1> Halt the WDT
#define __HALT_WDT 1
/*--------------------- CPU Frequency Configuration -------------------------*/
// CPU Frequency
// <1500000> 1.5 MHz
// <3000000> 3 MHz
// <12000000> 12 MHz
// <24000000> 24 MHz
// <48000000> 48 MHz
#define __SYSTEM_CLOCK 3000000
/*--------------------- Power Regulator Configuration -----------------------*/
// Power Regulator Mode
// <0> LDO
// <1> DC-DC
#define __REGULATOR 0
/*----------------------------------------------------------------------------
Define clocks, used for SystemCoreClockUpdate()
*---------------------------------------------------------------------------*/
#define __VLOCLK 10000
#define __MODCLK 24000000
#define __LFXT 32768
#define __HFXT 48000000
/*----------------------------------------------------------------------------
Clock Variable definitions
*---------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
uint32_t source, divider;
uint8_t dividerValue;
float dcoConst;
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
dividerValue = 1 << divider;
source = CS->CTL1 & CS_CTL1_SELM_MASK;
switch(source)
{
case CS_CTL1_SELM__LFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
break;
case CS_CTL1_SELM__VLOCLK:
SystemCoreClock = __VLOCLK / dividerValue;
break;
case CS_CTL1_SELM__REFOCLK:
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
break;
case CS_CTL1_SELM__DCOCLK:
dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
case CS_CTL0_DCORSEL_0:
centeredFreq = 1500000;
break;
case CS_CTL0_DCORSEL_1:
centeredFreq = 3000000;
break;
case CS_CTL0_DCORSEL_2:
centeredFreq = 6000000;
break;
case CS_CTL0_DCORSEL_3:
centeredFreq = 12000000;
break;
case CS_CTL0_DCORSEL_4:
centeredFreq = 24000000;
break;
case CS_CTL0_DCORSEL_5:
centeredFreq = 48000000;
break;
}
if(dcoTune == 0)
{
SystemCoreClock = centeredFreq;
}
else
{
if(dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
calVal = TLV->DCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
calVal = TLV->DCOIR_FCAL_RSEL04;
}
SystemCoreClock = (uint32_t) ((centeredFreq)
/ (1
- ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal))))));
}
break;
case CS_CTL1_SELM__MODOSC:
SystemCoreClock = __MODCLK / dividerValue;
break;
case CS_CTL1_SELM__HFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*
* Performs the following initialization steps:
* 1. Enables the FPU
* 2. Halts the WDT if requested
* 3. Enables all SRAM banks
* 4. Sets up power regulator and VCORE
* 5. Enable Flash wait states if needed
* 6. Change MCLK to desired frequency
* 7. Enable Flash read buffering
*/
void SystemInit(void)
{
// Enable FPU if used
#if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
(3UL << 11 * 2)); /* Set CP11 Full Access */
#endif
#if (__HALT_WDT == 1)
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
#endif
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 1.5 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
#endif
// No flash wait states necessary
// DCO = 3 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 12 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
// DCO = 24 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
// Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
// Switches LDO VCORE1 to DCDC VCORE1 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
// DCO = 48 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#endif
}

231
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
View file

@ -1,5 +1,76 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Startup Code for IAR Embedded Workbench for ARM
//
//****************************************************************************
#include <stdint.h>
#include <msp.h>
//*****************************************************************************
//
@ -13,10 +84,10 @@
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
void resetISR(void);
static void nmiSR(void);
static void faultISR(void);
static void intDefaultHandler(void);
void ResetISR(void);
static void NmiSR(void);
static void FaultISR(void);
static void IntDefaultHandler(void);
//*****************************************************************************
//
@ -67,86 +138,86 @@ __root const uVectorEntry __vector_table[] @ ".intvec" =
{
{ .ptr = (uint32_t)systemStack + sizeof(systemStack) },
// The initial stack pointer
resetISR, // The reset handler
nmiSR, // The NMI handler
faultISR, // The hard fault handler
intDefaultHandler, // The MPU fault handler
intDefaultHandler, // The bus fault handler
intDefaultHandler, // The usage fault handler
ResetISR, // The reset handler
NmiSR, // The NMI handler
FaultISR, // The hard fault handler
IntDefaultHandler, // The MPU fault handler
IntDefaultHandler, // The bus fault handler
IntDefaultHandler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
intDefaultHandler, // Debug monitor handler
IntDefaultHandler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
intDefaultHandler, // PSS ISR
intDefaultHandler, // CS ISR
intDefaultHandler, // PCM ISR
intDefaultHandler, // WDT ISR
intDefaultHandler, // FPU ISR
intDefaultHandler, // FLCTL ISR
intDefaultHandler, // COMP0 ISR
intDefaultHandler, // COMP1 ISR
intDefaultHandler, // TA0_0 ISR
intDefaultHandler, // TA0_N ISR
intDefaultHandler, // TA1_0 ISR
intDefaultHandler, // TA1_N ISR
intDefaultHandler, // TA2_0 ISR
intDefaultHandler, // TA2_N ISR
intDefaultHandler, // TA3_0 ISR
intDefaultHandler, // TA3_N ISR
IntDefaultHandler, // PSS ISR
IntDefaultHandler, // CS ISR
IntDefaultHandler, // PCM ISR
IntDefaultHandler, // WDT ISR
IntDefaultHandler, // FPU ISR
IntDefaultHandler, // FLCTL ISR
IntDefaultHandler, // COMP_E0_MODULE ISR
IntDefaultHandler, // COMP_E1_MODULE ISR
IntDefaultHandler, // TA0_0 ISR
IntDefaultHandler, // TA0_N ISR
IntDefaultHandler, // TA1_0 ISR
IntDefaultHandler, // TA1_N ISR
IntDefaultHandler, // TA2_0 ISR
IntDefaultHandler, // TA2_N ISR
IntDefaultHandler, // TA3_0 ISR
IntDefaultHandler, // TA3_N ISR
vUART_Handler, // EUSCIA0 ISR
intDefaultHandler, // EUSCIA1 ISR
intDefaultHandler, // EUSCIA2 ISR
intDefaultHandler, // EUSCIA3 ISR
intDefaultHandler, // EUSCIB0 ISR
intDefaultHandler, // EUSCIB1 ISR
intDefaultHandler, // EUSCIB2 ISR
intDefaultHandler, // EUSCIB3 ISR
intDefaultHandler, // ADC14 ISR
IntDefaultHandler, // EUSCIA1 ISR
IntDefaultHandler, // EUSCIA2 ISR
IntDefaultHandler, // EUSCIA3 ISR
IntDefaultHandler, // EUSCIB0 ISR
IntDefaultHandler, // EUSCIB1 ISR
IntDefaultHandler, // EUSCIB2 ISR
IntDefaultHandler, // EUSCIB3 ISR
IntDefaultHandler, // ADC12 ISR
vT32_0_Handler, // T32_INT1 ISR
vT32_1_Handler, // T32_INT2 ISR
intDefaultHandler, // T32_INTC ISR
intDefaultHandler, // AES ISR
intDefaultHandler, // RTC ISR
intDefaultHandler, // DMA_ERR ISR
intDefaultHandler, // DMA_INT3 ISR
intDefaultHandler, // DMA_INT2 ISR
intDefaultHandler, // DMA_INT1 ISR
intDefaultHandler, // DMA_INT0 ISR
intDefaultHandler, // PORT1 ISR
intDefaultHandler, // PORT2 ISR
intDefaultHandler, // PORT3 ISR
intDefaultHandler, // PORT4 ISR
intDefaultHandler, // PORT5 ISR
intDefaultHandler, // PORT6 ISR
intDefaultHandler, // Reserved 41
intDefaultHandler, // Reserved 42
intDefaultHandler, // Reserved 43
intDefaultHandler, // Reserved 44
intDefaultHandler, // Reserved 45
intDefaultHandler, // Reserved 46
intDefaultHandler, // Reserved 47
intDefaultHandler, // Reserved 48
intDefaultHandler, // Reserved 49
intDefaultHandler, // Reserved 50
intDefaultHandler, // Reserved 51
intDefaultHandler, // Reserved 52
intDefaultHandler, // Reserved 53
intDefaultHandler, // Reserved 54
intDefaultHandler, // Reserved 55
intDefaultHandler, // Reserved 56
intDefaultHandler, // Reserved 57
intDefaultHandler, // Reserved 58
intDefaultHandler, // Reserved 59
intDefaultHandler, // Reserved 60
intDefaultHandler, // Reserved 61
intDefaultHandler, // Reserved 62
intDefaultHandler, // Reserved 63
intDefaultHandler // Reserved 64
IntDefaultHandler, // T32_INTC ISR
IntDefaultHandler, // AES ISR
IntDefaultHandler, // RTC ISR
IntDefaultHandler, // DMA_ERR ISR
IntDefaultHandler, // DMA_INT3 ISR
IntDefaultHandler, // DMA_INT2 ISR
IntDefaultHandler, // DMA_INT1 ISR
IntDefaultHandler, // DMA_INT0 ISR
IntDefaultHandler, // PORT1 ISR
IntDefaultHandler, // PORT2 ISR
IntDefaultHandler, // PORT3 ISR
IntDefaultHandler, // PORT4 ISR
IntDefaultHandler, // PORT5 ISR
IntDefaultHandler, // PORT6 ISR
IntDefaultHandler, // Reserved 41
IntDefaultHandler, // Reserved 42
IntDefaultHandler, // Reserved 43
IntDefaultHandler, // Reserved 44
IntDefaultHandler, // Reserved 45
IntDefaultHandler, // Reserved 46
IntDefaultHandler, // Reserved 47
IntDefaultHandler, // Reserved 48
IntDefaultHandler, // Reserved 49
IntDefaultHandler, // Reserved 50
IntDefaultHandler, // Reserved 51
IntDefaultHandler, // Reserved 52
IntDefaultHandler, // Reserved 53
IntDefaultHandler, // Reserved 54
IntDefaultHandler, // Reserved 55
IntDefaultHandler, // Reserved 56
IntDefaultHandler, // Reserved 57
IntDefaultHandler, // Reserved 58
IntDefaultHandler, // Reserved 59
IntDefaultHandler, // Reserved 60
IntDefaultHandler, // Reserved 61
IntDefaultHandler, // Reserved 62
IntDefaultHandler, // Reserved 63
IntDefaultHandler // Reserved 64
};
//*****************************************************************************
@ -160,10 +231,12 @@ __root const uVectorEntry __vector_table[] @ ".intvec" =
//
//*****************************************************************************
void
resetISR(void)
ResetISR(void)
{
void SystemInit(void);
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
// Initialize the device
SystemInit();
//
// Call the application's entry point.
@ -179,7 +252,7 @@ resetISR(void)
//
//*****************************************************************************
static void
nmiSR(void)
NmiSR(void)
{
//
// Enter an infinite loop.
@ -197,7 +270,7 @@ nmiSR(void)
//
//*****************************************************************************
static void
faultISR(void)
FaultISR(void)
{
//
// Enter an infinite loop.
@ -215,7 +288,7 @@ faultISR(void)
//
//*****************************************************************************
static void
intDefaultHandler(void)
IntDefaultHandler(void)
{
//
// Go into an infinite loop.

434
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c Normal file
View file

@ -0,0 +1,434 @@
/*
* -------------------------------------------
* MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
/**************************************************************************//**
* @file system_msp432p401r.c
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
* MSP432P401R
* @version V1.00
* @date 20-Oct-2015
*
* @note View configuration instructions embedded in comments
*
******************************************************************************/
//*****************************************************************************
//
// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include <stdint.h>
#include "msp.h"
/*--------------------- Configuration Instructions ----------------------------
1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
#define __HALT_WDT 1
2. Insert your desired CPU frequency in Hz at:
#define __SYSTEM_CLOCK 3000000
3. If you prefer the DC-DC power regulator (more efficient at higher
frequencies), set the __REGULATOR to 1:
#define __REGULATOR 1
*---------------------------------------------------------------------------*/
/*--------------------- Watchdog Timer Configuration ------------------------*/
// Halt the Watchdog Timer
// <0> Do not halt the WDT
// <1> Halt the WDT
#define __HALT_WDT 1
/*--------------------- CPU Frequency Configuration -------------------------*/
// CPU Frequency
// <1500000> 1.5 MHz
// <3000000> 3 MHz
// <12000000> 12 MHz
// <24000000> 24 MHz
// <48000000> 48 MHz
#define __SYSTEM_CLOCK 1500000
/*--------------------- Power Regulator Configuration -----------------------*/
// Power Regulator Mode
// <0> LDO
// <1> DC-DC
#define __REGULATOR 1
/*----------------------------------------------------------------------------
Define clocks, used for SystemCoreClockUpdate()
*---------------------------------------------------------------------------*/
#define __VLOCLK 10000
#define __MODCLK 24000000
#define __LFXT 32768
#define __HFXT 48000000
/*----------------------------------------------------------------------------
Clock Variable definitions
*---------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
uint32_t source, divider;
uint8_t dividerValue;
float dcoConst;
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
dividerValue = 1 << divider;
source = CS->CTL1 & CS_CTL1_SELM_MASK;
switch(source)
{
case CS_CTL1_SELM__LFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
break;
case CS_CTL1_SELM__VLOCLK:
SystemCoreClock = __VLOCLK / dividerValue;
break;
case CS_CTL1_SELM__REFOCLK:
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
break;
case CS_CTL1_SELM__DCOCLK:
dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
case CS_CTL0_DCORSEL_0:
centeredFreq = 1500000;
break;
case CS_CTL0_DCORSEL_1:
centeredFreq = 3000000;
break;
case CS_CTL0_DCORSEL_2:
centeredFreq = 6000000;
break;
case CS_CTL0_DCORSEL_3:
centeredFreq = 12000000;
break;
case CS_CTL0_DCORSEL_4:
centeredFreq = 24000000;
break;
case CS_CTL0_DCORSEL_5:
centeredFreq = 48000000;
break;
}
if(dcoTune == 0)
{
SystemCoreClock = centeredFreq;
}
else
{
if(dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
calVal = TLV->DCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
calVal = TLV->DCOIR_FCAL_RSEL04;
}
SystemCoreClock = (uint32_t) ((centeredFreq)
/ (1
- ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal))))));
}
break;
case CS_CTL1_SELM__MODOSC:
SystemCoreClock = __MODCLK / dividerValue;
break;
case CS_CTL1_SELM__HFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*
* Performs the following initialization steps:
* 1. Enables the FPU
* 2. Halts the WDT if requested
* 3. Enables all SRAM banks
* 4. Sets up power regulator and VCORE
* 5. Enable Flash wait states if needed
* 6. Change MCLK to desired frequency
* 7. Enable Flash read buffering
*/
void SystemInit(void)
{
// Enable FPU if used
#if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
(3UL << 11 * 2)); /* Set CP11 Full Access */
#endif
#if (__HALT_WDT == 1)
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
#endif
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 1.5 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
#endif
// No flash wait states necessary
// DCO = 3 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 12 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
// DCO = 24 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
// Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
// Switches LDO VCORE1 to DCDC VCORE1 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
// DCO = 48 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#endif
}

244
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s
View file

@ -43,85 +43,85 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD IntDefault_Handler ; PSS ISR
DCD IntDefault_Handler ; CS ISR
DCD IntDefault_Handler ; PCM ISR
DCD IntDefault_Handler ; WDT ISR
DCD IntDefault_Handler ; FPU ISR
DCD IntDefault_Handler ; FLCTL ISR
DCD IntDefault_Handler ; COMP0 ISR
DCD IntDefault_Handler ; COMP1 ISR
DCD IntDefault_Handler ; TA0_0 ISR
DCD IntDefault_Handler ; TA0_N ISR
DCD IntDefault_Handler ; TA1_0 ISR
DCD IntDefault_Handler ; TA1_N ISR
DCD IntDefault_Handler ; TA2_0 ISR
DCD IntDefault_Handler ; TA2_N ISR
DCD IntDefault_Handler ; TA3_0 ISR
DCD IntDefault_Handler ; TA3_N ISR
DCD PSS_IRQHandler ; 0: PSS Interrupt
DCD CS_IRQHandler ; 1: CS Interrupt
DCD PCM_IRQHandler ; 2: PCM Interrupt
DCD WDT_A_IRQHandler ; 3: WDT_A Interrupt
DCD FPU_IRQHandler ; 4: FPU Interrupt
DCD FLCTL_IRQHandler ; 5: FLCTL Interrupt
DCD COMP_E0_IRQHandler ; 6: COMP_E0 Interrupt
DCD COMP_E1_IRQHandler ; 7: COMP_E1 Interrupt
DCD TA0_0_IRQHandler ; 8: TA0_0 Interrupt
DCD TA0_N_IRQHandler ; 9: TA0_N Interrupt
DCD TA1_0_IRQHandler ; 10: TA1_0 Interrupt
DCD TA1_N_IRQHandler ; 11: TA1_N Interrupt
DCD TA2_0_IRQHandler ; 12: TA2_0 Interrupt
DCD TA2_N_IRQHandler ; 13: TA2_N Interrupt
DCD TA3_0_IRQHandler ; 14: TA3_0 Interrupt
DCD TA3_N_IRQHandler ; 15: TA3_N Interrupt
DCD vUART_Handler ; EUSCIA0 ISR
DCD IntDefault_Handler ; EUSCIA1 ISR
DCD IntDefault_Handler ; EUSCIA2 ISR
DCD IntDefault_Handler ; EUSCIA3 ISR
DCD IntDefault_Handler ; EUSCIB0 ISR
DCD IntDefault_Handler ; EUSCIB1 ISR
DCD IntDefault_Handler ; EUSCIB2 ISR
DCD IntDefault_Handler ; EUSCIB3 ISR
DCD IntDefault_Handler ; ADC12 ISR
DCD EUSCIA1_IRQHandler ; 17: EUSCIA1 Interrupt
DCD EUSCIA2_IRQHandler ; 18: EUSCIA2 Interrupt
DCD EUSCIA3_IRQHandler ; 19: EUSCIA3 Interrupt
DCD EUSCIB0_IRQHandler ; 20: EUSCIB0 Interrupt
DCD EUSCIB1_IRQHandler ; 21: EUSCIB1 Interrupt
DCD EUSCIB2_IRQHandler ; 22: EUSCIB2 Interrupt
DCD EUSCIB3_IRQHandler ; 23: EUSCIB3 Interrupt
DCD ADC14_IRQHandler ; 24: ADC14 Interrupt
DCD vT32_0_Handler ; T32_INT1 ISR
DCD vT32_1_Handler ; T32_INT2 ISR
DCD IntDefault_Handler ; T32_INTC ISR
DCD IntDefault_Handler ; AES ISR
DCD IntDefault_Handler ; RTC ISR
DCD IntDefault_Handler ; DMA_ERR ISR
DCD IntDefault_Handler ; DMA_INT3 ISR
DCD IntDefault_Handler ; DMA_INT2 ISR
DCD IntDefault_Handler ; DMA_INT1 ISR
DCD IntDefault_Handler ; DMA_INT0 ISR
DCD IntDefault_Handler ; PORT1 ISR
DCD IntDefault_Handler ; PORT2 ISR
DCD IntDefault_Handler ; PORT3 ISR
DCD IntDefault_Handler ; PORT4 ISR
DCD IntDefault_Handler ; PORT5 ISR
DCD IntDefault_Handler ; PORT6 ISR
DCD IntDefault_Handler ; Reserved 41
DCD IntDefault_Handler ; Reserved 42
DCD IntDefault_Handler ; Reserved 43
DCD IntDefault_Handler ; Reserved 44
DCD IntDefault_Handler ; Reserved 45
DCD IntDefault_Handler ; Reserved 46
DCD IntDefault_Handler ; Reserved 47
DCD IntDefault_Handler ; Reserved 48
DCD IntDefault_Handler ; Reserved 49
DCD IntDefault_Handler ; Reserved 50
DCD IntDefault_Handler ; Reserved 51
DCD IntDefault_Handler ; Reserved 52
DCD IntDefault_Handler ; Reserved 53
DCD IntDefault_Handler ; Reserved 54
DCD IntDefault_Handler ; Reserved 55
DCD IntDefault_Handler ; Reserved 56
DCD IntDefault_Handler ; Reserved 57
DCD IntDefault_Handler ; Reserved 58
DCD IntDefault_Handler ; Reserved 59
DCD IntDefault_Handler ; Reserved 60
DCD IntDefault_Handler ; Reserved 61
DCD IntDefault_Handler ; Reserved 62
DCD IntDefault_Handler ; Reserved 63
DCD IntDefault_Handler ; Reserved 64
DCD T32_INTC_IRQHandler ; 27: T32_INTC Interrupt
DCD AES256_IRQHandler ; 28: AES256 Interrupt
DCD RTC_C_IRQHandler ; 29: RTC_C Interrupt
DCD DMA_ERR_IRQHandler ; 30: DMA_ERR Interrupt
DCD DMA_INT3_IRQHandler ; 31: DMA_INT3 Interrupt
DCD DMA_INT2_IRQHandler ; 32: DMA_INT2 Interrupt
DCD DMA_INT1_IRQHandler ; 33: DMA_INT1 Interrupt
DCD DMA_INT0_IRQHandler ; 34: DMA_INT0 Interrupt
DCD PORT1_IRQHandler ; 35: PORT1 Interrupt
DCD PORT2_IRQHandler ; 36: PORT2 Interrupt
DCD PORT3_IRQHandler ; 37: PORT3 Interrupt
DCD PORT4_IRQHandler ; 38: PORT4 Interrupt
DCD PORT5_IRQHandler ; 39: PORT5 Interrupt
DCD PORT6_IRQHandler ; 40: PORT6 Interrupt
DCD 0 ; 41: Reserved
DCD 0 ; 42: Reserved
DCD 0 ; 43: Reserved
DCD 0 ; 44: Reserved
DCD 0 ; 45: Reserved
DCD 0 ; 46: Reserved
DCD 0 ; 47: Reserved
DCD 0 ; 48: Reserved
DCD 0 ; 49: Reserved
DCD 0 ; 50: Reserved
DCD 0 ; 51: Reserved
DCD 0 ; 52: Reserved
DCD 0 ; 53: Reserved
DCD 0 ; 54: Reserved
DCD 0 ; 55: Reserved
DCD 0 ; 56: Reserved
DCD 0 ; 57: Reserved
DCD 0 ; 58: Reserved
DCD 0 ; 59: Reserved
DCD 0 ; 60: Reserved
DCD 0 ; 61: Reserved
DCD 0 ; 62: Reserved
DCD 0 ; 63: Reserved
DCD 0 ; 64: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -153,10 +153,30 @@ HardFault_Handler\
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
@ -165,14 +185,97 @@ SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
IntDefault_Handler PROC
EXPORT IntDefault_Handler [WEAK]
Default_Handler PROC
EXPORT PSS_IRQHandler [WEAK]
EXPORT CS_IRQHandler [WEAK]
EXPORT PCM_IRQHandler [WEAK]
EXPORT WDT_A_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT FLCTL_IRQHandler [WEAK]
EXPORT COMP_E0_IRQHandler [WEAK]
EXPORT COMP_E1_IRQHandler [WEAK]
EXPORT TA0_0_IRQHandler [WEAK]
EXPORT TA0_N_IRQHandler [WEAK]
EXPORT TA1_0_IRQHandler [WEAK]
EXPORT TA1_N_IRQHandler [WEAK]
EXPORT TA2_0_IRQHandler [WEAK]
EXPORT TA2_N_IRQHandler [WEAK]
EXPORT TA3_0_IRQHandler [WEAK]
EXPORT TA3_N_IRQHandler [WEAK]
EXPORT EUSCIA0_IRQHandler [WEAK]
EXPORT EUSCIA1_IRQHandler [WEAK]
EXPORT EUSCIA2_IRQHandler [WEAK]
EXPORT EUSCIA3_IRQHandler [WEAK]
EXPORT EUSCIB0_IRQHandler [WEAK]
EXPORT EUSCIB1_IRQHandler [WEAK]
EXPORT EUSCIB2_IRQHandler [WEAK]
EXPORT EUSCIB3_IRQHandler [WEAK]
EXPORT ADC14_IRQHandler [WEAK]
EXPORT T32_INT1_IRQHandler [WEAK]
EXPORT T32_INT2_IRQHandler [WEAK]
EXPORT T32_INTC_IRQHandler [WEAK]
EXPORT AES256_IRQHandler [WEAK]
EXPORT RTC_C_IRQHandler [WEAK]
EXPORT DMA_ERR_IRQHandler [WEAK]
EXPORT DMA_INT3_IRQHandler [WEAK]
EXPORT DMA_INT2_IRQHandler [WEAK]
EXPORT DMA_INT1_IRQHandler [WEAK]
EXPORT DMA_INT0_IRQHandler [WEAK]
EXPORT PORT1_IRQHandler [WEAK]
EXPORT PORT2_IRQHandler [WEAK]
EXPORT PORT3_IRQHandler [WEAK]
EXPORT PORT4_IRQHandler [WEAK]
EXPORT PORT5_IRQHandler [WEAK]
EXPORT PORT6_IRQHandler [WEAK]
PSS_IRQHandler
CS_IRQHandler
PCM_IRQHandler
WDT_A_IRQHandler
FPU_IRQHandler
FLCTL_IRQHandler
COMP_E0_IRQHandler
COMP_E1_IRQHandler
TA0_0_IRQHandler
TA0_N_IRQHandler
TA1_0_IRQHandler
TA1_N_IRQHandler
TA2_0_IRQHandler
TA2_N_IRQHandler
TA3_0_IRQHandler
TA3_N_IRQHandler
EUSCIA0_IRQHandler
EUSCIA1_IRQHandler
EUSCIA2_IRQHandler
EUSCIA3_IRQHandler
EUSCIB0_IRQHandler
EUSCIB1_IRQHandler
EUSCIB2_IRQHandler
EUSCIB3_IRQHandler
ADC14_IRQHandler
T32_INT1_IRQHandler
T32_INT2_IRQHandler
T32_INTC_IRQHandler
AES256_IRQHandler
RTC_C_IRQHandler
DMA_ERR_IRQHandler
DMA_INT3_IRQHandler
DMA_INT2_IRQHandler
DMA_INT1_IRQHandler
DMA_INT0_IRQHandler
PORT1_IRQHandler
PORT2_IRQHandler
PORT3_IRQHandler
PORT4_IRQHandler
PORT5_IRQHandler
PORT6_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
@ -185,13 +288,14 @@ IntDefault_Handler PROC
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN

398
FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_msp432p401r.c Normal file
View file

@ -0,0 +1,398 @@
/**************************************************************************//**
* @file system_msp432p401r.c
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
* MSP432P401R
* @version V1.00
* @date 20-Oct-2015
*
* @note View configuration instructions embedded in comments
*
******************************************************************************/
//*****************************************************************************
//
// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include <stdint.h>
#include "msp.h"
/*--------------------- Configuration Instructions ----------------------------
1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
#define __HALT_WDT 1
2. Insert your desired CPU frequency in Hz at:
#define __SYSTEM_CLOCK 3000000
3. If you prefer the DC-DC power regulator (more efficient at higher
frequencies), set the __REGULATOR to 1:
#define __REGULATOR 1
*---------------------------------------------------------------------------*/
/*--------------------- Watchdog Timer Configuration ------------------------*/
// Halt the Watchdog Timer
// <0> Do not halt the WDT
// <1> Halt the WDT
#define __HALT_WDT 1
/*--------------------- CPU Frequency Configuration -------------------------*/
// CPU Frequency
// <1500000> 1.5 MHz
// <3000000> 3 MHz
// <12000000> 12 MHz
// <24000000> 24 MHz
// <48000000> 48 MHz
#define __SYSTEM_CLOCK 1500000
/*--------------------- Power Regulator Configuration -----------------------*/
// Power Regulator Mode
// <0> LDO
// <1> DC-DC
#define __REGULATOR 1
/*----------------------------------------------------------------------------
Define clocks, used for SystemCoreClockUpdate()
*---------------------------------------------------------------------------*/
#define __VLOCLK 10000
#define __MODCLK 24000000
#define __LFXT 32768
#define __HFXT 48000000
/*----------------------------------------------------------------------------
Clock Variable definitions
*---------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
uint32_t source, divider;
uint8_t dividerValue;
float dcoConst;
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
dividerValue = 1 << divider;
source = CS->CTL1 & CS_CTL1_SELM_MASK;
switch(source)
{
case CS_CTL1_SELM__LFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
break;
case CS_CTL1_SELM__VLOCLK:
SystemCoreClock = __VLOCLK / dividerValue;
break;
case CS_CTL1_SELM__REFOCLK:
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
break;
case CS_CTL1_SELM__DCOCLK:
dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
case CS_CTL0_DCORSEL_0:
centeredFreq = 1500000;
break;
case CS_CTL0_DCORSEL_1:
centeredFreq = 3000000;
break;
case CS_CTL0_DCORSEL_2:
centeredFreq = 6000000;
break;
case CS_CTL0_DCORSEL_3:
centeredFreq = 12000000;
break;
case CS_CTL0_DCORSEL_4:
centeredFreq = 24000000;
break;
case CS_CTL0_DCORSEL_5:
centeredFreq = 48000000;
break;
}
if(dcoTune == 0)
{
SystemCoreClock = centeredFreq;
}
else
{
if(dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
calVal = TLV->DCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
calVal = TLV->DCOIR_FCAL_RSEL04;
}
SystemCoreClock = (uint32_t) ((centeredFreq)
/ (1
- ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal))))));
}
break;
case CS_CTL1_SELM__MODOSC:
SystemCoreClock = __MODCLK / dividerValue;
break;
case CS_CTL1_SELM__HFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*
* Performs the following initialization steps:
* 1. Enables the FPU
* 2. Halts the WDT if requested
* 3. Enables all SRAM banks
* 4. Sets up power regulator and VCORE
* 5. Enable Flash wait states if needed
* 6. Change MCLK to desired frequency
* 7. Enable Flash read buffering
*/
void SystemInit(void)
{
// Enable FPU if used
#if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
(3UL << 11 * 2)); /* Set CP11 Full Access */
#endif
#if (__HALT_WDT == 1)
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
#endif
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 1.5 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
#endif
// No flash wait states necessary
// DCO = 3 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 12 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
// DCO = 24 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
// Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
// Switches LDO VCORE1 to DCDC VCORE1 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
// DCO = 48 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#endif
}

2
FreeRTOS/Demo/Common/Minimal/TimerDemo.c
View file

@ -302,7 +302,7 @@ TickType_t xTimer;
}
else
{
configASSERT( strcmp( pcTimerGetTimerName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
configASSERT( strcmp( pcTimerGetName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
/* The scheduler has not yet started, so the block period of
portMAX_DELAY should just get set to zero in xTimerStart(). Also,

14
FreeRTOS/Demo/Common/ReadMe.txt Normal file
View file

@ -0,0 +1,14 @@
Contains the files that are not specific to any one demo, but are instead used
by all the demo applications.
Most of the directories are now obsolete, and only maintained for backward
compatibility. The directories in active use are:
+ Minimal - this contains the implementation of what are referred to as the
"Standard Demo Tasks". These are used by all the demo applications. Their only
purpose is to demonstrate the FreeRTOS API and test the FreeRTOS features. The
directory is called 'Minimal' as it contains a minimal implementation of files
contained in the 'Full' directory - but the 'Full' directory is no longer used.
+ include - contains header files for the C source files located in the Minimal
directory.

24
FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewd
View file

@ -153,7 +153,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
<version>29</version>
<version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -318,6 +318,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
<option>
<name>variablewatch</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -563,7 +567,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
<version>29</version>
<version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -728,6 +732,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
<option>
<name>variablewatch</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -973,7 +981,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
<version>29</version>
<version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -1138,6 +1146,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
<option>
<name>variablewatch</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -1383,7 +1395,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
<version>29</version>
<version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -1548,6 +1560,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
<option>
<name>variablewatch</name>
<state>0</state>
</option>
</data>
</settings>
<settings>

24
FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp
View file

@ -10,7 +10,7 @@
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>17</archiveVersion>
<archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@ -754,7 +754,7 @@
</option>
<option>
<name>FormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -948,7 +948,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -1139,7 +1139,7 @@
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>17</archiveVersion>
<archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@ -1883,7 +1883,7 @@
</option>
<option>
<name>FormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -2077,7 +2077,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -2268,7 +2268,7 @@
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>17</archiveVersion>
<archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@ -3012,7 +3012,7 @@
</option>
<option>
<name>FormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -3206,7 +3206,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -3397,7 +3397,7 @@
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>17</archiveVersion>
<archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@ -4141,7 +4141,7 @@
</option>
<option>
<name>FormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>
@ -4335,7 +4335,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
<version>8</version>
<version>9</version>
<state>2</state>
</option>
<option>

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