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Add MPU project for multiple MEC17xx devices.

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Richard Barry 2016-12-11 22:56:30 +00:00
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

218
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* The MPU version of port.c includes and excludes functions depending on the
settings within this file. Therefore, to ensure all the functions in port.c
build, this configuration file has all options turned on. */
#define configUSE_PREEMPTION 1
#define configTICK_RATE_HZ ( 1000 )
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_QUEUE_SETS 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ 48000000
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 5
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configSUPPORT_STATIC_ALLOCATION 1
#define configUSE_TICKLESS_IDLE 0
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 2
/* Run time stats gathering definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE()
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 0
#define INCLUDE_xSemaphoreGetMutexHolder 1
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
#define INCLUDE_xTaskAbortDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 3 /* 7 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define xPortPendSVHandler PendSV_Handler
#define vPortSVCHandler SVC_Handler
#define xPortSysTickHandler SysTick_Handler
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
/* LED not used at present, so just increment a variable to keep a count of the
number of times the LED would otherwise have been toggled. */
#define configTOGGLE_LED() ulLED++
/* Definitions for the messages that can be sent to the check task. */
#define configREG_TEST_1_STILL_EXECUTING ( 0 )
#define configREG_TEST_2_STILL_EXECUTING ( 1 )
#define configTIMER_STILL_EXECUTING ( 2 )
#define configPRINT_SYSTEM_STATUS ( 3 )
/* Parameters that are passed into the third and fourth register check tasks
solely for the purpose of ensuring parameters are passed into tasks correctly. */
#define configREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x11112222 )
#define configREG_TEST_TASK_3_PARAMETER ( ( void * ) 0x12345678 )
#define configREG_TEST_TASK_4_PARAMETER ( ( void * ) 0x87654321 )
#ifdef __cplusplus
}
#endif
#endif /* FREERTOS_CONFIG_H */

35
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/JLinkSettings.ini Normal file
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Unspecified"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

600
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c;*.S</cExt>
<aExt></aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>RTOSDemo_GCC_MPU</TargetName>
<ToolsetNumber>0x3</ToolsetNumber>
<ToolsetName>ARM-GNU</ToolsetName>
<TargetOption>
<CLKARM>12000000</CLKARM>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>120</PageWidth>
<PageLength>65</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>init_app.ini</tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59101789 -O3047 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8006 -TDT0 -TDC1F -TIE1 -TIP8 -TB1 -TFE0 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=1377,131,1842,431,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UV1115SAE -O3047 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8028 -TDT0 -TDC1F -TIE1 -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>2428</LineNumber>
<EnabledFlag>1</EnabledFlag>
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<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>C:\E\Dev\FreeRTOS\Trial\Active\Microchip_CEC1302\WorkingCopy\Source\tasks.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\RTOSDemo\../../../Source/tasks.c\2428</Expression>
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<Bp>
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<ExecCommand></ExecCommand>
<Expression>\\RTOSDemo\../main.c\851</Expression>
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<Bp>
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<ExecCommand></ExecCommand>
<Expression>\\RTOSDemo\../../../Source/portable/GCC/ARM_CM4_MPU/port.c\307</Expression>
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<ExecCommand></ExecCommand>
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<WatchWindow1>
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FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx Normal file
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@ -0,0 +1,443 @@
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</Project>

692
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/RegTest.c Normal file
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@ -0,0 +1,692 @@
/*
FreeRTOS V9.0.0 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "queue.h"
/*
* "Reg test" tasks - These fill the registers with known values, then check
* that each register maintains its expected value for the lifetime of the
* task. Each task uses a different set of values. The reg test tasks execute
* with a very low priority, so get preempted very frequently. A register
* containing an unexpected value is indicative of an error in the context
* switching mechanism.
*/
void vRegTest1Implementation( void *pvParameters );
void vRegTest2Implementation( void *pvParameters );
void vRegTest3Implementation( void ) __attribute__ ((naked));
void vRegTest4Implementation( void ) __attribute__ ((naked));
/*
* Used as an easy way of deleting a task from inline assembly.
*/
extern void vMainDeleteMe( void ) __attribute__((noinline));
/*
* Used by the first two reg test tasks and a software timer callback function
* to send messages to the check task. The message just lets the check task
* know that the tasks and timer are still functioning correctly. If a reg test
* task detects an error it will delete itself, and in so doing prevent itself
* from sending any more 'I'm Alive' messages to the check task.
*/
extern void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber );
/* The queue used to send a message to the check task. */
extern QueueHandle_t xGlobalScopeCheckQueue;
/*-----------------------------------------------------------*/
void vRegTest1Implementation( void *pvParameters )
{
/* This task is created in privileged mode so can access the file scope
queue variable. Take a stack copy of this before the task is set into user
mode. Once this task is in user mode the file scope queue variable will no
longer be accessible but the stack copy will. */
QueueHandle_t xQueue = xGlobalScopeCheckQueue;
/* Now the queue handle has been obtained the task can switch to user
mode. This is just one method of passing a handle into a protected
task, the other reg test task uses the task parameter instead. */
portSWITCH_TO_USER_MODE();
/* First check that the parameter value is as expected. */
if( pvParameters != ( void * ) configREG_TEST_TASK_1_PARAMETER )
{
/* Error detected. Delete the task so it stops communicating with
the check task. */
vMainDeleteMe();
}
for( ;; )
{
/* This task tests the kernel context switch mechanism by reading and
writing directly to registers - which requires the test to be written
in assembly code. */
__asm volatile
(
" MOV R4, #104 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */
" MOV R5, #105 \n"
" MOV R6, #106 \n"
" MOV R8, #108 \n"
" MOV R9, #109 \n"
" MOV R10, #110 \n"
" MOV R11, #111 \n"
"reg1loop: \n"
" MOV R0, #100 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */
" MOV R1, #101 \n"
" MOV R2, #102 \n"
" MOV R3, #103 \n"
" MOV R12, #112 \n"
" SVC #1 \n" /* Yield just to increase test coverage. */
" CMP R0, #100 \n" /* Check all the registers still contain their expected values. */
" BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task. */
" CMP R1, #101 \n"
" BNE vMainDeleteMe \n"
" CMP R2, #102 \n"
" BNE vMainDeleteMe \n"
" CMP R3, #103 \n"
" BNE vMainDeleteMe \n"
" CMP R4, #104 \n"
" BNE vMainDeleteMe \n"
" CMP R5, #105 \n"
" BNE vMainDeleteMe \n"
" CMP R6, #106 \n"
" BNE vMainDeleteMe \n"
" CMP R8, #108 \n"
" BNE vMainDeleteMe \n"
" CMP R9, #109 \n"
" BNE vMainDeleteMe \n"
" CMP R10, #110 \n"
" BNE vMainDeleteMe \n"
" CMP R11, #111 \n"
" BNE vMainDeleteMe \n"
" CMP R12, #112 \n"
" BNE vMainDeleteMe \n"
:::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"
);
/* Send configREG_TEST_1_STILL_EXECUTING to the check task to indicate that this
task is still functioning. */
vMainSendImAlive( xQueue, configREG_TEST_1_STILL_EXECUTING );
/* Go back to check all the register values again. */
__asm volatile( " B reg1loop " );
}
}
/*-----------------------------------------------------------*/
void vRegTest2Implementation( void *pvParameters )
{
/* The queue handle is passed in as the task parameter. This is one method of
passing data into a protected task, the other reg test task uses a different
method. */
QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
for( ;; )
{
/* This task tests the kernel context switch mechanism by reading and
writing directly to registers - which requires the test to be written
in assembly code. */
__asm volatile
(
" MOV R4, #4 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */
" MOV R5, #5 \n"
" MOV R6, #6 \n"
" MOV R8, #8 \n" /* Frame pointer is omitted as it must not be changed. */
" MOV R9, #9 \n"
" MOV R10, 10 \n"
" MOV R11, #11 \n"
"reg2loop: \n"
" MOV R0, #13 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */
" MOV R1, #1 \n"
" MOV R2, #2 \n"
" MOV R3, #3 \n"
" MOV R12, #12 \n"
" CMP R0, #13 \n" /* Check all the registers still contain their expected values. */
" BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task */
" CMP R1, #1 \n"
" BNE vMainDeleteMe \n"
" CMP R2, #2 \n"
" BNE vMainDeleteMe \n"
" CMP R3, #3 \n"
" BNE vMainDeleteMe \n"
" CMP R4, #4 \n"
" BNE vMainDeleteMe \n"
" CMP R5, #5 \n"
" BNE vMainDeleteMe \n"
" CMP R6, #6 \n"
" BNE vMainDeleteMe \n"
" CMP R8, #8 \n"
" BNE vMainDeleteMe \n"
" CMP R9, #9 \n"
" BNE vMainDeleteMe \n"
" CMP R10, #10 \n"
" BNE vMainDeleteMe \n"
" CMP R11, #11 \n"
" BNE vMainDeleteMe \n"
" CMP R12, #12 \n"
" BNE vMainDeleteMe \n"
:::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"
);
/* Send configREG_TEST_2_STILL_EXECUTING to the check task to indicate that this
task is still functioning. */
vMainSendImAlive( xQueue, configREG_TEST_2_STILL_EXECUTING );
/* Go back to check all the register values again. */
__asm volatile( " B reg2loop " );
}
}
/*-----------------------------------------------------------*/
void vRegTest3Implementation( void )
{
__asm volatile
(
".extern pulRegTest3LoopCounter \n"
"/* Fill the core registers with known values. */ \n"
"mov r0, #100 \n"
"mov r1, #101 \n"
"mov r2, #102 \n"
"mov r3, #103 \n"
"mov r4, #104 \n"
"mov r5, #105 \n"
"mov r6, #106 \n"
"mov r7, #107 \n"
"mov r8, #108 \n"
"mov r9, #109 \n"
"mov r10, #110 \n"
"mov r11, #111 \n"
"mov r12, #112 \n"
"/* Fill the VFP registers with known values. */ \n"
"vmov d0, r0, r1 \n"
"vmov d1, r2, r3 \n"
"vmov d2, r4, r5 \n"
"vmov d3, r6, r7 \n"
"vmov d4, r8, r9 \n"
"vmov d5, r10, r11 \n"
"vmov d6, r0, r1 \n"
"vmov d7, r2, r3 \n"
"vmov d8, r4, r5 \n"
"vmov d9, r6, r7 \n"
"vmov d10, r8, r9 \n"
"vmov d11, r10, r11 \n"
"vmov d12, r0, r1 \n"
"vmov d13, r2, r3 \n"
"vmov d14, r4, r5 \n"
"vmov d15, r6, r7 \n"
"reg1_loop: \n"
"/* Check all the VFP registers still contain the values set above. \n"
"First save registers that are clobbered by the test. */ \n"
"push { r0-r1 } \n"
"vmov r0, r1, d0 \n"
"cmp r0, #100 \n"
"bne reg1_error_loopf \n"
"cmp r1, #101 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d1 \n"
"cmp r0, #102 \n"
"bne reg1_error_loopf \n"
"cmp r1, #103 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d2 \n"
"cmp r0, #104 \n"
"bne reg1_error_loopf \n"
"cmp r1, #105 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d3 \n"
"cmp r0, #106 \n"
"bne reg1_error_loopf \n"
"cmp r1, #107 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d4 \n"
"cmp r0, #108 \n"
"bne reg1_error_loopf \n"
"cmp r1, #109 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d5 \n"
"cmp r0, #110 \n"
"bne reg1_error_loopf \n"
"cmp r1, #111 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d6 \n"
"cmp r0, #100 \n"
"bne reg1_error_loopf \n"
"cmp r1, #101 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d7 \n"
"cmp r0, #102 \n"
"bne reg1_error_loopf \n"
"cmp r1, #103 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d8 \n"
"cmp r0, #104 \n"
"bne reg1_error_loopf \n"
"cmp r1, #105 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d9 \n"
"cmp r0, #106 \n"
"bne reg1_error_loopf \n"
"cmp r1, #107 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d10 \n"
"cmp r0, #108 \n"
"bne reg1_error_loopf \n"
"cmp r1, #109 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d11 \n"
"cmp r0, #110 \n"
"bne reg1_error_loopf \n"
"cmp r1, #111 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d12 \n"
"cmp r0, #100 \n"
"bne reg1_error_loopf \n"
"cmp r1, #101 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d13 \n"
"cmp r0, #102 \n"
"bne reg1_error_loopf \n"
"cmp r1, #103 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d14 \n"
"cmp r0, #104 \n"
"bne reg1_error_loopf \n"
"cmp r1, #105 \n"
"bne reg1_error_loopf \n"
"vmov r0, r1, d15 \n"
"cmp r0, #106 \n"
"bne reg1_error_loopf \n"
"cmp r1, #107 \n"
"bne reg1_error_loopf \n"
"/* Restore the registers that were clobbered by the test. */ \n"
"pop {r0-r1} \n"
"/* VFP register test passed. Jump to the core register test. */ \n"
"b reg1_loopf_pass \n"
"reg1_error_loopf: \n"
"/* If this line is hit then a VFP register value was found to be incorrect. */ \n"
"b reg1_error_loopf \n"
"reg1_loopf_pass: \n"
"cmp r0, #100 \n"
"bne reg1_error_loop \n"
"cmp r1, #101 \n"
"bne reg1_error_loop \n"
"cmp r2, #102 \n"
"bne reg1_error_loop \n"
"cmp r3, #103 \n"
"bne reg1_error_loop \n"
"cmp r4, #104 \n"
"bne reg1_error_loop \n"
"cmp r5, #105 \n"
"bne reg1_error_loop \n"
"cmp r6, #106 \n"
"bne reg1_error_loop \n"
"cmp r7, #107 \n"
"bne reg1_error_loop \n"
"cmp r8, #108 \n"
"bne reg1_error_loop \n"
"cmp r9, #109 \n"
"bne reg1_error_loop \n"
"cmp r10, #110 \n"
"bne reg1_error_loop \n"
"cmp r11, #111 \n"
"bne reg1_error_loop \n"
"cmp r12, #112 \n"
"bne reg1_error_loop \n"
"/* Everything passed, increment the loop counter. */ \n"
"push { r0-r1 } \n"
"ldr r0, =pulRegTest3LoopCounter \n"
"ldr r0, [r0] \n"
"ldr r1, [r0] \n"
"adds r1, r1, #1 \n"
"str r1, [r0] \n"
"pop { r0-r1 } \n"
"/* Start again. */ \n"
"b reg1_loop \n"
"reg1_error_loop: \n"
"/* If this line is hit then there was an error in a core register value. \n"
"The loop ensures the loop counter stops incrementing. */ \n"
"b reg1_error_loop \n"
"nop "
); /* __asm volatile. */
}
/*-----------------------------------------------------------*/
void vRegTest4Implementation( void )
{
__asm volatile
(
".extern pulRegTest4LoopCounter \n"
"/* Set all the core registers to known values. */ \n"
"mov r0, #-1 \n"
"mov r1, #1 \n"
"mov r2, #2 \n"
"mov r3, #3 \n"
"mov r4, #4 \n"
"mov r5, #5 \n"
"mov r6, #6 \n"
"mov r7, #7 \n"
"mov r8, #8 \n"
"mov r9, #9 \n"
"mov r10, #10 \n"
"mov r11, #11 \n"
"mov r12, #12 \n"
"/* Set all the VFP to known values. */ \n"
"vmov d0, r0, r1 \n"
"vmov d1, r2, r3 \n"
"vmov d2, r4, r5 \n"
"vmov d3, r6, r7 \n"
"vmov d4, r8, r9 \n"
"vmov d5, r10, r11 \n"
"vmov d6, r0, r1 \n"
"vmov d7, r2, r3 \n"
"vmov d8, r4, r5 \n"
"vmov d9, r6, r7 \n"
"vmov d10, r8, r9 \n"
"vmov d11, r10, r11 \n"
"vmov d12, r0, r1 \n"
"vmov d13, r2, r3 \n"
"vmov d14, r4, r5 \n"
"vmov d15, r6, r7 \n"
"reg2_loop: \n"
"/* Check all the VFP registers still contain the values set above. \n"
"First save registers that are clobbered by the test. */ \n"
"push { r0-r1 } \n"
"vmov r0, r1, d0 \n"
"cmp r0, #-1 \n"
"bne reg2_error_loopf \n"
"cmp r1, #1 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d1 \n"
"cmp r0, #2 \n"
"bne reg2_error_loopf \n"
"cmp r1, #3 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d2 \n"
"cmp r0, #4 \n"
"bne reg2_error_loopf \n"
"cmp r1, #5 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d3 \n"
"cmp r0, #6 \n"
"bne reg2_error_loopf \n"
"cmp r1, #7 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d4 \n"
"cmp r0, #8 \n"
"bne reg2_error_loopf \n"
"cmp r1, #9 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d5 \n"
"cmp r0, #10 \n"
"bne reg2_error_loopf \n"
"cmp r1, #11 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d6 \n"
"cmp r0, #-1 \n"
"bne reg2_error_loopf \n"
"cmp r1, #1 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d7 \n"
"cmp r0, #2 \n"
"bne reg2_error_loopf \n"
"cmp r1, #3 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d8 \n"
"cmp r0, #4 \n"
"bne reg2_error_loopf \n"
"cmp r1, #5 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d9 \n"
"cmp r0, #6 \n"
"bne reg2_error_loopf \n"
"cmp r1, #7 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d10 \n"
"cmp r0, #8 \n"
"bne reg2_error_loopf \n"
"cmp r1, #9 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d11 \n"
"cmp r0, #10 \n"
"bne reg2_error_loopf \n"
"cmp r1, #11 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d12 \n"
"cmp r0, #-1 \n"
"bne reg2_error_loopf \n"
"cmp r1, #1 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d13 \n"
"cmp r0, #2 \n"
"bne reg2_error_loopf \n"
"cmp r1, #3 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d14 \n"
"cmp r0, #4 \n"
"bne reg2_error_loopf \n"
"cmp r1, #5 \n"
"bne reg2_error_loopf \n"
"vmov r0, r1, d15 \n"
"cmp r0, #6 \n"
"bne reg2_error_loopf \n"
"cmp r1, #7 \n"
"bne reg2_error_loopf \n"
"/* Restore the registers that were clobbered by the test. */ \n"
"pop {r0-r1} \n"
"/* VFP register test passed. Jump to the core register test. */ \n"
"b reg2_loopf_pass \n"
"reg2_error_loopf: \n"
"/* If this line is hit then a VFP register value was found to be \n"
"incorrect. */ \n"
"b reg2_error_loopf \n"
"reg2_loopf_pass: \n"
"cmp r0, #-1 \n"
"bne reg2_error_loop \n"
"cmp r1, #1 \n"
"bne reg2_error_loop \n"
"cmp r2, #2 \n"
"bne reg2_error_loop \n"
"cmp r3, #3 \n"
"bne reg2_error_loop \n"
"cmp r4, #4 \n"
"bne reg2_error_loop \n"
"cmp r5, #5 \n"
"bne reg2_error_loop \n"
"cmp r6, #6 \n"
"bne reg2_error_loop \n"
"cmp r7, #7 \n"
"bne reg2_error_loop \n"
"cmp r8, #8 \n"
"bne reg2_error_loop \n"
"cmp r9, #9 \n"
"bne reg2_error_loop \n"
"cmp r10, #10 \n"
"bne reg2_error_loop \n"
"cmp r11, #11 \n"
"bne reg2_error_loop \n"
"cmp r12, #12 \n"
"bne reg2_error_loop \n"
"/* Increment the loop counter so the check task knows this task is \n"
"still running. */ \n"
"push { r0-r1 } \n"
"ldr r0, =pulRegTest4LoopCounter \n"
"ldr r0, [r0] \n"
"ldr r1, [r0] \n"
"adds r1, r1, #1 \n"
"str r1, [r0] \n"
"pop { r0-r1 } \n"
"/* Yield to increase test coverage. */ \n"
"SVC #1 \n"
"/* Start again. */ \n"
"b reg2_loop \n"
"reg2_error_loop: \n"
"/* If this line is hit then there was an error in a core register value. \n"
"This loop ensures the loop counter variable stops incrementing. */ \n"
"b reg2_error_loop \n"
); /* __asm volatile */
}
/*-----------------------------------------------------------*/
/* Fault handlers are here for convenience as they use compiler specific syntax
and this file is specific to the GCC compiler. */
void hard_fault_handler( uint32_t * hardfault_args )
{
volatile uint32_t stacked_r0;
volatile uint32_t stacked_r1;
volatile uint32_t stacked_r2;
volatile uint32_t stacked_r3;
volatile uint32_t stacked_r12;
volatile uint32_t stacked_lr;
volatile uint32_t stacked_pc;
volatile uint32_t stacked_psr;
stacked_r0 = ((uint32_t) hardfault_args[ 0 ]);
stacked_r1 = ((uint32_t) hardfault_args[ 1 ]);
stacked_r2 = ((uint32_t) hardfault_args[ 2 ]);
stacked_r3 = ((uint32_t) hardfault_args[ 3 ]);
stacked_r12 = ((uint32_t) hardfault_args[ 4 ]);
stacked_lr = ((uint32_t) hardfault_args[ 5 ]);
stacked_pc = ((uint32_t) hardfault_args[ 6 ]);
stacked_psr = ((uint32_t) hardfault_args[ 7 ]);
/* Inspect stacked_pc to locate the offending instruction. */
for( ;; );
( void ) stacked_psr;
( void ) stacked_pc;
( void ) stacked_lr;
( void ) stacked_r12;
( void ) stacked_r0;
( void ) stacked_r1;
( void ) stacked_r2;
( void ) stacked_r3;
}
/*-----------------------------------------------------------*/
void HardFault_Handler( void ) __attribute__((naked));
void HardFault_Handler( void )
{
__asm volatile
(
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
" ldr r1, [r0, #24] \n"
" ldr r2, handler_address_const \n"
" bx r2 \n"
" handler_address_const: .word hard_fault_handler \n"
);
}
/*-----------------------------------------------------------*/
void MemManage_Handler( void ) __attribute__((naked));
void MemManage_Handler( void )
{
__asm volatile
(
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
" ldr r1, [r0, #24] \n"
" ldr r2, handler2_address_const \n"
" bx r2 \n"
" handler2_address_const: .word hard_fault_handler \n"
);
}/*-----------------------------------------------------------*/

8
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/init_app.ini Normal file
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//Initialization file for the application code
RESET
T
T
T
//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine
eval PC = Reset_Handler;
T

10
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/init_app_simulator.ini Normal file
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//Initialization file for the application code
//RESET
//T
//T
//T
//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine
MAP 0xE0000, 0x118000 Read // map ROM
MAP 0x118000, 0x120000 Read WRITE // map RAM
eval PC = Reset_Handler;
//T

373
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/sections.ld Normal file
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/*
* Memory Spaces Definitions.
*
* Need modifying for a specific board.
* FLASH.ORIGIN: starting address of flash
* FLASH.LENGTH: length of flash
* RAM.ORIGIN: starting address of RAM bank 0
* RAM.LENGTH: length of RAM bank 0
*
* The values below can be addressed in further linker scripts
* using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.
*/
MEMORY
{
/* Due to restrictions in the MPU, the size of memory regions must be a power
of two, and start on a boundary equal to their size. */
ROM (rx) : ORIGIN = 0xE0000, LENGTH = 0x20000
RAM (rw) : ORIGIN = 0x100000, LENGTH = 0x20000
}
/* Variables used by FreeRTOS-MPU. */
_Privileged_Functions_Region_Size = 32K;
_Privileged_Data_Region_Size = 512;
__FLASH_segment_start__ = ORIGIN( ROM );
__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( ROM );
__privileged_functions_start__ = ORIGIN( ROM );
__privileged_functions_end__ = __privileged_functions_start__ + _Privileged_Functions_Region_Size;
__SRAM_segment_start__ = ORIGIN( RAM );
__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM );
__privileged_data_start__ = ORIGIN( RAM );
__privileged_data_end__ = ORIGIN( RAM ) + _Privileged_Data_Region_Size;
/*
* The '__stack' definition is required by crt0, do not remove it.
*/
__stack = ORIGIN(RAM) + LENGTH(RAM);
_estack = __stack;
/*
* Default stack sizes.
* These are used by the startup in order to allocate stacks
* for the different modes.
*/
__Main_Stack_Size = 2048 ;
PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;
__Main_Stack_Limit = __stack - __Main_Stack_Size ;
/*"PROVIDE" allows to easily override these values from an object file or the command line. */
PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;
/*
* There will be a link error if there is not this amount of
* RAM free at the end.
*/
_Minimum_Stack_Size = 1024 ;
/*
* Default heap definitions.
* The heap start immediately after the last statically allocated
* .sbss/.noinit section, and extends up to the main stack limit.
*/
PROVIDE ( _Heap_Begin = _end_noinit ) ;
PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;
/*
* The entry point is informative, for debuggers and simulators,
* since the Cortex-M vector points to it anyway.
*/
ENTRY(_start)
/* Sections Definitions */
SECTIONS
{
/*
* For Cortex-M devices, the beginning of the startup code is stored in
* the .isr_vector section, which goes to ROM
*/
.isr_vector :
{
. = ALIGN(4);
_isr_vector = .;
KEEP(*(.isr_vector))
} >ROM
privileged_functions :
{
. = ALIGN(4);
*(privileged_functions)
/* Non privileged code is after _Privileged_Functions_Region_Size. */
__privileged_functions_actual_end__ = .;
. = _Privileged_Functions_Region_Size;
} > ROM
.text :
{
. = ALIGN(4);
/*
* This section is here for convenience, to store the
* startup code at the beginning of the flash area, hoping that
* this will increase the readability of the listing.
*/
KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */
. = ALIGN(4);
/*
* These are the old initialisation sections, intended to contain
* naked code, with the prologue/epilogue added by crti.o/crtn.o
* when linking with startup files. The standalone startup code
* currently does not run these, better use the init arrays below.
*/
KEEP(*(.init))
KEEP(*(.fini))
. = ALIGN(4);
/*
* The preinit code, i.e. an array of pointers to initialisation
* functions to be performed before constructors.
*/
PROVIDE_HIDDEN (__preinit_array_start = .);
/*
* Used to run the SystemInit() before anything else.
*/
KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))
/*
* Used for other platform inits.
*/
KEEP(*(.preinit_array_platform .preinit_array_platform.*))
/*
* The application inits. If you need to enforce some order in
* execution, create new sections, as before.
*/
KEEP(*(.preinit_array .preinit_array.*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/*
* The init code, i.e. an array of pointers to static constructors.
*/
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/*
* The fini code, i.e. an array of pointers to static destructors.
*/
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
. = ALIGN(4);
*(.text*) /* all remaining code */
*(vtable) /* C++ virtual tables */
} >ROM
.rodata :
{
*(.rodata*) /* read-only data (constants) */
} >ROM
.glue :
{
KEEP(*(.eh_frame*))
/*
* Stub sections generated by the linker, to glue together
* ARM and Thumb code. .glue_7 is used for ARM code calling
* Thumb code, and .glue_7t is used for Thumb code calling
* ARM code. Apparently always generated by the linker, for some
* architectures, so better leave them here.
*/
*(.glue_7)
*(.glue_7t)
} >ROM
/* ARM magic sections */
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;
. = ALIGN(4);
_etext = .;
__etext = .;
/*
* This address is used by the startup code to
* initialise the .data section.
*/
_sidata = _etext;
/* MEMORY_ARRAY */
/*
.ROarraySection :
{
*(.ROarraySection .ROarraySection.*)
} >MEMORY_ARRAY
*/
privileged_data :
{
*(privileged_data)
/* Non kernel data is kept out of the first _Privileged_Data_Region_Size
bytes of SRAM. */
__privileged_data_actual_end__ = .;
. = _Privileged_Data_Region_Size;
} > RAM
/*
* The initialised data section.
* The program executes knowing that the data is in the RAM
* but the loader puts the initial values in the ROM (inidata).
* It is one task of the startup to copy the initial values from
* ROM to RAM.
*/
.data : AT ( _sidata )
{
. = ALIGN(4);
/* This is used by the startup code to initialise the .data section */
_sdata = . ; /* STM specific definition */
__data_start__ = . ;
*(.data_begin .data_begin.*)
*(.data .data.*)
*(.data_end .data_end.*)
. = ALIGN(4);
/* This is used by the startup code to initialise the .data section */
_edata = . ; /* STM specific definition */
__data_end__ = . ;
} >RAM
/*
* The uninitialised data section. NOLOAD is used to avoid
* the "section `.bss' type changed to PROGBITS" warning
*/
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .; /* standard newlib definition */
_sbss = .; /* STM specific definition */
*(.bss_begin .bss_begin.*)
*(.bss .bss.*)
*(COMMON)
*(.bss_end .bss_end.*)
. = ALIGN(4);
__bss_end__ = .; /* standard newlib definition */
_ebss = . ; /* STM specific definition */
} >RAM
.noinit (NOLOAD) :
{
. = ALIGN(4);
_noinit = .;
*(.noinit .noinit.*)
. = ALIGN(4) ;
_end_noinit = .;
} > RAM
/* Mandatory to be word aligned, _sbrk assumes this */
PROVIDE ( end = _end_noinit ); /* was _ebss */
PROVIDE ( _end = _end_noinit );
PROVIDE ( __end = _end_noinit );
PROVIDE ( __end__ = _end_noinit );
PROVIDE ( ROM_DATA_START = __data_start__ );
/*
* Used for validation only, do not allocate anything here!
*
* This is just to check that there is enough RAM left for the Main
* stack. It should generate an error if it's full.
*/
._check_stack :
{
. = ALIGN(4);
. = . + _Minimum_Stack_Size ;
. = ALIGN(4);
} >RAM
/* After that there are only debugging sections. */
/* This can remove the debugging information from the standard libraries */
/*
DISCARD :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
*/
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/*
* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

475
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/GCC_Specific/startup_ARMCM4.S Normal file
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/* File: startup_ARMCM4.S
* Purpose: startup file for Cortex-M4 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V2.0
* Date: 16 August 2013
*
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7e-m
.extern __SRAM_segment_end__
.section .isr_vector,"a",%progbits
.align 4
.globl __isr_vector
.global __Vectors
__Vectors:
__isr_vector:
.long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08
.long NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09
.long NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10
.long NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11
.long NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12
.long NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13
.long NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14
.long NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15
.long NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16
.long NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17
.long NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18
.long NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19
.long NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20
.long NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21
.long NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23
.long NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24
.long NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25
.long NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26
.long 0 // 88h: 18, RSVD
.long 0 // 8Ch: 19, RSVD
.long NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0
.long NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1
.long NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2
.long NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3
.long NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0
.long NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1
.long NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2
.long NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3
.long NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4
.long NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5
.long NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6
.long NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7
.long NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8
.long NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9
.long NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10
.long NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11
.long NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12
.long NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13
.long 0 // D8h: 38, Unused
.long 0 // DCh: 39, Unused
.long NVIC_Handler_UART0 // E0h: 40, UART0
.long NVIC_Handler_UART1 // E4h: 41, UART1
.long NVIC_Handler_EMI0 // E8h: 42, EMI0
.long NVIC_Handler_EMI1 // ECh: 43, EMI0
.long NVIC_Handler_EMI2 // F0h: 44, EMI0
.long NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF
.long NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF
.long NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF
.long NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF
.long NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF
.long NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF
.long NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF
.long NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF
.long NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF
.long NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF
.long NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL
.long NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN
.long NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS
.long NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF
.long NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF
.long NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC
.long NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data
.long NVIC_Handler_P80A // 138h: 62, Port 80h A
.long NVIC_Handler_P80B // 13Ch: 63, Port 80h B
.long 0 // 140h: 64, Reserved
.long NVIC_Handler_PKE_ERR // 144h: 65, PKE Error
.long NVIC_Handler_PKE_END // 148h: 66, PKE End
.long NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen
.long NVIC_Handler_AES // 150h: 68, AES
.long NVIC_Handler_HASH // 154h: 69, HASH
.long NVIC_Handler_PECI // 158h: 70, PECI
.long NVIC_Handler_TACH0 // 15Ch: 71, TACH0
.long NVIC_Handler_TACH1 // 160h: 72, TACH1
.long NVIC_Handler_TACH2 // 164h: 73, TACH2
.long NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail
.long NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall
.long NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail
.long NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall
.long NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL
.long NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT
.long NVIC_Handler_RCID0 // 180h: 80, RCID 0
.long NVIC_Handler_RCID1 // 184h: 81, RCID 1
.long NVIC_Handler_RCID2 // 188h: 82, RCID 2
.long NVIC_Handler_LED0 // 18Ch: 83, LED0
.long NVIC_Handler_LED1 // 190h: 84, LED1
.long NVIC_Handler_LED2 // 194h: 85, LED2
.long NVIC_Handler_LED3 // 198h: 86, LED2
.long NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor
.long NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status
.long NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status
.long NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error
.long NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0
.long NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX
.long NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX
.long NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX
.long NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX
.long NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear
.long NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error
.long NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear
.long NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error
.long NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0
.long NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1
.long NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2
.long NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan
.long NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1
.long NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2
.long NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR
.long NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1
.long NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2
.long NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan
.long NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset
.long NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer
.long NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0
.long NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1
.long NVIC_Handler_WK // 208h: 114, Week Alarm
.long NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week
.long NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec
.long NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec
.long NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin
.long NVIC_Handler_RTC // 21Ch: 119, RTC
.long NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM
.long NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input
.long NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0
.long NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1
.long NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2
.long NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3
.long NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4
.long NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5
.long NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6
.long NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake
.long NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake
.long NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake
.long NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake
.long NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake
.long NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor
.long NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan
.long NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0
.long NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1
.long NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2
.long NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3
.long NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0
.long NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1
.long NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0
.long NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1
.long NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2
.long NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3
.long NVIC_Handler_CAPTMR // 288h: 146, Capture Timer
.long NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event
.long NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event
.long NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event
.long NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event
.long NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event
.long NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event
.long NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event
.long NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event
.text
.thumb
.thumb_func
.align 2
.globl _start
.extern main
.globl Reset_Handler
.type Reset_Handler, %function
_start:
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr sp, =__SRAM_segment_end__
sub sp, sp, #4
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#ifndef __NO_SYSTEM_INIT
/* bl SystemInit */
#endif
bl main
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
/* def_irq_handler SVC_Handler */
def_irq_handler DebugMon_Handler
/* def_irq_handler PendSV_Handler */
/* def_irq_handler SysTick_Handler */
def_irq_handler DEF_IRQHandler
def_irq_handler NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08
def_irq_handler NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09
def_irq_handler NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10
def_irq_handler NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11
def_irq_handler NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12
def_irq_handler NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13
def_irq_handler NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14
def_irq_handler NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15
def_irq_handler NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16
def_irq_handler NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17
def_irq_handler NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18
def_irq_handler NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19
def_irq_handler NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20
def_irq_handler NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21
def_irq_handler NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23
def_irq_handler NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24
def_irq_handler NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25
def_irq_handler NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26
def_irq_handler NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0
def_irq_handler NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1
def_irq_handler NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2
def_irq_handler NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3
def_irq_handler NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0
def_irq_handler NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1
def_irq_handler NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2
def_irq_handler NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3
def_irq_handler NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4
def_irq_handler NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5
def_irq_handler NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6
def_irq_handler NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7
def_irq_handler NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8
def_irq_handler NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9
def_irq_handler NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10
def_irq_handler NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11
def_irq_handler NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12
def_irq_handler NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13
def_irq_handler NVIC_Handler_UART0 // E0h: 40, UART0
def_irq_handler NVIC_Handler_UART1 // E4h: 41, UART1
def_irq_handler NVIC_Handler_EMI0 // E8h: 42, EMI0
def_irq_handler NVIC_Handler_EMI1 // ECh: 43, EMI0
def_irq_handler NVIC_Handler_EMI2 // F0h: 44, EMI0
def_irq_handler NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF
def_irq_handler NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF
def_irq_handler NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF
def_irq_handler NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF
def_irq_handler NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF
def_irq_handler NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF
def_irq_handler NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF
def_irq_handler NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF
def_irq_handler NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF
def_irq_handler NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF
def_irq_handler NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL
def_irq_handler NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN
def_irq_handler NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS
def_irq_handler NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF
def_irq_handler NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF
def_irq_handler NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC
def_irq_handler NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data
def_irq_handler NVIC_Handler_P80A // 138h: 62, Port 80h A
def_irq_handler NVIC_Handler_P80B // 13Ch: 63, Port 80h B
def_irq_handler NVIC_Handler_PKE_ERR // 144h: 65, PKE Error
def_irq_handler NVIC_Handler_PKE_END // 148h: 66, PKE End
def_irq_handler NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen
def_irq_handler NVIC_Handler_AES // 150h: 68, AES
def_irq_handler NVIC_Handler_HASH // 154h: 69, HASH
def_irq_handler NVIC_Handler_PECI // 158h: 70, PECI
def_irq_handler NVIC_Handler_TACH0 // 15Ch: 71, TACH0
def_irq_handler NVIC_Handler_TACH1 // 160h: 72, TACH1
def_irq_handler NVIC_Handler_TACH2 // 164h: 73, TACH2
def_irq_handler NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail
def_irq_handler NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall
def_irq_handler NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail
def_irq_handler NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall
def_irq_handler NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL
def_irq_handler NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT
def_irq_handler NVIC_Handler_RCID0 // 180h: 80, RCID 0
def_irq_handler NVIC_Handler_RCID1 // 184h: 81, RCID 1
def_irq_handler NVIC_Handler_RCID2 // 188h: 82, RCID 2
def_irq_handler NVIC_Handler_LED0 // 18Ch: 83, LED0
def_irq_handler NVIC_Handler_LED1 // 190h: 84, LED1
def_irq_handler NVIC_Handler_LED2 // 194h: 85, LED2
def_irq_handler NVIC_Handler_LED3 // 198h: 86, LED2
def_irq_handler NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor
def_irq_handler NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status
def_irq_handler NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status
def_irq_handler NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error
def_irq_handler NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0
def_irq_handler NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX
def_irq_handler NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX
def_irq_handler NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX
def_irq_handler NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX
def_irq_handler NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear
def_irq_handler NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error
def_irq_handler NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear
def_irq_handler NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error
def_irq_handler NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0
def_irq_handler NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1
def_irq_handler NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2
def_irq_handler NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan
def_irq_handler NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1
def_irq_handler NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2
def_irq_handler NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR
def_irq_handler NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1
def_irq_handler NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2
def_irq_handler NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan
def_irq_handler NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset
def_irq_handler NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer
def_irq_handler NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0
def_irq_handler NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1
def_irq_handler NVIC_Handler_WK // 208h: 114, Week Alarm
def_irq_handler NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week
def_irq_handler NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec
def_irq_handler NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec
def_irq_handler NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin
def_irq_handler NVIC_Handler_RTC // 21Ch: 119, RTC
def_irq_handler NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM
def_irq_handler NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input
def_irq_handler NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0
def_irq_handler NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1
def_irq_handler NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2
def_irq_handler NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3
def_irq_handler NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4
def_irq_handler NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5
def_irq_handler NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6
def_irq_handler NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake
def_irq_handler NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake
def_irq_handler NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake
def_irq_handler NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake
def_irq_handler NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake
def_irq_handler NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor
def_irq_handler NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan
def_irq_handler NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0
def_irq_handler NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1
def_irq_handler NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2
def_irq_handler NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3
def_irq_handler NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0
def_irq_handler NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1
def_irq_handler NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0
def_irq_handler NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1
def_irq_handler NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2
def_irq_handler NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3
def_irq_handler NVIC_Handler_CAPTMR // 288h: 146, Capture Timer
def_irq_handler NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event
def_irq_handler NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event
def_irq_handler NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event
def_irq_handler NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event
def_irq_handler NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event
def_irq_handler NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event
def_irq_handler NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event
def_irq_handler NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event
.end

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/****************************************************************************
* © 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*/
/** @defgroup pwm pwm_c_wrapper
* @{
*/
/** @file pwm_c_wrapper.cpp
\brief the pwm component C wrapper
This program is designed to allow the other C programs to be able to use this component
There are entry points for all C wrapper API implementation
<b>Platform:</b> This is ARC-based component
<b>Toolset:</b> Metaware IDE(8.5.1)
<b>Reference:</b> smsc_reusable_fw_requirement.doc */
/*******************************************************************************
* SMSC version control information (Perforce):
*
* FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/GCC_Specific/system.c $
* REVISION: $Revision: #1 $
* DATETIME: $DateTime: 2016/09/22 08:03:49 $
* AUTHOR: $Author: pramans $
*
* Revision history (latest first):
* #3 2011/05/09 martin_y update to Metaware IDE(8.5.1)
* #2 2011/03/25 martin_y support FPGA build 058 apps
* #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200
***********************************************************************************
*/
/* Imported Header File */
//#include "common.h"
//#include "build.h"
#include <stdint.h>
#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120
#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))
#define CPU_CLOCK_DIVIDER 1
/******************************************************************************/
/** system_set_ec_clock
* Set CPU speed
* @param void
* @return void
*******************************************************************************/
void system_set_ec_clock(void)
{
/* Set ARC CPU Clock Divider to determine the CPU speed */
/* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */
MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;
} /* End system_set_ec_clock() */

35
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/JLinkSettings.ini Normal file
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@ -0,0 +1,35 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Unspecified"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

29
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/RTOSDemo.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0xE0000 0x40000 ; load region size_region
{
ER_PRIVILEGED_FUNCTIONS 0xE0000 0x8000 {
*.o (RESET, +First)
startup_MPS_CM4.o
*(InRoot$$Sections)
*( privileged_functions )
}
ER_UNPRIVILEGED_FUNCTIONS 0xE8000 0x18000 {
.ANY (+RO)
}
RW_PRIVILEGED_DATA 0x100000 0x200 {
*( privileged_data )
}
RW_UNPRIVILEGED_DATA 0x100200 0x1FE00 {
.ANY (+RW +ZI)
}
}

491
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
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<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
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<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>48000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
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<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
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<uTrg>1</uTrg>
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<tRSysVw>1</tRSysVw>
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<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>init_app.ini</tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
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<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=1199,245,1664,545,0)</Name>
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<SetRegEntry>
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<Name>-T0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-UV1115SAE -O3047 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8028 -TDT0 -TDC1F -TIE1 -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>pxCurrentTCB</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>2</SubType>
<ItemText>0xe000e284</ItemText>
<AccSizeX>4</AccSizeX>
</Mm>
</MemoryWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>1</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
</TargetOption>
</Target>
<Group>
<GroupName>System</GroupName>
<tvExp>1</tvExp>
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<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
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<FileNumber>1</FileNumber>
<FileType>2</FileType>
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<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\startup_MPS_CM4.S</PathWithFileName>
<FilenameWithoutPath>startup_MPS_CM4.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>main_and_config</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\FreeRTOSConfig.h</PathWithFileName>
<FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
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<bDave2>0</bDave2>
<PathWithFileName>.\RegTest.c</PathWithFileName>
<FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>FreeRTOS_Source</GroupName>
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</File>
</Group>
</ProjectOpt>

536
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>RTOSDemo</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.4.3.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>RTOSDemo</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<nStopU1X>0</nStopU1X>
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</BeforeCompile>
<BeforeMake>
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<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
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<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<nStopA1X>0</nStopA1X>
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</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
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<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>init_app.ini</InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>1</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0xe0000</StartAddress>
<Size>0x38000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x118000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4_MPU;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full;..\peripheral_library\interrupt</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>RTOSDemo.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>System</GroupName>
<Files>
<File>
<FileName>startup_MPS_CM4.S</FileName>
<FileType>2</FileType>
<FilePath>.\startup_MPS_CM4.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>main_and_config</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\main.c</FilePath>
</File>
<File>
<FileName>FreeRTOSConfig.h</FileName>
<FileType>5</FileType>
<FilePath>..\FreeRTOSConfig.h</FilePath>
</File>
<File>
<FileName>RegTest.c</FileName>
<FileType>1</FileType>
<FilePath>.\RegTest.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FreeRTOS_Source</GroupName>
<Files>
<File>
<FileName>event_groups.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\event_groups.c</FilePath>
</File>
<File>
<FileName>list.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\list.c</FilePath>
</File>
<File>
<FileName>queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\queue.c</FilePath>
</File>
<File>
<FileName>tasks.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\tasks.c</FilePath>
</File>
<File>
<FileName>timers.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\timers.c</FilePath>
</File>
<File>
<FileName>heap_4.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\portable\MemMang\heap_4.c</FilePath>
</File>
<File>
<FileName>port.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\portable\RVDS\ARM_CM4_MPU\port.c</FilePath>
</File>
<File>
<FileName>mpu_wrappers.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\Source\portable\Common\mpu_wrappers.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>peripheral_library</GroupName>
<Files>
<File>
<FileName>interrupt_api.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\interrupt\interrupt_api.c</FilePath>
</File>
<File>
<FileName>interrupt_ecia_perphl.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\interrupt\interrupt_ecia_perphl.c</FilePath>
</File>
<File>
<FileName>interrupt_nvic_perphl.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\interrupt\interrupt_nvic_perphl.c</FilePath>
</File>
<File>
<FileName>btimer_api.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\basic_timer\btimer_api.c</FilePath>
</File>
<File>
<FileName>btimer_perphl.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\basic_timer\btimer_perphl.c</FilePath>
</File>
<File>
<FileName>pcr_api.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\pcr\pcr_api.c</FilePath>
</File>
<File>
<FileName>pcr_perphl.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\pcr\pcr_perphl.c</FilePath>
</File>
<File>
<FileName>system_internal.c</FileName>
<FileType>1</FileType>
<FilePath>..\peripheral_library\system_internal.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>

703
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/RegTest.c Normal file
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@ -0,0 +1,703 @@
/*
FreeRTOS V9.0.0 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/*
* "Reg test" tasks - These fill the registers with known values, then check
* that each register maintains its expected value for the lifetime of the
* task. Each task uses a different set of values. The reg test tasks execute
* with a very low priority, so get preempted very frequently. A register
* containing an unexpected value is indicative of an error in the context
* switching mechanism.
*/
void vRegTest1Implementation( void *pvParameters );
void vRegTest2Implementation( void *pvParameters );
void vRegTest3Implementation( void );
void vRegTest4Implementation( void );
/*
* Used as an easy way of deleting a task from inline assembly.
*/
extern void vMainDeleteMe( void ) __attribute__((noinline));
/*
* Used by the first two reg test tasks and a software timer callback function
* to send messages to the check task. The message just lets the check task
* know that the tasks and timer are still functioning correctly. If a reg test
* task detects an error it will delete itself, and in so doing prevent itself
* from sending any more 'I'm Alive' messages to the check task.
*/
extern void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber );
/* The queue used to send a message to the check task. */
extern QueueHandle_t xGlobalScopeCheckQueue;
/*-----------------------------------------------------------*/
void vRegTest1Implementation( void *pvParameters )
{
/* This task is created in privileged mode so can access the file scope
queue variable. Take a stack copy of this before the task is set into user
mode. Once this task is in user mode the file scope queue variable will no
longer be accessible but the stack copy will. */
QueueHandle_t xQueue = xGlobalScopeCheckQueue;
const TickType_t xDelayTime = pdMS_TO_TICKS( 100UL );
/* Now the queue handle has been obtained the task can switch to user
mode. This is just one method of passing a handle into a protected
task, the other reg test task uses the task parameter instead. */
portSWITCH_TO_USER_MODE();
/* First check that the parameter value is as expected. */
if( pvParameters != ( void * ) configREG_TEST_TASK_1_PARAMETER )
{
/* Error detected. Delete the task so it stops communicating with
the check task. */
vMainDeleteMe();
}
for( ;; )
{
#if defined ( __GNUC__ )
{
/* This task tests the kernel context switch mechanism by reading and
writing directly to registers - which requires the test to be written
in assembly code. */
__asm volatile
(
" MOV R4, #104 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */
" MOV R5, #105 \n"
" MOV R6, #106 \n"
" MOV R8, #108 \n"
" MOV R9, #109 \n"
" MOV R10, #110 \n"
" MOV R11, #111 \n"
"reg1loop: \n"
" MOV R0, #100 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */
" MOV R1, #101 \n"
" MOV R2, #102 \n"
" MOV R3, #103 \n"
" MOV R12, #112 \n"
" SVC #1 \n" /* Yield just to increase test coverage. */
" CMP R0, #100 \n" /* Check all the registers still contain their expected values. */
" BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task. */
" CMP R1, #101 \n"
" BNE vMainDeleteMe \n"
" CMP R2, #102 \n"
" BNE vMainDeleteMe \n"
" CMP R3, #103 \n"
" BNE vMainDeleteMe \n"
" CMP R4, #104 \n"
" BNE vMainDeleteMe \n"
" CMP R5, #105 \n"
" BNE vMainDeleteMe \n"
" CMP R6, #106 \n"
" BNE vMainDeleteMe \n"
" CMP R8, #108 \n"
" BNE vMainDeleteMe \n"
" CMP R9, #109 \n"
" BNE vMainDeleteMe \n"
" CMP R10, #110 \n"
" BNE vMainDeleteMe \n"
" CMP R11, #111 \n"
" BNE vMainDeleteMe \n"
" CMP R12, #112 \n"
" BNE vMainDeleteMe \n"
:::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"
);
}
#endif /* __GNUC__ */
/* Send configREG_TEST_1_STILL_EXECUTING to the check task to indicate that this
task is still functioning. */
vMainSendImAlive( xQueue, configREG_TEST_1_STILL_EXECUTING );
vTaskDelay( xDelayTime );
#if defined ( __GNUC__ )
{
/* Go back to check all the register values again. */
__asm volatile( " B reg1loop " );
}
#endif /* __GNUC__ */
}
}
/*-----------------------------------------------------------*/
void vRegTest2Implementation( void *pvParameters )
{
/* The queue handle is passed in as the task parameter. This is one method of
passing data into a protected task, the other reg test task uses a different
method. */
QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
const TickType_t xDelayTime = pdMS_TO_TICKS( 100UL );
for( ;; )
{
#if defined ( __GNUC__ )
{
/* This task tests the kernel context switch mechanism by reading and
writing directly to registers - which requires the test to be written
in assembly code. */
__asm volatile
(
" MOV R4, #4 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */
" MOV R5, #5 \n"
" MOV R6, #6 \n"
" MOV R8, #8 \n" /* Frame pointer is omitted as it must not be changed. */
" MOV R9, #9 \n"
" MOV R10, 10 \n"
" MOV R11, #11 \n"
"reg2loop: \n"
" MOV R0, #13 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */
" MOV R1, #1 \n"
" MOV R2, #2 \n"
" MOV R3, #3 \n"
" MOV R12, #12 \n"
" CMP R0, #13 \n" /* Check all the registers still contain their expected values. */
" BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task */
" CMP R1, #1 \n"
" BNE vMainDeleteMe \n"
" CMP R2, #2 \n"
" BNE vMainDeleteMe \n"
" CMP R3, #3 \n"
" BNE vMainDeleteMe \n"
" CMP R4, #4 \n"
" BNE vMainDeleteMe \n"
" CMP R5, #5 \n"
" BNE vMainDeleteMe \n"
" CMP R6, #6 \n"
" BNE vMainDeleteMe \n"
" CMP R8, #8 \n"
" BNE vMainDeleteMe \n"
" CMP R9, #9 \n"
" BNE vMainDeleteMe \n"
" CMP R10, #10 \n"
" BNE vMainDeleteMe \n"
" CMP R11, #11 \n"
" BNE vMainDeleteMe \n"
" CMP R12, #12 \n"
" BNE vMainDeleteMe \n"
:::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"
);
}
#endif /* __GNUC__ */
/* Send configREG_TEST_2_STILL_EXECUTING to the check task to indicate
that this task is still functioning. */
vMainSendImAlive( xQueue, configREG_TEST_2_STILL_EXECUTING );
vTaskDelay( xDelayTime );
#if defined ( __GNUC__ )
{
/* Go back to check all the register values again. */
__asm volatile( " B reg2loop " );
}
#endif /* __GNUC__ */
}
}
/*-----------------------------------------------------------*/
__asm void vRegTest3Implementation( void )
{
extern pulRegTest3LoopCounter
PRESERVE8
/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
/* Fill the VFP registers with known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg1_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d1
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d2
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d3
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d4
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d5
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d6
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d7
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d8
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d9
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
vmov r0, r1, d10
cmp r0, #108
bne reg1_error_loopf
cmp r1, #109
bne reg1_error_loopf
vmov r0, r1, d11
cmp r0, #110
bne reg1_error_loopf
cmp r1, #111
bne reg1_error_loopf
vmov r0, r1, d12
cmp r0, #100
bne reg1_error_loopf
cmp r1, #101
bne reg1_error_loopf
vmov r0, r1, d13
cmp r0, #102
bne reg1_error_loopf
cmp r1, #103
bne reg1_error_loopf
vmov r0, r1, d14
cmp r0, #104
bne reg1_error_loopf
cmp r1, #105
bne reg1_error_loopf
vmov r0, r1, d15
cmp r0, #106
bne reg1_error_loopf
cmp r1, #107
bne reg1_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg1_loopf_pass
reg1_error_loopf
/* If this line is hit then a VFP register value was found to be incorrect. */
b reg1_error_loopf
reg1_loopf_pass
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, =pulRegTest3LoopCounter
ldr r0, [r0]
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Start again. */
b reg1_loop
reg1_error_loop
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
nop
nop
}
/*-----------------------------------------------------------*/
__asm void vRegTest4Implementation( void )
{
extern pulRegTest4LoopCounter;
PRESERVE8
/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
/* Set all the VFP to known values. */
vmov d0, r0, r1
vmov d1, r2, r3
vmov d2, r4, r5
vmov d3, r6, r7
vmov d4, r8, r9
vmov d5, r10, r11
vmov d6, r0, r1
vmov d7, r2, r3
vmov d8, r4, r5
vmov d9, r6, r7
vmov d10, r8, r9
vmov d11, r10, r11
vmov d12, r0, r1
vmov d13, r2, r3
vmov d14, r4, r5
vmov d15, r6, r7
reg2_loop
/* Check all the VFP registers still contain the values set above.
First save registers that are clobbered by the test. */
push { r0-r1 }
vmov r0, r1, d0
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d1
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d2
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d3
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d4
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d5
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d6
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d7
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d8
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d9
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
vmov r0, r1, d10
cmp r0, #8
bne reg2_error_loopf
cmp r1, #9
bne reg2_error_loopf
vmov r0, r1, d11
cmp r0, #10
bne reg2_error_loopf
cmp r1, #11
bne reg2_error_loopf
vmov r0, r1, d12
cmp r0, #-1
bne reg2_error_loopf
cmp r1, #1
bne reg2_error_loopf
vmov r0, r1, d13
cmp r0, #2
bne reg2_error_loopf
cmp r1, #3
bne reg2_error_loopf
vmov r0, r1, d14
cmp r0, #4
bne reg2_error_loopf
cmp r1, #5
bne reg2_error_loopf
vmov r0, r1, d15
cmp r0, #6
bne reg2_error_loopf
cmp r1, #7
bne reg2_error_loopf
/* Restore the registers that were clobbered by the test. */
pop {r0-r1}
/* VFP register test passed. Jump to the core register test. */
b reg2_loopf_pass
reg2_error_loopf
/* If this line is hit then a VFP register value was found to be
incorrect. */
b reg2_error_loopf
reg2_loopf_pass
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
/* Increment the loop counter so the check task knows this task is
still running. */
push { r0-r1 }
ldr r0, =pulRegTest4LoopCounter
ldr r0, [r0]
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
/* Yield to increase test coverage. */
SVC #1
/* Start again. */
b reg2_loop
reg2_error_loop
/* If this line is hit then there was an error in a core register value.
This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
nop
}
/*-----------------------------------------------------------*/
/* Fault handlers are here for convenience as they use compiler specific syntax
and this file is specific to the Keil compiler. */
void hard_fault_handler( uint32_t * hardfault_args )
{
volatile uint32_t stacked_r0;
volatile uint32_t stacked_r1;
volatile uint32_t stacked_r2;
volatile uint32_t stacked_r3;
volatile uint32_t stacked_r12;
volatile uint32_t stacked_lr;
volatile uint32_t stacked_pc;
volatile uint32_t stacked_psr;
stacked_r0 = ((uint32_t) hardfault_args[ 0 ]);
stacked_r1 = ((uint32_t) hardfault_args[ 1 ]);
stacked_r2 = ((uint32_t) hardfault_args[ 2 ]);
stacked_r3 = ((uint32_t) hardfault_args[ 3 ]);
stacked_r12 = ((uint32_t) hardfault_args[ 4 ]);
stacked_lr = ((uint32_t) hardfault_args[ 5 ]);
stacked_pc = ((uint32_t) hardfault_args[ 6 ]);
stacked_psr = ((uint32_t) hardfault_args[ 7 ]);
/* Inspect stacked_pc to locate the offending instruction. */
for( ;; );
}
/*-----------------------------------------------------------*/
void HardFault_Handler( void );
__asm void HardFault_Handler( void )
{
extern hard_fault_handler
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldr r2, hard_fault_handler
bx r2
}
/*-----------------------------------------------------------*/
void MemManage_Handler( void );
__asm void MemManage_Handler( void )
{
extern hard_fault_handler
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldr r2, hard_fault_handler
bx r2
}
/*-----------------------------------------------------------*/

7
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/init_app.ini Normal file
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@ -0,0 +1,7 @@
//Initialization file for the application code
RESET
T
T
T
eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine
T

643
FreeRTOS/Demo/CORTEX_MPU_MEC17xx_Keil_GCC/Keil_Specific/startup_MPS_CM4.S Normal file
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@ -0,0 +1,643 @@
;/*****************************************************************************
; * @file: startup_MPS_CM4.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * for the ARM 'Microcontroller Prototyping System'
; * @version: V1.00
; * @date: 1. Jun. 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2008-2010 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD NVIC_Handler_GIRQ08 ; 40h: 0, GIRQ08
DCD NVIC_Handler_GIRQ09 ; 44h: 1, GIRQ09
DCD NVIC_Handler_GIRQ10 ; 48h: 2, GIRQ10
DCD NVIC_Handler_GIRQ11 ; 4Ch: 3, GIRQ11
DCD NVIC_Handler_GIRQ12 ; 50h: 4, GIRQ12
DCD NVIC_Handler_GIRQ13 ; 54h: 5, GIRQ13
DCD NVIC_Handler_GIRQ14 ; 58h: 6, GIRQ14
DCD NVIC_Handler_GIRQ15 ; 5Ch: 7, GIRQ15
DCD NVIC_Handler_GIRQ16 ; 60h: 8, GIRQ16
DCD NVIC_Handler_GIRQ17 ; 64h: 9, GIRQ17
DCD NVIC_Handler_GIRQ18 ; 68h: 10, GIRQ18
DCD NVIC_Handler_GIRQ19 ; 6Ch: 11, GIRQ19
DCD NVIC_Handler_GIRQ20 ; 70h: 12, GIRQ20
DCD NVIC_Handler_GIRQ21 ; 74h: 13, GIRQ21
DCD NVIC_Handler_GIRQ23 ; 78h: 14, GIRQ23
DCD NVIC_Handler_GIRQ24 ; 7Ch: 15, GIRQ24
DCD NVIC_Handler_GIRQ25 ; 80h: 16, GIRQ25
DCD NVIC_Handler_GIRQ26 ; 84h: 17, GIRQ26
DCD 0 ; 88h: 18, RSVD
DCD 0 ; 8Ch: 19, RSVD
DCD NVIC_Handler_I2C0 ; 90h: 20, I2C/SMBus 0
DCD NVIC_Handler_I2C1 ; 94h: 21, I2C/SMBus 1
DCD NVIC_Handler_I2C2 ; 98h: 22, I2C/SMBus 2
DCD NVIC_Handler_I2C3 ; 9Ch: 23, I2C/SMBus 3
DCD NVIC_Handler_DMA0 ; A0h: 24, DMA Channel 0
DCD NVIC_Handler_DMA1 ; A4h: 25, DMA Channel 1
DCD NVIC_Handler_DMA2 ; A8h: 26, DMA Channel 2
DCD NVIC_Handler_DMA3 ; ACh: 27, DMA Channel 3
DCD NVIC_Handler_DMA4 ; B0h: 28, DMA Channel 4
DCD NVIC_Handler_DMA5 ; B4h: 29, DMA Channel 5
DCD NVIC_Handler_DMA6 ; B8h: 30, DMA Channel 6
DCD NVIC_Handler_DMA7 ; BCh: 31, DMA Channel 7
DCD NVIC_Handler_DMA8 ; C0h: 32, DMA Channel 8
DCD NVIC_Handler_DMA9 ; C4h: 33, DMA Channel 9
DCD NVIC_Handler_DMA10 ; C8h: 34, DMA Channel 10
DCD NVIC_Handler_DMA11 ; CCh: 35, DMA Channel 11
DCD NVIC_Handler_DMA12 ; D0h: 36, DMA Channel 12
DCD NVIC_Handler_DMA13 ; D4h: 37, DMA Channel 13
DCD 0 ; D8h: 38, Unused
DCD 0 ; DCh: 39, Unused
DCD NVIC_Handler_UART0 ; E0h: 40, UART0
DCD NVIC_Handler_UART1 ; E4h: 41, UART1
DCD NVIC_Handler_EMI0 ; E8h: 42, EMI0
DCD NVIC_Handler_EMI1 ; ECh: 43, EMI0
DCD NVIC_Handler_EMI2 ; F0h: 44, EMI0
DCD NVIC_Handler_ACPI_EC0_IBF ; F4h: 45, ACPI_EC0_IBF
DCD NVIC_Handler_ACPI_EC0_OBF ; F8h: 46, ACPI_EC0_OBF
DCD NVIC_Handler_ACPI_EC1_IBF ; FCh: 47, ACPI_EC1_IBF
DCD NVIC_Handler_ACPI_EC1_OBF ; 100h: 48, ACPI_EC1_OBF
DCD NVIC_Handler_ACPI_EC2_IBF ; 104h: 49, ACPI_EC0_IBF
DCD NVIC_Handler_ACPI_EC2_OBF ; 108h: 50, ACPI_EC0_OBF
DCD NVIC_Handler_ACPI_EC3_IBF ; 10Ch: 51, ACPI_EC1_IBF
DCD NVIC_Handler_ACPI_EC3_OBF ; 110h: 52, ACPI_EC1_OBF
DCD NVIC_Handler_ACPI_EC4_IBF ; 114h: 53, ACPI_EC0_IBF
DCD NVIC_Handler_ACPI_EC4_OBF ; 118h: 54, ACPI_EC0_OBF
DCD NVIC_Handler_PM1_CTL ; 11Ch: 55, ACPI_PM1_CTL
DCD NVIC_Handler_PM1_EN ; 120h: 56, ACPI_PM1_EN
DCD NVIC_Handler_PM1_STS ; 124h: 57, ACPI_PM1_STS
DCD NVIC_Handler_MIF8042_OBF ; 128h: 58, MIF8042_OBF
DCD NVIC_Handler_MIF8042_IBF ; 12Ch: 59, MIF8042_IBF
DCD NVIC_Handler_MB_H2EC ; 130h: 60, Mailbox Host to EC
DCD NVIC_Handler_MB_DATA ; 134h: 61, Mailbox Host Data
DCD NVIC_Handler_P80A ; 138h: 62, Port 80h A
DCD NVIC_Handler_P80B ; 13Ch: 63, Port 80h B
DCD 0 ; 140h: 64, Reserved
DCD NVIC_Handler_PKE_ERR ; 144h: 65, PKE Error
DCD NVIC_Handler_PKE_END ; 148h: 66, PKE End
DCD NVIC_Handler_TRNG ; 14Ch: 67, Random Num Gen
DCD NVIC_Handler_AES ; 150h: 68, AES
DCD NVIC_Handler_HASH ; 154h: 69, HASH
DCD NVIC_Handler_PECI ; 158h: 70, PECI
DCD NVIC_Handler_TACH0 ; 15Ch: 71, TACH0
DCD NVIC_Handler_TACH1 ; 160h: 72, TACH1
DCD NVIC_Handler_TACH2 ; 164h: 73, TACH2
DCD NVIC_Handler_R2P0_FAIL ; 168h: 74, RPM2PWM 0 Fan Fail
DCD NVIC_Handler_R2P0_STALL ; 16Ch: 75, RPM2PWM 0 Fan Stall
DCD NVIC_Handler_R2P1_FAIL ; 170h: 76, RPM2PWM 1 Fan Fail
DCD NVIC_Handler_R2P1_STALL ; 174h: 77, RPM2PWM 1 Fan Stall
DCD NVIC_Handler_ADC_SNGL ; 178h: 78, ADC_SNGL
DCD NVIC_Handler_ADC_RPT ; 17Ch: 79, ADC_RPT
DCD NVIC_Handler_RCID0 ; 180h: 80, RCID 0
DCD NVIC_Handler_RCID1 ; 184h: 81, RCID 1
DCD NVIC_Handler_RCID2 ; 188h: 82, RCID 2
DCD NVIC_Handler_LED0 ; 18Ch: 83, LED0
DCD NVIC_Handler_LED1 ; 190h: 84, LED1
DCD NVIC_Handler_LED2 ; 194h: 85, LED2
DCD NVIC_Handler_LED3 ; 198h: 86, LED2
DCD NVIC_Handler_PHOT ; 19Ch: 87, ProcHot Monitor
DCD NVIC_Handler_PWRGD0 ; 1A0h: 88, PowerGuard 0 Status
DCD NVIC_Handler_PWRGD1 ; 1A4h: 89, PowerGuard 1 Status
DCD NVIC_Handler_LPCBERR ; 1A8h: 90, LPC Bus Error
DCD NVIC_Handler_QMSPI0 ; 1ACh: 91, QMSPI 0
DCD NVIC_Handler_GPSPI0_TX ; 1B0h: 92, GP-SPI0 TX
DCD NVIC_Handler_GPSPI0_RX ; 1B4h: 93, GP-SPI0 RX
DCD NVIC_Handler_GPSPI1_TX ; 1B8h: 94, GP-SPI1 TX
DCD NVIC_Handler_GPSPI1_RX ; 1BCh: 95, GP-SPI1 RX
DCD NVIC_Handler_BC0_BUSY ; 1C0h: 96, BC-Link0 Busy-Clear
DCD NVIC_Handler_BC0_ERR ; 1C4h: 97, BC-Link0 Error
DCD NVIC_Handler_BC1_BUSY ; 1C8h: 98, BC-Link1 Busy-Clear
DCD NVIC_Handler_BC1_ERR ; 1CCh: 99, BC-Link1 Error
DCD NVIC_Handler_PS2_0 ; 1D0h: 100, PS2_0
DCD NVIC_Handler_PS2_1 ; 1D4h: 101, PS2_1
DCD NVIC_Handler_PS2_2 ; 1D8h: 102, PS2_2
DCD NVIC_Handler_ESPI_PC ; 1DCh: 103, eSPI Periph Chan
DCD NVIC_Handler_ESPI_BM1 ; 1E0h: 104, eSPI Bus Master 1
DCD NVIC_Handler_ESPI_BM2 ; 1E4h: 105, eSPI Bus Master 2
DCD NVIC_Handler_ESPI_LTR ; 1E8h: 106, eSPI LTR
DCD NVIC_Handler_ESPI_OOB_UP ; 1ECh: 107, eSPI Bus Master 1
DCD NVIC_Handler_ESPI_OOB_DN ; 1F0h: 108, eSPI Bus Master 2
DCD NVIC_Handler_ESPI_FLASH ; 1F4h: 109, eSPI Flash Chan
DCD NVIC_Handler_ESPI_RESET ; 1F8h: 110, eSPI Reset
DCD NVIC_Handler_RTMR ; 1FCh: 111, RTOS Timer
DCD NVIC_Handler_HTMR0 ; 200h: 112, Hibernation Timer 0
DCD NVIC_Handler_HTMR1 ; 204h: 113, Hibernation Timer 1
DCD NVIC_Handler_WK ; 208h: 114, Week Alarm
DCD NVIC_Handler_WKSUB ; 20Ch: 115, Week Alarm, sub week
DCD NVIC_Handler_WKSEC ; 210h: 116, Week Alarm, one sec
DCD NVIC_Handler_WKSUBSEC ; 214h: 117, Week Alarm, sub sec
DCD NVIC_Handler_SYSPWR ; 218h: 118, System Power Present pin
DCD NVIC_Handler_RTC ; 21Ch: 119, RTC
DCD NVIC_Handler_RTC_ALARM ; 220h: 120, RTC_ALARM
DCD NVIC_Handler_VCI_OVRD_IN ; 224h: 121, VCI Override Input
DCD NVIC_Handler_VCI_IN0 ; 228h: 122, VCI Input 0
DCD NVIC_Handler_VCI_IN1 ; 22Ch: 123, VCI Input 1
DCD NVIC_Handler_VCI_IN2 ; 230h: 124, VCI Input 2
DCD NVIC_Handler_VCI_IN3 ; 234h: 125, VCI Input 3
DCD NVIC_Handler_VCI_IN4 ; 238h: 126, VCI Input 4
DCD NVIC_Handler_VCI_IN5 ; 23Ch: 127, VCI Input 5
DCD NVIC_Handler_VCI_IN6 ; 240h: 128, VCI Input 6
DCD NVIC_Handler_PS20A_WAKE ; 244h: 129, PS2 Port 0A Wake
DCD NVIC_Handler_PS20B_WAKE ; 248h: 130, PS2 Port 0B Wake
DCD NVIC_Handler_PS21A_WAKE ; 24Ch: 131, PS2 Port 1A Wake
DCD NVIC_Handler_PS21B_WAKE ; 250h: 132, PS2 Port 1B Wake
DCD NVIC_Handler_PS21_WAKE ; 254h: 133, PS2 Port 1 Wake
DCD NVIC_Handler_ENVMON ; 258h: 134, Thernal Monitor
DCD NVIC_Handler_KEYSCAN ; 25Ch: 135, Key Scan
DCD NVIC_Handler_BTMR16_0 ; 260h: 136, 16-bit Basic Timer 0
DCD NVIC_Handler_BTMR16_1 ; 264h: 137, 16-bit Basic Timer 1
DCD NVIC_Handler_BTMR16_2 ; 268h: 138, 16-bit Basic Timer 2
DCD NVIC_Handler_BTMR16_3 ; 26Ch: 139, 16-bit Basic Timer 3
DCD NVIC_Handler_BTMR32_0 ; 270h: 140, 32-bit Basic Timer 0
DCD NVIC_Handler_BTMR32_1 ; 274h: 141, 32-bit Basic Timer 1
DCD NVIC_Handler_EVTMR0 ; 278h: 142, Event Counter/Timer 0
DCD NVIC_Handler_EVTMR1 ; 27Ch: 143, Event Counter/Timer 1
DCD NVIC_Handler_EVTMR2 ; 280h: 144, Event Counter/Timer 2
DCD NVIC_Handler_EVTMR3 ; 284h: 145, Event Counter/Timer 3
DCD NVIC_Handler_CAPTMR ; 288h: 146, Capture Timer
DCD NVIC_Handler_CAP0 ; 28Ch: 147, Capture 0 Event
DCD NVIC_Handler_CAP1 ; 290h: 148, Capture 1 Event
DCD NVIC_Handler_CAP2 ; 294h: 149, Capture 2 Event
DCD NVIC_Handler_CAP3 ; 298h: 150, Capture 3 Event
DCD NVIC_Handler_CAP4 ; 29Ch: 151, Capture 4 Event
DCD NVIC_Handler_CAP5 ; 2A0h: 152, Capture 5 Event
DCD NVIC_Handler_CMP0 ; 2A4h: 153, Compare 0 Event
DCD NVIC_Handler_CMP1 ; 2A8h: 154, Compare 1 Event
; Project build information
AREA |.text|, CODE, READONLY
; AREA RESET, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
; Remap vector table
LDR R0, =__Vectors
LDR R1, =0xE000ED08
STR R0, [r1]
NOP
IF {CPU} = "Cortex-M4.fp"
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1,[R0]
ORR R1,R1,#(0xF << 20)
STR R1,[R0]
ENDIF
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NVIC_Handler_GIRQ08 [WEAK]
EXPORT NVIC_Handler_GIRQ09 [WEAK]
EXPORT NVIC_Handler_GIRQ10 [WEAK]
EXPORT NVIC_Handler_GIRQ11 [WEAK]
EXPORT NVIC_Handler_GIRQ12 [WEAK]
EXPORT NVIC_Handler_GIRQ13 [WEAK]
EXPORT NVIC_Handler_GIRQ14 [WEAK]
EXPORT NVIC_Handler_GIRQ15 [WEAK]
EXPORT NVIC_Handler_GIRQ16 [WEAK]
EXPORT NVIC_Handler_GIRQ17 [WEAK]
EXPORT NVIC_Handler_GIRQ18 [WEAK]
EXPORT NVIC_Handler_GIRQ19 [WEAK]
EXPORT NVIC_Handler_GIRQ20 [WEAK]
EXPORT NVIC_Handler_GIRQ21 [WEAK]
EXPORT NVIC_Handler_GIRQ23 [WEAK]
EXPORT NVIC_Handler_GIRQ24 [WEAK]
EXPORT NVIC_Handler_GIRQ25 [WEAK]
EXPORT NVIC_Handler_GIRQ26 [WEAK]
EXPORT NVIC_Handler_I2C0 [WEAK]
EXPORT NVIC_Handler_I2C1 [WEAK]
EXPORT NVIC_Handler_I2C2 [WEAK]
EXPORT NVIC_Handler_I2C3 [WEAK]
EXPORT NVIC_Handler_DMA0 [WEAK]
EXPORT NVIC_Handler_DMA1 [WEAK]
EXPORT NVIC_Handler_DMA2 [WEAK]
EXPORT NVIC_Handler_DMA3 [WEAK]
EXPORT NVIC_Handler_DMA4 [WEAK]
EXPORT NVIC_Handler_DMA5 [WEAK]
EXPORT NVIC_Handler_DMA6 [WEAK]
EXPORT NVIC_Handler_DMA7 [WEAK]
EXPORT NVIC_Handler_DMA8 [WEAK]
EXPORT NVIC_Handler_DMA9 [WEAK]
EXPORT NVIC_Handler_DMA10 [WEAK]
EXPORT NVIC_Handler_DMA11 [WEAK]
EXPORT NVIC_Handler_DMA12 [WEAK]
EXPORT NVIC_Handler_DMA13 [WEAK]
EXPORT NVIC_Handler_UART0 [WEAK]
EXPORT NVIC_Handler_UART1 [WEAK]
EXPORT NVIC_Handler_EMI0 [WEAK]
EXPORT NVIC_Handler_EMI1 [WEAK]
EXPORT NVIC_Handler_EMI2 [WEAK]
EXPORT NVIC_Handler_ACPI_EC0_IBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC0_OBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC1_IBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC1_OBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC2_IBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC2_OBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC3_IBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC3_OBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC4_IBF [WEAK]
EXPORT NVIC_Handler_ACPI_EC4_OBF [WEAK]
EXPORT NVIC_Handler_PM1_CTL [WEAK]
EXPORT NVIC_Handler_PM1_EN [WEAK]
EXPORT NVIC_Handler_PM1_STS [WEAK]
EXPORT NVIC_Handler_MIF8042_OBF [WEAK]
EXPORT NVIC_Handler_MIF8042_IBF [WEAK]
EXPORT NVIC_Handler_MB_H2EC [WEAK]
EXPORT NVIC_Handler_MB_DATA [WEAK]
EXPORT NVIC_Handler_P80A [WEAK]
EXPORT NVIC_Handler_P80B [WEAK]
EXPORT NVIC_Handler_PKE_ERR [WEAK]
EXPORT NVIC_Handler_PKE_END [WEAK]
EXPORT NVIC_Handler_TRNG [WEAK]
EXPORT NVIC_Handler_AES [WEAK]
EXPORT NVIC_Handler_HASH [WEAK]
EXPORT NVIC_Handler_PECI [WEAK]
EXPORT NVIC_Handler_TACH0 [WEAK]
EXPORT NVIC_Handler_TACH1 [WEAK]
EXPORT NVIC_Handler_TACH2 [WEAK]
EXPORT NVIC_Handler_R2P0_FAIL [WEAK]
EXPORT NVIC_Handler_R2P0_STALL [WEAK]
EXPORT NVIC_Handler_R2P1_FAIL [WEAK]
EXPORT NVIC_Handler_R2P1_STALL [WEAK]
EXPORT NVIC_Handler_ADC_SNGL [WEAK]
EXPORT NVIC_Handler_ADC_RPT [WEAK]
EXPORT NVIC_Handler_RCID0 [WEAK]
EXPORT NVIC_Handler_RCID1 [WEAK]
EXPORT NVIC_Handler_RCID2 [WEAK]
EXPORT NVIC_Handler_LED0 [WEAK]
EXPORT NVIC_Handler_LED1 [WEAK]
EXPORT NVIC_Handler_LED2 [WEAK]
EXPORT NVIC_Handler_LED3 [WEAK]
EXPORT NVIC_Handler_PHOT [WEAK]
EXPORT NVIC_Handler_PWRGD0 [WEAK]
EXPORT NVIC_Handler_PWRGD1 [WEAK]
EXPORT NVIC_Handler_LPCBERR [WEAK]
EXPORT NVIC_Handler_QMSPI0 [WEAK]
EXPORT NVIC_Handler_GPSPI0_TX [WEAK]
EXPORT NVIC_Handler_GPSPI0_RX [WEAK]
EXPORT NVIC_Handler_GPSPI1_TX [WEAK]
EXPORT NVIC_Handler_GPSPI1_RX [WEAK]
EXPORT NVIC_Handler_BC0_BUSY [WEAK]
EXPORT NVIC_Handler_BC0_ERR [WEAK]
EXPORT NVIC_Handler_BC1_BUSY [WEAK]
EXPORT NVIC_Handler_BC1_ERR [WEAK]
EXPORT NVIC_Handler_PS2_0 [WEAK]
EXPORT NVIC_Handler_PS2_1 [WEAK]
EXPORT NVIC_Handler_PS2_2 [WEAK]
EXPORT NVIC_Handler_ESPI_PC [WEAK]
EXPORT NVIC_Handler_ESPI_BM1 [WEAK]
EXPORT NVIC_Handler_ESPI_BM2 [WEAK]
EXPORT NVIC_Handler_ESPI_LTR [WEAK]
EXPORT NVIC_Handler_ESPI_OOB_UP [WEAK]
EXPORT NVIC_Handler_ESPI_OOB_DN [WEAK]
EXPORT NVIC_Handler_ESPI_FLASH [WEAK]
EXPORT NVIC_Handler_ESPI_RESET [WEAK]
EXPORT NVIC_Handler_RTMR [WEAK]
EXPORT NVIC_Handler_HTMR0 [WEAK]
EXPORT NVIC_Handler_HTMR1 [WEAK]
EXPORT NVIC_Handler_WK [WEAK]
EXPORT NVIC_Handler_WKSUB [WEAK]
EXPORT NVIC_Handler_WKSEC [WEAK]
EXPORT NVIC_Handler_WKSUBSEC [WEAK]
EXPORT NVIC_Handler_SYSPWR [WEAK]
EXPORT NVIC_Handler_RTC [WEAK]
EXPORT NVIC_Handler_RTC_ALARM [WEAK]
EXPORT NVIC_Handler_VCI_OVRD_IN [WEAK]
EXPORT NVIC_Handler_VCI_IN0 [WEAK]
EXPORT NVIC_Handler_VCI_IN1 [WEAK]
EXPORT NVIC_Handler_VCI_IN2 [WEAK]
EXPORT NVIC_Handler_VCI_IN3 [WEAK]
EXPORT NVIC_Handler_VCI_IN4 [WEAK]
EXPORT NVIC_Handler_VCI_IN5 [WEAK]
EXPORT NVIC_Handler_VCI_IN6 [WEAK]
EXPORT NVIC_Handler_PS20A_WAKE [WEAK]
EXPORT NVIC_Handler_PS20B_WAKE [WEAK]
EXPORT NVIC_Handler_PS21A_WAKE [WEAK]
EXPORT NVIC_Handler_PS21B_WAKE [WEAK]
EXPORT NVIC_Handler_PS21_WAKE [WEAK]
EXPORT NVIC_Handler_ENVMON [WEAK]
EXPORT NVIC_Handler_KEYSCAN [WEAK]
EXPORT NVIC_Handler_BTMR16_0 [WEAK]
EXPORT NVIC_Handler_BTMR16_1 [WEAK]
EXPORT NVIC_Handler_BTMR16_2 [WEAK]
EXPORT NVIC_Handler_BTMR16_3 [WEAK]
EXPORT NVIC_Handler_BTMR32_0 [WEAK]
EXPORT NVIC_Handler_BTMR32_1 [WEAK]
EXPORT NVIC_Handler_EVTMR0 [WEAK]
EXPORT NVIC_Handler_EVTMR1 [WEAK]
EXPORT NVIC_Handler_EVTMR2 [WEAK]
EXPORT NVIC_Handler_EVTMR3 [WEAK]
EXPORT NVIC_Handler_CAPTMR [WEAK]
EXPORT NVIC_Handler_CAP0 [WEAK]
EXPORT NVIC_Handler_CAP1 [WEAK]
EXPORT NVIC_Handler_CAP2 [WEAK]
EXPORT NVIC_Handler_CAP3 [WEAK]
EXPORT NVIC_Handler_CAP4 [WEAK]
EXPORT NVIC_Handler_CAP5 [WEAK]
EXPORT NVIC_Handler_CMP0 [WEAK]
EXPORT NVIC_Handler_CMP1 [WEAK]
NVIC_Handler_GIRQ08
NVIC_Handler_GIRQ09
NVIC_Handler_GIRQ10
NVIC_Handler_GIRQ11
NVIC_Handler_GIRQ12
NVIC_Handler_GIRQ13
NVIC_Handler_GIRQ14
NVIC_Handler_GIRQ15
NVIC_Handler_GIRQ16
NVIC_Handler_GIRQ17
NVIC_Handler_GIRQ18
NVIC_Handler_GIRQ19
NVIC_Handler_GIRQ20
NVIC_Handler_GIRQ21
NVIC_Handler_GIRQ23
NVIC_Handler_GIRQ24
NVIC_Handler_GIRQ25
NVIC_Handler_GIRQ26
NVIC_Handler_I2C0
NVIC_Handler_I2C1
NVIC_Handler_I2C2
NVIC_Handler_I2C3
NVIC_Handler_DMA0
NVIC_Handler_DMA1
NVIC_Handler_DMA2
NVIC_Handler_DMA3
NVIC_Handler_DMA4
NVIC_Handler_DMA5
NVIC_Handler_DMA6
NVIC_Handler_DMA7
NVIC_Handler_DMA8
NVIC_Handler_DMA9
NVIC_Handler_DMA10
NVIC_Handler_DMA11
NVIC_Handler_DMA12
NVIC_Handler_DMA13
NVIC_Handler_UART0
NVIC_Handler_UART1
NVIC_Handler_EMI0
NVIC_Handler_EMI1
NVIC_Handler_EMI2
NVIC_Handler_ACPI_EC0_IBF
NVIC_Handler_ACPI_EC0_OBF
NVIC_Handler_ACPI_EC1_IBF
NVIC_Handler_ACPI_EC1_OBF
NVIC_Handler_ACPI_EC2_IBF
NVIC_Handler_ACPI_EC2_OBF
NVIC_Handler_ACPI_EC3_IBF
NVIC_Handler_ACPI_EC3_OBF
NVIC_Handler_ACPI_EC4_IBF
NVIC_Handler_ACPI_EC4_OBF
NVIC_Handler_PM1_CTL
NVIC_Handler_PM1_EN
NVIC_Handler_PM1_STS
NVIC_Handler_MIF8042_OBF
NVIC_Handler_MIF8042_IBF
NVIC_Handler_MB_H2EC
NVIC_Handler_MB_DATA
NVIC_Handler_P80A
NVIC_Handler_P80B
NVIC_Handler_PKE_ERR
NVIC_Handler_PKE_END
NVIC_Handler_TRNG
NVIC_Handler_AES
NVIC_Handler_HASH
NVIC_Handler_PECI
NVIC_Handler_TACH0
NVIC_Handler_TACH1
NVIC_Handler_TACH2
NVIC_Handler_R2P0_FAIL
NVIC_Handler_R2P0_STALL
NVIC_Handler_R2P1_FAIL
NVIC_Handler_R2P1_STALL
NVIC_Handler_ADC_SNGL
NVIC_Handler_ADC_RPT
NVIC_Handler_RCID0
NVIC_Handler_RCID1
NVIC_Handler_RCID2
NVIC_Handler_LED0
NVIC_Handler_LED1
NVIC_Handler_LED2
NVIC_Handler_LED3
NVIC_Handler_PHOT
NVIC_Handler_PWRGD0
NVIC_Handler_PWRGD1
NVIC_Handler_LPCBERR
NVIC_Handler_QMSPI0
NVIC_Handler_GPSPI0_TX
NVIC_Handler_GPSPI0_RX
NVIC_Handler_GPSPI1_TX
NVIC_Handler_GPSPI1_RX
NVIC_Handler_BC0_BUSY
NVIC_Handler_BC0_ERR
NVIC_Handler_BC1_BUSY
NVIC_Handler_BC1_ERR
NVIC_Handler_PS2_0
NVIC_Handler_PS2_1
NVIC_Handler_PS2_2
NVIC_Handler_ESPI_PC
NVIC_Handler_ESPI_BM1
NVIC_Handler_ESPI_BM2
NVIC_Handler_ESPI_LTR
NVIC_Handler_ESPI_OOB_UP
NVIC_Handler_ESPI_OOB_DN
NVIC_Handler_ESPI_FLASH
NVIC_Handler_ESPI_RESET
NVIC_Handler_RTMR
NVIC_Handler_HTMR0
NVIC_Handler_HTMR1
NVIC_Handler_WK
NVIC_Handler_WKSUB
NVIC_Handler_WKSEC
NVIC_Handler_WKSUBSEC
NVIC_Handler_SYSPWR
NVIC_Handler_RTC
NVIC_Handler_RTC_ALARM
NVIC_Handler_VCI_OVRD_IN
NVIC_Handler_VCI_IN0
NVIC_Handler_VCI_IN1
NVIC_Handler_VCI_IN2
NVIC_Handler_VCI_IN3
NVIC_Handler_VCI_IN4
NVIC_Handler_VCI_IN5
NVIC_Handler_VCI_IN6
NVIC_Handler_PS20A_WAKE
NVIC_Handler_PS20B_WAKE
NVIC_Handler_PS21A_WAKE
NVIC_Handler_PS21B_WAKE
NVIC_Handler_PS21_WAKE
NVIC_Handler_ENVMON
NVIC_Handler_KEYSCAN
NVIC_Handler_BTMR16_0
NVIC_Handler_BTMR16_1
NVIC_Handler_BTMR16_2
NVIC_Handler_BTMR16_3
NVIC_Handler_BTMR32_0
NVIC_Handler_BTMR32_1
NVIC_Handler_EVTMR0
NVIC_Handler_EVTMR1
NVIC_Handler_EVTMR2
NVIC_Handler_EVTMR3
NVIC_Handler_CAPTMR
NVIC_Handler_CAP0
NVIC_Handler_CAP1
NVIC_Handler_CAP2
NVIC_Handler_CAP3
NVIC_Handler_CAP4
NVIC_Handler_CAP5
NVIC_Handler_CMP0
NVIC_Handler_CMP1
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/*
**********************************************************************************
* © 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
**********************************************************************************
* ARM_REG.h
* This is the header to define Cortex-M3 system control & status registers
**********************************************************************************
* SMSC version control information (Perforce):
*
* FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/ARM_REG.h $
* REVISION: $Revision: #1 $
* DATETIME: $DateTime: 2016/09/22 08:03:49 $
* AUTHOR: $Author: pramans $
*
* Revision history (latest first):
* #xx
***********************************************************************************
*/
/******************************************************************************/
/** @defgroup ARM_REG ARM_REG
* @{
*/
/** @file ARM_REG.h
* \brief ARM Cortex-M3 registers header file
* \author KBCEC Team
*
* This file contains ARM Cortex-M3 system control & status registers.
******************************************************************************/
#ifndef ARM_REG_H_
#define ARM_REG_H_
#define REG8(x) (*((volatile unsigned char *)(x)))
#define REG16(x) (*((volatile unsigned short *)(x)))
#define REG32(x) (*((volatile unsigned long *)(x)))
/* NVIC Registers */
#define NVIC_INT_TYPE REG32(0xE000E004)
#define NVIC_AUX_ACTLR REG32(0xE000E008)
#define WR_BUF_DISABLE (1 << 1)
#define NVIC_ST_CTRL REG32(0xE000E010)
#define ST_ENABLE (1 << 0)
#define ST_TICKINT (1 << 1)
#define ST_CLKSOURCE (1 << 2)
#define ST_COUNTFLAG (1 << 3)
#define NVIC_ST_RELOAD REG32(0xE000E014)
#define NVIC_ST_CURRENT REG32(0xE000E018)
#define NVIC_ST_CALIB REG32(0xE000E01C)
#define NVIC_ENABLE0 REG32(0xE000E100)
#define NVIC_ENABLE1 REG32(0xE000E104)
#define NVIC_ENABLE2 REG32(0xE000E108)
#define NVIC_ENABLE3 REG32(0xE000E10C)
#define NVIC_ENABLE4 REG32(0xE000E110)
#define NVIC_ENABLE5 REG32(0xE000E114)
#define NVIC_ENABLE6 REG32(0xE000E118)
#define NVIC_ENABLE7 REG32(0xE000E11C)
#define NVIC_DISABLE0 REG32(0xE000E180)
#define NVIC_DISABLE1 REG32(0xE000E184)
#define NVIC_DISABLE2 REG32(0xE000E188)
#define NVIC_DISABLE3 REG32(0xE000E18C)
#define NVIC_DISABLE4 REG32(0xE000E190)
#define NVIC_DISABLE5 REG32(0xE000E194)
#define NVIC_DISABLE6 REG32(0xE000E198)
#define NVIC_DISABLE7 REG32(0xE000E19C)
#define NVIC_PEND0 REG32(0xE000E200)
#define NVIC_PEND1 REG32(0xE000E204)
#define NVIC_PEND2 REG32(0xE000E208)
#define NVIC_PEND3 REG32(0xE000E20C)
#define NVIC_PEND4 REG32(0xE000E210)
#define NVIC_PEND5 REG32(0xE000E214)
#define NVIC_PEND6 REG32(0xE000E218)
#define NVIC_PEND7 REG32(0xE000E21C)
#define NVIC_UNPEND0 REG32(0xE000E280)
#define NVIC_UNPEND1 REG32(0xE000E284)
#define NVIC_UNPEND2 REG32(0xE000E288)
#define NVIC_UNPEND3 REG32(0xE000E28C)
#define NVIC_UNPEND4 REG32(0xE000E290)
#define NVIC_UNPEND5 REG32(0xE000E294)
#define NVIC_UNPEND6 REG32(0xE000E298)
#define NVIC_UNPEND7 REG32(0xE000E29C)
#define NVIC_ACTIVE0 REG32(0xE000E300)
#define NVIC_ACTIVE1 REG32(0xE000E304)
#define NVIC_ACTIVE2 REG32(0xE000E308)
#define NVIC_ACTIVE3 REG32(0xE000E30C)
#define NVIC_ACTIVE4 REG32(0xE000E310)
#define NVIC_ACTIVE5 REG32(0xE000E314)
#define NVIC_ACTIVE6 REG32(0xE000E318)
#define NVIC_ACTIVE7 REG32(0xE000E31C)
#define NVIC_PRI0 REG32(0xE000E400)
#define NVIC_PRI1 REG32(0xE000E404)
#define NVIC_PRI2 REG32(0xE000E408)
#define NVIC_PRI3 REG32(0xE000E40C)
#define NVIC_PRI4 REG32(0xE000E410)
#define NVIC_PRI5 REG32(0xE000E414)
#define NVIC_PRI6 REG32(0xE000E418)
#define NVIC_PRI7 REG32(0xE000E41C)
#define NVIC_PRI8 REG32(0xE000E420)
#define NVIC_PRI9 REG32(0xE000E424)
#define NVIC_PRI10 REG32(0xE000E428)
#define NVIC_PRI11 REG32(0xE000E42C)
#define NVIC_PRI12 REG32(0xE000E430)
#define NVIC_PRI13 REG32(0xE000E434)
#define NVIC_PRI14 REG32(0xE000E438)
#define NVIC_PRI15 REG32(0xE000E43C)
#define NVIC_PRI16 REG32(0xE000E440)
#define NVIC_PRI17 REG32(0xE000E444)
#define NVIC_PRI18 REG32(0xE000E448)
#define NVIC_PRI19 REG32(0xE000E44C)
#define NVIC_PRI20 REG32(0xE000E450)
#define NVIC_PRI21 REG32(0xE000E454)
#define NVIC_PRI22 REG32(0xE000E458)
#define NVIC_PRI23 REG32(0xE000E45C)
#define NVIC_PRI24 REG32(0xE000E460)
#define NVIC_PRI25 REG32(0xE000E464)
#define NVIC_PRI26 REG32(0xE000E468)
#define NVIC_PRI27 REG32(0xE000E46C)
#define NVIC_PRI28 REG32(0xE000E470)
#define NVIC_PRI29 REG32(0xE000E474)
#define NVIC_PRI30 REG32(0xE000E478)
#define NVIC_PRI31 REG32(0xE000E47C)
#define NVIC_PRI32 REG32(0xE000E480)
#define NVIC_PRI33 REG32(0xE000E484)
#define NVIC_PRI34 REG32(0xE000E488)
#define NVIC_PRI35 REG32(0xE000E48C)
#define NVIC_PRI36 REG32(0xE000E490)
#define NVIC_PRI37 REG32(0xE000E494)
#define NVIC_PRI38 REG32(0xE000E498)
#define NVIC_PRI39 REG32(0xE000E49C)
#define NVIC_PRI40 REG32(0xE000E4A0)
#define NVIC_PRI41 REG32(0xE000E4A4)
#define NVIC_PRI42 REG32(0xE000E4A8)
#define NVIC_PRI43 REG32(0xE000E4AC)
#define NVIC_PRI44 REG32(0xE000E4B0)
#define NVIC_PRI45 REG32(0xE000E4B4)
#define NVIC_PRI46 REG32(0xE000E4B8)
#define NVIC_PRI47 REG32(0xE000E4BC)
#define NVIC_PRI48 REG32(0xE000E4C0)
#define NVIC_PRI49 REG32(0xE000E4C4)
#define NVIC_PRI50 REG32(0xE000E4C8)
#define NVIC_PRI51 REG32(0xE000E4CC)
#define NVIC_PRI52 REG32(0xE000E4D0)
#define NVIC_PRI53 REG32(0xE000E4D4)
#define NVIC_PRI54 REG32(0xE000E4D8)
#define NVIC_PRI55 REG32(0xE000E4DC)
#define NVIC_PRI56 REG32(0xE000E4E0)
#define NVIC_PRI57 REG32(0xE000E4E4)
#define NVIC_PRI58 REG32(0xE000E4E8)
#define NVIC_PRI59 REG32(0xE000E4EC)
#define NVIC_CPUID REG32(0xE000ED00)
#define NVIC_INT_CTRL REG32(0xE000ED04)
#define NVIC_VECT_TABLE REG32(0xE000ED08)
#define NVIC_AP_INT_RST REG32(0xE000ED0C)
#define NVIC_SYS_CTRL REG32(0xE000ED10)
#define NVIC_CFG_CTRL REG32(0xE000ED14)
#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)
#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)
#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)
#define NVIC_SYS_H_CTRL REG32(0xE000ED24)
#define NVIC_FAULT_STA REG32(0xE000ED28)
#define NVIC_HARD_F_STA REG32(0xE000ED2C)
#define NVIC_DBG_F_STA REG32(0xE000ED30)
#define NVIC_MM_F_ADR REG32(0xE000ED34)
#define NVIC_BUS_F_ADR REG32(0xE000ED38)
#define NVIC_SW_TRIG REG32(0xE000EF00)
/* MPU Registers */
#define MPU_TYPE REG32(0xE000ED90)
#define MPU_CTRL REG32(0xE000ED94)
#define MPU_RG_NUM REG32(0xE000ED98)
#define MPU_RG_ADDR REG32(0xE000ED9C)
#define MPU_RG_AT_SZ REG32(0xE000EDA0)
#endif /* #ifndef ARM_REG_H_ */
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Updated with unit testing feedbacks
******************************************************************************/
/** @file btimer.h
* \brief Basic Timer Peripheral Header file
* \author jvasanth
*
* This file is the header file for Basic Timer Peripheral
******************************************************************************/
/** @defgroup Basic_Timer
* @{
*/
#ifndef _BTIMER_H
#define _BTIMER_H
/******************************************************************************/
/** Logical Timer ID for APIs.
* This is the timer IDs passed to Basic Timer API function calls
*******************************************************************************/
enum _PID_BTIMER_
{
PID_BTIMER_0,
PID_BTIMER_1,
PID_BTIMER_2,
PID_BTIMER_3,
PID_BTIMER_4,
PID_BTIMER_5,
PID_BTIMER_MAX
};
/* ---------------------------------------------------------------------- */
/* Logical flags for Timer Control */
/* ---------------------------------------------------------------------- */
//This is for tmr_cntl parameter in btimer_init function
#define BTIMER_AUTO_RESTART (0x08u)
#define BTIMER_ONE_SHOT (0u)
#define BTIMER_COUNT_UP (0x04u)
#define BTIMER_COUNT_DOWN (0u)
#define BTIMER_INT_EN (0x01u)
#define BTIMER_NO_INT (0u)
/* ---------------------------------------------------------------------- */
//Timer Block Hardware Bits and Masks
#define BTIMER_CNTL_HALT (0x80UL)
#define BTIMER_CNTL_RELOAD (0x40UL)
#define BTIMER_CNTL_START (0x20UL)
#define BTIMER_CNTL_SOFT_RESET (0x10UL)
#define BTIMER_CNTL_AUTO_RESTART (0x08UL)
#define BTIMER_CNTL_COUNT_UP (0x04UL)
#define BTIMER_CNTL_ENABLE (0x01UL)
#define BTIMER_CNTL_HALT_BIT (7U)
#define BTIMER_CNTL_RELOAD_BIT (6U)
#define BTIMER_CNTL_START_BIT (5U)
#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)
#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)
#define BTIMER_CNTL_COUNT_DIR_BIT (2U)
#define BTIMER_CNTL_ENABLE_BIT (0U)
#define BTIMER_GIRQ MEC_GIRQ23_ID
#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX
/* ---------------------------------------------------------------------- */
/* API - Basic Timer Intitialization function */
/* ---------------------------------------------------------------------- */
/** Initialize specified timer
* @param btimer_id Basic Timer ID
* @param tmr_cntl Logical flags for Timer Control
* @param initial_count Initial Count
* @param preload_count Preload Count
* @note Performs a soft reset of the timer before configuration
*/
void btimer_init(uint8_t btimer_id,
uint16_t tmr_cntl,
uint16_t prescaler,
uint32_t initial_count,
uint32_t preload_count);
/* ---------------------------------------------------------------------- */
/* API - Functions to program and read the Basic Timer Counter */
/* ---------------------------------------------------------------------- */
/** Program timer's counter register.
* @param btimer_id Basic Timer ID
* @param count new counter value
* @note Timer hardware may implement a 16-bit or 32-bit
* hardware counter. If the timer is 16-bit only the lower
* 16-bits of the count paramter are used.
*/
void btimer_count_set(uint8_t btimer_id, uint32_t count);
/** Return current value of timer's count register.
* @param btimer_id Basic Timer ID.
* @return uint32_t timer count may be 32 or 16 bits depending
* upon the hardware. Timers 0-3 are 16-bit
* and Timers 4-5 are 32-bit.
*/
uint32_t btimer_count_get(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Function to reload counter from Preload Register */
/* ---------------------------------------------------------------------- */
/** Force timer to reload counter from preload
* register.
* @param btimer_id Basic Timer ID.
* @note Hardware will only reload counter if timer is running.
*/
void btimer_reload(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Functions for stopping and starting the basic Timer */
/* ---------------------------------------------------------------------- */
/** Start timer counting.
* @param btimer_id Basic Timer ID.
*/
void btimer_start(uint8_t btimer_id);
/** Stop timer.
* @param btimer_id Basic Timer ID.
* @note When a stopped timer is started again it will reload
* the count register from preload value.
*/
void btimer_stop(uint8_t btimer_id);
/** Return state of timer's START bit.
* @param btimer_id Basic Timer ID.
* @return uint8_t 0(timer not started), 1 (timer started)
*/
uint8_t btimer_is_started(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Function to perform basic timer soft reset */
/* ---------------------------------------------------------------------- */
/** Peform soft reset of specified timer.
* @param btimer_id Basic Timer ID
* @note Soft reset set all registers to POR values.
* Spins 256 times waiting on hardware to clear reset bit.
*/
void btimer_reset(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Functions to halt/unhalt the timer counting */
/* ---------------------------------------------------------------------- */
/** Halt timer counting with no reload on unhalt.
* @param btimer_id Basic Timer ID.
* @note A halted timer will not reload the count register when
* unhalted, it will continue counting from the current
* count value.
*/
void btimer_halt(uint8_t btimer_id);
/** Unhalt timer counting.
* @param btimer_id Basic Timer ID.
*/
void btimer_unhalt(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Functions for Basic Timer interrupt */
/* ---------------------------------------------------------------------- */
/** Enable specified timer's interrupt from the block.
* @param btimer_id Basic Timer ID.
* @param ien Non-zero enable interrupt in timer block, 0
* disable.
*/
void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);
/** Read Timer interrupt status and clear if set
* @param btimer_id Basic Timer ID.
* @return uint8_t 1 (Timer interrupt status set) else 0.
* @note If timer interrupt status is set then clear it before
* returning.
*/
uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Functions for Basic Timer GIRQ */
/* ---------------------------------------------------------------------- */
/** Enables GIRQ enable bit for the timer
* @param btimer_id Basic Timer ID.
*/
void btimer_girq_enable_set(uint8_t btimer_id);
/** Clears GIRQ enable bit for the timer
* @param btimer_id Basic Timer ID.
*/
void btimer_girq_enable_clr(uint8_t btimer_id);
/** Returns GIRQ source bit for the timer
* @param btimer_id Basic Timer ID.
* @return uint8_t 0(src bit not set), Non-zero (src bit set)
*/
uint8_t btimer_girq_src_get(uint8_t btimer_id);
/** Clears GIRQ source bit for the timer
* @param btimer_id Basic Timer ID.
*/
void btimer_girq_src_clr(uint8_t btimer_id);
/** Returns GIRQ result bit for the timer
* @param btimer_id Basic Timer ID.
* @return uint8_t 0(result bit not set), Non-zero (result bit set)
*/
uint8_t btimer_girq_result_get(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* API - Functions for Basic Timer Sleep */
/* ---------------------------------------------------------------------- */
/** Enable/Disable clock gating on idle of a timer
* @param btimer_id Basic Timer ID.
* @param sleep_en 1 = Sleep enable, 0 = Sleep disable
*/
void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);
/** Returns clk required status for the timer block
* @param btimer_id Basic Timer ID.
* @return Non-zero if clk required, else 0
*/
uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);
/** Enable/Disable reset on sleep for the timer block
* @param btimer_id Basic Timer ID.
* @param reset_en 1 to enable, 0 to disable
*/
void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions to set and read Timer Counter Register */
/* ---------------------------------------------------------------------- */
/** Sets timer counter
* @param btimer_id Basic Timer ID
* @param count - 32-bit counter
*/
void p_btimer_count_set(uint8_t btimer_id, uint32_t count);
/** Read the timer counter
* @param btimer_id Basic Timer ID
* @return count - 32-bit counter
*/
uint32_t p_btimer_count_get(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Function to program the Preload */
/* ---------------------------------------------------------------------- */
/** Sets preload for the counter
* @param btimer_id Basic Timer ID
* @param preload_count - 32-bit pre-load value
*/
void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);
/* ---------------------------------------------------------------------- */
/* Peripheral Functions - Functions for basic timer interrupts */
/* ---------------------------------------------------------------------- */
/** Reads the interrupt status bit in the timer block
* @param btimer_id Basic Timer ID
* @return status - 1 if interrupt status set, else 0
*/
uint8_t p_btimer_int_status_get(uint8_t btimer_id);
/** Clears interrupt status bit in the timer block
* @param btimer_id Basic Timer ID
*/
void p_btimer_int_status_clr(uint8_t btimer_id);
/** Sets interrupt enable bit in the timer block
* @param btimer_id Basic Timer ID
*/
void p_btimer_int_enable_set(uint8_t btimer_id);
/** Clears interrupt enable bit for the timer block
* @param btimer_id Basic Timer ID
*/
void p_btimer_int_enable_clr(uint8_t btimer_id);
/* ---------------------------------------------------------------------- */
/* Peripheral Functions - Functions for Control Register */
/* ---------------------------------------------------------------------- */
/** Writes the control register 32-bits
* @param btimer_id Basic Timer ID
* @param value - 32-bit value to program
*/
void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);
/** Reads the control register
* @param btimer_id Basic Timer ID
* @return uint32_t - 32-bit value
*/
uint32_t p_btimer_ctrl_read(uint8_t btimer_id);
/** Clears enable bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_enable_set(uint8_t btimer_id);
/** Clears enable bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_enable_clr(uint8_t btimer_id);
/** Sets counter direction bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);
/** Clears counter direction bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);
/** Sets auto restart bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);
/** Clears auto resetart bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);
/** Sets soft reset bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);
/** Read Soft Reset bit
* @param btimer_id Basic Timer ID
* @return 0 if soft reset status bit cleared; else non-zero value
*/
uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);
/** Sets start bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_start_set(uint8_t btimer_id);
/** Read start bit in the control register
* @param btimer_id Basic Timer ID
* @return 0 if start bit not set; else non-zero value
*/
uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);
/** Clears start bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_start_clr(uint8_t btimer_id);
/** Sets reload bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_reload_set(uint8_t btimer_id);
/** Clears reload bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_reload_clr(uint8_t btimer_id);
/** Sets halt bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_halt_set(uint8_t btimer_id);
/** Clears halt bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_halt_clr(uint8_t btimer_id);
/** Sets prescale value
* @param btimer_id Basic Timer ID
* @param prescaler - 16-bit pre-scale value
*/
void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);
#endif // #ifndef _BTIMER_H
/* end btimer_perphl.c */
/** @} //Peripherals Basic_Timer
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Updated for tabs
******************************************************************************/
/** @file btimer_api.c
* \brief Basic Timer APIs Source file
* \author jvasanth
*
* This file implements the Basic Timer API functions
******************************************************************************/
/** @defgroup Basic_Timer
* @{
*/
#include "common_lib.h"
#include "btimer.h"
#include "..\pcr\pcr.h"
//#include "..\interrupt\ecia.h"
/** Basic Timer Sleep Registers & Bit Positions */
static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {
PCR_BTIMER0,
PCR_BTIMER1,
PCR_BTIMER2,
PCR_BTIMER3,
PCR_BTIMER4,
PCR_BTIMER5
};
#ifdef PLIB_BTIMER_CHECK_ID
/** Local helper that checks if logical Timer ID is valid.
* @param btimer_id Basic Timer ID
* @return uint8_t Non-zero(VALID), 0(Invalid)
*/
static uint8_t btmr_valid(uint8_t btimer_id)
{
if ( btimer_id < (PID_BTIMER_MAX ) ) {
return true;
}
return false;
}
#else
/** This version of tmr_valid skips checking always returning 1.
* Compiler may optimize it out.
* @param btimer_id Basic Timer ID
* @return uint8_t 1(VALID)
*/
static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }
#endif
/* ---------------------------------------------------------------------- */
/* Basic Timer Intitialization function */
/* ---------------------------------------------------------------------- */
/** Initialize specified timer
* @param btimer_id Basic Timer ID
* @param tmr_cntl Logical flags for Timer Control
* @param initial_count Initial Count
* @param preload_count Preload Count
* @note Performs a soft reset of the timer before configuration
*/
void btimer_init(uint8_t btimer_id,
uint16_t tmr_cntl,
uint16_t prescaler,
uint32_t initial_count,
uint32_t preload_count)
{
uint32_t value;
if (btmr_valid(btimer_id)) {
btimer_reset(btimer_id);
// Ungate timer clocks and program prescale
value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE);
p_btimer_ctrl_write(btimer_id, value);
// Program Preload & initial counter value
p_btimer_preload_set(btimer_id, preload_count);
p_btimer_count_set(btimer_id, initial_count);
// Program control register, interrupt enable, and clear status
if (tmr_cntl & BTIMER_COUNT_UP) {
p_btimer_ctrl_counter_dir_set(btimer_id);
}
if (tmr_cntl & BTIMER_AUTO_RESTART) {
p_btimer_ctrl_auto_restart_set(btimer_id);
}
if (tmr_cntl & BTIMER_INT_EN) {
p_btimer_int_enable_set(btimer_id); // enable first
p_btimer_int_status_clr(btimer_id); // clear status
}
}
}
/* ---------------------------------------------------------------------- */
/* Functions to program and read the Basic Timer Counter */
/* ---------------------------------------------------------------------- */
/** Program timer's counter register.
* @param btimer_id Basic Timer ID
* @param count new counter value
* @note Timer hardware may implement a 16-bit or 32-bit
* hardware counter. If the timer is 16-bit only the lower
* 16-bits of the count paramter are used.
*/
void btimer_count_set(uint8_t btimer_id, uint32_t count)
{
if ( btmr_valid(btimer_id) ) {
p_btimer_count_set(btimer_id, count);
}
}
/** Return current value of timer's count register.
* @param btimer_id Basic Timer ID.
* @return uint32_t timer count may be 32 or 16 bits depending
* upon the hardware. Timers 0-3 are 16-bit
* and Timers 4-5 are 32-bit.
*/
uint32_t btimer_count_get(uint8_t btimer_id)
{
uint32_t cnt;
cnt = 0ul;
if ( btmr_valid(btimer_id) ) {
cnt = p_btimer_count_get(btimer_id);
}
return cnt;
}
/* ---------------------------------------------------------------------- */
/* Function to reload counter from Preload Register */
/* ---------------------------------------------------------------------- */
/** Force timer to reload counter from preload
* register.
* @param btimer_id Basic Timer ID.
* @note Hardware will only reload counter if timer is running.
*/
void btimer_reload(uint8_t btimer_id)
{
if ( btmr_valid(btimer_id) ) {
if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running
{
p_btimer_ctrl_reload_set(btimer_id);
}
}
}
/* ---------------------------------------------------------------------- */
/* Functions for stopping and starting the basic Timer */
/* ---------------------------------------------------------------------- */
/** Start timer counting.
* @param btimer_id Basic Timer ID.
*/
void btimer_start(uint8_t btimer_id)
{
if ( btmr_valid(btimer_id) ) {
p_btimer_ctrl_start_set(btimer_id);
}
}
/** Stop timer.
* @param btimer_id Basic Timer ID.
* @note When a stopped timer is started again it will reload
* the count register from preload value.
*/
void btimer_stop(uint8_t btimer_id)
{
if ( btmr_valid(btimer_id) ) {
p_btimer_ctrl_start_clr(btimer_id);
}
}
/** Return state of timer's START bit.
* @param btimer_id Basic Timer ID.
* @return uint8_t 0(timer not started), 1 (timer started)
*/
uint8_t btimer_is_started(uint8_t btimer_id)
{
uint8_t sts;
sts = 0;
if ( btmr_valid(btimer_id) ) {
if (p_btimer_ctrl_start_get(btimer_id))
{
sts = 1;
}
}
return sts;
}
/* ---------------------------------------------------------------------- */
/* Function to perform basic timer soft reset */
/* ---------------------------------------------------------------------- */
/** Peform soft reset of specified timer.
* @param btimer_id Basic Timer ID
* @note Soft reset set all registers to POR values.
* Spins 256 times waiting on hardware to clear reset bit.
*/
void btimer_reset(uint8_t btimer_id)
{
uint32_t wait_cnt;
uint8_t soft_reset_sts;
if (btmr_valid(btimer_id)) {
p_btimer_ctrl_soft_reset_set(btimer_id);
wait_cnt = 256ul;
do {
soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);
if (0 == soft_reset_sts){
break;
}
}
while ( wait_cnt-- );
}
}
/* ---------------------------------------------------------------------- */
/* Functions to halt/unhalt the timer counting */
/* ---------------------------------------------------------------------- */
/** Halt timer counting with no reload on unhalt.
* @param btimer_id Basic Timer ID.
* @note A halted timer will not reload the count register when
* unhalted, it will continue counting from the current
* count value.
*/
void btimer_halt(uint8_t btimer_id)
{
if ( btmr_valid(btimer_id) ) {
p_btimer_ctrl_halt_set(btimer_id);
}
}
/** Unhalt timer counting.
* @param btimer_id Basic Timer ID.
*/
void btimer_unhalt(uint8_t btimer_id)
{
if ( btmr_valid(btimer_id) ) {
p_btimer_ctrl_halt_clr(btimer_id);
}
}
/* ---------------------------------------------------------------------- */
/* Functions for Basic Timer interrupt */
/* ---------------------------------------------------------------------- */
/** Enable specified timer's interrupt from the block.
* @param btimer_id Basic Timer ID.
* @param ien Non-zero enable interrupt in timer block, 0
* disable.
*/
void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)
{
if (btmr_valid(btimer_id)) {
p_btimer_int_enable_set(btimer_id);
if (ien) {
p_btimer_int_enable_set(btimer_id);
} else {
p_btimer_int_enable_clr(btimer_id);
}
}
}
/** Read Timer interrupt status and clear if set
* @param btimer_id Basic Timer ID.
* @return uint8_t 1 (Timer interrupt status set) else 0.
* @note If timer interrupt status is set then clear it before
* returning.
*/
uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)
{
uint8_t sts;
sts = 0;
if (btmr_valid(btimer_id)) {
sts = p_btimer_int_status_get(btimer_id);
if (sts) {
p_btimer_int_status_clr(btimer_id);
}
}
return sts;
}
#if 0 //Temporary disable until interrupt module
/* ---------------------------------------------------------------------- */
/* Functions for Basic Timer GIRQ */
/* ---------------------------------------------------------------------- */
/** Enables GIRQ enable bit for the timer
* @param btimer_id Basic Timer ID.
*/
void btimer_girq_enable_set(uint8_t btimer_id)
{
if (btmr_valid(btimer_id))
{
//Note: Bit Position is same as Timer ID
p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);
}
}
/** Clears GIRQ enable bit for the timer
* @param btimer_id Basic Timer ID.
*/
void btimer_girq_enable_clr(uint8_t btimer_id)
{
if (btmr_valid(btimer_id))
{
//Note: Bit Position is same as Timer ID
p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);
}
}
/** Returns GIRQ source bit for the timer
* @param btimer_id Basic Timer ID.
* @return uint8_t 0(src bit not set), Non-zero (src bit set)
*/
uint8_t btimer_girq_src_get(uint8_t btimer_id)
{
uint8_t retVal;
retVal = 0;
if (btmr_valid(btimer_id))
{
//Note: Bit Position is same as Timer ID
retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id);
}
return retVal;
}
/** Clears GIRQ source bit for the timer
* @param btimer_id Basic Timer ID.
*/
void btimer_girq_src_clr(uint8_t btimer_id)
{
if (btmr_valid(btimer_id))
{
//Note: Bit Position is same as Timer ID
p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id);
}
}
/** Returns GIRQ result bit for the timer
* @param btimer_id Basic Timer ID.
* @return uint8_t 0(result bit not set), Non-zero (result bit set)
*/
uint8_t btimer_girq_result_get(uint8_t btimer_id)
{
uint8_t retVal;
retVal = 0;
if (btmr_valid(btimer_id))
{
//Note: Bit Position is same as Timer ID
retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id);
}
return retVal;
}
#endif
/* ---------------------------------------------------------------------- */
/* Functions for Basic Timer Sleep */
/* ---------------------------------------------------------------------- */
/** Enable/Disable clock gating on idle of a timer
* @param btimer_id Basic Timer ID.
* @param sleep_en 1 = Sleep enable, 0 = Sleep disable
*/
void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)
{
uint32_t pcr_blk_id;
if ( btmr_valid(btimer_id) )
{
pcr_blk_id = btmr_pcr_id[btimer_id];
pcr_sleep_enable(pcr_blk_id, sleep_en);
}
}
/** Returns clk required status for the timer block
* @param btimer_id Basic Timer ID.
* @return Non-zero if clk required, else 0
*/
uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)
{
uint32_t retVal;
uint32_t pcr_blk_id;
retVal = 0ul;
if ( btmr_valid(btimer_id) )
{
pcr_blk_id = btmr_pcr_id[btimer_id];
retVal = pcr_clock_reqd_status_get(pcr_blk_id);
}
return retVal;
}
/** Enable/Disable reset on sleep for the timer block
* @param btimer_id Basic Timer ID.
* @param reset_en 1 to enable, 0 to disable
*/
void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)
{
uint32_t pcr_blk_id;
if ( btmr_valid(btimer_id) )
{
pcr_blk_id = btmr_pcr_id[btimer_id];
pcr_reset_enable(pcr_blk_id, reset_en);
}
}
/* end btimer_api.c */
/** @} //Peripheral Basic_Timer
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Updated for tabs
******************************************************************************/
/** @file btimer_perphl.c
* \brief Basic Timer Peripheral Source file
* \author jvasanth
*
* This file implements the Basic Timer Peripheral functions
******************************************************************************/
/** @defgroup Basic_Timer
* @{
*/
#include "common_lib.h"
#include "btimer.h"
/** Basic Timer Instance base addresses */
static TIMER0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {
MEC2016_TIMER0,
MEC2016_TIMER1,
MEC2016_TIMER2,
MEC2016_TIMER3,
MEC2016_TIMER4,
MEC2016_TIMER5
};
/* ---------------------------------------------------------------------- */
/* Functions to set and read Timer Counter Register */
/* ---------------------------------------------------------------------- */
/** Sets timer counter
* @param btimer_id Basic Timer ID
* @param count - 32-bit counter
*/
void p_btimer_count_set(uint8_t btimer_id, uint32_t count)
{
btmr_inst[btimer_id]->COUNT = count;
}
/** Read the timer counter
* @param btimer_id Basic Timer ID
* @return count - 32-bit counter
*/
uint32_t p_btimer_count_get(uint8_t btimer_id)
{
return btmr_inst[btimer_id]->COUNT;
}
/* ---------------------------------------------------------------------- */
/* Function to program the Preload */
/* ---------------------------------------------------------------------- */
/** Sets preload for the counter
* @param btimer_id Basic Timer ID
* @param preload_count - 32-bit pre-load value
*/
void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)
{
btmr_inst[btimer_id]->PRE_LOAD = preload_count;
}
/* ---------------------------------------------------------------------- */
/* Functions for basic timer interrupts */
/* ---------------------------------------------------------------------- */
/** Reads the interrupt status bit in the timer block
* @param btimer_id Basic Timer ID
* @return status - 1 if interrupt status set, else 0
*/
uint8_t p_btimer_int_status_get(uint8_t btimer_id)
{
return (uint8_t)(btmr_inst[btimer_id]->STATUS);
}
/** Clears interrupt status bit in the timer block
* @param btimer_id Basic Timer ID
*/
void p_btimer_int_status_clr(uint8_t btimer_id)
{
// Write 1 to clear
btmr_inst[btimer_id]->STATUS = 1;
}
/** Sets interrupt enable bit in the timer block
* @param btimer_id Basic Timer ID
*/
void p_btimer_int_enable_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->INT_EN = 1;
}
/** Clears interrupt enable bit for the timer block
* @param btimer_id Basic Timer ID
*/
void p_btimer_int_enable_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->INT_EN = 0;
}
/* ---------------------------------------------------------------------- */
/* Functions for Control Register */
/* ---------------------------------------------------------------------- */
/** Writes the control register 32-bits
* @param btimer_id Basic Timer ID
* @param value - 32-bit value to program
*/
void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)
{
btmr_inst[btimer_id]->CONTROL.w = value;
}
/** Reads the control register
* @param btimer_id Basic Timer ID
* @return uint32_t - 32-bit value
*/
uint32_t p_btimer_ctrl_read(uint8_t btimer_id)
{
uint32_t retVal;
retVal = btmr_inst[btimer_id]->CONTROL.w;
return retVal;
}
/** Sets enable bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_enable_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;
}
/** Clears enable bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_enable_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;
}
/** Sets counter direction bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;
}
/** Clears counter direction bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;
}
/** Sets auto restart bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;
}
/** Clears auto resetart bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;
}
/** Sets soft reset bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;
}
/** Read Soft Reset bit
* @param btimer_id Basic Timer ID
* @return 0 if soft reset status bit cleared; else non-zero value
*/
uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)
{
return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);
}
/** Sets start bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_start_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;
}
/** Read start bit in the control register
* @param btimer_id Basic Timer ID
* @return 0 if start bit not set; else non-zero value
*/
uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)
{
return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);
}
/** Clears start bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_start_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;
}
/** Sets reload bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_reload_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;
}
/** Clears reload bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_reload_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;
}
/** Sets halt bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_halt_set(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;
}
/** Clears halt bit in the control register
* @param btimer_id Basic Timer ID
*/
void p_btimer_ctrl_halt_clr(uint8_t btimer_id)
{
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;
}
/** Sets prescale value
* @param btimer_id Basic Timer ID
* @param prescaler - 16-bit pre-scale value
*/
void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)
{
btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;
}
/* end btimer_perphl.c */
/** @} //Peripheral Basic_Timer
*/

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/*
**********************************************************************************
* © 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
**********************************************************************************
* common.h
* This is the header file including common headers from various modules
**********************************************************************************
* $Revision: #1 $ $DateTime: 2016/09/22 08:03:49 $ $ $
* Description: added ict module
**********************************************************************************
* #xx
**********************************************************************************
* $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/common.h $
*/
/*********************************************************************************/
/** @defgroup common common
* @{
*/
/** @file common.h
* \brief header file including common headers from various modules
* \author App Firmware Team
*
**********************************************************************************/
#ifndef _COMMON_H_
#define _COMMON_H_
// Include common headers from various modules
// !!! The include order is important !!!
#include "platform.h"
#include "MCHP_device_header.h"
/* Cortex-M4 processor and core peripherals */
#include "core_cm4.h"
#include "defs.h"
#include "string.h"
#include "interrupt.h"
#include "system_internal.h"
#endif /*_COMMON_H_*/
/** @}
*/

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/*
**********************************************************************************
* © 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
**********************************************************************************
* common.h
* This is the header file including common headers from various modules
**********************************************************************************
* $Revision: #1 $ $DateTime: 2016/09/22 08:03:49 $ $ $
* Description: added ict module
**********************************************************************************
* #xx
**********************************************************************************
* $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/common_lib.h $
*/
/*********************************************************************************/
/** @defgroup common common
* @{
*/
/** @file common.h
* \brief header file including common headers from various modules
* \author App Firmware Team
*
**********************************************************************************/
#ifndef _COMMON_LIB_H_
#define _COMMON_LIB_H_
// Include common headers from various modules
// !!! The include order is important !!!
#include "platform.h"
#include "ARM_REG.h"
#include "MCHP_device_header.h"
/* Cortex-M4 processor and core peripherals */
#include "core_cm4.h"
#include "defs.h"
#include "string.h"
#include "system_internal.h"
#include <stdbool.h>
#endif /*_COMMON_LIB_H_*/
/** @}
*/

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/*
**********************************************************************************
* © 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
**********************************************************************************
* defs.h
* This is the definition header file for generic usages
**********************************************************************************
* #xx
**********************************************************************************
* $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/defs.h $
*/
/*********************************************************************************/
/** @defgroup defs defs
* @{
*/
/** @file defs.h
* \brief definition header file for generic usages
* \author App Firmware Team
*
**********************************************************************************/
#ifndef _DEFS_H_
#define _DEFS_H_
/* bit operation MACRO, xvar could be byte, word or dword */
#define mSET_BIT(x, xvar) ( xvar |= x )
#define mCLR_BIT(x, xvar) ( xvar &= ~x )
#define mGET_BIT(x, xvar) ( xvar & x )
#define mCLR_SRC_BIT(x, xvar) ( xvar = x )
#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}
#endif /*_DEFS_H_*/
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Renamed ecia_init to interrupt_init
******************************************************************************/
/** @file interrupt_api.c
* \brief Interrupt APIs Source File
* \author jvasanth
*
* This file implements the Interrupt Source file
******************************************************************************/
/** @defgroup Interrupt
* @{
*/
#include "common_lib.h"
#include "interrupt.h"
#include "..\pcr\pcr.h"
static uint8_t interrupt_is_girq_direct(uint8_t girq_num);
/* ------------------------------------------------------------------------------- */
/* NVIC,ECIA Routing Policy for Direct Mode */
/* ------------------------------------------------------------------------------- */
/* In Direct Mode, some interrupts could be configured to be used as aggregated.
* Configuration:
* 1. Always set ECS Interrupt Direct enable bit.
* 2. If GIRQn aggregated set Block Enable bit.
* 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.
* Switching issues:
* Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.
* Also requires set/clear of individual NVIC Enables.
*
* Note: interrupt_is_girq_direct() internal function uses this policy to detect
* if any interrupt is configured as direct or aggregated
*/
/** Initialize EC Interrupt Aggregator
* @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode
* @param girq_bitmask - BitMask of GIRQ to be configured as aggregated
* This parameter is only applicable in direct mode.
* @note All GPIO's and wake capable sources are always
* aggregated! GPIO's interrupts will still work in direct mode.
* Block wakes are not be routed to the processor in direct
* mode.
* Note2: This function disables and enables global interrupt
*/
void interrupt_init(uint8_t mode, uint32_t girq_bitmask)
{
uint32_t isave;
isave = __get_PRIMASK();
__disable_irq();
//Clear Sleep for Interrupt block
pcr_sleep_enable(PCR_INT, 0);
interrupt_mode_set(mode);
p_interrupt_ecia_girqs_enable_reset();
p_interrupt_nvic_enpend_clr();
p_interrupt_nvic_priorities_default_set();
if (mode)
{//If direct mode, enable specific GIRQs to be aggregated
p_interrupt_ecia_block_enable_bitmask_set(girq_bitmask);
}
if (!isave) {
__enable_irq();
}
}
/** Set interrupt routing mode to aggregated or direct.
* @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated
* @note In direct mode, one could enable certain GIRQs as aggregated using
* p_interrupt_ecia_block_enable_set function
*/
void interrupt_mode_set(uint8_t mode)
{
if (mode)
{
p_interrupt_ecia_block_enable_all_clr();
}
else
{
p_interrupt_ecia_block_enable_all_set();
}
p_interrupt_control_set(mode);
}
/** Clears all individual interrupts Enables and Source in ECIA,
* and Clears all NVIC external enables and pending bits
*/
void interrupt_reset(void)
{
p_interrupt_ecia_girqs_enable_reset();
p_interrupt_ecia_girqs_source_reset();
p_interrupt_nvic_enpend_clr();
}
/** Enables interrupt for a device
* @param dev_iroute - source IROUTING information
* @note This function disables and enables global interrupt
*/
void interrupt_device_enable(uint32_t dev_iroute)
{
uint32_t isave;
IRQn_Type nvic_num;
uint8_t girq_num;
uint8_t ia_bitpos;
girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;
ia_bitpos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu;
if (interrupt_is_girq_direct(girq_num))
{ // GIRQ is hooked direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else
{ // GIRQ is aggregated
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
isave = __get_PRIMASK();
__disable_irq();
NVIC_EnableIRQ(nvic_num);
p_interrupt_ecia_girq_enable_set(girq_num, ia_bitpos);
__DSB();
if (!isave) {
__enable_irq();
}
}
/** Disables interrupt for a device
* @param dev_iroute - source IROUTING information
* @note This function disables and enables global interrupt
*/
void interrupt_device_disable(uint32_t dev_iroute)
{
uint32_t isave;
IRQn_Type nvic_num;
uint8_t girq_num;
uint8_t ia_bitpos;
girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;
ia_bitpos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu;
isave = __get_PRIMASK();
__disable_irq();
if (interrupt_is_girq_direct(girq_num))
{ // GIRQ is hooked direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
NVIC_DisableIRQ(nvic_num);
}
p_interrupt_ecia_girq_enable_clr(girq_num, ia_bitpos);
__DSB();
if (!isave) {
__enable_irq();
}
}
/** ecia_is_girq_direct - Return true if GIRQn sources can be directly
* connected to the NVIC - based on ECS->INTERRUPT_CONTROL and GIRQ block enable
* @param girq_num - enum MEC_GIRQ_IDS
* @return 1 if GIRQn sources can be directly routed to the NVIC, else 0
*/
static uint8_t interrupt_is_girq_direct(uint8_t girq_num)
{
uint32_t bpos;
uint8_t retVal;
uint8_t girq_block_enabled;
retVal = 0;
bpos = (girq_num & 0x1Fu) + 8u;
if ((ECIA_GIRQ_DIRECT_BITMAP) & (1ul << bpos))
{
if (p_interrupt_control_get())
{// direct NVIC enabled
girq_block_enabled = p_interrupt_ecia_block_enable_get(girq_num);
if (!girq_block_enabled)
{
retVal = 1;
}
}
}
return retVal;
}
/* ------------------------------------------------------------------------------- */
/* ECIA APIs using device IROUTE() as input */
/* ------------------------------------------------------------------------------- */
/** Clear Source in the ECIA for the device
* @param devi - device IROUTING value
*/
void interrupt_device_ecia_source_clear(const uint32_t dev_iroute)
{
uint8_t girq_num;
uint8_t ia_bit_pos;
girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;
ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu;
p_interrupt_ecia_girq_source_clr(girq_num, ia_bit_pos);
__DSB();
}
/** Get the Source bit in the ECIA for the device
* @param devi - device IROUTING value
* @return 0 if source bit not set; else non-zero value
*/
uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute)
{
uint8_t girq_num;
uint8_t ia_bit_pos;
uint8_t retVal;
girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;
ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu;
retVal = p_interrupt_ecia_girq_source_get(girq_num, ia_bit_pos);
return retVal;
}
/** Get the Result bit in the ECIA for the device
* @param devi - device IROUTING value
* @return 0 if result bit not set; else non-zero value
*/
uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute)
{
uint8_t girq_num;
uint8_t ia_bit_pos;
uint8_t retVal;
girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;
ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu;
retVal = p_interrupt_ecia_girq_result_get(girq_num, ia_bit_pos);
return retVal;
}
/* ------------------------------------------------------------------------------- */
/* NVIC APIs using device IROUTE() as input */
/* ------------------------------------------------------------------------------- */
/* Note that if the device interrupt is aggregated, then these APIs would affect the
* NVIC corresponding to the aggregated GIRQ
*/
/** Enable/Disable the NVIC (in the NVIC controller) for the device
* @param dev_iroute : source IROUTING information (encoded in a uint32_t)
* @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
* @note 1. Recommended to use interrupt_device_enable, interrupt_device_disable
* to enable/disable interrupts for the device, since those APIs configure ECIA as well
* 2. This function disables and enables global interrupt
*/
void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag)
{
uint32_t isave;
IRQn_Type nvic_num;
if (p_interrupt_control_get())
{ // direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else // fully aggregated
{
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
isave = __get_PRIMASK();
__disable_irq();
p_interrupt_nvic_enable(nvic_num, en_flag);
if (!isave) {
__enable_irq();
}
}
/** Set NVIC priority for specified peripheral interrupt
* @param dev_iroute - source IROUTING information (encoded in a uint32_t)
* @param nvic_pri - NVIC Priority
* @note If ECIA is in aggregated mode, the priority affects all interrupt
* sources in the GIRQ.
*/
void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri)
{
IRQn_Type nvic_num;
if (p_interrupt_control_get())
{ // direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else // fully aggregated
{
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
NVIC_SetPriority(nvic_num, (uint32_t)nvic_pri);
}
/** Return NVIC priority for the device's interrupt
* @param dev_iroute - source IROUTING information
* @return uint32_t NVIC priority
*/
uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute)
{
IRQn_Type nvic_num;
uint32_t nvic_priority;
if (p_interrupt_control_get())
{ // direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else // fully aggregated
{
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
nvic_priority = NVIC_GetPriority(nvic_num);
return nvic_priority;
}
/** Return NVIC pending for the device
* @param dev_iroute - source IROUTING information
* @return uint8_t 0(not pending), 1 (pending in NVIC)
*
*/
uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute)
{
IRQn_Type nvic_num;
uint8_t nvic_pending;
if (p_interrupt_control_get())
{ // direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else // fully aggregated
{
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
nvic_pending = (uint8_t)(NVIC_GetPendingIRQ(nvic_num));
return nvic_pending;
}
/** Set NVIC pending for interrupt source
* @param dev_iroute - source IROUTING information
*/
void interrupt_device_nvic_pending_set(const uint32_t dev_iroute)
{
IRQn_Type nvic_num;
if (p_interrupt_control_get())
{ // direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else // fully aggregated
{
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
NVIC_SetPendingIRQ(nvic_num);
}
/** Clears NVIC pending for interrupt source
* @param dev_iroute - source IROUTING information
* @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear
* @note This function disables and enables global interrupt
*/
uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute)
{
uint32_t was_masked;
IRQn_Type nvic_num;
uint8_t pending;
if (p_interrupt_control_get())
{ // direct
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);
}
else // fully aggregated
{
nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);
}
was_masked = __get_PRIMASK();
__disable_irq();
pending = (uint8_t)(NVIC_GetPendingIRQ(nvic_num));
NVIC_ClearPendingIRQ(nvic_num);
__DSB();
if (!was_masked) {
__enable_irq();
}
return pending;
}
/* ------------------------------------------------------------------------------- */
/* end interrupt_api.c */
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Initial Draft
******************************************************************************/
/** @file interrupt_ecia_perphl.c
* \brief Interrupt ECIA Peripheral Source File
* \author jvasanth
*
* This file implements the ECIA peripheral functions
******************************************************************************/
/** @defgroup Interrupt
* @{
*/
#include "common_lib.h"
#include "interrupt.h"
#define ECIA ((INTS_Type *) INTS_BASE)
#define ECS ((EC_REG_BANK_Type *) EC_REG_BANK_BASE)
/* ------------------------------------------------------------------------------- */
/* Operations on GIRQ Block Enable Set, Enable Clear and Status Register */
/* ------------------------------------------------------------------------------- */
/** Enable specified GIRQ in ECIA block
* @param girq_id - enum MEC_GIRQ_IDS
*/
void p_interrupt_ecia_block_enable_set(uint8_t girq_id)
{
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
ECIA->BLOCK_ENABLE_SET = (1ul << ((girq_id + 8) & 0x1Fu));
}
}
/** Enable GIRQs in ECIA Block
* @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block
*/
void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask)
{
ECIA->BLOCK_ENABLE_SET = girq_bitmask;
}
/** Check if specified GIRQ block enabled or not
* @param girq_id - enum MEC_GIRQ_IDS
* @return retVal - 1 if the particular GIRQ block enabled, else 0
*/
uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id)
{
uint8_t retVal;
retVal = 0;
if ( girq_id < (MEC_GIRQ_ID_MAX) )
{
if ((ECIA->BLOCK_ENABLE_SET) & (1ul << ((girq_id + 8) & 0x1Fu)))
{
retVal = 1;
}
}
return retVal;
}
/** Set all GIRQ block enables */
void p_interrupt_ecia_block_enable_all_set(void)
{
ECIA->BLOCK_ENABLE_SET = 0xfffffffful;
}
/** Clear specified GIRQ in ECIA Block
* @param girq_id - enum MEC_GIRQ_IDS
*/
void p_interrupt_ecia_block_enable_clr(uint8_t girq_id)
{
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
ECIA->BLOCK_ENABLE_CLEAR = (1ul << ((girq_id + 8) & 0x1Fu));
}
}
/** Clear GIRQs in ECIA Block
* @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block
*/
void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask)
{
ECIA->BLOCK_ENABLE_CLEAR = girq_bitmask;
}
/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */
void p_interrupt_ecia_block_enable_all_clr(void)
{
ECIA->BLOCK_ENABLE_CLEAR = 0xfffffffful;
}
/** Get status of GIRQ in ECIA Block
* @param girq_id - enum MEC_GIRQ_IDS
* @return 0 if status bit not set; else non-zero value
*/
uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id)
{
uint32_t retVal;
retVal = ECIA->BLOCK_IRQ_VECTOR & (1ul << ((girq_id + 8) & 0x1Fu));
return retVal;
}
/** Reads the Block IRQ Vector Register
* @return 32-bit value
*/
uint32_t p_interrupt_ecia_block_irq_all_status_get(void)
{
uint32_t retVal;
retVal = ECIA->BLOCK_IRQ_VECTOR;
return retVal;
}
/* ------------------------------------------------------------------------------- */
/* Operations on GIRQx Source, Enable, Result and Enable Registers */
/* ------------------------------------------------------------------------------- */
/** Clear specified interrupt source bit in GIRQx
* @param girq_id - enum MEC_GIRQ_IDS
* @param bitnum -[0, 31]
*/
void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum)
{
__IO uint32_t *girq_source = (uint32_t*)ECIA;
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_source += (5 * girq_id);
*girq_source |= (1ul << (bitnum & 0x1Fu));
}
}
/** Read the specified interrupt source bit in GIRQx
* @param girq_id - enum MEC_GIRQ_IDS
* @param bitnum -[0, 31]
* @return 0 if source bit not set; else non-zero value
*/
uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum)
{
uint32_t retVal;
__IO uint32_t *girq_source = (uint32_t*)ECIA;
retVal = 0;
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_source += (5 * girq_id);
retVal = (*girq_source & (1ul << (bitnum & 0x1Fu)));
}
return retVal;
}
/** Enable the specified interrupt in GIRQx
* girq_id - enum MEC_GIRQ_IDS
* bitnum = [0, 31]
*/
void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum)
{
__IO uint32_t *girq_enable_set = (uint32_t*)(&(ECIA->GIRQ08_EN_SET));
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_enable_set += (5 * girq_id);
*girq_enable_set |= (1ul << (bitnum & 0x1Fu));
}
}
/** Disable the specified interrupt in GIRQx
* girq_id - enum MEC_GIRQ_IDS
* bitnum = [0, 31]
*/
void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum)
{
__IO uint32_t *girq_enable_clr = (uint32_t*)(&(ECIA->GIRQ08_EN_CLR));
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_enable_clr += (5 * girq_id);
*girq_enable_clr |= (1ul << (bitnum & 0x1Fu));
}
}
/** Read the status of the specified interrupt in GIRQx
* girq_id - enum MEC_GIRQ_IDS
* bitnum = [0, 31]
* @return 0 if enable bit not set; else non-zero value
*/
uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum)
{
uint32_t retVal;
__IO uint32_t *girq_enable_set = (uint32_t*)(&(ECIA->GIRQ08_EN_SET));
retVal = 0;
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_enable_set += (5 * girq_id);
retVal = (*girq_enable_set & (1ul << (bitnum & 0x1Fu)));
}
return retVal;
}
/** Read the result bit of the interrupt in GIRQx
* @param girq_id - enum MEC_GIRQ_IDS
* @param bitnum -[0, 31]
* @return 0 if enable bit not set; else non-zero value
*/
uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum)
{
uint32_t retVal;
__IO uint32_t *girq_result = (uint32_t*)(&(ECIA->GIRQ08_RESULT));
retVal = 0;
if ( girq_id < (MEC_GIRQ_ID_MAX) ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_result += (5 * girq_id);
retVal = (*girq_result & (1ul << (bitnum & 0x1Fu)));
}
return retVal;
}
/* ------------------------------------------------------------------------------- */
/* Operations on all GIRQs */
/* ------------------------------------------------------------------------------- */
/** Clear all aggregator GIRQn status registers */
void p_interrupt_ecia_girqs_source_reset(void)
{
uint16_t i;
__IO uint32_t *girq_source = (uint32_t*)ECIA;
for ( i = 0u; i < (MEC_GIRQ_ID_MAX); i++ ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_source += 5;
*girq_source = 0xfffffffful;
}
}
/** Clear all aggregator GIRQn enables */
void p_interrupt_ecia_girqs_enable_reset(void)
{
uint16_t i;
__IO uint32_t *girq_enable_clr = (uint32_t*)(&(ECIA->GIRQ08_EN_CLR));
for ( i = 0u; i < (MEC_GIRQ_ID_MAX); i++ ) {
/* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED
* please refer INTS_Type in MCHP_device_internal.h
* Based on the girq id calculate the offset in the structure INTS_Type
*
* BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON
* 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES
*/
girq_enable_clr += 5;
*girq_enable_clr = 0xfffffffful;
}
}
/* ------------------------------------------------------------------------------- */
/* Function to set interrupt control */
/* ------------------------------------------------------------------------------- */
/** Set interrupt control
* @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
*/
void p_interrupt_control_set(uint8_t nvic_en_flag)
{
ECS->INTERRUPT_CONTROL = nvic_en_flag;
}
/** Read interrupt control
* @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
*/
uint8_t p_interrupt_control_get(void)
{
return (ECS->INTERRUPT_CONTROL & 0x1);
}
/* end interrupt_ecia_perphl.c */
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Initial Draft
******************************************************************************/
/** @file interrupt_nvic_perphl.c
* \brief Interrupt NVIC Peripheral Source File
* \author jvasanth
*
* This file implements the NVIC peripheral functions
******************************************************************************/
/** @defgroup Interrupt
* @{
*/
#include "common_lib.h"
#include "interrupt.h"
/* ------------------------------------------------------------------------------- */
/* NVIC Functions */
/* ------------------------------------------------------------------------------- */
/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller
* @param nvic_num : NVIC number (see enum IRQn_Type)
* @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
*/
void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag)
{
if (en_flag) {
NVIC_EnableIRQ(nvic_num);
} else {
NVIC_DisableIRQ(nvic_num);
}
__DSB();
}
/** ecia_nvic_clr_en - Clear all NVIC external enables */
void p_interrupt_nvic_extEnables_clr(void)
{
uint32_t i, m;
m = (uint32_t)(MAX_IRQn) >> 5;
if ( (uint32_t)(MAX_IRQn) & 0x1Ful ) { m++; }
for ( i = 0ul; i < m ; i++ )
{
NVIC->ICER[i] = 0xfffffffful;
}
}
/** Clear all NVIC external enables and pending bits */
void p_interrupt_nvic_enpend_clr(void)
{
uint32_t i, m;
// Clear NVIC enables & pending status
m = (uint32_t)(MAX_IRQn) >> 5;
if ( (uint32_t)(MAX_IRQn) & 0x1Ful ) { m++; }
for ( i = 0ul; i < m ; i++ )
{
NVIC->ICER[i] = 0xfffffffful;
NVIC->ICPR[i] = 0xfffffffful;
}
}
/** Set NVIC external priorities to POR value */
void p_interrupt_nvic_priorities_default_set(void)
{
uint32_t i;
// Set POR default NVIC priority (highest)
for ( i = 0ul; i < (uint32_t)MAX_IRQn; i++ ) {
NVIC->IP[i] = 0u;
}
}
/** Set NVIC external priorities to specified priority (0 - 7)
* @param zero-based 3-bit priority value: 0=highest, 7=lowest.
* @note NVIC highest priority is the value 0, lowest is all 1's.
* Each external interrupt has an 8-bit register and the priority
* is left justified in the registers. MECxxx implements 8 priority
* levels or bits [7:5] in the register. Lowest priority = 0xE0
*/
void p_interrupt_nvic_priorities_set(uint8_t new_pri)
{
uint16_t i;
for ( i = 0ul; i < MAX_IRQn; i++ ) {
NVIC_SetPriority((IRQn_Type)i, new_pri);
}
}
/* end interrupt_nvic_perphl.c */
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Updated for tabs
******************************************************************************/
/** @file pcr.h
* \brief Power, Clocks, and Resets Header file
* \author jvasanth
*
* This file is the PCR header file
******************************************************************************/
/** @defgroup PCR
* @{
*/
#ifndef _PCR_H
#define _PCR_H
/******************************************************************************/
/** PCR Register IDS
*******************************************************************************/
enum _PCR_REGSET_ID_
{
PCR_REG_SYSTEM_SLEEP_CTRL = 0,
PCR_REG_PROCESSOR_CLK_CTRL,
PCR_REG_SLOW_CLK_CTRL,
PCR_REG_OSCILLATOR_ID,
PCR_REG_PWR_RESET_STS,
PCR_REG_PWR_RESET_CTRL,
PCR_REG_SYSTEM_RESET,
PCR_TEST0,
PCR_TEST1,
PCR_REG_EC_SLEEP_ENABLE_0 = 12,
PCR_REG_EC_SLEEP_ENABLE_1,
PCR_REG_EC_SLEEP_ENABLE_2,
PCR_REG_EC_SLEEP_ENABLE_3,
PCR_REG_EC_SLEEP_ENABLE_4,
PCR_REG_EC_CLK_REQD_STS_0 = 20,
PCR_REG_EC_CLK_REQD_STS_1,
PCR_REG_EC_CLK_REQD_STS_2,
PCR_REG_EC_CLK_REQD_STS_3,
PCR_REG_EC_CLK_REQD_STS_4,
PCR_REG_EC_RESET_ENABLE_0 = 28,
PCR_REG_EC_RESET_ENABLE_1,
PCR_REG_EC_RESET_ENABLE_2,
PCR_REG_EC_RESET_ENABLE_3,
PCR_REG_EC_RESET_ENABLE_4,
};
/* ---------------------------------------------------------------------- */
// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable
//PCR register group 0 - EC 0
#define PCR0_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_0) & 0xFF) + \
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_0) & 0xFF)<<8u) + \
(((uint32_t)(PCR_REG_EC_RESET_ENABLE_0) & 0xFF)<<16u))
//PCR register group 1 - EC 1
#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_1) & 0xFF) + \
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_1) & 0xFF)<<8u) + \
(((uint32_t)(PCR_REG_EC_RESET_ENABLE_1) & 0xFF)<<16u))
//PCR register group 2 - EC 2
#define PCR2_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \
(((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))
//PCR register group 3 - EC 3
#define PCR3_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_3) & 0xFF) + \
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_3) & 0xFF)<<8u) + \
(((uint32_t)(PCR_REG_EC_RESET_ENABLE_3) & 0xFF)<<16u))
//PCR register group 4 - EC 4
#define PCR4_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_4) & 0xFF) + \
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_4) & 0xFF)<<8u) + \
(((uint32_t)(PCR_REG_EC_RESET_ENABLE_4) & 0xFF)<<16u))
//PCR0_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
#define PCR0_EC_JTAG_STAP_BITPOS (0u)
#define PCR0_EC_EFUSE_BITPOS (1u)
#define PCR0_EC_ISPI_BITPOS (2u)
//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
#define PCR1_EC_INT_BITPOS (0u)
#define PCR1_EC_PECI_BITPOS (1u)
#define PCR1_EC_TACH0_BITPOS (2u)
#define PCR1_EC_PWM0_BITPOS (4u)
#define PCR1_EC_PMC_BITPOS (5u)
#define PCR1_EC_DMA_BITPOS (6u)
#define PCR1_EC_TFDP_BITPOS (7u)
#define PCR1_EC_CPU_BITPOS (8u)
#define PCR1_EC_WDT_BITPOS (9u)
#define PCR1_EC_SMB0_BITPOS (10u)
#define PCR1_EC_TACH1_BITPOS (11u)
#define PCR1_EC_TACH2_BITPOS (12u)
#define PCR1_EC_PWM1_BITPOS (20u)
#define PCR1_EC_PWM2_BITPOS (21u)
#define PCR1_EC_PWM3_BITPOS (22u)
#define PCR1_EC_PWM4_BITPOS (23u)
#define PCR1_EC_PWM5_BITPOS (24u)
#define PCR1_EC_PWM6_BITPOS (25u)
#define PCR1_EC_PWM7_BITPOS (26u)
#define PCR1_EC_PWM8_BITPOS (27u)
#define PCR1_EC_REG_BITPOS (29u)
#define PCR1_EC_BTIMER0_BITPOS (30u)
#define PCR1_EC_BTIMER1_BITPOS (31u)
//PCR2_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
#define PCR2_EC_LPC_BITPOS (0u)
#define PCR2_EC_UART0_BITPOS (1u)
#define PCR2_EC_UART1_BITPOS (2u)
#define PCR2_EC_GLBL_CFG_BITPOS (12u)
#define PCR2_EC_ACPI_EC0_BITPOS (13u)
#define PCR2_EC_ACPI_EC1_BITPOS (14u)
#define PCR2_EC_ACPI_PM1_BITPOS (15u)
#define PCR2_EC_8042EM_BITPOS (16u)
#define PCR2_EC_MBOX_BITPOS (17u)
#define PCR2_EC_RTC_BITPOS (18u)
#define PCR2_EC_ESPI_BITPOS (19u)
#define PCR2_EC_ACPI_EC_2_BITPOS (21u)
#define PCR2_EC_ACPI_EC_3_BITPOS (22u)
#define PCR2_EC_ACPI_EC_BITPOS (23u)
#define PCR2_EC_PORT80_0_BITPOS (25u)
#define PCR2_EC_PORT80_1_BITPOS (26u)
//PCR3_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
#define PCR3_EC_ADC_BITPOS (3u)
#define PCR3_EC_PS2_0_BITPOS (5u)
#define PCR3_EC_PS2_1_BITPOS (6u)
#define PCR3_EC_PS2_2_BITPOS (7u)
#define PCR3_EC_SPI0_BITPOS (9u)
#define PCR3_EC_HTIMER_BITPOS (10u)
#define PCR3_EC_KEYSCAN_BITPOS (11u)
#define PCR3_EC_RPM_PWM_BITPOS (12u)
#define PCR3_EC_SMB1_BITPOS (13u)
#define PCR3_EC_SMB2_BITPOS (14u)
#define PCR3_EC_SMB3_BITPOS (15u)
#define PCR3_EC_LED0_BITPOS (16u)
#define PCR3_EC_LED1_BITPOS (17u)
#define PCR3_EC_LED2_BITPOS (18u)
#define PCR3_EC_BCM_BITPOS (19u)
#define PCR3_EC_SPI1_BITPOS (20u)
#define PCR3_EC_BTIMER2_BITPOS (21u)
#define PCR3_EC_BTIMER3_BITPOS (22u)
#define PCR3_EC_BTIMER4_BITPOS (23u)
#define PCR3_EC_BTIMER5_BITPOS (24u)
#define PCR3_EC_LED3_BITPOS (25u)
#define PCR3_EC_PKE_BITPOS (26u)
#define PCR3_EC_RNG_BITPOS (27u)
#define PCR3_EC_AES_BITPOS (28u)
#define PCR3_EC_HTIMER_1_BITPOS (29u)
#define PCR3_EC_C_C_TIMER_BITPOS (30u)
#define PCR3_EC_PWM9_BITPOS (31u)
//PCR4_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
#define PCR4_EC_PWM10_BITPOS (0u)
#define PCR4_EC_PWM11_BITPOS (1u)
#define PCR4_EC_CTIMER0_BITPOS (2u)
#define PCR4_EC_CTIMER1_BITPOS (3u)
#define PCR4_EC_CTIMER2_BITPOS (4u)
#define PCR4_EC_CTIMER3_BITPOS (5u)
#define PCR4_EC_RTOS_TIMER_BITPOS (6u)
#define PCR4_EC_RPM2_PWM_BITPOS (7u)
#define PCR4_EC_QMSPI_BITPOS (8u)
#define PCR4_EC_BCM_1_BITPOS (9u)
#define PCR4_EC_RC_ID0_BITPOS (10u)
#define PCR4_EC_RC_ID1_BITPOS (11u)
#define PCR4_EC_RC_ID2_BITPOS (12u)
#define PCR4_EC_PROCHOT_BITPOS (13u)
#define PCR4_EC_EEPROM_BITPOS (14u)
#define PCR4_EC_CUST_LOG_BITPOS (15u)
/*
* n = b[7:0] = PCR Reg Bit Position
* m = b[31:8] = PCRx Regs IDs
*/
//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul))
//PCRx_REGS_BIT positions
#define PCRx_REGS_POS_SLEEP_ENABLE (8u)
#define PCRx_REGS_POS_CLK_REQD_STS (16u)
#define PCRx_REGS_POS_RESET_ENABLE (24u)
/******************************************************************************/
/** PCR Block IDS.
* These IDs are used to directly refer to a block
*******************************************************************************/
typedef enum {
PCR_JTAG = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_JTAG_STAP_BITPOS & 0xFFu)),
PCR_EFUSE = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_EFUSE_BITPOS & 0xFFu)),
PCR_ISPI = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_ISPI_BITPOS & 0xFFu)),
PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)),
PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)),
PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)),
PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)),
PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)),
PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)),
PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)),
PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)),
PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)),
PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)),
PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)),
PCR_TACH2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH2_BITPOS & 0xFFu)),
PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)),
PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)),
PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)),
PCR_PWM4 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM4_BITPOS & 0xFFu)),
PCR_PWM5 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM5_BITPOS & 0xFFu)),
PCR_PWM6 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM6_BITPOS & 0xFFu)),
PCR_PWM7 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM7_BITPOS & 0xFFu)),
PCR_PWM8 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM8_BITPOS & 0xFFu)),
PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)),
PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)),
PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)),
PCR_LPC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_LPC_BITPOS & 0xFFu)),
PCR_UART0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART0_BITPOS & 0xFFu)),
PCR_UART1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART1_BITPOS & 0xFFu)),
PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_GLBL_CFG_BITPOS & 0xFFu)),
PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC0_BITPOS & 0xFFu)),
PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC1_BITPOS & 0xFFu)),
PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_PM1_BITPOS & 0xFFu)),
PCR_8042EM = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_8042EM_BITPOS & 0xFFu)),
PCR_MBOX = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_MBOX_BITPOS & 0xFFu)),
PCR_RTC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_RTC_BITPOS & 0xFFu)),
PCR_ESPI = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ESPI_BITPOS & 0xFFu)),
PCR_ACPI_EC2 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_2_BITPOS & 0xFFu)),
PCR_ACPI_EC3 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_3_BITPOS & 0xFFu)),
PCR_ACPI_EC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_BITPOS & 0xFFu)),
PCR_PORT80_0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_0_BITPOS & 0xFFu)),
PCR_PORT80_1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_1_BITPOS & 0xFFu)),
PCR_ADC = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_ADC_BITPOS & 0xFFu)),
PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_0_BITPOS & 0xFFu)),
PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_1_BITPOS & 0xFFu)),
PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_2_BITPOS & 0xFFu)),
PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI0_BITPOS & 0xFFu)),
PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_BITPOS & 0xFFu)),
PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_KEYSCAN_BITPOS & 0xFFu)),
PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RPM_PWM_BITPOS & 0xFFu)),
PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB1_BITPOS & 0xFFu)),
PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB2_BITPOS & 0xFFu)),
PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB3_BITPOS & 0xFFu)),
PCR_LED0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED0_BITPOS & 0xFFu)),
PCR_LED1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED1_BITPOS & 0xFFu)),
PCR_LED2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED2_BITPOS & 0xFFu)),
PCR_BCM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BCM_BITPOS & 0xFFu)),
PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI1_BITPOS & 0xFFu)),
PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER2_BITPOS & 0xFFu)),
PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER3_BITPOS & 0xFFu)),
PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER4_BITPOS & 0xFFu)),
PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER5_BITPOS & 0xFFu)),
PCR_LED3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED3_BITPOS & 0xFFu)),
PCR_PKE = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PKE_BITPOS & 0xFFu)),
PCR_RNG = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RNG_BITPOS & 0xFFu)),
PCR_AES = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_AES_BITPOS & 0xFFu)),
PCR_HTIMER_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_1_BITPOS & 0xFFu)),
PCR_C_C_TIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_C_C_TIMER_BITPOS & 0xFFu)),
PCR_PWM9 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PWM9_BITPOS & 0xFFu)),
PCR_PWM10 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM10_BITPOS & 0xFFu)),
PCR_PWM11 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM11_BITPOS & 0xFFu)),
PCR_CTIMER0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER0_BITPOS & 0xFFu)),
PCR_CTIMER1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER1_BITPOS & 0xFFu)),
PCR_CTIMER2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER2_BITPOS & 0xFFu)),
PCR_CTIMER3 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER3_BITPOS & 0xFFu)),
PCR_RTOS_TIMER = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RTOS_TIMER_BITPOS & 0xFFu)),
PCR_RPM2_PWM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RPM2_PWM_BITPOS & 0xFFu)),
PCR_QMSPI = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_QMSPI_BITPOS & 0xFFu)),
PCR_BCM1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_BCM_1_BITPOS & 0xFFu)),
PCR_RCID0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID0_BITPOS & 0xFFu)),
PCR_RCID1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID1_BITPOS & 0xFFu)),
PCR_RCID2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID2_BITPOS & 0xFFu)),
PCR_PROCHOT = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PROCHOT_BITPOS & 0xFFu)),
PCR_EEPROM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_EEPROM_BITPOS & 0xFFu)),
PCR_CUST_LOG = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CUST_LOG_BITPOS & 0xFFu)),
} PCR_BLK_ID;
/******************************************************************************/
/** PCR Processor ClK Divide Values
*******************************************************************************/
enum PROCESSOR_CLK_DIVIDE_VALUE
{
PCR_CPU_CLK_DIVIDE_1 = 1,
PCR_CPU_CLK_DIVIDE_2 = 2,
PCR_CPU_CLK_DIVIDE_3 = 3,
PCR_CPU_CLK_DIVIDE_4 = 4,
PCR_CPU_CLK_DIVIDE_16 = 16,
PCR_CPU_CLK_DIVIDE_48 = 48
};
/******************************************************************************/
/** System Sleep Modes
*******************************************************************************/
enum SYSTEM_SLEEP_MODES
{
SYSTEM_LIGHT_SLEEP = 0,
SYSTEM_HEAVY_SLEEP = 1,
SYSTEM_SLEEP_ALL = 4
};
/* Bitmask for Power Reset Status Register */
#define PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK (1UL<<2)
#define PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK (1UL<<3)
#define PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK (1UL<<5)
#define PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK (1UL<<6)
#define PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK (1UL<<7)
#define PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK (1UL<<10)
#define PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)
#define PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK (1UL<<12)
/* Bitmask for Processor Clock Control Register */
#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)
/* Bitmask for Power Reset Control Register */
#define PCR_PWR_RESET_CTRL_PWR_INV_BITMASK (1UL<<0)
#define PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK (1UL<<8)
/* Bitmask for OScillator ID register */
#define PCR_OSCILLATOR_ID_FOUNDARY_BITMASK (3UL<<5)
#define PCR_OSCILLATOR_ID_REVISION_BITMASK (0xFUL)
#define PCR_OSCILLATOR_ID_FOUNDARY_CHART_TSMC (0UL)
#define PCR_OSCILLATOR_ID_FOUNDARY_TSMC (0x10u)
#define PCR_OSCILLATOR_ID_FOUNDARY_CHART (0x20u)
#define PCR_OSCILLATOR_ID_FOUNDARY_GRACE (0x30u)
/* Bitmask for PKE Clock register */
#define PCR_PKE_CLOCK_REG_PKE_CLK_BITMASK (1UL<<1)
#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_BITMASK (1UL<<0)
#define PCR_PKE_CLOCK_REG_PKE_CLK_48MHZ (1UL<<1)
#define PCR_PKE_CLOCK_REG_PKE_CLK_96MHZ (0UL<<0)
#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_EN (1UL<<0)
#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_DIS (0UL<<0)
/* ---------------------------------------------------------------------- */
/* API - Functions to program Sleep Enable, CLK Reqd Status, *
* Reset Enable for a block *
* ---------------------------------------------------------------------- */
/** Sets or Clears block specific bit in PCR Sleep Enable Register
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
*/
void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
/** Get Clock Required Status for the block
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
* @return uint8_t - 1 if Clock Required Status set, else 0
*/
uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);
/** Sets or Clears Reset Enable register bit for the block
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
*/
void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
/* ---------------------------------------------------------------------- */
/* API - Functions for entering low power modes */
/* ---------------------------------------------------------------------- */
/** Instructs all blocks to sleep by setting the Sleep Enable bits */
void pcr_all_blocks_sleep(void);
/** Clears the Sleep Enable bits for all blocks */
void pcr_all_blocks_wake(void);
/** Programs required sleep mode in System Sleep Control Register
* @param sleep_mode - see enum SYSTEM_SLEEP_MODES
*/
void pcr_system_sleep(uint8_t sleep_mode);
/** Reads the value of Power Reset status register
* @param none
* @return Power Status Reg value
*/
uint16_t pcr_power_reset_status_read(void);
/** Reads the value of Power Reset control register
* @param none
* @return Power reset control Reg value
*/
uint16_t pcr_power_reset_ctrl_read(void);
/** Sets the value of PWR_INV bit to 1 or 0
* @param set_clr: 1 or 0
* @return none
*/
void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);
/** Sets the value of HOST_RESET bit to 1 or 0
* @param set_clr: 1 or 0
* @return none
*/
void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);
/** Sets the SOFT SYS RESET bit to 1
* @param none
* @return none
*/
void pcr_system_reset_set(void);
/** Writes to the PKE Clock register
* @param clock value
* @return none
*/
void pcr_pke_clock_write(uint8_t pke_clk_val);
/** Reads the PKE clock register
* @param none
* @return clock value
*/
uint8_t pcr_pke_clock_read(void);
/** Writes to the OSC cal register
* @param calibration value: 1 or 0
* @return none
*/
void pcr_osc_cal_write(uint8_t pke_clk_val);
/** Reads the osc cal register
* @param none
* @return cal value
*/
uint8_t pcr_osc_cal_read(void);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions to program and read 32-bit values *
* from PCR Registers *
* ---------------------------------------------------------------------- */
/** Write 32-bit value in the PCR Register
* @param pcr_reg_id - pcr register id
* @param value - 32-bit value
*/
void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);
/** Reads 32-bit value from the PCR Register
* @param pcr_reg_id - pcr register id
* @return value - 32-bit value
*/
uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions to set, clr and get bits in *
* PCR Registers *
* ---------------------------------------------------------------------- */
/** Sets bits in a PCR Register
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to set
*/
void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);
/** Clears bits in a PCR Register
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to clear
*/
void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);
/** Read bits in a PCR Register
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to read
* @return value - 32-bit value
*/
uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);
/** Sets or Clears bits in a PCR Register - Helper Function
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to set or clear
* @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
*/
void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);
//Functions to operate on System Sleep Control Register
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions to operate on System Sleep Control *
* Register *
* ---------------------------------------------------------------------- */
/** Writes required sleep mode in System Sleep Control Register
* @param sleep_value - System Sleep control value - [D2, D1, D0]
*/
void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);
/** Reads the System Sleep Control PCR Register
* @return value - byte 0 of the system sleep control PCR register
*/
uint8_t p_pcr_system_sleep_ctrl_read(void);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Function to program to CLK Divide Value *
* ---------------------------------------------------------------------- */
/** Writes the clock divide value in the Processor Clock Control Register
* @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
*/
void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Function to program the Slow Clock Control *
* Register *
* ---------------------------------------------------------------------- */
/** Write the slow clock divide value in the Slow Clock Control Register
* @param slow_clk_divide_value - slow clk divide value
*/
void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Function to read the Oscillator Lock Status */
/* ---------------------------------------------------------------------- */
/** Reads the Oscillator Lock status bit in the Oscillator ID Register
* @return 1 if Oscillator Lock Status bit is set, else 0
*/
uint8_t p_pcr_oscillator_lock_sts_get(void);
/** Reads the Oscillator ID Register
* @return oscillator ID value
*/
uint16_t p_pcr_oscillator_id_reg_read(void);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions to read various power status in *
* Power Reset register *
* ---------------------------------------------------------------------- */
/** Reads the VCC Reset Status bit
* in the Power Reset Status Register
* @return 1 if VCC Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_vcc_reset_sts_get(void);
/** Reads the Host Reset Status bit
* in the Power Reset Status Register
* @return 1 if Host Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_host_reset_sts_get(void);
/** Reads the VBAT Reset Status bit
* in the Power Reset Status Register
* @return 1 if VBAT Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void);
/** Clears the VBAT Reset Status bit
* in the Power Reset Status Register
*/
void p_pcr_pwr_reset_vbat_reset_sts_clr(void);
/** Reads the VTR Reset Status bit
* in the Power Reset Status Register
* @return 1 if VCC1 Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void);
/** Clears the VTR Reset Status bit
* in the Power Reset Status Register
*/
void p_pcr_chip_subsystem_vtr_reset_sts_clr(void);
/** Reads the 32K_ACTIVE status bit
* in the Chip Subsystem Power Reset Status Register
* @return 1 if 32_ACTIVE bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_32K_active_sts_get(void);
/** Reads the PCICLK_ACTIVE status bit
* in the Power Reset Status Register
* @return 1 if CICLK_ACTIVE bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void);
/** Reads the ESPICLK_ACTIVE status bit
* in the Power Reset Status Register
* @return 1 if ESPICLK_ACTIVE bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void);
/** Reads the Power status reg
* @return Power Status Reg value
*/
uint16_t p_pcr_pwr_reset_sts_get(void);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions for Power Reset Control Register */
/* ---------------------------------------------------------------------- */
/** Reads the Power Reset Control Register
* @return Power Reset Control Register value
*/
uint16_t p_pcr_pwr_reset_ctrl_read(void);
/** Set the PWR_INV bit in the Power Reset Control Register
* @param set_clr value 1 or 0
* @return none
*/
void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);
/** Set the HOST RESET SELECT bit in the Power Reset Control Register
* @param set_clr value 1 or 0
* @return none
*/
void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);
/* ---------------------------------------------------------------------- */
/* Peripheral Function - Functions for System Reset Register */
/* ---------------------------------------------------------------------- */
/** Set the SOFT_SYS_RESET bit in the System Reset Register
* @param none
* @return none
*/
void p_pcr_system_reset_set(void);
/** Set the value in PKE CLOCK Register
* @param PKE Clock value
* @return none
*/
void p_pcr_pke_clock_write(uint8_t pke_clk_val);
/** Read the value in PKE CLOCK Register
* @none
* @return PKE Clock value
*/
uint8_t p_pcr_pke_clock_read(void);
/** Set the value in Oscillator calibration Register
* @param Oscillator calibration value
* @return none
*/
void p_pcr_osc_cal_write(uint8_t osc_cal_val);
/** Read the value in Osc cal Register
* @none
* @return Osc cal value
*/
uint8_t p_pcr_osc_cal_read(void);
#endif // #ifndef _PCR_H
/* end pcr.h */
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Updated for tabs
******************************************************************************/
/** @file pcr_api.c
* \brief Power, Clocks, and Resets API Source file
* \author jvasanth
*
* This file implements the PCR APIs
******************************************************************************/
/** @defgroup PCR
* @{
*/
#include "common_lib.h"
#include "pcr.h"
/* ------------------------------------------------------------------------------- */
/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */
/* ------------------------------------------------------------------------------- */
/** Sets or Clears block specific bit in PCR Sleep Enable Register
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
*/
void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
{
uint32_t bit_mask;
uint8_t pcr_reg_id;
bit_mask = 1UL<<(pcr_block_id & 0xFFu);
pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);
p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
}
/** Get Clock Required Status for the block
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
* @return uint8_t - 1 if Clock Required Status set, else 0
*/
uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)
{
uint32_t bit_mask;
uint8_t pcr_reg_id, retVal;
bit_mask = 1UL<<(pcr_block_id & 0xFFu);
pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);
retVal = 0;
if (p_pcr_reg_get(pcr_reg_id, bit_mask))
{
retVal = 1;
}
return retVal;
}
/** Sets or Clears Reset Enable register bit for the block
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
*/
void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
{
uint32_t bit_mask;
uint8_t pcr_reg_id;
bit_mask = 1UL<<(pcr_block_id & 0xFFu);
pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);
p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
}
/* ------------------------------------------------------------------------------- */
/* Functions for entering low power modes */
/* ------------------------------------------------------------------------------- */
/** Instructs all blocks to sleep by setting the Sleep Enable bits */
void pcr_all_blocks_sleep(void)
{
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0xFFFFFFFF);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0xFFFFFFFF);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0xFFFFFFFF);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0xFFFFFFFF);
}
/** Clears the Sleep Enable bits for all blocks */
void pcr_all_blocks_wake(void)
{
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0);
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0);
}
/** Programs required sleep mode in System Sleep Control Register
* @param sleep_mode - see enum SYSTEM_SLEEP_MODES
*/
void pcr_system_sleep(uint8_t sleep_mode)
{
p_pcr_system_sleep_ctrl_write(sleep_mode);
}
/** Reads the value of Power Reset status register
* @param none
* @return Power Reset Status Reg value
*/
uint16_t pcr_power_reset_status_read(void)
{
return (p_pcr_pwr_reset_sts_get());
}
/** Reads the value of Power Reset control register
* @param none
* @return Power reset control Reg value
*/
uint16_t pcr_power_reset_ctrl_read(void)
{
return (p_pcr_pwr_reset_ctrl_read());
}
/** Sets the value of PWR_INV bit to 1 or 0
* @param set_clr: 1 or 0
* @return none
*/
void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)
{
p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(set_clr);
}
/** Sets the value of HOST_RESET bit to 1 or 0
* @param set_clr: 1 or 0
* @return none
*/
void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)
{
p_pcr_pwr_reset_ctrl_host_rst_set_clr(set_clr);
}
/** Sets the SOFT SYS RESET bit to 1
* @param none
* @return none
*/
void pcr_system_reset_set()
{
p_pcr_system_reset_set();
}
/** Writes to the PKE Clock register
* @param clock value
* @return none
*/
void pcr_pke_clock_write(uint8_t pke_clk_val)
{
p_pcr_pke_clock_write(pke_clk_val);
}
/** Reads the PKE clock register
* @param none
* @return clock value
*/
uint8_t pcr_pke_clock_read()
{
return (p_pcr_pke_clock_read());
}
/** Writes to the OSC cal register
* @param calibration value: 1 or 0
* @return none
*/
void pcr_osc_cal_write(uint8_t pke_clk_val)
{
p_pcr_osc_cal_write(pke_clk_val);
}
/** Reads the osc cal register
* @param none
* @return cal value
*/
uint8_t pcr_osc_cal_read()
{
return (p_pcr_osc_cal_read());
}
/* end pcr_api.c */
/** @}
*/

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/*****************************************************************************
* © 2015 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
******************************************************************************
Version Control Information (Perforce)
******************************************************************************
$Revision: #1 $
$DateTime: 2016/09/22 08:03:49 $
$Author: pramans $
Last Change: Updated for tabs
******************************************************************************/
/** @file pcr_perphl.c
* \brief Power, Clocks, and Resets Peripheral Source file
* \author jvasanth
*
* This file implements the PCR Peripheral functions
******************************************************************************/
/** @defgroup PCR
* @{
*/
#include "common_lib.h"
#include "pcr.h"
/* ---------------------------------------------------------------------- */
/* Generic functions to program and read 32-bit values from PCR Registers */
/* ---------------------------------------------------------------------- */
/** Writes 32-bit value in the PCR Register
* @param pcr_reg_id - pcr register id
* @param value - 32-bit value
*/
void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE);
pPCR_Reg += pcr_reg_id;
*pPCR_Reg = value;
}
/** Reads 32-bit value from the PCR Register
* @param pcr_reg_id - pcr register id
* @return value - 32-bit value
*/
uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)
{
__IO uint32_t *pPCR_Reg;
uint32_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE);
pPCR_Reg += pcr_reg_id;
retVal = *pPCR_Reg;
return retVal;
}
/* ---------------------------------------------------------------------- */
/* Functions to set, clr and get bits in PCR Registers */
/* ---------------------------------------------------------------------- */
/** Sets bits in a PCR Register
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to set
*/
void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE);
pPCR_Reg += pcr_reg_id;
*pPCR_Reg |= bit_mask;
}
/** Clears bits in a PCR Register
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to clear
*/
void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE);
pPCR_Reg += pcr_reg_id;
*pPCR_Reg &= ~bit_mask;
}
/** Read bits in a PCR Register
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to read
* @return value - 32-bit value
*/
uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)
{
__IO uint32_t *pPCR_Reg;
uint32_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE);
pPCR_Reg += pcr_reg_id;
retVal = (*pPCR_Reg) & bit_mask;
return retVal;
}
/** Sets or Clears bits in a PCR Register - Helper Function
* @param pcr_reg_id - pcr register id
* @param bit_mask - Bit mask of bits to set or clear
* @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
*/
void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)
{
if (set_clr_flag)
{
p_pcr_reg_set(pcr_reg_id, bit_mask);
}
else
{
p_pcr_reg_clr(pcr_reg_id, bit_mask);
}
}
/* ---------------------------------------------------------------------- */
/* Functions to operate on System Sleep Control Register */
/* ---------------------------------------------------------------------- */
/** Writes required sleep mode in System Sleep Control Register
* @param sleep_value - System Sleep control value (Heavy/Light/Sleep All)
*/
void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)
{
__IO uint32_t *pPCR_Reg;
/* Check for valid value */
if ((sleep_value == SYSTEM_LIGHT_SLEEP) ||
(sleep_value == SYSTEM_LIGHT_SLEEP) ||
(sleep_value == SYSTEM_LIGHT_SLEEP))
{
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
*pPCR_Reg = (sleep_value & 0x7);
}
}
/** Reads the System Sleep Control PCR Register
* @return value - byte 0 of the system sleep control PCR register
*/
uint8_t p_pcr_system_sleep_ctrl_read(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
retVal = (uint8_t)((*pPCR_Reg) & 0xFF);
return retVal;
}
/* ---------------------------------------------------------------------- */
/* Function to program to CLK Divide Value */
/* ---------------------------------------------------------------------- */
/** Writes the clock divide value in the Processor Clock Control Register
* @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
*/
void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)
{
__IO uint32_t *pPCR_Reg;
/* Check for valid value */
if (((clk_divide_value >= PCR_CPU_CLK_DIVIDE_1) &&
(clk_divide_value <= PCR_CPU_CLK_DIVIDE_4)) ||
(clk_divide_value == PCR_CPU_CLK_DIVIDE_16) ||
(clk_divide_value == PCR_CPU_CLK_DIVIDE_48))
{
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;
*pPCR_Reg = (clk_divide_value & 0xFF);
}
}
/** Writes the clock divide value in the Processor Clock Control Register
* @param none
* @ return value - clk divide value, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
*/
uint8_t p_pcr_processor_clk_ctrl_read(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;
retVal = ((uint8_t)((*pPCR_Reg) & 0xFF));
return retVal;
}
/* ---------------------------------------------------------------------- */
/* Function to program the slow clock divide value */
/* ---------------------------------------------------------------------- */
/** Write the slow clock divide value in the Slow Clock Control Register
* @param slow_clk_divide_value - slow clk divide value
*/
void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL;
*pPCR_Reg = (slow_clk_divide_value & 0x3FF);
}
/* ---------------------------------------------------------------------- */
/* Function to read the Oscillator Lock Status */
/* ---------------------------------------------------------------------- */
/** Reads the Oscillator Lock status bit in the Oscillator ID Register
* @return 1 if Oscillator Lock Status bit is set, else 0
*/
uint8_t p_pcr_oscillator_lock_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;
retVal = 0;
if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Reads the Oscillator ID Register
* @return oscillator ID value
*/
uint16_t p_pcr_oscillator_id_reg_read(void)
{
__IO uint32_t *pPCR_Reg;
uint16_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;
retVal = ((uint16_t)((*pPCR_Reg) & 0x1FFu));
return retVal;
}
/* ---------------------------------------------------------------------- */
/* Functions to read various power status in Power Reset register */
/* ---------------------------------------------------------------------- */
/** Reads the VCC PWRGD Status bit
* in the Power Reset Status Register
* @return 1 if VCC PWRGD Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_vcc_pwrdg_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Reads the Host Reset Status bit
* in the Power Reset Status Register
* @return 1 if Host Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_host_reset_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Reads the VBAT Reset Status bit
* in the Power Reset Status Register
* @return 1 if VBAT Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Clears the VBAT Reset Status bit
* in the Power Reset Status Register
*/
void p_pcr_pwr_reset_vbat_reset_sts_clr(void)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
// Write to clear
*pPCR_Reg |= PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK;
}
/** Reads the VTR Reset Status bit
* in the Power Reset Status Register
* @return 1 if VTR Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Clears the VTR Reset Status bit
* in the Power Reset Status Register
*/
void p_pcr_pwr_reset_vtr_reset_sts_clr(void)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
// Write to clear
*pPCR_Reg |= PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK;
}
/** Reads the JTAG Reset Status bit
* in the Power Reset Status Register
* @return 1 if JTAG Reset Status bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_jtag_reset_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Clears the JTAG Reset Status bit
* in the Power Reset Status Register
*/
void p_pcr_pwr_reset_jtag_reset_sts_clr(void)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
// Write to clear
*pPCR_Reg |= PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK;
}
/** Reads the 32K_ACTIVE status bit
* in the Chip Subsystem Power Reset Status Register
* @return 1 if 32_ACTIVE bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_32K_active_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Reads the PCICLK_ACTIVE status bit
* in the Power Reset Status Register
* @return 1 if PCICLK_ACTIVE bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Reads the ESPI status bit
* in the Power Reset Status Register
* @return 1 if ESPICLK_ACTIVE bit is set, else 0
*/
uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint8_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = 0;
if (*pPCR_Reg & PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK)
{
retVal = 1;
}
return retVal;
}
/** Reads the Power status reg
* @return Power Status Reg value
*/
uint16_t p_pcr_pwr_reset_sts_get(void)
{
__IO uint32_t *pPCR_Reg;
uint16_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;
retVal = (uint16_t)((*pPCR_Reg) & 0xFFF);
return (retVal);
}
/* ---------------------------------------------------------------------- */
/* Functions for Power Reset Control Register */
/* ---------------------------------------------------------------------- */
/** Reads the Power Reset Control Register
* @return Power Reset Control Register value
*/
uint16_t p_pcr_pwr_reset_ctrl_read(void)
{
__IO uint32_t *pPCR_Reg;
uint16_t retVal;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
retVal = (uint16_t)((*pPCR_Reg) & 0x1FFUL);
return retVal;
}
/** Set the PWR_INV bit in the Power Reset Control Register
* @param set_clr value 1 or 0
* @return none
*/
void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
if (set_clr)
{
*pPCR_Reg |= (PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);
}
else
{
*pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);
}
}
/** Set the HOST RESET SELECT bit in the Power Reset Control Register
* @param set_clr value 1 or 0
* @return none
*/
void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
if (set_clr)
{
*pPCR_Reg |= (PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK);
}
else
{
*pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK);
}
}
/* ---------------------------------------------------------------------- */
/* Functions for System Reset Register */
/* ---------------------------------------------------------------------- */
/** Set the SOFT_SYS_RESET bit in the System Reset Register
* @param none
* @return none
*/
void p_pcr_system_reset_set()
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_RESET;
*pPCR_Reg |= (1<<8);
}
/* ---------------------------------------------------------------------- */
/* Functions for PKE Clock Register */
/* ---------------------------------------------------------------------- */
/** Set the value in PKE CLOCK Register
* @param PKE Clock value
* @return none
*/
void p_pcr_pke_clock_write(uint8_t pke_clk_val)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0;
*pPCR_Reg = pke_clk_val;
}
/** Read the value in PKE CLOCK Register
* @none
* @return PKE Clock value
*/
uint8_t p_pcr_pke_clock_read(void)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0;
return ((uint8_t)(*pPCR_Reg & 0xFF));
}
/* ---------------------------------------------------------------------- */
/* Functions for Oscillator calibration Register */
/* ---------------------------------------------------------------------- */
/** Set the value in Oscillator calibration Register
* @param Oscillator calibration value
* @return none
*/
void p_pcr_osc_cal_write(uint8_t osc_cal_val)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1;
*pPCR_Reg = osc_cal_val;
}
/** Read the value in Osc cal Register
* @none
* @return Osc cal value
*/
uint8_t p_pcr_osc_cal_read(void)
{
__IO uint32_t *pPCR_Reg;
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1;
return ((uint8_t)(*pPCR_Reg & 0xFF));
}
/* end pcr_perphl.c */
/** @}
*/

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@ -0,0 +1,398 @@
/****************************************************************************
* © 2013 Microchip Technology Inc. and its subsidiaries.
* You may use this software and any derivatives exclusively with
* Microchip products.
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
* OF THESE TERMS.
*/
/** @defgroup pwm pwm_c_wrapper
* @{
*/
/** @file pwm_c_wrapper.cpp
\brief the pwm component C wrapper
This program is designed to allow the other C programs to be able to use this component
There are entry points for all C wrapper API implementation
<b>Platform:</b> This is ARC-based component
<b>Toolset:</b> Metaware IDE(8.5.1)
<b>Reference:</b> smsc_reusable_fw_requirement.doc */
/*******************************************************************************
* SMSC version control information (Perforce):
*
* FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/platform.h $
* REVISION: $Revision: #1 $
* DATETIME: $DateTime: 2016/09/22 08:03:49 $
* AUTHOR: $Author: pramans $
*
* Revision history (latest first):
* #xx
***********************************************************************************
*/
#ifndef _PLATFORM_H_
#define _PLATFORM_H_
#include <stdint.h>
/* Enable any one of the below flag which enables either Aggregated or Disaggregated Interrupts */
#define DISAGGREGATED_INPT_DEFINED 1
//#define AGGREGATED_INPT_DEFINED 1
/* Platform Configuration PreProcessor Conditions */
#define TOOLKEIL 1
#define TOOLPC 2
#define TOOLMW 3
#define TOOLMDK 4
#define PCLINT 9 //added to satisfy PC Lint's need for a value here
#ifdef __CC_ARM // Keil ARM MDK
#define TOOLSET TOOLMDK
#endif
#if 0
#ifdef _WIN32 //always defined by visual c++
#define TOOLSET TOOLPC
#endif
#ifdef __WIN32__ //always defined by borland
#define TOOLSET TOOLPC
#endif
#endif
#ifdef _ARC
#define TOOLSET TOOLMW // ARC Metaware
#endif
#ifndef TOOLSET
//#error "ERROR: cfg.h TOOLSET not defined!"
#endif
#if TOOLSET == TOOLMDK
#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */
#define _KEIL_ 0 /* Make 1 for Keil Compiler */
#define _PC_ 0
#define _ARC_CORE_ 0
#endif
#if TOOLSET == TOOLKEIL
#define _KEIL_ARM_ 0
#define _KEIL_ 1 /* Make 1 for Keil Compiler */
#define _PC_ 0
#define _ARC_CORE_ 0
#endif
#if TOOLSET == TOOLPC
#define _KEIL_ARM_ 0
#define _KEIL_ 0
#define _PC_ 1 /* Make 1 for PC Environment */
#define _ARC_CORE_ 0
#endif
#if TOOLSET == TOOLMW
#define _KEIL_ARM_ 0
#define _KEIL_ 0
#define _PC_ 0
#define _ARC_CORE_ 1
#endif
/* Short form for Standard Data Types */
typedef unsigned char UINT8;
typedef unsigned short UINT16;
typedef unsigned long UINT32;
typedef volatile unsigned char REG8;
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned long ULONG;
typedef unsigned char BOOL;
typedef unsigned int UINT;
/* signed types */
typedef signed char INT8;
typedef signed short INT16;
typedef signed long INT32;
typedef void VOID;
typedef volatile unsigned char VUINT8;
typedef volatile unsigned short int VUINT16;
typedef volatile unsigned long int VUINT32;
/* union types */
typedef union _BITS_8
{
UINT8 byte;
struct
{
UINT8 bit0: 1;
UINT8 bit1: 1;
UINT8 bit2: 1;
UINT8 bit3: 1;
UINT8 bit4: 1;
UINT8 bit5: 1;
UINT8 bit6: 1;
UINT8 bit7: 1;
}bit;
}BITS_8;
/* MACROS FOR Platform Portability */
/* macro for defining MMCR register */
/* add MMCRARRAY() & EXTERNMMCRARRAY() */
#if _KEIL_
#define MMCR(name,address) volatile unsigned char xdata name _at_ address
#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address
#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address
#define EXTERNMMCR(name) extern volatile unsigned char xdata name
#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[]
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name
#define SFR(name,address) sfr name = address
#define SFRBIT(name,address) sbit name = address
#define EXTERNSFR(name)
#define BITADDRESSTYPE(name) bit name
#define XDATA xdata
#define CODE code
#define DATA data
#define IDATA idata
#define INTERRUPT(x) interrupt x
#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)
#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)
#define NULLPTR (char *)(0)
#define PLATFORM_TRIM_OSC() // TODO
#define PNOP()
#define DISABLE_INTERRUPTS() sfrIE_EAbit=0
#define ENABLE_INTERRUPTS() sfrIE_EAbit=1
#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; }
#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; }
#define ATOMIC_CPU_SLEEP()
#define NUM_IRQ_VECTORS 12 // DW-8051
#define IRQ_VECTOR_SIZE 8
#define USE_INLINE_PATCHER 1
#define IRQ_VECTABLE_IN_RAM 0
#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start
#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start
#define FUNC_NEVER_RETURNS
#define BEGIN_SMALL_DATA_BLOCK(x)
#define END_SMALL_DATA_BLOCK()
UINT32 soft_norm(UINT32 val);
#define NORM(x) soft_norm(x)
//
#define USE_FUNC_REPLACEMENT 0
#endif
#if _PC_
#define MMCR(name,address) volatile unsigned char name
#define MMCRARRAY(name,length,address) volatile unsigned char name[length]
#define MMCRTYPE(name,dtype,address) volatile dtype name
#define EXTERNMMCR(name) extern volatile unsigned char name
#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name
#define SFR(name,address) volatile unsigned char name
#define SFRBIT(name,address) volatile unsigned char name
#define EXTERNSFR(name) extern volatile unsigned char name
#define BITADDRESSTYPE(name) volatile unsigned char name
#define XDATA
#define CODE
#define DATA
#define IDATA
#define INTERRUPT(x)
#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)
#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)
#define NULLPTR (char *)(0)
#define PLATFORM_TRIM_OSC() // TODO
#define PNOP()
#define DISABLE_INTERRUPTS()
#define ENABLE_INTERRUPTS()
#define SAVE_DIS_INTERRUPTS(x)
#define RESTORE_INTERRUPTS(x)
#define ATOMIC_CPU_SLEEP()
#define NUM_IRQ_VECTORS 24
#define IRQ_VECTOR_SIZE 8
#define USE_INLINE_PATCHER 1
#define IRQ_VECTABLE_IN_RAM 0
#define FUNC_NEVER_RETURNS
#define BEGIN_SMALL_DATA_BLOCK(x)
#define END_SMALL_DATA_BLOCK()
UINT32 soft_norm(UINT32 val);
#define NORM(x) soft_norm(x)
//
#define USE_FUNC_REPLACEMENT 0
#endif
#if _ARC_CORE_
// ARC C has no equivalent operator to specify address of a variable
// ARC MMCR's are 32-bit registers
#define MMCR(name,address) volatile unsigned char name
#define MMCRARRAY(name,length,address) volatile unsigned char name[length]
#define MMCRTYPE(name,dtype,address) volatile dtype name
#define EXTERNMMCR(name) extern volatile unsigned char name
#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name
#define SFR(name,address) volatile unsigned char name
#define SFRBIT(name,address) volatile unsigned char name
#define EXTERNSFR(name) extern volatile unsigned char name
#define BITADDRESSTYPE(name)
#define XDATA
#define CODE
#define DATA
#define IDATA
#define INTERRUPT(x)
#define SET_GLOBAL_INTR_ENABLE() (_enable())
#define CLR_GLOBAL_INTR_ENABLE() (_disable())
#define NULLPTR (char *)(0)
#define NULLVOIDPTR (void *)(0)
#define NULLFPTR (void (*)(void))0
#define PLATFORM_TRIM_OSC() // TODO
#define PNOP() _nop()
#define DISABLE_INTERRUPTS() _disable()
#define ENABLE_INTERRUPTS() _enable()
#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }
#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }
#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop();
#define NUM_IRQ_VECTORS 24
#define IRQ_VECTOR_SIZE 8
#define USE_INLINE_PATCHER 0
#define DCCM_CODE_ALIAS_ADDR 0x00060000
#define PLAT_ROM_IRQ_VECTOR_BASE 0
#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)
/// y #define IRQ_VECTABLE_IN_RAM 1
#define IRQ_VECTABLE_IN_RAM 0
#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)
#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)
#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()
#define NORM(x) _norm(x)
#define INLINE_FUNCTION(x) #pragma On_inline(x)
//
#define USE_FUNC_REPLACEMENT 0
#endif
#if _KEIL_ARM_
// For ARM MDK compiler
// ARM MMCR's are 32-bit registers
#define MMCR(name,address) volatile unsigned char name
#define MMCRARRAY(name,length,address) volatile unsigned char name[length]
#define MMCRTYPE(name,dtype,address) volatile dtype name
#define EXTERNMMCR(name) extern volatile unsigned char name
#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name
#define SFR(name,address) volatile unsigned char name
#define SFRBIT(name,address) volatile unsigned char name
#define EXTERNSFR(name) extern volatile unsigned char name
#define BITADDRESSTYPE(name)
#define XDATA
#define CODE
#define DATA
#define IDATA
#define INTERRUPT(x)
#define SET_GLOBAL_INTR_ENABLE() (__enable_irq())
#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq())
#define NULLPTR (char *)(0)
#define NULLVOIDPTR (void *)(0)
#define NULLFPTR (void (*)(void))0
#define PLATFORM_TRIM_OSC() // TODO
#define PNOP() __NOP()
#define DISABLE_INTERRUPTS() __disable_irq()
#define ENABLE_INTERRUPTS() __enable_irq()
#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop();
#if 0 /* need further efforts if needed */
#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }
#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }
#define NUM_IRQ_VECTORS 24
#define IRQ_VECTOR_SIZE 8
#define USE_INLINE_PATCHER 0
#define DCCM_CODE_ALIAS_ADDR 0x00060000
#define PLAT_ROM_IRQ_VECTOR_BASE 0
#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)
/// y #define IRQ_VECTABLE_IN_RAM 1
#define IRQ_VECTABLE_IN_RAM 0
#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)
#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()
#define INLINE_FUNCTION(x) #pragma On_inline(x)
#define USE_FUNC_REPLACEMENT 0
#endif
#if 0
#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)
#define NORM(x) _norm(x)
#else
/* for ARM MDK */
#define FUNC_NEVER_RETURNS
UINT32 soft_norm(UINT32 val);
#define NORM(x) soft_norm(x)
#endif
#endif
/* General Constants */
#define FALSE 0x00
#define TRUE !FALSE
#define BIT_n_MASK(n) (1U << (n))
#define BIT_0_MASK (1<<0)
#define BIT_1_MASK (1<<1)
#define BIT_2_MASK (1<<2)
#define BIT_3_MASK (1<<3)
#define BIT_4_MASK (1<<4)
#define BIT_5_MASK (1<<5)
#define BIT_6_MASK (1<<6)
#define BIT_7_MASK (1<<7)
#define BIT_8_MASK ((UINT16)1<<8)
#define BIT_9_MASK ((UINT16)1<<9)
#define BIT_10_MASK ((UINT16)1<<10)
#define BIT_11_MASK ((UINT16)1<<11)
#define BIT_12_MASK ((UINT16)1<<12)
#define BIT_13_MASK ((UINT16)1<<13)
#define BIT_14_MASK ((UINT16)1<<14)
#define BIT_15_MASK ((UINT16)1<<15)
#define BIT_16_MASK ((UINT32)1<<16)
#define BIT_17_MASK ((UINT32)1<<17)
#define BIT_18_MASK ((UINT32)1<<18)
#define BIT_19_MASK ((UINT32)1<<19)
#define BIT_20_MASK ((UINT32)1<<20)
#define BIT_21_MASK ((UINT32)1<<21)
#define BIT_22_MASK ((UINT32)1<<22)
#define BIT_23_MASK ((UINT32)1<<23)
#define BIT_24_MASK ((UINT32)1<<24)
#define BIT_25_MASK ((UINT32)1<<25)
#define BIT_26_MASK ((UINT32)1<<26)
#define BIT_27_MASK ((UINT32)1<<27)
#define BIT_28_MASK ((UINT32)1<<28)
#define BIT_29_MASK ((UINT32)1<<29)
#define BIT_30_MASK ((UINT32)1<<30)
#define BIT_31_MASK ((UINT32)1<<31)
/* For CEC application */
#define ON 1
#define OFF 0
#endif /*_PLATFORM_H_*/
/** @}
*/

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/**************************************************************************//**
* @file system_internal.c
* @brief CMSIS Device System Source File for
* Microchip ARMCM4F Device Series
* @version V1.09
* @date 27. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
* Device CMSIS header file
*/
#include "common_lib.h"
#include "MCHP_device_header.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __HSI ( 48000000UL)
#define __XTAL ( 48000000UL) /* Oscillator frequency */
/*
* Core system clock is 48MHz derived from an internal oscillator
* It may be divided down using the PCR Processor Clock Control register.
* Supported dividers are: 1, 2, 3, 4, 16, and 48.
* Power on default is 4.
*/
#define __SYSTEM_CLOCK (__XTAL)
/* !!!! Define EC_INIT_CLK_DIV for the clock divider you
* want the ARM CM4F core to run at !!!!
*/
#ifndef EC_INIT_CLK_DIV
#define EC_INIT_CLK_DIV (1u)
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
* @note Read the EC core clock divider from the PCR block's processor
* clock control register. Actual EC core frequency is 48MHz / proc_clock_control[7:0].
*/
void SystemCoreClockUpdate (void)
{
uint32_t cpu_clk_div;
SystemCoreClock = __SYSTEM_CLOCK;
cpu_clk_div = PCR->PROC_CLK_CNTRL;
if (cpu_clk_div) {
SystemCoreClock = __SYSTEM_CLOCK / cpu_clk_div;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
* @note SystemInit is usually called from early startup code before
* C/C++ library initialization. It is used for early hardware initialization
* such as clocks, FPU, debug hardware, etc.
*/
void SystemInit (void)
{
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Program device PCR Processor Clock Control divider to set the EC core clock */
PCR->PROC_CLK_CNTRL = (EC_INIT_CLK_DIV);
SystemCoreClock = ( __SYSTEM_CLOCK / (EC_INIT_CLK_DIV) );
}

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/**************************************************************************//**
* @file system_internal.h
* @brief CMSIS Device System Header File for
* Microchip ARMCM4F Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_INTERNAL_H
#define SYSTEM_INTERNAL_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#define PCR MEC2016_PCR
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_INTERNAL_H */