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Add Multicore SMP on Armv8-M ports (#1385)
* ARMv8-M: Add SMP support to CM33 NTZ non-MPU port * Enable SMP for Arm Cortex-M33 NTZ port for GCC, ArmClang, and IAR toolchains. * Add per-core scheduler/port state: critical nesting. * Introduce spinlocks and inter-core yield/wakeup (SEV/WFE) plus primary/secondary core bring-up sync. * Update PendSV (i.e., context switch assembly) for core-safe preemption and restore paths. * Extend port macros/hooks for SMP in portmacrocommon.h, single-core builds remain unchanged. * Add the SMP boot sequence along with the necessary steps to enable SMP on Armv8-M based ports. This should help developers understand the requirements and process for enabling SMP on their Armv8-M based applications. * Update the kernel checker script to accept comma separated years in the copyright header. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * Armv8-M: Copy SMP changes to all Armv8-M based ports This commit executes the `copy_files.py` python script to copy the changes applied in the previous commit (i.e., SMP changes) to all the Armv8-M based ports. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> --------- Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
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Ahmed Ismail
GitHub
parent
c5c6f1514c
commit
f965eda041
121 changed files with 15014 additions and 4213 deletions
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@ -1,8 +1,7 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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* Copyright 2024, 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -31,6 +30,8 @@
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#ifndef PORTMACROCOMMON_H
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#define PORTMACROCOMMON_H
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#include "mpu_wrappers.h"
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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@ -59,6 +60,19 @@
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#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
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#endif /* configENABLE_TRUSTZONE */
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#if ( configNUMBER_OF_CORES > 1 )
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#if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 )
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#error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port."
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#endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */
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#ifndef configCORE_ID_REGISTER
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#error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code."
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#endif /* ifndef configCORE_ID_REGISTER */
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#ifndef configWAKE_SECONDARY_CORES
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#error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores."
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#endif /* ifndef configWAKE_SECONDARY_CORES */
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#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
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/*-----------------------------------------------------------*/
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/**
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@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
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void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
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#endif /* configENABLE_PAC */
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/**
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* @brief Configures interrupt priorities.
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*/
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void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION;
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/*-----------------------------------------------------------*/
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/**
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@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
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/**
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* @brief Critical section management.
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*/
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#define portSET_INTERRUPT_MASK() ulSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x )
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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#if ( configNUMBER_OF_CORES == 1 )
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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#else /* ( configNUMBER_OF_CORES == 1 ) */
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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extern UBaseType_t vTaskEnterCriticalFromISR( void );
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extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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#define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR()
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#define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x )
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#endif /* if ( configNUMBER_OF_CORES != 1 ) */
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/*-----------------------------------------------------------*/
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/**
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@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
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/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
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* based on whether or not Mainline extension is implemented. */
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#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
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#if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
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#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
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#else
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/*-----------------------------------------------------------*/
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#if ( configNUMBER_OF_CORES > 1 )
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typedef enum
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{
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eIsrLock = 0,
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eTaskLock,
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eLockCount
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} ePortRTOSLock;
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extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ];
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extern void vPortRecursiveLock( uint8_t ucCoreID,
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ePortRTOSLock eLockNum,
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BaseType_t uxAcquire );
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extern uint8_t ucPortGetCoreID( void );
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extern void vInterruptCore( uint8_t ucCoreID );
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#define portGET_CORE_ID() ucPortGetCoreID()
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#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] )
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#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) )
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#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ )
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#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- )
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#define portMAX_CORE_COUNT ( configNUMBER_OF_CORES )
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#define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID )
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#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE )
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#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE )
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#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE )
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#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE )
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#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
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uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister );
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#endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */
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#endif
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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