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Update RISC-V IAR port to support vector mode. (#458)
* Update RISC-V IAR port to support vector mode. * uncrustify Co-authored-by: David Chalco <david@chalco.io> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>
This commit is contained in:
Ming Yue
GitHub
parent
49777e3387
commit
f789a0e790
4 changed files with 615 additions and 464 deletions
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@ -56,43 +56,27 @@
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* registers.
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*
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*/
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#if __riscv_xlen == 64
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#elif __riscv_xlen == 32
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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#include "freertos_risc_v_chip_specific_extensions.h"
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#include "portContext.h"
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/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
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definitions. */
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#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
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#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifdef portasmHAS_CLINT
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#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#define portasmHAS_MTIME portasmHAS_CLINT
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#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
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#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#define portasmHAS_MTIME portasmHAS_CLINT
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#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
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#endif
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#ifndef portasmHAS_MTIME
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#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifndef portasmHANDLE_INTERRUPT
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#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifndef portasmHAS_SIFIVE_CLINT
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#define portasmHAS_SIFIVE_CLINT 0
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#define portasmHAS_SIFIVE_CLINT 0
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#endif
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/* CSR definitions. */
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@ -101,260 +85,60 @@ definitions. */
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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/* Only the standard core registers are stored by default. Any additional
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registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
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at the top of this file. */
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#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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PUBLIC xPortStartFirstTask
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PUBLIC freertos_risc_v_trap_handler
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PUBLIC pxPortInitialiseStack
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EXTERN pxCurrentTCB
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EXTERN ulPortTrapHandler
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PUBLIC freertos_risc_v_trap_handler
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PUBLIC freertos_risc_v_exception_handler
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PUBLIC freertos_risc_v_interrupt_handler
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PUBLIC freertos_risc_v_mtimer_interrupt_handler
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EXTERN vTaskSwitchContext
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EXTERN xTaskIncrementTick
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EXTERN Timer_IRQHandler
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EXTERN pullMachineTimerCompareRegister
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EXTERN pullNextTime
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EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
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EXTERN xISRStackTop
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EXTERN portasmHANDLE_INTERRUPT
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EXTERN xTaskReturnAddress
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PUBWEAK freertos_risc_v_application_exception_handler
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PUBWEAK freertos_risc_v_application_interrupt_handler
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/*-----------------------------------------------------------*/
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SECTION `.text`:CODE:NOROOT(2)
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CODE
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freertos_risc_v_trap_handler:
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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store_x x16, 13 * portWORD_SIZE( sp )
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store_x x17, 14 * portWORD_SIZE( sp )
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store_x x18, 15 * portWORD_SIZE( sp )
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store_x x19, 16 * portWORD_SIZE( sp )
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store_x x20, 17 * portWORD_SIZE( sp )
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store_x x21, 18 * portWORD_SIZE( sp )
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store_x x22, 19 * portWORD_SIZE( sp )
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store_x x23, 20 * portWORD_SIZE( sp )
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store_x x24, 21 * portWORD_SIZE( sp )
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store_x x25, 22 * portWORD_SIZE( sp )
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store_x x26, 23 * portWORD_SIZE( sp )
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store_x x27, 24 * portWORD_SIZE( sp )
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store_x x28, 25 * portWORD_SIZE( sp )
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store_x x29, 26 * portWORD_SIZE( sp )
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store_x x30, 27 * portWORD_SIZE( sp )
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store_x x31, 28 * portWORD_SIZE( sp )
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portUPDATE_MTIMER_COMPARE_REGISTER MACRO
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load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
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csrr t0, CSR_MSTATUS /* Required for MPIE bit. */
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store_x t0, 29 * portWORD_SIZE( sp )
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#if( __riscv_xlen == 32 )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
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li t4, -1
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lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
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sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
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sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
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sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
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add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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sw t4, 0(t1) /* Store new low word of ullNextTime. */
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sw t6, 4(t1) /* Store new high word of ullNextTime. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0( t0 ) /* Write sp to first TCB member. */
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#endif /* __riscv_xlen == 32 */
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csrr a0, CSR_MCAUSE
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csrr a1, CSR_MEPC
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#if( __riscv_xlen == 64 )
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test_if_asynchronous:
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srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
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beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
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store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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handle_asynchronous:
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#if( portasmHAS_MTIME != 0 )
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test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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addi t0, x0, 1
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slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
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addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
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bne a0, t1, test_if_external_interrupt
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load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
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#if( __riscv_xlen == 32 )
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/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
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li t4, -1
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lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
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sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
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sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
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sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
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add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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sw t4, 0(t1) /* Store new low word of ullNextTime. */
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sw t6, 4(t1) /* Store new high word of ullNextTime. */
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#endif /* __riscv_xlen == 32 */
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#if( __riscv_xlen == 64 )
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/* Update the 64-bit mtimer compare match value. */
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ld t2, 0(t1) /* Load ullNextTime into t2. */
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sd t2, 0(t0) /* Store ullNextTime into compare register. */
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ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
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sd t4, 0(t1) /* Store ullNextTime. */
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#endif /* __riscv_xlen == 64 */
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load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal xTaskIncrementTick
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beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
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jal vTaskSwitchContext
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j processed_source
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test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
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addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
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#endif /* portasmHAS_MTIME */
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load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
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j processed_source
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handle_synchronous:
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addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
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store_x a1, 0( sp ) /* Save updated exception return address. */
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test_if_environment_call:
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li t0, 11 /* 11 == environment call. */
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bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
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load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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j processed_source
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is_exception:
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csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
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csrr t1, CSR_MEPC /* For viewing in the debugger only */
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csrr t2, CSR_MSTATUS
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j is_exception /* No other exceptions handled yet. */
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as_yet_unhandled:
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csrr t0, mcause /* For viewing in the debugger only. */
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j as_yet_unhandled
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processed_source:
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( t1 ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next instruction in the task to run next. */
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load_x t0, 0( sp )
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csrw CSR_MEPC, t0
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, 29 * portWORD_SIZE( sp )
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csrw CSR_MSTATUS, t0 /* Required for MPIE bit. */
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
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load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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mret
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/*-----------------------------------------------------------*/
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xPortStartFirstTask:
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#if( portasmHAS_SIFIVE_CLINT != 0 )
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/* If there is a clint then interrupts can branch directly to the FreeRTOS
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trap handler. Otherwise the interrupt controller will need to be configured
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outside of this file. */
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la t0, freertos_risc_v_trap_handler
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csrw CSR_MTVEC, t0
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#endif /* portasmHAS_CLILNT */
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load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( sp ) /* Read sp from first TCB member. */
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load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */
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addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */
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load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
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addi sp, sp, portCONTEXT_SIZE
|
||||
ret
|
||||
/* Update the 64-bit mtimer compare match value. */
|
||||
ld t2, 0(t1) /* Load ullNextTime into t2. */
|
||||
sd t2, 0(t0) /* Store ullNextTime into compare register. */
|
||||
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
|
||||
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
|
||||
sd t4, 0(t1) /* Store ullNextTime. */
|
||||
|
||||
#endif /* __riscv_xlen == 64 */
|
||||
ENDM
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
|
|
@ -369,25 +153,26 @@ xPortStartFirstTask:
|
|||
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
||||
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
||||
*
|
||||
* Register ABI Name Description Saver
|
||||
* x0 zero Hard-wired zero -
|
||||
* x1 ra Return address Caller
|
||||
* x2 sp Stack pointer Callee
|
||||
* x3 gp Global pointer -
|
||||
* x4 tp Thread pointer -
|
||||
* x5-7 t0-2 Temporaries Caller
|
||||
* x8 s0/fp Saved register/Frame pointer Callee
|
||||
* x9 s1 Saved register Callee
|
||||
* x10-11 a0-1 Function Arguments/return values Caller
|
||||
* x12-17 a2-7 Function arguments Caller
|
||||
* x18-27 s2-11 Saved registers Callee
|
||||
* x28-31 t3-6 Temporaries Caller
|
||||
* Register ABI Name Description Saver
|
||||
* x0 zero Hard-wired zero -
|
||||
* x1 ra Return address Caller
|
||||
* x2 sp Stack pointer Callee
|
||||
* x3 gp Global pointer -
|
||||
* x4 tp Thread pointer -
|
||||
* x5-7 t0-2 Temporaries Caller
|
||||
* x8 s0/fp Saved register/Frame pointer Callee
|
||||
* x9 s1 Saved register Callee
|
||||
* x10-11 a0-1 Function Arguments/return values Caller
|
||||
* x12-17 a2-7 Function arguments Caller
|
||||
* x18-27 s2-11 Saved registers Callee
|
||||
* x28-31 t3-6 Temporaries Caller
|
||||
*
|
||||
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
||||
* where the global and thread pointers are currently assumed to be constant so
|
||||
* are not saved:
|
||||
*
|
||||
* mstatus
|
||||
* xCriticalNesting
|
||||
* x31
|
||||
* x30
|
||||
* x29
|
||||
|
|
@ -420,29 +205,189 @@ xPortStartFirstTask:
|
|||
* pxCode
|
||||
*/
|
||||
pxPortInitialiseStack:
|
||||
csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
|
||||
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
|
||||
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
||||
slli t1, t1, 4
|
||||
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
||||
|
||||
csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
|
||||
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
|
||||
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
||||
slli t1, t1, 4
|
||||
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
||||
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
store_x t0, 0(a0) /* mstatus onto the stack. */
|
||||
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
||||
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||
beq t0, x0, no_more_regs /* No more chip specific registers to save. */
|
||||
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
store_x t0, 0(a0) /* mstatus onto the stack. */
|
||||
addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
|
||||
store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
|
||||
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||
load_x t0, xTaskReturnAddress
|
||||
store_x t0, 0(a0) /* Return address onto the stack. */
|
||||
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||
beq t0, x0, no_more_regs /* No more chip specific registers to save. */
|
||||
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||
no_more_regs:
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||
ret
|
||||
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||
ret
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
xPortStartFirstTask:
|
||||
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||
load_x sp, 0( sp ) /* Read sp from first TCB member. */
|
||||
|
||||
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
|
||||
|
||||
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||
|
||||
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||
|
||||
load_x x5, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
|
||||
load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
|
||||
store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
|
||||
|
||||
load_x x5, 30 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
|
||||
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
|
||||
csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */
|
||||
|
||||
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
|
||||
load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
|
||||
|
||||
addi sp, sp, portCONTEXT_SIZE
|
||||
ret
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
freertos_risc_v_application_exception_handler:
|
||||
csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
|
||||
csrr t1, CSR_MEPC /* For viewing in the debugger only */
|
||||
csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
|
||||
j $
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
freertos_risc_v_application_interrupt_handler:
|
||||
csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
|
||||
csrr t1, CSR_MEPC /* For viewing in the debugger only */
|
||||
csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
|
||||
j $
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SECTION `.text.freertos_risc_v_exception_handler`:CODE:NOROOT(2)
|
||||
CODE
|
||||
|
||||
freertos_risc_v_exception_handler:
|
||||
portcontextSAVE_EXCEPTION_CONTEXT
|
||||
/* a0 now contains mcause. */
|
||||
li t0, 11 /* 11 == environment call. */
|
||||
bne a0, t0, other_exception /* Not an M environment call, so some other exception. */
|
||||
call vTaskSwitchContext
|
||||
portcontextRESTORE_CONTEXT
|
||||
|
||||
other_exception:
|
||||
call freertos_risc_v_application_exception_handler
|
||||
portcontextRESTORE_CONTEXT
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SECTION `.text.freertos_risc_v_interrupt_handler`:CODE:NOROOT(2)
|
||||
CODE
|
||||
|
||||
freertos_risc_v_interrupt_handler:
|
||||
portcontextSAVE_INTERRUPT_CONTEXT
|
||||
call freertos_risc_v_application_interrupt_handler
|
||||
portcontextRESTORE_CONTEXT
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SECTION `.text.freertos_risc_v_mtimer_interrupt_handler`:CODE:NOROOT(2)
|
||||
CODE
|
||||
|
||||
freertos_risc_v_mtimer_interrupt_handler:
|
||||
portcontextSAVE_INTERRUPT_CONTEXT
|
||||
portUPDATE_MTIMER_COMPARE_REGISTER
|
||||
call xTaskIncrementTick
|
||||
beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
|
||||
call vTaskSwitchContext
|
||||
exit_without_context_switch:
|
||||
portcontextRESTORE_CONTEXT
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
SECTION `.text.freertos_risc_v_trap_handler`:CODE:NOROOT(8)
|
||||
CODE
|
||||
|
||||
freertos_risc_v_trap_handler:
|
||||
portcontextSAVE_CONTEXT_INTERNAL
|
||||
|
||||
csrr a0, CSR_MCAUSE
|
||||
csrr a1, CSR_MEPC
|
||||
|
||||
bge a0, x0, synchronous_exception
|
||||
|
||||
asynchronous_interrupt:
|
||||
store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
|
||||
load_x sp, xISRStackTop /* Switch to ISR stack. */
|
||||
j handle_interrupt
|
||||
|
||||
synchronous_exception:
|
||||
addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
|
||||
store_x a1, 0( sp ) /* Save updated exception return address. */
|
||||
load_x sp, xISRStackTop /* Switch to ISR stack. */
|
||||
j handle_exception
|
||||
|
||||
handle_interrupt:
|
||||
#if( portasmHAS_MTIME != 0 )
|
||||
|
||||
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
|
||||
addi t0, x0, 1
|
||||
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
|
||||
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
|
||||
bne a0, t1, application_interrupt_handler
|
||||
|
||||
portUPDATE_MTIMER_COMPARE_REGISTER
|
||||
call xTaskIncrementTick
|
||||
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
|
||||
call vTaskSwitchContext
|
||||
j processed_source
|
||||
|
||||
#endif /* portasmHAS_MTIME */
|
||||
|
||||
application_interrupt_handler:
|
||||
call freertos_risc_v_application_interrupt_handler
|
||||
j processed_source
|
||||
|
||||
handle_exception:
|
||||
/* a0 contains mcause. */
|
||||
li t0, 11 /* 11 == environment call. */
|
||||
bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */
|
||||
call vTaskSwitchContext
|
||||
j processed_source
|
||||
|
||||
application_exception_handler:
|
||||
call freertos_risc_v_application_exception_handler
|
||||
j processed_source /* No other exceptions handled yet. */
|
||||
|
||||
processed_source:
|
||||
portcontextRESTORE_CONTEXT
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue