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Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.
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@ -38,6 +38,7 @@
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* main_full.c.
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*/
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.align( 8 )
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vRegTest1Implementation:
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/* Fill the core registers with known values. */
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@ -144,13 +145,15 @@ reg1_loop:
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reg1_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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// ebreak
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ebreak
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jal reg1_error_loop
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.align( 16 )
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ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
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/*-----------------------------------------------------------*/
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.align( 8 )
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vRegTest2Implementation:
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/* Fill the core registers with known values. */
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@ -254,9 +257,10 @@ Reg2_loop:
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reg2_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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// ebreak
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ebreak
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jal reg2_error_loop
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.align( 16 )
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ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
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@ -47,6 +47,8 @@
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* The register check tasks are described in the comments at the top of
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* main_full.c.
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*/
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.align( 8 )
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vRegTest1Implementation:
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/* Fill the additional registers with known values. */
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@ -191,10 +193,12 @@ reg1_error_loop:
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ebreak
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jal reg1_error_loop
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.align( 16 )
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ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
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/*-----------------------------------------------------------*/
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.align( 8 )
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vRegTest2Implementation:
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/* Fill the additional registers with known values. */
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@ -336,6 +340,7 @@ reg2_error_loop:
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ebreak
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jal reg2_error_loop
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.align( 16 )
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ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
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@ -58,7 +58,7 @@
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/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
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or 0 to run the more comprehensive test and demo application. */
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#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
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#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
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/* Index to first HART (there is only one). */
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#define mainHART_0 0
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