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Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.

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This commit is contained in:
Richard Barry 2019-10-14 00:16:25 +00:00
parent 96e61a10a5
commit f6edf4adf9
3 changed files with 12 additions and 3 deletions
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5
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
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@ -47,6 +47,8 @@
* The register check tasks are described in the comments at the top of
* main_full.c.
*/
.align( 8 )
vRegTest1Implementation:
/* Fill the additional registers with known values. */
@ -191,10 +193,12 @@ reg1_error_loop:
ebreak
jal reg1_error_loop
.align( 16 )
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
/*-----------------------------------------------------------*/
.align( 8 )
vRegTest2Implementation:
/* Fill the additional registers with known values. */
@ -336,6 +340,7 @@ reg2_error_loop:
ebreak
jal reg2_error_loop
.align( 16 )
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter