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Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.

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This commit is contained in:
Richard Barry 2019-10-14 00:16:25 +00:00
parent 96e61a10a5
commit f6edf4adf9
3 changed files with 12 additions and 3 deletions
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8
FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
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@ -38,6 +38,7 @@
* main_full.c.
*/
.align( 8 )
vRegTest1Implementation:
/* Fill the core registers with known values. */
@ -144,13 +145,15 @@ reg1_loop:
reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
// ebreak
ebreak
jal reg1_error_loop
.align( 16 )
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
/*-----------------------------------------------------------*/
.align( 8 )
vRegTest2Implementation:
/* Fill the core registers with known values. */
@ -254,9 +257,10 @@ Reg2_loop:
reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
// ebreak
ebreak
jal reg2_error_loop
.align( 16 )
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter