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A little optimisation.
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@ -167,19 +167,6 @@ extern void *pxCurrentTCB;
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}
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}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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void vPortYield( void )
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{
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unsigned portLONG ulStatus;
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SetCoreSW0();
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/* Unmask all interrupts. */
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ulStatus = _CP0_GET_STATUS();
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ulStatus &= ~portALL_IPL_BITS;
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_CP0_SET_STATUS( ulStatus );
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}
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/*-----------------------------------------------------------*/
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void vPortIncrementTick( void )
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void vPortIncrementTick( void )
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{
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{
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unsigned portBASE_TYPE uxSavedStatus;
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unsigned portBASE_TYPE uxSavedStatus;
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@ -51,7 +51,6 @@
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#include <sys/asm.h>
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#include <sys/asm.h>
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#include "ISR_Support.h"
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#include "ISR_Support.h"
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#define portEXC_CODE_MASK ( 0x1f << 2 )
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.set nomips16
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.set nomips16
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.set noreorder
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.set noreorder
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@ -138,10 +137,9 @@ vPortYieldISR:
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la sp, xISRStackTop
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la sp, xISRStackTop
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lw sp, (sp)
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lw sp, (sp)
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/* Increment and save the nesting count in case this gets preempted. */
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/* Set the nesting count. */
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la k0, uxInterruptNesting
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la k0, uxInterruptNesting
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lw s6, (k0)
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addiu s6, zero, 1
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addiu s6, s6, 1
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sw s6, 0(k0)
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sw s6, 0(k0)
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/* s6 holds the EPC value, this is saved with the rest of the context
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/* s6 holds the EPC value, this is saved with the rest of the context
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@ -261,11 +259,10 @@ vPortYieldISR:
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/* Protect access to the k registers, and others. */
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/* Protect access to the k registers, and others. */
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di
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di
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/* Decrement the nesting count. */
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/* Set nesting back to zero. As the lowest priority interrupt this
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interrupt cannot have nested. */
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la k0, uxInterruptNesting
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la k0, uxInterruptNesting
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lw k1, (k0)
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sw zero, 0(k0)
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addiu k1, k1, -1
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sw k1, 0(k0)
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/* Switch back to use the real stack pointer. */
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/* Switch back to use the real stack pointer. */
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add sp, zero, s5
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add sp, zero, s5
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@ -273,8 +270,7 @@ vPortYieldISR:
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/* Restore the real s5 value. */
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/* Restore the real s5 value. */
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lw s5, 40(sp)
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lw s5, 40(sp)
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/* If the critical nesting is not zero and a yield is not pended
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/* Pop the status and epc values. */
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then set status as if within a critical section. */
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lw k1, portSTATUS_STACK_LOCATION(sp)
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lw k1, portSTATUS_STACK_LOCATION(sp)
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lw k0, portEPC_STACK_LOCATION(sp)
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lw k0, portEPC_STACK_LOCATION(sp)
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@ -94,6 +94,7 @@ extern "C" {
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/* Critical section management. */
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/* Critical section management. */
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#define portIPL_SHIFT ( 10 )
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#define portIPL_SHIFT ( 10 )
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#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )
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#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )
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#define portSW0_BIT ( 0x01 << 8 )
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#define portDISABLE_INTERRUPTS() \
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#define portDISABLE_INTERRUPTS() \
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{ \
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{ \
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@ -130,8 +131,17 @@ extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE );
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Task utilities. */
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/* Task utilities. */
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extern void vPortYield( void );
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#define portYIELD() vPortYield()
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#define portYIELD() \
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{ \
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unsigned portLONG ulStatus; \
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\
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/* Unmask all interrupts. */ \
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ulStatus = _CP0_GET_CAUSE(); \
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ulStatus |= portSW0_BIT; \
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_CP0_SET_CAUSE( ulStatus ); \
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}
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#define portNOP() asm volatile ( "nop" )
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#define portNOP() asm volatile ( "nop" )
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