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Add FreeRTOS-Plus directory.
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Richard Barry
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6798 changed files with 134949 additions and 19 deletions
236
FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
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236
FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
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/*
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FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong? *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, training, latest information,
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license and contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool.
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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the code with commercial support, indemnification, and middleware, under
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the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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provide a safety engineered and independently SIL3 certified version under
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the SafeRTOS brand: http://www.SafeRTOS.com.
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*/
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.extern pxCurrentTCB
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.extern vTaskISRHandler
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.extern vTaskSwitchContext
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.extern uxCriticalNesting
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.extern pulISRStack
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.global __FreeRTOS_interrupt_handler
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.global VPortYieldASM
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.global vStartFirstTask
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.macro portSAVE_CONTEXT
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/* Make room for the context on the stack. */
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addik r1, r1, -132
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/* Save r31 so it can then be used. */
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swi r31, r1, 4
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/* Copy the msr into r31 - this is stacked later. */
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mfs r31, rmsr
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/* Stack general registers. */
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swi r30, r1, 12
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swi r29, r1, 16
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swi r28, r1, 20
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swi r27, r1, 24
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swi r26, r1, 28
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swi r25, r1, 32
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swi r24, r1, 36
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swi r23, r1, 40
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swi r22, r1, 44
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swi r21, r1, 48
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swi r20, r1, 52
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swi r19, r1, 56
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swi r18, r1, 60
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swi r17, r1, 64
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swi r16, r1, 68
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swi r15, r1, 72
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swi r13, r1, 80
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swi r12, r1, 84
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swi r11, r1, 88
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swi r10, r1, 92
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swi r9, r1, 96
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swi r8, r1, 100
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swi r7, r1, 104
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swi r6, r1, 108
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swi r5, r1, 112
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swi r4, r1, 116
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swi r3, r1, 120
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swi r2, r1, 124
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/* Stack the critical section nesting value. */
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lwi r3, r0, uxCriticalNesting
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swi r3, r1, 128
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/* Save the top of stack value to the TCB. */
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lwi r3, r0, pxCurrentTCB
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sw r1, r0, r3
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.endm
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.macro portRESTORE_CONTEXT
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/* Load the top of stack value from the TCB. */
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lwi r3, r0, pxCurrentTCB
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lw r1, r0, r3
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/* Restore the general registers. */
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lwi r31, r1, 4
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lwi r30, r1, 12
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lwi r29, r1, 16
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lwi r28, r1, 20
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lwi r27, r1, 24
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lwi r26, r1, 28
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lwi r25, r1, 32
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lwi r24, r1, 36
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lwi r23, r1, 40
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lwi r22, r1, 44
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lwi r21, r1, 48
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lwi r20, r1, 52
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lwi r19, r1, 56
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lwi r18, r1, 60
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lwi r17, r1, 64
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lwi r16, r1, 68
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lwi r15, r1, 72
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lwi r14, r1, 76
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lwi r13, r1, 80
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lwi r12, r1, 84
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lwi r11, r1, 88
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lwi r10, r1, 92
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lwi r9, r1, 96
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lwi r8, r1, 100
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lwi r7, r1, 104
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lwi r6, r1, 108
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lwi r5, r1, 112
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lwi r4, r1, 116
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lwi r2, r1, 124
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/* Load the critical nesting value. */
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lwi r3, r1, 128
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swi r3, r0, uxCriticalNesting
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/* Obtain the MSR value from the stack. */
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lwi r3, r1, 8
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/* Are interrupts enabled in the MSR? If so return using an return from
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interrupt instruction to ensure interrupts are enabled only once the task
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is running again. */
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andi r3, r3, 2
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beqid r3, 36
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or r0, r0, r0
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/* Reload the rmsr from the stack, clear the enable interrupt bit in the
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value before saving back to rmsr register, then return enabling interrupts
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as we return. */
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lwi r3, r1, 8
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andi r3, r3, ~2
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mts rmsr, r3
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lwi r3, r1, 120
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addik r1, r1, 132
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rtid r14, 0
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or r0, r0, r0
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/* Reload the rmsr from the stack, place it in the rmsr register, and
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return without enabling interrupts. */
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lwi r3, r1, 8
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mts rmsr, r3
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lwi r3, r1, 120
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addik r1, r1, 132
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rtsd r14, 0
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or r0, r0, r0
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.endm
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.text
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.align 2
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__FreeRTOS_interrupt_handler:
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portSAVE_CONTEXT
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/* Entered via an interrupt so interrupts must be enabled in msr. */
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ori r31, r31, 2
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/* Stack msr. */
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swi r31, r1, 8
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/* Stack the return address. As we entered via an interrupt we do
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not need to modify the return address prior to stacking. */
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swi r14, r1, 76
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/* Now switch to use the ISR stack. */
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lwi r3, r0, pulISRStack
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add r1, r3, r0
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bralid r15, vTaskISRHandler
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or r0, r0, r0
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portRESTORE_CONTEXT
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VPortYieldASM:
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portSAVE_CONTEXT
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/* Stack msr. */
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swi r31, r1, 8
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/* Modify the return address so we return to the instruction after the
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exception. */
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addi r14, r14, 8
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swi r14, r1, 76
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/* Now switch to use the ISR stack. */
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lwi r3, r0, pulISRStack
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add r1, r3, r0
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bralid r15, vTaskSwitchContext
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or r0, r0, r0
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portRESTORE_CONTEXT
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vStartFirstTask:
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portRESTORE_CONTEXT
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