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Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
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113
FreeRTOS/Demo/MicroBlaze/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "xparameters.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 100000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 5 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

186
FreeRTOS/Demo/MicroBlaze/ParTest/ParTest.c Normal file
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/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
/* Kernel includes. */
#include "FreeRTOS.h"
/* Demo application includes. */
#include "partest.h"
/* Library includes. */
#include "xgpio_l.h"
/* Misc hardware specific definitions. */
#define partstALL_AS_OUTPUT 0x00
#define partstCHANNEL_1 0x01
#define partstMAX_4BIT_LED 0x03
/* The outputs are split into two IO sections, these variables maintain the
current value of either section. */
static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit;
/*-----------------------------------------------------------*/
/*
* Setup the IO for the LED outputs.
*/
void vParTestInitialise( void )
{
/* Set both sets of LED's on the demo board to outputs. */
XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );
/* Start with all outputs off. */
uxCurrentOutput4Bit = 0;
XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 );
uxCurrentOutput5Bit = 0;
XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
portENTER_CRITICAL();
{
/* Which IO section does the LED being set/cleared belong to? The
4 bit or 5 bit outputs? */
if( uxLED <= partstMAX_4BIT_LED )
{
uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;
puxCurrentValue = &uxCurrentOutput4Bit;
}
else
{
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
puxCurrentValue = &uxCurrentOutput5Bit;
uxLED -= partstMAX_4BIT_LED;
}
/* Setup the bit mask accordingly. */
uxLED = 0x01 << uxLED;
/* Maintain the current output value. */
if( xValue )
{
*puxCurrentValue |= uxLED;
}
else
{
*puxCurrentValue &= ~uxLED;
}
/* Write the value to the port. */
XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
}
portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;
portENTER_CRITICAL();
{
/* Which IO section does the LED being toggled belong to? The
4 bit or 5 bit outputs? */
if( uxLED <= partstMAX_4BIT_LED )
{
uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;
puxCurrentValue = &uxCurrentOutput4Bit;
}
else
{
uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;
puxCurrentValue = &uxCurrentOutput5Bit;
uxLED -= partstMAX_4BIT_LED;
}
/* Setup the bit mask accordingly. */
uxLED = 0x01 << uxLED;
/* Maintain the current output value. */
if( *puxCurrentValue & uxLED )
{
*puxCurrentValue &= ~uxLED;
}
else
{
*puxCurrentValue |= uxLED;
}
/* Write the value to the port. */
XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );
}
portEXIT_CRITICAL();
}

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FreeRTOS/Demo/MicroBlaze/__xps/bitinit.opt Normal file
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-pe microblaze_0 RTOSDemo/executable.elf

1
FreeRTOS/Demo/MicroBlaze/__xps/libgen.opt Normal file
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-p virtex4

1
FreeRTOS/Demo/MicroBlaze/__xps/platgen.opt Normal file
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-p virtex4 -lang vhdl -st xst

23
FreeRTOS/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt Normal file
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microblaze_0
RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c
RTOSDEMO_HEADERS = FreeRTOSConfig.h
RTOSDEMO_CC = mb-gcc
RTOSDEMO_CC_SIZE = mb-size
RTOSDEMO_CC_OPT = -Os
RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall
RTOSDEMO_CC_SEARCH = # -B
RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L
RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze
RTOSDEMO_LFLAGS = # -l
RTOSDEMO_CC_PREPROC_FLAG = # -Wp,
RTOSDEMO_CC_ASM_FLAG = # -Wa,
RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map
RTOSDEMO_LINKER_SCRIPT =
RTOSDEMO_CC_DEBUG_FLAG = -g
RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt
RTOSDEMO_MODE = executable
RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0
RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul
RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=
RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=
$(RTOSDEMO_CC_SOFTMUL_FLAG) \

1
FreeRTOS/Demo/MicroBlaze/__xps/simgen.opt Normal file
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-p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti

23
FreeRTOS/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt Normal file
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microblaze_0
TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xuartlite_selftest_example.c
TESTAPP_PERIPHERAL_HEADERS =
TESTAPP_PERIPHERAL_CC = mb-gcc
TESTAPP_PERIPHERAL_CC_SIZE = mb-size
TESTAPP_PERIPHERAL_CC_OPT = -O2
TESTAPP_PERIPHERAL_CFLAGS =
TESTAPP_PERIPHERAL_CC_SEARCH = # -B
TESTAPP_PERIPHERAL_LIBPATH = -L./microblaze_0/lib/ # -L
TESTAPP_PERIPHERAL_INCLUDES = -I./microblaze_0/include/ # -I
TESTAPP_PERIPHERAL_LFLAGS = # -l
TESTAPP_PERIPHERAL_CC_PREPROC_FLAG = # -Wp,
TESTAPP_PERIPHERAL_CC_ASM_FLAG = # -Wa,
TESTAPP_PERIPHERAL_CC_LINKER_FLAG = # -Wl,
TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr
TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g
TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -mxl-gp-opt
TESTAPP_PERIPHERAL_MODE = executable
TESTAPP_PERIPHERAL_LIBG_OPT = -$(TESTAPP_PERIPHERAL_MODE) microblaze_0
TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG= -mno-xl-soft-mul
TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=
TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=
$(TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG) \

1
FreeRTOS/Demo/MicroBlaze/__xps/vpgen.opt Normal file
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-p xc4vfx12ff668-10

1
FreeRTOS/Demo/MicroBlaze/__xps/xpsxflow.opt Normal file
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-device xc4vfx12ff668-10

7
FreeRTOS/Demo/MicroBlaze/_impact.cmd Normal file
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setMode -bs
setCable -port auto
identify
identifyMPM
setAttribute -position 3 -attr configFileName -value "implementation/download.bit"
program -p 3
quit

126
FreeRTOS/Demo/MicroBlaze/crt0.s Normal file
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###################################-*-asm*-
#
# Copyright (c) 2001 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc. CONFIDENTIAL
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# crt0.s
#
# C RunTime:
# Used for initialization of small data
# anchors and stack for programs compiled using
# Xilinx Gnu Tools. This routine also intializes the
# exception and interrupt handlers
#
# $Id: crt0.s,v 1.1.4.2 2005/05/26 21:50:39 vasanth Exp $
#
#######################################
/* Vector map (Interrupts, Exceptions, Breakpoints) */
# # 0x00 # Jump to Start
# # 0x04 # nop
# # 0x08 # Imm instr for soft exception address [Hi halfword]
# # 0x0c # Jump to sof Exception handler [Lo halfword]
# # 0x10 # Imm instr for interrupt address [Hi halfword]
# # 0x14 # Jump to interrupt handler [Lo halfword]
# # 0x18 # nop - Reserved for breakpoint vector
# # 0x1C # nop - Reserved for breakpoint vector
# # 0x20 # Imm instr for hw exception address [Hi halfword]
# # 0x24 # Jump instr to hw exception handler [Lo halfword]
.globl _start
/* Set the exception and interrupt address vectors */
/* to jump to the appropriate handlers */
.align 2
.ent _start
_start:
bri _start1 # 0x00
nop # 0x04
nop # 0x08 # Reserve space for software exception vector
nop # 0x0c
nop # 0x10 # Reserve space for interrupt vector
nop # 0x14
nop # 0x18 # Reserve space for breakpoint vector
nop # 0x1c
nop # 0x18 # Reserve space for hw exception vector
nop # 0x1c
_start1:
/* Set the Small Data Anchors and the Stack pointer */
la r13, r0, _SDA_BASE_
la r2, r0, _SDA2_BASE_
la r1, r0, _stack-16 # 16 bytes (4 words are needed by
# crt for args and link reg )
/* Set the opcodes brai and imm for handlers */
la r6,r0,0xb8080000 # [opcode for brai ]
swi r6,r0,0x4 # [brai opcode for reset]
swi r6,r0,0xc # [brai opcode for exception]
swi r6,r0,0x14 # [brai opcode for interrupt]
swi r6,r0,0x24 # [brai opcode for hw exceptions]
la r6,r0,0xb0000000 # [opcode for imm ]
swi r6,r0,0x0 # [imm opcode for reset]
swi r6,r0,0x8 # [imm opcode for exception]
swi r6,r0,0x10 # [imm opocde for interrupt]
swi r6,r0,0x20 # [imm opocde for hw exceptions]
/* Set Reset vector */
la r6,r0,_start1
sw r6,r1,r0
lhu r7,r1,r0
shi r7,r0, 0x2 # [imm for reset]
shi r6,r0, 0x6 # [lower half for reset]
/* Set Software Exception Handler */
la r6,r0,_exception_handler
sw r6,r1,r0
lhu r7,r1,r0
shi r7,r0, 0xa # [imm for exception]
shi r6,r0, 0xe # [lower half for exception ]
/* Set Interrupt Handler */
la r6,r0,_interrupt_handler
sw r6,r1,r0
lhu r7,r1,r0
shi r7,r0, 0x12 # [imm for exception]
shi r6,r0, 0x16 # [lower half for intterupt ]
/* Set HW Exception Handler */
la r6,r0,_hw_exception_handler
sw r6,r1,r0
lhu r7,r1,r0
shi r7,r0, 0x22 # [imm for exception]
shi r6,r0, 0x26 # [lower half for hw exception]
/* initialize bss sections */
brlid r15,_crtinit
nop
/* Adjust the stack pointer */
addi r1,r1,16
/* Fall through to exit */
.end _start
/* Use this exit function */
.globl exit # exit library call
.ent exit
exit:
bri exit
.end exit

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FreeRTOS/Demo/MicroBlaze/data/system.ucf Normal file
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############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################
Net sys_clk_pin LOC=AE14;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=D6;
Net sys_rst_pin PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
## FPGA pin constraints
Net fpga_0_RS232_Uart_RX_pin LOC=W2;
Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_Uart_TX_pin LOC=W1;
Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;

21
FreeRTOS/Demo/MicroBlaze/etc/bitgen.ut Normal file
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-g ConfigRate:4
-g CclkPin:PULLUP
-g TdoPin:PULLNONE
-g M1Pin:PULLDOWN
-g DonePin:PULLUP
-g DriveDone:No
-g StartUpClk:JTAGCLK
-g DONE_cycle:4
-g GTS_cycle:5
-g M0Pin:PULLUP
-g M2Pin:PULLUP
-g ProgPin:PULLUP
-g TckPin:PULLUP
-g TdiPin:PULLUP
-g TmsPin:PULLUP
-g DonePipe:No
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:NONE
-m
-g Persist:No

15
FreeRTOS/Demo/MicroBlaze/etc/bitgen_spartan3.ut Normal file
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-g CclkPin:PULLUP
-g TdoPin:PULLNONE
-g M1Pin:PULLDOWN
-g DonePin:PULLUP
-g StartUpClk:JTAGCLK
-g M0Pin:PULLUP
-g M2Pin:PULLUP
-g ProgPin:PULLUP
-g TckPin:PULLUP
-g TdiPin:PULLUP
-g TmsPin:PULLUP
-g LCK_cycle:NoWait
-g Security:NONE
-m
-g Persist:No

6
FreeRTOS/Demo/MicroBlaze/etc/download.cmd Normal file
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setMode -bscan
setCable -p auto
identify
assignfile -p 3 -file implementation/download.bit
program -p 3
quit

80
FreeRTOS/Demo/MicroBlaze/etc/fast_runtime.opt Normal file
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FLOWTYPE = FPGA;
###############################################################
## Filename: fast_runtime.opt
##
## Option File For Xilinx FPGA Implementation Flow for Fast
## Runtime.
##
## Version: 4.1.1
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-bm <design>.bmm # Block RAM memory map file
<userdesign>; # User design - pick from xflow command line
-uc <design>.ucf; # ucf constraints
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-pr b; # Pack internal FF/latches into IOBs
#-fp <design>.mfp; # Floorplan file
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>_map.twr; # Output trace report file
-xml <design>_map.twx; # Output XML version of the timing report
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
<inputdir><design>_map.ncd; # Input mapped NCD file
<design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>.twr; # Output trace report file
-xml <design>.twx; # Output XML version of the timing report
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce

1
FreeRTOS/Demo/MicroBlaze/etc/xmd_microblaze_0.opt Normal file
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connect mb mdm -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1

472
FreeRTOS/Demo/MicroBlaze/main.c Normal file
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#error This project has been reworked for use with a later version of the Xilinx tools and IP. Please find more up to date projects in other FreeRTOS/Demo/MicroBlaze_nnn directories.
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the standard demo application tasks.
*
* In addition to the standard tasks, main() creates two "Register Check"
* tasks. These tasks write known values into every general purpose register,
* then check each register to ensure it still contains the expected (written)
* value. The register check tasks operate at the idle priority so will get
* repeatedly preempted. A register being found to contain an incorrect value
* following such a preemption would be indicative of an error in the context
* switch mechanism.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "comtest2.h"
#include "integer.h"
#include "semtest.h"
#include "BlockQ.h"
#include "dynamic.h"
#include "PollQ.h"
/* Hardware library includes. */
#include <xintc.h>
/* The rate at which the 'check' LED will flash when no errors have been
detected. */
#define mainNO_ERROR_CHECK_PERIOD 3000
/* The rate at which the 'check' LED will flash when an error has been
detected in one of the demo tasks. */
#define mainERROR_CHECK_PERIOD 500
/* Demo application task priorities. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Software cannot influence the BAUD rate used by the simple UART
implementation. */
#define mainBAUD_RATE 0
/* The LED flashed by the 'check' task to indicate the system status. */
#define mainCHECK_TASK_LED 3
/* The first LED flashed by the COM port test tasks. LED mainCOM_TEST_LED + 1
will also be used. */
#define mainCOM_TEST_LED 4
/* The register test task does not make any function calls so does not require
much stack at all. */
#define mainTINY_STACK 70
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );
/*
* The register test task as described at the top of this file.
*/
static void vRegisterTest( void *pvParameters );
/*
* Perform any necessary hardware configuration.
*/
static void prvSetupHardware( void );
/* Set to pdFAIL should an error be discovered in the register test tasks. */
static unsigned long ulRegisterTestStatus = pdPASS;
const unsigned long *pulStatusAddr = &ulRegisterTestStatus;
/*-----------------------------------------------------------*/
/*
* Create all the demo tasks - then start the scheduler.
*/
int main (void)
{
/* When re-starting a debug session (rather than cold booting) we want
to ensure the installed interrupt handlers do not execute until after the
scheduler has been started. */
portDISABLE_INTERRUPTS();
prvSetupHardware();
/* Start the standard demo application tasks. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED );
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartDynamicPriorityTasks();
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
/* Create two register check tasks - using a different parameter for each.
The parameter is used to generate the known values written to the registers. */
#if configUSE_PREEMPTION == 1
xTaskCreate( vRegisterTest, "Reg1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
xTaskCreate( vRegisterTest, "Reg2", mainTINY_STACK, ( void * ) 20, tskIDLE_PRIORITY, NULL );
#endif
/* Create the 'check' task that is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Finally start the scheduler. */
vTaskStartScheduler();
/* Should not get here as the processor is now under control of the
scheduler! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_CHECK_PERIOD;
/* The parameters are not used. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The delay period used will depend on whether
or not an error has been discovered in one of the demo tasks. */
for( ;; )
{
vTaskDelay( xDelayPeriod );
if( !prvCheckOtherTasksAreStillRunning() )
{
/* An error has been found. Shorten the delay period to make
the LED flash faster. */
xDelayPeriod = mainERROR_CHECK_PERIOD;
}
vParTestToggleLED( mainCHECK_TASK_LED );
}
}
/*-----------------------------------------------------------*/
static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )
{
static portBASE_TYPE xAllTestsPass = pdTRUE;
/* Return pdFALSE if any demo application task set has encountered
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
xAllTestsPass = pdFALSE;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
xAllTestsPass = pdFALSE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
xAllTestsPass = pdFALSE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
xAllTestsPass = pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
xAllTestsPass = ( long ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
xAllTestsPass = ( long ) pdFAIL;
}
/* Mutual exclusion on this variable is not necessary as we only read it. */
if( ulRegisterTestStatus != pdPASS )
{
xAllTestsPass = pdFALSE;
}
return xAllTestsPass;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Ensure the interrupt controller is enabled in order that subsequent
code can successfully configure the peripherals. */
XIntc_mMasterEnable( XPAR_OPB_INTC_0_BASEADDR );
/* Initialise the GPIO used for the LED's. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static void vRegisterTest( void *pvParameters )
{
for( ;; )
{
/* Fill the registers with their register number plus the offset
(added) value. The added value is passed in as a parameter so
is contained in r5. */
asm volatile ( "addi r3, r5, 3 \n\t" \
"addi r4, r5, 4 \n\t" \
"addi r6, r5, 6 \n\t" \
"addi r7, r5, 7 \n\t" \
"addi r8, r5, 8 \n\t" \
"addi r9, r5, 9 \n\t" \
"addi r10, r5, 10 \n\t" \
"addi r11, r5, 11 \n\t" \
"addi r12, r5, 12 \n\t" \
"addi r16, r5, 16 \n\t" \
"addi r17, r5, 17 \n\t" \
"addi r18, r5, 18 \n\t" \
"addi r19, r5, 19 \n\t" \
"addi r20, r5, 20 \n\t" \
"addi r21, r5, 21 \n\t" \
"addi r22, r5, 22 \n\t" \
"addi r23, r5, 23 \n\t" \
"addi r24, r5, 24 \n\t" \
"addi r25, r5, 25 \n\t" \
"addi r26, r5, 26 \n\t" \
"addi r27, r5, 27 \n\t" \
"addi r28, r5, 28 \n\t" \
"addi r29, r5, 29 \n\t" \
"addi r30, r5, 30 \n\t" \
"addi r31, r5, 31 \n\t"
);
/* Now read back the register values to ensure they are as we expect.
This task will get preempted frequently so other tasks are likely to
have executed since the register values were written. */
/* r3 should contain r5 + 3. Subtract 3 to leave r3 equal to r5. */
asm volatile ( "addi r3, r3, -3 " );
/* Compare r3 and r5. If they are not equal then either r3 or r5
contains the wrong value and *pulStatusAddr is to pdFAIL. */
asm volatile ( "cmp r3, r3, r5 \n\t" \
"beqi r3, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t"
);
/* Repeat for all the other registers. */
asm volatile ( "addi r4, r4, -4 \n\t" \
"cmp r4, r4, r5 \n\t" \
"beqi r4, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r6, r6, -6 \n\t" \
"cmp r6, r6, r5 \n\t" \
"beqi r6, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r7, r7, -7 \n\t" \
"cmp r7, r7, r5 \n\t" \
"beqi r7, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r8, r8, -8 \n\t" \
"cmp r8, r8, r5 \n\t" \
"beqi r8, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r9, r9, -9 \n\t" \
"cmp r9, r9, r5 \n\t" \
"beqi r9, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r10, r10, -10 \n\t" \
"cmp r10, r10, r5 \n\t" \
"beqi r10, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r11, r11, -11 \n\t" \
"cmp r11, r11, r5 \n\t" \
"beqi r11, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r12, r12, -12 \n\t" \
"cmp r12, r12, r5 \n\t" \
"beqi r12, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r16, r16, -16 \n\t" \
"cmp r16, r16, r5 \n\t" \
"beqi r16, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r17, r17, -17 \n\t" \
"cmp r17, r17, r5 \n\t" \
"beqi r17, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r18, r18, -18 \n\t" \
"cmp r18, r18, r5 \n\t" \
"beqi r18, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r19, r19, -19 \n\t" \
"cmp r19, r19, r5 \n\t" \
"beqi r19, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r20, r20, -20 \n\t" \
"cmp r20, r20, r5 \n\t" \
"beqi r20, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r21, r21, -21 \n\t" \
"cmp r21, r21, r5 \n\t" \
"beqi r21, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r22, r22, -22 \n\t" \
"cmp r22, r22, r5 \n\t" \
"beqi r22, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r23, r23, -23 \n\t" \
"cmp r23, r23, r5 \n\t" \
"beqi r23, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r24, r24, -24 \n\t" \
"cmp r24, r24, r5 \n\t" \
"beqi r24, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r25, r25, -25 \n\t" \
"cmp r25, r25, r5 \n\t" \
"beqi r25, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r26, r26, -26 \n\t" \
"cmp r26, r26, r5 \n\t" \
"beqi r26, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r27, r27, -27 \n\t" \
"cmp r27, r27, r5 \n\t" \
"beqi r27, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r28, r28, -28 \n\t" \
"cmp r28, r28, r5 \n\t" \
"beqi r28, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r29, r29, -29 \n\t" \
"cmp r29, r29, r5 \n\t" \
"beqi r29, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r30, r30, -30 \n\t" \
"cmp r30, r30, r5 \n\t" \
"beqi r30, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t" \
"addi r31, r31, -31 \n\t" \
"cmp r31, r31, r5 \n\t" \
"beqi r31, 12 \n\t" \
"lwi r3, r0, pulStatusAddr \n\t" \
"sw r0, r0, r3 \n\t"
);
}
}

7
FreeRTOS/Demo/MicroBlaze/platgen.opt Normal file
View file

@ -0,0 +1,7 @@
-p
xc4vfx12ff668-10
-lang
vhdl
-st
xst
system.mhs

229
FreeRTOS/Demo/MicroBlaze/serial/serial.c Normal file
View file

@ -0,0 +1,229 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/* Microblaze driver includes. */
#include "xuartlite_l.h"
#include "xintc_l.h"
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulControlReg, ulMask;
/* NOTE: The baud rate used by this driver is determined by the hardware
parameterization of the UART Lite peripheral, and the baud value passed to
this function has no effect. */
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
if( ( xRxedChars ) && ( xCharsForTx ) )
{
/* Disable the interrupt. */
XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
/* Flush the fifos. */
ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
/* Enable the interrupt again. The interrupt controller has not yet been
initialised so there is no chance of receiving an interrupt until the
scheduler has been started. */
XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
/* Enable the interrupt in the interrupt controller while maintaining
all the other bit settings. */
ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
}
return ( xComPortHandle ) 0;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports one UART. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
portBASE_TYPE xReturn = pdTRUE;
portENTER_CRITICAL();
{
/* If the UART FIFO is full we can block posting the new data on the
Tx queue. */
if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
{
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
xReturn = pdFAIL;
}
}
/* Otherwise, if there is data already in the queue we should add the
new data to the back of the queue to ensure the sequencing is
maintained. */
else if( uxQueueMessagesWaiting( xCharsForTx ) )
{
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
xReturn = pdFAIL;
}
}
/* If the UART FIFO is not full and there is no data already in the
queue we can write directly to the FIFO without disrupting the
sequence. */
else
{
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/
void vSerialISR( void *pvBaseAddress )
{
unsigned long ulISRStatus;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
char cChar;
/* Determine the cause of the interrupt. */
ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
{
/* A character is available - place it in the queue of received
characters. This might wake a task that was blocked waiting for
data. */
cChar = ( char )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
}
if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
{
/* There is space in the FIFO - if there are any characters queue for
transmission they can be send to the UART now. This might unblock a
task that was waiting for space to become available on the Tx queue. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
}
}
/* If we woke any tasks we may require a context switch. */
if( xHigherPriorityTaskWoken )
{
portYIELD_FROM_ISR();
}
}

1
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@ -0,0 +1 @@
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#################################################################
# Makefile generated by Xilinx Platform Studio
# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp
#################################################################
# Name of the Microprocessor system
# The hardware specification of the system is in file :
# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mhs
# The software specification of the system is in file :
# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mss
include system_incl.make
#################################################################
# EXTERNAL TARGETS
#################################################################
all:
@echo "Makefile to build a Microprocessor system :"
@echo "Run make with any of the following targets"
@echo " "
@echo " netlist : Generates the netlist for the given MHS "
@echo " bits : Runs Implementation tools to generate the bitstream"
@echo " exporttopn:Export to ProjNav"
@echo " "
@echo " libs : Configures the sw libraries for this system"
@echo " program : Compiles the program sources for all the processor instances"
@echo " "
@echo " init_bram: Initializes bitstream with BRAM data"
@echo " ace : Generate ace file from bitstream and elf"
@echo " download : Downloads the bitstream onto the board"
@echo " "
@echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
@echo " simmodel : Generates HDL simulation models for chosen simulation mode"
@echo " behavioral_model:Generates behavioral HDL models with BRAM initialization"
@echo " structural_model:Generates structural simulation HDL models with BRAM initialization"
@echo " timing_model : Generates timing simulation HDL models with BRAM initialization"
@echo " vp : Generates virtual platform model"
@echo " "
@echo " netlistclean: Deletes netlist"
@echo " bitsclean: Deletes bit, ncd, bmm files"
@echo " hwclean : Deletes implementation dir"
@echo " libsclean: Deletes sw libraries"
@echo " programclean: Deletes compiled ELF files"
@echo " swclean : Deletes sw libraries and ELF files"
@echo " simclean : Deletes simulation dir"
@echo " vpclean : Deletes virtualplatform dir"
@echo " clean : Deletes all generated files/directories"
@echo " "
@echo " make <target> : (Default)"
@echo " Creates a Microprocessor system using default initializations"
@echo " specified for each processor in MSS file"
bits: $(SYSTEM_BIT)
ace: $(SYSTEM_ACE)
netlist: $(POSTSYN_NETLIST)
libs: $(LIBRARIES)
program: $(ALL_USER_ELF_FILES)
download: $(DOWNLOAD_BIT) dummy
@echo "*********************************************"
@echo "Downloading Bitstream onto the target board"
@echo "*********************************************"
impact -batch etc/download.cmd
init_bram: $(DOWNLOAD_BIT)
sim: $(DEFAULT_SIM_SCRIPT)
cd simulation/behavioral; \
$(SIM_CMD) &
simmodel: $(DEFAULT_SIM_SCRIPT)
behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
structural_model: $(STRUCTURAL_SIM_SCRIPT)
timing_model: $(TIMING_SIM_SCRIPT)
vp: $(VPEXEC)
clean: hwclean libsclean programclean simclean vpclean
rm -f _impact.cmd
hwclean: netlistclean bitsclean
rm -rf implementation synthesis xst hdl
rm -rf xst.srp $(SYSTEM).srp
netlistclean:
rm -f $(POSTSYN_NETLIST)
rm -f $(BMM_FILE)
bitsclean:
rm -f $(SYSTEM_BIT)
rm -f implementation/$(SYSTEM).ncd
rm -f implementation/$(SYSTEM)_bd.bmm
bitsclean:
simclean:
rm -rf simulation/behavioral
swclean: libsclean programclean
@echo ""
libsclean: $(LIBSCLEAN_TARGETS)
programclean: $(PROGRAMCLEAN_TARGETS)
vpclean:
rm -rf virtualplatform
#################################################################
# SOFTWARE PLATFORM FLOW
#################################################################
$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
@echo "*********************************************"
@echo "Creating software libraries..."
@echo "*********************************************"
libgen $(LIBGEN_OPTIONS) $(MSSFILE)
microblaze_0_libsclean:
rm -rf microblaze_0/lib/
$(MICROBLAZE_0_XMDSTUB): $(LIBRARIES)
#################################################################
# SOFTWARE APPLICATION RTOSDEMO
#################################################################
RTOSDemo_program: $(RTOSDEMO_OUTPUT)
$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \
$(LIBRARIES) __xps/rtosdemo_compiler.opt
@mkdir -p $(RTOSDEMO_OUTPUT_DIR)
$(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \
$(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \
-xl-mode-$(RTOSDEMO_MODE) \
$(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS)
$(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT)
RTOSDemo_programclean:
rm -f $(RTOSDEMO_OUTPUT)
#################################################################
# BOOTLOOP ELF FILES
#################################################################
$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP)
@mkdir -p $(BOOTLOOP_DIR)
cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP)
#################################################################
# HARDWARE IMPLEMENTATION FLOW
#################################################################
$(BMM_FILE) \
$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
$(CORE_STATE_DEVELOPMENT_FILES)
@echo "****************************************************"
@echo "Creating system netlist for hardware specification.."
@echo "****************************************************"
platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)
$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
@echo "Running synthesis..."
bash -c "cd synthesis; ./synthesis.sh; cd .."
$(SYSTEM_BIT): $(BMM_FILE) $(POSTSYN_NETLIST) __xps/xpsxflow.opt \
$(UCF_FILE) $(BITGEN_UT_FILE) $(FASTRUNTIME_OPT_FILE)
@echo "Copying Xilinx Implementation tool scripts.."
@cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
@cp -f $(FASTRUNTIME_OPT_FILE) implementation/fast_runtime.opt
@cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
@echo "*********************************************"
@echo "Running Xilinx Implementation tools.."
@echo "*********************************************"
xflow -wd implementation -p $(DEVICE) -implement fast_runtime.opt $(SYSTEM).ngc
cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)
exporttopn:
@echo "You have chosen XPS for implementation tool flow."
@echo "Please select ProjNav as your implementation flow in Project Options."
@echo "In batch mode, use commad xset pnproj <isefile>."
$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
@cp -f implementation/$(SYSTEM)_bd.bmm .
@echo "*********************************************"
@echo "Initializing BRAM contents of the bitstream"
@echo "*********************************************"
bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
-bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
@rm -f $(SYSTEM)_bd.bmm
$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT)
@echo "*********************************************"
@echo "Creating system ace file"
@echo "*********************************************"
xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -ace $(SYSTEM_ACE)
#################################################################
# SIMULATION FLOW
#################################################################
################## BEHAVIORAL SIMULATION ##################
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
$(BRAMINIT_ELF_FILES)
@echo "*********************************************"
@echo "Creating behavioral simulation models..."
@echo "*********************************************"
simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
################## STRUCTURAL SIMULATION ##################
$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
$(BRAMINIT_ELF_FILES)
@echo "*********************************************"
@echo "Creating structural simulation models..."
@echo "*********************************************"
simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
################## TIMING SIMULATION ##################
$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \
$(BRAMINIT_ELF_FILES)
@echo "*********************************************"
@echo "Creating timing simulation models..."
@echo "*********************************************"
simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
#################################################################
# VIRTUAL PLATFORM FLOW
#################################################################
$(VPEXEC): $(MHSFILE) __xps/vpgen.opt
@echo "****************************************************"
@echo "Creating virtual platform for hardware specification.."
@echo "****************************************************"
vpgen $(VPGEN_OPTIONS) $(MHSFILE)
dummy:
@echo ""

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
# Sun Nov 13 16:46:19 2005
# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family: virtex4
# Device: xc4vfx12
# Package: ff668
# Speed Grade: -10
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 64 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3]
PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4]
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = RS232_Uart_Interrupt
PORT RX = fpga_0_RS232_Uart_RX
PORT TX = fpga_0_RS232_Uart_TX
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_Positions
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
END
BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41c00000
PARAMETER C_HIGHADDR = 0x41c0ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = opb_timer_1_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
PARAMETER C_HAS_IPR = 0
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END

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PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER XMDSTUB_PERIPHERAL = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = RS232_Uart
PARAMETER int_handler = vSerialISR, int_port = Interrupt
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = LEDs_4Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = LEDs_Positions
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = opb_timer_1
PARAMETER int_handler = vTickISR, int_port = Interrupt
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = opb_intc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_0
END

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FreeRTOS/Demo/MicroBlaze/system.xmp Normal file
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#Please do not modify this file by hand
XmpVersion: 7.1
IntStyle: default
MHS File: system.mhs
MSS File: system.mss
NPL File: projnav/system.ise
Architecture: virtex4
Device: xc4vfx12
Package: ff668
SpeedGrade: -10
UseProjNav: 0
AddToNPL: 0
PNImportBitFile:
PNImportBmmFile:
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
SynProj: xst
ReloadPbde: 0
MainMhsEditor: 0
InsertNoPads: 0
HdlLang: VHDL
Simulator: mti
SimModel: BEHAVIORAL
SimXLib:
SimEdkLib:
MixLangSim: 1
UcfFile: data/system.ucf
Processor: microblaze_0
BootLoop: 0
XmdStub: 0
SwProj: RTOSDemo
Processor: microblaze_0
Executable: RTOSDemo/executable.elf
Source: main.c
Source: ParTest/ParTest.c
Source: ../../Source/tasks.c
Source: ../../Source/queue.c
Source: ../../Source/list.c
Source: ../../Source/portable/MemMang/heap_1.c
Source: ../../Source/portable/GCC/MicroBlaze/port.c
Source: ../../Source/portable/GCC/MicroBlaze/portasm.s
Source: ../Common/Minimal/flash.c
Source: serial/serial.c
Source: ../Common/Minimal/comtest.c
Source: ../Common/Minimal/integer.c
Source: ../Common/Minimal/semtest.c
Source: ../Common/Minimal/dynamic.c
Source: ../Common/Minimal/PollQ.c
Source: ../Common/Minimal/BlockQ.c
Header: FreeRTOSConfig.h
DefaultInit: EXECUTABLE
InitBram: 1
Active: 1
CompilerOptLevel: 4
GlobPtrOpt: 0
DebugSym: 1
SearchIncl: . ../Common/include ../../Source/include ../../Source/portable/GCC/MicroBlaze
AsmOpt:
LinkOpt: -Map=rtosdemo.map
ProgStart:
StackSize:
HeapSize:
LinkerScript:
ProgCCFlags: -D MICROBLAZE_GCC -Wall

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#################################################################
# Makefile generated by Xilinx Platform Studio
# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp
#################################################################
XILINX_EDK_DIR = C:/devtools/xilinx/EDK
SYSTEM = system
MHSFILE = system.mhs
MSSFILE = system.mss
FPGA_ARCH = virtex4
DEVICE = xc4vfx12ff668-10
LANGUAGE = vhdl
SEARCHPATHOPT =
SUBMODULE_OPT =
PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT)
LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) \
$(MICROBLAZE_0_LIBG_OPT)
VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT)
RTOSDEMO_OUTPUT_DIR = RTOSDemo
RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf
MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
BOOTLOOP_DIR = bootloops
MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf
MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf
BRAMINIT_ELF_FILES = $(RTOSDEMO_OUTPUT)
BRAMINIT_ELF_FILE_ARGS = -pe microblaze_0 $(RTOSDEMO_OUTPUT)
ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT)
SIM_CMD = vsim
BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do
STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do
TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
MIX_LANG_SIM_OPT = -mixed yes
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti
MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf
LIBRARIES = \
microblaze_0/lib/libxil.a
VPEXEC = virtualplatform/vpexec.exe
LIBSCLEAN_TARGETS = microblaze_0_libsclean
PROGRAMCLEAN_TARGETS = RTOSDemo_programclean
CORE_STATE_DEVELOPMENT_FILES =
WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \
implementation/mb_opb_wrapper.ngc \
implementation/debug_module_wrapper.ngc \
implementation/ilmb_wrapper.ngc \
implementation/dlmb_wrapper.ngc \
implementation/dlmb_cntlr_wrapper.ngc \
implementation/ilmb_cntlr_wrapper.ngc \
implementation/lmb_bram_wrapper.ngc \
implementation/rs232_uart_wrapper.ngc \
implementation/leds_4bit_wrapper.ngc \
implementation/leds_positions_wrapper.ngc \
implementation/opb_timer_1_wrapper.ngc \
implementation/opb_intc_0_wrapper.ngc \
implementation/dcm_0_wrapper.ngc
POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
SYSTEM_BIT = implementation/$(SYSTEM).bit
DOWNLOAD_BIT = implementation/download.bit
SYSTEM_ACE = implementation/$(SYSTEM).ace
UCF_FILE = data/system.ucf
BMM_FILE = implementation/$(SYSTEM).bmm
FASTRUNTIME_OPT_FILE = etc/fast_runtime.opt
BITGEN_UT_FILE = etc/bitgen.ut
#################################################################
# SOFTWARE APPLICATION RTOSDEMO
#################################################################
RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c
RTOSDEMO_HEADERS = FreeRTOSConfig.h
RTOSDEMO_CC = mb-gcc
RTOSDEMO_CC_SIZE = mb-size
RTOSDEMO_CC_OPT = -Os
RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall
RTOSDEMO_CC_SEARCH = # -B
RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L
RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze
RTOSDEMO_LFLAGS = # -l
RTOSDEMO_CC_PREPROC_FLAG = # -Wp,
RTOSDEMO_CC_ASM_FLAG = # -Wa,
RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map
RTOSDEMO_LINKER_SCRIPT =
RTOSDEMO_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT)
RTOSDEMO_CC_DEBUG_FLAG = -g
RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt
RTOSDEMO_MODE = executable
RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0
RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul
RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR=
RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE=
RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \
$(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) \
$(RTOSDEMO_CC_SOFTMUL_FLAG) \
$(RTOSDEMO_CC_PREPROC_FLAG) $(RTOSDEMO_CC_ASM_FLAG) $(RTOSDEMO_CC_LINKER_FLAG) \
$(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG)