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This commit is contained in:
Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
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135
FreeRTOS/Demo/MCF5235_GCC/system/crt0.S Normal file
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@ -0,0 +1,135 @@
/*
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
.title "crt0.S"
.extern main
.extern __stack
.extern __bss_start
.extern __text_start
.extern init_main
.equ MCF5XXX_RAMBAR_SPV, 0x00000200
.equ MCF5XXX_RAMBAR_V, 0x00000001
.global start
.align 4
debug:
.word 0x2C80 /* write to CSR */
.word 0x0010
.word 0x0400
.word 0x0000
start:
/* disable all interrupts on startup. */
move.w #0x2700, sr
/* prepare internal SRAM. */
move.l #__SRAM, d0
ori.l #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0
movec d0, rambar
/* prepare stack and frame pointer. */
move.l #__stack, sp
link a6, #-8
/* initialize hardware. */
jsr init_main
/* zero out the bss section. */
move.l #__bss_start, d1
move.l #_end, d0
cmp.l d0, d1
jbeq 3f
move.l d1, a0
sub.l d1, d0
subq.l #1, d0
2:
clr.b (a0)+
subq.l #1, d0
jbpl 2b
3:
/* Relocate the data section. */
move.l #__data_load_start, %a0 /* .data in ROM */
move.l #copy_start, %a1 /* .data in RAM */
/* Test if the two sections overlap. This is the case when we are working
* with the debugger and the debugger loads the .data section.
*/
cmpa.l %a0, %a1
beq 2f
1:
/* Have we already copied everything. */
cmpa.l #__data_load_end, %a0
beq 2f
move.b (%a0)+, (%a1)+
bra 1b
2:
/* C library */
move.l #__FINI_SECTION__, -(%sp)
jsr atexit
jsr __INIT_SECTION__
/* call main(int argc, char *argv[] */
move.l #0, -(sp)
move.l #0, -(sp)
move.l #0, -(sp)
jsr main
lea (sp, 12), %sp
/* stop on exit from main. */
1:
halt

763
FreeRTOS/Demo/MCF5235_GCC/system/init.c Normal file
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/*
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#include "mcf5xxx.h"
#include "mcf523x.h"
/* Function prototypes */
void init_main( void );
static void disable_interrupts( void );
static void disable_watchdog_timer( void );
static void disable_cache( void );
static void init_ipsbar( void );
static void init_basics( void );
static void init_clock_config( void );
static void init_chip_selects( void );
static void init_bus_config( void );
static void init_cache( void );
static void init_eport( void );
static void init_flexcan( void );
static void init_power_management( void );
static void init_dma_timers( void );
static void init_interrupt_timers( void );
static void init_watchdog_timers( void );
static void init_pin_assignments( void );
static void init_sdram_controller( void );
static void init_interrupt_controller( void );
/*********************************************************************
* init_main - Main entry point for initialisation code *
**********************************************************************/
void
init_main( void )
{
/* Initialise base address of peripherals, VBR, etc */
init_ipsbar( );
init_basics( );
init_clock_config( );
/* Disable interrupts, watchdog timer, cache */
disable_interrupts( );
disable_watchdog_timer( );
disable_cache( );
/* Initialise individual modules */
init_chip_selects( );
init_bus_config( );
init_cache( );
init_eport( );
init_flexcan( );
init_power_management( );
init_dma_timers( );
init_interrupt_timers( );
init_watchdog_timers( );
init_pin_assignments( );
init_sdram_controller( );
/* Initialise interrupt controller */
init_interrupt_controller( );
}
/*********************************************************************
* disable_interrupts - Disable all interrupt sources *
**********************************************************************/
static void
disable_interrupts( void )
{
vuint8 *p;
int i;
/* Set ICR008-ICR063 to 0x0 */
p = ( vuint8 * ) & MCF_INTC0_ICR8;
for( i = 8; i <= 63; i++ )
*p++ = 0x0;
/* Set ICR108-ICR163 to 0x0 */
p = ( vuint8 * ) & MCF_INTC1_ICR8;
for( i = 108; i <= 163; i++ )
*p++ = 0x0;
}
/*********************************************************************
* disable_watchdog_timer - Disable system watchdog timer *
**********************************************************************/
static void
disable_watchdog_timer( void )
{
/* Disable Core Watchdog Timer */
MCF_SCM_CWCR = 0;
}
/*********************************************************************
* disable_cache - Disable and invalidate cache *
**********************************************************************/
static void
disable_cache( void )
{
asm ( "move.l #0x01000000, %d0" );
asm ( "movec %d0, %CACR" );
}
/*********************************************************************
* init_basics - Configuration Information & VBR *
**********************************************************************/
static void
init_basics( void )
{
int i;
extern uint32 __RAMVEC[];
extern uint32 __ROMVEC[];
/* Transfer size not driven on SIZ[1:0] pins during external cycles
Processor Status (PST) and Debug Data (DDATA) functions disabled
Bus monitor disabled
Output pads configured for full strength
*/
MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
/* Set up RAM vectors */
for( i = 0; i < 256; i++ )
{
__RAMVEC[i] = __ROMVEC[i];
}
asm( "move.l %0,%%d0": :"i"( __RAMVEC ) );
asm( "movec %d0,%vbr" );
}
/*********************************************************************
* init_clock_config - Clock Module *
**********************************************************************/
static void
init_clock_config( void )
{
/* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
MFD = 0, RFD = 1
Bus clock frequency = 25.00 MHz
Processor clock frequency = 2 x bus clock = 50.00 MHz
Frequency Modulation disabled
Loss of clock detection disabled
Reset/Interrupt on loss of lock disabled
*/
MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */
while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
;
MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */
while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
;
}
/*********************************************************************
* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) *
**********************************************************************/
static void
init_ipsbar( void )
{
extern int __SRAM;
/* Base address of internal peripherals (IPSBAR) = 0x40000000
Note: Processor powers up with IPS base address = 0x40000000
Write to IPS base + 0x00000000 to set new value
*/
*( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
/* Configure RAMBAR in SCM module and allow dual-ported access. */
MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
}
/*********************************************************************
* init_chip_selects - Chip Select Module *
**********************************************************************/
static void
init_chip_selects( void )
{
extern void __FLASH;
uint32 FLASH_ADDR = (uint32)&__FLASH;
/* Chip Select 0 - External Flash */
MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
MCF_CS_CSCR0 = ( 0
| MCF_CS_CSCR_IWS( 6 )
| MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
/* Chip Select 1 disabled (CSMR1[V] = 0) */
MCF_CS_CSAR1 = 0;
MCF_CS_CSMR1 = 0;
MCF_CS_CSCR1 = 0;
/* Chip Select 2 disabled (CSMR2[V] = 0) */
MCF_CS_CSAR2 = 0;
MCF_CS_CSMR2 = 0;
MCF_CS_CSCR2 = 0;
/* Chip Select 3 disabled (CSMR3[V] = 0) */
MCF_CS_CSAR3 = 0;
MCF_CS_CSMR3 = 0;
MCF_CS_CSCR3 = 0;
/* Chip Select 4 disabled (CSMR4[V] = 0) */
MCF_CS_CSAR4 = 0;
MCF_CS_CSMR4 = 0;
MCF_CS_CSCR4 = 0;
/* Chip Select 5 disabled (CSMR5[V] = 0) */
MCF_CS_CSAR5 = 0;
MCF_CS_CSMR5 = 0;
MCF_CS_CSCR5 = 0;
/* Chip Select 6 disabled (CSMR6[V] = 0) */
MCF_CS_CSAR6 = 0;
MCF_CS_CSMR6 = 0;
MCF_CS_CSCR6 = 0;
/* Chip Select 7 disabled (CSMR7[V] = 0) */
MCF_CS_CSAR7 = 0;
MCF_CS_CSMR7 = 0;
MCF_CS_CSCR7 = 0;
}
/*********************************************************************
* init_bus_config - Internal Bus Arbitration *
**********************************************************************/
static void
init_bus_config( void )
{
/* Use round robin arbitration scheme
Assigned priorities (highest first):
Ethernet
DMA Controller
ColdFire Core
DMA bandwidth control disabled
Park on last active bus master
*/
MCF_SCM_MPARK =
MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
MCF_SCM_MPARK_M1_PRTY( 0x1 );
}
/*********************************************************************
* init_cache - Instruction/Data Cache *
**********************************************************************/
static void
init_cache( void )
{
/* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
ACR0: Don't cache accesses to 16 MB memory region at address $20000000
ACR1: Don't cache accesses to 1 GB memory region at address $40000000
CACR: Cache accesses to the rest of memory
*/
asm("move.l #0x80000000,%d0");
asm("movec %d0,%CACR");
asm("move.l #0x2000c040,%d0");
asm("movec %d0,%ACR0");
asm("move.l #0x403fc040,%d0");
asm("movec %d0,%ACR1");
/* Instruction/Data cache disabled. */
//asm( "move.l #0x00000000, %d0" );
//asm( "movec %d0,%cacr" );
}
/*********************************************************************
* init_eport - Edge Port Module (EPORT) *
**********************************************************************/
static void
init_eport( void )
{
/* Pins 1-7 configured as GPIO inputs */
MCF_EPORT_EPPAR = 0;
MCF_EPORT_EPDDR = 0;
MCF_EPORT_EPIER = 0;
}
/*********************************************************************
* init_flexcan - FlexCAN Module *
**********************************************************************/
static void
init_flexcan( void )
{
/* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
MCF_CAN_IMASK0 = 0;
MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
MCF_CAN_CANCTRL0 = 0;
MCF_CAN_CANMCR0 =
MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
/* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
MCF_CAN_IMASK1 = 0;
MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
MCF_CAN_CANCTRL1 = 0;
MCF_CAN_CANMCR1 =
MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
}
/*********************************************************************
* init_power_management - Power Management *
**********************************************************************/
static void
init_power_management( void )
{
/* On executing STOP instruction, processor enters RUN mode
Mode is exited when an interrupt of level 1 or higher is received
*/
MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
MCF_CCM_LPCR = 0;
}
/*********************************************************************
* init_sdram_controller - SDRAM Controller *
**********************************************************************/
static void
init_sdram_controller( void )
{
extern void __SDRAM;
uint32 SDRAM_ADDR = (uint32)&__SDRAM;
int i;
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
{
/* Initialize DRAM Control Register: DCR */
MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
/* Initialize DACR0 */
MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
MCF_SDRAMC_DACR0_CASL( 1 ) |
MCF_SDRAMC_DACR0_CBM( 3 ) |
MCF_SDRAMC_DACR0_PS( 0 ) );
/* Initialize DMR0 */
MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
/* Set IP (bit 3) in DACR */
MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
/* Wait 30ns to allow banks to precharge */
for( i = 0; i < 5; i++ )
{
asm volatile ( " nop" );
}
/* Write to this block to initiate precharge */
*( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
/* Wait for at least 8 auto refresh cycles to occur */
for( i = 0; i < 2000; i++ )
{
asm volatile ( "nop" );
}
/* Finish the configuration by issuing the IMRS. */
MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
/* Write to the SDRAM Mode Register */
*( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
}
}
/*********************************************************************
* init_dma_timers - DMA Timer Modules *
**********************************************************************/
static void
init_dma_timers( void )
{
/* DMA Timer 0 disabled (DTMR0[RST] = 0) */
MCF_TIMER_DTMR0 = 0;
MCF_TIMER_DTXMR0 = 0;
MCF_TIMER_DTRR0 = 0xffffffff;
/* DMA Timer 1 disabled (DTMR1[RST] = 0) */
MCF_TIMER_DTMR1 = 0;
MCF_TIMER_DTXMR1 = 0;
MCF_TIMER_DTRR1 = 0xffffffff;
/* DMA Timer 2 disabled (DTMR2[RST] = 0) */
MCF_TIMER_DTMR2 = 0;
MCF_TIMER_DTXMR2 = 0;
MCF_TIMER_DTRR2 = 0xffffffff;
/* DMA Timer 3 disabled (DTMR3[RST] = 0) */
MCF_TIMER_DTMR3 = 0;
MCF_TIMER_DTXMR3 = 0;
MCF_TIMER_DTRR3 = 0xffffffff;
}
/**********************************************************************
* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules *
***********************************************************************/
static void
init_interrupt_timers( void )
{
/* PIT0 disabled (PCSR0[EN]=0) */
MCF_PIT_PCSR0 = 0;
/* PIT1 disabled (PCSR1[EN]=0) */
MCF_PIT_PCSR1 = 0;
/* PIT2 disabled (PCSR2[EN]=0) */
MCF_PIT_PCSR2 = 0;
/* PIT3 disabled (PCSR3[EN]=0) */
MCF_PIT_PCSR3 = 0;
}
/*********************************************************************
* init_watchdog_timers - Watchdog Timer Modules *
**********************************************************************/
static void
init_watchdog_timers( void )
{
/* Watchdog Timer disabled (WCR[EN]=0)
NOTE: WCR and WMR cannot be written again until after the
processor is reset.
*/
MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
MCF_WTM_WMR = 0xffff;
/* Core Watchdog Timer disabled (CWCR[CWE]=0) */
MCF_SCM_CWCR = 0;
}
/*********************************************************************
* init_interrupt_controller - Interrupt Controller *
**********************************************************************/
static void
init_interrupt_controller( void )
{
/* Configured interrupt sources in order of priority...
Level 7: External interrupt /IRQ7, (initially masked)
Level 6: External interrupt /IRQ6, (initially masked)
Level 5: External interrupt /IRQ5, (initially masked)
Level 4: External interrupt /IRQ4, (initially masked)
Level 3: External interrupt /IRQ3, (initially masked)
Level 2: External interrupt /IRQ2, (initially masked)
Level 1: External interrupt /IRQ1, (initially masked)
*/
MCF_INTC0_ICR1 = 0;
MCF_INTC0_ICR2 = 0;
MCF_INTC0_ICR3 = 0;
MCF_INTC0_ICR4 = 0;
MCF_INTC0_ICR5 = 0;
MCF_INTC0_ICR6 = 0;
MCF_INTC0_ICR7 = 0;
MCF_INTC0_ICR8 = 0;
MCF_INTC0_ICR9 = 0;
MCF_INTC0_ICR10 = 0;
MCF_INTC0_ICR11 = 0;
MCF_INTC0_ICR12 = 0;
MCF_INTC0_ICR13 = 0;
MCF_INTC0_ICR14 = 0;
MCF_INTC0_ICR15 = 0;
MCF_INTC0_ICR17 = 0;
MCF_INTC0_ICR18 = 0;
MCF_INTC0_ICR19 = 0;
MCF_INTC0_ICR20 = 0;
MCF_INTC0_ICR21 = 0;
MCF_INTC0_ICR22 = 0;
MCF_INTC0_ICR23 = 0;
MCF_INTC0_ICR24 = 0;
MCF_INTC0_ICR25 = 0;
MCF_INTC0_ICR26 = 0;
MCF_INTC0_ICR27 = 0;
MCF_INTC0_ICR28 = 0;
MCF_INTC0_ICR29 = 0;
MCF_INTC0_ICR30 = 0;
MCF_INTC0_ICR31 = 0;
MCF_INTC0_ICR32 = 0;
MCF_INTC0_ICR33 = 0;
MCF_INTC0_ICR34 = 0;
MCF_INTC0_ICR35 = 0;
MCF_INTC0_ICR36 = 0;
MCF_INTC0_ICR37 = 0;
MCF_INTC0_ICR38 = 0;
MCF_INTC0_ICR39 = 0;
MCF_INTC0_ICR40 = 0;
MCF_INTC0_ICR41 = 0;
MCF_INTC0_ICR42 = 0;
MCF_INTC0_ICR43 = 0;
MCF_INTC0_ICR44 = 0;
MCF_INTC0_ICR45 = 0;
MCF_INTC0_ICR46 = 0;
MCF_INTC0_ICR47 = 0;
MCF_INTC0_ICR48 = 0;
MCF_INTC0_ICR49 = 0;
MCF_INTC0_ICR50 = 0;
MCF_INTC0_ICR51 = 0;
MCF_INTC0_ICR52 = 0;
MCF_INTC0_ICR53 = 0;
MCF_INTC0_ICR54 = 0;
MCF_INTC0_ICR55 = 0;
MCF_INTC0_ICR56 = 0;
MCF_INTC0_ICR57 = 0;
MCF_INTC0_ICR58 = 0;
MCF_INTC0_ICR59 = 0;
MCF_INTC0_ICR60 = 0;
MCF_INTC1_ICR8 = 0;
MCF_INTC1_ICR9 = 0;
MCF_INTC1_ICR10 = 0;
MCF_INTC1_ICR11 = 0;
MCF_INTC1_ICR12 = 0;
MCF_INTC1_ICR13 = 0;
MCF_INTC1_ICR14 = 0;
MCF_INTC1_ICR15 = 0;
MCF_INTC1_ICR16 = 0;
MCF_INTC1_ICR17 = 0;
MCF_INTC1_ICR18 = 0;
MCF_INTC1_ICR19 = 0;
MCF_INTC1_ICR20 = 0;
MCF_INTC1_ICR21 = 0;
MCF_INTC1_ICR22 = 0;
MCF_INTC1_ICR23 = 0;
MCF_INTC1_ICR24 = 0;
MCF_INTC1_ICR25 = 0;
MCF_INTC1_ICR27 = 0;
MCF_INTC1_ICR28 = 0;
MCF_INTC1_ICR29 = 0;
MCF_INTC1_ICR30 = 0;
MCF_INTC1_ICR31 = 0;
MCF_INTC1_ICR32 = 0;
MCF_INTC1_ICR33 = 0;
MCF_INTC1_ICR34 = 0;
MCF_INTC1_ICR35 = 0;
MCF_INTC1_ICR36 = 0;
MCF_INTC1_ICR37 = 0;
MCF_INTC1_ICR38 = 0;
MCF_INTC1_ICR39 = 0;
MCF_INTC1_ICR40 = 0;
MCF_INTC1_ICR41 = 0;
MCF_INTC1_ICR42 = 0;
MCF_INTC1_ICR59 = 0;
MCF_INTC0_IMRH = 0xffffffff;
MCF_INTC0_IMRL =
MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
MCF_INTC0_IMRL_INT_MASK1;
MCF_INTC1_IMRH = 0xffffffff;
MCF_INTC1_IMRL =
MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
MCF_INTC1_IMRL_INT_MASK1;
}
/*********************************************************************
* init_pin_assignments - Pin Assignment and General Purpose I/O *
**********************************************************************/
static void
init_pin_assignments( void )
{
/* Pin assignments for port ADDR
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_APDDR = 0;
MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
| MCF_GPIO_PAR_AD_PAR_ADDR22
| MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
/* Pin assignments for ports DATAH and DATAL
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_DATAH = 0;
MCF_GPIO_PDDR_DATAL = 0;
/* Pin assignments for port BUSCTL
Pin /OE : External bus output enable, /OE
Pin /TA : External bus transfer acknowledge, /TA
Pin /TEA : External bus transfer error acknowledge, /TEA
Pin R/W : External bus read/write indication, R/W
Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
Pin /TS : External bus transfer start, /TS
Pin /TIP : External bus transfer in progess, /TIP
*/
MCF_GPIO_PDDR_BUSCTL = 0;
MCF_GPIO_PAR_BUSCTL =
MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
/* Pin assignments for port BS
Pin /BS3 : External byte strobe /BS3
Pin /BS2 : External byte strobe /BS2
Pin /BS1 : External byte strobe /BS1
Pin /BS0 : External byte strobe /BS0
*/
MCF_GPIO_PDDR_BS = 0;
MCF_GPIO_PAR_BS =
MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
/* Pin assignments for port CS
Pin /CS7 : Chip select /CS7
Pin /CS6 : Chip select /CS6
Pin /CS5 : Chip select /CS5
Pin /CS4 : Chip select /CS4
Pin /CS3 : Chip select /CS3
Pin /CS2 : Chip select /CS2
Pin /CS1 : Chip select /CS1
*/
MCF_GPIO_PDDR_CS = 0;
MCF_GPIO_PAR_CS =
MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
MCF_GPIO_PAR_CS_PAR_CS1;
/* Pin assignments for port SDRAM
Pin /SD_WE : SDRAM controller /SD_WE
Pin /SD_SCAS : SDRAM controller /SD_SCAS
Pin /SD_SRAS : SDRAM controller /SD_SRAS
Pin /SD_SCKE : SDRAM controller /SD_SCKE
Pin /SD_CS1 : SDRAM controller /SD_CS1
Pin /SD_CS0 : SDRAM controller /SD_CS0
*/
MCF_GPIO_PDDR_SDRAM = 0;
MCF_GPIO_PAR_SDRAM =
MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
/* Pin assignments for port FECI2C
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_FECI2C = 0;
MCF_GPIO_PAR_FECI2C =
MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
/* Pin assignments for port UARTL
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_UARTL = 0;
MCF_GPIO_PAR_UART = 0;
/* Pin assignments for port UARTH
Pin U2TXD : GPIO input
Pin U2RXD : GPIO input
Pin /IRQ2 : Interrupt request /IRQ2 or GPIO
*/
MCF_GPIO_PDDR_UARTH = 0;
/* Pin assignments for port QSPI
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_QSPI = 0;
MCF_GPIO_PAR_QSPI = 0;
/* Pin assignments for port TIMER
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_TIMER = 0;
MCF_GPIO_PAR_TIMER = 0;
/* Pin assignments for port ETPU
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_ETPU = 0;
MCF_GPIO_PAR_ETPU = 0;
}

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/*
* Lowest level routines for all ColdFire processors. Based on the
* MCF523x examples from Freescale.
*
* Freescale explicitly grants the redistribution and modification
* of these source files. The complete licensing information is
* available in the file LICENSE_FREESCALE.TXT.
*
* Modifications Copyright (c) 2006 Christian Walter <wolti@sil.at>
*
* File: $Id: mcf5xxx.S,v 1.2 2006/09/24 22:50:22 wolti Exp $
*/
.global asm_set_ipl
.global _asm_set_ipl
.global mcf5xxx_wr_cacr
.global _mcf5xxx_wr_cacr
.global mcf5xxx_wr_acr0
.global _mcf5xxx_wr_acr0
.global mcf5xxx_wr_acr1
.global _mcf5xxx_wr_acr1
.global mcf5xxx_wr_acr2
.global _mcf5xxx_wr_acr2
.global mcf5xxx_wr_acr3
.global _mcf5xxx_wr_acr3
.global mcf5xxx_wr_other_sp
.global _mcf5xxx_wr_other_sp
.global mcf5xxx_wr_other_a7
.global _mcf5xxx_wr_other_a7
.global mcf5xxx_wr_vbr
.global _mcf5xxx_wr_vbr
.global mcf5xxx_wr_macsr
.global _mcf5xxx_wr_macsr
.global mcf5xxx_wr_mask
.global _mcf5xxx_wr_mask
.global mcf5xxx_wr_acc0
.global _mcf5xxx_wr_acc0
.global mcf5xxx_wr_accext01
.global _mcf5xxx_wr_accext01
.global mcf5xxx_wr_accext23
.global _mcf5xxx_wr_accext23
.global mcf5xxx_wr_acc1
.global _mcf5xxx_wr_acc1
.global mcf5xxx_wr_acc2
.global _mcf5xxx_wr_acc2
.global mcf5xxx_wr_acc3
.global _mcf5xxx_wr_acc3
.global mcf5xxx_wr_sr
.global _mcf5xxx_wr_sr
.global mcf5xxx_wr_rambar0
.global _mcf5xxx_wr_rambar0
.global mcf5xxx_wr_rambar1
.global _mcf5xxx_wr_rambar1
.global mcf5xxx_wr_mbar
.global _mcf5xxx_wr_mbar
.global mcf5xxx_wr_mbar0
.global _mcf5xxx_wr_mbar0
.global mcf5xxx_wr_mbar1
.global _mcf5xxx_wr_mbar1
.text
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
asm_set_ipl:
_asm_set_ipl:
link a6,#-8
movem.l d6-d7,(sp)
move.w sr,d7 /* current sr */
move.l d7,d0 /* prepare return value */
andi.l #0x0700,d0 /* mask out IPL */
lsr.l #8,d0 /* IPL */
move.l 8(a6),d6 /* get argument */
andi.l #0x07,d6 /* least significant three bits */
lsl.l #8,d6 /* move over to make mask */
andi.l #0x0000F8FF,d7 /* zero out current IPL */
or.l d6,d7 /* place new IPL in sr */
move.w d7,sr
movem.l (sp),d6-d7
lea 8(sp),sp
unlk a6
rts
/********************************************************************/
/*
* These routines write to the special purpose registers in the ColdFire
* core. Since these registers are write-only in the supervisor model,
* no corresponding read routines exist.
*/
mcf5xxx_wr_cacr:
_mcf5xxx_wr_cacr:
move.l 4(sp),d0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
mcf5xxx_wr_acr0:
_mcf5xxx_wr_acr0:
move.l 4(sp),d0
.long 0x4e7b0004 /* movec d0,ACR0 */
nop
rts
mcf5xxx_wr_acr1:
_mcf5xxx_wr_acr1:
move.l 4(sp),d0
.long 0x4e7b0005 /* movec d0,ACR1 */
nop
rts
mcf5xxx_wr_acr2:
_mcf5xxx_wr_acr2:
move.l 4(sp),d0
.long 0x4e7b0006 /* movec d0,ACR2 */
nop
rts
mcf5xxx_wr_acr3:
_mcf5xxx_wr_acr3:
move.l 4(sp),d0
.long 0x4e7b0007 /* movec d0,ACR3 */
nop
rts
mcf5xxx_wr_other_sp:
_mcf5xxx_wr_other_sp:
mcf5xxx_wr_other_a7:
_mcf5xxx_wr_other_a7:
move.l 4(sp),d0
.long 0x4e7b0800 /* movec d0,OTHER_A7 */
nop
rts
mcf5xxx_wr_vbr:
_mcf5xxx_wr_vbr:
move.l 4(sp),d0
.long 0x4e7b0801 /* movec d0,VBR */
nop
rts
mcf5xxx_wr_macsr:
_mcf5xxx_wr_macsr:
move.l 4(sp),d0
.long 0x4e7b0804 /* movec d0,MACSR */
nop
rts
mcf5xxx_wr_mask:
_mcf5xxx_wr_mask:
move.l 4(sp),d0
.long 0x4e7b0805 /* movec d0,MASK */
nop
rts
mcf5xxx_wr_acc0:
_mcf5xxx_wr_acc0:
move.l 4(sp),d0
.long 0x4e7b0806 /* movec d0,ACC0 */
nop
rts
mcf5xxx_wr_accext01:
_mcf5xxx_wr_accext01:
move.l 4(sp),d0
.long 0x4e7b0807 /* movec d0,ACCEXT01 */
nop
rts
mcf5xxx_wr_accext23:
_mcf5xxx_wr_accext23:
move.l 4(sp),d0
.long 0x4e7b0808 /* movec d0,ACCEXT23 */
nop
rts
mcf5xxx_wr_acc1:
_mcf5xxx_wr_acc1:
move.l 4(sp),d0
.long 0x4e7b0809 /* movec d0,ACC1 */
nop
rts
mcf5xxx_wr_acc2:
_mcf5xxx_wr_acc2:
move.l 4(sp),d0
.long 0x4e7b080A /* movec d0,ACC2 */
nop
rts
mcf5xxx_wr_acc3:
_mcf5xxx_wr_acc3:
move.l 4(sp),d0
.long 0x4e7b080B /* movec d0,ACC3 */
nop
rts
mcf5xxx_wr_sr:
_mcf5xxx_wr_sr:
move.l 4(sp),d0
move.w d0,SR
rts
mcf5xxx_wr_rambar0:
_mcf5xxx_wr_rambar0:
move.l 4(sp),d0
.long 0x4e7b0C04 /* movec d0,RAMBAR0 */
nop
rts
mcf5xxx_wr_rambar1:
_mcf5xxx_wr_rambar1:
move.l 4(sp),d0
.long 0x4e7b0C05 /* movec d0,RAMBAR1 */
nop
rts
mcf5xxx_wr_mbar:
_mcf5xxx_wr_mbar:
mcf5xxx_wr_mbar0:
_mcf5xxx_wr_mbar0:
move.l 4(sp),d0
.long 0x4e7b0C0F /* movec d0,MBAR0 */
nop
rts
mcf5xxx_wr_mbar1:
_mcf5xxx_wr_mbar1:
move.l 4(sp),d0
.long 0x4e7b0C0E /* movec d0,MBAR1 */
nop
rts
.end
/********************************************************************/

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/*
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* ------------------------ System includes ------------------------------- */
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <errno.h>
/* ------------------------ FreeRTOS includes ----------------------------- */
#include <FreeRTOS.h>
#include <serial.h>
/* ------------------------ Prototypes ------------------------------------ */
void vSerialPutStringNOISR( xComPortHandle pxPort,
const signed char * const pcString,
unsigned short usStringLength );
/* ------------------------ Start implementation -------------------------- */
void
_exit( int status )
{
asm volatile ( "halt" );
for( ;; );
}
pid_t
getpid( void )
{
return 0;
}
int
kill( pid_t pid, int sig )
{
_exit( 0 );
}
int
close( int fd )
{
return 0;
}
int
fstat( int fd, struct stat *buf )
{
buf->st_mode = S_IFCHR;
buf->st_blksize = 0;
return 0;
}
ssize_t
write( int fd, const void *buf, size_t nbytes )
{
ssize_t res = nbytes;
extern xComPortHandle xSTDComPort;
switch ( fd )
{
case STDERR_FILENO:
vSerialPutStringNOISR( xSTDComPort,
( const signed char * const )buf,
( unsigned short )nbytes );
break;
case STDOUT_FILENO:
vSerialPutString( xSTDComPort,
( const signed char * const)buf,
( unsigned short )nbytes );
break;
default:
errno = EIO;
res = -1;
break;
}
return res;
}
int
read( int fd, void *buf, size_t nbytes )
{
switch ( fd )
{
default:
errno = EIO;
return -1;
}
}
int
isatty( int fd )
{
return 0;
}
off_t
lseek( int fd, off_t offset, int whence )
{
errno = EIO;
return ( off_t ) - 1;
}
extern char _end[];
char *heap_ptr;
void *
sbrk( ptrdiff_t nbytes )
{
char *base;
if( !heap_ptr )
heap_ptr = ( char * )&_end;
base = heap_ptr;
heap_ptr += nbytes;
return base;
}

318
FreeRTOS/Demo/MCF5235_GCC/system/serial.c Normal file
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/*
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/* ------------------------ MCF523x includes ------------------------------ */
#include "mcf5xxx.h"
#include "mcf523x.h"
/* ------------------------ FreeRTOS includes ----------------------------- */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
#include "serial.h"
/* ----------------------- Defines ----------------------------------------- */
#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) )
#define MCF_UART_VECTOR ( 64 + 13 )
#define COM_NIFACE 1
#define COM_BLOCK_RETRYTIME 10
/* ------------------------ Static functions ------------------------------ */
static void prvSerialISR( void );
/* ------------------------ Static variables ------------------------------ */
typedef struct
{
portBASE_TYPE xInitialized;
xQueueHandle xRXChars;
xQueueHandle xTXChars;
} xComPortIF_t;
static xComPortIF_t xComPortIF[ COM_NIFACE ];
/* ------------------------ Begin implementation -------------------------- */
xComPortHandle
xSerialPortInitMinimal( unsigned long ulWantedBaud,
unsigned portBASE_TYPE uxQueueLength )
{
extern void ( *__RAMVEC[] ) ( );
xComPortHandle xReturn;
portBASE_TYPE xOldIPL;
/* Create the queues used to hold Rx and Tx characters. */
xComPortIF[ 0 ].xRXChars =
xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed char ) );
xComPortIF[ 0 ].xTXChars =
xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port hardware. */
if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) )
{
xOldIPL = portSET_IPL( portIPL_MAX );
/* UART 0: Reset transmitter, receiver and mode register pointer */
MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 );
MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 );
MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 );
/* Enable receive interrupts. */
MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
/* 8 Databits, 1 Stopbit and no parity */
MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 );
/* UART 0 Clocking */
MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd );
MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U;
MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU;
/* UART 0: Enable interrupts */
__RAMVEC[MCF_UART_VECTOR] = prvSerialISR;
MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 );
MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13;
/* UART 0 Miscellaneous */
MCF_UART_UACR0 = 0;
/* UART 0: Enable pins */
MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD;
/* Enable the UART. */
MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 );
xComPortIF[ 0 ].xInitialized = TRUE;
xReturn = ( xComPortHandle ) &xComPortIF[ 0 ];
( void )portSET_IPL( xOldIPL );
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
signed portBASE_TYPE
xSerialGetChar( xComPortHandle pxPort, signed char * pcRxedChar,
portTickType xBlockTime )
{
int i;
portBASE_TYPE xResult = pdFALSE;
/* Lookup the correct interface. */
for( i = 0; i < COM_NIFACE; i++ )
{
if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
{
break;
}
}
/* This COM port is available. */
if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
{
/* Get the next character from the buffer. Return false if no characters
* are available, or arrive before xBlockTime expires.
*/
if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) )
{
xResult = pdTRUE;
}
}
return xResult;
}
void
vSerialPutString( xComPortHandle pxPort, const signed char *
const pcString, unsigned short usStringLength )
{
int i;
signed char *pChNext;
/* Send each character in the string, one at a time. */
pChNext = ( signed char * )pcString;
for( i = 0; i < usStringLength; i++ )
{
/* Block until character has been transmitted. */
while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++;
}
}
signed portBASE_TYPE
xSerialPutChar( xComPortHandle pxPort, signed char cOutChar,
portTickType xBlockTime )
{
int i;
portBASE_TYPE xResult = pdFALSE;
portBASE_TYPE xOldIPL;
/* Lookup the correct interface. */
for( i = 0; i < COM_NIFACE; i++ )
{
if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
{
break;
}
}
/* This COM port is available. */
if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
{
/* Place the character in the queue of characters to be transmitted. */
if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS )
{
/* Turn on the Tx interrupt so the ISR will remove the character from the
* queue and send it. */
MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU;
xResult = pdTRUE;
}
}
return xResult;
}
signed portBASE_TYPE
xSerialPutCharNOISR( xComPortHandle pxPort, signed char cOutChar )
{
int i;
portBASE_TYPE xResult = pdFALSE;
portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
/* Lookup the correct interface. */
for( i = 0; i < COM_NIFACE; i++ )
{
if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
{
break;
}
}
/* This COM port is available. Support for this only available for COM1 right now. */
if( ( i != COM_NIFACE ) && ( i == 0 ) )
{
/* Wait until the transmit buffer is ready. */
while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) );
/* Place the character in the transmit buffer. */
MCF_UART_UTB0 = cOutChar;
xResult = pdTRUE;
}
( void )portSET_IPL( xOldIPL );
return xResult;
}
void
vSerialPutStringNOISR( xComPortHandle pxPort, const signed char *
const pcString, unsigned short usStringLength )
{
int i;
signed char *pChNext;
portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
/* Send each character in the string, one at a time. */
pChNext = ( signed char * )pcString;
for( i = 0; i < usStringLength; i++ )
{
/* Block until character has been transmitted. */
while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE );
pChNext++;
}
( void )portSET_IPL( xOldIPL );
}
void
vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
void
prvSerialISR( void )
{
static signed char cChar;
static portBASE_TYPE xHigherPriorityTaskWoken;
/* We have to remvoe the effect of the GCC. Please note that the
* __attribute__ ((interrupt_handler)) does not work here because we
* have to do the storing of the registers ourself. Another problem
* is the usage of a frame pointer which is unlinked on entry.
*/
#if _GCC_USES_FP == 1
asm volatile ( "unlk %fp\n\t" );
#endif
/* This ISR can cause a context switch, so the first statement must be
* a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
* variable declarations.
*/
portENTER_SWITCHING_ISR();
xHigherPriorityTaskWoken = pdFALSE;
/* Ready to send a character from the buffer. */
if( MCF_UART_USR0 & MCF_UART_USR_TXRDY )
{
/* Transmit buffer is ready. Test if there are characters available. */
if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xHigherPriorityTaskWoken ) ==
pdTRUE )
{
/* A character was retrieved from the queue so can be sent. */
MCF_UART_UTB0 = cChar;
}
else
{
/* Leave only receiver enabled. */
MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
}
}
if( MCF_UART_USR0 & MCF_UART_USR_RXRDY )
{
cChar = MCF_UART_URB0;
xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, &xHigherPriorityTaskWoken );
}
/* Exit the ISR. If a task was woken by either a character being
* or transmitted then a context switch will occur.
*/
portEXIT_SWITCHING_ISR( xHigherPriorityTaskWoken );
}

322
FreeRTOS/Demo/MCF5235_GCC/system/vector.S Normal file
View file

@ -0,0 +1,322 @@
/*
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License** as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
* *
* This is a concise, step by step, 'hands on' guide that describes both *
* general multitasking concepts and FreeRTOS specifics. It presents and *
* explains numerous examples that are written using the FreeRTOS API. *
* Full source code for all the examples is provided in an accompanying *
* .zip file. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
.extern __stack
.extern start
.extern fec_handler
.extern fec_if
.extern decrement_timers
.global __RAMVEC
.global __ROMVEC
.equ MCF_PIT_PCSR0, IPSBAR + 0x150000
.equ MCF_PIT_PCSR_PIF, 0x0004
.section .vector_rom, "x"
__ROMVEC:
.long __stack /* Reset: Initial Stack Pointer */
.long start /* Reset: Initial Program Counter */
.long VecDefault /* Bus Error */
.long VecDefault /* Address Error */
.long VecDefault /* Illegal Instruction */
.long VecDefault /* Zero Divison */
.space 4 /* reserved */
.space 4 /* reserved */
.long VecDefault /* Privilege Violation */
.long VecDefault /* Trace */
.long VecDefault /* Unimplemented line-a opcode */
.long VecDefault /* Unimplemented line-b opcode */
.long VecDefault /* Non-PC breakpoint debug interrupt */
.long VecDefault /* PC breakpoint debug interrupt */
.long VecDefault /* Format Error */
.long VecDefault /* Uninitialized Interrupt */
.org 0x60
.long IRQSpurious /* Spurious Interrupt */
.long IRQDefault /* Level 1 Interrupt */
.long IRQDefault /* Level 2 Interrupt */
.long IRQDefault /* Level 3 Interrupt */
.long IRQDefault /* Level 4 Interrupt */
.long IRQDefault /* Level 5 Interrupt */
.long IRQDefault /* Level 6 Interrupt */
.long IRQDefault /* Level 7 Interrupt */
.org 0x80
.long TrapDefault /* TRAP 0 */
.long TrapDefault /* TRAP 1 */
.long TrapDefault /* TRAP 2 */
.long TrapDefault /* TRAP 3 */
.long TrapDefault /* TRAP 4 */
.long TrapDefault /* TRAP 5 */
.long TrapDefault /* TRAP 6 */
.long TrapDefault /* TRAP 7 */
.long TrapDefault /* TRAP 8 */
.long TrapDefault /* TRAP 9 */
.long TrapDefault /* TRAP 10 */
.long TrapDefault /* TRAP 11 */
.long TrapDefault /* TRAP 12 */
.long TrapDefault /* TRAP 13 */
.long TrapDefault /* TRAP 14 */
.long TrapDefault /* TRAP 15 */
.org 0x100
.long IRQDefault /* User-Defined Interrupt 0 */
.long IRQDefault /* User-Defined Interrupt 1 */
.long IRQDefault /* User-Defined Interrupt 2 */
.long IRQDefault /* User-Defined Interrupt 3 */
.long IRQDefault /* User-Defined Interrupt 4 */
.long IRQDefault /* User-Defined Interrupt 5 */
.long IRQDefault /* User-Defined Interrupt 6 */
.long IRQDefault /* User-Defined Interrupt 7 */
.long IRQDefault /* User-Defined Interrupt 8 */
.long IRQDefault /* User-Defined Interrupt 9 */
.long IRQDefault /* User-Defined Interrupt 10 */
.long IRQDefault /* User-Defined Interrupt 11 */
.long IRQDefault /* User-Defined Interrupt 12 */
.long IRQDefault /* User-Defined Interrupt 13 */
.long IRQDefault /* User-Defined Interrupt 14 */
.long IRQDefault /* User-Defined Interrupt 15 */
.long IRQDefault /* User-Defined Interrupt 16 */
.long IRQDefault /* User-Defined Interrupt 17 */
.long IRQDefault /* User-Defined Interrupt 18 */
.long IRQDefault /* User-Defined Interrupt 19 */
.long IRQDefault /* User-Defined Interrupt 20 */
.long IRQDefault /* User-Defined Interrupt 21 */
.long IRQDefault /* User-Defined Interrupt 22 */
.long IRQDefault /* Transmit frame interrupt */
.long IRQDefault /* Transmit buffer interrupt */
.long IRQDefault /* Transmit FIFO underrun */
.long IRQDefault /* Collision retry limit */
.long IRQDefault /* Receive frame interrupt */
.long IRQDefault /* Receive buffer interrupt */
.long IRQDefault /* MII interrupt */
.long IRQDefault /* Late collision */
.long IRQDefault /* Heartbeat error */
.long IRQDefault /* Graceful stop complete */
.long IRQDefault /* Ethernet bus error */
.long IRQDefault /* Babbling transmit error */
.long IRQDefault /* Babbling receive error */
.long IRQDefault /* Timer interrupt */
.long IRQDefault /* User-Defined Interrupt 37 */
.long IRQDefault /* User-Defined Interrupt 38 */
.long IRQDefault /* User-Defined Interrupt 39 */
.long IRQDefault /* User-Defined Interrupt 40 */
.long IRQDefault /* User-Defined Interrupt 41 */
.long IRQDefault /* User-Defined Interrupt 42 */
.long IRQDefault /* User-Defined Interrupt 43 */
.long IRQDefault /* User-Defined Interrupt 44 */
.long IRQDefault /* User-Defined Interrupt 45 */
.long IRQDefault /* User-Defined Interrupt 46 */
.long IRQDefault /* User-Defined Interrupt 47 */
.long IRQDefault /* User-Defined Interrupt 48 */
.long IRQDefault /* User-Defined Interrupt 49 */
.long IRQDefault /* User-Defined Interrupt 50 */
.long IRQDefault /* User-Defined Interrupt 51 */
.long IRQDefault /* User-Defined Interrupt 52 */
.long IRQDefault /* User-Defined Interrupt 53 */
.long IRQDefault /* User-Defined Interrupt 54 */
.long IRQDefault /* User-Defined Interrupt 55 */
.long IRQDefault /* User-Defined Interrupt 56 */
.long IRQDefault /* User-Defined Interrupt 57 */
.long IRQDefault /* User-Defined Interrupt 58 */
.long IRQDefault /* User-Defined Interrupt 59 */
.long IRQDefault /* User-Defined Interrupt 60 */
.long IRQDefault /* User-Defined Interrupt 61 */
.long IRQDefault /* User-Defined Interrupt 62 */
.long IRQDefault /* User-Defined Interrupt 63 */
.long IRQDefault /* User-Defined Interrupt 64 */
.long IRQDefault /* User-Defined Interrupt 65 */
.long IRQDefault /* User-Defined Interrupt 66 */
.long IRQDefault /* User-Defined Interrupt 67 */
.long IRQDefault /* User-Defined Interrupt 68 */
.long IRQDefault /* User-Defined Interrupt 69 */
.long IRQDefault /* User-Defined Interrupt 70 */
.long IRQDefault /* User-Defined Interrupt 71 */
.long IRQDefault /* User-Defined Interrupt 72 */
.long IRQDefault /* User-Defined Interrupt 73 */
.long IRQDefault /* User-Defined Interrupt 74 */
.long IRQDefault /* User-Defined Interrupt 75 */
.long IRQDefault /* User-Defined Interrupt 76 */
.long IRQDefault /* User-Defined Interrupt 77 */
.long IRQDefault /* User-Defined Interrupt 78 */
.long IRQDefault /* User-Defined Interrupt 79 */
.long IRQDefault /* User-Defined Interrupt 80 */
.long IRQDefault /* User-Defined Interrupt 81 */
.long IRQDefault /* User-Defined Interrupt 82 */
.long IRQDefault /* User-Defined Interrupt 83 */
.long IRQDefault /* User-Defined Interrupt 84 */
.long IRQDefault /* User-Defined Interrupt 85 */
.long IRQDefault /* User-Defined Interrupt 86 */
.long IRQDefault /* User-Defined Interrupt 87 */
.long IRQDefault /* User-Defined Interrupt 88 */
.long IRQDefault /* User-Defined Interrupt 89 */
.long IRQDefault /* User-Defined Interrupt 90 */
.long IRQDefault /* User-Defined Interrupt 91 */
.long IRQDefault /* User-Defined Interrupt 92 */
.long IRQDefault /* User-Defined Interrupt 93 */
.long IRQDefault /* User-Defined Interrupt 94 */
.long IRQDefault /* User-Defined Interrupt 95 */
.long IRQDefault /* User-Defined Interrupt 96 */
.long IRQDefault /* User-Defined Interrupt 97 */
.long IRQDefault /* User-Defined Interrupt 98 */
.long IRQDefault /* User-Defined Interrupt 99 */
.long IRQDefault /* User-Defined Interrupt 100 */
.long IRQDefault /* User-Defined Interrupt 101 */
.long IRQDefault /* User-Defined Interrupt 102 */
.long IRQDefault /* User-Defined Interrupt 103 */
.long IRQDefault /* User-Defined Interrupt 104 */
.long IRQDefault /* User-Defined Interrupt 105 */
.long IRQDefault /* User-Defined Interrupt 106 */
.long IRQDefault /* User-Defined Interrupt 107 */
.long IRQDefault /* User-Defined Interrupt 108 */
.long IRQDefault /* User-Defined Interrupt 109 */
.long IRQDefault /* User-Defined Interrupt 110 */
.long IRQDefault /* User-Defined Interrupt 111 */
.long IRQDefault /* User-Defined Interrupt 112 */
.long IRQDefault /* User-Defined Interrupt 113 */
.long IRQDefault /* User-Defined Interrupt 114 */
.long IRQDefault /* User-Defined Interrupt 115 */
.long IRQDefault /* User-Defined Interrupt 116 */
.long IRQDefault /* User-Defined Interrupt 117 */
.long IRQDefault /* User-Defined Interrupt 118 */
.long IRQDefault /* User-Defined Interrupt 119 */
.long IRQDefault /* User-Defined Interrupt 120 */
.long IRQDefault /* User-Defined Interrupt 121 */
.long IRQDefault /* User-Defined Interrupt 122 */
.long IRQDefault /* User-Defined Interrupt 123 */
.long IRQDefault /* User-Defined Interrupt 124 */
.long IRQDefault /* User-Defined Interrupt 125 */
.long IRQDefault /* User-Defined Interrupt 126 */
.long IRQDefault /* User-Defined Interrupt 127 */
.long IRQDefault /* User-Defined Interrupt 128 */
.long IRQDefault /* User-Defined Interrupt 129 */
.long IRQDefault /* User-Defined Interrupt 130 */
.long IRQDefault /* User-Defined Interrupt 131 */
.long IRQDefault /* User-Defined Interrupt 132 */
.long IRQDefault /* User-Defined Interrupt 133 */
.long IRQDefault /* User-Defined Interrupt 134 */
.long IRQDefault /* User-Defined Interrupt 135 */
.long IRQDefault /* User-Defined Interrupt 136 */
.long IRQDefault /* User-Defined Interrupt 137 */
.long IRQDefault /* User-Defined Interrupt 138 */
.long IRQDefault /* User-Defined Interrupt 139 */
.long IRQDefault /* User-Defined Interrupt 140 */
.long IRQDefault /* User-Defined Interrupt 141 */
.long IRQDefault /* User-Defined Interrupt 142 */
.long IRQDefault /* User-Defined Interrupt 143 */
.long IRQDefault /* User-Defined Interrupt 144 */
.long IRQDefault /* User-Defined Interrupt 145 */
.long IRQDefault /* User-Defined Interrupt 146 */
.long IRQDefault /* User-Defined Interrupt 147 */
.long IRQDefault /* User-Defined Interrupt 148 */
.long IRQDefault /* User-Defined Interrupt 149 */
.long IRQDefault /* User-Defined Interrupt 150 */
.long IRQDefault /* User-Defined Interrupt 151 */
.long IRQDefault /* User-Defined Interrupt 152 */
.long IRQDefault /* User-Defined Interrupt 153 */
.long IRQDefault /* User-Defined Interrupt 154 */
.long IRQDefault /* User-Defined Interrupt 155 */
.long IRQDefault /* User-Defined Interrupt 156 */
.long IRQDefault /* User-Defined Interrupt 157 */
.long IRQDefault /* User-Defined Interrupt 158 */
.long IRQDefault /* User-Defined Interrupt 159 */
.long IRQDefault /* User-Defined Interrupt 160 */
.long IRQDefault /* User-Defined Interrupt 161 */
.long IRQDefault /* User-Defined Interrupt 162 */
.long IRQDefault /* User-Defined Interrupt 163 */
.long IRQDefault /* User-Defined Interrupt 164 */
.long IRQDefault /* User-Defined Interrupt 165 */
.long IRQDefault /* User-Defined Interrupt 166 */
.long IRQDefault /* User-Defined Interrupt 167 */
.long IRQDefault /* User-Defined Interrupt 168 */
.long IRQDefault /* User-Defined Interrupt 169 */
.long IRQDefault /* User-Defined Interrupt 170 */
.long IRQDefault /* User-Defined Interrupt 171 */
.long IRQDefault /* User-Defined Interrupt 172 */
.long IRQDefault /* User-Defined Interrupt 173 */
.long IRQDefault /* User-Defined Interrupt 174 */
.long IRQDefault /* User-Defined Interrupt 175 */
.long IRQDefault /* User-Defined Interrupt 176 */
.long IRQDefault /* User-Defined Interrupt 177 */
.long IRQDefault /* User-Defined Interrupt 178 */
.long IRQDefault /* User-Defined Interrupt 179 */
.long IRQDefault /* User-Defined Interrupt 180 */
.long IRQDefault /* User-Defined Interrupt 181 */
.long IRQDefault /* User-Defined Interrupt 182 */
.long IRQDefault /* User-Defined Interrupt 183 */
.long IRQDefault /* User-Defined Interrupt 184 */
.long IRQDefault /* User-Defined Interrupt 185 */
.long IRQDefault /* User-Defined Interrupt 186 */
.long IRQDefault /* User-Defined Interrupt 187 */
.long IRQDefault /* User-Defined Interrupt 188 */
.long IRQDefault /* User-Defined Interrupt 189 */
.long IRQDefault /* User-Defined Interrupt 190 */
.long IRQDefault /* User-Defined Interrupt 191 */
.org 0x00000400
.section .vector_ram
__RAMVEC:
.space 0x400
.section .text
VecDefault:
halt
bra VecDefault
IRQDefault:
halt
bra IRQDefault
IRQSpurious:
halt
bra IRQSpurious
TrapDefault:
halt
bra TrapDefault