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Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
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121
FreeRTOS/Demo/Cygnal/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "c8051f120.h"
/* THE VALUE FOR configSTACK_START MUST BE OBTAINED FROM THE .MEM FILE. */
#define configSTACK_START ( 0x0e )
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 98000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 - ( unsigned short ) configSTACK_START )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 8 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 1
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

124
FreeRTOS/Demo/Cygnal/Makefile Normal file
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#/*
# FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
#
#
# ***************************************************************************
# * *
# * FreeRTOS tutorial books are available in pdf and paperback. *
# * Complete, revised, and edited pdf reference manuals are also *
# * available. *
# * *
# * Purchasing FreeRTOS documentation will not only help you, by *
# * ensuring you get running as quickly as possible and with an *
# * in-depth knowledge of how to use FreeRTOS, it will also help *
# * the FreeRTOS project to continue with its mission of providing *
# * professional grade, cross platform, de facto standard solutions *
# * for microcontrollers - completely free of charge! *
# * *
# * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
# * *
# * Thank you for using FreeRTOS, and thank you for your support! *
# * *
# ***************************************************************************
#
#
# This file is part of the FreeRTOS distribution.
#
# FreeRTOS is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License (version 2) as published by the
# Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
# >>>NOTE<<< The modification to the GPL is included to allow you to
# distribute a combined work that includes FreeRTOS without being obliged to
# provide the source code for proprietary components outside of the FreeRTOS
# kernel. FreeRTOS is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details. You should have received a copy of the GNU General Public
# License and the FreeRTOS license exception along with FreeRTOS; if not it
# can be viewed here: http://www.freertos.org/a00114.html and also obtained
# by writing to Richard Barry, contact details for whom are available on the
# FreeRTOS WEB site.
#
# 1 tab == 4 spaces!
#
# http://www.FreeRTOS.org - Documentation, latest information, license and
# contact details.
#
# http://www.SafeRTOS.com - A version that is certified for use in safety
# critical systems.
#
# http://www.OpenRTOS.com - Commercial support, development, porting,
# licensing and training services.
#*/
CC=sdcc
NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse --nolabelopt --nooverlay --peep-asm
DEBUG=--debug
CFLAGS=--model-large -I. -I../Common/include -I../include -I../../Source/include \
-DSDCC_CYGNAL $(DEBUG) --less-pedantic --xram-size 8448 --stack-auto \
--no-peep --int-long-reent --float-reent
DEMO_DIR = ../Common
SOURCE_DIR = ../../Source
PORT_DIR = ../../Source/portable/SDCC/Cygnal
SRC = \
ParTest/ParTest.c \
serial/serial.c \
$(DEMO_DIR)/Full/flash.c \
$(DEMO_DIR)/Full/print.c \
$(DEMO_DIR)/Minimal/integer.c \
$(DEMO_DIR)/Minimal/PollQ.c \
$(DEMO_DIR)/Minimal/comtest.c \
$(DEMO_DIR)/Full/semtest.c \
$(SOURCE_DIR)/tasks.c \
$(SOURCE_DIR)/queue.c \
$(SOURCE_DIR)/list.c \
$(SOURCE_DIR)/portable/MemMang/heap_1.c \
$(PORT_DIR)/port.c
# Define all object files.
OBJ = $(SRC:.c=.rel)
######################################
# THIS VERSION WILL ONLY BUILD FILES THAT HAVE CHANGED, BUT MAY HAVE A DANGEROUS
# COMMAND LINE. IT WORKS FINE UNDER WINDOWS, BUT I HAVE COMMENTED IT OUT IN
# CASE IT CAUSES PROBLEMS ON OTHER SYSTEMS.
#main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ)
# $(CC) $(CFLAGS) main.c $(OBJ)
#%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h
# $(CC) -c $(CFLAGS) -o$< $<
######################################
# INSTEAD OF THE FOUR LINES ABOVE, THIS VERSION CAN BE USED BUT WILL CAUSE ALL
# FILES TO BUILD EVERY TIME.
main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ)
$(CC) $(CFLAGS) main.c $(OBJ)
%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h
$(CC) -c $(CFLAGS) $<

215
FreeRTOS/Demo/Cygnal/ParTest/ParTest.c Normal file
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/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#include <c8051f120.h>
#include "FreeRTOS.h"
#include "task.h"
#include "partest.h"
#define partstPUSH_PULL ( ( unsigned char ) 0xff )
#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0xff )
/* LED to output is dependent on how the LED's are wired. */
#define partstOUTPUT_0 ( ( unsigned char ) 0x02 )
#define partstOUTPUT_1 ( ( unsigned char ) 0x08 )
#define partstOUTPUT_2 ( ( unsigned char ) 0x20 )
#define partstOUTPUT_3 ( ( unsigned char ) 0x01 )
#define partstOUTPUT_4 ( ( unsigned char ) 0x04 )
#define partstOUTPUT_5 ( ( unsigned char ) 0x10 )
#define partstOUTPUT_6 ( ( unsigned char ) 0x40 )
#define partstOUTPUT_7 ( ( unsigned char ) 0x80 )
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
unsigned char ucOriginalSFRPage;
/* Remember the SFR page before it is changed so it can get set back
before the function exits. */
ucOriginalSFRPage = SFRPAGE;
/* Setup the SFR page to access the config SFR's. */
SFRPAGE = CONFIG_PAGE;
/* Set the on board LED to push pull. */
P3MDOUT |= partstPUSH_PULL;
/* Return the SFR page. */
SFRPAGE = ucOriginalSFRPage;
P3 = partstALL_OUTPUTS_OFF;
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue )
{
portBASE_TYPE xError = pdFALSE;
vTaskSuspendAll();
{
if( xValue == pdFALSE )
{
switch( uxLED )
{
case 0 : P3 |= partstOUTPUT_0;
break;
case 1 : P3 |= partstOUTPUT_1;
break;
case 2 : P3 |= partstOUTPUT_2;
break;
case 3 : P3 |= partstOUTPUT_3;
break;
case 4 : P3 |= partstOUTPUT_4;
break;
case 5 : P3 |= partstOUTPUT_5;
break;
case 6 : P3 |= partstOUTPUT_6;
break;
case 7 : P3 |= partstOUTPUT_7;
break;
default : /* There are no other LED's wired in. */
xError = pdTRUE;
break;
}
}
else
{
switch( uxLED )
{
case 0 : P3 &= ~partstOUTPUT_0;
break;
case 1 : P3 &= ~partstOUTPUT_1;
break;
case 2 : P3 &= ~partstOUTPUT_2;
break;
case 3 : P3 &= ~partstOUTPUT_3;
break;
case 4 : P3 &= ~partstOUTPUT_4;
break;
case 5 : P3 &= ~partstOUTPUT_5;
break;
case 6 : P3 &= ~partstOUTPUT_6;
break;
case 7 : P3 &= ~partstOUTPUT_7;
break;
default : /* There are no other LED's wired in. */
break;
}
}
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned char ucBit;
portBASE_TYPE xError = pdFALSE;
vTaskSuspendAll();
{
switch( uxLED )
{
case 0 : ucBit = partstOUTPUT_0;
break;
case 1 : ucBit = partstOUTPUT_1;
break;
case 2 : ucBit = partstOUTPUT_2;
break;
case 3 : ucBit = partstOUTPUT_3;
break;
case 4 : ucBit = partstOUTPUT_4;
break;
case 5 : ucBit = partstOUTPUT_5;
break;
case 6 : ucBit = partstOUTPUT_6;
break;
case 7 : ucBit = partstOUTPUT_7;
break;
default : /* There are no other LED's wired in. */
xError = pdTRUE;
break;
}
if( xError != pdTRUE )
{
if( P3 & ucBit )
{
P3 &= ~ucBit;
}
else
{
P3 |= ucBit;
}
}
}
xTaskResumeAll();
}

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FreeRTOS/Demo/Cygnal/c8051f120.h Normal file
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/*-------------------------------------------------------------------------
Register Declarations for the Cygnal C8051F12x Processor Range
Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------*/
#ifndef C8051F120_H
#define C8051F120_H
/* BYTE Registers */
/* All Pages */
sfr at 0x80 P0 ; /* PORT 0 */
sfr at 0x81 SP ; /* STACK POINTER */
sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
sfr at 0x87 PCON ; /* POWER CONTROL */
sfr at 0x90 P1 ; /* PORT 1 */
sfr at 0xA0 P2 ; /* PORT 2 */
sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
sfr at 0xB0 P3 ; /* PORT 3 */
sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
sfr at 0xE0 ACC ; /* ACCUMULATOR */
sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
sfr at 0xF0 B ; /* B REGISTER */
sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
sfr at 0x88 TCON ; /* TIMER CONTROL */
sfr at 0x89 TMOD ; /* TIMER MODE */
sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
sfr at 0x98 SCON ; /* UART 0 CONTROL */
sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
sfr at 0x99 SBUF ; /* UART 0 BUFFER */
sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
sfr at 0xB7 FLSCL ; /* FLASH SCALE */
sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
sfr at 0xEF RSTSRC ; /* RESET SOURCE */
sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
/* Page 0x02 */
sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
sfr at 0xBE ADC2 ; /* ADC 2 DATA */
sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
/* Page 0x02 */
sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
/* Page 0x0F */
sfr at 0x88 FLSTAT ; /* FLASH STATUS */
sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
sfr at 0xC8 P4 ; /* PORT 4 */
sfr at 0xD8 P5 ; /* PORT 5 */
sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
sfr at 0xE8 P6 ; /* PORT 6 */
sfr at 0xF8 P7 ; /* PORT 7 */
/* BIT Registers */
/* P0 0x80 */
sbit at 0x80 P0_0 ;
sbit at 0x81 P0_1 ;
sbit at 0x82 P0_2 ;
sbit at 0x83 P0_3 ;
sbit at 0x84 P0_4 ;
sbit at 0x85 P0_5 ;
sbit at 0x86 P0_6 ;
sbit at 0x87 P0_7 ;
/* TCON 0x88 */
sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
/* FLSTAT 0x88 */
sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
/* SCON0 0x98 */
sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
sbit at 0x9C REN ; /* UART 0 RX ENABLE */
sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
/* SCON1 0x98 */
sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
sbit at 0x9D MCE1 ; /* UART 1 MCE */
sbit at 0x9F S1MODE ; /* UART 1 MODE */
/* IE 0xA8 */
sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
/* TMR2CN 0xC8 */
sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
sbit at 0xC8 P4_0 ;
sbit at 0xC9 P4_1 ;
sbit at 0xCA P4_2 ;
sbit at 0xCB P4_3 ;
sbit at 0xCC P4_4 ;
sbit at 0xCD P4_5 ;
sbit at 0xCE P4_6 ;
sbit at 0xCF P4_7 ;
/* PSW 0xD0 */
sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
sbit at 0xD1 F1 ; /* USER FLAG 1 */
sbit at 0xD2 OV ; /* OVERFLOW FLAG */
sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
sbit at 0xD5 F0 ; /* USER FLAG 0 */
sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
sbit at 0xD7 CY ; /* CARRY FLAG */
/* PCA0CN D8H */
sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* P5 0xD8 */
sbit at 0xD8 P5_0 ;
sbit at 0xD9 P5_1 ;
sbit at 0xDA P5_2 ;
sbit at 0xDB P5_3 ;
sbit at 0xDC P5_4 ;
sbit at 0xDD P5_5 ;
sbit at 0xDE P5_6 ;
sbit at 0xDF P5_7 ;
/* ADC0CN E8H */
sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
/* ADC2CN E8H */
sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
/* P6 0xE8 */
sbit at 0xE8 P6_0 ;
sbit at 0xE9 P6_1 ;
sbit at 0xEA P6_2 ;
sbit at 0xEB P6_3 ;
sbit at 0xEC P6_4 ;
sbit at 0xED P6_5 ;
sbit at 0xEE P6_6 ;
sbit at 0xEF P6_7 ;
/* SPI0CN F8H */
sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
/* P7 0xF8 */
sbit at 0xF8 P7_0 ;
sbit at 0xF9 P7_1 ;
sbit at 0xFA P7_2 ;
sbit at 0xFB P7_3 ;
sbit at 0xFC P7_4 ;
sbit at 0xFD P7_5 ;
sbit at 0xFE P7_6 ;
sbit at 0xFF P7_7 ;
/* Predefined SFR Bit Masks */
#define IDLE 0x01 /* PCON */
#define STOP 0x02 /* PCON */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
/* SFR PAGE DEFINITIONS */
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
#define UART0_PAGE 0x00 /* UART 0 */
#define UART1_PAGE 0x01 /* UART 1 */
#define SPI0_PAGE 0x00 /* SPI 0 */
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
#define ADC0_PAGE 0x00 /* ADC 0 */
#define ADC2_PAGE 0x02 /* ADC 2 */
#define SMB0_PAGE 0x00 /* SMBUS 0 */
#define TMR2_PAGE 0x00 /* TIMER 2 */
#define TMR3_PAGE 0x01 /* TIMER 3 */
#define TMR4_PAGE 0x02 /* TIMER 4 */
#define DAC0_PAGE 0x00 /* DAC 0 */
#define DAC1_PAGE 0x01 /* DAC 1 */
#define PCA0_PAGE 0x00 /* PCA 0 */
#define PLL0_PAGE 0x0F /* PLL 0 */
#endif

597
FreeRTOS/Demo/Cygnal/main.c Normal file
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@ -0,0 +1,597 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* Creates the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main. c also creates four other tasks:
*
* 1) vErrorChecks()
* This only executes every few seconds but has the highest priority so is
* guaranteed to get processor time. Its main function is to check that all
* the standard demo application tasks are still operational and have not
* experienced any errors. vErrorChecks() will toggle the on board LED
* every mainNO_ERROR_FLASH_PERIOD milliseconds if none of the demo application
* tasks have reported an error. Should any task report an error at any time
* the rate at which the on board LED is toggled is increased to
* mainERROR_FLASH_PERIOD - providing visual feedback that something has gone
* wrong.
*
* 2) vRegisterCheck()
* This is a very simple task that checks that all the registers are always
* in their expected state. The task only makes use of the A register, so
* all the other registers should always contain their initial values.
* An incorrect value indicates an error in the context switch mechanism.
* The task operates at the idle priority so will be preempted regularly.
* Any error will cause the toggle rate of the on board LED to increase to
* mainERROR_FLASH_PERIOD milliseconds.
*
* 3 and 4) vFLOPCheck1() and vFLOPCheck2()
* These are very basic versions of the standard FLOP tasks. They are good
* at detecting errors in the context switch mechanism, and also check that
* the floating point libraries are correctly built to be re-enterant. The
* stack restrictions of the 8051 prevent the use of the standard FLOP demo
* tasks.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
/* Demo task priorities. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainINTEGER_PRIORITY tskIDLE_PRIORITY
/* Constants required to disable the watchdog. */
#define mainDISABLE_BYTE_1 ( ( unsigned char ) 0xde )
#define mainDISABLE_BYTE_2 ( ( unsigned char ) 0xad )
/* Constants to setup and use the on board LED. */
#define ucLED_BIT ( ( unsigned char ) 0x40 )
#define mainPORT_1_BIT_6 ( ( unsigned char ) 0x40 )
#define mainENABLE_CROSS_BAR ( ( unsigned char ) 0x40 )
/* Constants to set the clock frequency. */
#define mainSELECT_INTERNAL_OSC ( ( unsigned char ) 0x80 )
#define mainDIVIDE_CLOCK_BY_1 ( ( unsigned char ) 0x03 )
#define mainPLL_USES_INTERNAL_OSC ( ( unsigned char ) 0x04 )
#define mainFLASH_READ_TIMING ( ( unsigned char ) 0x30 )
#define mainPLL_POWER_ON ( ( unsigned char ) 0x01 )
#define mainPLL_NO_PREDIVIDE ( ( unsigned char ) 0x01 )
#define mainPLL_FILTER ( ( unsigned char ) 0x01 )
#define mainPLL_MULTIPLICATION ( ( unsigned char ) 0x04 )
#define mainENABLE_PLL ( ( unsigned char ) 0x02 )
#define mainPLL_LOCKED ( ( unsigned char ) 0x10 )
#define mainSELECT_PLL_AS_SOURCE ( ( unsigned char ) 0x02 )
/* Toggle rate for the on board LED - which is dependent on whether or not
an error has been detected. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 5000 )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 250 )
/* Baud rate used by the serial port tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
/* Pass an invalid LED number to the COM test task as we don't want it to flash
an LED. There are only 8 LEDs (excluding the on board LED) wired in and these
are all used by the flash tasks. */
#define mainCOM_TEST_LED ( 200 )
/* We want the Cygnal to act as much as possible as a standard 8052. */
#define mainAUTO_SFR_OFF ( ( unsigned char ) 0 )
/* Constants required to setup the IO pins for serial comms. */
#define mainENABLE_COMS ( ( unsigned char ) 0x04 )
#define mainCOMS_LINES_TO_PUSH_PULL ( ( unsigned char ) 0x03 )
/* Pointer passed as a parameter to vRegisterCheck() just so it has some know
values to check for in the DPH, DPL and B registers. */
#define mainDUMMY_POINTER ( ( xdata void * ) 0xabcd )
/* Macro that lets vErrorChecks() know that one of the tasks defined in
main. c has detected an error. A critical region is used around xLatchError
as it is accessed from vErrorChecks(), which has a higher priority. */
#define mainLATCH_ERROR() \
{ \
portENTER_CRITICAL(); \
xLatchedError = pdTRUE; \
portEXIT_CRITICAL(); \
}
/*
* Setup the Cygnal microcontroller for its fastest operation.
*/
static void prvSetupSystemClock( void );
/*
* Setup the peripherals, including the on board LED.
*/
static void prvSetupHardware( void );
/*
* Toggle the state of the on board LED.
*/
static void prvToggleOnBoardLED( void );
/*
* See comments at the top of the file for details.
*/
static void vErrorChecks( void *pvParameters );
/*
* See comments at the top of the file for details.
*/
static void vRegisterCheck( void *pvParameters );
/*
* See comments at the top of the file for details.
*/
static void vFLOPCheck1( void *pvParameters );
/*
* See comments at the top of the file for details.
*/
static void vFLOPCheck2( void *pvParameters );
/* File scope variable used to communicate the occurrence of an error between
tasks. */
static portBASE_TYPE xLatchedError = pdFALSE;
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
void main( void )
{
/* Initialise the hardware including the system clock and on board
LED. */
prvSetupHardware();
/* Initialise the port that controls the external LED's utilized by the
flash tasks. */
vParTestInitialise();
/* Start the used standard demo tasks. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartIntegerMathTasks( mainINTEGER_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
/* Start the tasks defined in this file. The first three never block so
must not be used with the co-operative scheduler. */
#if configUSE_PREEMPTION == 1
{
xTaskCreate( vRegisterCheck, "RegChck", configMINIMAL_STACK_SIZE, mainDUMMY_POINTER, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
xTaskCreate( vFLOPCheck1, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
xTaskCreate( vFLOPCheck2, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
}
#endif
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, ( xTaskHandle * ) NULL );
/* Finally kick off the scheduler. This function should never return. */
vTaskStartScheduler();
/* Should never reach here as the tasks will now be executing under control
of the scheduler. */
}
/*-----------------------------------------------------------*/
/*
* Setup the hardware prior to using the scheduler. Most of the Cygnal
* specific initialisation is performed here leaving standard 8052 setup
* only in the driver code.
*/
static void prvSetupHardware( void )
{
unsigned char ucOriginalSFRPage;
/* Remember the SFR page before it is changed so it can get set back
before the function exits. */
ucOriginalSFRPage = SFRPAGE;
/* Setup the SFR page to access the config SFR's. */
SFRPAGE = CONFIG_PAGE;
/* Don't allow the microcontroller to automatically switch SFR page, as the
SFR page is not stored as part of the task context. */
SFRPGCN = mainAUTO_SFR_OFF;
/* Disable the watchdog. */
WDTCN = mainDISABLE_BYTE_1;
WDTCN = mainDISABLE_BYTE_2;
/* Set the on board LED to push pull. */
P1MDOUT |= mainPORT_1_BIT_6;
/* Setup the cross bar to enable serial comms here as it is not part of the
standard 8051 setup and therefore is not in the driver code. */
XBR0 |= mainENABLE_COMS;
P0MDOUT |= mainCOMS_LINES_TO_PUSH_PULL;
/* Enable the cross bar so our hardware setup takes effect. */
XBR2 = mainENABLE_CROSS_BAR;
/* Setup a fast system clock. */
prvSetupSystemClock();
/* Return the SFR page. */
SFRPAGE = ucOriginalSFRPage;
}
/*-----------------------------------------------------------*/
static void prvSetupSystemClock( void )
{
volatile unsigned short usWait;
const unsigned short usWaitTime = ( unsigned short ) 0x2ff;
unsigned char ucOriginalSFRPage;
/* Remember the SFR page so we can set it back at the end. */
ucOriginalSFRPage = SFRPAGE;
SFRPAGE = CONFIG_PAGE;
/* Use the internal oscillator set to its fasted frequency. */
OSCICN = mainSELECT_INTERNAL_OSC | mainDIVIDE_CLOCK_BY_1;
/* Ensure the clock is stable. */
for( usWait = 0; usWait < usWaitTime; usWait++ );
/* Setup the clock source for the PLL. */
PLL0CN &= ~mainPLL_USES_INTERNAL_OSC;
/* Change the read timing for the flash ready for the fast clock. */
SFRPAGE = LEGACY_PAGE;
FLSCL |= mainFLASH_READ_TIMING;
/* Turn on the PLL power. */
SFRPAGE = CONFIG_PAGE;
PLL0CN |= mainPLL_POWER_ON;
/* Don't predivide the clock. */
PLL0DIV = mainPLL_NO_PREDIVIDE;
/* Set filter for fastest clock. */
PLL0FLT = mainPLL_FILTER;
PLL0MUL = mainPLL_MULTIPLICATION;
/* Ensure the clock is stable. */
for( usWait = 0; usWait < usWaitTime; usWait++ );
/* Enable the PLL and wait for it to lock. */
PLL0CN |= mainENABLE_PLL;
for( usWait = 0; usWait < usWaitTime; usWait++ )
{
if( PLL0CN & mainPLL_LOCKED )
{
break;
}
}
/* Select the PLL as the clock source. */
CLKSEL |= mainSELECT_PLL_AS_SOURCE;
/* Return the SFR back to its original value. */
SFRPAGE = ucOriginalSFRPage;
}
/*-----------------------------------------------------------*/
static void prvToggleOnBoardLED( void )
{
/* If the on board LED is on, turn it off and visa versa. */
if( P1 & ucLED_BIT )
{
P1 &= ~ucLED_BIT;
}
else
{
P1 |= ucLED_BIT;
}
}
/*-----------------------------------------------------------*/
/*
* See the documentation at the top of this file.
*/
static void vErrorChecks( void *pvParameters )
{
portBASE_TYPE xErrorHasOccurred = pdFALSE;
/* Just to prevent compiler warnings. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The delay period depends on whether an error
has ever been detected. */
for( ;; )
{
if( xLatchedError == pdFALSE )
{
/* No errors have been detected so delay for a longer period. The
on board LED will get toggled every mainNO_ERROR_FLASH_PERIOD ms. */
vTaskDelay( mainNO_ERROR_FLASH_PERIOD );
}
else
{
/* We have at some time recognised an error in one of the demo
application tasks, delay for a shorter period. The on board LED
will get toggled every mainERROR_FLASH_PERIOD ms. */
vTaskDelay( mainERROR_FLASH_PERIOD );
}
/* Check the demo application tasks for errors. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
xErrorHasOccurred = pdTRUE;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
xErrorHasOccurred = pdTRUE;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
xErrorHasOccurred = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
xErrorHasOccurred = pdTRUE;
}
/* If an error has occurred, latch it to cause the LED flash rate to
increase. */
if( xErrorHasOccurred == pdTRUE )
{
xLatchedError = pdTRUE;
}
/* Toggle the LED to indicate the completion of a check cycle. The
frequency of check cycles is dependent on whether or not we have
latched an error. */
prvToggleOnBoardLED();
}
}
/*-----------------------------------------------------------*/
/*
* See the documentation at the top of this file. Also see the standard FLOP
* demo task documentation for the rationale of these tasks.
*/
static void vFLOPCheck1( void *pvParameters )
{
volatile portFLOAT fVal1, fVal2, fResult;
( void ) pvParameters;
for( ;; )
{
fVal1 = ( portFLOAT ) -1234.5678;
fVal2 = ( portFLOAT ) 2345.6789;
fResult = fVal1 + fVal2;
if( ( fResult > ( portFLOAT ) 1111.15 ) || ( fResult < ( portFLOAT ) 1111.05 ) )
{
mainLATCH_ERROR();
}
fResult = fVal1 / fVal2;
if( ( fResult > ( portFLOAT ) -0.51 ) || ( fResult < ( portFLOAT ) -0.53 ) )
{
mainLATCH_ERROR();
}
}
}
/*-----------------------------------------------------------*/
/*
* See the documentation at the top of this file.
*/
static void vFLOPCheck2( void *pvParameters )
{
volatile portFLOAT fVal1, fVal2, fResult;
( void ) pvParameters;
for( ;; )
{
fVal1 = ( portFLOAT ) -12340.5678;
fVal2 = ( portFLOAT ) 23450.6789;
fResult = fVal1 + fVal2;
if( ( fResult > ( portFLOAT ) 11110.15 ) || ( fResult < ( portFLOAT ) 11110.05 ) )
{
mainLATCH_ERROR();
}
fResult = fVal1 / -fVal2;
if( ( fResult > ( portFLOAT ) 0.53 ) || ( fResult < ( portFLOAT ) 0.51 ) )
{
mainLATCH_ERROR();
}
}
}
/*-----------------------------------------------------------*/
/*
* See the documentation at the top of this file.
*/
static void vRegisterCheck( void *pvParameters )
{
( void ) pvParameters;
for( ;; )
{
if( SP != configSTACK_START )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar0
_endasm;
if( ACC != 0 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar1
_endasm;
if( ACC != 1 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar2
_endasm;
if( ACC != 2 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar3
_endasm;
if( ACC != 3 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar4
_endasm;
if( ACC != 4 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar5
_endasm;
if( ACC != 5 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar6
_endasm;
if( ACC != 6 )
{
mainLATCH_ERROR();
}
_asm
MOV ACC, ar7
_endasm;
if( ACC != 7 )
{
mainLATCH_ERROR();
}
if( DPL != 0xcd )
{
mainLATCH_ERROR();
}
if( DPH != 0xab )
{
mainLATCH_ERROR();
}
if( B != 0x01 )
{
mainLATCH_ERROR();
}
}
}

1670
FreeRTOS/Demo/Cygnal/sdcc.wsp Normal file
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246
FreeRTOS/Demo/Cygnal/serial/serial.c Normal file
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@ -0,0 +1,246 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR DEMO PURPOSES */
#include <stdlib.h>
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
#include "serial.h"
/* Constants required to setup the serial control register. */
#define ser8_BIT_MODE ( ( unsigned char ) 0x40 )
#define serRX_ENABLE ( ( unsigned char ) 0x10 )
/* Constants to setup the timer used to generate the baud rate. */
#define serCLOCK_DIV_48 ( ( unsigned char ) 0x03 )
#define serUSE_PRESCALED_CLOCK ( ( unsigned char ) 0x10 )
#define ser8BIT_WITH_RELOAD ( ( unsigned char ) 0x20 )
#define serSMOD ( ( unsigned char ) 0x10 )
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
data static unsigned portBASE_TYPE uxTxEmpty;
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulReloadValue;
const portFLOAT fBaudConst = ( portFLOAT ) configCPU_CLOCK_HZ * ( portFLOAT ) 2.0;
unsigned char ucOriginalSFRPage;
portENTER_CRITICAL();
{
ucOriginalSFRPage = SFRPAGE;
SFRPAGE = 0;
uxTxEmpty = pdTRUE;
/* Create the queues used by the com test task. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( char ) );
xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( char ) );
/* Calculate the baud rate to use timer 1. */
ulReloadValue = ( unsigned long ) ( ( ( portFLOAT ) 256 - ( fBaudConst / ( portFLOAT ) ( 32 * ulWantedBaud ) ) ) + ( portFLOAT ) 0.5 );
/* Set timer one for desired mode of operation. */
TMOD &= 0x08;
TMOD |= ser8BIT_WITH_RELOAD;
SSTA0 |= serSMOD;
/* Set the reload and start values for the time. */
TL1 = ( unsigned char ) ulReloadValue;
TH1 = ( unsigned char ) ulReloadValue;
/* Setup the control register for standard n, 8, 1 - variable baud rate. */
SCON = ser8_BIT_MODE | serRX_ENABLE;
/* Enable the serial port interrupts */
ES = 1;
/* Start the timer. */
TR1 = 1;
SFRPAGE = ucOriginalSFRPage;
}
portEXIT_CRITICAL();
/* Unlike some ports, this serial code does not allow for more than one
com port. We therefore don't return a pointer to a port structure and can
instead just return NULL. */
return NULL;
}
/*-----------------------------------------------------------*/
void vSerialISR( void ) interrupt 4
{
char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* 8051 port interrupt routines MUST be placed within a critical section
if taskYIELD() is used within the ISR! */
portENTER_CRITICAL();
{
if( RI )
{
/* Get the character and post it on the queue of Rxed characters.
If the post causes a task to wake force a context switch if the woken task
has a higher priority than the task we have interrupted. */
cChar = SBUF;
RI = 0;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
}
if( TI )
{
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == ( portBASE_TYPE ) pdTRUE )
{
/* Send the next character queued for Tx. */
SBUF = cChar;
}
else
{
/* Queue empty, nothing to send. */
uxTxEmpty = pdTRUE;
}
TI = 0;
}
if( xHigherPriorityTaskWoken )
{
portYIELD();
}
}
portEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
/* There is only one port supported. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return ( portBASE_TYPE ) pdTRUE;
}
else
{
return ( portBASE_TYPE ) pdFALSE;
}
}
/*-----------------------------------------------------------*/
portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
portBASE_TYPE xReturn;
/* There is only one port supported. */
( void ) pxPort;
portENTER_CRITICAL();
{
if( uxTxEmpty == pdTRUE )
{
SBUF = cOutChar;
uxTxEmpty = pdFALSE;
xReturn = ( portBASE_TYPE ) pdTRUE;
}
else
{
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
if( xReturn == ( portBASE_TYPE ) pdFALSE )
{
xReturn = ( portBASE_TYPE ) pdTRUE;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not implemented in this port. */
( void ) xPort;
}
/*-----------------------------------------------------------*/