mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Add FreeRTOS-Plus directory.
This commit is contained in:
Richard Barry
parent
7bd5f21ad5
commit
f508a5f653
6798 changed files with 134949 additions and 19 deletions
File diff suppressed because it is too large
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x200000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x21FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_startup__ = 0x100;
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_ROM_start__;
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export symbol __ICFEDIT_region_ROM_end__;
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_startup__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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initialize by copy { section .vectors };
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do not initialize { section .noinit };
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place in STA_region { section .cstartup };
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place in ROM_region { readonly };
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place in VEC_region { section .vectors };
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place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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||||
/*-Editor annotation file-*/
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||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_startup__ = 0x100;
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_SDRAM_start__;
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export symbol __ICFEDIT_region_SDRAM_end__;
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_startup__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
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define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { section .vectors };
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do not initialize { section .noinit };
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place in STA_region { section .cstartup };
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place in VEC_region { section .vectors };
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place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x800;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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do not initialize { section .noinit };
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place in VEC_region { section .vectors };
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place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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File diff suppressed because it is too large
Load diff
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@ -0,0 +1,48 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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||||
/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x200000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x23FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_startup__ = 0x100;
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_ROM_start__;
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export symbol __ICFEDIT_region_ROM_end__;
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_startup__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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initialize by copy { section .vectors };
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do not initialize { section .noinit };
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place in STA_region { section .cstartup };
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place in ROM_region { readonly };
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place in VEC_region { section .vectors };
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place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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@ -0,0 +1,46 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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||||
/*-Editor annotation file-*/
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||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_startup__ = 0x100;
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_SDRAM_start__;
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export symbol __ICFEDIT_region_SDRAM_end__;
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_startup__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
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define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { section .vectors };
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do not initialize { section .noinit };
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place in STA_region { section .cstartup };
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place in VEC_region { section .vectors };
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place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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@ -0,0 +1,36 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x800;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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do not initialize { section .noinit };
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place in VEC_region { section .vectors };
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place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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File diff suppressed because it is too large
Load diff
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@ -0,0 +1,48 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x200000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x27FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_startup__ = 0x100;
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_svcstack__ = 0x60;
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define symbol __ICFEDIT_size_irqstack__ = 0x60;
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define symbol __ICFEDIT_size_heap__ = 0x0;
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/*-Exports-*/
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export symbol __ICFEDIT_region_ROM_start__;
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export symbol __ICFEDIT_region_ROM_end__;
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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export symbol __ICFEDIT_size_startup__;
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export symbol __ICFEDIT_size_vectors__;
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export symbol __ICFEDIT_size_cstack__;
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export symbol __ICFEDIT_size_svcstack__;
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export symbol __ICFEDIT_size_irqstack__;
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export symbol __ICFEDIT_size_heap__;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
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define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
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define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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initialize by copy { section .vectors };
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do not initialize { section .noinit };
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place in STA_region { section .cstartup };
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place in ROM_region { readonly };
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place in VEC_region { section .vectors };
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place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
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@ -0,0 +1,46 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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||||
/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_startup__ = 0x100;
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define symbol __ICFEDIT_size_vectors__ = 0x100;
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x60;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x60;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
/*-Exports-*/
|
||||
export symbol __ICFEDIT_region_SDRAM_start__;
|
||||
export symbol __ICFEDIT_region_SDRAM_end__;
|
||||
export symbol __ICFEDIT_region_RAM_start__;
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
export symbol __ICFEDIT_size_startup__;
|
||||
export symbol __ICFEDIT_size_vectors__;
|
||||
export symbol __ICFEDIT_size_cstack__;
|
||||
export symbol __ICFEDIT_size_svcstack__;
|
||||
export symbol __ICFEDIT_size_irqstack__;
|
||||
export symbol __ICFEDIT_size_heap__;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
|
||||
define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
|
||||
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { section .vectors };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place in STA_region { section .cstartup };
|
||||
place in VEC_region { section .vectors };
|
||||
place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_vectors__ = 0x100;
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x60;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x60;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
/*-Exports-*/
|
||||
export symbol __ICFEDIT_region_RAM_start__;
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
export symbol __ICFEDIT_size_vectors__;
|
||||
export symbol __ICFEDIT_size_cstack__;
|
||||
export symbol __ICFEDIT_size_svcstack__;
|
||||
export symbol __ICFEDIT_size_irqstack__;
|
||||
export symbol __ICFEDIT_size_heap__;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place in VEC_region { section .vectors };
|
||||
place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,428 @@
|
|||
/* ----------------------------------------------------------------------------
|
||||
* ATMEL Microcontroller Software Support
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \dir
|
||||
/// !Purpose
|
||||
///
|
||||
/// Definition and functions for using AT91SAM9XE-related features, such
|
||||
/// has PIO pins, memories, etc.
|
||||
///
|
||||
/// !Usage
|
||||
/// -# The code for booting the board is provided by board_cstartup.S and
|
||||
/// board_lowlevel.c.
|
||||
/// -# For using board PIOs, board characteristics (clock, etc.) and external
|
||||
/// components, see board.h.
|
||||
/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \unit
|
||||
/// !Purpose
|
||||
///
|
||||
/// Definition of AT91SAM9XE-EK characteristics, AT91SAM9XE-dependant PIOs and
|
||||
/// external components interfacing.
|
||||
///
|
||||
/// !Usage
|
||||
/// -# For operating frequency information, see "SAM9XE-EK - Operating frequencies".
|
||||
/// -# For using portable PIO definitions, see "SAM9XE-EK - PIO definitions".
|
||||
/// -# Several USB definitions are included here (see "SAM9XE-EK - USB device").
|
||||
/// -# For external components definitions, see "SAM79260-EK - External components".
|
||||
/// -# For memory-related definitions, see "SAM79260-EK - Memories".
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Headers
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(at91sam9xe128)
|
||||
#include "at91sam9xe128/AT91SAM9XE128.h"
|
||||
#elif defined(at91sam9xe256)
|
||||
#include "at91sam9xe256/AT91SAM9XE256.h"
|
||||
#elif defined(at91sam9xe512)
|
||||
#include "at91sam9xe512/AT91SAM9XE512.h"
|
||||
#else
|
||||
#error Board does not support the specified chip.
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Definitions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE-EK - Board Description"
|
||||
/// This page lists several definition related to the board description.
|
||||
///
|
||||
/// !Definitions
|
||||
/// - BOARD_NAME
|
||||
|
||||
/// Name of the board.
|
||||
#define BOARD_NAME "AT91SAM9XE-EK"
|
||||
/// Board definition.
|
||||
#define at91sam9xeek
|
||||
/// Family definition.
|
||||
#define at91sam9xe
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE-EK - Operating frequencies"
|
||||
/// This page lists several definition related to the board operating frequency
|
||||
/// (when using the initialization done by board_lowlevel.c).
|
||||
///
|
||||
/// !Definitions
|
||||
/// - BOARD_MAINOSC
|
||||
/// - BOARD_MCK
|
||||
|
||||
/// Frequency of the board main oscillator.
|
||||
#define BOARD_MAINOSC 18432000
|
||||
|
||||
/// Master clock frequency (when using board_lowlevel.c).
|
||||
#define BOARD_MCK ((18432000 * 97 / 9) / 2)
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE-EK - USB device"
|
||||
/// This page lists constants describing several characteristics (controller
|
||||
/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board.
|
||||
///
|
||||
/// !Constants
|
||||
/// - BOARD_USB_UDP
|
||||
/// - BOARD_USB_PULLUP_INTERNAL
|
||||
/// - BOARD_USB_NUMENDPOINTS
|
||||
/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE
|
||||
/// - BOARD_USB_ENDPOINTS_BANKS
|
||||
/// - BOARD_USB_BMATTRIBUTES
|
||||
|
||||
/// Chip has a UDP controller.
|
||||
#define BOARD_USB_UDP
|
||||
|
||||
/// Indicates the D+ pull-up is internal to the USB controller.
|
||||
#define BOARD_USB_PULLUP_INTERNAL
|
||||
|
||||
/// Number of endpoints in the USB controller.
|
||||
#define BOARD_USB_NUMENDPOINTS 6
|
||||
|
||||
/// Returns the maximum packet size of the given endpoint.
|
||||
#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) ((i >= 4) ? 512 : 64)
|
||||
#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE_FS 64
|
||||
|
||||
/// Returns the number of FIFO banks for the given endpoint.
|
||||
#define BOARD_USB_ENDPOINTS_BANKS(i) (((i == 0) || (i == 3)) ? 1 : 2)
|
||||
|
||||
/// USB attributes configuration descriptor (bus or self powered, remote wakeup)
|
||||
#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE-EK - PIO definitions"
|
||||
/// This pages lists all the pio definitions contained in board.h. The constants
|
||||
/// are named using the following convention: PIN_* for a constant which defines
|
||||
/// a single Pin instance (but may include several PIOs sharing the same
|
||||
/// controller), and PINS_* for a list of Pin instances.
|
||||
///
|
||||
/// !DBGU
|
||||
/// - PINS_DBGU
|
||||
///
|
||||
/// !LEDs
|
||||
/// - PIN_LED_0
|
||||
/// - PIN_LED_1
|
||||
/// - PINS_LEDS
|
||||
/// - LED_POWER
|
||||
/// - LED_DS1
|
||||
///
|
||||
/// !Push buttons
|
||||
/// - PIN_PUSHBUTTON_1
|
||||
/// - PIN_PUSHBUTTON_2
|
||||
/// - PINS_PUSHBUTTONS
|
||||
/// - PUSHBUTTON_BP1
|
||||
/// - PUSHBUTTON_BP2
|
||||
///
|
||||
/// !USART0
|
||||
/// - PIN_USART0_RXD
|
||||
/// - PIN_USART0_TXD
|
||||
/// - PIN_USART0_SCK
|
||||
///
|
||||
/// !SPI0
|
||||
/// - PIN_SPI0_MISO
|
||||
/// - PIN_SPI0_MOSI
|
||||
/// - PIN_SPI0_SPCK
|
||||
/// - PINS_SPI0
|
||||
/// - PIN_SPI0_NPCS0
|
||||
/// - PIN_SPI0_NPCS1
|
||||
///
|
||||
/// !SSC
|
||||
/// - PINS_SSC_TX
|
||||
///
|
||||
/// !USB
|
||||
/// - PIN_USB_VBUS
|
||||
///
|
||||
/// !MCI
|
||||
/// - PINS_MCI
|
||||
///
|
||||
/// !TWI0
|
||||
/// - PINS_TWI0
|
||||
|
||||
/// List of all DBGU pin definitions.
|
||||
#define PINS_DBGU {(1<<14) | (1<<15), AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
|
||||
/// LED #0 pin definition.
|
||||
#define PIN_LED_0 {1 << 9, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
|
||||
/// LED #1 pin definition.
|
||||
#define PIN_LED_1 {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
|
||||
/// List of all LED definitions.
|
||||
#define PINS_LEDS PIN_LED_0, PIN_LED_1
|
||||
/// Power LED index.
|
||||
#define LED_POWER 0
|
||||
/// DS1 LED index.
|
||||
#define LED_DS1 1
|
||||
|
||||
/// Push button #1 pin definition.
|
||||
#define PIN_PUSHBUTTON_1 {1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
|
||||
/// Pusb button #2 pin definition.
|
||||
#define PIN_PUSHBUTTON_2 {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
|
||||
/// List of all pushbutton pin definitions.
|
||||
#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2
|
||||
/// Push button #1 index.
|
||||
#define PUSHBUTTON_BP1 0
|
||||
/// Push button #2 index.
|
||||
#define PUSHBUTTON_BP2 1
|
||||
|
||||
/// USART0 TXD pin definition.
|
||||
#define PIN_USART0_TXD {1 << 4, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// USART0 RXD pin definition.
|
||||
#define PIN_USART0_RXD {1 << 5, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// USART0 RTS pin definition.
|
||||
#define PIN_USART0_RTS {1 << 26, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// USART0 CTS pin definition.
|
||||
#define PIN_USART0_CTS {1 << 27, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// USART0 SCK pin definition.
|
||||
#define PIN_USART0_SCK {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
|
||||
/// SPI0 MISO pin definition.
|
||||
#define PIN_SPI0_MISO {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
|
||||
/// SPI0 MOSI pin definition.
|
||||
#define PIN_SPI0_MOSI {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// SPI0 SPCK pin definition.
|
||||
#define PIN_SPI0_SPCK {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// List of SPI0 pin definitions (MISO, MOSI & SPCK).
|
||||
#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK
|
||||
/// SPI0 chip select 0 pin definition.
|
||||
#define PIN_SPI0_NPCS0 {AT91C_PA3_SPI0_NPCS0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
/// SPI0 chip select 1 pin definition.
|
||||
#define PIN_SPI0_NPCS1 {AT91C_PC11_SPI0_NPCS1, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
|
||||
|
||||
/// SSC transmitter pins definition.
|
||||
#define PINS_SSC_TX {0x00038000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
|
||||
/// USB VBus monitoring pin definition.
|
||||
#define PIN_USB_VBUS {1 << 5, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}
|
||||
|
||||
/// List of MCI pins definitions.
|
||||
#define PINS_MCI {0x0000003B, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \
|
||||
{1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
|
||||
/// TWI0 pins definition.
|
||||
#define PINS_TWI0 {0x01800000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE-EK - External components"
|
||||
/// This page lists the definitions related to external on-board components
|
||||
/// located in the board.h file for the AT91SAM9XE-EK.
|
||||
///
|
||||
/// !AT45 Dataflash Card (A)
|
||||
/// - BOARD_AT45_A_SPI_BASE
|
||||
/// - BOARD_AT45_A_SPI_ID
|
||||
/// - BOARD_AT45_A_SPI_PINS
|
||||
/// - BOARD_AT45_A_SPI
|
||||
/// - BOARD_AT45_A_NPCS
|
||||
/// - BOARD_AT45_A_NPCS_PIN
|
||||
///
|
||||
/// !AT45 Dataflash (B)
|
||||
/// - BOARD_AT45_B_SPI_BASE
|
||||
/// - BOARD_AT45_B_SPI_ID
|
||||
/// - BOARD_AT45_B_SPI_PINS
|
||||
/// - BOARD_AT45_B_SPI
|
||||
/// - BOARD_AT45_B_NPCS
|
||||
/// - BOARD_AT45_B_NPCS_PIN
|
||||
///
|
||||
/// !SD Card
|
||||
/// - BOARD_SD_MCI_BASE
|
||||
/// - BOARD_SD_MCI_ID
|
||||
/// - BOARD_SD_PINS
|
||||
/// - BOARD_SD_SLOT
|
||||
///
|
||||
///
|
||||
/// !EMAC
|
||||
/// - AT91C_BASE_EMAC
|
||||
/// - BOARD_EMAC_POWER_ALWAYS_ON
|
||||
/// - BOARD_EMAC_MODE_RMII
|
||||
/// - BOARD_EMAC_PINS
|
||||
/// - BOARD_EMAC_PIN_TEST
|
||||
/// - BOARD_EMAC_PIN_RPTR
|
||||
/// - BOARD_EMAC_RST_PINS
|
||||
/// - BOARD_EMAC_RUN_PINS
|
||||
|
||||
|
||||
/// Base address of SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT45_A_SPI_BASE AT91C_BASE_SPI0
|
||||
/// Identifier of SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT45_A_SPI_ID AT91C_ID_SPI0
|
||||
/// Pins of the SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT45_A_SPI_PINS PINS_SPI0
|
||||
/// Dataflahs SPI number.
|
||||
#define BOARD_AT45_A_SPI 0
|
||||
/// Chip select connected to the dataflash.
|
||||
#define BOARD_AT45_A_NPCS 0
|
||||
/// Chip select pin connected to the dataflash.
|
||||
#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS0
|
||||
|
||||
/// Base address of SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT45_B_SPI_BASE AT91C_BASE_SPI0
|
||||
/// Identifier of SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT45_B_SPI_ID AT91C_ID_SPI0
|
||||
/// Pins of the SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT45_B_SPI_PINS PINS_SPI0
|
||||
/// Dataflahs SPI number.
|
||||
#define BOARD_AT45_B_SPI 0
|
||||
/// Chip select connected to the dataflash.
|
||||
#define BOARD_AT45_B_NPCS 1
|
||||
/// Chip select pin connected to the dataflash.
|
||||
#define BOARD_AT45_B_NPCS_PIN PIN_SPI0_NPCS1
|
||||
|
||||
/// Base address of SPI peripheral connected to the serialflash.
|
||||
#define BOARD_AT26_A_SPI_BASE AT91C_BASE_SPI0
|
||||
/// Identifier of SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT26_A_SPI_ID AT91C_ID_SPI0
|
||||
/// Pins of the SPI peripheral connected to the dataflash.
|
||||
#define BOARD_AT26_A_SPI_PINS PINS_SPI0
|
||||
/// Dataflahs SPI number.
|
||||
#define BOARD_AT26_A_SPI 0
|
||||
/// Chip select connected to the dataflash.
|
||||
#define BOARD_AT26_A_NPCS 0
|
||||
/// Chip select pin connected to the dataflash.
|
||||
#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS0
|
||||
|
||||
/// Base address of the MCI peripheral connected to the SD card.
|
||||
#define BOARD_SD_MCI_BASE AT91C_BASE_MCI
|
||||
/// Peripheral identifier of the MCI connected to the SD card.
|
||||
#define BOARD_SD_MCI_ID AT91C_ID_MCI
|
||||
/// MCI pins that shall be configured to access the SD card.
|
||||
#define BOARD_SD_PINS PINS_MCI
|
||||
/// MCI slot to which the SD card is connected to.
|
||||
#define BOARD_SD_SLOT MCI_SD_SLOTB
|
||||
|
||||
/// Board EMAC base address
|
||||
#if !defined(AT91C_BASE_EMAC) && defined(AT91C_BASE_EMACB)
|
||||
#define AT91C_BASE_EMAC AT91C_BASE_EMACB
|
||||
#endif
|
||||
/// Board EMAC power control - ALWAYS ON
|
||||
#define BOARD_EMAC_POWER_ALWAYS_ON
|
||||
/// Board EMAC work mode - RMII/MII ( 1 / 0 )
|
||||
#define BOARD_EMAC_MODE_RMII 1
|
||||
/// The PIN list of PIO for EMAC
|
||||
#define BOARD_EMAC_PINS { ((1<<19)|(1<<13)|(1<<12)|(1<<16)|(1<<15)|(1<<14)\
|
||||
|(1<<17)|(1<<18)|(1<<20)|(1<<21)|(1<<7)),\
|
||||
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT},\
|
||||
{ ((1<<11)|(1<<10)|(1<<26)|(1<<25)|(1<<27)|(1<<22)\
|
||||
|(1<<29)|(1<<28)),\
|
||||
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
|
||||
/// The power up reset latch PIO for PHY
|
||||
#define BOARD_EMAC_PIN_TEST {(1<<17), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
|
||||
//#define BOARD_EMAC_PIN_RMII : connected to 3v3 (RMII)
|
||||
// We force the address
|
||||
// (1<<14) PHY address 0, (1<<15) PHY address 1 (PIO A, perih A)
|
||||
// (1<<25) PHY address 2, (1<<26) PHY address 3 (PIO A, perih B)
|
||||
#define BOARD_EMAC_PINS_PHYAD { ((1<<14)|(1<<15)),\
|
||||
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT},\
|
||||
{ ((1<<25)|(1<<26)),\
|
||||
AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
|
||||
//#define BOARD_EMAC_PIN_10BT : not connected
|
||||
#define BOARD_EMAC_PIN_RPTR {(1<<27), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
|
||||
/// The PIN Configure list for EMAC on power up reset
|
||||
#define BOARD_EMAC_RST_PINS BOARD_EMAC_PINS_PHYAD,\
|
||||
BOARD_EMAC_PIN_TEST,\
|
||||
BOARD_EMAC_PIN_RPTR
|
||||
/// The runtime pin configure list for EMAC
|
||||
#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE-EK - Memories"
|
||||
/// This page lists definitions related to external on-board memories.
|
||||
///
|
||||
/// !Embedded Flash
|
||||
/// - BOARD_FLASH_EEFC
|
||||
///
|
||||
/// !SDRAM
|
||||
/// - BOARD_SDRAM_SIZE
|
||||
/// - PINS_SDRAM
|
||||
///
|
||||
/// !Nandflash
|
||||
/// - PINS_NANDFLASH
|
||||
/// - BOARD_NF_COMMAND_ADDR
|
||||
/// - BOARD_NF_ADDRESS_ADDR
|
||||
/// - BOARD_NF_DATA_ADDR
|
||||
/// - BOARD_NF_CE_PIN
|
||||
/// - BOARD_NF_RB_PIN
|
||||
|
||||
/// Indicates chip has an Enhanced EFC.
|
||||
#define BOARD_FLASH_EEFC
|
||||
/// Address of the IAP function in ROM.
|
||||
#define BOARD_FLASH_IAP_ADDRESS 0x100008
|
||||
|
||||
/// Board SDRAM size
|
||||
#define BOARD_SDRAM_SIZE 0x02000000
|
||||
/// List of all SDRAM pins definitions.
|
||||
#define PINS_SDRAM {0xFFFF0000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
|
||||
|
||||
|
||||
/// Nandflash controller peripheral pins definition.
|
||||
#define PINS_NANDFLASH BOARD_NF_CE_PIN, BOARD_NF_RB_PIN
|
||||
/// Nandflash chip enable pin definition.
|
||||
#define BOARD_NF_CE_PIN {1 << 14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
|
||||
/// Nandflash ready/busy pin definition.
|
||||
#define BOARD_NF_RB_PIN {1 << 13, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}
|
||||
/// Address for transferring command bytes to the nandflash.
|
||||
#define BOARD_NF_COMMAND_ADDR 0x40400000
|
||||
/// Address for transferring address bytes to the nandflash.
|
||||
#define BOARD_NF_ADDRESS_ADDR 0x40200000
|
||||
/// Address for transferring data bytes to the nandflash.
|
||||
#define BOARD_NF_DATA_ADDR 0x40000000
|
||||
|
||||
/// Address for transferring command bytes to the norflash.
|
||||
#define BOARD_NORFLASH_ADDR 0x10000000
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#endif //#ifndef BOARD_H
|
||||
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/* ----------------------------------------------------------------------------
|
||||
* ATMEL Microcontroller Software Support
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "ISR_Support.h"
|
||||
|
||||
/*
|
||||
IAR startup file for AT91SAM9XE microcontrollers.
|
||||
*/
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION IRQ_STACK:DATA:NOROOT(2)
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Headers
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include "board.h"
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Definitions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define ARM_MODE_ABT 0x17
|
||||
#define ARM_MODE_FIQ 0x11
|
||||
#define ARM_MODE_IRQ 0x12
|
||||
#define ARM_MODE_SVC 0x13
|
||||
#define ARM_MODE_SYS 0x1F
|
||||
|
||||
#define I_BIT 0x80
|
||||
#define F_BIT 0x40
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Startup routine
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
Exception vectors
|
||||
*/
|
||||
SECTION .vectors:CODE:NOROOT(2)
|
||||
|
||||
PUBLIC resetVector
|
||||
PUBLIC irqHandler
|
||||
|
||||
EXTERN Undefined_Handler
|
||||
EXTERN vPortYieldProcessor
|
||||
EXTERN Prefetch_Handler
|
||||
EXTERN Abort_Handler
|
||||
EXTERN FIQ_Handler
|
||||
|
||||
ARM
|
||||
|
||||
__iar_init$$done: ; The interrupt vector is not needed
|
||||
; until after copy initialization is done
|
||||
|
||||
resetVector:
|
||||
; All default exception handlers (except reset) are
|
||||
; defined as weak symbol definitions.
|
||||
; If a handler is defined by the application it will take precedence.
|
||||
LDR pc, =resetHandler ; Reset
|
||||
LDR pc, Undefined_Addr ; Undefined instructions
|
||||
LDR pc, SWI_Addr ; Software interrupt (SWI/SVC)
|
||||
LDR pc, Prefetch_Addr ; Prefetch abort
|
||||
LDR pc, Abort_Addr ; Data abort
|
||||
B . ; RESERVED
|
||||
LDR pc, =irqHandler ; IRQ
|
||||
LDR pc, FIQ_Addr ; FIQ
|
||||
|
||||
Undefined_Addr: DCD Undefined_Handler
|
||||
SWI_Addr: DCD vPortYieldProcessor
|
||||
Prefetch_Addr: DCD Prefetch_Handler
|
||||
Abort_Addr: DCD Abort_Handler
|
||||
FIQ_Addr: DCD FIQ_Handler
|
||||
|
||||
/*
|
||||
Handles incoming interrupt requests by branching to the corresponding
|
||||
handler, as defined in the AIC. Supports interrupt nesting.
|
||||
*/
|
||||
irqHandler:
|
||||
portSAVE_CONTEXT
|
||||
|
||||
/* Write in the IVR to support Protect Mode */
|
||||
LDR lr, =AT91C_BASE_AIC
|
||||
LDR r0, [r14, #AIC_IVR]
|
||||
STR lr, [r14, #AIC_IVR]
|
||||
|
||||
/* Branch to C portion of the interrupt handler */
|
||||
MOV lr, pc
|
||||
BX r0
|
||||
|
||||
/* Acknowledge interrupt */
|
||||
LDR lr, =AT91C_BASE_AIC
|
||||
STR lr, [r14, #AIC_EOICR]
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
/*
|
||||
After a reset, execution starts here, the mode is ARM, supervisor
|
||||
with interrupts disabled.
|
||||
Initializes the chip and branches to the main() function.
|
||||
*/
|
||||
SECTION .cstartup:CODE:NOROOT(2)
|
||||
|
||||
PUBLIC resetHandler
|
||||
EXTERN LowLevelInit
|
||||
EXTERN ?main
|
||||
REQUIRE resetVector
|
||||
ARM
|
||||
|
||||
resetHandler:
|
||||
|
||||
/* Set pc to actual code location (i.e. not in remap zone) */
|
||||
LDR pc, =label
|
||||
|
||||
/* Perform low-level initialization of the chip using LowLevelInit() */
|
||||
label:
|
||||
LDR r0, =LowLevelInit
|
||||
LDR r4, =SFE(CSTACK)
|
||||
MOV sp, r4
|
||||
MOV lr, pc
|
||||
BX r0
|
||||
|
||||
/* Set up the interrupt stack pointer. */
|
||||
MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
|
||||
LDR sp, =SFE(IRQ_STACK)
|
||||
|
||||
/* Set up the SVC stack pointer. */
|
||||
MSR cpsr_c, #ARM_MODE_SVC | F_BIT ; Change the mode
|
||||
LDR sp, =SFE(CSTACK)
|
||||
|
||||
/* Branch to main() */
|
||||
LDR r0, =?main
|
||||
MOV lr, pc
|
||||
BX r0
|
||||
|
||||
/* Loop indefinitely when program is finished */
|
||||
loop4:
|
||||
B loop4
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/* ----------------------------------------------------------------------------
|
||||
* ATMEL Microcontroller Software Support
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Headers
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#include "board.h"
|
||||
#include "board_memories.h"
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Local definitions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// \page "SAM9XE - Oscillator & PLL Parameters"
|
||||
/// This page lists the parameters which are set for the PLL and main
|
||||
/// oscillator configuration.
|
||||
///
|
||||
/// !Parameters
|
||||
/// - BOARD_OSCOUNT
|
||||
/// - BOARD_CKGR_PLLA
|
||||
/// - BOARD_PLLACOUNT
|
||||
/// - BOARD_MULA
|
||||
/// - BOARD_DIVA
|
||||
/// - BOARD_CKGR_PLLB
|
||||
/// - BOARD_PLLBCOUNT
|
||||
/// - BOARD_MULB
|
||||
/// - BOARD_DIVB
|
||||
/// - BOARD_USBDIV
|
||||
/// - BOARD_PRESCALER
|
||||
|
||||
/// Main oscillator startup time (in number of slow clock ticks).
|
||||
#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
|
||||
|
||||
/// PLLA frequency range.
|
||||
#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)
|
||||
/// PLLA startup time (in number of slow clock ticks).
|
||||
#define BOARD_PLLACOUNT (63 << 8)
|
||||
/// PLLA MUL value.
|
||||
#define BOARD_MULA (AT91C_CKGR_MULA & (96 << 16))
|
||||
/// PLLA DIV value.
|
||||
#define BOARD_DIVA (AT91C_CKGR_DIVA & 9)
|
||||
|
||||
/// PLLB frequency range
|
||||
#define BOARD_CKGR_PLLB AT91C_CKGR_OUTB_1
|
||||
/// PLLB startup time (in number of slow clock ticks).
|
||||
#define BOARD_PLLBCOUNT BOARD_PLLACOUNT
|
||||
/// PLLB MUL value.
|
||||
#define BOARD_MULB (124 << 16)
|
||||
/// PLLB DIV value.
|
||||
#define BOARD_DIVB 12
|
||||
|
||||
/// USB PLL divisor value to obtain a 48MHz clock.
|
||||
#define BOARD_USBDIV AT91C_CKGR_USBDIV_2
|
||||
/// Master clock prescaler value.
|
||||
#define BOARD_PRESCALER AT91C_PMC_MDIV_2
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Local functions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Default spurious interrupt handler
|
||||
//------------------------------------------------------------------------------
|
||||
void DefaultSpuriousHandler(void)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Default handler for fast interrupt requests.
|
||||
//------------------------------------------------------------------------------
|
||||
void DefaultFiqHandler(void)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Default handler for standard interrupt requests.
|
||||
//------------------------------------------------------------------------------
|
||||
void DefaultIrqHandler(void)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Global functions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Performs the low-level initialization of the chip.
|
||||
//------------------------------------------------------------------------------
|
||||
void LowLevelInit(void)
|
||||
{
|
||||
unsigned char i;
|
||||
|
||||
// Set flash wait states
|
||||
//----------------------
|
||||
AT91C_BASE_EFC->EFC_FMR = 6 << 8;
|
||||
|
||||
//#if !defined(sdram)
|
||||
// Initialize main oscillator
|
||||
//---------------------------
|
||||
AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
|
||||
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
|
||||
|
||||
// Initialize PLLA at 200MHz (198.656)
|
||||
AT91C_BASE_PMC->PMC_PLLAR = BOARD_CKGR_PLLA
|
||||
| BOARD_PLLACOUNT
|
||||
| BOARD_MULA
|
||||
| BOARD_DIVA;
|
||||
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
|
||||
|
||||
// Initialize PLLB for USB usage
|
||||
AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV
|
||||
| BOARD_CKGR_PLLB
|
||||
| BOARD_PLLBCOUNT
|
||||
| BOARD_MULB
|
||||
| BOARD_DIVB;
|
||||
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB));
|
||||
|
||||
// Wait for the master clock if it was already initialized
|
||||
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
|
||||
|
||||
// Switch to fast clock
|
||||
//---------------------
|
||||
// Switch to main oscillator + prescaler
|
||||
AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER;
|
||||
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
|
||||
|
||||
// Switch to PLL + prescaler
|
||||
AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
|
||||
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
|
||||
//#endif //#if !defined(sdram)
|
||||
|
||||
// Initialize AIC
|
||||
//---------------
|
||||
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
|
||||
AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) DefaultFiqHandler;
|
||||
for (i = 1; i < 31; i++) {
|
||||
|
||||
AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) DefaultIrqHandler;
|
||||
}
|
||||
AT91C_BASE_AIC->AIC_SPU = (unsigned int) DefaultSpuriousHandler;
|
||||
|
||||
// Unstack nested interrupts
|
||||
for (i = 0; i < 8 ; i++) {
|
||||
|
||||
AT91C_BASE_AIC->AIC_EOICR = 0;
|
||||
}
|
||||
|
||||
// Watchdog initialization
|
||||
//------------------------
|
||||
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
|
||||
|
||||
// Remap
|
||||
//------
|
||||
BOARD_RemapRam();
|
||||
|
||||
// Disable RTT and PIT interrupts (potential problem when program A
|
||||
// configures RTT, then program B wants to use PIT only, interrupts
|
||||
// from the RTT will still occur since they both use AT91C_ID_SYS)
|
||||
AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);
|
||||
AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,304 @@
|
|||
/* ----------------------------------------------------------------------------
|
||||
* ATMEL Microcontroller Software Support
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Headers
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#include <board.h>
|
||||
#include <pio/pio.h>
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Local macros
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/// Reads a register value. Useful to add trace information to read accesses.
|
||||
#define READ(peripheral, register) (peripheral->register)
|
||||
/// Writes data in a register. Useful to add trace information to write accesses.
|
||||
#define WRITE(peripheral, register, value) (peripheral->register = value)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Global functions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Changes the mapping of the chip so that the remap area mirrors the
|
||||
/// internal ROM or the EBI CS0 (depending on the BMS input).
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_RemapRom(void)
|
||||
{
|
||||
WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Changes the mapping of the chip so that the remap area mirrors the
|
||||
/// internal RAM.
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_RemapRam(void)
|
||||
{
|
||||
WRITE(AT91C_BASE_MATRIX,
|
||||
MATRIX_MRCR,
|
||||
(AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Initialize and configure the external SDRAM.
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_ConfigureSdram(void)
|
||||
{
|
||||
volatile unsigned int i;
|
||||
static const Pin pinsSdram = PINS_SDRAM;
|
||||
volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
|
||||
|
||||
// Enable corresponding PIOs
|
||||
PIO_Configure(&pinsSdram, 1);
|
||||
|
||||
// Enable EBI chip select for the SDRAM
|
||||
WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
|
||||
|
||||
|
||||
// CFG Control Register
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
|
||||
| AT91C_SDRAMC_NR_13
|
||||
| AT91C_SDRAMC_CAS_2
|
||||
| AT91C_SDRAMC_NB_4_BANKS
|
||||
| AT91C_SDRAMC_DBW_32_BITS
|
||||
| AT91C_SDRAMC_TWR_2
|
||||
| AT91C_SDRAMC_TRC_7
|
||||
| AT91C_SDRAMC_TRP_2
|
||||
| AT91C_SDRAMC_TRCD_2
|
||||
| AT91C_SDRAMC_TRAS_5
|
||||
| AT91C_SDRAMC_TXSR_8);
|
||||
|
||||
for (i = 0; i < 1000; i++);
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
|
||||
pSdram[0] = 0x00000000;
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
|
||||
pSdram[0] = 0x00000000; // Perform PRCHG
|
||||
|
||||
for (i = 0; i < 10000; i++);
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
|
||||
pSdram[1] = 0x00000001; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
|
||||
pSdram[2] = 0x00000002; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
|
||||
pSdram[3] = 0x00000003; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
|
||||
pSdram[4] = 0x00000004; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
|
||||
pSdram[5] = 0x00000005; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
|
||||
pSdram[6] = 0x00000006; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
|
||||
pSdram[7] = 0x00000007; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
|
||||
pSdram[8] = 0x00000008; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
|
||||
pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
|
||||
pSdram[0] = 0x00000000; // Perform Normal mode
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_ConfigureSdram48MHz(void)
|
||||
{
|
||||
volatile unsigned int i;
|
||||
static const Pin pinsSdram = PINS_SDRAM;
|
||||
volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
|
||||
|
||||
// Enable corresponding PIOs
|
||||
PIO_Configure(&pinsSdram, 1);
|
||||
|
||||
// Enable EBI chip select for the SDRAM
|
||||
WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
|
||||
|
||||
|
||||
// CFG Control Register
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
|
||||
| AT91C_SDRAMC_NR_13
|
||||
| AT91C_SDRAMC_CAS_2
|
||||
| AT91C_SDRAMC_NB_4_BANKS
|
||||
| AT91C_SDRAMC_DBW_32_BITS
|
||||
| AT91C_SDRAMC_TWR_1
|
||||
| AT91C_SDRAMC_TRC_4
|
||||
| AT91C_SDRAMC_TRP_1
|
||||
| AT91C_SDRAMC_TRCD_1
|
||||
| AT91C_SDRAMC_TRAS_2
|
||||
| AT91C_SDRAMC_TXSR_3);
|
||||
|
||||
for (i = 0; i < 1000; i++);
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
|
||||
pSdram[0] = 0x00000000;
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
|
||||
pSdram[0] = 0x00000000; // Perform PRCHG
|
||||
|
||||
for (i = 0; i < 10000; i++);
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
|
||||
pSdram[1] = 0x00000001; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
|
||||
pSdram[2] = 0x00000002; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
|
||||
pSdram[3] = 0x00000003; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
|
||||
pSdram[4] = 0x00000004; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
|
||||
pSdram[5] = 0x00000005; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
|
||||
pSdram[6] = 0x00000006; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
|
||||
pSdram[7] = 0x00000007; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
|
||||
pSdram[8] = 0x00000008; // Perform CBR
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
|
||||
pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer
|
||||
|
||||
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
|
||||
pSdram[0] = 0x00000000; // Perform Normal mode
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Configures the EBI for NandFlash access. Pins must be configured after or
|
||||
/// before calling this function.
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_ConfigureNandFlash(unsigned char busWidth)
|
||||
{
|
||||
// Configure EBI
|
||||
AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;
|
||||
|
||||
// Configure SMC
|
||||
AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;
|
||||
AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;
|
||||
AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
|
||||
AT91C_BASE_SMC->SMC_CTRL3 = 0x00002003;
|
||||
|
||||
if (busWidth == 8) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
|
||||
}
|
||||
else if (busWidth == 16) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
|
||||
}
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
|
||||
/// after or before calling this function.
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
|
||||
{
|
||||
// Configure EBI
|
||||
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;
|
||||
|
||||
// Configure SMC
|
||||
AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
|
||||
AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;
|
||||
AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;
|
||||
AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE
|
||||
| AT91C_SMC_WRITEMODE
|
||||
| AT91C_SMC_NWAITM_NWAIT_DISABLE
|
||||
| ((0x1 << 16) & AT91C_SMC_TDF));
|
||||
|
||||
if (busWidth == 8) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
|
||||
}
|
||||
else if (busWidth == 16) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
|
||||
}
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Configures the EBI for NorFlash access at 48MHz.
|
||||
/// \Param busWidth Bus width
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)
|
||||
{
|
||||
// Configure SMC
|
||||
AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;
|
||||
AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;
|
||||
AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;
|
||||
AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE
|
||||
| AT91C_SMC_WRITEMODE
|
||||
| AT91C_SMC_NWAITM_NWAIT_DISABLE
|
||||
| ((0x1 << 16) & AT91C_SMC_TDF));
|
||||
|
||||
if (busWidth == 8) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
|
||||
}
|
||||
else if (busWidth == 16) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
|
||||
}
|
||||
else if (busWidth == 32) {
|
||||
|
||||
AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
|
||||
}
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// Set flash wait states in the EFC for 48MHz
|
||||
//------------------------------------------------------------------------------
|
||||
void BOARD_ConfigureFlash48MHz(void)
|
||||
{
|
||||
// Set flash wait states
|
||||
//----------------------
|
||||
AT91C_BASE_EFC->EFC_FMR = 6 << 8;
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/* ----------------------------------------------------------------------------
|
||||
* ATMEL Microcontroller Software Support
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifndef BOARD_MEMORIES_H
|
||||
#define BOARD_MEMORIES_H
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Global functions
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
extern void BOARD_RemapRom(void);
|
||||
|
||||
extern void BOARD_RemapRam(void);
|
||||
|
||||
extern void BOARD_ConfigureSdram(void);
|
||||
|
||||
extern void BOARD_ConfigureSdram48MHz(void);
|
||||
|
||||
extern void BOARD_ConfigureNandFlash(unsigned char busWidth);
|
||||
|
||||
extern void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth);
|
||||
|
||||
extern void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth);
|
||||
|
||||
extern void BOARD_ConfigureFlash48MHz(void);
|
||||
|
||||
#endif //#ifndef BOARD_MEMORIES_H
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue