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Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
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114
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) )
#define configMAX_TASK_NAME_LEN ( 3 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 0
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */
#endif /* FREERTOS_CONFIG_H */

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FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h Normal file
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#ifndef DRIVER_LIB_H
#define DRIVER_LIB_H
#include "DriverLib.h"
#include "hw_adc.h"
#include "hw_comp.h"
#include "hw_flash.h"
#include "hw_gpio.h"
#include "hw_i2c.h"
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_nvic.h"
#include "hw_pwm.h"
#include "hw_qei.h"
#include "hw_ssi.h"
#include "hw_sysctl.h"
#include "hw_timer.h"
#include "hw_types.h"
#include "hw_uart.h"
#include "hw_watchdog.h"
#include "osram96x16.h"
#include "src\adc.h"
#include "src\comp.h"
#include "src\cpu.h"
#include "src\debug.h"
#include "src\flash.h"
#include "src\gpio.h"
#include "src\i2c.h"
#include "src\interrupt.h"
#include "src\pwm.h"
#include "src\qei.h"
#include "src\ssi.h"
#include "src\sysctl.h"
#include "src\systick.h"
#include "src\timer.h"
#include "src\uart.h"
#include "src\watchdog.h"
#endif

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FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h Normal file
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//*****************************************************************************
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following define the offsets of the ADC registers.
//
//*****************************************************************************
#define ADC_O_ACTSS 0x00000000 // Active sample register
#define ADC_O_RIS 0x00000004 // Raw interrupt status register
#define ADC_O_IM 0x00000008 // Interrupt mask register
#define ADC_O_ISC 0x0000000C // Interrupt status/clear register
#define ADC_O_OSTAT 0x00000010 // Overflow status register
#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.
#define ADC_O_USTAT 0x00000018 // Underflow status register
#define ADC_O_SSPRI 0x00000020 // Channel priority register
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
#define ADC_O_TMLB 0x00000100 // Test mode loopback register
//*****************************************************************************
//
// The following define the offsets of the ADC sequence registers.
//
//*****************************************************************************
#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
//*****************************************************************************
//
// The following define the bit fields in the ADC_ACTSS register.
//
//*****************************************************************************
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable
#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable
#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable
#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable
//*****************************************************************************
//
// The following define the bit fields in the ADC_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the ADC_IM register.
//
//*****************************************************************************
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask
//*****************************************************************************
//
// The following define the bit fields in the ADC_ISC register.
//
//*****************************************************************************
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the ADC_OSTAT register.
//
//*****************************************************************************
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow
#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow
#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow
#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow
//*****************************************************************************
//
// The following define the bit fields in the ADC_EMUX register.
//
//*****************************************************************************
#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event
#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event
#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event
#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event
#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event
#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event
#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event
#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event
#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
//*****************************************************************************
//
// The following define the bit fields in the ADC_USTAT register.
//
//*****************************************************************************
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow
#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow
#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow
#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSPRI register.
//
//*****************************************************************************
#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
//*****************************************************************************
//
// The following define the bit fields in the ADC_PSSI register.
//
//*****************************************************************************
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,
// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all
// registers.
//
//*****************************************************************************
#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
#define ADC_SSMUX_MUX7_SHIFT 28
#define ADC_SSMUX_MUX6_SHIFT 24
#define ADC_SSMUX_MUX5_SHIFT 20
#define ADC_SSMUX_MUX4_SHIFT 16
#define ADC_SSMUX_MUX3_SHIFT 12
#define ADC_SSMUX_MUX2_SHIFT 8
#define ADC_SSMUX_MUX1_SHIFT 4
#define ADC_SSMUX_MUX0_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,
// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all
// registers.
//
//*****************************************************************************
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
#define ADC_SSCTL_D7 0x10000000 // 8th differential select
#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
#define ADC_SSCTL_D6 0x01000000 // 7th differential select
#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
#define ADC_SSCTL_D5 0x00100000 // 6th differential select
#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
#define ADC_SSCTL_D4 0x00010000 // 5th differential select
#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
#define ADC_SSCTL_D3 0x00001000 // 4th differential select
#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
#define ADC_SSCTL_D0 0x00000001 // 1st differential select
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,
// ADC_SSFIFO2, and ADC_SSFIFO3 registers.
//
//*****************************************************************************
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
#define ADC_SSFIFO_DATA_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,
// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
//
//*****************************************************************************
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
//*****************************************************************************
//
// The following define the bit fields in the ADC_TMLB register.
//
//*****************************************************************************
#define ADC_TMLB_LB 0x00000001 // Loopback control signals
//*****************************************************************************
//
// The following define the bit fields in the loopback ADC data.
//
//*****************************************************************************
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
#define ADC_LB_CONT 0x00000020 // Continuation sample
#define ADC_LB_DIFF 0x00000010 // Differential sample
#define ADC_LB_TS 0x00000008 // Temperature sensor sample
#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
#endif // __HW_ADC_H__

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//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following define the offsets of the comparator registers.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
//*****************************************************************************
//
// The following define the bit fields in the COMP_MIS, COMP_RIS, and
// COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the COMP_REFCTL register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and
// COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and
// COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following define the reset values for the comparator registers.
//
//*****************************************************************************
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#endif // __HW_COMP_H__

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//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following define the offsets of the FLASH registers.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Memory address register
#define FLASH_FMD 0x400FD004 // Memory data register
#define FLASH_FMC 0x400FD008 // Memory control register
#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
#define FLASH_USECRL 0x400FE140 // uSec reload register
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit user register
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMIS register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE
// registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following define the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
//*****************************************************************************
//
// The erase size is the size of the FLASH block that is erased by an erase
// operation, and the protect size is the size of the FLASH block that is
// protected by each protection register.
//
//*****************************************************************************
#define FLASH_ERASE_SIZE 0x00000400
#define FLASH_PROTECT_SIZE 0x00000800
#endif // __HW_FLASH_H__

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//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// GPIO Register Offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // Data register.
#define GPIO_O_DIR 0x00000400 // Data direction register.
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
#define GPIO_O_IEV 0x0000040C // Intterupt event register.
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
#define GPIO_O_ODR 0x0000050C // Open drain select register.
#define GPIO_O_PUR 0x00000510 // Pull up select register.
#define GPIO_O_PDR 0x00000514 // Pull down select register.
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
#define GPIO_O_PeriphID4 0x00000FD0 //
#define GPIO_O_PeriphID5 0x00000FD4 //
#define GPIO_O_PeriphID6 0x00000FD8 //
#define GPIO_O_PeriphID7 0x00000FDC //
#define GPIO_O_PeriphID0 0x00000FE0 //
#define GPIO_O_PeriphID1 0x00000FE4 //
#define GPIO_O_PeriphID2 0x00000FE8 //
#define GPIO_O_PeriphID3 0x00000FEC //
#define GPIO_O_PCellID0 0x00000FF0 //
#define GPIO_O_PCellID1 0x00000FF4 //
#define GPIO_O_PCellID2 0x00000FF8 //
#define GPIO_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
#define GPIO_RV_PeriphID4 0x00000000 //
#define GPIO_RV_PeriphID5 0x00000000 //
#define GPIO_RV_PeriphID6 0x00000000 //
#define GPIO_RV_PeriphID7 0x00000000 //
#define GPIO_RV_PeriphID0 0x00000061 //
#define GPIO_RV_PeriphID1 0x00000010 //
#define GPIO_RV_PeriphID2 0x00000004 //
#define GPIO_RV_PeriphID3 0x00000000 //
#define GPIO_RV_PCellID0 0x0000000D //
#define GPIO_RV_PCellID1 0x000000F0 //
#define GPIO_RV_PCellID2 0x00000005 //
#define GPIO_RV_PCellID3 0x000000B1 //
#endif // __HW_GPIO_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following defines the offset between the I2C master and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following define the offsets of the I2C master registers.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following define the offsets of the I2C slave registers.
//
//*****************************************************************************
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
//*****************************************************************************
//
// The followng define the bit fields in the I2C master slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Control and Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
//*****************************************************************************
//
// The following define values used in determining the contents of the I2C
// Master Timer Period register.
//
//*****************************************************************************
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_SCL_FAST 400000 // SCL fast frequency
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Configuration
// register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Own Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Control/Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Clear
// register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
#endif // __HW_I2C_H__

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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following define the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following define the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
//*****************************************************************************
//
// The total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 46
//*****************************************************************************
//
// The total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following define the base address of the memories and peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI_BASE 0x40008000 // SSI
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define ADC_BASE 0x40038000 // ADC
#define COMP_BASE 0x4003C000 // Analog comparators
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
#endif // __HW_MEMMAP_H__

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//*****************************************************************************
//
// hw_nvic.h - Macros used when accessing the NVIC hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_NVIC_H__
#define __HW_NVIC_H__
//*****************************************************************************
//
// The following define the addresses of the NVIC registers.
//
//*****************************************************************************
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
//*****************************************************************************
//
// The following define the bit fields in the NVIC_INT_TYPE register.
//
//*****************************************************************************
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
#define NVIC_INT_TYPE_LINES_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CTRL register.
//
//*****************************************************************************
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_RELOAD register.
//
//*****************************************************************************
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
#define NVIC_ST_RELOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CURRENT register.
//
//*****************************************************************************
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
#define NVIC_ST_CURRENT_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CAL register.
//
//*****************************************************************************
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
#define NVIC_ST_CAL_ONEMS_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EN0 register.
//
//*****************************************************************************
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DIS0 register.
//
//*****************************************************************************
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PEND0 register.
//
//*****************************************************************************
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
//*****************************************************************************
//
// The following define the bit fields in the NVIC_UNPEND0 register.
//
//*****************************************************************************
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ACTIVE0 register.
//
//*****************************************************************************
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI0 register.
//
//*****************************************************************************
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
#define NVIC_PRI0_INT3_S 24
#define NVIC_PRI0_INT2_S 16
#define NVIC_PRI0_INT1_S 8
#define NVIC_PRI0_INT0_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI1 register.
//
//*****************************************************************************
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
#define NVIC_PRI1_INT7_S 24
#define NVIC_PRI1_INT6_S 16
#define NVIC_PRI1_INT5_S 8
#define NVIC_PRI1_INT4_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI2 register.
//
//*****************************************************************************
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
#define NVIC_PRI2_INT11_S 24
#define NVIC_PRI2_INT10_S 16
#define NVIC_PRI2_INT9_S 8
#define NVIC_PRI2_INT8_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI3 register.
//
//*****************************************************************************
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
#define NVIC_PRI3_INT15_S 24
#define NVIC_PRI3_INT14_S 16
#define NVIC_PRI3_INT13_S 8
#define NVIC_PRI3_INT12_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI4 register.
//
//*****************************************************************************
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
#define NVIC_PRI4_INT19_S 24
#define NVIC_PRI4_INT18_S 16
#define NVIC_PRI4_INT17_S 8
#define NVIC_PRI4_INT16_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI5 register.
//
//*****************************************************************************
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
#define NVIC_PRI5_INT23_S 24
#define NVIC_PRI5_INT22_S 16
#define NVIC_PRI5_INT21_S 8
#define NVIC_PRI5_INT20_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI6 register.
//
//*****************************************************************************
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
#define NVIC_PRI6_INT27_S 24
#define NVIC_PRI6_INT26_S 16
#define NVIC_PRI6_INT25_S 8
#define NVIC_PRI6_INT24_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI7 register.
//
//*****************************************************************************
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
#define NVIC_PRI7_INT31_S 24
#define NVIC_PRI7_INT30_S 16
#define NVIC_PRI7_INT29_S 8
#define NVIC_PRI7_INT28_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_CPUID register.
//
//*****************************************************************************
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
#define NVIC_CPUID_REV_M 0x0000000F // Revision
//*****************************************************************************
//
// The following define the bit fields in the NVIC_INT_CTRL register.
//
//*****************************************************************************
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
#define NVIC_INT_CTRL_VEC_PEN_S 12
#define NVIC_INT_CTRL_VEC_ACT_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_VTABLE register.
//
//*****************************************************************************
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
#define NVIC_VTABLE_OFFSET_S 8
//*****************************************************************************
//
// The following define the bit fields in the NVIC_APINT register.
//
//*****************************************************************************
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
//*****************************************************************************
//
// The following define the bit fields in the NVIC_CFG_CTRL register.
//
//*****************************************************************************
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI1 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
#define NVIC_SYS_PRI1_USAGE_S 16
#define NVIC_SYS_PRI1_BUS_S 8
#define NVIC_SYS_PRI1_MEM_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI2 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
#define NVIC_SYS_PRI2_SVC_S 24
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI3 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
#define NVIC_SYS_PRI3_TICK_S 24
#define NVIC_SYS_PRI3_PENDSV_S 16
#define NVIC_SYS_PRI3_DEBUG_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_HND_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_STAT register.
//
//*****************************************************************************
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
//*****************************************************************************
//
// The following define the bit fields in the NVIC_HFAULT_STAT register.
//
//*****************************************************************************
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DEBUG_STAT register.
//
//*****************************************************************************
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MM_ADDR register.
//
//*****************************************************************************
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
#define NVIC_MM_ADDR_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_ADDR register.
//
//*****************************************************************************
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
#define NVIC_FAULT_ADDR_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_STACK register.
//
//*****************************************************************************
#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_NUM register.
//
//*****************************************************************************
#define NVIC_EXC_NUM_M 0x000003FF // Exception number
#define NVIC_EXC_NUM_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_COPRO register.
//
//*****************************************************************************
#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask
#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied
#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess
#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access
#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask
#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied
#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess
#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access
#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask
#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied
#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess
#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access
#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask
#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied
#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess
#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access
#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask
#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied
#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess
#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access
#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask
#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied
#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess
#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access
#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask
#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied
#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess
#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access
#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask
#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied
#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess
#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access
#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask
#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied
#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess
#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access
#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask
#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied
#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess
#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access
#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask
#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied
#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess
#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access
#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask
#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied
#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess
#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access
#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask
#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied
#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess
#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access
#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask
#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied
#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess
#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access
#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask
#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied
#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess
#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access
#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask
#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied
#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess
#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_TYPE register.
//
//*****************************************************************************
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
#define NVIC_MPU_TYPE_IREGION_S 16
#define NVIC_MPU_TYPE_DREGION_S 8
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_CTRL register.
//
//*****************************************************************************
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_NUMBER register.
//
//*****************************************************************************
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
#define NVIC_MPU_NUMBER_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_BASE register.
//
//*****************************************************************************
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
#define NVIC_MPU_BASE_ADDR_S 8
#define NVIC_MPU_BASE_REGION_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_ATTR register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes
#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable
#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_CTRL register.
//
//*****************************************************************************
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_XFER register.
//
//*****************************************************************************
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_DATA register.
//
//*****************************************************************************
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
#define NVIC_DBG_DATA_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_INT register.
//
//*****************************************************************************
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
#define NVIC_SW_TRIG_INTID_S 0
#endif // __HW_NVIC_H__

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//*****************************************************************************
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_PWM_H__
#define __HW_PWM_H__
//*****************************************************************************
//
// PWM Module Register Offsets.
//
//*****************************************************************************
#define PWM_O_CTL 0x00000000 // PWM Master Control register
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
#define PWM_O_STATUS 0x00000020 // PWM Status register
//*****************************************************************************
//
// The following define the bit fields in the PWM Master Control register.
//
//*****************************************************************************
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
//*****************************************************************************
//
// The following define the bit fields in the PWM Time Base Sync register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
//*****************************************************************************
//
// The following define the bit fields in the PWM Output Enable register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
//*****************************************************************************
//
// The following define the bit fields in the PWM Inversion register.
//
//*****************************************************************************
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
//*****************************************************************************
//
// The following define the bit fields in the PWM Fault register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault
#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault
#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault
#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault
#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault
//*****************************************************************************
//
// PWM Interrupt Register bit definitions.
//
//*****************************************************************************
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
//*****************************************************************************
//
// The following define the bit fields in the PWM Status register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT 0x00000001 // Fault status
//*****************************************************************************
//
// PWM Generator standard offsets.
//
//*****************************************************************************
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
//*****************************************************************************
//
// PWM_X Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
//*****************************************************************************
//
// PWM_X Interrupt/Trigger Enable Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// PWM_X Raw Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
//*****************************************************************************
//
// PWM_X Interrupt Status Register bit definitions.
//
//*****************************************************************************
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
//*****************************************************************************
//
// PWM_X Generator A/B Control Register bit definitions.
//
//*****************************************************************************
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
//*****************************************************************************
//
// PWM_X Generator A/B Control Register action definitions.
//
//*****************************************************************************
#define PWM_GEN_ACT_NONE 0x0 // Do nothing
#define PWM_GEN_ACT_INV 0x1 // Invert the output signal
#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero
#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
//*****************************************************************************
//
// PWM_X Dead Band Control Register bit definitions.
//
//*****************************************************************************
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
//*****************************************************************************
//
// PWM Register reset values.
//
//*****************************************************************************
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM
// output pins
#define PWM_RV_INVERT 0x00000000 // Inversion control for
// PWM output pins
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
// output pins
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_STATUS 0x00000000 // Status
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
// generator block
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
// count
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
// count
#endif // __HW_PWM_H__

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//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following define the offsets of the QEI registers.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // Configuration and control reg.
#define QEI_O_STAT 0x00000004 // Status register
#define QEI_O_POS 0x00000008 // Current position register
#define QEI_O_MAXPOS 0x0000000C // Maximum position register
#define QEI_O_LOAD 0x00000010 // Velocity timer load register
#define QEI_O_TIME 0x00000014 // Velocity timer register
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
#define QEI_O_SPEED 0x0000001C // Velocity speed register
#define QEI_O_INTEN 0x00000020 // Interrupt enable register
#define QEI_O_RIS 0x00000024 // Raw interrupt status register
#define QEI_O_ISC 0x00000028 // Interrupt status register
//*****************************************************************************
//
// The following define the bit fields in the QEI_CTL register.
//
//*****************************************************************************
#define QEI_CTL_STALLEN 0x00001000 // Stall enable
#define QEI_CTL_INVI 0x00000800 // Invert Index input
#define QEI_CTL_INVB 0x00000400 // Invert PhB input
#define QEI_CTL_INVA 0x00000200 // Invert PhA input
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
#define QEI_CTL_VELEN 0x00000020 // Velocity enable
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
#define QEI_CTL_SWAP 0x00000002 // Swap input signals
#define QEI_CTL_ENABLE 0x00000001 // QEI enable
//*****************************************************************************
//
// The following define the bit fields in the QEI_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current encoder position
#define QEI_POS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following define the bit fields in the QEI_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
#define QEI_INTEN_DIR 0x00000004 // Direction change
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase error detected
#define QEI_RIS_DIR 0x00000004 // Direction change
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the bit fields in the QEI_ISC register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following define the reset values for the QEI registers.
//
//*****************************************************************************
#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#endif // __HW_QEI_H__

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//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following define the offsets of the SSI registers.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // Control register 0
#define SSI_O_CR1 0x00000004 // Control register 1
#define SSI_O_DR 0x00000008 // Data register
#define SSI_O_SR 0x0000000C // Status register
#define SSI_O_CPSR 0x00000010 // Clock prescale register
#define SSI_O_IM 0x00000014 // Int mask set and clear register
#define SSI_O_RIS 0x00000018 // Raw interrupt register
#define SSI_O_MIS 0x0000001C // Masked interrupt register
#define SSI_O_ICR 0x00000020 // Interrupt clear register
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
#define SSI_CR0_DSS 0x0000000F // Data size select
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
#define SSI_CR1_LBM 0x00000001 // Loopback mode
//*****************************************************************************
//
// The following define the bit fields in the SSI Status register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy
#define SSI_SR_RFF 0x00000008 // RX FIFO full
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
//*****************************************************************************
//
// The following define the bit fields in the SSI clock prescale register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following define information concerning the SSI Data register.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following define the bit fields in the interrupt mask set and clear,
// raw interrupt, masked interrupt, and interrupt clear registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SYSCTL_H__
#define __HW_SYSCTL_H__
//*****************************************************************************
//
// The following define the offsets of the system control registers.
//
//*****************************************************************************
#define SYSCTL_DID0 0x400fe000 // Device identification register 0
#define SYSCTL_DID1 0x400fe004 // Device identification register 1
#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
#define SYSCTL_MISC 0x400fe058 // Interrupt status register
#define SYSCTL_RESC 0x400fe05c // Reset cause register
#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID0 register.
//
//*****************************************************************************
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID1 register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
#define SYSCTL_DID1_PRTNO_SHIFT 16
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
#define SYSCTL_DC2_I2C 0x00001000 // I2C present
#define SYSCTL_DC2_QEI 0x00000100 // QEI present
#define SYSCTL_DC2_SSI 0x00000010 // SSI present
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC3 register.
//
//*****************************************************************************
#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC4 register.
//
//*****************************************************************************
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PBORCTL register.
//
//*****************************************************************************
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
#define SYSCTL_PBORCTL_BOR_SH 2
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOPCTL register.
//
//*****************************************************************************
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
//
//*****************************************************************************
#define SYSCTL_SET0_PWM 0x00100000 // PWM module
#define SYSCTL_SET0_ADC 0x00010000 // ADC module
#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
//
//*****************************************************************************
#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
#define SYSCTL_SET1_I2C 0x00001000 // I2C module
#define SYSCTL_SET1_QEI 0x00000100 // QEI module
#define SYSCTL_SET1_SSI 0x00000010 // SSI module
#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
//
//*****************************************************************************
#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
// SYSCTL_IMS registers.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RESC register.
//
//*****************************************************************************
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
#define SYSCTL_RESC_SW 0x00000010 // Software reset
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
#define SYSCTL_RESC_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RCC register.
//
//*****************************************************************************
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PLLCFG register.
//
//*****************************************************************************
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
#define SYSCTL_PLLCFG_F_SHIFT 5
#define SYSCTL_PLLCFG_R_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_CLKVCLR register.
//
//*****************************************************************************
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOARST register.
//
//*****************************************************************************
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
#endif // __HW_SYSCTL_H__

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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following define the offsets of the timer registers.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // Configuration register
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
#define TIMER_O_CTL 0x0000000C // Control register
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
#define TIMER_O_RIS 0x0000001C // Interrupt status register
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
//*****************************************************************************
//
// The following define the reset values of the timer registers.
//
//*****************************************************************************
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TnMR register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
//*****************************************************************************
//
// The following define the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
//*****************************************************************************
//
// The following define the bit fields in the TIMER_MIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following define the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPR register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPMR register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
#endif // __HW_TIMER_H__

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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#endif // __HW_TYPES_H__

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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// UART Register Offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // Data Register
#define UART_O_RSR 0x00000004 // Receive Status Register (read)
#define UART_O_ECR 0x00000004 // Error Clear Register (write)
#define UART_O_FR 0x00000018 // Flag Register (read only)
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_CTL 0x00000030 // Control Register
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
#define UART_O_PeriphID4 0x00000FD0 //
#define UART_O_PeriphID5 0x00000FD4 //
#define UART_O_PeriphID6 0x00000FD8 //
#define UART_O_PeriphID7 0x00000FDC //
#define UART_O_PeriphID0 0x00000FE0 //
#define UART_O_PeriphID1 0x00000FE4 //
#define UART_O_PeriphID2 0x00000FE8 //
#define UART_O_PeriphID3 0x00000FEC //
#define UART_O_PCellID0 0x00000FF0 //
#define UART_O_PCellID1 0x00000FF4 //
#define UART_O_PCellID2 0x00000FF8 //
#define UART_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// Data Register bits
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // Overrun Error
#define UART_DR_BE 0x00000400 // Break Error
#define UART_DR_PE 0x00000200 // Parity Error
#define UART_DR_FE 0x00000100 // Framing Error
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // Overrun Error
#define UART_RSR_BE 0x00000004 // Break Error
#define UART_RSR_PE 0x00000002 // Parity Error
#define UART_RSR_FE 0x00000001 // Framing Error
//*****************************************************************************
//
// Flag Register bits
//
//*****************************************************************************
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
#define UART_FR_RXFF 0x00000040 // RX FIFO Full
#define UART_FR_TXFF 0x00000020 // TX FIFO Full
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
//*****************************************************************************
//
// Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// Line Control Register High bits
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// Control Register bits
//
//*****************************************************************************
#define UART_CTL_RXE 0x00000200 // Receive Enable
#define UART_CTL_TXE 0x00000100 // Transmit Enable
#define UART_CTL_LBE 0x00000080 // Loopback Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full
#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full
#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full
#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
//*****************************************************************************
//
// Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
//*****************************************************************************
//
// Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
//*****************************************************************************
//
// Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_RSR_ANY (UART_RSR_OE | \
UART_RSR_BE | \
UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// Reset Values for UART Registers.
//
//*****************************************************************************
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_FR 0x00000090
#define UART_RV_IBRD 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_CTL 0x00000300
#define UART_RV_IFLS 0x00000012
#define UART_RV_IM 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PCellID3 0x000000B1
#endif // __HW_UART_H__

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//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following define the offsets of the Watchdog Timer registers.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_LOCK 0x00000C00 // Lock register
#define WDT_O_PeriphID4 0x00000FD0 //
#define WDT_O_PeriphID5 0x00000FD4 //
#define WDT_O_PeriphID6 0x00000FD8 //
#define WDT_O_PeriphID7 0x00000FDC //
#define WDT_O_PeriphID0 0x00000FE0 //
#define WDT_O_PeriphID1 0x00000FE4 //
#define WDT_O_PeriphID2 0x00000FE8 //
#define WDT_O_PeriphID3 0x00000FEC //
#define WDT_O_PCellID0 0x00000FF0 //
#define WDT_O_PCellID1 0x00000FF4 //
#define WDT_O_PCellID2 0x00000FF8 //
#define WDT_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// The following define the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
// registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following define the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
#ifndef DEPRECATED
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
#endif
//*****************************************************************************
//
// The following define the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following define the reset values for the WDT registers.
//
//*****************************************************************************
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_PeriphID4 0x00000000 //
#define WDT_RV_PeriphID5 0x00000000 //
#define WDT_RV_PeriphID6 0x00000000 //
#define WDT_RV_PeriphID7 0x00000000 //
#define WDT_RV_PeriphID0 0x00000005 //
#define WDT_RV_PeriphID1 0x00000018 //
#define WDT_RV_PeriphID2 0x00000018 //
#define WDT_RV_PeriphID3 0x00000001 //
#define WDT_RV_PCellID0 0x0000000D //
#define WDT_RV_PCellID1 0x000000F0 //
#define WDT_RV_PCellID2 0x00000005 //
#define WDT_RV_PCellID3 0x000000B1 //
#endif // __HW_WATCHDOG_H__

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//*****************************************************************************
//
// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ev_lm3s811_api
//! @{
//
//*****************************************************************************
#include "hw_i2c.h"
#include "hw_memmap.h"
#include "hw_sysctl.h"
#include "hw_types.h"
#include "src/debug.h"
#include "src/gpio.h"
#include "src/i2c.h"
#include "src/sysctl.h"
#include "osram96x16.h"
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, tBoolean bFast);
//*****************************************************************************
//
// The I2C slave address of the SSD0303 controller on the OLED display.
//
//*****************************************************************************
#define SSD0303_ADDR 0x3d
//*****************************************************************************
//
// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this
// table) for displaying text on the OLED display. The data is organized as
// bytes from the left column to the right column, with each byte containing
// the top row in the LSB and the bottom row in the MSB.
//
//*****************************************************************************
static const unsigned char g_pucFont[95][5] =
{
{ 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "
{ 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !
{ 0x00, 0x07, 0x00, 0x07, 0x00 }, // "
{ 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #
{ 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $
{ 0x23, 0x13, 0x08, 0x64, 0x62 }, // %
{ 0x36, 0x49, 0x55, 0x22, 0x50 }, // &
{ 0x00, 0x05, 0x03, 0x00, 0x00 }, // '
{ 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (
{ 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )
{ 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *
{ 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +
{ 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,
{ 0x08, 0x08, 0x08, 0x08, 0x08 }, // -
{ 0x00, 0x60, 0x60, 0x00, 0x00 }, // .
{ 0x20, 0x10, 0x08, 0x04, 0x02 }, // /
{ 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0
{ 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1
{ 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2
{ 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3
{ 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4
{ 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5
{ 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6
{ 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7
{ 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8
{ 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9
{ 0x00, 0x36, 0x36, 0x00, 0x00 }, // :
{ 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;
{ 0x08, 0x14, 0x22, 0x41, 0x00 }, // <
{ 0x14, 0x14, 0x14, 0x14, 0x14 }, // =
{ 0x00, 0x41, 0x22, 0x14, 0x08 }, // >
{ 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?
{ 0x32, 0x49, 0x79, 0x41, 0x3e }, // @
{ 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A
{ 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B
{ 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C
{ 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D
{ 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E
{ 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F
{ 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G
{ 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H
{ 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I
{ 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J
{ 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K
{ 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L
{ 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M
{ 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N
{ 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O
{ 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P
{ 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q
{ 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R
{ 0x46, 0x49, 0x49, 0x49, 0x31 }, // S
{ 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T
{ 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U
{ 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V
{ 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W
{ 0x63, 0x14, 0x08, 0x14, 0x63 }, // X
{ 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y
{ 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z
{ 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [
{ 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"
{ 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]
{ 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^
{ 0x40, 0x40, 0x40, 0x40, 0x40 }, // _
{ 0x00, 0x01, 0x02, 0x04, 0x00 }, // `
{ 0x20, 0x54, 0x54, 0x54, 0x78 }, // a
{ 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b
{ 0x38, 0x44, 0x44, 0x44, 0x20 }, // c
{ 0x38, 0x44, 0x44, 0x48, 0x7f }, // d
{ 0x38, 0x54, 0x54, 0x54, 0x18 }, // e
{ 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f
{ 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g
{ 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h
{ 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i
{ 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j
{ 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k
{ 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l
{ 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m
{ 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n
{ 0x38, 0x44, 0x44, 0x44, 0x38 }, // o
{ 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p
{ 0x08, 0x14, 0x14, 0x18, 0x7c }, // q
{ 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r
{ 0x48, 0x54, 0x54, 0x54, 0x20 }, // s
{ 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t
{ 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u
{ 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v
{ 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w
{ 0x44, 0x28, 0x10, 0x28, 0x44 }, // x
{ 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y
{ 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z
{ 0x00, 0x08, 0x36, 0x41, 0x00 }, // {
{ 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |
{ 0x00, 0x41, 0x36, 0x08, 0x00 }, // }
{ 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~
};
//*****************************************************************************
//
// The sequence of commands used to initialize the SSD0303 controller. Each
// command is described as follows: there is a byte specifying the number of
// bytes in the I2C transfer, followed by that many bytes of command data.
//
//*****************************************************************************
static const unsigned char g_pucOSRAMInit[] =
{
//
// Turn off the panel
//
0x02, 0x80, 0xae,
//
// Set lower column address
//
0x02, 0x80, 0x04,
//
// Set higher column address
//
0x02, 0x80, 0x12,
//
// Set contrast control register
//
0x04, 0x80, 0x81, 0x80, 0x2b,
//
// Set segment re-map
//
0x02, 0x80, 0xa1,
//
// Set display start line
//
0x02, 0x80, 0x40,
//
// Set display offset
//
0x04, 0x80, 0xd3, 0x80, 0x00,
//
// Set multiplex ratio
//
0x04, 0x80, 0xa8, 0x80, 0x0f,
//
// Set the display to normal mode
//
0x02, 0x80, 0xa4,
//
// Non-inverted display
//
0x02, 0x80, 0xa6,
//
// Set the page address
//
0x02, 0x80, 0xb0,
//
// Set COM output scan direction
//
0x02, 0x80, 0xc8,
//
// Set display clock divide ratio/oscillator frequency
//
0x04, 0x80, 0xd5, 0x80, 0x72,
//
// Enable mono mode
//
0x04, 0x80, 0xd8, 0x80, 0x00,
//
// Set pre-charge period
//
0x04, 0x80, 0xd9, 0x80, 0x22,
//
// Set COM pins hardware configuration
//
0x04, 0x80, 0xda, 0x80, 0x12,
//
// Set VCOM deslect level
//
0x04, 0x80, 0xdb, 0x80, 0x0f,
//
// Set DC-DC on
//
0x04, 0x80, 0xad, 0x80, 0x8b,
//
// Turn on the panel
//
0x02, 0x80, 0xaf,
};
//*****************************************************************************
//
// The inter-byte delay required by the SSD0303 OLED controller.
//
//*****************************************************************************
static unsigned long g_ulDelay;
//*****************************************************************************
//
//! \internal
//!
//! Provide a small delay.
//!
//! \param ulCount is the number of delay loop iterations to perform.
//!
//! Since the SSD0303 controller needs a delay between bytes written to it over
//! the I2C bus, this function provides a means of generating that delay. It
//! is written in assembly to keep the delay consistent across tool chains,
//! avoiding the need to tune the delay based on the tool chain in use.
//!
//! \return None.
//
//*****************************************************************************
#if defined(ewarm)
static void
OSRAMDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne OSRAMDelay\n"
" bx lr");
}
#endif
#if defined(gcc)
static void __attribute__((naked))
OSRAMDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne OSRAMDelay\n"
" bx lr");
}
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm void
OSRAMDelay(unsigned long ulCount)
{
subs r0, #1;
bne OSRAMDelay;
bx lr;
}
#endif
//*****************************************************************************
//
//! \internal
//!
//! Start a transfer to the SSD0303 controller.
//!
//! \param ucChar is the first byte to be written to the controller.
//!
//! This function will start a transfer to the SSD0303 controller via the I2C
//! bus.
//!
//! The data is written in a polled fashion; this function will not return
//! until the byte has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteFirst(unsigned char ucChar)
{
//
// Set the slave address.
//
I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false);
//
// Write the first byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, ucChar);
//
// Start the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);
}
//*****************************************************************************
//
//! \internal
//!
//! Write a byte to the SSD0303 controller.
//!
//! \param ucChar is the byte to be transmitted to the controller.
//!
//! This function continues a transfer to the SSD0303 controller by writing
//! another byte over the I2C bus. This must only be called after calling
//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().
//!
//! The data is written in a polled faashion; this function will not return
//! until the byte has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteByte(unsigned char ucChar)
{
//
// Wait until the current byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
//
// Write the next byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, ucChar);
//
// Continue the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);
}
//*****************************************************************************
//
//! \internal
//!
//! Write a sequence of bytes to the SSD0303 controller.
//!
//! This function continues a transfer to the SSD0303 controller by writing a
//! sequence of bytes over the I2C bus. This must only be called after calling
//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().
//!
//! The data is written in a polled fashion; this function will not return
//! until the entire byte sequence has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount)
{
//
// Loop while there are more bytes left to be transferred.
//
while(ulCount != 0)
{
//
// Wait until the current byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
//
// Write the next byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++);
ulCount--;
//
// Continue the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);
}
}
//*****************************************************************************
//
//! \internal
//!
//! Finish a transfer to the SSD0303 controller.
//!
//! \param ucChar is the final byte to be written to the controller.
//!
//! This function will finish a transfer to the SSD0303 controller via the I2C
//! bus. This must only be called after calling OSRAMWriteFirst().
//!
//! The data is written in a polled fashion; this function will not return
//! until the byte has been written to the controller.
//!
//! \return None.
//
//*****************************************************************************
static void
OSRAMWriteFinal(unsigned char ucChar)
{
//
// Wait until the current byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
//
// Write the final byte to the controller.
//
I2CMasterDataPut(I2C_MASTER_BASE, ucChar);
//
// Finish the transfer.
//
I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);
//
// Wait until the final byte has been transferred.
//
while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)
{
}
//
// Provide the required inter-byte delay.
//
OSRAMDelay(g_ulDelay);
}
//*****************************************************************************
//
//! Clears the OLED display.
//!
//! This function will clear the display. All pixels in the display will be
//! turned off.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMClear(void)
{
static const unsigned char pucRow1[] =
{
0xb0, 0x80, 0x04, 0x80, 0x12, 0x40
};
static const unsigned char pucRow2[] =
{
0xb1, 0x80, 0x04, 0x80, 0x12, 0x40
};
unsigned long ulIdx;
//
// Move the display cursor to the first column of the first row.
//
OSRAMWriteFirst(0x80);
OSRAMWriteArray(pucRow1, sizeof(pucRow1));
//
// Fill this row with zeros.
//
for(ulIdx = 0; ulIdx < 95; ulIdx++)
{
OSRAMWriteByte(0x00);
}
OSRAMWriteFinal(0x00);
//
// Move the display cursor to the first column of the second row.
//
OSRAMWriteFirst(0x80);
OSRAMWriteArray(pucRow2, sizeof(pucRow2));
//
// Fill this row with zeros.
//
for(ulIdx = 0; ulIdx < 95; ulIdx++)
{
OSRAMWriteByte(0x00);
}
OSRAMWriteFinal(0x00);
}
//*****************************************************************************
//
//! Displays a string on the OLED display.
//!
//! \param pcStr is a pointer to the string to display.
//! \param ulX is the horizontal position to display the string, specified in
//! columns from the left edge of the display.
//! \param ulY is the vertical position to display the string, specified in
//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are
//! valid).
//!
//! This function will draw a string on the display. Only the ASCII characters
//! between 32 (space) and 126 (tilde) are supported; other characters will
//! result in random data being draw on the display (based on whatever appears
//! before/after the font in memory). The font is mono-spaced, so characters
//! such as "i" and "l" have more white space around them than characters such
//! as "m" or "w".
//!
//! If the drawing of the string reaches the right edge of the display, no more
//! characters will be drawn. Therefore, special care is not required to avoid
//! supplying a string that is "too long" to display.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY)
{
//
// Check the arguments.
//
ASSERT(ulX < 96);
ASSERT(ulY < 2);
//
// Move the display cursor to the requested position on the display.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);
OSRAMWriteByte(0x80);
OSRAMWriteByte((ulX + 36) & 0x0f);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f));
OSRAMWriteByte(0x40);
//
// Loop while there are more characters in the string.
//
while(*pcStr != 0)
{
//
// See if there is enough space on the display for this entire
// character.
//
if(ulX <= 90)
{
//
// Write the contents of this character to the display.
//
OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5);
//
// See if this is the last character to display (either because the
// right edge has been reached or because there are no more
// characters).
//
if((ulX == 90) || (pcStr[1] == 0))
{
//
// Write the final column of the display.
//
OSRAMWriteFinal(0x00);
//
// The string has been displayed.
//
return;
}
//
// Write the inter-character padding column.
//
OSRAMWriteByte(0x00);
}
else
{
//
// Write the portion of the character that will fit onto the
// display.
//
OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX);
OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]);
//
// The string has been displayed.
//
return;
}
//
// Advance to the next character.
//
pcStr++;
//
// Increment the X coordinate by the six columns that were just
// written.
//
ulX += 6;
}
}
//*****************************************************************************
//
//! Displays an image on the OLED display.
//!
//! \param pucImage is a pointer to the image data.
//! \param ulX is the horizontal position to display this image, specified in
//! columns from the left edge of the display.
//! \param ulY is the vertical position to display this image, specified in
//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are
//! valid).
//! \param ulWidth is the width of the image, specified in columns.
//! \param ulHeight is the height of the image, specified in eight row blocks
//! (i.e. only 1 and 2 are valid).
//!
//! This function will display a bitmap graphic on the display. The image to
//! be displayed must be a multiple of eight scan lines high (i.e. one row) and
//! will be drawn at a vertical position that is a multiple of eight scan lines
//! (i.e. scan line zero or scan line eight, corresponding to row zero or row
//! one).
//!
//! The image data is organized with the first row of image data appearing left
//! to right, followed immediately by the second row of image data. Each byte
//! contains the data for the eight scan lines of the column, with the top scan
//! line being in the least significant bit of the byte and the bottom scan
//! line being in the most significant bit of the byte.
//!
//! For example, an image four columns wide and sixteen scan lines tall would
//! be arranged as follows (showing how the eight bytes of the image would
//! appear on the display):
//!
//! \verbatim
//! +-------+ +-------+ +-------+ +-------+
//! | | 0 | | | 0 | | | 0 | | | 0 |
//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |
//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |
//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |
//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |
//! | | 5 | | | 5 | | | 5 | | | 5 |
//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 |
//! | | 7 | | | 7 | | | 7 | | | 7 |
//! +-------+ +-------+ +-------+ +-------+
//!
//! +-------+ +-------+ +-------+ +-------+
//! | | 0 | | | 0 | | | 0 | | | 0 |
//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |
//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |
//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |
//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |
//! | | 5 | | | 5 | | | 5 | | | 5 |
//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 |
//! | | 7 | | | 7 | | | 7 | | | 7 |
//! +-------+ +-------+ +-------+ +-------+
//! \endverbatim
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,
unsigned long ulY, unsigned long ulWidth,
unsigned long ulHeight)
{
//
// Check the arguments.
//
ASSERT(ulX < 96);
ASSERT(ulY < 2);
ASSERT((ulX + ulWidth) <= 96);
ASSERT((ulY + ulHeight) <= 2);
//
// The first 36 columns of the LCD buffer are not displayed, so increment
// the X coorddinate by 36 to account for the non-displayed frame buffer
// memory.
//
ulX += 36;
//
// Loop while there are more rows to display.
//
while(ulHeight--)
{
//
// Write the starting address within this row.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);
OSRAMWriteByte(0x80);
OSRAMWriteByte(ulX & 0x0f);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f));
OSRAMWriteByte(0x40);
//
// Write this row of image data.
//
OSRAMWriteArray(pucImage, ulWidth - 1);
OSRAMWriteFinal(pucImage[ulWidth - 1]);
//
// Advance to the next row of the image.
//
pucImage += ulWidth;
ulY++;
}
}
//*****************************************************************************
//
//! Initialize the OLED display.
//!
//! \param bFast is a boolean that is \e true if the I2C interface should be
//! run at 400 kbps and \e false if it should be run at 100 kbps.
//!
//! This function initializes the I2C interface to the OLED display and
//! configures the SSD0303 controller on the panel.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMInit(tBoolean bFast)
{
unsigned long ulIdx;
//
// Enable the I2C and GPIO port B blocks as they are needed by this driver.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
//
// Configure the I2C SCL and SDA pins for I2C operation.
//
GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);
//
// Initialize the I2C master.
//
I2CMasterInitExpClk(I2C_MASTER_BASE, SysCtlClockGet(), bFast);
//
// Compute the inter-byte delay for the SSD0303 controller. This delay is
// dependent upon the I2C bus clock rate; the slower the clock the longer
// the delay required.
//
// The derivation of this formula is based on a measured delay of
// OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz
// (referred to as C). To scale this to the delay for a different CPU
// speed (since this is just a CPU-based delay loop) is:
//
// f(CPU)
// C * ----------
// 50,000,000
//
// To then scale this to the actual I2C rate (since it won't always be
// precisely 100 kHz):
//
// f(CPU) 100,000
// C * ---------- * -------
// 50,000,000 f(I2C)
//
// This equation will give the inter-byte delay required for any
// configuration of the I2C master. But, as arranged it is impossible to
// directly compute in 32-bit arithmetic (without loosing a lot of
// accuracy). So, the equation is simplified.
//
// Since f(I2C) is generated by dividing down from f(CPU), replace it with
// the equivalent (where TPR is the value programmed into the Master Timer
// Period Register of the I2C master, with the 1 added back):
//
// 100,000
// f(CPU) -------
// C * ---------- * f(CPU)
// 50,000,000 ------------
// 2 * 10 * TPR
//
// Inverting the dividend in the last term:
//
// f(CPU) 100,000 * 2 * 10 * TPR
// C * ---------- * ----------------------
// 50,000,000 f(CPU)
//
// The f(CPU) now cancels out.
//
// 100,000 * 2 * 10 * TPR
// C * ----------------------
// 50,000,000
//
// Since there are no clock frequencies left in the equation, this equation
// also works for 400 kHz bus operation as well, since the 100,000 in the
// numerator becomes 400,000 but C is 1/4, which cancel out each other.
// Reducing the constants gives:
//
// TPR TPR TPR
// C * --- = 1700 * --- = 340 * ---
// 25 25 5
//
// Note that the constant C is actually a bit larger than it needs to be in
// order to provide some safety margin.
//
// When the panel is being initialized, the value of C actually needs to be
// a bit longer (3200 instead of 1700). So, set the larger value for now.
//
g_ulDelay = (640 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5;
//
// Initialize the SSD0303 controller. Loop through the initialization
// sequence doing a single I2C transfer for each command.
//
for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit);
ulIdx += g_pucOSRAMInit[ulIdx] + 1)
{
//
// Send this command.
//
OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]);
OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2);
OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]);
}
//
// Now, switch to the actual value of C.
//
g_ulDelay = (340 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5;
//
// Clear the frame buffer.
//
OSRAMClear();
}
//*****************************************************************************
//
//! Turns on the OLED display.
//!
//! This function will turn on the OLED display, causing it to display the
//! contents of its internal frame buffer.
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMDisplayOn(void)
{
//
// Turn on the DC-DC converter and the display.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte(0xad);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0x8b);
OSRAMWriteByte(0x80);
OSRAMWriteFinal(0xaf);
}
//*****************************************************************************
//
//! Turns off the OLED display.
//!
//! This function will turn off the OLED display. This will stop the scanning
//! of the panel and turn off the on-chip DC-DC converter, preventing damage to
//! the panel due to burn-in (it has similar characters to a CRT in this
//! respect).
//!
//! \return None.
//
//*****************************************************************************
void
OSRAMDisplayOff(void)
{
//
// Turn off the DC-DC converter and the display.
//
OSRAMWriteFirst(0x80);
OSRAMWriteByte(0xad);
OSRAMWriteByte(0x80);
OSRAMWriteByte(0x8a);
OSRAMWriteByte(0x80);
OSRAMWriteFinal(0xae);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED
// display.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 852 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __OSRAM96X16_H__
#define __OSRAM96X16_H__
//*****************************************************************************
//
// Prototypes for the driver APIs.
//
//*****************************************************************************
extern void OSRAMClear(void);
extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX,
unsigned long ulY);
extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,
unsigned long ulY, unsigned long ulWidth,
unsigned long ulHeight);
extern void OSRAMInit(tBoolean bFast);
extern void OSRAMDisplayOn(void);
extern void OSRAMDisplayOff(void);
#endif // __OSRAM96X16_H__

124
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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and ORed together will values from the other
// groups.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void CPUcpsid(void);
extern void CPUcpsie(void);
extern void CPUwfi(void);
#endif // __CPU_H__

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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_START \
(I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_CONT \
(I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
(I2C_MASTER_CS_STOP)
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
//*****************************************************************************
// Miscellaneous I2C driver definitions.
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void IntMasterEnable(void);
extern void IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultKill);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or less
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfig.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,
unsigned long ulMode, unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData);
extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#define SYSCTL_PERIPH_PWM 0x00100000 // PWM
#define SYSCTL_PERIPH_ADC 0x00010000 // ADC
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2
#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

55
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h Normal file
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//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

137
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h Normal file
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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

102
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h Normal file
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//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSet as the ulConfig parameter and
// returned by UARTConfigGet in the pulConfig parameter. Additionally, the
// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity
// parameter, and are returned by UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,
unsigned long ulConfig);
extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharNonBlockingGet(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

63
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h Normal file
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//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 816 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

54
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt Normal file
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@ -0,0 +1,54 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'
GRPOPT 1,(Demo_Source),1,0,0
GRPOPT 2,(Libraries),0,0,0
GRPOPT 3,(RTOS_Source),0,0,0
GRPOPT 4,(Documentation),0,0,0
OPTFFF 1,1,2,301989888,0,0,0,0,<.\startup_rvmdk.S><startup_rvmdk.S>
OPTFFF 1,2,1,167772160,0,0,0,0,<.\LuminaryCode\osram96x16.c><osram96x16.c>
OPTFFF 1,3,1,2,0,148,161,0,<.\main.c><main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,100,0,0,0,12,0,0,0,27,4,0,0,178,1,0,0 }
OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c>
OPTFFF 1,5,1,989855744,0,0,0,0,<..\Common\Minimal\integer.c><integer.c>
OPTFFF 1,6,1,939524096,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c>
OPTFFF 1,7,1,201326592,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c>
OPTFFF 1,8,1,0,0,0,0,0,<.\heap\heap_1.c><heap_1.c>
OPTFFF 2,9,4,0,0,0,0,0,<C:\Devtools\Keil\ARM\RV30\LIB\Luminary\driverlib.lib><driverlib.lib>
OPTFFF 3,10,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c>
OPTFFF 3,11,1,0,0,0,0,0,<..\..\Source\list.c><list.c>
OPTFFF 3,12,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c>
OPTFFF 3,13,1,335544320,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c>
OPTFFF 4,14,5,0,0,0,0,0,<.\readme.txt><readme.txt>
TARGOPT 1, (FreeRTOS_Demo)
ADSCLK=50000000
OPTTT 1,1,1,0
OPTHX 1,65535,0,0,0
OPTLX 79,66,8,<.\rvmdk\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTAX 0
OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811)
OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()
OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTKEY 0,(LMIDK-AGDI)(-B0 -O1792)
OPTDF 0x84
OPTLE <>
OPTLC <>
EndOpt

116
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 Normal file
View file

@ -0,0 +1,116 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'
Group (Demo_Source)
Group (Libraries)
Group (RTOS_Source)
Group (Documentation)
File 1,2,<.\startup_rvmdk.S><startup_rvmdk.S>
File 1,1,<.\LuminaryCode\osram96x16.c><osram96x16.c>
File 1,1,<.\main.c><main.c>
File 1,1,<..\Common\Minimal\semtest.c><semtest.c>
File 1,1,<..\Common\Minimal\integer.c><integer.c>
File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c>
File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c>
File 1,1,<.\heap\heap_1.c><heap_1.c>
File 2,4,<C:\Devtools\Keil\ARM\RV30\LIB\Luminary\driverlib.lib><driverlib.lib>
File 3,1,<..\..\Source\tasks.c><tasks.c>
File 3,1,<..\..\Source\list.c><list.c>
File 3,1,<..\..\Source\queue.c><queue.c>
File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c>
File 4,5,<.\readme.txt><readme.txt>
Options 1,0,0 // Target 'FreeRTOS_Demo'
Device (LM3S811)
Vendor (Luminary Micro)
Cpu (IRAM(0x20000000-0x20001fff) IROM(0-0xffff) CLOCK(50000000) CPUTYPE("Cortex-M3"))
FlashUt ()
StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))
FlashDR (LMIDK-AGDI(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000))
DevID (4079)
Rgf (LM3Sxxx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿLuminary\)
OrgReg (ÿLuminary\)
TgStat=16
OutDir (.\rvmdk\)
OutName (RTOSDemo)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=1
LstDir (.\rvmdk\)
HexSel=1
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
CrunUsr 0 0 <>
CrunUsr 1 0 <>
SVCSID <>
GLFLAGS=1790
ADSFLGA { 176,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP ("Cortex-M3")
RVDEV ()
ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,32,0,32,0,0 }
OCMADSIROM { 1,0,0,0,0,0,0,1,0 }
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,32,0,0,0,0,0,0,0,0,0,0,0 }
RV_STAVEC ()
ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN (RVDS_ARMCM3_LM3S102)
ADSCUDEF ()
ADSCINCD (.;./LuminaryCode;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
ADSAUDEF ()
ADSAINCD ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSLDTA (0x00000000)
ADSLDDA (0x20000000)
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC (--entry Reset_Handler --last xHeap)
ADSLDIF ()
ADSLDDW ()
OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811)
OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()
FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\LMIDK-AGDI.DLL)
FLASH3 ("" ())
FLASH4 ()
EndOpt

154
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c Normal file
View file

@ -0,0 +1,154 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* The simplest possible implementation of pvPortMalloc(). Note that this
* implementation does NOT allow allocated memory to be freed again.
*
* See heap_2.c and heap_3.c for alternative implementations, and the memory
* management pages of http://www.FreeRTOS.org for more information.
*/
#include <stdlib.h>
#include "FreeRTOS.h"
#include "task.h"
/* Setup the correct byte alignment mask for the defined byte alignment. */
#if portBYTE_ALIGNMENT == 4
#define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 )
#endif
#if portBYTE_ALIGNMENT == 2
#define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 )
#endif
#if portBYTE_ALIGNMENT == 1
#define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 )
#endif
#ifndef heapBYTE_ALIGNMENT_MASK
#error "Invalid portBYTE_ALIGNMENT definition"
#endif
/* Allocate the memory for the heap. The struct is used to force byte
alignment without using any non-portable code. */
extern struct xRTOS_HEAP
{
unsigned long ulDummy;
unsigned char ucHeap[ configTOTAL_HEAP_SIZE ];
} xHeap;
static size_t xNextFreeByte = ( size_t ) 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
void *pvReturn = NULL;
/* Ensure that blocks are always aligned to the required number of bytes. */
#if portBYTE_ALIGNMENT != 1
if( xWantedSize & heapBYTE_ALIGNMENT_MASK )
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) );
}
#endif
vTaskSuspendAll();
{
/* Check there is enough room left for the allocation. */
if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) &&
( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */
{
/* Return the next free byte then increment the index past this
block. */
pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] );
xNextFreeByte += xWantedSize;
}
}
xTaskResumeAll();
return pvReturn;
}
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
/* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c
for alternative implementations, and the memory management pages of
http://www.FreeRTOS.org for more information. */
( void ) pv;
}
/*-----------------------------------------------------------*/
void vPortInitialiseBlocks( void )
{
/* Only required when static memory is not cleared. */
xNextFreeByte = ( size_t ) 0;
}

400
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/main.c Normal file
View file

@ -0,0 +1,400 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* This project contains an application demonstrating the use of the
* FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval
* board. See http://www.FreeRTOS.org for more information.
*
* main() simply sets up the hardware, creates all the demo application tasks,
* then starts the scheduler. http://www.freertos.org/a00102.html provides
* more information on the standard demo tasks.
*
* In addition to a subset of the standard demo application tasks, main.c also
* defines the following tasks:
*
* + A 'Print' task. The print task is the only task permitted to access the
* LCD - thus ensuring mutual exclusion and consistent access to the resource.
* Other tasks do not access the LCD directly, but instead send the text they
* wish to display to the print task. The print task spends most of its time
* blocked - only waking when a message is queued for display.
*
* + A 'Button handler' task. The eval board contains a user push button that
* is configured to generate interrupts. The interrupt handler uses a
* semaphore to wake the button handler task - demonstrating how the priority
* mechanism can be used to defer interrupt processing to the task level. The
* button handler task sends a message both to the LCD (via the print task) and
* the UART where it can be viewed using a dumb terminal (via the UART to USB
* converter on the eval board). NOTES: The dumb terminal must be closed in
* order to reflash the microcontroller. A very basic interrupt driven UART
* driver is used that does not use the FIFO. 19200 baud is used.
*
* + A 'check' task. The check task only executes every five seconds but has a
* high priority so is guaranteed to get processor time. Its function is to
* check that all the other tasks are still operational and that no errors have
* been detected at any time. If no errors have every been detected 'PASS' is
* written to the display (via the print task) - if an error has ever been
* detected the message is changed to 'FAIL'. The position of the message is
* changed for each write.
*/
/* Environment includes. */
#include "DriverLib.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo app includes. */
#include "integer.h"
#include "PollQ.h"
#include "semtest.h"
#include "BlockQ.h"
/* Delay between cycles of the 'check' task. */
#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )
/* UART configuration - note this does not use the FIFO so is not very
efficient. */
#define mainBAUD_RATE ( 19200 )
#define mainFIFO_SET ( 0x10 )
/* Demo task priorities. */
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Demo board specifics. */
#define mainPUSH_BUTTON GPIO_PIN_4
/* Misc. */
#define mainQUEUE_SIZE ( 3 )
#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS )
#define mainNO_DELAY ( ( portTickType ) 0 )
/*
* Configure the processor and peripherals for this demo.
*/
static void prvSetupHardware( void );
/*
* The 'check' task, as described at the top of this file.
*/
static void vCheckTask( void *pvParameters );
/*
* The task that is woken by the ISR that processes GPIO interrupts originating
* from the push button.
*/
static void vButtonHandlerTask( void *pvParameters );
/*
* The task that controls access to the LCD.
*/
static void vPrintTask( void *pvParameter );
/* String that is transmitted on the UART. */
static char *cMessage = "Task woken by button interrupt! --- ";
static volatile char *pcNextChar;
/* The semaphore used to wake the button handler task from within the GPIO
interrupt handler. */
xSemaphoreHandle xButtonSemaphore;
/* The queue used to send strings to the print task for display on the LCD. */
xQueueHandle xPrintQueue;
/* Newer library version. */
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, unsigned long ulBaud, unsigned long ulConfig);
/*-----------------------------------------------------------*/
int main( void )
{
/* Configure the clocks, UART and GPIO. */
prvSetupHardware();
/* Create the semaphore used to wake the button handler task from the GPIO
ISR. */
vSemaphoreCreateBinary( xButtonSemaphore );
xSemaphoreTake( xButtonSemaphore, 0 );
/* Create the queue used to pass message to vPrintTask. */
xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) );
/* Start the standard demo tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the tasks defined within the file. */
xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL );
xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* Will only get here if there was insufficient heap to start the
scheduler. */
return 0;
}
/*-----------------------------------------------------------*/
static void vCheckTask( void *pvParameters )
{
portBASE_TYPE xErrorOccurred = pdFALSE;
portTickType xLastExecutionTime;
const char *pcPassMessage = "PASS";
const char *pcFailMessage = "FAIL";
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
for( ;; )
{
/* Perform this check every mainCHECK_DELAY milliseconds. */
vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );
/* Has an error been found in any task? */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
/* Send either a pass or fail message. If an error is found it is
never cleared again. We do not write directly to the LCD, but instead
queue a message for display by the print task. */
if( xErrorOccurred == pdTRUE )
{
xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY );
}
else
{
xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY );
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL. */
SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );
/* Setup the push button. */
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN);
GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE );
IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY );
GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON );
IntEnable( INT_GPIOC );
/* Enable the UART. */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
/* Set GPIO A0 and A1 as peripheral function. They are used to output the
UART signals. */
GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );
/* Configure the UART for 8-N-1 operation. */
UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );
/* We don't want to use the fifo. This is for test purposes to generate
as many interrupts as possible. */
HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;
/* Enable Tx interrupts. */
HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX;
IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY );
IntEnable( INT_UART0 );
/* Initialise the LCD> */
OSRAMInit( false );
OSRAMStringDraw("www.FreeRTOS.org", 0, 0);
OSRAMStringDraw("LM3S811 demo", 16, 1);
}
/*-----------------------------------------------------------*/
static void vButtonHandlerTask( void *pvParameters )
{
const char *pcInterruptMessage = "Int";
for( ;; )
{
/* Wait for a GPIO interrupt to wake this task. */
while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS );
/* Start the Tx of the message on the UART. */
UARTIntDisable( UART0_BASE, UART_INT_TX );
{
pcNextChar = cMessage;
/* Send the first character. */
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;
}
pcNextChar++;
}
UARTIntEnable(UART0_BASE, UART_INT_TX);
/* Queue a message for the print task to display on the LCD. */
xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY );
/* Make sure we don't process bounces. */
vTaskDelay( mainDEBOUNCE_DELAY );
xSemaphoreTake( xButtonSemaphore, mainNO_DELAY );
}
}
/*-----------------------------------------------------------*/
void vUART_ISR(void)
{
unsigned long ulStatus;
/* What caused the interrupt. */
ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );
/* Clear the interrupt. */
UARTIntClear( UART0_BASE, ulStatus );
/* Was a Tx interrupt pending? */
if( ulStatus & UART_INT_TX )
{
/* Send the next character in the string. We are not using the FIFO. */
if( *pcNextChar != NULL )
{
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;
}
pcNextChar++;
}
}
}
/*-----------------------------------------------------------*/
void vGPIO_ISR( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* Clear the interrupt. */
GPIOPinIntClear( GPIO_PORTC_BASE, mainPUSH_BUTTON );
/* Wake the button handler task. */
xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken );
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void vPrintTask( void *pvParameters )
{
char *pcMessage;
unsigned portBASE_TYPE uxLine = 0, uxRow = 0;
for( ;; )
{
/* Wait for a message to arrive. */
xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY );
/* Write the message to the LCD. */
uxRow++;
uxLine++;
OSRAMClear();
OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01);
}
}

36
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/readme.txt Normal file
View file

@ -0,0 +1,36 @@
/*
* This project contains an application demonstrating the use of the
* FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval
* board. See http://www.FreeRTOS.org for more information.
*
* main() simply sets up the hardware, creates all the demo application tasks,
* then starts the scheduler. http://www.freertos.org/a00102.html provides
* more information on the standard demo tasks.
*
* In addition to a subset of the standard demo application tasks, main.c also
* defines the following tasks:
*
* + A 'Print' task. The print task is the only task permitted to access the
* LCD - thus ensuring mutual exclusion and consistent access to the resource.
* Other tasks do not access the LCD directly, but instead send the text they
* wish to display to the print task. The print task spends most of its time
* blocked - only waking when a message is queued for display.
*
* + A 'Button handler' task. The eval board contains a user push button that
* is configured to generate interrupts. The interrupt handler uses a
* semaphore to wake the button handler task - demonstrating how the priority
* mechanism can be used to defer interrupt processing to the task level. The
* button handler task sends a message both to the LCD (via the print task) and
* the UART where it can be viewed using a dumb terminal (via the UART to USB
* converter on the eval board). NOTES: The dumb terminal must be closed in
* order to reflash the microcontroller. A very basic interrupt driven UART
* driver is used that does not use the FIFO. 19200 baud is used.
*
* + A 'check' task. The check task only executes every five seconds but has a
* high priority so is guaranteed to get processor time. Its function is to
* check that all the other tasks are still operational and that no errors have
* been detected at any time. If no errors have every been detected 'PASS' is
* written to the display (via the print task) - if an error has ever been
* detected the message is changed to 'FAIL'. The position of the message is
* changed for each write.
*/

240
FreeRTOS/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S Normal file
View file

@ -0,0 +1,240 @@
; <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;
; startup_rvmdk.S - Startup code for Stellaris.
;
; Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
;
; Software License Agreement
;
; Luminary Micro, Inc. (LMI) is supplying this software for use solely and
; exclusively on LMI's Stellaris Family of microcontroller products.
;
; The software is owned by LMI and/or its suppliers, and is protected under
; applicable copyright laws. All rights are reserved. Any use in violation of
; the foregoing restrictions may subject the user to criminal sanctions under
; applicable laws, as well as to civil liability for the breach of the terms
; and conditions of this license.
;
; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
;
; This is part of revision 816 of the Stellaris Driver Library.
;
;******************************************************************************
;******************************************************************************
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
;
;******************************************************************************
Stack EQU 0x00000100
;******************************************************************************
;
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
;
;******************************************************************************
Heap EQU 0x00000000
;******************************************************************************
;
; Allocate space for the stack.
;
;******************************************************************************
AREA STACK, NOINIT, READWRITE, ALIGN=3
StackMem
SPACE Stack
;******************************************************************************
;
; Allocate space for the heap.
;
;******************************************************************************
AREA HEAP, NOINIT, READWRITE, ALIGN=3
HeapMem
SPACE Heap
;******************************************************************************
;
; Indicate that the code in this file preserves 8-byte alignment of the stack.
;
;******************************************************************************
PRESERVE8
;******************************************************************************
;
; Place code into the reset code section.
;
;******************************************************************************
AREA RESET, CODE, READONLY
THUMB
;******************************************************************************
;
; The vector table.
;
;******************************************************************************
EXPORT __Vectors
__Vectors
DCD StackMem + Stack ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NmiSR ; NMI Handler
DCD FaultISR ; Hard Fault Handler
DCD IntDefaultHandler ; MPU Fault Handler
DCD IntDefaultHandler ; Bus Fault Handler
DCD IntDefaultHandler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD vPortSVCHandler ; SVCall Handler
DCD IntDefaultHandler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD xPortPendSVHandler ; PendSV Handler
DCD xPortSysTickHandler ; SysTick Handler
DCD IntDefaultHandler ; GPIO Port A
DCD IntDefaultHandler ; GPIO Port B
DCD vGPIO_ISR ; GPIO Port C
DCD IntDefaultHandler ; GPIO Port D
DCD IntDefaultHandler ; GPIO Port E
DCD vUART_ISR ; UART0
DCD IntDefaultHandler ; UART1
DCD IntDefaultHandler ; SSI
DCD IntDefaultHandler ; I2C
DCD IntDefaultHandler ; PWM Fault
DCD IntDefaultHandler ; PWM Generator 0
DCD IntDefaultHandler ; PWM Generator 1
DCD IntDefaultHandler ; PWM Generator 2
DCD IntDefaultHandler ; Quadrature Encoder
DCD IntDefaultHandler ; ADC Sequence 0
DCD IntDefaultHandler ; ADC Sequence 1
DCD IntDefaultHandler ; ADC Sequence 2
DCD IntDefaultHandler ; ADC Sequence 3
DCD IntDefaultHandler ; Watchdog
DCD IntDefaultHandler ; Timer 0A
DCD IntDefaultHandler ; Timer 0B
DCD IntDefaultHandler ; Timer 1A
DCD IntDefaultHandler ; Timer 1B
DCD IntDefaultHandler ; Timer 2A
DCD IntDefaultHandler ; Timer 2B
DCD IntDefaultHandler ; Comp 0
DCD IntDefaultHandler ; Comp 1
DCD IntDefaultHandler ; Comp 2
DCD IntDefaultHandler ; System Control
DCD IntDefaultHandler ; Flash Control
;******************************************************************************
;
; This is the code that gets called when the processor first starts execution
; following a reset event.
;
;******************************************************************************
EXPORT Reset_Handler
Reset_Handler
;
; Call __main() in the C library, which will call the application
; supplied main().
;
IMPORT __main
IMPORT vGPIO_ISR
IMPORT vUART_ISR
IMPORT xPortPendSVHandler
IMPORT xPortSysTickHandler
IMPORT vPortSVCHandler
LDR R0, =__main
BX R0
;******************************************************************************
;
; This is the code that gets called when the processor receives a NMI. This
; simply enters an infinite loop, preserving the system state for examination
; by a debugger.
;
;******************************************************************************
NmiSR
B NmiSR
;******************************************************************************
;
; This is the code that gets called when the processor receives a fault
; interrupt. This simply enters an infinite loop, preserving the system state
; for examination by a debugger.
;
;******************************************************************************
FaultISR
B FaultISR
;******************************************************************************
;
; This is the code that gets called when the processor receives an unexpected
; interrupt. This simply enters an infinite loop, preserving the system state
; for examination by a debugger.
;
;******************************************************************************
IntDefaultHandler
B IntDefaultHandler
;******************************************************************************
;
; Make sure the end of this section is aligned.
;
;******************************************************************************
ALIGN
;******************************************************************************
;
; Some code in the normal code section for initializing the heap and stack.
;
;******************************************************************************
AREA |.text|, CODE, READONLY
;******************************************************************************
;
; The function expected of the C library startup code for defining the stack
; and heap memory locations.
;
;******************************************************************************
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, =HeapMem
LDR R1, =(StackMem + Stack)
LDR R2, =(HeapMem + Heap)
LDR R3, =StackMem
BX LR
;******************************************************************************
;
; Make sure the end of this section is aligned.
;
;******************************************************************************
ALIGN
; Note:
; Using READWRITE places Section .RTOSHeap in Region ER_RW.
; Using NOINIT places Section .RTOSHeap in Region ER_ZI,which means
; "ZEROINITIALIZE" (sic), and which is the last region in memory. Then
; we need to make this section the last section, which is somewhat tricky,
; because we cannot use the sectionname, but need to use a defined symbol:
; Linker option: "--last xHeap"
EXPORT xHeap
AREA RTOSHeap, DATA, NOINIT
xHeap
;******************************************************************************
;
; Tell the assembler that we're done.
;
;******************************************************************************
END