len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-19 09:38:32 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add FreeRTOS-Plus directory.

Browse source
This commit is contained in:
Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

114
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h Normal file
View file

@ -0,0 +1,114 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) )
#define configMAX_TASK_NAME_LEN ( 3 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 0
#define INCLUDE_vTaskDelay 1
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */
#endif /* FREERTOS_CONFIG_H */

146
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c Normal file
View file

@ -0,0 +1,146 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
/*
*/
#include "FreeRTOS.h"
#include "task.h"
#include "partest.h"
#include "pdc.h"
#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 )
#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 )
static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF;
void vParTestInitialise( void )
{
PDCInit();
PDCWrite( PDC_LED, ucOutputValue );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned char ucBit = ( unsigned char ) 1;
vTaskSuspendAll();
{
if( uxLED < partstMAX_OUTPUT_LED )
{
ucBit = ( ( unsigned char ) 1 ) << uxLED;
if( xValue == pdFALSE )
{
ucBit ^= ( unsigned char ) 0xff;
ucOutputValue &= ucBit;
}
else
{
ucOutputValue |= ucBit;
}
PDCWrite( PDC_LED, ucOutputValue );
}
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned char ucBit;
vTaskSuspendAll();
{
if( uxLED < partstMAX_OUTPUT_LED )
{
ucBit = ( ( unsigned char ) 1 ) << uxLED;
if( ucOutputValue & ucBit )
{
ucOutputValue &= ~ucBit;
}
else
{
ucOutputValue |= ucBit;
}
PDCWrite( PDC_LED, ucOutputValue );
}
}
xTaskResumeAll();
}

648
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c Normal file
View file

@ -0,0 +1,648 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* This demo application creates six co-routines and two tasks (three including
* the idle task). The co-routines execute as part of the idle task hook.
*
* Five of the created co-routines are the standard 'co-routine flash'
* co-routines contained within the Demo/Common/Minimal/crflash.c file and
* documented on the FreeRTOS.org WEB site.
*
* The 'LCD Task' rotates a string on the LCD, delaying between each character
* as necessitated by the slow interface, and delaying between each string just
* long enough to enable the text to be read.
*
* The sixth co-routine and final task control the transmission and reception
* of a string to UART 0. The co-routine periodically sends the first
* character of the string to the UART, with the UART's TxEnd interrupt being
* used to transmit the remaining characters. The UART's RxEnd interrupt
* receives the characters and places them on a queue to be processed by the
* 'COMs Rx' task. An error is latched should an unexpected character be
* received, or any character be received out of sequence.
*
* A loopback connector is required to ensure that each character transmitted
* on the UART is also received on the same UART. For test purposes the UART
* FIFO's are not utalised in order to maximise the interrupt overhead. Also
* a pseudo random interval is used between the start of each transmission in
* order that the resultant interrupts are more randomly distributed and
* therefore more likely to highlight any problems.
*
* The flash co-routines control LED's zero to four. LED five is toggled each
* time the string is transmitted on the UART. LED six is toggled each time
* the string is CORRECTLY received on the UART. LED seven is latched on should
* an error be detected in any task or co-routine.
*
* In addition the idle task makes repetative calls to
* prvSetAndCheckRegisters(). This simply loads the general purpose registers
* with a known value, then checks each register to ensure the held value is
* still correct. As a low priority task this checking routine is likely to
* get repeatedly swapped in and out. A register being found to contain an
* incorrect value is therefore indicative of an error in the task switching
* mechansim.
*
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "croutine.h"
/* Demo application include files. */
#include "partest.h"
#include "crflash.h"
/* Library include files. */
#include "DriverLib.h"
/* The time to delay between writing each character to the LCD. */
#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )
/* The time to delay between writing each string to the LCD. */
#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )
/* The number of flash co-routines to create. */
#define mainNUM_FLASH_CO_ROUTINES ( 5 )
/* The length of the queue used to pass received characters to the Comms Rx
task. */
#define mainRX_QUEUE_LEN ( 5 )
/* The priority of the co-routine used to initiate the transmission of the
string on UART 0. */
#define mainTX_CO_ROUTINE_PRIORITY ( 1 )
/* Only one co-routine is created so its index is not important. */
#define mainTX_CO_ROUTINE_INDEX ( 0 )
/* The time between transmissions of the string on UART 0. This is pseudo
random in order to generate a bit or randomness to when the interrupts occur.*/
#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )
#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )
#define mainOFFSET_TIME ( ( portTickType ) 3 )
/* The time the Comms Rx task should wait to receive a character. This should
be slightly longer than the time between transmissions. If we do not receive
a character after this time then there must be an error in the transmission or
the timing of the transmission. */
#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )
/* The task priorites. */
#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The LED's toggled by the various tasks. */
#define mainCOMMS_FAIL_LED ( 7 )
#define mainCOMMS_RX_LED ( 6 )
#define mainCOMMS_TX_LED ( 5 )
/* The baud rate used by the UART comms tasks/co-routine. */
#define mainBAUD_RATE ( 57600 )
/* FIFO setting for the UART. The FIFO is not used to create a better test. */
#define mainFIFO_SET ( 0x10 )
/* The string that is transmitted on the UART contains sequentially the
characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */
#define mainFIRST_TX_CHAR '0'
#define mainLAST_TX_CHAR 'z'
/* Just used to walk through the program memory in order that some random data
can be generated. */
#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) )
#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 )
/* The error routine that is called if the driver library encounters an error. */
#ifdef DEBUG
void
__error__(char *pcFilename, unsigned long ulLine)
{
}
#endif
/*-----------------------------------------------------------*/
/*
* The task that rotates text on the LCD.
*/
static void vLCDTask( void * pvParameters );
/*
* The task that receives the characters from UART 0.
*/
static void vCommsRxTask( void * pvParameters );
/*
* The co-routine that periodically initiates the transmission of the string on
* the UART.
*/
static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*
* Writes a string the the LCD.
*/
static void prvWriteString( const char *pcString );
/*
* Initialisation routine for the UART.
*/
static void vSerialInit( void );
/*
* Thread safe write to the PDC.
*/
static void prvPDCWrite( char cAddress, char cData );
/*
* Function to simply set a known value into the general purpose registers
* then read them back to ensure they remain set correctly. An incorrect value
* being indicative of an error in the task switching mechanism.
*/
void prvSetAndCheckRegisters( void );
/*
* Latch the LED that indicates that an error has occurred.
*/
void vSetErrorLED( void );
/*
* Sets up the PLL and ports used by the demo.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines
defined within this file. */
unsigned portBASE_TYPE uxErrorStatus = pdPASS;
/* The next character to transmit. */
static char cNextChar;
/* The queue used to transmit characters from the interrupt to the Comms Rx
task. */
static xQueueHandle xCommsQueue;
/*-----------------------------------------------------------*/
int main( void )
{
/* Create the queue used to communicate between the UART ISR and the Comms
Rx task. */
xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) );
/* Setup the ports used by the demo and the clock. */
prvSetupHardware();
/* Create the co-routines that flash the LED's. */
vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );
/* Create the co-routine that initiates the transmission of characters
on the UART. */
xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );
/* Create the LCD and Comms Rx tasks. */
xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );
xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );
/* Start the scheduler running the tasks and co-routines just created. */
vTaskStartScheduler();
/* Should not get here unless we did not have enough memory to start the
scheduler. */
for( ;; );
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL. */
SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );
/* Initialise the hardware used to talk to the LCD, LED's and UART. */
PDCInit();
vParTestInitialise();
vSerialInit();
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* The co-routines are executed in the idle task using the idle task
hook. */
for( ;; )
{
/* Schedule the co-routines. */
vCoRoutineSchedule();
/* Run the register check function between each co-routine. */
prvSetAndCheckRegisters();
}
}
/*-----------------------------------------------------------*/
static void prvWriteString( const char *pcString )
{
/* Write pcString to the LED, pausing between each character. */
prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR);
while( *pcString )
{
vTaskDelay( mainCHAR_WRITE_DELAY );
prvPDCWrite( PDC_LCD_RAM, *pcString );
pcString++;
}
}
/*-----------------------------------------------------------*/
void vLCDTask( void * pvParameters )
{
unsigned portBASE_TYPE uxIndex;
const unsigned char ucCFGData[] = {
0x30, /* Set data bus to 8-bits. */
0x30,
0x30,
0x3C, /* Number of lines/font. */
0x08, /* Display off. */
0x01, /* Display clear. */
0x06, /* Entry mode [cursor dir][shift]. */
0x0C /* Display on [display on][curson on][blinking on]. */
};
/* The strings that are written to the LCD. */
const char *pcStringsToDisplay[] = {
"Stellaris",
"Demo",
"One",
"www.FreeRTOS.org",
""
};
/* Configure the LCD. */
uxIndex = 0;
while( uxIndex < sizeof( ucCFGData ) )
{
prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );
uxIndex++;
vTaskDelay( mainCHAR_WRITE_DELAY );
}
/* Turn the LCD Backlight on. */
prvPDCWrite( PDC_CSR, 0x01 );
/* Clear display. */
vTaskDelay( mainCHAR_WRITE_DELAY );
prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR );
uxIndex = 0;
for( ;; )
{
/* Display the string on the LCD. */
prvWriteString( pcStringsToDisplay[ uxIndex ] );
/* Move on to the next string - wrapping if necessary. */
uxIndex++;
if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )
{
uxIndex = 0;
/* Longer pause on the last string to be sent. */
vTaskDelay( mainSTRING_WRITE_DELAY * 2 );
}
/* Wait until it is time to move onto the next string. */
vTaskDelay( mainSTRING_WRITE_DELAY );
}
}
/*-----------------------------------------------------------*/
static void vCommsRxTask( void * pvParameters )
{
static char cRxedChar, cExpectedChar;
/* Set the char we expect to receive to the start of the string. */
cExpectedChar = mainFIRST_TX_CHAR;
for( ;; )
{
/* Wait for a character to be received. */
xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY );
/* Was the character recived (if any) the expected character. */
if( cRxedChar != cExpectedChar )
{
/* Got an unexpected character. This can sometimes occur when
reseting the system using the debugger leaving characters already
in the UART regsters. */
uxErrorStatus = pdFAIL;
/* Resync by waiting for the end of the current string. */
while( cRxedChar != mainLAST_TX_CHAR )
{
while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );
}
/* The next expected character is the start of the string again. */
cExpectedChar = mainFIRST_TX_CHAR;
}
else
{
if( cExpectedChar == mainLAST_TX_CHAR )
{
/* We have reached the end of the string - we now expect to
receive the first character in the string again. The LED is
toggled to indicate that the entire string was received without
error. */
vParTestToggleLED( mainCOMMS_RX_LED );
cExpectedChar = mainFIRST_TX_CHAR;
}
else
{
/* We got the expected character, we now expect to receive the
next character in the string. */
cExpectedChar++;
}
}
}
}
/*-----------------------------------------------------------*/
static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
portTickType xDelayPeriod;
static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES;
/* Co-routine MUST start with a call to crSTART. */
crSTART( xHandle );
for(;;)
{
/* Was the previously transmitted string received correctly? */
if( uxErrorStatus != pdPASS )
{
/* An error was encountered so set the error LED. */
vSetErrorLED();
}
/* The next character to Tx is the first in the string. */
cNextChar = mainFIRST_TX_CHAR;
UARTIntDisable( UART0_BASE, UART_INT_TX );
{
/* Send the first character. */
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = cNextChar;
}
/* Move the variable to the char to Tx on so the ISR transmits
the next character in the string once this one has completed. */
cNextChar++;
}
UARTIntEnable(UART0_BASE, UART_INT_TX);
/* Toggle the LED to show a new string is being transmitted. */
vParTestToggleLED( mainCOMMS_TX_LED );
/* Delay before we start the string off again. A pseudo-random delay
is used as this will provide a better test. */
xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );
pulRandomBytes++;
if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )
{
pulRandomBytes = mainFIRST_PROGRAM_BYTES;
}
/* Make sure we don't wait too long... */
xDelayPeriod &= mainMAX_TX_DELAY;
/* ...but we do want to wait. */
if( xDelayPeriod < mainMIN_TX_DELAY )
{
xDelayPeriod = mainMIN_TX_DELAY;
}
/* Block for the random(ish) time. */
crDELAY( xHandle, xDelayPeriod );
}
/* Co-routine MUST end with a call to crEND. */
crEND();
}
/*-----------------------------------------------------------*/
static void vSerialInit( void )
{
/* Enable the UART. GPIOA has already been initialised. */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
/* Set GPIO A0 and A1 as peripheral function. They are used to output the
UART signals. */
GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );
/* Configure the UART for 8-N-1 operation. */
UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );
/* We dont want to use the fifo. This is for test purposes to generate
as many interrupts as possible. */
HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;
/* Enable both Rx and Tx interrupts. */
HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );
IntEnable( INT_UART0 );
}
/*-----------------------------------------------------------*/
void vUART_ISR(void)
{
unsigned long ulStatus;
char cRxedChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* What caused the interrupt. */
ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );
/* Clear the interrupt. */
UARTIntClear( UART0_BASE, ulStatus );
/* Was an Rx interrpt pending? */
if( ulStatus & UART_INT_RX )
{
if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )
{
/* Get the char from the buffer and post it onto the queue of
Rxed chars. Posting the character should wake the task that is
blocked on the queue waiting for characters. */
cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR );
xQueueSendFromISR( xCommsQueue, &cRxedChar, &xHigherPriorityTaskWoken );
}
}
/* Was a Tx interrupt pending? */
if( ulStatus & UART_INT_TX )
{
/* Send the next character in the string. We are not using the FIFO. */
if( cNextChar <= mainLAST_TX_CHAR )
{
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = cNextChar;
}
cNextChar++;
}
}
/* If a task was woken by the character being received then we force
a context switch to occur in case the task is of higher priority than
the currently executing task (i.e. the task that this interrupt
interrupted.) */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void prvPDCWrite( char cAddress, char cData )
{
vTaskSuspendAll();
{
PDCWrite( cAddress, cData );
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vSetErrorLED( void )
{
vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );
}
/*-----------------------------------------------------------*/
void prvSetAndCheckRegisters( void )
{
/* Fill the general purpose registers with known values. */
__asm volatile
(
" mov r11, #10 \n"
" add r0, r11, #1 \n"
" add r1, r11, #2 \n"
" add r2, r11, #3 \n"
" add r3, r11, #4 \n"
" add r4, r11, #5 \n"
" add r5, r11, #6 \n"
" add r6, r11, #7 \n"
" add r7, r11, #8 \n"
" add r8, r11, #9 \n"
" add r9, r11, #10 \n"
" add r10, r11, #11 \n"
" add r12, r11, #12"
);
/* Check the values are as expected. */
__asm volatile
(
" cmp r11, #10 \n"
" bne set_error_led \n"
" cmp r0, #11 \n"
" bne set_error_led \n"
" cmp r1, #12 \n"
" bne set_error_led \n"
" cmp r2, #13 \n"
" bne set_error_led \n"
" cmp r3, #14 \n"
" bne set_error_led \n"
" cmp r4, #15 \n"
" bne set_error_led \n"
" cmp r5, #16 \n"
" bne set_error_led \n"
" cmp r6, #17 \n"
" bne set_error_led \n"
" cmp r7, #18 \n"
" bne set_error_led \n"
" cmp r8, #19 \n"
" bne set_error_led \n"
" cmp r9, #20 \n"
" bne set_error_led \n"
" cmp r10, #21 \n"
" bne set_error_led \n"
" cmp r12, #22 \n"
" bne set_error_led \n"
" bx lr"
);
__asm volatile
(
"set_error_led: \n"
" push {r14} \n"
" ldr r1, vSetErrorLEDConst\n"
" blx r1 \n"
" pop {r14} \n"
" bx lr \n"
" \n"
" .align 2 \n"
"vSetErrorLEDConst: .word vSetErrorLED"
);
}
/*-----------------------------------------------------------*/

120
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s Normal file
View file

@ -0,0 +1,120 @@
/*****************************************************************************
* Copyright (c) 2006 Rowley Associates Limited. *
* *
* This file may be distributed under the terms of the License Agreement *
* provided with this software. *
* *
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
*****************************************************************************/
.section .vectors, "ax"
.code 16
.align 0
.global _vectors
.extern xPortPendSVHandler
.extern xPortSysTickHandler
.extern vUART_ISR
.extern vPortSVCHandler
.macro DEFAULT_ISR_HANDLER name=
.thumb_func
.weak \name
\name:
1: b 1b /* endless loop */
.endm
_vectors:
.word __stack_end__
#ifdef STARTUP_FROM_RESET
.word _start
#else
.word reset_wait
#endif /* STARTUP_FROM_RESET */
.word NmiISR
.word FaultISR
.word 0 // Populate if using MemManage (MPU)
.word 0 // Populate if using Bus fault
.word 0 // Populate if using Usage fault
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word vPortSVCHandler
.word 0 // Populate if using a debug monitor
.word 0 // Reserved
.word xPortPendSVHandler // Populate if using pendable service request
.word xPortSysTickHandler
// External interrupts start her
.word GPIO_Port_A_ISR
.word GPIO_Port_B_ISR
.word GPIO_Port_C_ISR
.word GPIO_Port_D_ISR
.word GPIO_Port_E_ISR
.word vUART_ISR
.word UART1_ISR
.word SSI_ISR
.word I2C_ISR
.word PWM_Fault_ISR
.word PWM_Generator_0_ISR
.word PWM_Generator_1_ISR
.word PWM_Generator_2_ISR
.word QEI_ISR
.word ADC_Sequence_0_ISR
.word ADC_Sequence_1_ISR
.word ADC_Sequence_2_ISR
.word ADC_Sequence_3_ISR
.word Watchdog_timer_ISR
.word Timer0a_ISR
.word Timer0b_ISR
.word Timer1a_ISR
.word Timer1b_ISR
.word Timer2a_ISR
.word Timer2b_ISR
.word Analog_Comparator_0_ISR
.word Analog_Comparator_1_ISR
.word Analog_Comparator_2_ISR
.word System_Control_ISR
.word FLASH_Control_ISR
.section .init, "ax"
.thumb_func
DEFAULT_ISR_HANDLER NmiISR
DEFAULT_ISR_HANDLER FaultISR
DEFAULT_ISR_HANDLER SVCallISR
DEFAULT_ISR_HANDLER SysTickISR
DEFAULT_ISR_HANDLER GPIO_Port_A_ISR
DEFAULT_ISR_HANDLER GPIO_Port_B_ISR
DEFAULT_ISR_HANDLER GPIO_Port_C_ISR
DEFAULT_ISR_HANDLER GPIO_Port_D_ISR
DEFAULT_ISR_HANDLER GPIO_Port_E_ISR
DEFAULT_ISR_HANDLER UART0_ISR
DEFAULT_ISR_HANDLER UART1_ISR
DEFAULT_ISR_HANDLER SSI_ISR
DEFAULT_ISR_HANDLER I2C_ISR
DEFAULT_ISR_HANDLER PWM_Fault_ISR
DEFAULT_ISR_HANDLER PWM_Generator_0_ISR
DEFAULT_ISR_HANDLER PWM_Generator_1_ISR
DEFAULT_ISR_HANDLER PWM_Generator_2_ISR
DEFAULT_ISR_HANDLER QEI_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR
DEFAULT_ISR_HANDLER Watchdog_timer_ISR
DEFAULT_ISR_HANDLER Timer0a_ISR
DEFAULT_ISR_HANDLER Timer0b_ISR
DEFAULT_ISR_HANDLER Timer1a_ISR
DEFAULT_ISR_HANDLER Timer1b_ISR
DEFAULT_ISR_HANDLER Timer2a_ISR
DEFAULT_ISR_HANDLER Timer2b_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
DEFAULT_ISR_HANDLER System_Control_ISR
DEFAULT_ISR_HANDLER FLASH_Control_ISR
#ifndef STARTUP_FROM_RESET
DEFAULT_ISR_HANDLER reset_wait
#endif /* STARTUP_FROM_RESET */

114
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h Normal file
View file

@ -0,0 +1,114 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) )
#define configMAX_TASK_NAME_LEN ( 3 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 3 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 0
#define INCLUDE_vTaskDelay 1
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */
#endif /* FREERTOS_CONFIG_H */

146
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c Normal file
View file

@ -0,0 +1,146 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
/*
*/
#include "FreeRTOS.h"
#include "task.h"
#include "partest.h"
#include "pdc.h"
#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
#define partstALL_OUTPUTS_OFF ( ( unsigned char ) 0x00 )
#define partstMAX_OUTPUT_LED ( ( unsigned char ) 8 )
static volatile unsigned char ucOutputValue = partstALL_OUTPUTS_OFF;
void vParTestInitialise( void )
{
PDCInit();
PDCWrite( PDC_LED, ucOutputValue );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned char ucBit = ( unsigned char ) 1;
vTaskSuspendAll();
{
if( uxLED < partstMAX_OUTPUT_LED )
{
ucBit = ( ( unsigned char ) 1 ) << uxLED;
if( xValue == pdFALSE )
{
ucBit ^= ( unsigned char ) 0xff;
ucOutputValue &= ucBit;
}
else
{
ucOutputValue |= ucBit;
}
PDCWrite( PDC_LED, ucOutputValue );
}
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned char ucBit;
vTaskSuspendAll();
{
if( uxLED < partstMAX_OUTPUT_LED )
{
ucBit = ( ( unsigned char ) 1 ) << uxLED;
if( ucOutputValue & ucBit )
{
ucOutputValue &= ~ucBit;
}
else
{
ucOutputValue |= ucBit;
}
PDCWrite( PDC_LED, ucOutputValue );
}
}
xTaskResumeAll();
}

656
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c Normal file
View file

@ -0,0 +1,656 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* This demo application creates seven co-routines and one task (two including
* the idle task). The co-routines execute as part of the idle task hook.
*
* Five of the created co-routines are the standard 'co-routine flash'
* co-routines contained within the Demo/Common/Minimal/crflash.c file and
* documented on the FreeRTOS.org WEB site.
*
* The 'LCD Task' rotates a string on the LCD, delaying between each character
* as necessitated by the slow interface, and delaying between each string just
* long enough to enable the text to be read.
*
* The sixth co-routine controls the transmission of a string to UART 0. The
* co-routine periodically sends the first character of the string to the UART,
* with the UART's TxEnd interrupt being used to transmit the remaining
* characters. The UART's RxEnd interrupt receives the characters and places
* them on a queue to be processed by the seventh and final co-routine. An
* error is latched should an unexpected character be received, or any
* character be received out of sequence.
*
* A loopback connector is required to ensure that each character transmitted
* on the UART is also received on the same UART. For test purposes the UART
* FIFO's are not utalised in order to maximise the interrupt overhead. Also
* a pseudo random interval is used between the start of each transmission in
* order that the resultant interrupts are more randomly distributed and
* therefore more likely to highlight any problems.
*
* The flash co-routines control LED's zero to four. LED five is toggled each
* time the string is transmitted on the UART. LED six is toggled each time
* the string is CORRECTLY received on the UART. LED seven is latched on should
* an error be detected in any task or co-routine.
*
* In addition the idle task makes repetative calls to
* prvSetAndCheckRegisters(). This simply loads the general purpose registers
* with a known value, then checks each register to ensure the held value is
* still correct. As a low priority task this checking routine is likely to
* get repeatedly swapped in and out. A register being found to contain an
* incorrect value is therefore indicative of an error in the task switching
* mechansim.
*
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "croutine.h"
/* Demo application include files. */
#include "partest.h"
#include "crflash.h"
/* Library include files. */
#include "DriverLib.h"
/* The time to delay between writing each character to the LCD. */
#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS )
/* The time to delay between writing each string to the LCD. */
#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS )
/* The number of flash co-routines to create. */
#define mainNUM_FLASH_CO_ROUTINES ( 5 )
/* The length of the queue used to pass received characters to the Comms Rx
task. */
#define mainRX_QUEUE_LEN ( 5 )
/* The priority of the co-routine used to initiate the transmission of the
string on UART 0. */
#define mainTX_CO_ROUTINE_PRIORITY ( 1 )
/* The priority of the co-routine used to receive characters from the UART. */
#define mainRX_CO_ROUTINE_PRIORITY ( 2 )
/* Only one co-routine is created so its index is not important. */
#define mainTX_CO_ROUTINE_INDEX ( 0 )
#define mainRX_CO_ROUTINE_INDEX ( 0 )
/* The time between transmissions of the string on UART 0. This is pseudo
random in order to generate a bit or randomness to when the interrupts occur.*/
#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS )
#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f )
#define mainOFFSET_TIME ( ( portTickType ) 3 )
/* The time the Comms Rx task should wait to receive a character. This should
be slightly longer than the time between transmissions. If we do not receive
a character after this time then there must be an error in the transmission or
the timing of the transmission. */
#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 )
/* The task priorites. */
#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The LED's toggled by the various tasks. */
#define mainCOMMS_FAIL_LED ( 7 )
#define mainCOMMS_RX_LED ( 6 )
#define mainCOMMS_TX_LED ( 5 )
/* The baud rate used by the UART comms tasks/co-routine. */
#define mainBAUD_RATE ( 57600 )
/* FIFO setting for the UART. The FIFO is not used to create a better test. */
#define mainFIFO_SET ( 0x10 )
/* The string that is transmitted on the UART contains sequentially the
characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */
#define mainFIRST_TX_CHAR '0'
#define mainLAST_TX_CHAR 'z'
/* Just used to walk through the program memory in order that some random data
can be generated. */
#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned long * ) ( 8 * 1024 ) )
#define mainFIRST_PROGRAM_BYTES ( ( unsigned long * ) 4 )
/* The error routine that is called if the driver library encounters an error. */
#ifdef DEBUG
void
__error__(char *pcFilename, unsigned long ulLine)
{
}
#endif
/*-----------------------------------------------------------*/
/*
* The task that rotates text on the LCD.
*/
static void vLCDTask( void * pvParameters );
/*
* The task that receives the characters from UART 0.
*/
static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*
* The co-routine that periodically initiates the transmission of the string on
* the UART.
*/
static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*
* Writes a string the the LCD.
*/
static void prvWriteString( const char *pcString );
/*
* Initialisation routine for the UART.
*/
static void vSerialInit( void );
/*
* Thread safe write to the PDC.
*/
static void prvPDCWrite( char cAddress, char cData );
/*
* Function to simply set a known value into the general purpose registers
* then read them back to ensure they remain set correctly. An incorrect value
* being indicative of an error in the task switching mechanism.
*/
void prvSetAndCheckRegisters( void );
/*
* Latch the LED that indicates that an error has occurred.
*/
void vSetErrorLED( void );
/*
* Sets up the PLL and ports used by the demo.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines
defined within this file. */
unsigned portBASE_TYPE uxErrorStatus = pdPASS;
/* The next character to transmit. */
static char cNextChar;
/* The queue used to transmit characters from the interrupt to the Comms Rx
task. */
static xQueueHandle xCommsQueue;
/*-----------------------------------------------------------*/
int main( void )
{
/* Create the queue used to communicate between the UART ISR and the Comms
Rx task. */
xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( char ) );
/* Setup the ports used by the demo and the clock. */
prvSetupHardware();
/* Create the co-routines that flash the LED's. */
vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );
/* Create the co-routine that initiates the transmission of characters
on the UART. */
xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );
/* Create the co-routine that receives characters from the UART. */
xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX );
/* Create the LCD task. */
xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );
/* Start the scheduler running the tasks and co-routines just created. */
vTaskStartScheduler();
/* Should not get here unless we did not have enough memory to start the
scheduler. */
for( ;; );
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL. */
SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );
/* Initialise the hardware used to talk to the LCD, LED's and UART. */
PDCInit();
vParTestInitialise();
vSerialInit();
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* The co-routines are executed in the idle task using the idle task
hook. */
for( ;; )
{
/* Schedule the co-routines. */
vCoRoutineSchedule();
/* Run the register check function between each co-routine. */
prvSetAndCheckRegisters();
}
}
/*-----------------------------------------------------------*/
static void prvWriteString( const char *pcString )
{
/* Write pcString to the LED, pausing between each character. */
prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR);
while( *pcString )
{
vTaskDelay( mainCHAR_WRITE_DELAY );
prvPDCWrite( PDC_LCD_RAM, *pcString );
pcString++;
}
}
/*-----------------------------------------------------------*/
void vLCDTask( void * pvParameters )
{
unsigned portBASE_TYPE uxIndex;
const unsigned char ucCFGData[] = {
0x30, /* Set data bus to 8-bits. */
0x30,
0x30,
0x3C, /* Number of lines/font. */
0x08, /* Display off. */
0x01, /* Display clear. */
0x06, /* Entry mode [cursor dir][shift]. */
0x0C /* Display on [display on][curson on][blinking on]. */
};
/* The strings that are written to the LCD. */
const char *pcStringsToDisplay[] = {
"Stellaris",
"Demo",
"Two",
"www.FreeRTOS.org",
""
};
/* Configure the LCD. */
uxIndex = 0;
while( uxIndex < sizeof( ucCFGData ) )
{
prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );
uxIndex++;
vTaskDelay( mainCHAR_WRITE_DELAY );
}
/* Turn the LCD Backlight on. */
prvPDCWrite( PDC_CSR, 0x01 );
/* Clear display. */
vTaskDelay( mainCHAR_WRITE_DELAY );
prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR );
uxIndex = 0;
for( ;; )
{
/* Display the string on the LCD. */
prvWriteString( pcStringsToDisplay[ uxIndex ] );
/* Move on to the next string - wrapping if necessary. */
uxIndex++;
if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 )
{
uxIndex = 0;
/* Longer pause on the last string to be sent. */
vTaskDelay( mainSTRING_WRITE_DELAY * 2 );
}
/* Wait until it is time to move onto the next string. */
vTaskDelay( mainSTRING_WRITE_DELAY );
}
}
/*-----------------------------------------------------------*/
static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
static char cRxedChar, cExpectedChar = mainFIRST_TX_CHAR;
portBASE_TYPE xResult;
crSTART( xHandle );
for( ;; )
{
/* Wait for a character to be received. */
crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );
/* Was the character recived (if any) the expected character. */
if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) )
{
/* Got an unexpected character. This can sometimes occur when
reseting the system using the debugger leaving characters already
in the UART regsters. */
uxErrorStatus = pdFAIL;
/* Resync by waiting for the end of the current string. */
while( cRxedChar != mainLAST_TX_CHAR )
{
crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult );
}
/* The next expected character is the start of the string again. */
cExpectedChar = mainFIRST_TX_CHAR;
}
else
{
if( cExpectedChar == mainLAST_TX_CHAR )
{
/* We have reached the end of the string - we now expect to
receive the first character in the string again. The LED is
toggled to indicate that the entire string was received without
error. */
vParTestToggleLED( mainCOMMS_RX_LED );
cExpectedChar = mainFIRST_TX_CHAR;
}
else
{
/* We got the expected character, we now expect to receive the
next character in the string. */
cExpectedChar++;
}
}
}
crEND();
}
/*-----------------------------------------------------------*/
static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
portTickType xDelayPeriod;
static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES;
/* Co-routine MUST start with a call to crSTART. */
crSTART( xHandle );
for(;;)
{
/* Was the previously transmitted string received correctly? */
if( uxErrorStatus != pdPASS )
{
/* An error was encountered so set the error LED. */
vSetErrorLED();
}
/* The next character to Tx is the first in the string. */
cNextChar = mainFIRST_TX_CHAR;
UARTIntDisable( UART0_BASE, UART_INT_TX );
{
/* Send the first character. */
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = cNextChar;
}
/* Move the variable to the char to Tx on so the ISR transmits
the next character in the string once this one has completed. */
cNextChar++;
}
UARTIntEnable(UART0_BASE, UART_INT_TX);
/* Toggle the LED to show a new string is being transmitted. */
vParTestToggleLED( mainCOMMS_TX_LED );
/* Delay before we start the string off again. A pseudo-random delay
is used as this will provide a better test. */
xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );
pulRandomBytes++;
if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )
{
pulRandomBytes = mainFIRST_PROGRAM_BYTES;
}
/* Make sure we don't wait too long... */
xDelayPeriod &= mainMAX_TX_DELAY;
/* ...but we do want to wait. */
if( xDelayPeriod < mainMIN_TX_DELAY )
{
xDelayPeriod = mainMIN_TX_DELAY;
}
/* Block for the random(ish) time. */
crDELAY( xHandle, xDelayPeriod );
}
/* Co-routine MUST end with a call to crEND. */
crEND();
}
/*-----------------------------------------------------------*/
static void vSerialInit( void )
{
/* Enable the UART. GPIOA has already been initialised. */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
/* Set GPIO A0 and A1 as peripheral function. They are used to output the
UART signals. */
GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );
/* Configure the UART for 8-N-1 operation. */
UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );
/* We dont want to use the fifo. This is for test purposes to generate
as many interrupts as possible. */
HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;
/* Enable both Rx and Tx interrupts. */
HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );
IntEnable( INT_UART0 );
}
/*-----------------------------------------------------------*/
void vUART_ISR(void)
{
unsigned long ulStatus;
char cRxedChar;
portBASE_TYPE xTaskWokenByPost = pdFALSE;
/* What caused the interrupt. */
ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );
/* Clear the interrupt. */
UARTIntClear( UART0_BASE, ulStatus );
/* Was an Rx interrpt pending? */
if( ulStatus & UART_INT_RX )
{
if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )
{
/* Get the char from the buffer and post it onto the queue of
Rxed chars. Posting the character should wake the task that is
blocked on the queue waiting for characters. */
cRxedChar = ( char ) HWREG( UART0_BASE + UART_O_DR );
xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );
}
}
/* Was a Tx interrupt pending? */
if( ulStatus & UART_INT_TX )
{
/* Send the next character in the string. We are not using the FIFO. */
if( cNextChar <= mainLAST_TX_CHAR )
{
if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )
{
HWREG( UART0_BASE + UART_O_DR ) = cNextChar;
}
cNextChar++;
}
}
if( xTaskWokenByPost )
{
/* We are posting to a co-routine rather than a task so don't bother
causing a task switch. */
}
}
/*-----------------------------------------------------------*/
static void prvPDCWrite( char cAddress, char cData )
{
vTaskSuspendAll();
{
PDCWrite( cAddress, cData );
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vSetErrorLED( void )
{
vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE );
}
/*-----------------------------------------------------------*/
void prvSetAndCheckRegisters( void )
{
/* Fill the general purpose registers with known values. */
__asm volatile
(
" mov r11, #10 \n"
" add r0, r11, #1 \n"
" add r1, r11, #2 \n"
" add r2, r11, #3 \n"
" add r3, r11, #4 \n"
" add r4, r11, #5 \n"
" add r5, r11, #6 \n"
" add r6, r11, #7 \n"
" add r7, r11, #8 \n"
" add r8, r11, #9 \n"
" add r9, r11, #10 \n"
" add r10, r11, #11 \n"
" add r12, r11, #12"
);
/* Check the values are as expected. */
__asm volatile
(
" cmp r11, #10 \n"
" bne set_error_led \n"
" cmp r0, #11 \n"
" bne set_error_led \n"
" cmp r1, #12 \n"
" bne set_error_led \n"
" cmp r2, #13 \n"
" bne set_error_led \n"
" cmp r3, #14 \n"
" bne set_error_led \n"
" cmp r4, #15 \n"
" bne set_error_led \n"
" cmp r5, #16 \n"
" bne set_error_led \n"
" cmp r6, #17 \n"
" bne set_error_led \n"
" cmp r7, #18 \n"
" bne set_error_led \n"
" cmp r8, #19 \n"
" bne set_error_led \n"
" cmp r9, #20 \n"
" bne set_error_led \n"
" cmp r10, #21 \n"
" bne set_error_led \n"
" cmp r12, #22 \n"
" bne set_error_led \n"
" bx lr"
);
__asm volatile
(
"set_error_led: \n"
" push {r14} \n"
" ldr r1, vSetErrorLEDConst\n"
" blx r1 \n"
" pop {r14} \n"
" bx lr \n"
" \n"
" .align 2 \n"
"vSetErrorLEDConst: .word vSetErrorLED"
);
}
/*-----------------------------------------------------------*/

120
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s Normal file
View file

@ -0,0 +1,120 @@
/*****************************************************************************
* Copyright (c) 2006 Rowley Associates Limited. *
* *
* This file may be distributed under the terms of the License Agreement *
* provided with this software. *
* *
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
*****************************************************************************/
.section .vectors, "ax"
.code 16
.align 0
.global _vectors
.extern xPortPendSVHandler
.extern xPortSysTickHandler
.extern vUART_ISR
.extern vPortSVCHandler
.macro DEFAULT_ISR_HANDLER name=
.thumb_func
.weak \name
\name:
1: b 1b /* endless loop */
.endm
_vectors:
.word __stack_end__
#ifdef STARTUP_FROM_RESET
.word _start
#else
.word reset_wait
#endif /* STARTUP_FROM_RESET */
.word NmiISR
.word FaultISR
.word 0 // Populate if using MemManage (MPU)
.word 0 // Populate if using Bus fault
.word 0 // Populate if using Usage fault
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word vPortSVCHandler
.word 0 // Populate if using a debug monitor
.word 0 // Reserved
.word xPortPendSVHandler // Populate if using pendable service request
.word xPortSysTickHandler
// External interrupts start her
.word GPIO_Port_A_ISR
.word GPIO_Port_B_ISR
.word GPIO_Port_C_ISR
.word GPIO_Port_D_ISR
.word GPIO_Port_E_ISR
.word vUART_ISR
.word UART1_ISR
.word SSI_ISR
.word I2C_ISR
.word PWM_Fault_ISR
.word PWM_Generator_0_ISR
.word PWM_Generator_1_ISR
.word PWM_Generator_2_ISR
.word QEI_ISR
.word ADC_Sequence_0_ISR
.word ADC_Sequence_1_ISR
.word ADC_Sequence_2_ISR
.word ADC_Sequence_3_ISR
.word Watchdog_timer_ISR
.word Timer0a_ISR
.word Timer0b_ISR
.word Timer1a_ISR
.word Timer1b_ISR
.word Timer2a_ISR
.word Timer2b_ISR
.word Analog_Comparator_0_ISR
.word Analog_Comparator_1_ISR
.word Analog_Comparator_2_ISR
.word System_Control_ISR
.word FLASH_Control_ISR
.section .init, "ax"
.thumb_func
DEFAULT_ISR_HANDLER NmiISR
DEFAULT_ISR_HANDLER FaultISR
DEFAULT_ISR_HANDLER SVCallISR
DEFAULT_ISR_HANDLER SysTickISR
DEFAULT_ISR_HANDLER GPIO_Port_A_ISR
DEFAULT_ISR_HANDLER GPIO_Port_B_ISR
DEFAULT_ISR_HANDLER GPIO_Port_C_ISR
DEFAULT_ISR_HANDLER GPIO_Port_D_ISR
DEFAULT_ISR_HANDLER GPIO_Port_E_ISR
DEFAULT_ISR_HANDLER UART0_ISR
DEFAULT_ISR_HANDLER UART1_ISR
DEFAULT_ISR_HANDLER SSI_ISR
DEFAULT_ISR_HANDLER I2C_ISR
DEFAULT_ISR_HANDLER PWM_Fault_ISR
DEFAULT_ISR_HANDLER PWM_Generator_0_ISR
DEFAULT_ISR_HANDLER PWM_Generator_1_ISR
DEFAULT_ISR_HANDLER PWM_Generator_2_ISR
DEFAULT_ISR_HANDLER QEI_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR
DEFAULT_ISR_HANDLER Watchdog_timer_ISR
DEFAULT_ISR_HANDLER Timer0a_ISR
DEFAULT_ISR_HANDLER Timer0b_ISR
DEFAULT_ISR_HANDLER Timer1a_ISR
DEFAULT_ISR_HANDLER Timer1b_ISR
DEFAULT_ISR_HANDLER Timer2a_ISR
DEFAULT_ISR_HANDLER Timer2b_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
DEFAULT_ISR_HANDLER System_Control_ISR
DEFAULT_ISR_HANDLER FLASH_Control_ISR
#ifndef STARTUP_FROM_RESET
DEFAULT_ISR_HANDLER reset_wait
#endif /* STARTUP_FROM_RESET */

114
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h Normal file
View file

@ -0,0 +1,114 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 0
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 59 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) )
#define configMAX_TASK_NAME_LEN ( 3 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 0
#define INCLUDE_vTaskDelayUntil 0
#define INCLUDE_vTaskDelay 0
#define configKERNEL_INTERRUPT_PRIORITY 255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */
#endif /* FREERTOS_CONFIG_H */

146
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c Normal file
View file

@ -0,0 +1,146 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
/*
*/
/* Kernel include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "partest.h"
/* Hardware specific include files. */
#include "DriverLib.h"
static const unsigned long ulLEDs[] =
{
GPIO_PIN_6, GPIO_PIN_1, GPIO_PIN_0
};
#define partstLED_PINS ( GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_6 )
#define partstMAX_OUTPUT_LED ( ( unsigned char ) 3 )
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
portBASE_TYPE xLED;
/* The LED's are on port B. */
GPIODirModeSet( GPIO_PORTB_BASE, partstLED_PINS, GPIO_DIR_MODE_OUT );
for( xLED = 0; xLED < partstMAX_OUTPUT_LED; xLED++ )
{
vParTestSetLED( xLED, pdFALSE );
}
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
vTaskSuspendAll();
{
if( uxLED < partstMAX_OUTPUT_LED )
{
if( xValue == pdFALSE )
{
GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] );
}
else
{
GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] );
}
}
}
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
portBASE_TYPE xCurrentValue;
vTaskSuspendAll();
{
if( uxLED < partstMAX_OUTPUT_LED )
{
xCurrentValue = GPIOPinRead( GPIO_PORTB_BASE, ulLEDs[ uxLED ] );
if( xCurrentValue )
{
GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] );
}
else
{
GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] );
}
}
}
xTaskResumeAll();
}

324
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c Normal file
View file

@ -0,0 +1,324 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
* This is a mini co-routine demo for the Rowley CrossFire LM3S102 development
* board. It makes use of the boards tri-colour LED and analogue input.
*
* Four co-routines are created - an 'I2C' co-routine and three 'flash'
* co-routines.
*
* The I2C co-routine triggers an ADC conversion then blocks on a queue to
* wait for the conversion result - which it receives on the queue directly
* from the I2C interrupt service routine. The conversion result is then
* scalled to a delay period. The I2C interrupt then wakes each of the
* flash co-routines before itself delaying for the calculated period and
* then repeating the whole process.
*
* When woken by the I2C co-routine the flash co-routines each block for
* a given period, illuminate an LED for a fixed period, then go back to
* sleep to wait for the next cycle. The uxIndex parameter of the flash
* co-routines is used to ensure that each flashes a different LED, and that
* the delay periods are such that the LED's get flashed in sequence.
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "croutine.h"
/* Demo application include files. */
#include "partest.h"
/* Library include files. */
#include "DriverLib.h"
/* States of the I2C master interface. */
#define mainI2C_IDLE 0
#define mainI2C_READ_1 1
#define mainI2C_READ_2 2
#define mainI2C_READ_DONE 3
#define mainZERO_LENGTH 0
/* Address of the A2D IC on the CrossFire board. */
#define mainI2CAddress 0x4D
/* The queue used to send data from the I2C ISR to the co-routine should never
contain more than one item as the same co-routine is used to trigger the I2C
activity. */
#define mainQUEUE_LENGTH 1
/* The CrossFire board contains a tri-colour LED. */
#define mainNUM_LEDs 3
/* The I2C co-routine has a higher priority than the flash co-routines. This
is not really necessary as when the I2C co-routine is active the other
co-routines are delaying. */
#define mainI2c_CO_ROUTINE_PRIORITY 1
/* The current state of the I2C master. */
static volatile unsigned portBASE_TYPE uxState = mainI2C_IDLE;
/* The delay period derived from the A2D value. */
static volatile portBASE_TYPE uxDelay = 250;
/* The queue used to communicate between the I2C interrupt and the I2C
co-routine. */
static xQueueHandle xADCQueue;
/* The queue used to synchronise the flash co-routines. */
static xQueueHandle xDelayQueue;
/*
* Sets up the PLL, I2C and GPIO used by the demo.
*/
static void prvSetupHardware( void );
/* The co-routines as described at the top of the file. */
static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );
/*-----------------------------------------------------------*/
int main( void )
{
unsigned portBASE_TYPE uxCoRoutine;
/* Setup all the hardware used by this demo. */
prvSetupHardware();
/* Create the queue used to communicate between the ISR and I2C co-routine.
This can only ever contain one value. */
xADCQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( portTickType ) );
/* Create the queue used to synchronise the flash co-routines. The queue
is used to trigger three tasks, but is for synchronisation only and does
not pass any data. It therefore has three position each of zero length. */
xDelayQueue = xQueueCreate( mainNUM_LEDs, mainZERO_LENGTH );
/* Create the co-routine that initiates the i2c. */
xCoRoutineCreate( vI2CCoRoutine, mainI2c_CO_ROUTINE_PRIORITY, 0 );
/* Create the flash co-routines. */
for( uxCoRoutine = 0; uxCoRoutine < mainNUM_LEDs; uxCoRoutine++ )
{
xCoRoutineCreate( vFlashCoRoutine, tskIDLE_PRIORITY, uxCoRoutine );
}
/* Start the scheduler. From this point on the co-routines should
execute. */
vTaskStartScheduler();
/* Should not get here unless we did not have enough memory to start the
scheduler. */
for( ;; );
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL. */
SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );
/* Enable the I2C used to read the pot. */
SysCtlPeripheralEnable( SYSCTL_PERIPH_I2C );
SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOB );
GPIOPinTypeI2C( GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3 );
/* Initialize the I2C master. */
I2CMasterInit( I2C_MASTER_BASE, pdFALSE );
/* Enable the I2C master interrupt. */
I2CMasterIntEnable( I2C_MASTER_BASE );
IntEnable( INT_I2C );
/* Initialise the hardware used to talk to the LED's. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
portTickType xADCResult;
static portBASE_TYPE xResult = 0, xMilliSecs, xLED;
crSTART( xHandle );
for( ;; )
{
/* Start the I2C off to read the ADC. */
uxState = mainI2C_READ_1;
I2CMasterSlaveAddrSet( I2C_MASTER_BASE, mainI2CAddress, pdTRUE );
I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START );
/* Wait to receive the conversion result. */
crQUEUE_RECEIVE( xHandle, xADCQueue, &xADCResult, portMAX_DELAY, &xResult );
/* Scale the result to give a useful range of values for a visual
demo. */
xADCResult >>= 2;
xMilliSecs = xADCResult / portTICK_RATE_MS;
/* The delay is split between the four co-routines so they remain in
synch. */
uxDelay = xMilliSecs / ( mainNUM_LEDs + 1 );
/* Trigger each of the flash co-routines. */
for( xLED = 0; xLED < mainNUM_LEDs; xLED++ )
{
crQUEUE_SEND( xHandle, xDelayQueue, &xLED, 0, &xResult );
}
/* Wait for the full delay time then start again. This delay is long
enough to ensure the flash co-routines have done their thing and gone
back to sleep. */
crDELAY( xHandle, xMilliSecs );
}
crEND();
}
/*-----------------------------------------------------------*/
static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
{
portBASE_TYPE xResult, xNothing;
crSTART( xHandle );
for( ;; )
{
/* Wait for start of next round. */
crQUEUE_RECEIVE( xHandle, xDelayQueue, &xNothing, portMAX_DELAY, &xResult );
/* Wait until it is this co-routines turn to flash. */
crDELAY( xHandle, uxDelay * uxIndex );
/* Turn on the LED for a fixed period. */
vParTestSetLED( uxIndex, pdTRUE );
crDELAY( xHandle, uxDelay );
vParTestSetLED( uxIndex, pdFALSE );
/* Go back and wait for the next round. */
}
crEND();
}
/*-----------------------------------------------------------*/
void vI2C_ISR(void)
{
static portTickType xReading;
/* Clear the interrupt. */
I2CMasterIntClear( I2C_MASTER_BASE );
/* Determine what to do based on the current uxState. */
switch (uxState)
{
case mainI2C_IDLE: break;
case mainI2C_READ_1: /* Read ADC result high byte. */
xReading = I2CMasterDataGet( I2C_MASTER_BASE );
xReading <<= 8;
/* Continue the burst read. */
I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT );
uxState = mainI2C_READ_2;
break;
case mainI2C_READ_2: /* Read ADC result low byte. */
xReading |= I2CMasterDataGet( I2C_MASTER_BASE );
/* Finish the burst read. */
I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH );
uxState = mainI2C_READ_DONE;
break;
case mainI2C_READ_DONE: /* Complete. */
I2CMasterDataGet( I2C_MASTER_BASE );
uxState = mainI2C_IDLE;
/* Send the result to the co-routine. */
crQUEUE_SEND_FROM_ISR( xADCQueue, &xReading, pdFALSE );
break;
}
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
for( ;; )
{
vCoRoutineSchedule();
}
}

121
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s Normal file
View file

@ -0,0 +1,121 @@
/*****************************************************************************
* Copyright (c) 2006 Rowley Associates Limited. *
* *
* This file may be distributed under the terms of the License Agreement *
* provided with this software. *
* *
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
*****************************************************************************/
.section .vectors, "ax"
.code 16
.align 0
.global _vectors
.extern xPortPendSVHandler
.extern xPortSysTickHandler
.extern vI2C_ISR
.extern faultisr
.extern vPortSVCHandler
.macro DEFAULT_ISR_HANDLER name=
.thumb_func
.weak \name
\name:
1: b 1b /* endless loop */
.endm
_vectors:
.word __stack_end__
#ifdef STARTUP_FROM_RESET
.word _start
#else
.word reset_wait
#endif /* STARTUP_FROM_RESET */
.word NmiISR
.word FaultISR
.word 0 // Populate if using MemManage (MPU)
.word 0 // Populate if using Bus fault
.word 0 // Populate if using Usage fault
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word vPortSVCHandler
.word 0 // Populate if using a debug monitor
.word 0 // Reserved
.word xPortPendSVHandler // Populate if using pendable service request
.word xPortSysTickHandler
// External interrupts start her
.word GPIO_Port_A_ISR
.word GPIO_Port_B_ISR
.word GPIO_Port_C_ISR
.word GPIO_Port_D_ISR
.word GPIO_Port_E_ISR
.word UART0_ISR
.word UART1_ISR
.word SSI_ISR
.word vI2C_ISR
.word PWM_Fault_ISR
.word PWM_Generator_0_ISR
.word PWM_Generator_1_ISR
.word PWM_Generator_2_ISR
.word QEI_ISR
.word ADC_Sequence_0_ISR
.word ADC_Sequence_1_ISR
.word ADC_Sequence_2_ISR
.word ADC_Sequence_3_ISR
.word Watchdog_timer_ISR
.word Timer0a_ISR
.word Timer0b_ISR
.word Timer1a_ISR
.word Timer1b_ISR
.word Timer2a_ISR
.word Timer2b_ISR
.word Analog_Comparator_0_ISR
.word Analog_Comparator_1_ISR
.word Analog_Comparator_2_ISR
.word System_Control_ISR
.word FLASH_Control_ISR
.section .init, "ax"
.thumb_func
DEFAULT_ISR_HANDLER NmiISR
DEFAULT_ISR_HANDLER FaultISR
DEFAULT_ISR_HANDLER SVCallISR
DEFAULT_ISR_HANDLER SysTickISR
DEFAULT_ISR_HANDLER GPIO_Port_A_ISR
DEFAULT_ISR_HANDLER GPIO_Port_B_ISR
DEFAULT_ISR_HANDLER GPIO_Port_C_ISR
DEFAULT_ISR_HANDLER GPIO_Port_D_ISR
DEFAULT_ISR_HANDLER GPIO_Port_E_ISR
DEFAULT_ISR_HANDLER UART0_ISR
DEFAULT_ISR_HANDLER UART1_ISR
DEFAULT_ISR_HANDLER SSI_ISR
DEFAULT_ISR_HANDLER I2C_ISR
DEFAULT_ISR_HANDLER PWM_Fault_ISR
DEFAULT_ISR_HANDLER PWM_Generator_0_ISR
DEFAULT_ISR_HANDLER PWM_Generator_1_ISR
DEFAULT_ISR_HANDLER PWM_Generator_2_ISR
DEFAULT_ISR_HANDLER QEI_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR
DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR
DEFAULT_ISR_HANDLER Watchdog_timer_ISR
DEFAULT_ISR_HANDLER Timer0a_ISR
DEFAULT_ISR_HANDLER Timer0b_ISR
DEFAULT_ISR_HANDLER Timer1a_ISR
DEFAULT_ISR_HANDLER Timer1b_ISR
DEFAULT_ISR_HANDLER Timer2a_ISR
DEFAULT_ISR_HANDLER Timer2b_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR
DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
DEFAULT_ISR_HANDLER System_Control_ISR
DEFAULT_ISR_HANDLER FLASH_Control_ISR
#ifndef STARTUP_FROM_RESET
DEFAULT_ISR_HANDLER reset_wait
#endif /* STARTUP_FROM_RESET */

110
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp Normal file
View file

@ -0,0 +1,110 @@
<!DOCTYPE CrossStudio_Project_File>
<solution version="1" Name="RTOSDemo" >
<project Name="Demo1" >
<configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="_start" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="200" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
<configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
<configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
<folder Name="Source Files" >
<configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
<folder Name="Demo Source" >
<file file_name="../Common/Minimal/crflash.c" Name="crflash.c" />
<file file_name="Demo1/main.c" Name="main.c" />
<file file_name="Demo1/ParTest.c" Name="ParTest.c" />
</folder>
<folder Name="RTOS Source" >
<file file_name="../../Source/tasks.c" Name="tasks.c" />
<file file_name="../../Source/croutine.c" Name="croutine.c" />
<file file_name="../../Source/list.c" Name="list.c" />
<file file_name="../../Source/queue.c" Name="queue.c" />
<file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
<configuration gcc_optimization_level="Level 1" Name="Flash Release" />
</file>
<file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
</folder>
<folder Name="Library" >
<file file_name="hw_include/pdc.c" Name="pdc.c" />
</folder>
</folder>
<folder Name="System Files" >
<file file_name="$(StudioDir)/source/thumb_crt0.s" Name="thumb_crt0.s" />
<file file_name="$(StudioDir)/targets/Luminary_LM3S/LM3S_Target.js" Name="LM3S_Target.js" >
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="Demo1/vectors.s" Name="vectors.s" />
</folder>
<configuration linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="_start" build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="" arm_use_gcc_libraries="No" arm_core_type="Cortex-M3" linker_output_format="None" arm_linker_heap_size="0" />
<configuration linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" Name="Flash Debug" arm_linker_heap_size="0" />
</project>
<configuration inherited_configurations="Flash;Release" c_preprocessor_definitions="" Name="Flash Release" />
<configuration c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes" Name="Flash" />
<configuration c_preprocessor_definitions="NDEBUG;STARTUP_FROM_RESET" arm_architecture="v7M" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" linker_printf_width_precision_supported="No" hidden="Yes" Name="Release" arm_core_type="Cortex-M3" />
<project Name="Demo2" >
<configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
<configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
<configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
<folder Name="Source Files" >
<configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
<folder Name="Demo Source" >
<file file_name="../Common/Minimal/crflash.c" Name="crflash.c" />
<file file_name="Demo2/main.c" Name="main.c" />
<file file_name="Demo2/ParTest.c" Name="ParTest.c" />
</folder>
<folder Name="RTOS Source" >
<file file_name="../../Source/tasks.c" Name="tasks.c" />
<file file_name="../../Source/croutine.c" Name="croutine.c" />
<file file_name="../../Source/list.c" Name="list.c" />
<file file_name="../../Source/queue.c" Name="queue.c" />
<file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
<configuration gcc_optimization_level="Level 1" Name="Flash Release" />
</file>
<file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
</folder>
<folder Name="Library" >
<file file_name="hw_include/pdc.c" Name="pdc.c" />
</folder>
</folder>
<folder Name="System Files" >
<file file_name="$(StudioDir)/source/thumb_crt0.s" Name="thumb_crt0.s" />
<file file_name="$(StudioDir)/targets/Luminary_LM3S/LM3S_Target.js" Name="LM3S_Target.js" >
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="Demo2/vectors.s" Name="vectors.s" />
</folder>
<configuration gcc_entry_point="_start" build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo2;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
<configuration gcc_entry_point="_start" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" arm_linker_stack_size="200" Name="Flash Debug" arm_linker_heap_size="0" />
</project>
<project Name="Demo3" >
<configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
<configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
<configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
<folder Name="Source Files" >
<configuration filter="c;cpp;cxx;cc;h;s;asm;inc" Name="Common" />
<folder Name="Demo Source" >
<file file_name="Demo3/main.c" Name="main.c" />
<file file_name="Demo3/ParTest.c" Name="ParTest.c" />
</folder>
<folder Name="RTOS Source" >
<file file_name="../../Source/tasks.c" Name="tasks.c" />
<file file_name="../../Source/croutine.c" Name="croutine.c" />
<file file_name="../../Source/list.c" Name="list.c" />
<file file_name="../../Source/queue.c" Name="queue.c" />
<file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
<configuration gcc_optimization_level="None" Name="Flash Release" />
</file>
<file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
</folder>
</folder>
<folder Name="System Files" >
<file file_name="$(StudioDir)/source/thumb_crt0.s" Name="thumb_crt0.s" />
<file file_name="$(StudioDir)/targets/Luminary_LM3S/LM3S_Target.js" Name="LM3S_Target.js" >
<configuration Name="Common" file_type="Reset Script" />
</file>
<file file_name="Demo3/vectors.s" Name="vectors.s" />
</folder>
<configuration gcc_entry_point="_start" build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo3;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
<configuration gcc_entry_point="_start" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" arm_linker_stack_size="200" Name="Flash Debug" arm_linker_heap_size="0" />
</project>
<configuration build_remove_unused_symbols="Yes" arm_architecture="v7M" linker_printf_width_precision_supported="No" hidden="Yes" Name="debug" arm_core_type="Cortex-M3" />
<configuration inherited_configurations="debug;Flash" gcc_optimization_level="Level 1" Name="Flash Debug" />
<configuration linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" arm_linker_fiq_stack_size="0" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo1;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" arm_linker_irq_stack_size="0" link_symbol_definitions="" arm_linker_stack_size="200" Name="Common" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" />
</solution>

105
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs Normal file
View file

@ -0,0 +1,105 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<session>
<Autos>
<Watches active="0" />
</Autos>
<Bookmarks/>
<Breakpoints>
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="D_Abort" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="FIQ" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="IRQ" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="P_Abort" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Reset" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="SWI" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Undef" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="BusFault" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="ExceptionEntryReturnFault" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="HardFault" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="MemManage" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Reset" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_CheckingError" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_Coprocessor" filename="" />
<BreakpointListItem actiontype="0" chainFrom="" line="-1" defaultBreakType="true" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_StateError" filename="" />
</Breakpoints>
<ExecutionCountWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x20000000" numColumns="8" sizeText="2048" dataSize="1" radix="16" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
</Memory4>
<MemoryUsageWindow>
<ProjectSessionItem path="RTOSDemo" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo2" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo2;Source Files" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo2;Source Files;Demo Source" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3;Source Files" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3;Source Files;Demo Source" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3;Source Files;RTOS Source" name="unnamed" />
</MemoryUsageWindow>
<Project>
<ProjectSessionItem path="RTOSDemo" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo2" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo2;Source Files" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo2;Source Files;Demo Source" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3;Source Files" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3;Source Files;Demo Source" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;Demo3;Source Files;RTOS Source" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="CPU - Current Mode" decimalNodes="" octalNodes="" asciiNodes="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
</Register4>
<SourceNavigatorWindow/>
<TraceWindow>
<Trace wrap="Yes" type="1" enabled="Yes" />
</TraceWindow>
<Watch1>
<Watches active="0" >
<Watchpoint linenumber="0" radix="16" name="ul" expression="ul" filename="" />
<Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="pxCurrentTCB" expression="pxCurrentTCB" filename="" />
<Watchpoint linenumber="0" radix="-1" name="uxCriticalNesting" expression="uxCriticalNesting" filename="" />
<Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="ulglob" expression="ulglob" filename="" />
</Watches>
</Watch1>
<Watch2>
<Watches active="0" />
</Watch2>
<Watch3>
<Watches active="0" />
</Watch3>
<Watch4>
<Watches active="1" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="1" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_LM3S102_Rowley\Demo2\main.c" y="269" path="C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_LM3S102_Rowley\Demo2\main.c" left="0" selected="0" name="unnamed" top="235" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_LM3S102_Rowley\Demo3\main.c" y="135" path="C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_LM3S102_Rowley\Demo3\main.c" left="0" selected="0" name="unnamed" top="129" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="38" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy2\Source\queue.c" y="391" path="C:\E\Dev\FreeRTOS\WorkingCopy2\Source\queue.c" left="0" selected="1" name="unnamed" top="371" />
</Files>
<ARMCrossStudioWindow activeProject="Demo3" autoConnectTarget="/USB CrossConnect for ARM" debugSearchFileMap="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\gpio.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\gpio.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\interrupt.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\interrupt.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\ssi.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\ssi.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\sysctl.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\uart.c
C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\uart.c" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3" fileDialogDefaultFilter="*.asm;*.s;*.inc" autoConnectCapabilities="1919" debugSearchPath="" buildConfiguration="Flash Debug" />
</session>

20
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h Normal file
View file

@ -0,0 +1,20 @@
#ifndef INCLUDE_DRIVER_LIB_H
#define INCLUDE_DRIVER_LIB_H
#include "hw_ints.h"
#include "hw_uart.h"
#include "hw_memmap.h"
#include "hw_types.h"
#include "hw_nvic.h"
#include "hw_ssi.h"
#include "hw_i2c.h"
#include "gpio.h"
#include "interrupt.h"
#include "sysctl.h"
#include "uart.h"
#include "ssi.h"
#include "pdc.h"
#include "i2c.h"
#endif

126
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt Normal file
View file

@ -0,0 +1,126 @@
IMPORTANT. Read the following LMI Software License Agreement ("Agreement")
completely.
LUMINARY MICRO SOFTWARE LICENSE AGREEMENT
This is a legal agreement between you (either as an individual or as an
authorized representative of your employer) and Luminary Micro, Inc. ("LMI").
It concerns your rights to use this file and any accompanying written materials
(the "Software"). In consideration for LMI allowing you to access the
Software, you are agreeing to be bound by the terms of this Agreement. If you
do not agree to all of the terms of this Agreement, do not download or use the
Software. If you change your mind later, stop using the Software and delete
all copies of the Software in your possession or control. Any copies of the
Software that you have already distributed, where permitted, and do not destroy
will continue to be governed by this Agreement. Your prior use will also
continue to be governed by this Agreement.
1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive,
non-transferable right (1) to use the Software, (2) to reproduce the Software,
(3) to prepare derivative works of the Software, (4) to distribute the Software
and derivative works thereof in source (human-readable) form and object
(machine-readable) form, and (5) to sublicense to others the right to use the
distributed Software. If you violate any of the terms or restrictions of this
Agreement, LMI may immediately terminate this Agreement, and require that you
stop using and delete all copies of the Software in your possession or control.
2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the
Software, and United States copyright laws and international treaty provisions
protect the Software. Therefore, you must treat the Software like any other
copyrighted material (e.g. a book or musical recording). You may not use or
copy the Software for any other purpose than what is described in this
Agreement. Except as expressly provided herein, LMI does not grant to you any
express or implied rights under any LMI or third-party patents, copyrights,
trademarks, or trade secrets. Additionally, you must reproduce and apply any
copyright or other proprietary rights notices included on or embedded in the
Software to any copies or derivative works made thereof, in whole or in part,
if any.
3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new
releases of the Software. If you wish, you may contact LMI and report problems
and provide suggestions regarding the Software. LMI has no obligation
whatsoever to respond in any way to such a problem report or suggestion. LMI
may make changes to the Software at any time, without any obligation to notify
or provide updated versions of the Software to you.
4. INDEMNITY. You agree to fully defend and indemnify LMI from any and
all claims, liabilities, and costs (including reasonable attorney’s fees)
related to (1) your use (including your sub-licensee’s use, if permitted) of
the Software or (2) your violation of the terms and conditions of this
Agreement.
5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault
tolerant and is not designed, manufactured or intended by LMI for incorporation
into products intended for use or resale in on-line control equipment in
hazardous, dangerous to life or potentially life-threatening environments
requiring fail-safe performance, such as in the operation of nuclear
facilities, aircraft navigation or communication systems, air traffic control,
direct life support machines or weapons systems, in which the failure of
products could lead directly to death, personal injury or severe physical or
environmental damage ("High Risk Activities"). You specifically represent and
warrant that you will not use the Software or any derivative work of the
Software for High Risk Activities.
6. PRODUCT LABELING. You are not authorized to use any LMI trademarks,
brand names, or logos.
7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software
in accordance with all applicable U.S. laws, regulations and statutes. You
agree that neither you nor your licensees (if any) intend to or will, directly
or indirectly, export or transmit the Software to any country in violation of
U.S. export restrictions.
8. GOVERNMENT USE. Use of the Software and any corresponding
documentation, if any, is provided with RESTRICTED RIGHTS. Use, duplication or
disclosure by the Government is subject to restrictions as set forth in
subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software
clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial
Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable.
Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100,
Austin, Texas 78746.
9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI
EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED
"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING,
WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING
OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING
THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A
WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK
DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF
THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.
10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN
CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT,
CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR
ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS,
SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.
11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and
laws of the United States and the State of Texas, USA, without regard to
conflicts of laws principles, will apply to all matters relating to this
Agreement or the Software, and you agree that any litigation will be subject to
the exclusive jurisdiction of the state or federal courts in Austin, Travis
County, Texas, USA. You agree that regardless of any statute or law to the
contrary, any claim or cause of action arising out of or related to this
Agreement or the Software must be filed within one (1) year after such claim or
cause of action arose or be forever barred.
12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement
between you and LMI regarding the subject matter of this Agreement, and
supersedes all prior communications, negotiations, understandings, agreements
or representations, either written or oral, if any. This Agreement may only be
amended in written form, executed by you and LMI.
13. SEVERABILITY. If any provision of this Agreement is held for any
reason to be invalid or unenforceable, then the remaining provisions of this
Agreement will be unimpaired and, unless a modification or replacement of the
invalid or unenforceable provision is further held to deprive you or LMI of a
material benefit, in which case the Agreement will immediately terminate, the
invalid or unenforceable provision will be replaced with a provision that is
valid and enforceable and that comes closest to the intention underlying the
invalid or unenforceable provision.
14. NO WAIVER. The waiver by LMI of any breach of any provision of this
Agreement will not operate or be construed as a waiver of any other or a
subsequent breach of the same or a different provision.

112
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h Normal file
View file

@ -0,0 +1,112 @@
//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_INT_xxx, COMP_ASRCP_xxx, etc.), one of
// the values may be selected and ORed together will values from the other
// groups.
//
//*****************************************************************************
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

40
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h Normal file
View file

@ -0,0 +1,40 @@
//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void CPUcpsid(void);
extern void CPUcpsie(void);
extern void CPUwfi(void);
#endif // __CPU_H__

56
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h Normal file
View file

@ -0,0 +1,56 @@
//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

75
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h Normal file
View file

@ -0,0 +1,75 @@
//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntGetStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

135
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h Normal file
View file

@ -0,0 +1,135 @@
//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

113
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h Normal file
View file

@ -0,0 +1,113 @@
//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following define the offsets of the comparator registers.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
//*****************************************************************************
//
// The following define the bit fields in the COMP_MIS, COMP_RIS, and
// COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following define the bit fields in the COMP_REFCTL register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACSTAT0 and COMP_ACSTAT1
// registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following define the bit fields in the COMP_ACCTL0 and COMP_ACCTL1
// registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following define the reset values for the comparator registers.
//
//*****************************************************************************
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#endif // __HW_COMP_H__

141
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h Normal file
View file

@ -0,0 +1,141 @@
//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following define the offsets of the FLASH registers.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Memory address register
#define FLASH_FMD 0x400FD004 // Memory data register
#define FLASH_FMC 0x400FD008 // Memory control register
#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register
#define FLASH_USECRL 0x400FE140 // uSec reload register
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_REG_MASK 0x00000F00 // Register select mask
#define FLASH_FMC_REG_UDFP 0x00000000 // Select FLASH protection register
#define FLASH_FMC_COMT 0x00000008 // Commit user register
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMIS register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE
// registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following define the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
//*****************************************************************************
//
// The erase size is the size of the FLASH block that is erased by an erase
// operation, and the protect size is the size of the FLASH block that is
// protected by each protection register.
//
//*****************************************************************************
#define FLASH_ERASE_SIZE 0x00000400
#define FLASH_PROTECT_SIZE 0x00000800
#endif // __HW_FLASH_H__

95
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h Normal file
View file

@ -0,0 +1,95 @@
//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// GPIO Register Offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // Data register.
#define GPIO_O_DIR 0x00000400 // Data direction register.
#define GPIO_O_IS 0x00000404 // Interrupt sense register.
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.
#define GPIO_O_IEV 0x0000040C // Intterupt event register.
#define GPIO_O_IM 0x00000410 // Interrupt mask register.
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.
#define GPIO_O_ICR 0x0000041C // Interrupt clear register.
#define GPIO_O_AFSEL 0x00000420 // Mode control select register.
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.
#define GPIO_O_ODR 0x0000050C // Open drain select register.
#define GPIO_O_PUR 0x00000510 // Pull up select register.
#define GPIO_O_PDR 0x00000514 // Pull down select register.
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
#define GPIO_O_PeriphID0 0x00000FE0 //
#define GPIO_O_PeriphID1 0x00000FE4 //
#define GPIO_O_PeriphID2 0x00000FE8 //
#define GPIO_O_PeriphID3 0x00000FEC //
#define GPIO_O_PCellID0 0x00000FF0 //
#define GPIO_O_PCellID1 0x00000FF4 //
#define GPIO_O_PCellID2 0x00000FF8 //
#define GPIO_O_PCellID3 0x00000FFC //
//*****************************************************************************
//
// GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
#define GPIO_RV_PeriphID0 0x00000061 //
#define GPIO_RV_PeriphID1 0x00000010 //
#define GPIO_RV_PeriphID2 0x00000004 //
#define GPIO_RV_PeriphID3 0x00000000 //
#define GPIO_RV_PCellID0 0x0000000D //
#define GPIO_RV_PCellID1 0x000000F0 //
#define GPIO_RV_PCellID2 0x00000005 //
#define GPIO_RV_PCellID3 0x000000B1 //
#endif // __HW_GPIO_H__

157
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h Normal file
View file

@ -0,0 +1,157 @@
//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following define the offsets of the I2C master registers.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_ICR 0x0000001c // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following define the offsets of the I2C slave registers.
//
//*****************************************************************************
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_ICR 0x00000018 // Interrupt clear register
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Control and Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
//*****************************************************************************
//
// The following define values used in determining the contents of the I2C
// Master Timer Period register.
//
//*****************************************************************************
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_SCL_FAST 400000 // SCL fast frequency
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Master Configuration
// register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Control/Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Interrupt Mask
// register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Raw Interrupt Status
// register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following define the bit fields in the I2C Slave Masked Interrupt
// Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Master masked interrupt status
#endif // __HW_I2C_H__

82
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h Normal file
View file

@ -0,0 +1,82 @@
//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following define the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following define the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
//*****************************************************************************
//
// The total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 46
//*****************************************************************************
//
// The total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

57
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h Normal file
View file

@ -0,0 +1,57 @@
//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following define the base address of the memories and peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define SSI_BASE 0x40008000 // SSI
#define UART0_BASE 0x4000C000 // UART0
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define COMP_BASE 0x4003C000 // Analog comparators
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
#endif // __HW_MEMMAP_H__

830
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h Normal file
View file

@ -0,0 +1,830 @@
//*****************************************************************************
//
// hw_nvic.h - Macros used when accessing the NVIC hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_NVIC_H__
#define __HW_NVIC_H__
//*****************************************************************************
//
// The following define the addresses of the NVIC registers.
//
//*****************************************************************************
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
//*****************************************************************************
//
// The following define the bit fields in the NVIC_INT_TYPE register.
//
//*****************************************************************************
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
#define NVIC_INT_TYPE_LINES_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CTRL register.
//
//*****************************************************************************
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_RELOAD register.
//
//*****************************************************************************
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
#define NVIC_ST_RELOAD_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CURRENT register.
//
//*****************************************************************************
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
#define NVIC_ST_CURRENT_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ST_CAL register.
//
//*****************************************************************************
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
#define NVIC_ST_CAL_ONEMS_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EN0 register.
//
//*****************************************************************************
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DIS0 register.
//
//*****************************************************************************
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PEND0 register.
//
//*****************************************************************************
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
//*****************************************************************************
//
// The following define the bit fields in the NVIC_UNPEND0 register.
//
//*****************************************************************************
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
//*****************************************************************************
//
// The following define the bit fields in the NVIC_ACTIVE0 register.
//
//*****************************************************************************
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI0 register.
//
//*****************************************************************************
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
#define NVIC_PRI0_INT3_S 24
#define NVIC_PRI0_INT2_S 16
#define NVIC_PRI0_INT1_S 8
#define NVIC_PRI0_INT0_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI1 register.
//
//*****************************************************************************
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
#define NVIC_PRI1_INT7_S 24
#define NVIC_PRI1_INT6_S 16
#define NVIC_PRI1_INT5_S 8
#define NVIC_PRI1_INT4_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI2 register.
//
//*****************************************************************************
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
#define NVIC_PRI2_INT11_S 24
#define NVIC_PRI2_INT10_S 16
#define NVIC_PRI2_INT9_S 8
#define NVIC_PRI2_INT8_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI3 register.
//
//*****************************************************************************
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
#define NVIC_PRI3_INT15_S 24
#define NVIC_PRI3_INT14_S 16
#define NVIC_PRI3_INT13_S 8
#define NVIC_PRI3_INT12_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI4 register.
//
//*****************************************************************************
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
#define NVIC_PRI4_INT19_S 24
#define NVIC_PRI4_INT18_S 16
#define NVIC_PRI4_INT17_S 8
#define NVIC_PRI4_INT16_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI5 register.
//
//*****************************************************************************
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
#define NVIC_PRI5_INT23_S 24
#define NVIC_PRI5_INT22_S 16
#define NVIC_PRI5_INT21_S 8
#define NVIC_PRI5_INT20_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI6 register.
//
//*****************************************************************************
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
#define NVIC_PRI6_INT27_S 24
#define NVIC_PRI6_INT26_S 16
#define NVIC_PRI6_INT25_S 8
#define NVIC_PRI6_INT24_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_PRI7 register.
//
//*****************************************************************************
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
#define NVIC_PRI7_INT31_S 24
#define NVIC_PRI7_INT30_S 16
#define NVIC_PRI7_INT29_S 8
#define NVIC_PRI7_INT28_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_CPUID register.
//
//*****************************************************************************
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
#define NVIC_CPUID_REV_M 0x0000000F // Revision
//*****************************************************************************
//
// The following define the bit fields in the NVIC_INT_CTRL register.
//
//*****************************************************************************
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
#define NVIC_INT_CTRL_VEC_PEN_S 12
#define NVIC_INT_CTRL_VEC_ACT_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_VTABLE register.
//
//*****************************************************************************
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base
#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
#define NVIC_VTABLE_OFFSET_S 8
//*****************************************************************************
//
// The following define the bit fields in the NVIC_APINT register.
//
//*****************************************************************************
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
//*****************************************************************************
//
// The following define the bit fields in the NVIC_CFG_CTRL register.
//
//*****************************************************************************
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI1 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
#define NVIC_SYS_PRI1_USAGE_S 16
#define NVIC_SYS_PRI1_BUS_S 8
#define NVIC_SYS_PRI1_MEM_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI2 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
#define NVIC_SYS_PRI2_SVC_S 24
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_PRI3 register.
//
//*****************************************************************************
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
#define NVIC_SYS_PRI3_TICK_S 24
#define NVIC_SYS_PRI3_PENDSV_S 16
#define NVIC_SYS_PRI3_DEBUG_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SYS_HND_CTRL register.
//
//*****************************************************************************
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_STAT register.
//
//*****************************************************************************
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
//*****************************************************************************
//
// The following define the bit fields in the NVIC_HFAULT_STAT register.
//
//*****************************************************************************
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DEBUG_STAT register.
//
//*****************************************************************************
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MM_ADDR register.
//
//*****************************************************************************
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
#define NVIC_MM_ADDR_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_ADDR register.
//
//*****************************************************************************
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
#define NVIC_FAULT_ADDR_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_STACK register.
//
//*****************************************************************************
#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack
//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_NUM register.
//
//*****************************************************************************
#define NVIC_EXC_NUM_M 0x000003FF // Exception number
#define NVIC_EXC_NUM_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_COPRO register.
//
//*****************************************************************************
#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask
#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied
#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess
#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access
#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask
#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied
#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess
#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access
#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask
#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied
#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess
#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access
#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask
#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied
#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess
#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access
#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask
#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied
#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess
#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access
#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask
#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied
#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess
#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access
#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask
#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied
#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess
#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access
#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask
#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied
#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess
#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access
#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask
#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied
#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess
#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access
#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask
#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied
#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess
#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access
#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask
#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied
#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess
#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access
#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask
#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied
#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess
#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access
#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask
#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied
#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess
#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access
#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask
#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied
#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess
#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access
#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask
#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied
#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess
#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access
#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask
#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied
#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess
#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_TYPE register.
//
//*****************************************************************************
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
#define NVIC_MPU_TYPE_IREGION_S 16
#define NVIC_MPU_TYPE_DREGION_S 8
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_CTRL register.
//
//*****************************************************************************
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_NUMBER register.
//
//*****************************************************************************
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
#define NVIC_MPU_NUMBER_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_BASE register.
//
//*****************************************************************************
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
#define NVIC_MPU_BASE_ADDR_S 8
#define NVIC_MPU_BASE_REGION_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_ATTR register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes
#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable
#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_CTRL register.
//
//*****************************************************************************
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_XFER register.
//
//*****************************************************************************
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_DATA register.
//
//*****************************************************************************
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
#define NVIC_DBG_DATA_S 0
//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_INT register.
//
//*****************************************************************************
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
//*****************************************************************************
//
// The following define the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
#define NVIC_SW_TRIG_INTID_S 0
#endif // __HW_NVIC_H__

113
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h Normal file
View file

@ -0,0 +1,113 @@
//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following define the offsets of the SSI registers.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // Control register 0
#define SSI_O_CR1 0x00000004 // Control register 1
#define SSI_O_DR 0x00000008 // Data register
#define SSI_O_SR 0x0000000C // Status register
#define SSI_O_CPSR 0x00000010 // Clock prescale register
#define SSI_O_IM 0x00000014 // Int mask set and clear register
#define SSI_O_RIS 0x00000018 // Raw interrupt register
#define SSI_O_MIS 0x0000001C // Masked interrupt register
#define SSI_O_ICR 0x00000020 // Interrupt clear register
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 0.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
#define SSI_CR0_DSS 0x0000000F // Data size select
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
//*****************************************************************************
//
// The following define the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
#define SSI_CR1_LBM 0x00000001 // Loopback mode
//*****************************************************************************
//
// The following define the bit fields in the SSI Status register
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy
#define SSI_SR_RFF 0x00000008 // RX FIFO full
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
#define SSI_SR_TNF 0x00000002 // TX FIFO not full
#define SSI_SR_TFE 0x00000001 // TX FIFO empty
//*****************************************************************************
//
// The following define information concerning the SSI Data register.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following define the bit fields in the interrupt mask set and clear,
// raw interrupt, masked interrupt, and interrupt clear registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif // __HW_SSI_H__

325
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h Normal file
View file

@ -0,0 +1,325 @@
//*****************************************************************************
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_SYSCTL_H__
#define __HW_SYSCTL_H__
//*****************************************************************************
//
// The following define the offsets of the system control registers.
//
//*****************************************************************************
#define SYSCTL_DID0 0x400fe000 // Device identification register 0
#define SYSCTL_DID1 0x400fe004 // Device identification register 1
#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
#define SYSCTL_MISC 0x400fe058 // Interrupt status register
#define SYSCTL_RESC 0x400fe05c // Reset cause register
#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID0 register.
//
//*****************************************************************************
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DID1 register.
//
//*****************************************************************************
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
#define SYSCTL_DID1_PRTNO_SHIFT 16
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC0 register.
//
//*****************************************************************************
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
#define SYSCTL_DC2_I2C 0x00001000 // I2C present
#define SYSCTL_DC2_SSI 0x00000010 // SSI present
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC3 register.
//
//*****************************************************************************
#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_DC4 register.
//
//*****************************************************************************
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PBORCTL register.
//
//*****************************************************************************
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
#define SYSCTL_PBORCTL_BOR_SH 2
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOPCTL register.
//
//*****************************************************************************
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
//
//*****************************************************************************
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
//
//*****************************************************************************
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
#define SYSCTL_SET1_I2C 0x00001000 // I2C module
#define SYSCTL_SET1_SSI 0x00000010 // SSI module
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
//
//*****************************************************************************
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
// SYSCTL_IMS registers.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RESC register.
//
//*****************************************************************************
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
#define SYSCTL_RESC_SW 0x00000010 // Software reset
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
#define SYSCTL_RESC_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_RCC register.
//
//*****************************************************************************
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator
#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4
#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_PLLCFG register.
//
//*****************************************************************************
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
#define SYSCTL_PLLCFG_F_SHIFT 5
#define SYSCTL_PLLCFG_R_SHIFT 0
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_CLKVCLR register.
//
//*****************************************************************************
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
//*****************************************************************************
//
// The following define the bit fields in the SYSCTL_LDOARST register.
//
//*****************************************************************************
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
#endif // __HW_SYSCTL_H__

233
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h Normal file
View file

@ -0,0 +1,233 @@
//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following define the offsets of the timer registers.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // Configuration register
#define TIMER_O_TAMR 0x00000004 // TimerA mode register
#define TIMER_O_TBMR 0x00000008 // TimerB mode register
#define TIMER_O_CTL 0x0000000C // Control register
#define TIMER_O_IMR 0x00000018 // Interrupt mask register
#define TIMER_O_RIS 0x0000001C // Interrupt status register
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.
#define TIMER_O_ICR 0x00000024 // Interrupt clear register
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
//*****************************************************************************
//
// The following define the reset values of the timer registers.
//
//*****************************************************************************
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TnMR register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
//*****************************************************************************
//
// The following define the bit fields in the TIMER_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable
//*****************************************************************************
//
// The following define the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask
//*****************************************************************************
//
// The following define the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status
//*****************************************************************************
//
// The following define the bit fields in the TIMER_MIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following define the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPR register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x0000000F // TimerN prescale value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TnPMR register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x0000000F // TimerN prescale match value
//*****************************************************************************
//
// The following define the bit fields in the TIMER_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following defines the bit fields in the TIMER_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
#endif // __HW_TIMER_H__

63
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h Normal file
View file

@ -0,0 +1,63 @@
//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#endif // __HW_TYPES_H__

234
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h Normal file
View file

@ -0,0 +1,234 @@
//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// UART Register Offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // Data Register
#define UART_O_RSR 0x00000004 // Receive Status Register (read)
#define UART_O_ECR 0x00000004 // Error Clear Register (write)
#define UART_O_FR 0x00000018 // Flag Register (read only)
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_CTL 0x00000030 // Control Register
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
//*****************************************************************************
//
// Data Register bits
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // Overrun Error
#define UART_DR_BE 0x00000400 // Break Error
#define UART_DR_PE 0x00000200 // Parity Error
#define UART_DR_FE 0x00000100 // Framing Error
//*****************************************************************************
//
// Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // Overrun Error
#define UART_RSR_BE 0x00000004 // Break Error
#define UART_RSR_PE 0x00000002 // Parity Error
#define UART_RSR_FE 0x00000001 // Framing Error
//*****************************************************************************
//
// Flag Register bits
//
//*****************************************************************************
#define UART_FR_RI 0x100 // Ring Indicator
#define UART_FR_TXFE 0x080 // TX FIFO Empty
#define UART_FR_RXFF 0x040 // RX FIFO Full
#define UART_FR_TXFF 0x020 // TX FIFO Full
#define UART_FR_RXFE 0x010 // RX FIFO Empty
#define UART_FR_BUSY 0x008 // UART Busy
//*****************************************************************************
//
// Line Control Register High bits
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x80 // Stick Parity Select
#define UART_LCR_H_WLEN 0x60 // Word length
#define UART_LCR_H_WLEN_8 0x60 // 8 bit data
#define UART_LCR_H_WLEN_7 0x40 // 7 bit data
#define UART_LCR_H_WLEN_6 0x20 // 6 bit data
#define UART_LCR_H_WLEN_5 0x00 // 5 bit data
#define UART_LCR_H_FEN 0x10 // Enable FIFO
#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x04 // Even Parity Select
#define UART_LCR_H_PEN 0x02 // Parity Enable
#define UART_LCR_H_BRK 0x01 // Send Break
//*****************************************************************************
//
// Control Register bits
//
//*****************************************************************************
#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control
#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control
#define UART_CTL_OUT2 0x2000 // OUT2
#define UART_CTL_OUT1 0x1000 // OUT1
#define UART_CTL_RTS 0x0800 // Request To Send
#define UART_CTL_DTR 0x0400 // Data Terminal Ready
#define UART_CTL_RXE 0x0200 // Receive Enable
#define UART_CTL_TXE 0x0100 // Transmit Enable
#define UART_CTL_LBE 0x0080 // Loopback Enable
#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode
#define UART_CTL_SIREN 0x0002 // SIR Enable
#define UART_CTL_UARTEN 0x0001 // UART Enable
//*****************************************************************************
//
// Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX1_8 0x00 // 1/8 Full
#define UART_IFLS_RX2_8 0x10 // 1/4 Full
#define UART_IFLS_RX4_8 0x20 // 1/2 Full
#define UART_IFLS_RX6_8 0x30 // 3/4 Full
#define UART_IFLS_RX7_8 0x40 // 7/8 Full
#define UART_IFLS_TX1_8 0x00 // 1/8 Full
#define UART_IFLS_TX2_8 0x01 // 1/4 Full
#define UART_IFLS_TX4_8 0x02 // 1/2 Full
#define UART_IFLS_TX6_8 0x03 // 3/4 Full
#define UART_IFLS_TX7_8 0x04 // 7/8 Full
//*****************************************************************************
//
// Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask
#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask
#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x010 // Receive Interrupt Mask
#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask
#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask
#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask
#define UART_IM_RIMIM 0x001 // RI Interrupt Mask
//*****************************************************************************
//
// Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status
#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status
#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status
#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status
#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status
#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status
#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status
//*****************************************************************************
//
// Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status
#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status
#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status
#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status
#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status
#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status
#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status
//*****************************************************************************
//
// Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear
#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear
#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear
#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear
//*****************************************************************************
//
// DMA Control Register bits
//
//*****************************************************************************
#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error
#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA
#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA
#define UART_RSR_ANY (UART_RSR_OE | \
UART_RSR_BE | \
UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// Reset Values for UART Registers.
//
//*****************************************************************************
#define UART_RV_DR 0
#define UART_RV_RSR 0x0
#define UART_RV_ECR 0
#define UART_RV_FR 0x90
#define UART_RV_IBRD 0x0000
#define UART_RV_FBRD 0x00
#define UART_RV_LCR_H 0x00
#define UART_RV_CTL 0x0300
#define UART_RV_IFLS 0x12
#define UART_RV_IM 0x000
#define UART_RV_RIS 0x000
#define UART_RV_MIS 0x000
#define UART_RV_ICR 0x000
#endif // __HW_UART_H__

99
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h Normal file
View file

@ -0,0 +1,99 @@
//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following define the offsets of the Watchdog Timer registers.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_CAUSE 0x0000041C // Cause register
#define WDT_O_LOCK 0x00000C00 // Lock register
//*****************************************************************************
//
// The following define the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
// registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following define the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
#define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test
//*****************************************************************************
//
// The following define the bit fields in the WDT_CAUSE register.
//
//*****************************************************************************
#define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred
#define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred
//*****************************************************************************
//
// The following define the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following define the reset values for the WDT registers.
//
//*****************************************************************************
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#define WDT_RV_LOCK 0x00000000 // Lock register
#endif // __HW_WATCHDOG_H__

137
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h Normal file
View file

@ -0,0 +1,137 @@
//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_START \
(I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_CONT \
(I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
(I2C_MASTER_CS_STOP)
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
(I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
(I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
//*****************************************************************************
// Miscellaneous I2C driver definitions.
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

57
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h Normal file
View file

@ -0,0 +1,57 @@
//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void IntMasterEnable(void);
extern void IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

BIN
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a Normal file
View file

Binary file not shown.

132
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c Normal file
View file

@ -0,0 +1,132 @@
//*****************************************************************************
//
// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris
// development board.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup utilities_api
//! @{
//
//*****************************************************************************
#include "hw_memmap.h"
#include "hw_types.h"
#include "gpio.h"
#include "ssi.h"
#include "sysctl.h"
#include "pdc.h"
//*****************************************************************************
//
//! Initializes the connection to the PDC.
//!
//! This function will enable clocking to the SSI and GPIO A modules, configure
//! the GPIO pins to be used for an SSI interface, and it will configure the
//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable
//! the SSI module, and will enable the chip select for the PDC on the
//! Stellaris development board.
//!
//! This function is contained in <tt>utils/pdc.c</tt>, with
//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
//!
//! \return None.
//
//*****************************************************************************
void
PDCInit(void)
{
//
// Enable the peripherals used to drive the PDC.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
//
// Configure the appropriate pins to be SSI instead of GPIO.
//
GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,
GPIO_DIR_MODE_HW);
GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);
GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
//
// Configure the SSI port.
//
SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
SSIEnable(SSI_BASE);
//
// Reset the PDC SSI state machine. The chip select needs to be held low
// for 100ns; the procedure call overhead more than accounts for this time.
//
GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);
GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);
}
//*****************************************************************************
//
//! Write a PDC register.
//!
//! \param ucAddr specifies the PDC register to write.
//! \param ucData specifies the data to write.
//!
//! This function will perform the SSI transfers required to write a register
//! in the PDC on the Stellaris development board.
//!
//! This function is contained in <tt>utils/pdc.c</tt>, with
//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
//!
//! \return None.
//
//*****************************************************************************
void
PDCWrite(unsigned char ucAddr, unsigned char ucData)
{
unsigned long ulTemp;
//
// Send address and write command.
//
SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);
//
// Write the data.
//
SSIDataPut(SSI_BASE, ucData);
//
// Flush data read during address write.
//
SSIDataGet(SSI_BASE, &ulTemp);
//
// Flush data read during data write.
//
SSIDataGet(SSI_BASE, &ulTemp);
}

124
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h Normal file
View file

@ -0,0 +1,124 @@
//*****************************************************************************
//
// pdc.h - Stellaris development board Peripheral Device Controller definitions
// and prototypes.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __PDC_H__
#define __PDC_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The registers within the peripheral device controller.
//
//*****************************************************************************
#define PDC_VER 0x0 // Version register
#define PDC_CSR 0x1 // Command/Status register
#define PDC_DSW 0x4 // DIP Switch register
#define PDC_LED 0x5 // LED register
#define PDC_LCD_CSR 0x6 // LCD Command/Status register
#define PDC_LCD_RAM 0x7 // LCD RAM register
#define PDC_GPXDAT 0x8 // GPIO X Data register
#define PDC_GPXDIR 0x9 // GPIO X Direction register
#define PDC_GPYDAT 0xA // GPIO Y Data register
#define PDC_GPYDIR 0xB // GPIO Y Direction register
#define PDC_GPZDAT 0xC // GPIO Z Data register
#define PDC_GPZDIR 0xD // GPIO Z Direction register
//*****************************************************************************
//
// Flags indicating a read or write to the peripheral device controller.
//
//*****************************************************************************
#define PDC_RD 0x80 // PDC read command
#define PDC_WR 0x00 // PDC write command
//*****************************************************************************
//
// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0
//
//*****************************************************************************
#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM).
#define LCD_HOME 0x02 // Cursor home.
#define LCD_MODE 0x04 // Set entry mode (cursor dir)
#define LCD_ON 0x08 // Set display, cursor, blinking
// on/off
#define LCD_CUR 0x10 // Cursor, display shift
#define LCD_IF 0x20 // Set interface data length,
// lines, font
#define LCD_CGADDR 0x40 // Set CGRAM AC address
#define LCD_DDADDR 0x80 // Set DDRAM AC address
//*****************************************************************************
//
// LCD Status bit
//
//*****************************************************************************
#define LCD_B_BUSY 0x80 // Busy flag.
//*****************************************************************************
//
// The GPIO port A pin numbers for the various SSI signals.
//
//*****************************************************************************
#define SSI_CS GPIO_PIN_3
#define PDC_CS GPIO_PIN_3
#define SSI_CLK GPIO_PIN_2
#define SSI_TX GPIO_PIN_5
#define SSI_RX GPIO_PIN_4
//*****************************************************************************
//
// Function Prototypes
//
//*****************************************************************************
extern void PDCInit(void);
extern unsigned char PDCRead(unsigned char ucAddr);
extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);
extern unsigned char PDCDIPRead(void);
extern void PDCLEDWrite(unsigned char ucLED);
extern unsigned char PDCLEDRead(void);
extern void PDCLCDInit(void);
extern void PDCLCDBacklightOn(void);
extern void PDCLCDBacklightOff(void);
extern void PDCLCDClear(void);
extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);
extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);
extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);
extern unsigned char PDCGPIODirRead(unsigned char ucIdx);
extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);
extern unsigned char PDCGPIORead(unsigned char ucIdx);
extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);
#ifdef __cplusplus
}
#endif
#endif // __PDC_H__

88
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h Normal file
View file

@ -0,0 +1,88 @@
//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or less
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfig.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,
unsigned long ulMode, unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData);
extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

221
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h Normal file
View file

@ -0,0 +1,221 @@
//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1
#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc
#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc
#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4
#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlBOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

53
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h Normal file
View file

@ -0,0 +1,53 @@
//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

137
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h Normal file
View file

@ -0,0 +1,137 @@
//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000F // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000F00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerB time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

102
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h Normal file
View file

@ -0,0 +1,102 @@
//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSet as the ulConfig parameter and
// returned by UARTConfigGet in the pulConfig parameter. Additionally, the
// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity
// parameter, and are returned by UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,
unsigned long ulConfig);
extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharNonBlockingGet(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

63
FreeRTOS/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h Normal file
View file

@ -0,0 +1,63 @@
//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__