mirror of
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Add FreeRTOS-Plus directory.
This commit is contained in:
Richard Barry
parent
7bd5f21ad5
commit
f508a5f653
6798 changed files with 134949 additions and 19 deletions
588
FreeRTOS/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
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588
FreeRTOS/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
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@ -0,0 +1,588 @@
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/********************
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* Original work (C) COPYRIGHT 2006 STMicroelectronics **************************
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* Modifications (C) CopyRight 2006 Richard barry
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* File Name : 91x_enet.c
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* Author : MCD Application Team
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* Date First Issued : May 2006
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* Description : ENET library functions
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********************************************************************************
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* History:
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* May 2006: v1.0
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "FreeRTOS.h"
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#include "task.h"
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#include "91x_lib.h"
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#include "string.h" //include when using memcpy function
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/* Include of other module interface headers ---------------------------------*/
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/* Local includes ------------------------------------------------------------*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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#ifndef NULL
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#define NULL (0)
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#endif
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/* Function return values */
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#define ENET_OK (1)
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#define ENET_NOK (0)
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/* PHY interface constants. */
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#define STE100P_STATUS_REG 0x01
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#define STE100P_CONTROL_REG 0x00
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#define STE100P_LINK_ABILITY 0x05
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#define STE100P_STATUS_LINKED 0x0004
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#define STE100P_AUTO_NEGOTIATE_ABILITY 0x1000
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#define STE100P_AUTO_NEGOTIATE_COMPLETE 0x20
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#define STE100P_10HALF 0x0020
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#define STE100P_10FULL 0x0040
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#define STE100P_100HALF 0x0080
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#define STE100P_100FULL 0x0100
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#define STE100P_CTRL_FULL 0x0100
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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#define ENET_NUM_RX_BUFFERS 8
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static ENET_DMADSCRBase dmaTxDscrBase, dmaRxDscrBase[ ENET_NUM_RX_BUFFERS ];
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static u8 RxBuff[ ENET_NUM_RX_BUFFERS ][ENET_BUFFER_SIZE];
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u8 TxBuff[ENET_BUFFER_SIZE];
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/* Interface functions -------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/*******************************************************************************
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* Function Name : ENET_SetMACConfig(ENET_MACConfig * MAC_Config)
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* Description : MAC Control Register Configuration
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* Input : MAC_Config structure
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* Output : None
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* Return : None
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*******************************************************************************/
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void ENET_MACControlConfig(ENET_MACConfig *MAC_Config)
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{
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/* ReceiveALL bit */
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if (MAC_Config->ReceiveALL==ENABLE) ENET_MAC->MCR |= MAC_MCR_RA;
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else ENET_MAC->MCR &=~MAC_MCR_RA;
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/* MIIPrescaler */
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ENET_MAC->MCR &=~(0x3<<24);
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if ((MAC_Config->MIIPrescaler) == MIIPrescaler_2)
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ENET_MAC->MCR |=0x1<<24;
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/* Loopback mode */
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if (MAC_Config->LoopbackMode==ENABLE)
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{
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ENET_MAC->MCR &=~MAC_MCR_LM;
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ENET_MAC->MCR |=0x1<<21;
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ENET_MAC->MCR &=~MAC_MCR_DRO; /*enable frame reception during transmission*/
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}
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/* Address filtering mode */
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ENET_MAC->MCR &=~MAC_MCR_AFM;
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ENET_MAC->MCR |= MAC_Config->AddressFilteringMode;
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/* VLAN Filtering Mode */
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ENET_MAC->MCR |= (MAC_Config->VLANFilteringMode)<<15;
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/*Wrong Frame Pass */
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if (MAC_Config->PassWrongFrame == ENABLE) ENET_MAC->MCR |=MAC_MCR_PWF;
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else ENET_MAC->MCR &=~MAC_MCR_PWF;
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/* Late Collision Retransmission*/
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if (MAC_Config->LateCollision == ENABLE) ENET_MAC->MCR |=MAC_MCR_ELC;
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else ENET_MAC->MCR &=~MAC_MCR_ELC;
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/* Broadcast Frame Reception */
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if (MAC_Config->BroadcastFrameReception == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DBF;
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else ENET_MAC->MCR |=MAC_MCR_DBF;
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/* PacketRetry */
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if (MAC_Config->PacketRetry == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DPR;
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else ENET_MAC->MCR |=MAC_MCR_DPR;
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/* RxFrameFiltering */
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if (MAC_Config->RxFrameFiltering == ENABLE) ENET_MAC->MCR |=MAC_MCR_RVFF;
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else ENET_MAC->MCR &=~MAC_MCR_RVFF;
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/* AutomaticPadRemoval */
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if (MAC_Config->AutomaticPadRemoval == ENABLE) ENET_MAC->MCR |=MAC_MCR_APR;
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else ENET_MAC->MCR &=~MAC_MCR_APR;
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/* DefferalCheck */
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if (MAC_Config->DeferralCheck == ENABLE) ENET_MAC->MCR |=MAC_MCR_DCE;
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else ENET_MAC->MCR &=~MAC_MCR_DCE;
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}
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/*******************************************************************************
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* Function Name : ENET_SetOperatingMode
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* Description : Sets the Operating mode
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* Input : ENET_OperatingMode:(see ENET_OperatingMode in 91x_enet.h)
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* Output : None
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* Return : None
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*******************************************************************************/
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portBASE_TYPE ENET_SetOperatingMode( void )
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{
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unsigned long ulStatusReg, ulControlReg, ulLinkAbilityReg;
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/* Link status is latched, so read twice to get current value */
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ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
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ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
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if( !( ulStatusReg & STE100P_STATUS_LINKED ) )
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{
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/* No Link. */
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return pdFAIL;
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}
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ulControlReg = ENET_MIIReadReg(0, STE100P_CONTROL_REG);
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if (ulControlReg & STE100P_AUTO_NEGOTIATE_ABILITY)
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{
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/* AutoNegotiation is enabled. */
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if (!(ulStatusReg & STE100P_AUTO_NEGOTIATE_COMPLETE))
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{
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/* Auto-negotiation in progress. */
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return pdFAIL;
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}
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ulLinkAbilityReg = ENET_MIIReadReg(0, STE100P_LINK_ABILITY);
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if( ( ulLinkAbilityReg & STE100P_100FULL ) || ( ulLinkAbilityReg & STE100P_10FULL ) )
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{
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ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */
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ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */
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}
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else
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{
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ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
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ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */
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}
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}
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else
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{
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if( ulStatusReg & STE100P_CTRL_FULL )
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{
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ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */
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ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */
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}
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else
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{
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ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
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ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */
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}
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}
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return pdPASS;
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}
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/*******************************************************************************
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* Function Name : ENET_MIIWriteReg
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* Description : Writes a value on the PHY registers
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* Input : phyDev PHY device address
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: phyReg PHY register to be written
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* : phyVal PHY register value
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* Output : None
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* Return : None
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*******************************************************************************/
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void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal)
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{
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volatile u32 addr;
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volatile u32 res; /* temporary result for address register status */
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volatile u32 timeout;
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/* Prepare the MII register address */
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addr = 0;
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addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
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addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
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addr |= MAC_MII_ADDR_MII_WRITE; /* in write mode */
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addr |= MAC_MII_ADDR_MII_BUSY;
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/* Check for the Busy flag */
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timeout=0;
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do
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{
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timeout++;
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res = ENET_MAC->MIIA;
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} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));
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/* Give the value to the MII data register */
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ENET_MAC->MIID = (phyVal & 0xFFFF);
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/* write the result value into the MII Address register */
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ENET_MAC->MIIA =addr;
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/* Check for the Busy flag */
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timeout=0;
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do
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{
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timeout++;
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res = ENET_MAC->MIIA;
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} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));
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}
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/*******************************************************************************
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* Function Name : ENET_MIIReadReg
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* Description : Writes a value on the PHY
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* Input : phyDev PHY device address
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* : phyReg PHY register to be read
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* Output : None
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* Return : The read value (16 bits)
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*******************************************************************************/
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u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg )
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{
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u32 rValue;
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u32 addr;
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u32 res; /* temporary result for address register status */
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u32 timeout; /* timeout value for read process */
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/* prepare the MII register address */
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addr = 0;
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addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
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addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
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addr &= ~(MAC_MII_ADDR_MII_WRITE); /* ... in read mode */
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addr |= MAC_MII_ADDR_MII_BUSY;
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/* Check for the Busy flag */
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timeout = 0;
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do
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{
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timeout++;
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res = ENET_MAC->MIIA;
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} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));
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/* write the result value into the MII Address register */
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ENET_MAC->MIIA = addr;
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/* Check for the Busy flag */
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timeout = 0;
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do
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{
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timeout++;
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res = ENET_MAC->MIIA;
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} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));
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/* read the result value from data register*/
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rValue = ENET_MAC->MIID;
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return (rValue & 0x0000FFFF);
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}
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/*******************************************************************************
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* Function Name : ENET_RxDscrInit
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* Description : Initializes the Rx ENET descriptor chain. Single Descriptor
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void ENET_RxDscrInit(void)
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{
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int i;
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for( i = 0; i < ENET_NUM_RX_BUFFERS; i++ )
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{
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/* Assign temp Rx array to the ENET buffer */
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dmaRxDscrBase[ i ].dmaAddr = (u32)&(RxBuff[ i ][ 0 ]);
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/* Initialize RX ENET Status and control */
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dmaRxDscrBase[ i ].dmaStatCntl = 0x4000;
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/* Initialize the next descriptor- In our case its single descriptor */
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dmaRxDscrBase[ i ].dmaNext = (u32)&(dmaRxDscrBase[i+1]) | 0x01;
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/* Set the max packet size */
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dmaRxDscrBase[ i ].dmaStatCntl = ENET_MAX_PACKET_SIZE | ENET_NEXT_ENABLE;
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/* Setting the VALID bit */
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dmaRxDscrBase[ i ].dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK;
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}
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dmaRxDscrBase[ ENET_NUM_RX_BUFFERS - 1 ].dmaNext = (u32)&(dmaRxDscrBase[ 0 ]);
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/* Setting the RX NEXT Descriptor Register inside the ENET */
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ENET_DMA->RXNDAR = (u32)&(dmaRxDscrBase) | 0x01;
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}
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/*******************************************************************************
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* Function Name : ENET_TxDscrInit
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* Description : Initializes the Tx ENET descriptor chain with single descriptor
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void ENET_TxDscrInit(void)
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{
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/* ENET Start Address */
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dmaTxDscrBase.dmaAddr = (u32)TxBuff;
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/* Next Descriptor Address */
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dmaTxDscrBase.dmaNext = (u32)&(dmaTxDscrBase);
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/* Initialize ENET status and control */
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dmaTxDscrBase.dmaStatCntl = 0;
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/* Tx next set to Tx decriptor base */
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ENET_DMA->TXNDAR = (u32)&(dmaTxDscrBase);
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/* Enable next enable */
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ENET_DMA->TXNDAR |= DMA_DSCR_NXT_NPOL_EN;
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}
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/*******************************************************************************
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* Function Name : ENET_Init
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* Description : ENET MAC, PHY and DMA initializations
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void ENET_Init ()
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{
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vu32 regValue;
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ENET_MACConfig *MAC_Config;
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ENET_MACConfig config;
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/* De-assert the SRESET bit of ENET + MAC devices */
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ENET_DMA->SCR &=~DMA_SCR_SRESET;
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MAC_Config =&config;
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/* Initialize MAC control register with common values */
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MAC_Config->ReceiveALL = DISABLE;
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if (SCU_GetHCLKFreqValue() > 50000)
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MAC_Config->MIIPrescaler = MIIPrescaler_2;
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MAC_Config->LoopbackMode = DISABLE;
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MAC_Config->AddressFilteringMode = MAC_Perfect_Multicast_Perfect;
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MAC_Config->VLANFilteringMode = VLANfilter_VLTAG;
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MAC_Config->PassWrongFrame = DISABLE;
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MAC_Config->LateCollision = DISABLE;
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MAC_Config->BroadcastFrameReception = ENABLE;
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MAC_Config->PacketRetry = ENABLE;
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MAC_Config->RxFrameFiltering = ENABLE;
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MAC_Config->AutomaticPadRemoval = ENABLE;
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MAC_Config->DeferralCheck = ENABLE;
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/* Configure MAC control register */
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ENET_MACControlConfig(MAC_Config);
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/* DMA initialization */
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/* Read the ENET DMA Status and Control Register */
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regValue = ENET_DMA->SCR;
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/* Setup Tx Max burst size */
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regValue &= ~(u32)DMA_SCR_TX_MAX_BURST_SZ;
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regValue |= (u32)DMA_SCR_TX_MAX_BURST_SZ_VAL;
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/* Setup Rx Max Burst size */
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regValue &= ~(u32)DMA_SCR_RX_MAX_BURST_SZ;
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regValue |= (u32)DMA_SCR_RX_MAX_BURST_SZ_VAL;
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/* Write Tx & Rx burst size to the ENET status and control register */
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ENET_DMA->SCR = regValue;
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/* Put the PHY in reset mode */
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ENET_MIIWriteReg(0x0,MAC_MII_REG_XCR, 0x8000);
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/* Delay to assure PHY reset */
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vTaskDelay( 3000 / portTICK_RATE_MS );
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/* initialize the opearting mode */
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while( ENET_SetOperatingMode() == pdFAIL )
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{
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vTaskDelay( 3000 / portTICK_RATE_MS );
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}
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/*set MAC physical*/
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//ENET_MAC->MAH = (MAC_ADDR5<<8) + MAC_ADDR4;
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//ENET_MAC->MAL = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + (MAC_ADDR1<<8) + MAC_ADDR0;
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/* Initialize Rx and Tx descriptors in memory */
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ENET_TxDscrInit();
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ENET_RxDscrInit();
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// What's happening ???
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#ifdef DEBUG
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//int pippo = 1; // Do NOT remove!!!
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#endif
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}
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/********************************************************************************
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* Function Name : ENET_HandleRxPkt
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* Description : receive a packet and copy it to memory pointed by ppkt.
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* Input : ppkt: pointer on application receive buffer.
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* Output : None
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* Return : ENET_NOK - If there is no packet
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* : ENET_OK - If there is a packet
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*******************************************************************************/
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u32 ENET_HandleRxPkt ( void *ppkt)
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{
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ENET_DMADSCRBase *pDescr;
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u16 size;
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static int iNextRx = 0;
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if( dmaRxDscrBase[ iNextRx ].dmaPackStatus & DMA_DSCR_RX_STATUS_VALID_MSK )
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{
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return 0;
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}
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pDescr = &dmaRxDscrBase[ iNextRx ];
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/*Get the size of the packet*/
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size = ((pDescr->dmaPackStatus & 0x7ff) - 4);
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//MEMCOPY_L2S_BY4((u8*)ppkt, RxBuff, size); /*optimized memcopy function*/
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memcpy(ppkt, RxBuff[iNextRx], size); //string.h library*/
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/* Give the buffer back to ENET */
|
||||
pDescr->dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK;
|
||||
|
||||
iNextRx++;
|
||||
|
||||
if( iNextRx >= ENET_NUM_RX_BUFFERS )
|
||||
{
|
||||
iNextRx = 0;
|
||||
}
|
||||
|
||||
/* Return no error */
|
||||
return size;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_TxPkt
|
||||
* Description : Transmit a packet
|
||||
* Input : ppkt: pointer to application packet Buffer
|
||||
* : size: Tx Packet size
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
u8 *pcGetNextBuffer( void )
|
||||
{
|
||||
if( dmaTxDscrBase.dmaPackStatus & DMA_DSCR_TX_STATUS_VALID_MSK )
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ( unsigned char * ) TxBuff;
|
||||
}
|
||||
}
|
||||
|
||||
void ENET_TxPkt(void *ppkt, u16 size)
|
||||
{
|
||||
/* Setting the Frame Length*/
|
||||
dmaTxDscrBase.dmaStatCntl = (size&0xFFF);
|
||||
|
||||
/* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
|
||||
dmaTxDscrBase.dmaPackStatus = DMA_DSCR_TX_STATUS_VALID_MSK;
|
||||
|
||||
/* Start the transmit operation */
|
||||
ENET_DMA->TXSTR|= DMA_TX_START_FETCH;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_Start
|
||||
* Description : Enables ENET MAC reception / transmission & starts DMA fetch
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
|
||||
void ENET_Start ( void)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
/* Force a ENET abort by software for the receive block */
|
||||
ENET_DMA->RXSTR &=~ DMA_RX_START_DMA_EN;
|
||||
|
||||
/* Force a ENET abort by software for the transmit block */
|
||||
ENET_DMA->TXSTR &=~DMA_TX_START_DMA_EN;
|
||||
|
||||
/* Reset all interrupts */
|
||||
ENET_DMA->ISR = 0xFFFFFFFF;
|
||||
|
||||
/* Setup Descriptor Fetch ENET_PhyDelay for Receive Block */
|
||||
value = ENET_DMA->RXSTR;
|
||||
value &= ~( DMA_RX_START_DFETCH_DLY );
|
||||
value |= DMA_RX_START_DFETCH_DEFAULT;
|
||||
ENET_DMA->RXSTR= value;
|
||||
|
||||
/* Setup Descriptor Fetch ENET_PhyDelay for Transmit Block */
|
||||
value = ENET_DMA->TXSTR;
|
||||
value &= ~( DMA_TX_START_DFETCH_DLY );
|
||||
value |= DMA_TX_START_DFETCH_DEFAULT;
|
||||
ENET_DMA->TXSTR= value;
|
||||
|
||||
/* Set Tx underrun bit */
|
||||
value &= ~( DMA_TX_START_URUN );
|
||||
value |= DMA_TX_START_URUN;
|
||||
ENET_DMA->TXSTR = value;
|
||||
|
||||
/* Clear the interrupts */
|
||||
ENET_DMA->IER = 0x0;
|
||||
|
||||
/* MAC TX enable */
|
||||
ENET_MAC->MCR|= MAC_MCR_TE;
|
||||
|
||||
/* MAC RX enable */
|
||||
ENET_MAC->MCR|= MAC_MCR_RE;
|
||||
|
||||
/* Start the DMA Fetch */
|
||||
ENET_DMA->RXSTR|= DMA_RX_START_FETCH;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : ENET_InitClocksGPIO
|
||||
* Description : Reset, clocks & GPIO Ethernet Pin initializations
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void ENET_InitClocksGPIO(void)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_Struct;
|
||||
|
||||
SCU_AHBPeriphClockConfig(__ENET, ENABLE);
|
||||
SCU_AHBPeriphReset(__ENET,DISABLE);
|
||||
SCU_PHYCLKConfig(ENABLE);
|
||||
|
||||
GPIO_DeInit(GPIO1);
|
||||
GPIO_Struct.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |GPIO_Pin_3 |GPIO_Pin_4 |GPIO_Pin_7 ;
|
||||
GPIO_Struct.GPIO_Type = GPIO_Type_PushPull;
|
||||
GPIO_Struct.GPIO_Direction = GPIO_PinOutput;
|
||||
GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable;
|
||||
GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2;
|
||||
GPIO_Init(GPIO1, &GPIO_Struct);
|
||||
|
||||
|
||||
GPIO_DeInit(GPIO5);
|
||||
GPIO_Struct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
|
||||
GPIO_Struct.GPIO_Type = GPIO_Type_PushPull;
|
||||
GPIO_Struct.GPIO_Direction = GPIO_PinOutput;
|
||||
GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable;
|
||||
GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2;
|
||||
GPIO_Init(GPIO5, &GPIO_Struct);
|
||||
|
||||
}
|
||||
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/
|
||||
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue