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Add FreeRTOS-Plus directory.

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Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
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131
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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM9XE_FLASH.mac
// User setup file for CSPY debugger.
// 1.1 08/Aug/06 jpp : Creation
//
// $Revision: 23594 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
__writeMemory32(0x00000500, 0xFFFFFA00, "Memory"); // Set flash wait states
__PllSetting(); //* Init PLL
__PllSetting100MHz();
__message "-------------------------------Set PC Reset ----------------------------------";
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__writeMemory32(0x00000500, 0xFFFFFA00, "Memory"); // Set flash wait states
__PllSetting(); //* Init PLL
__PllSetting100MHz();
_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
}
/*********************************************************************
*
* _InitRSTC()
*
* Function description
* Initializes the RSTC (Reset controller).
* This makes sense since the default is to not allow user resets, which makes it impossible to
* apply a second RESET via J-Link
*/
_InitRSTC() {
__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
}
/*********************************************************************
*
* __PllSetting()
* Function description
* Initializes the PMC.
* 1. Enable the Main Oscillator
* 2. Configure PLL
* 3. Switch Master
*/
__PllSetting()
{
if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
//* Disable all PMC interrupt ( $$ JPP)
//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
//* pPmc->PMC_IDR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
// Disable all clock only Processor clock is enabled.
__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
__sleep(10000);
__message "------------------------------- PLL Enable -----------------------------------------";
} else {
__message " ********* Core in SLOW CLOCK mode ********* "; }
}
/*********************************************************************
*
* __PllSetting100MHz()
* Function description
* Set core at 200 MHz and MCK at 100 MHz
*/
__PllSetting100MHz()
{
__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
__sleep(10000);
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
__sleep(10000);
//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
__sleep(10000);
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM9XE_SDRAM.mac
// User setup file for CSPY debugger.
// 1.1 08/Aug/06 jpp : Creation
//
// $Revision: 23594 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
_MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000
__PllSetting(); //* Init PLL
__PllSetting100MHz();
__message "-------------------------------Set PC Reset ----------------------------------";
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__PllSetting(); //* Init PLL
__PllSetting100MHz();
__initSDRAM(); //* Init SDRAM before load
_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
}
/*********************************************************************
*
* _InitRSTC()
*
* Function description
* Initializes the RSTC (Reset controller).
* This makes sense since the default is to not allow user resets, which makes it impossible to
* apply a second RESET via J-Link
*/
_InitRSTC() {
__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
}
/*********************************************************************
*
* __initSDRAM()
* Function description
* Set SDRAM for works at 100 MHz
*/
__initSDRAM()
{
//* Configure EBI Chip select
// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
__writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
//* Configure PIOs
//* AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
__writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
__writeMemory32(0x00000000,0xFFFFF874,"Memory");
__writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
//* psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 |
// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
__writeMemory32(0x85227279,0xFFFFEA08,"Memory");
__sleep(100);
//* psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
__writeMemory32(0x00000002,0xFFFFEA00,"Memory");
//* *AT91C_SDRAM = 0x00000000; // Perform PRCHG
__writeMemory32(0x00000000,0x20000000,"Memory");
__sleep(100);
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
__writeMemory32(0x00000001,0x20000010,"Memory");
//* psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
__writeMemory32(0x00000002,0x20000020,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
__writeMemory32(0x00000003,0x20000030,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
__writeMemory32(0x00000004,0x20000040,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
__writeMemory32(0x00000005,0x20000050,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
__writeMemory32(0x00000006,0x20000060,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
__writeMemory32(0x00000007,0x20000070,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
__writeMemory32(0x00000008,0x20000080,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
__writeMemory32(0x00000003,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
__writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
//* psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
// // (F : system clock freq. MHz
__writeMemory32(0x000002B9,0xFFFFEA04,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
__writeMemory32(0x00000000,0xFFFFEA00,"Memory");
//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
__writeMemory32(0x00000000,0x20000000,"Memory");
__message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
}
/*********************************************************************
*
* _MapRAMAt0()
* Function description
* Remap RAM at 0
*/
_MapRAMAt0()
{
// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
__message "------------------------------- The Remap is NOT & REMAP ----------------------------";
__writeMemory32(0x00000003,0xFFFFEF00,"Memory");
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
} else {
__message "------------------------------- The Remap is done -----------------------------------";
}
}
/*********************************************************************
*
* __PllSetting()
* Function description
* Initializes the PMC.
* 1. Enable the Main Oscillator
* 2. Configure PLL
* 3. Switch Master
*/
__PllSetting()
{
if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
//* Disable all PMC interrupt ( $$ JPP)
//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
//* pPmc->PMC_IDR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
// Disable all clock only Processor clock is enabled.
__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
__sleep(10000);
__message "------------------------------- PLL Enable -----------------------------------------";
} else {
__message " ********* Core in SLOW CLOCK mode ********* "; }
}
/*********************************************************************
*
* __PllSetting100MHz()
* Function description
* Set core at 200 MHz and MCK at 100 MHz
*/
__PllSetting100MHz()
{
__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
__sleep(10000);
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
__sleep(10000);
//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
__sleep(10000);
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM9XE_SRAM.mac
// User setup file for CSPY debugger.
// 1.1 08/Aug/06 jpp : Creation
//
// $Revision: 23594 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
_MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000
__PllSetting(); //* Init PLL
__PllSetting100MHz();
__message "-------------------------------Set PC Reset ----------------------------------";
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__PllSetting(); //* Init PLL
__PllSetting100MHz();
_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
}
/*********************************************************************
*
* _InitRSTC()
*
* Function description
* Initializes the RSTC (Reset controller).
* This makes sense since the default is to not allow user resets, which makes it impossible to
* apply a second RESET via J-Link
*/
_InitRSTC() {
__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
}
/*********************************************************************
*
* _MapRAMAt0()
* Function description
* Remap RAM at 0
*/
_MapRAMAt0()
{
// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
__message "------------------------------- The Remap is NOT & REMAP ----------------------------";
__writeMemory32(0x00000003,0xFFFFEF00,"Memory");
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
} else {
__message "------------------------------- The Remap is done -----------------------------------";
}
}
/*********************************************************************
*
* __PllSetting()
* Function description
* Initializes the PMC.
* 1. Enable the Main Oscillator
* 2. Configure PLL
* 3. Switch Master
*/
__PllSetting()
{
if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
//* Disable all PMC interrupt ( $$ JPP)
//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
//* pPmc->PMC_IDR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
// Disable all clock only Processor clock is enabled.
__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
__sleep(10000);
__message "------------------------------- PLL Enable -----------------------------------------";
} else {
__message " ********* Core in SLOW CLOCK mode ********* "; }
}
/*********************************************************************
*
* __PllSetting100MHz()
* Function description
* Set core at 200 MHz and MCK at 100 MHz
*/
__PllSetting100MHz()
{
__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
__sleep(10000);
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
__sleep(10000);
//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
__sleep(10000);
}

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x200000;
define symbol __ICFEDIT_region_ROM_end__ = 0x27FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_startup__ = 0x100;
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_svcstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x10000;
/*-Exports-*/
export symbol __ICFEDIT_region_ROM_start__;
export symbol __ICFEDIT_region_ROM_end__;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_startup__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_svcstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
initialize by copy { section .vectors };
do not initialize { section .noinit };
place in STA_region { section .cstartup };
place in ROM_region { readonly };
place in VEC_region { section .vectors };
place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_startup__ = 0x100;
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_svcstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x10000;
/*-Exports-*/
export symbol __ICFEDIT_region_SDRAM_start__;
export symbol __ICFEDIT_region_SDRAM_end__;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_startup__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_svcstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { section .vectors };
do not initialize { section .noinit };
place in STA_region { section .cstartup };
place in VEC_region { section .vectors };
place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };

32
FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.cspy.bat Normal file
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@REM This bat file has been generated by the IAR Embeddded Workbench
@REM C-SPY interactive debugger,as an aid to preparing a command
@REM line for running the cspybat command line utility with the
@REM appropriate settings.
@REM
@REM After making some adjustments to this file, you can launch cspybat
@REM by typing the name of this file followed by the name of the debug
@REM file (usually an ubrof file). Note that this file is generated
@REM every time a new debug session is initialized, so you may want to
@REM move or rename the file before making changes.
@REM
@REM Note: some command line arguments cannot be properly generated
@REM by this process. Specifically, the plugin which is responsible
@REM for the Terminal I/O window (and other C runtime functionality)
@REM comes in a special version for cspybat, and the name of that
@REM plugin dll is not known when generating this file. It resides in
@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or
@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding
@REM tool chain. Replace the '<libsupport_plugin>' parameter
@REM below with the appropriate file name. Other plugins loaded by
@REM C-SPY are usually not needed by, or will not work in, cspybat
@REM but they are listed at the end of this file for reference.
"C:\devtools\IAR Systems\Embedded Workbench 5.4\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\<libsupport_plugin>" --macro "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\ARM9_AT91SAM9XE_IAR\ewp\at91sam9xe-ek-sdram.mac" --backend -B "--endian=little" "--cpu=ARM926EJ-S" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\CONFIG\debugger\Atmel\ioAT91SAM9XE512.ddf" "--drv_verify_download" "--semihosting=none" "--device=AT91SAM9XE512" "-d" "jlink" "--drv_communication=USB0" "--jlink_speed=adaptive" "--drv_catch_exceptions=0x000"
@REM Loaded plugins:
@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armlibsupport.dll
@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\CodeCoverage\CodeCoverage.dll
@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\stack\stack.dll
@REM C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\SymList\SymList.dll

75
FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dbgdt Normal file
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<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1342</ColumnWidth1></Debug-Log>
<Build>
<ColumnWidth0>20</ColumnWidth0>
<ColumnWidth1>1216</ColumnWidth1>
<ColumnWidth2>324</ColumnWidth2>
<ColumnWidth3>81</ColumnWidth3>
</Build>
<Workspace>
<ColumnWidths>
<Column0>363</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow><InstrProfShow>0</InstrProfShow></Disassembly>
</Static>
<Windows>
<Wnd0>
<Tabs>
<Tab>
<Identity>TabID-27883-8575</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-24747-8634</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
<Tab><Identity>TabID-14901-7385</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory></Tab></Tabs>
<SelectedTab>0</SelectedTab></Wnd0><Wnd2>
<Tabs>
<Tab>
<Identity>TabID-5864-8578</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>at91sam9xe-ek</ExpandedNode><ExpandedNode>at91sam9xe-ek/scheduler_source</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\temp\V5.1.2\FreeRTOS\Demo\ARM9_AT91SAM9XE_IAR\main.c</Filename><XPos>0</XPos><YPos>97</YPos><SelStart>4730</SelStart><SelEnd>4730</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\temp\V5.1.2\FreeRTOS\Source\portable\IAR\AtmelSAM9XE\port.c</Filename><XPos>0</XPos><YPos>150</YPos><SelStart>6569</SelStart><SelEnd>6569</SelEnd></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-00abba18><key>iaridepm.enu1</key></Toolbar-00abba18><Toolbar-032d2d00><key>debuggergui.enu1</key></Toolbar-032d2d00></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>437</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>261310</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd0></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

41
FreeRTOS/Demo/ARM9_AT91SAM9XE_IAR/ewp/settings/at91sam9xe-ek.dni Normal file
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[JLinkDriver]
WatchCond=_ 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
[DisAssemblyWindow]
NumStates=_ 1
State 1=_ 1
[CodeCoverage]
Enabled=_ 0
[StackPlugin]
Enabled=1
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnHow=0
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[DebugChecksum]
Checksum=-425662186
[InstructionProfiling]
Enabled=_ 0
[TraceHelper]
Enabled=0
ShowSource=1
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[DriverProfiling]
Enabled=0
Source=2
Graph=0
[Disassemble mode]
mode=0
[Breakpoints]
Count=0