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Add FreeRTOS-Plus directory.
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Richard Barry
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6798 changed files with 134949 additions and 19 deletions
249
FreeRTOS/Demo/ARM7_STR75x_IAR/75x_init.s
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249
FreeRTOS/Demo/ARM7_STR75x_IAR/75x_init.s
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;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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;* File Name : 75x_init.s
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;* Author : MCD Application Team
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;* Date First Issued : 03/10/2006
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;* Description : This module performs:
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;* - Memory remapping (if required),
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;* - Stack pointer initialisation for each mode ,
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;* - Interrupt Controller Initialisation
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;* - Branches to ?main in the C library (which eventually
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;* calls main()).
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;* On reset, the ARM core starts up in Supervisor (SVC) mode,
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;* in ARM state,with IRQ and FIQ disabled.
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;*******************************************************************************
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; History:
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; 07/17/2006 : V1.0
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; 03/10/2006 : V0.1
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;*******************************************************************************
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; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;*******************************************************************************
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IMPORT WAKUP_Addr ; imported from 75x_vect.s
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; Depending on Your Application, Disable or Enable the following Defines
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; ----------------------------------------------------------------------------
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; SMI Bank0 configuration
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; ----------------------------------------------------------------------------
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; If you need to accees the SMI Bank0
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; uncomment next line
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;#define SMI_Bank0_EN
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; ----------------------------------------------------------------------------
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; Memory remapping
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; ----------------------------------------------------------------------------
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;#define Remap_SRAM ; remap SRAM at address 0x00
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; ----------------------------------------------------------------------------
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; EIC initialization
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; ----------------------------------------------------------------------------
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#define EIC_INIT ; Configure and Initialize EIC
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; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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; MRCC Register
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MRCC_PCLKEN_Addr EQU 0x60000030 ; Peripheral Clock Enable register base address
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; CFG Register
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CFG_GLCONF_Addr EQU 0x60000010 ; Global Configuration register base address
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SRAM_mask EQU 0x0002 ; to remap RAM at 0x0
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; GPIO Register
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GPIOREMAP0R_Addr EQU 0xFFFFE420
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SMI_EN_Mask EQU 0x00000001
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; SMI Register
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SMI_CR1_Addr EQU 0x90000000
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; EIC Registers offsets
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EIC_Base_addr EQU 0xFFFFF800 ; EIC base address
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ICR_off_addr EQU 0x00 ; Interrupt Control register offset
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CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset
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IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset
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FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset
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IER_off_addr EQU 0x20 ; Interrupt Enable Register offset
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IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset
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SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0
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;---------------------------------------------------------------
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; ?program_start
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;---------------------------------------------------------------
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MODULE ?program_start
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .text:CODE(2)
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PUBLIC __iar_program_start
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EXTERN ?main
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CODE32
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__iar_program_start:
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LDR pc, =NextInst
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NextInst
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; Reset all Peripheral Clocks
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; This is usefull only when using debugger to Reset\Run the application
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#ifdef SMI_Bank0_EN
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LDR r0, =0x01000000 ; Disable peripherals clock (except GPIO)
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#else
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LDR r0, =0x00000000 ; Disable peripherals clock
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#endif
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LDR r1, =MRCC_PCLKEN_Addr
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STR r0, [r1]
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#ifdef SMI_Bank0_EN
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LDR r0, =0x1875623F ; Peripherals kept under reset (except GPIO)
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#else
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LDR r0, =0x1975623F ; Peripherals kept under reset
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#endif
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STR r0, [r1,#4]
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MOV r0, #0
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NOP ; Wait
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NOP
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NOP
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NOP
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STR r0, [r1,#4] ; Disable peripherals reset
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; Initialize stack pointer registers
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; Enter each mode in turn and set up the stack pointer
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MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
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ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
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MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
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ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
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MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
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ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
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MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
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ldr sp,=SFE(UND_STACK) ; End of UND_STACK
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MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
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ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
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; ------------------------------------------------------------------------------
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; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register,
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; enable SMI alternate function in GPIO_REMAP register and enable
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; Bank0 in SMI_CR1 register.
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; ------------------------------------------------------------------------------
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#ifdef SMI_Bank0_EN
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MOV r0, #0x01000000
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LDR r1, =MRCC_PCLKEN_Addr
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STR r0, [r1] ; Enable GPIOs clock
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LDR r1, =GPIOREMAP0R_Addr
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MOV r0, #SMI_EN_Mask
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LDR r2, [r1]
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ORR r2, r2, r0
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STR r2, [r1] ; Enable SMI alternate function
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LDR r0, =0x251 ; SMI Bank0 enabled, Prescaler = 2, Deselect Time = 5
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LDR r1, =SMI_CR1_Addr
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STR r0, [r1] ; Configure CR1 register
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LDR r0, =0x00
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STR r0, [r1,#4] ; Reset CR2 register
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#endif
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; ------------------------------------------------------------------------------
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; Description : Remapping SRAM at address 0x00 after the application has
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; started executing.
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; ------------------------------------------------------------------------------
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#ifdef Remap_SRAM
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MOV r0, #SRAM_mask
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LDR r1, =CFG_GLCONF_Addr
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LDR r2, [r1] ; Read GLCONF Register
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BIC r2, r2, #0x03 ; Reset the SW_BOOT bits
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ORR r2, r2, r0 ; Change the SW_BOOT bits
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STR r2, [r1] ; Write GLCONF Register
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#endif
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;-------------------------------------------------------------------------------
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;Description : Initialize the EIC as following :
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; - IRQ disabled
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; - FIQ disabled
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; - IVR contains the load PC opcode
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; - All channels are disabled
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; - All channels priority equal to 0
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; - All SIR registers contains offset to the related IRQ table entry
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;-------------------------------------------------------------------------------
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#ifdef EIC_INIT
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LDR r3, =EIC_Base_addr
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LDR r4, =0x00000000
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STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ
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STR r4, [r3, #IER_off_addr] ; Disable all interrupts channels
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LDR r4, =0xFFFFFFFF
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STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits
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LDR r4, =0x18
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STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits
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LDR r4, =0x00000000
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STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register
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LDR r4, =0xE59F0000 ; Write the LDR pc,pc,#offset..
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STR r4, [r3, #IVR_off_addr] ; ..instruction code in IVR[31:16]
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LDR r2,= 32 ; 32 Channel to initialize
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LDR r0, =WAKUP_Addr ; Read the address of the IRQs address table
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LDR r1, =0x00000FFF
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AND r0,r0,r1
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LDR r5,=SIR0_off_addr ; Read SIR0 address
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SUB r4,r0,#8 ; subtract 8 for prefetch
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LDR r1, =0xF7E8 ; add the offset to the 0x00 address..
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; ..(IVR address + 7E8 = 0x00)
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; 0xF7E8 used to complete the LDR pc,offset opcode
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ADD r1,r4,r1 ; compute the jump offset
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EIC_INI
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MOV r4, r1, LSL #16 ; Left shift the result
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STR r4, [r3, r5] ; Store the result in SIRx register
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ADD r1, r1, #4 ; Next IRQ address
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ADD r5, r5, #4 ; Next SIR
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SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize
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BNE EIC_INI ; If more then continue
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#endif
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; --- Branch to C Library entry point
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IMPORT ?main
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B ?main ; use B not BL, because an application will never return this way
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LTORG
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END
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;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE*****
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