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Add FreeRTOS-Plus directory.
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189
FreeRTOS/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s
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189
FreeRTOS/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Part one of the system initialization code,
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;; contains low-level
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;; initialization.
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;;
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;; Copyright 2006 IAR Systems. All rights reserved.
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;;
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;; $Revision: 10608 $
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;;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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;
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; The module in this file are included in the libraries, and may be
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; replaced by any user-defined modules that define the PUBLIC symbol
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; __iar_program_start or a user defined start symbol.
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;
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; To override the cstartup defined in the library, simply add your
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; modified version to the workbench project.
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SECTION .intvec:CODE:NOROOT(2)
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PUBLIC __vector
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PUBLIC __vector_0x14
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PUBLIC __iar_program_start
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EXTERN vPortYieldProcessor
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ARM
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__vector:
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;;
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ldr pc,[pc,#+24] ;; Reset
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ldr pc,[pc,#+24] ;; Undefined instructions
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;; ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
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b vPortYieldProcessor
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ldr pc,[pc,#+24] ;; Prefetch abort
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ldr pc,[pc,#+24] ;; Data abort
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__vector_0x14
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DC32 0 ;; RESERVED
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ldr pc, [PC, #-0xFF0] ;; IRQ
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ldr pc,[pc,#+24] ;; FIQ
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DC32 __iar_program_start ;; Reset
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DC32 undef_handler ;; Undefined instructions
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DC32 0 ;; Software interrupt (SWI/SVC)
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DC32 prefetch_handler ;; Prefetch abort
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DC32 data_handler ;; Data abort
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DC32 0 ;; RESERVED
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DC32 0 ;; IRQ
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DC32 fiq_handler ;; FIQ
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undef_handler
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b undef_handler
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prefetch_handler
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b prefetch_handler
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data_handler
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b data_handler
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fiq_handler
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b fiq_handler
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; --------------------------------------------------
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; ?cstartup -- low-level system initialization code.
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;
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; After a reser execution starts here, the mode is ARM, supervisor
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; with interrupts disabled.
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;
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SECTION .text:CODE:NOROOT(2)
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; PUBLIC ?cstartup
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EXTERN ?main
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REQUIRE __vector
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ARM
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__iar_program_start:
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?cstartup:
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;
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; Add initialization needed before setup of stackpointers here.
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;
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; Errata MAM.1Incorrect read of data from SRAM after Reset and MAM
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; is not enabled or partially enabled.
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; Work-around: User code should enable the MAM after Reset and before
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; any RAM accesses
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MAMCR DEFINE 0xE01FC000 ; MAM Control Register
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MAMTIM DEFINE 0xE01FC004 ; MAM Timing register
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ldr r0,=MAMCR
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ldr r1,=MAMTIM
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ldr r2,=0
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str r2,[r0]
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ldr r2,=3 ; 1 < 20 MHz; 20 MHz < 2 < 40 MHz; 40MHz > 3
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str r2,[r1]
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ldr r2,=2
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str r2,[r0]
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; Initialize the stack pointers.
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; The pattern below can be used for any of the exception stacks:
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; FIQ, IRQ, SVC, ABT, UND, SYS.
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; The USR mode uses the same stack as SYS.
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; The stack segments must be defined in the linker command file,
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; and be declared above.
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;
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; --------------------
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; Mode, correspords to bits 0-5 in CPSR
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MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
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USR_MODE DEFINE 0x10 ; User mode
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FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
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IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
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SVC_MODE DEFINE 0x13 ; Supervisor mode
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ABT_MODE DEFINE 0x17 ; Abort mode
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UND_MODE DEFINE 0x1B ; Undefined Instruction mode
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SYS_MODE DEFINE 0x1F ; System mode
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MRS r0, cpsr ; Original PSR value
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BIC r0, r0, #MODE_BITS ; Clear the mode bits
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ORR r0, r0, #ABT_MODE ; Set ABT mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
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BIC r0, r0, #MODE_BITS ; Clear the mode bits
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ORR r0, r0, #SVC_MODE ; Set SVC mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
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BIC r0, r0, #MODE_BITS ; Clear the mode bits
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ORR r0, r0, #UND_MODE ; Set UND mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(UND_STACK) ; End of UND_STACK
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BIC r0, r0, #MODE_BITS ; Clear the mode bits
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ORR r0, r0, #FIQ_MODE ; Set FIQ mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
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BIC r0, r0, #MODE_BITS ; Clear the mode bits
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ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
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BIC r0 ,r0, #MODE_BITS ; Clear the mode bits
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ORR r0 ,r0, #SYS_MODE ; Set System mode bits
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MSR cpsr_c, r0 ; Change the mode
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LDR sp, =SFE(CSTACK) ; End of CSTACK
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#ifdef __ARMVFP__
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;; Enable the VFP coprocessor.
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MOV r0, #0x40000000 ; Set EN bit in VFP
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FMXR fpexc, r0 ; FPEXC, clear others.
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;
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; Disable underflow exceptions by setting flush to zero mode.
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; For full IEEE 754 underflow compliance this code should be removed
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; and the appropriate exception handler installed.
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;
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MOV r0, #0x01000000 ; Set FZ bit in VFP
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FMXR fpscr, r0 ; FPSCR, clear others.
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#endif
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;
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; Add more initialization here
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;
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BIC r0, r0, #MODE_BITS ; Clear the mode bits
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ORR r0, r0, #SVC_MODE ; Set SVC mode bits
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MSR cpsr_c, r0 ; Change the mode
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; Continue to ?main for C-level initialization.
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LDR r0, =?main
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BX r0
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END
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