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Add FreeRTOS-Plus directory.
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Richard Barry
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6798 changed files with 134949 additions and 19 deletions
302
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s
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302
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s
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;* ----------------------------------------------------------------------------
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;* ATMEL Microcontroller Software Support - ROUSSET -
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;* ----------------------------------------------------------------------------
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;* Copyright (c) 2006, Atmel Corporation
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;
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without
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;* modification, are permitted provided that the following conditions are met:
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;*
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;* - Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the disclaimer below.
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;*
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;* - Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the disclaimer below in the documentation and/or
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;* other materials provided with the distribution.
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;*
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;* Atmel's name may not be used to endorse or promote products derived from
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;* this software without specific prior written permission.
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;*
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;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;* ----------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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; Include your AT91 Library files
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;------------------------------------------------------------------------------
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#include "AT91SAM7X256_inc.h"
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;------------------------------------------------------------------------------
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#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE)
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#define IRQ_STACK_SIZE 200
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; 3 words to be saved per interrupt priority level
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; Mode, correspords to bits 0-5 in CPSR
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MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
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USR_MODE DEFINE 0x10 ; User mode
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FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
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IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
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SVC_MODE DEFINE 0x13 ; Supervisor mode
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ABT_MODE DEFINE 0x17 ; Abort mode
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UND_MODE DEFINE 0x1B ; Undefined Instruction mode
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SYS_MODE DEFINE 0x1F ; System mode
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I_BIT DEFINE 0x80
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F_BIT DEFINE 0x40
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;------------------------------------------------------------------------------
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; ?RESET
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; Reset Vector.
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; Normally, segment INTVEC is linked at address 0.
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; For debugging purposes, INTVEC may be placed at other addresses.
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; A debugger that honors the entry point will start the
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; program in a normal way even if INTVEC is not at address 0.
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;------------------------------------------------------------------------------
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SECTION .intvec:CODE:NOROOT(2)
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PUBLIC __vector
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PUBLIC __iar_program_start
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EXTERN vPortYieldProcessor
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ARM
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__vector:
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ldr pc,[pc,#+24] ;; Reset
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__und_handler:
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ldr pc,[pc,#+24] ;; Undefined instructions
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__swi_handler:
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ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
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__prefetch_handler:
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ldr pc,[pc,#+24] ;; Prefetch abort
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__data_handler:
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ldr pc,[pc,#+24] ;; Data abort
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DC32 0xFFFFFFFF ;; RESERVED
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__irq_handler:
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LDR PC, [PC, #-0xF20]
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__fiq_handler:
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ldr pc,[pc,#+24] ;; FIQ
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DC32 __iar_program_start
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DC32 __und_handler
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DC32 vPortYieldProcessor
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DC32 __prefetch_handler
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DC32 __data_handler
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B .
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DC32 IRQ_Handler_Entry
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DC32 FIQ_Handler_Entry
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;------------------------------------------------------------------------------
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;- Manage exception: The exception must be ensure in ARM mode
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;------------------------------------------------------------------------------
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SECTION text:CODE:NOROOT(2)
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ARM
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;------------------------------------------------------------------------------
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;- Function : FIQ_Handler_Entry
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;- Treatments : FIQ Controller Interrupt Handler.
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;- R8 is initialize in Cstartup
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;- Called Functions : None only by FIQ
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;------------------------------------------------------------------------------
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FIQ_Handler_Entry:
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;- Switch in SVC/User Mode to allow User Stack access for C code
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; because the FIQ is not yet acknowledged
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;- Save and r0 in FIQ_Register
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mov r9,r0
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ldr r0 , [r8, #AIC_FVR]
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msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
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;- Save scratch/used registers and LR in User Stack
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stmfd sp!, { r1-r3, r12, lr}
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;- Branch to the routine pointed by the AIC_FVR
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mov r14, pc
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bx r0
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;- Restore scratch/used registers and LR from User Stack
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ldmia sp!, { r1-r3, r12, lr}
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;- Leave Interrupts disabled and switch back in FIQ mode
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msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE
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;- Restore the R0 ARM_MODE_SVC register
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mov r0,r9
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;- Restore the Program Counter using the LR_fiq directly in the PC
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subs pc,lr,#4
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;------------------------------------------------------------------------------
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;- Function : IRQ_Handler_Entry
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;- Treatments : IRQ Controller Interrupt Handler.
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;- Called Functions : AIC_IVR[interrupt]
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;------------------------------------------------------------------------------
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IRQ_Handler_Entry:
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;-------------------------
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;- Manage Exception Entry
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;-------------------------
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;- Adjust and save LR_irq in IRQ stack
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sub lr, lr, #4
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stmfd sp!, {lr}
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;- Save r0 and SPSR (need to be saved for nested interrupt)
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mrs r14, SPSR
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stmfd sp!, {r0,r14}
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;- Write in the IVR to support Protect Mode
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;- No effect in Normal Mode
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;- De-assert the NIRQ and clear the source in Protect Mode
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ldr r14, =AT91C_BASE_AIC
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ldr r0 , [r14, #AIC_IVR]
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str r14, [r14, #AIC_IVR]
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;- Enable Interrupt and Switch in Supervisor Mode
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msr CPSR_c, #SVC_MODE
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;- Save scratch/used registers and LR in User Stack
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stmfd sp!, { r1-r3, r12, r14}
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;----------------------------------------------
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;- Branch to the routine pointed by the AIC_IVR
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;----------------------------------------------
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mov r14, pc
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bx r0
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;----------------------------------------------
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;- Manage Exception Exit
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;----------------------------------------------
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;- Restore scratch/used registers and LR from User Stack
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ldmia sp!, { r1-r3, r12, r14}
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;- Disable Interrupt and switch back in IRQ mode
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msr CPSR_c, #I_BIT | IRQ_MODE
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;- Mark the End of Interrupt on the AIC
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ldr r14, =AT91C_BASE_AIC
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str r14, [r14, #AIC_EOICR]
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;- Restore SPSR_irq and r0 from IRQ stack
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ldmia sp!, {r0,r14}
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msr SPSR_cxsf, r14
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;- Restore adjusted LR_irq from IRQ stack directly in the PC
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ldmia sp!, {pc}^
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;------------------------------------------------------------------------------
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;- Exception Vectors
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;------------------------------------------------------------------------------
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PUBLIC AT91F_Default_FIQ_handler
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PUBLIC AT91F_Default_IRQ_handler
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PUBLIC AT91F_Spurious_handler
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ARM ; Always ARM mode after exeption
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AT91F_Default_FIQ_handler
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b AT91F_Default_FIQ_handler
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AT91F_Default_IRQ_handler
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b AT91F_Default_IRQ_handler
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AT91F_Spurious_handler
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b AT91F_Spurious_handler
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;------------------------------------------------------------------------------
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; ?INIT
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; Program entry.
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;------------------------------------------------------------------------------
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION text:CODE:NOROOT(2)
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REQUIRE __vector
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EXTERN ?main
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PUBLIC __iar_program_start
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EXTERN AT91F_LowLevelInit
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__iar_program_start:
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;------------------------------------------------------------------------------
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;- Low level Init is performed in a C function: AT91F_LowLevelInit
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;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
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;------------------------------------------------------------------------------
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;- Retrieve end of RAM address
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ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution
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ldr r0,=AT91F_LowLevelInit
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mov lr, pc
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bx r0 ;- Branch on C function (with interworking)
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; Initialize the stack pointers.
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; The pattern below can be used for any of the exception stacks:
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; FIQ, IRQ, SVC, ABT, UND, SYS.
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; The USR mode uses the same stack as SYS.
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; The stack segments must be defined in the linker command file,
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; and be declared above.
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mrs r0,cpsr ; Original PSR value
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bic r0,r0,#MODE_BITS ; Clear the mode bits
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orr r0,r0,#SVC_MODE ; Set SVC mode bits
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msr cpsr_c,r0 ; Change the mode
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ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
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bic r0,r0,#MODE_BITS ; Clear the mode bits
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orr r0,r0,#UND_MODE ; Set UND mode bits
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msr cpsr_c,r0 ; Change the mode
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ldr sp,=SFE(UND_STACK) ; End of UND_STACK
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bic r0,r0,#MODE_BITS ; Clear the mode bits
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orr r0,r0,#ABT_MODE ; Set ABT mode bits
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msr cpsr_c,r0 ; Change the mode
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ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
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bic r0,r0,#MODE_BITS ; Clear the mode bits
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orr r0,r0,#FIQ_MODE ; Set FIQ mode bits
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msr cpsr_c,r0 ; Change the mode
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ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
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;- Init the FIQ register
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ldr r8, =AT91C_BASE_AIC
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bic r0,r0,#MODE_BITS ; Clear the mode bits
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orr r0,r0,#IRQ_MODE ; Set IRQ mode bits
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msr cpsr_c,r0 ; Change the mode
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ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
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bic r0,r0,#MODE_BITS ; Clear the mode bits
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orr r0,r0,#SYS_MODE ; Set System mode bits
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msr cpsr_c,r0 ; Change the mode
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ldr sp,=SFE(CSTACK) ; End of CSTACK
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#ifdef __ARMVFP__
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; Enable the VFP coprocessor.
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mov r0, #0x40000000 ; Set EN bit in VFP
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fmxr fpexc, r0 ; FPEXC, clear others.
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; Disable underflow exceptions by setting flush to zero mode.
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; For full IEEE 754 underflow compliance this code should be removed
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; and the appropriate exception handler installed.
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mov r0, #0x01000000 ; Set FZ bit in VFP
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fmxr fpscr, r0 ; FPSCR, clear others.
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#endif
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; Add more initialization here
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msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
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; Continue to ?main for more IAR specific system startup
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ldr r0,=?main
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bx r0
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END ;- Terminates the assembly of the last module in a file
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