len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-09-01 11:53:53 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add FreeRTOS-Plus directory.

Browse source
This commit is contained in:
Richard Barry 2012-08-11 21:34:11 +00:00
parent 7bd5f21ad5
commit f508a5f653
6798 changed files with 134949 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

707
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h Normal file
View file

@ -0,0 +1,707 @@
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : AT91R40008.h
// Object : AT91R40008 definitions
// Generated : AT91 SW Application Group 02/19/2003 (11:13:31)
//
// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002//
// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//
// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//
// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002//
// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//
// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//
// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//
// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//
// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002//
// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003//
// ----------------------------------------------------------------------------
#ifndef AT91R40008_H
#define AT91R40008_H
/* AT91 Register type */
typedef volatile unsigned int AT91_REG; // Hardware register definition
typedef volatile unsigned int at91_reg;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode egister
AT91_REG AIC_SVR[32]; // Source Vector egister
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command egister
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Interface
// *****************************************************************************
typedef struct _AT91S_WD {
AT91_REG WD_OMR; // Overflow Mode Register
AT91_REG WD_CMR; // Clock Mode Register
AT91_REG WD_CR; // Control Register
AT91_REG WD_SR; // Status Register
} AT91S_WD, *AT91PS_WD;
// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register --------
#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable
#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable
#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable
#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable
#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable
// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register --------
#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection
#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32
#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128
#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024
#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096
#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value
#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key
// -------- WD_CR : (WD Offset: 0x8) Control Register --------
#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key
// -------- WD_SR : (WD Offset: 0xc) Status Register --------
#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Saving Controler
// *****************************************************************************
typedef struct _AT91S_PS {
AT91_REG PS_CR; // Control Register
AT91_REG PS_PCER; // Peripheral Clock Enable Register
AT91_REG PS_PCDR; // Peripheral Clock Disable Register
AT91_REG PS_PCSR; // Peripheral Clock Status Register
} AT91S_PS, *AT91PS_PS;
// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register --------
#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock
#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock
#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock
#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock
#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock
#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock
// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register --------
// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral Data Controller
// *****************************************************************************
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
} AT91S_PDC, *AT91PS_PDC;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[1]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type
#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity
#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity
#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity
#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode
#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode
#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt
#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt
#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Special Function Interface
// *****************************************************************************
typedef struct _AT91S_SF {
AT91_REG SF_CIDR; // Chip ID Register
AT91_REG SF_EXID; // Chip ID Extension Register
AT91_REG SF_RSR; // Reset Status Register
AT91_REG SF_MMR; // Memory Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SF_PMR; // Protect Mode Register
} AT91S_SF, *AT91PS_SF;
// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip
#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0
#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1
#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0
#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size
#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None
#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes
#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes
#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes
#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes
#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size
#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None
#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size
#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None
#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes
#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes
#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes
#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes
#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture
#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy
#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy
#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy
#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type
#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series
#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series
#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag
// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset
#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog
#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin
// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register --------
#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection
// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable
#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
typedef struct _AT91S_EBI {
AT91_REG EBI_CSR[8]; // Chip-select Register
AT91_REG EBI_RCR; // Remap Control Register
AT91_REG EBI_MCR; // Memory Control Register
} AT91S_EBI, *AT91PS_EBI;
// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width
#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width
#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width
#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states
#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state
#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state
#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state
#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state
#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state
#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state
#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state
#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state
#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable
#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size
#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte
#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte
#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte
#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte
#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time
#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF
#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF
#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF
#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF
#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF
#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF
#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF
#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF
#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type
#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable
#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address
// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable
#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI)
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91R40008
// *****************************************************************************
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister
// ========== Register definition for WD peripheral ==========
#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register
#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register
#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register
#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register
// ========== Register definition for PS peripheral ==========
#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register
#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register
#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register
#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register
// ========== Register definition for PIO peripheral ==========
#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register
#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register
#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register
#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register
#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register
#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register
#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register
#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register
#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register
#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register
#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register
#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register
#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register
#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register
#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register
#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register
#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register
#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register
#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register
#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register
#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B
#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value
#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register
#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C
#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A
#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register
#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B
#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value
#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register
#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C
#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A
#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register
#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B
#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value
#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register
#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C
#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A
#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register
// ========== Register definition for TCB0 peripheral ==========
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register
#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register
#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register
#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register
#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register
#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register
#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register
#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register
// ========== Register definition for SF peripheral ==========
#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register
#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register
#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register
#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register
#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register
// ========== Register definition for EBI peripheral ==========
#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register
#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register
#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0
#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal
#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1
#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A
#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10
#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1
#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11
#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2
#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12
#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt
#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13
#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock
#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14
#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data
#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15
#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data
#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16
#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17
#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18
#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19
#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2
#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B
#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20
#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock
#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21
#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data
#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode
#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22
#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data
#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23
#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24
#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select
#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25
#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out
#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26
#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2
#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27
#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3
#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28
#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20
#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7
#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29
#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21
#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6
#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3
#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal
#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30
#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22
#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5
#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31
#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23
#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4
#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4
#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A
#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5
#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B
#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6
#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal
#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7
#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A
#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8
#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B
#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9
#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ((unsigned int) 1) // SWI
#define AT91C_ID_US0 ((unsigned int) 2) // USART 0
#define AT91C_ID_US1 ((unsigned int) 3) // USART 1
#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0
#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1
#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2
#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer
#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller
#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address
#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address
#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address
#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address
#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address
#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address
#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address
#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address
#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address
#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)
#endif

24
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg Normal file
View file

@ -0,0 +1,24 @@
[SETUP]
CpuVendor=Atmel
CpuChip=AT91R40807
FlashVendor=Atmel
FlashChip=AT49BV/F1614A
RamAddress=$00000000
RamSupport=1
FlashAddress=$01000000
FlashWidth=16
FlashChipsPerSector=1
LittleEndian=0
SectStart=0
SectEnd=38
AutoErase=0
AutoVerify=1
CpuEndian=LITTLE
SimCount=3
MemoryCount=0
ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex
UploadFile=c:\EB40_Lower.bin
Format=Intel Hex
Sim3=EBI_RCR:$00000001
Sim2=EBI_CSR1:$02002122
Sim1=EBI_CSR0:$01002539

118
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h Normal file
View file

@ -0,0 +1,118 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <AT91R40008.h>
#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*/
/*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 66000000 ) /* = 66.000MHz clk gen */
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

125
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/Makefile Normal file
View file

@ -0,0 +1,125 @@
#/*
# FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
#
#
# ***************************************************************************
# * *
# * FreeRTOS tutorial books are available in pdf and paperback. *
# * Complete, revised, and edited pdf reference manuals are also *
# * available. *
# * *
# * Purchasing FreeRTOS documentation will not only help you, by *
# * ensuring you get running as quickly as possible and with an *
# * in-depth knowledge of how to use FreeRTOS, it will also help *
# * the FreeRTOS project to continue with its mission of providing *
# * professional grade, cross platform, de facto standard solutions *
# * for microcontrollers - completely free of charge! *
# * *
# * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
# * *
# * Thank you for using FreeRTOS, and thank you for your support! *
# * *
# ***************************************************************************
#
#
# This file is part of the FreeRTOS distribution.
#
# FreeRTOS is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License (version 2) as published by the
# Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
# >>>NOTE<<< The modification to the GPL is included to allow you to
# distribute a combined work that includes FreeRTOS without being obliged to
# provide the source code for proprietary components outside of the FreeRTOS
# kernel. FreeRTOS is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details. You should have received a copy of the GNU General Public
# License and the FreeRTOS license exception along with FreeRTOS; if not it
# can be viewed here: http://www.freertos.org/a00114.html and also obtained
# by writing to Richard Barry, contact details for whom are available on the
# FreeRTOS WEB site.
#
# 1 tab == 4 spaces!
#
# http://www.FreeRTOS.org - Documentation, latest information, license and
# contact details.
#
# http://www.SafeRTOS.com - A version that is certified for use in safety
# critical systems.
#
# http://www.OpenRTOS.com - Commercial support, development, porting,
# licensing and training services.
#*/
CC=arm-elf-gcc
OBJCOPY=arm-elf-objcopy
ARCH=arm-elf-ar
CRT0=boot.s
#
# CFLAGS common to both the THUMB and ARM mode builds
#
CFLAGS=-Wall -Wextra -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \
-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
-Wcast-align $(OPTIM) -fomit-frame-pointer -fno-strict-aliasing \
-fno-dwarf2-cfi-asm
ifeq ($(USE_THUMB_MODE),YES)
CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
THUMB_FLAGS=-mthumb
endif
LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
#
# Source files that can be built to THUMB mode.
#
THUMB_SRC = \
main.c \
serial/serial.c \
ParTest/ParTest.c \
../Common/Minimal/integer.c \
../Common/Minimal/flash.c \
../Common/Minimal/PollQ.c \
../Common/Minimal/comtest.c \
../Common/Minimal/flop.c \
../Common/Minimal/semtest.c \
../Common/Minimal/dynamic.c \
../Common/Minimal/BlockQ.c \
../../Source/tasks.c \
../../Source/queue.c \
../../Source/list.c \
../../Source/portable/MemMang/heap_2.c \
../../Source/portable/GCC/ARM7_AT91FR40008/port.c
#
# Source files that must be built to ARM mode.
#
ARM_SRC = \
../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \
serial/serialISR.c
#
# Define all object files.
#
ARM_OBJ = $(ARM_SRC:.c=.o)
THUMB_OBJ = $(THUMB_SRC:.c=.o)
rtosdemo.hex : rtosdemo.elf
$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(CFLAGS) $< -o $@
clean :
touch Makefile
rm $(ARM_OBJ)
rm $(THUMB_OBJ)

154
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c Normal file
View file

@ -0,0 +1,154 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "portable.h"
/* Demo app includes. */
#include "partest.h"
/* Hardware specific definitions. */
#include "AT91R40008.h"
#include "pio.h"
#include "aic.h"
#define partstNUM_LEDS ( 8 )
#define partstALL_OUTPUTS_OFF ( ( unsigned long ) ~(0xFFFFFFFF << partstNUM_LEDS) )
static unsigned long ulLEDReg;
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
static void SetLeds (unsigned int leds)
{
unsigned long ulPIOSetReg, ulPIOClearReg;
/* LEDs are grouped in different port bits: P3-P6 and P16-P19.
A port bit set to '0' turns an LED on, '1' turns it off. */
ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 );
ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078;
AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg;
AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg;
}
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. Ensure the outputs are off to start. */
ulLEDReg = partstALL_OUTPUTS_OFF;
/* Enable clock to PIO... */
AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO;
/* Enable all 8 LEDs and the four switches to be controlled by PIO... */
AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12;
/* Configure all LED PIO lines for output... */
AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19;
/* Configure all switch PIO lines for input... */
AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12;
/* Set initial state of LEDs. */
SetLeds( ulLEDReg );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
/* Switch an LED on or off as requested. */
if (uxLED < partstNUM_LEDS)
{
if( xValue )
{
ulLEDReg &= ~(1 << uxLED);
}
else
{
ulLEDReg |= (1 << uxLED);
}
SetLeds( ulLEDReg );
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
/* Toggle the state of the requested LED. */
if (uxLED < partstNUM_LEDS)
{
ulLEDReg ^= ( 1 << uxLED );
SetLeds( ulLEDReg );
}
}

81
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/aic.h Normal file
View file

@ -0,0 +1,81 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : aic.h
//* Object : Advanced Interrupt Controller Definition File.
//*
//* 1.0 01/04/00 JCZ : Creation
//*----------------------------------------------------------------------------
#ifndef aic_h
#define aic_h
//#include "periph/stdc/std_c.h"
/*-----------------------------------------*/
/* AIC User Interface Structure Definition */
/*-----------------------------------------*/
typedef struct
{
at91_reg AIC_SMR[32] ; /* Source Mode Register */
at91_reg AIC_SVR[32] ; /* Source Vector Register */
at91_reg AIC_IVR ; /* IRQ Vector Register */
at91_reg AIC_FVR ; /* FIQ Vector Register */
at91_reg AIC_ISR ; /* Interrupt Status Register */
at91_reg AIC_IPR ; /* Interrupt Pending Register */
at91_reg AIC_IMR ; /* Interrupt Mask Register */
at91_reg AIC_CISR ; /* Core Interrupt Status Register */
at91_reg reserved0 ;
at91_reg reserved1 ;
at91_reg AIC_IECR ; /* Interrupt Enable Command Register */
at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */
at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */
at91_reg AIC_ISCR ; /* Interrupt Set Command Register */
at91_reg AIC_EOICR ; /* End of Interrupt Command Register */
at91_reg AIC_SPU ; /* Spurious Vector Register */
} StructAIC ;
/*--------------------------------------------*/
/* AIC_SMR[]: Interrupt Source Mode Registers */
/*--------------------------------------------*/
#define AIC_PRIOR 0x07 /* Priority */
#define AIC_SRCTYPE 0x60 /* Source Type Definition */
/* Internal Interrupts */
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */
/* External Interrupts */
#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */
#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */
/*------------------------------------*/
/* AIC_ISR: Interrupt Status Register */
/*------------------------------------*/
#define AIC_IRQID 0x1F /* Current source interrupt */
/*------------------------------------------*/
/* AIC_CISR: Interrupt Core Status Register */
/*------------------------------------------*/
#define AIC_NFIQ 0x01 /* Core FIQ Status */
#define AIC_NIRQ 0x02 /* Core IRQ Status */
/*-------------------------------*/
/* Advanced Interrupt Controller */
/*-------------------------------*/
#define AIC_BASE ((StructAIC *)0xFFFFF000)
#endif /* aic_h */

54
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld Normal file
View file

@ -0,0 +1,54 @@
MEMORY
{
ram : ORIGIN = 0x00000000, LENGTH = 256K
}
__stack_end__ = 0x00000000 + 256K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >ram
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >ram
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
. = ALIGN(4);
.eh_frame :
{
KEEP (*(.eh_frame))
} > ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

55
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld Normal file
View file

@ -0,0 +1,55 @@
MEMORY
{
flash : ORIGIN = 0x00000000, LENGTH = 2048K
ram : ORIGIN = 0x00300000, LENGTH = 256K
}
__stack_end__ = 0x00300000 + 256K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >flash
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >flash
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram AT>flash
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
. = ALIGN(4);
.eh_frame :
{
KEEP (*(.eh_frame))
} > ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

157
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/boot.s Normal file
View file

@ -0,0 +1,157 @@
/* Sample initialization file */
.extern main
.extern exit
.text
.code 32
.align 0
.extern __bss_beg__
.extern __bss_end__
.extern __stack_end__
.extern __data_beg__
.extern __data_end__
.extern __data+beg_src__
.global start
.global endless_loop
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
.set FIQ_STACK_SIZE, 0x00000004
.set IRQ_STACK_SIZE, 0X00000400
.set SVC_STACK_SIZE, 0x00000400
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set MODE_USR, 0x10 /* User Mode */
.set MODE_FIQ, 0x11 /* FIQ Mode */
.set MODE_IRQ, 0x12 /* IRQ Mode */
.set MODE_SVC, 0x13 /* Supervisor Mode */
.set MODE_ABT, 0x17 /* Abort Mode */
.set MODE_UND, 0x1B /* Undefined Mode */
.set MODE_SYS, 0x1F /* System Mode */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
start:
_start:
_mainCRTStartup:
/* Setup a stack for each mode - note that this only sets up a usable stack
for system/user, SWI and IRQ modes. Also each mode is setup with
interrupts initially disabled. */
ldr r0, .LC6
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
mov sp, r0
/* We want to start in supervisor mode. Operation will switch to system
mode when the first task starts. */
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
/* Clear BSS. */
mov a2, #0 /* Fill value */
mov fp, a2 /* Null frame pointer */
mov r7, a2 /* Null frame pointer for Thumb */
ldr r1, .LC1 /* Start of memory block */
ldr r3, .LC2 /* End of memory block */
subs r3, r3, r1 /* Length of block */
beq .end_clear_loop
mov r2, #0
.clear_loop:
strb r2, [r1], #1
subs r3, r3, #1
bgt .clear_loop
.end_clear_loop:
/* Initialise data. */
ldr r1, .LC3 /* Start of memory block */
ldr r2, .LC4 /* End of memory block */
ldr r3, .LC5
subs r3, r3, r1 /* Length of block */
beq .end_set_loop
.set_loop:
ldrb r4, [r2], #1
strb r4, [r1], #1
subs r3, r3, #1
bgt .set_loop
.end_set_loop:
mov r0, #0 /* no arguments */
mov r1, #0 /* no argv either */
bl main
endless_loop:
b endless_loop
.align 0
.LC1:
.word __bss_beg__
.LC2:
.word __bss_end__
.LC3:
.word __data_beg__
.LC4:
.word __data_beg_src__
.LC5:
.word __data_end__
.LC6:
.word __stack_end__
/* Setup vector table. Note that undf, pabt, dabt, fiq just execute
a null loop. */
.section .startup,"ax"
.code 32
.align 0
b _start /* reset - _start */
ldr pc, _undf /* undefined - _undf */
ldr pc, _swi /* SWI - _swi */
ldr pc, _pabt /* program abort - _pabt */
ldr pc, _dabt /* data abort - _dabt */
nop /* reserved */
ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */
ldr pc, _fiq /* FIQ - _fiq */
_undf: .word __undf /* undefined */
_swi: .word vPortYieldProcessor /* SWI */
_pabt: .word __pabt /* program abort */
_dabt: .word __dabt /* data abort */
_fiq: .word __fiq /* FIQ */
__undf: b . /* undefined */
__pabt: b . /* program abort */
__dabt: b . /* data abort */
__fiq: b . /* FIQ */

121
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ebi.h Normal file
View file

@ -0,0 +1,121 @@
//*-----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*-----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : ebi.h
//* Object : External Bus Interface Definition File
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* 1.0 03/11/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*-----------------------------------------------------------------------------
#ifndef ebi_h
#define ebi_h
/*----------------------------------------*/
/* Memory Controller Interface Definition */
/*----------------------------------------*/
typedef struct
{
at91_reg EBI_CSR[8] ; /* Chip Select Register */
at91_reg EBI_RCR ; /* Remap Control Register */
at91_reg EBI_MCR ; /* Memory Control Register */
} StructEBI ;
/*-----------------------*/
/* Chip Select Registers */
/*-----------------------*/
/* Data Bus Width */
#define DataBus16 (1<<0)
#define DataBus8 (2<<0)
#define DBW (3<<0)
/* Number of Wait States */
#define B_NWS 2
#define WaitState1 (0<<B_NWS)
#define WaitState2 (1<<B_NWS)
#define WaitState3 (2<<B_NWS)
#define WaitState4 (3<<B_NWS)
#define WaitState5 (4<<B_NWS)
#define WaitState6 (5<<B_NWS)
#define WaitState7 (6<<B_NWS)
#define WaitState8 (7<<B_NWS)
#define NWS (7<<B_NWS)
/* Wait State Enable */
#define WaitStateDisable (0<<5)
#define WaitStateEnable (1<<5)
#define WSE (1<<5)
/* Page size */
#define PageSize1M (0<<7)
#define PageSize4M (1<<7)
#define PageSize16M (2<<7)
#define PageSize64M (3<<7)
#define PAGES (3<<7)
/* Number of Data Float Output Time Clock Cycle */
#define B_TDF 9
#define tDF_0cycle (0<<B_TDF)
#define tDF_1cycle (1<<B_TDF)
#define tDF_2cycle (2<<B_TDF)
#define tDF_3cycle (3<<B_TDF)
#define tDF_4cycle (4<<B_TDF)
#define tDF_5cycle (5<<B_TDF)
#define tDF_6cycle (6<<B_TDF)
#define tDF_7cycle (7<<B_TDF)
#define TDF (7<<B_TDF)
/* Byte Access Type */
#define ByteWriteAccessType (0<<12)
#define ByteSelectAccessType (1<<12)
#define BAT 1<<12)
/* Chip Select Enable */
#define CSEnable (1<<13)
#define CSDisable (0<<13)
#define CSE (1<<13)
#define BA ((u_int)(0xFFF)<<20)
/*-------------------------*/
/* Memory Control Register */
/*-------------------------*/
/* Address Line Enable */
#define ALE (7<<0)
#define BankSize16M (0<<0)
#define BankSize8M (4<<0)
#define BankSize4M (5<<0)
#define BankSize2M (6<<0)
#define BankSize1M (7<<0)
/* Data Read Protocol */
#define StandardReadProtocol (0<<4)
#define EarlyReadProtocol (1<<4)
#define DRP (1<<4)
/*------------------------*/
/* Remap Control Register */
/*------------------------*/
#define RCB (1<<0)
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
#ifdef AT91M40400
/* External Bus Interface User Interface BAse Address */
#define EBI_BASE ((StructEBI *) 0xFFE00000)
#endif
#endif /* ebi_h */

506
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/main.c Normal file
View file

@ -0,0 +1,506 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
/* Hardware specific definitions. */
#include "aic.h"
#include "ebi.h"
/*-----------------------------------------------------------*/
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
#define mainCOM_TEST_LED ( 5 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which the on board LED will toggle when there is/is not an
error. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
#define mainON_BOARD_LED_BIT ( ( unsigned long ) 7 )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
#define MAX_WAIT_STATES 8
static const unsigned long ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] =
{
WaitState1,/* There is no "zero wait state" value, so use one wait state */
WaitState1,
WaitState2,
WaitState3,
WaitState4,
WaitState5,
WaitState6,
WaitState7,
WaitState8
};
/*-----------------------------------------------------------*/
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*
* Configure the processor for use with the Olimex demo board. This includes
* setup for the I/O, system clock, and access timings.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Olimex demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
unsigned long ulMemCheckTaskRunningCount;
xTaskHandle xCreatedTask;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
In addition to the standard tests the memory allocator is tested through
the dynamic creation and deletion of a task each cycle. Each time the
task is created memory must be allocated for its stack. When the task is
deleted this memory is returned to the heap. If the task cannot be created
then it is likely that the memory allocation failed. */
for( ;; )
{
/* Reset xCreatedTask. This is modified by the task about to be
created so we can tell if it is executing correctly or not. */
xCreatedTask = mainNO_TASK;
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
if( xTaskCreate( vMemCheckTask, ( signed char * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* The toggle rate of the LED depends on how long this task delays for.
An error reduces the delay period and so increases the toggle rate. */
vParTestToggleLED( mainON_BOARD_LED_BIT );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
long lCount;
#ifdef RUN_FROM_ROM
{
portFLOAT nsecsPerClockTick;
long lNumWaitStates;
unsigned long ulCSRWaitValue;
/* We are compiling to run from ROM (either on-chip or off-chip flash).
Leave the RAM/flash mapped the way they are on reset
(flash @ 0x00000000, RAM @ 0x00300000), and set up the
proper flash wait states (starts out at the maximum number
of wait states on reset, so we should be able to reduce it).
Most of this code will probably get removed by the compiler
if optimization is enabled, since these calculations are
based on constants. But the compiler should still produce
a correct wait state register value. */
nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ;
lNumWaitStates = ( long )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1;
if( lNumWaitStates < 0 )
{
lNumWaitStates = 0;
}
if( lNumWaitStates > MAX_WAIT_STATES )
{
lNumWaitStates = MAX_WAIT_STATES;
}
ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ];
ulCSRWaitValue = WaitState5;
AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable
| PageSize1M | tDF_0cycle
| ByteWriteAccessType | CSEnable
| 0x00000000 /* Base Address */;
}
#else /* else we are compiling to run from on-chip RAM */
{
/* If compiling to run from RAM, we expect the on-chip RAM to already
be mapped at 0x00000000. This is typically done with an initialization
script for the JTAG emulator you are using to download and run the
demo application. So there is nothing to do here in this case. */
}
#endif
/* Disable all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
/* Set all SVR and SMR entries to default values (start with a clean slate)... */
for( lCount = 0; lCount < 32; lCount++ )
{
AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0;
AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
}
/* Disable clocks to all peripherals initially... */
AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF;
/* Clear all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
/* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out
nIRQ */
for( lCount = 0; lCount < 8; lCount++ )
{
AT91C_BASE_AIC->AIC_EOICR = 0;
}
/* Initialise LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount )
{
long lReturn = ( long ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
{
/* The vMemCheckTask did not increment the counter - it must
have failed. */
lReturn = ( long ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/
static void vMemCheckTask( void *pvParameters )
{
unsigned long *pulMemCheckTaskRunningCounter;
void *pvMem1, *pvMem2, *pvMem3;
static long lErrorOccurred = pdFALSE;
/* This task is dynamically created then deleted during each cycle of the
vErrorChecks task to check the operation of the memory allocator. Each time
the task is created memory is allocated for the stack and TCB. Each time
the task is deleted this memory is returned to the heap. This task itself
exercises the allocator by allocating and freeing blocks.
The task executes at the idle priority so does not require a delay.
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
vErrorChecks() task that this task is still executing without error. */
pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters;
for( ;; )
{
if( lErrorOccurred == pdFALSE )
{
/* We have never seen an error so increment the counter. */
( *pulMemCheckTaskRunningCounter )++;
}
else
{
/* There has been an error so reset the counter so the check task
can tell that an error occurred. */
*pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;
}
/* Allocate some memory - just to give the allocator some extra
exercise. This has to be in a critical section to ensure the
task does not get deleted while it has memory allocated. */
vTaskSuspendAll();
{
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
if( pvMem1 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
vPortFree( pvMem1 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
if( pvMem2 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
vPortFree( pvMem2 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
if( pvMem3 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
vPortFree( pvMem3 );
}
}
xTaskResumeAll();
}
}

149
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/pio.h Normal file
View file

@ -0,0 +1,149 @@
//*---------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*---------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : pio.h
//* Object : Parallel I/O Definition File
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* 1.0 20/10/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*---------------------------------------------------------------------------
#ifndef pio_h
#define pio_h
/*---------------------------------------------*/
/* Parallel I/O Interface Structure Definition */
/*---------------------------------------------*/
typedef struct
{
at91_reg PIO_PER ; /* PIO Enable Register */
at91_reg PIO_PDR ; /* PIO Disable Register */
at91_reg PIO_PSR ; /* PIO Status Register */
at91_reg Reserved0 ;
at91_reg PIO_OER ; /* Output Enable Register */
at91_reg PIO_ODR ; /* Output Disable Register */
at91_reg PIO_OSR ; /* Output Status Register */
at91_reg Reserved1 ;
at91_reg PIO_IFER ; /* Input Filter Enable Register */
at91_reg PIO_IFDR ; /* Input Filter Disable Register */
at91_reg PIO_IFSR ; /* Input Filter Status Register */
at91_reg Reserved2 ;
at91_reg PIO_SODR ; /* Set Output Data Register */
at91_reg PIO_CODR ; /* Clear Output Data Register */
at91_reg PIO_ODSR ; /* Output Data Status Register */
at91_reg PIO_PDSR ; /* Pin Data Status Register */
at91_reg PIO_IER ; /* Interrupt Enable Register */
at91_reg PIO_IDR ; /* Interrupt Disable Register */
at91_reg PIO_IMR ; /* Interrupt Mask Register */
at91_reg PIO_ISR ; /* Interrupt Status Register */
} StructPIO ;
/*-----------------------------*/
/* PIO Handler type definition */
/*-----------------------------*/
//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
/* Number of PIO Controller */
#define NB_PIO_CTRL 1
/* Base Address */
#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
/* Number of PIO Lines */
#define NB_PIO 32
/* Parallel I/O Bits Definition */
#define P0 (1<<0)
#define P1 (1<<1)
#define P2 (1<<2)
#define P3 (1<<3)
#define P4 (1<<4)
#define P5 (1<<5)
#define P6 (1<<6)
#define P7 (1<<7)
#define P8 (1<<8)
#define P9 (1<<9)
#define P10 (1<<10)
#define P11 (1<<11)
#define P12 (1<<12)
#define P13 (1<<13)
#define P14 (1<<14)
#define P15 (1<<15)
#define P16 (1<<16)
#define P17 (1<<17)
#define P18 (1<<18)
#define P19 (1<<19)
#define P20 (1<<20)
#define P21 (1<<21)
#define P22 (1<<22)
#define P23 (1<<23)
#define P24 (1<<24)
#define P25 (1<<25)
#define P26 (1<<26)
#define P27 (1<<27)
#define P28 (1<<28)
#define P29 (1<<29)
#define P30 (1<<30)
#define P31 (1<<31)
/* PIO Multiplexing Definition */
/* There is only one PIO Controller */
#define PIO_CTRL 0
#define PIO_TC0 PIO_CTRL
#define TCLK0 P0
#define TIOA0 P1
#define TIOB0 P2
#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
#define PIO_TC1 PIO_CTRL
#define TCLK1 P3
#define TIOA1 P4
#define TIOB1 P5
#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
#define PIO_TC2 PIO_CTRL
#define TCLK2 P6
#define TIOA2 P7
#define TIOB2 P8
#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
#define PIO_EXT_IRQ PIO_CTRL
#define PIN_IRQ0 P9
#define PIN_IRQ1 P10
#define PIN_IRQ2 P11
#define PIN_FIQ P12
#define PIO_USART0 PIO_CTRL
#define SCK0 P13
#define TXD0 P14
#define RXD0 P15
#define PIN_USART0 (SCK0|TXD0|RXD0)
#define PIO_USART1 PIO_CTRL
#define SCK1 P20
#define TXD1 P21
#define RXD1 P22
#define PIN_USART1 (SCK1|TXD1|RXD1)
#define MCKO P25
#define CS2 P26
#define CS3 P27
#define CS4 P31
#define CS5 P30
#define CS6 P29
#define CS7 P28
#endif /* pio_h */

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat Normal file
View file

@ -0,0 +1,6 @@
set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=atmel-ram.ld
make

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat Normal file
View file

@ -0,0 +1,6 @@
set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=atmel-ram.ld
make

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat Normal file
View file

@ -0,0 +1,6 @@
set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O2
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=atmel-rom.ld
make

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat Normal file
View file

@ -0,0 +1,6 @@
set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O2
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=atmel-rom.ld
make

266
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serial.c Normal file
View file

@ -0,0 +1,266 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
#include "AT91R40008.h"
#include "usart.h"
#include "pio.h"
#include "aic.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define portUSART0_AIC_CHANNEL ( ( unsigned long ) 2 )
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulSpeed;
unsigned long ulCD;
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR_Wrapper )( void );
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode. */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned long ) 0 )
)
{
portENTER_CRITICAL();
{
/* Enable clock to USART0... */
AT91C_BASE_PS->PS_PCER = AT91C_PS_US0;
/* Disable all USART0 interrupt sources to begin... */
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
/* Reset various status bits (just in case)... */
AT91C_BASE_US0->US_CR = US_RSTSTA;
AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */
AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS;
/* Clear Transmit and Receive Counters */
AT91C_BASE_US0->US_RCR = 0;
AT91C_BASE_US0->US_TCR = 0;
/* Input clock to baud rate generator is MCK */
ulSpeed = configCPU_CLOCK_HZ * 10;
ulSpeed = ulSpeed / 16;
ulSpeed = ulSpeed / ulWantedBaud;
/* compute the error */
ulCD = ulSpeed / 10;
if ((ulSpeed - (ulCD * 10)) >= 5)
ulCD++;
/* Define the baud rate divisor register */
AT91C_BASE_US0->US_BRGR = ulCD;
/* Define the USART mode */
AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL;
/* Write the Timeguard Register */
AT91C_BASE_US0->US_TTGR = 0;
/* Setup the interrupt for USART0.
Store interrupt handler function address in USART0 vector register... */
AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR_Wrapper;
/* USART0 interrupt level-sensitive, priority 1... */
AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1;
/* Clear some pending USART0 interrupts (just in case)... */
AT91C_BASE_US0->US_CR = US_RSTSTA;
/* Enable USART0 interrupt sources (but not Tx for now)... */
AT91C_BASE_US0->US_IER = US_RXRDY;
/* Enable USART0 interrupts in the AIC... */
AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL );
/* Enable receiver and transmitter... */
AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
( void ) pxPort;
/* Place the character in the queue of characters to be transmitted. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
return pdFAIL;
}
/* Turn on the Tx interrupt so the ISR will remove the character from the
queue and send it. This does not need to be in a critical section as
if the interrupt has already removed the character the next interrupt
will simply turn off the Tx interrupt again. */
AT91C_BASE_US0->US_IER = US_TXRDY;
return pdPASS;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/

193
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c Normal file
View file

@ -0,0 +1,193 @@
/*
FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong? *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest information,
license and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
#include "AT91R40008.h"
#include "usart.h"
/*-----------------------------------------------------------*/
/* Constant to access the AIC. */
#define serCLEAR_AIC_INTERRUPT ( ( unsigned long ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned char ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
#define serSOURCE_RX ( ( unsigned char ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned long ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/* UART0 interrupt service routine. This can cause a context switch so MUST
be declared "naked". */
void vUART_ISR_Wrapper( void ) __attribute__ ((naked));
/* The ISR function that actually performs the work. This must be separate
from the wrapper to ensure the correct stack frame is set up. */
void vUART_ISR_Handler( void ) __attribute__ ((noinline));
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
}
/*-----------------------------------------------------------*/
void vUART_ISR_Wrapper( void )
{
/* Save the context of the interrupted task. */
portSAVE_CONTEXT();
/* Call the handler. This must be a separate function to ensure the
stack frame is correctly set up. */
__asm volatile( "bl vUART_ISR_Handler" );
/* Restore the context of whichever task will run next. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
void vUART_ISR_Handler( void )
{
/* Now we can declare the local variables. These must be static. */
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
unsigned long ulStatus;
/* What caused the interrupt? */
ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR;
if (ulStatus & US_TXRDY)
{
/* The interrupt was caused by the THR becoming empty. Are there any
more characters to transmit? */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
THR now. */
AT91C_BASE_US0->US_THR = cChar;
}
else
{
/* Queue empty, nothing to send so turn off the Tx interrupt. */
AT91C_BASE_US0->US_IDR = US_TXRDY;
}
}
if (ulStatus & US_RXRDY)
{
/* The interrupt was caused by the receiver getting data. */
cChar = AT91C_BASE_US0->US_RHR;
xQueueSendFromISR(xRxedChars, &cChar, &xHigherPriorityTaskWoken);
}
/* Acknowledge the interrupt at AIC level... */
AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT;
/* If an event caused a task to unblock then we call "Yield from ISR" to
ensure that the unblocked task is the task that executes when the interrupt
completes if the unblocked task has a priority higher than the interrupted
task. */
if( xHigherPriorityTaskWoken )
{
portYIELD_FROM_ISR();
}
}
/*-----------------------------------------------------------*/

301
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/tc.h Normal file
View file

@ -0,0 +1,301 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : tc.h
//* Object : Timer Counter Header File
//*
//* 1.0 01/04/00 JCZ : Creation
//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT,
//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT
//*-----------------------------------------------------------------------------
#ifndef tc_h
#define tc_h
//#include "periph/stdc/std_c.h"
//#include "periph/pio/lib_pio.h"
/*-------------------------------------------*/
/* Timer User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg TC_CCR ; /* Control Register */
at91_reg TC_CMR ; /* Mode Register */
at91_reg Reserved0 ;
at91_reg Reserved1 ;
at91_reg TC_CV ; /* Counter value */
at91_reg TC_RA ; /* Register A */
at91_reg TC_RB ; /* Register B */
at91_reg TC_RC ; /* Register C */
at91_reg TC_SR ; /* Status Register */
at91_reg TC_IER ; /* Interrupt Enable Register */
at91_reg TC_IDR ; /* Interrupt Disable Register */
at91_reg TC_IMR ; /* Interrupt Mask Register */
at91_reg Reserved2 ;
at91_reg Reserved3 ;
at91_reg Reserved4 ;
at91_reg Reserved5 ;
} StructTC ;
#define NB_TC_CHANNEL 3
typedef struct
{
StructTC TC[NB_TC_CHANNEL] ;
at91_reg TC_BCR ; /* Block Control Register */
at91_reg TC_BMR ; /* Block Mode Register */
} StructTCBlock ;
/*--------------------------------------------------------*/
/* TC_CCR: Timer Counter Control Register Bits Definition */
/*--------------------------------------------------------*/
#define TC_CLKEN 0x1
#define TC_CLKDIS 0x2
#define TC_SWTRG 0x4
/*---------------------------------------------------------------*/
/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */
/*---------------------------------------------------------------*/
/*-----------------*/
/* Clock Selection */
/*-----------------*/
#define TC_CLKS 0x7
#define TC_CLKS_MCK2 0x0
#define TC_CLKS_MCK8 0x1
#define TC_CLKS_MCK32 0x2
#define TC_CLKS_MCK128 0x3
#define TC_CLKS_MCK1024 0x4
#define TC_CLKS_SLCK 0x4
#define TC_CLKS_XC0 0x5
#define TC_CLKS_XC1 0x6
#define TC_CLKS_XC2 0x7
/*-----------------*/
/* Clock Inversion */
/*-----------------*/
#define TC_CLKI 0x8
/*------------------------*/
/* Burst Signal Selection */
/*------------------------*/
#define TC_BURST 0x30
#define TC_BURST_NONE 0x0
#define TC_BUSRT_XC0 0x10
#define TC_BURST_XC1 0x20
#define TC_BURST_XC2 0x30
/*------------------------------------------------------*/
/* Capture Mode : Counter Clock Stopped with RB Loading */
/*------------------------------------------------------*/
#define TC_LDBSTOP 0x40
/*-------------------------------------------------------*/
/* Waveform Mode : Counter Clock Stopped with RC Compare */
/*-------------------------------------------------------*/
#define TC_CPCSTOP 0x40
/*-------------------------------------------------------*/
/* Capture Mode : Counter Clock Disabled with RB Loading */
/*--------------------------------------------------------*/
#define TC_LDBDIS 0x80
/*--------------------------------------------------------*/
/* Waveform Mode : Counter Clock Disabled with RC Compare */
/*--------------------------------------------------------*/
#define TC_CPCDIS 0x80
/*------------------------------------------------*/
/* Capture Mode : External Trigger Edge Selection */
/*------------------------------------------------*/
#define TC_ETRGEDG 0x300
#define TC_ETRGEDG_EDGE_NONE 0x0
#define TC_ETRGEDG_RISING_EDGE 0x100
#define TC_ETRGEDG_FALLING_EDGE 0x200
#define TC_ETRGEDG_BOTH_EDGE 0x300
/*-----------------------------------------------*/
/* Waveform Mode : External Event Edge Selection */
/*-----------------------------------------------*/
#define TC_EEVTEDG 0x300
#define TC_EEVTEDG_EDGE_NONE 0x0
#define TC_EEVTEDG_RISING_EDGE 0x100
#define TC_EEVTEDG_FALLING_EDGE 0x200
#define TC_EEVTEDG_BOTH_EDGE 0x300
/*--------------------------------------------------------*/
/* Capture Mode : TIOA or TIOB External Trigger Selection */
/*--------------------------------------------------------*/
#define TC_ABETRG 0x400
#define TC_ABETRG_TIOB 0x0
#define TC_ABETRG_TIOA 0x400
/*------------------------------------------*/
/* Waveform Mode : External Event Selection */
/*------------------------------------------*/
#define TC_EEVT 0xC00
#define TC_EEVT_TIOB 0x0
#define TC_EEVT_XC0 0x400
#define TC_EEVT_XC1 0x800
#define TC_EEVT_XC2 0xC00
/*--------------------------------------------------*/
/* Waveform Mode : Enable Trigger on External Event */
/*--------------------------------------------------*/
#define TC_ENETRG 0x1000
/*----------------------------------*/
/* RC Compare Enable Trigger Enable */
/*----------------------------------*/
#define TC_CPCTRG 0x4000
/*----------------*/
/* Mode Selection */
/*----------------*/
#define TC_WAVE 0x8000
#define TC_CAPT 0x0
/*-------------------------------------*/
/* Capture Mode : RA Loading Selection */
/*-------------------------------------*/
#define TC_LDRA 0x30000
#define TC_LDRA_EDGE_NONE 0x0
#define TC_LDRA_RISING_EDGE 0x10000
#define TC_LDRA_FALLING_EDGE 0x20000
#define TC_LDRA_BOTH_EDGE 0x30000
/*-------------------------------------------*/
/* Waveform Mode : RA Compare Effect on TIOA */
/*-------------------------------------------*/
#define TC_ACPA 0x30000
#define TC_ACPA_OUTPUT_NONE 0x0
#define TC_ACPA_SET_OUTPUT 0x10000
#define TC_ACPA_CLEAR_OUTPUT 0x20000
#define TC_ACPA_TOGGLE_OUTPUT 0x30000
/*-------------------------------------*/
/* Capture Mode : RB Loading Selection */
/*-------------------------------------*/
#define TC_LDRB 0xC0000
#define TC_LDRB_EDGE_NONE 0x0
#define TC_LDRB_RISING_EDGE 0x40000
#define TC_LDRB_FALLING_EDGE 0x80000
#define TC_LDRB_BOTH_EDGE 0xC0000
/*-------------------------------------------*/
/* Waveform Mode : RC Compare Effect on TIOA */
/*-------------------------------------------*/
#define TC_ACPC 0xC0000
#define TC_ACPC_OUTPUT_NONE 0x0
#define TC_ACPC_SET_OUTPUT 0x40000
#define TC_ACPC_CLEAR_OUTPUT 0x80000
#define TC_ACPC_TOGGLE_OUTPUT 0xC0000
/*-----------------------------------------------*/
/* Waveform Mode : External Event Effect on TIOA */
/*-----------------------------------------------*/
#define TC_AEEVT 0x300000
#define TC_AEEVT_OUTPUT_NONE 0x0
#define TC_AEEVT_SET_OUTPUT 0x100000
#define TC_AEEVT_CLEAR_OUTPUT 0x200000
#define TC_AEEVT_TOGGLE_OUTPUT 0x300000
/*-------------------------------------------------*/
/* Waveform Mode : Software Trigger Effect on TIOA */
/*-------------------------------------------------*/
#define TC_ASWTRG 0xC00000
#define TC_ASWTRG_OUTPUT_NONE 0x0
#define TC_ASWTRG_SET_OUTPUT 0x400000
#define TC_ASWTRG_CLEAR_OUTPUT 0x800000
#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000
/*-------------------------------------------*/
/* Waveform Mode : RB Compare Effect on TIOB */
/*-------------------------------------------*/
#define TC_BCPB 0x1000000
#define TC_BCPB_OUTPUT_NONE 0x0
#define TC_BCPB_SET_OUTPUT 0x1000000
#define TC_BCPB_CLEAR_OUTPUT 0x2000000
#define TC_BCPB_TOGGLE_OUTPUT 0x3000000
/*-------------------------------------------*/
/* Waveform Mode : RC Compare Effect on TIOB */
/*-------------------------------------------*/
#define TC_BCPC 0xC000000
#define TC_BCPC_OUTPUT_NONE 0x0
#define TC_BCPC_SET_OUTPUT 0x4000000
#define TC_BCPC_CLEAR_OUTPUT 0x8000000
#define TC_BCPC_TOGGLE_OUTPUT 0xC000000
/*-----------------------------------------------*/
/* Waveform Mode : External Event Effect on TIOB */
/*-----------------------------------------------*/
#define TC_BEEVT 0x30000000 //* bit 29-28
#define TC_BEEVT_OUTPUT_NONE 0x0
#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01
#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10
#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11
/*- -----------------------------------------------*/
/* Waveform Mode : Software Trigger Effect on TIOB */
/*-------------------------------------------------*/
#define TC_BSWTRG 0xC0000000
#define TC_BSWTRG_OUTPUT_NONE 0x0
#define TC_BSWTRG_SET_OUTPUT 0x40000000
#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000
#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000
/*------------------------------------------------------*/
/* TC_SR: Timer Counter Status Register Bits Definition */
/*------------------------------------------------------*/
#define TC_COVFS 0x1 /* Counter Overflow Status */
#define TC_LOVRS 0x2 /* Load Overrun Status */
#define TC_CPAS 0x4 /* RA Compare Status */
#define TC_CPBS 0x8 /* RB Compare Status */
#define TC_CPCS 0x10 /* RC Compare Status */
#define TC_LDRAS 0x20 /* RA Loading Status */
#define TC_LDRBS 0x40 /* RB Loading Status */
#define TC_ETRGS 0x80 /* External Trigger Status */
#define TC_CLKSTA 0x10000 /* Clock Status */
#define TC_MTIOA 0x20000 /* TIOA Mirror */
#define TC_MTIOB 0x40000 /* TIOB Status */
/*--------------------------------------------------------------*/
/* TC_BCR: Timer Counter Block Control Register Bits Definition */
/*--------------------------------------------------------------*/
#define TC_SYNC 0x1 /* Synchronisation Trigger */
/*------------------------------------------------------------*/
/* TC_BMR: Timer Counter Block Mode Register Bits Definition */
/*------------------------------------------------------------*/
#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */
#define TC_TCLK0XC0 0x0
#define TC_NONEXC0 0x1
#define TC_TIOA1XC0 0x2
#define TC_TIOA2XC0 0x3
#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */
#define TC_TCLK1XC1 0x0
#define TC_NONEXC1 0x4
#define TC_TIOA0XC1 0x8
#define TC_TIOA2XC1 0xC
#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */
#define TC_TCLK2XC2 0x0
#define TC_NONEXC2 0x10
#define TC_TIOA0XC2 0x20
#define TC_TIOA1XC2 0x30
#endif /* tc_h */

151
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/usart.h Normal file
View file

@ -0,0 +1,151 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : usart.h
//* Object : USART Header File.
//*
//* 1.0 01/04/00 JCZ : Creation
//*----------------------------------------------------------------------------
#ifndef usart_h
#define usart_h
//#include "periph/stdc/std_c.h"
//#include "periph/pio/lib_pio.h"
/*-------------------------------------------*/
/* USART User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg US_CR ; /* Control Register */
at91_reg US_MR ; /* Mode Register */
at91_reg US_IER ; /* Interrupt Enable Register */
at91_reg US_IDR ; /* Interrupt Disable Register */
at91_reg US_IMR ; /* Interrupt Mask Register */
at91_reg US_CSR ; /* Channel Status Register */
at91_reg US_RHR ; /* Receive Holding Register */
at91_reg US_THR ; /* Transmit Holding Register */
at91_reg US_BRGR ; /* Baud Rate Generator Register */
at91_reg US_RTOR ; /* Receiver Timeout Register */
at91_reg US_TTGR ; /* Transmitter Time-guard Register */
at91_reg Reserved ;
at91_reg US_RPR ; /* Receiver Pointer Register */
at91_reg US_RCR ; /* Receiver Counter Register */
at91_reg US_TPR ; /* Transmitter Pointer Register */
at91_reg US_TCR ; /* Transmitter Counter Register */
} StructUSART ;
/*--------------------------*/
/* US_CR : Control Register */
/*--------------------------*/
#define US_RSTRX 0x0004 /* Reset Receiver */
#define US_RSTTX 0x0008 /* Reset Transmitter */
#define US_RXEN 0x0010 /* Receiver Enable */
#define US_RXDIS 0x0020 /* Receiver Disable */
#define US_TXEN 0x0040 /* Transmitter Enable */
#define US_TXDIS 0x0080 /* Transmitter Disable */
#define US_RSTSTA 0x0100 /* Reset Status Bits */
#define US_STTBRK 0x0200 /* Start Break */
#define US_STPBRK 0x0400 /* Stop Break */
#define US_STTTO 0x0800 /* Start Time-out */
#define US_SENDA 0x1000 /* Send Address */
/*-----------------------*/
/* US_MR : Mode Register */
/*-----------------------*/
#define US_CLKS 0x0030 /* Clock Selection */
#define US_CLKS_MCK 0x00 /* Master Clock */
#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */
#define US_CLKS_SCK 0x20 /* External Clock */
#define US_CLKS_SLCK 0x30 /* Slow Clock */
#define US_CHRL 0x00C0 /* Byte Length */
#define US_CHRL_5 0x00 /* 5 bits */
#define US_CHRL_6 0x40 /* 6 bits */
#define US_CHRL_7 0x80 /* 7 bits */
#define US_CHRL_8 0xC0 /* 8 bits */
#define US_SYNC 0x0100 /* Synchronous Mode Enable */
#define US_PAR 0x0E00 /* Parity Mode */
#define US_PAR_EVEN 0x00 /* Even Parity */
#define US_PAR_ODD 0x200 /* Odd Parity */
#define US_PAR_SPACE 0x400 /* Space Parity to 0 */
#define US_PAR_MARK 0x600 /* Marked Parity to 1 */
#define US_PAR_NO 0x800 /* No Parity */
#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */
#define US_NBSTOP 0x3000 /* Stop Bit Number */
#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */
#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */
#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */
#define US_CHMODE 0xC000 /* Channel Mode */
#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */
#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */
#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */
#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */
#define US_MODE9 0x20000 /* 9 Bit Mode */
#define US_CLKO 0x40000 /* Baud Rate Output Enable */
/* Mode Register model */
/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_SCK )
/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
#define US_SYNC_MODE ( US_SYNC + \
US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* SCK used Label */
#define SCK_USED (US_CLKO | US_CLKS_SCK)
/*---------------------------------------------------------------*/
/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */
/*---------------------------------------------------------------*/
#define US_RXRDY 0x1 /* Receiver Ready */
#define US_TXRDY 0x2 /* Transmitter Ready */
#define US_RXBRK 0x4 /* Receiver Break */
#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */
#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */
#define US_OVRE 0x20 /* Overrun Error */
#define US_FRAME 0x40 /* Framing Error */
#define US_PARE 0x80 /* Parity Error */
#define US_TIMEOUT 0x100 /* Receiver Timeout */
#define US_TXEMPTY 0x200 /* Transmitter Empty */
#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)
#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)
#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
#endif /* usart_h */