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Ready the PPC440 projects for release.

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This commit is contained in:
Richard Barry 2009-07-05 08:41:27 +00:00
parent 3634ebb497
commit f42b1510fa
41 changed files with 16992 additions and 833 deletions
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6
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
View file

@ -52,6 +52,8 @@
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <xparameters.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
@ -68,12 +70,12 @@
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 )
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 200000000 ) /* Clock setup from start.asm in the demo application. */
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ ) /* Clock setup from start.asm in the demo application. */
#define configTICK_RATE_HZ ( (portTickType) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )
#define configMAX_TASK_NAME_LEN ( 20 )
#define configUSE_16_BIT_TICKS 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_TRACE_FACILITY 0

1
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
View file

@ -699,3 +699,4 @@ volatile signed portCHAR *pcTaskNameIn = pcTaskName;

BIN
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system.ise
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Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock
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2
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
View file

@ -2,7 +2,7 @@ CommandLine-Map
s
CommandLine-Ngdbuild
ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd
s
CommandLine-Par

2
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
View file

@ -2,7 +2,7 @@ ISE_VERSION_CREATED_WITH
11.1
s
ISE_VERSION_LAST_SAVED_WITH
11.1
11.2
s
LastRepoDir
E:\my_projects\Wittenstein\release\svn\main2\FreeRTOS\Demo\PPC440_FPU_Xilinx_Virtex5_GCC\__xps\ise\

2
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version
View file

@ -7,4 +7,4 @@ OBJSTORE_VERSION
ISE_VERSION_CREATED_WITH
11.1
ISE_VERSION_LAST_SAVED_WITH
11.1
11.2

6
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/system.filters
View file

@ -3,7 +3,7 @@
<SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="146" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="0" COL_WIDTH="211" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
@ -74,8 +74,8 @@
</SET>
<SET CLASS="PROJECT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="211" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>

37
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/__xps/system.gui
View file

@ -3,15 +3,15 @@
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="0" COL_WIDTH="203" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="328" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="469" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="144,736,294" VERSION="0"/>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="105,721,287" VERSION="0"/>
<STATUS>
<SELECTIONS/>
</STATUS>
@ -32,7 +32,7 @@
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="67">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="252" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
@ -45,9 +45,12 @@
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,475,117" VERSION="0"/>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,875,215" VERSION="0"/>
<SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
<SET ID="xps_intc_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
@ -69,19 +72,23 @@
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="ADDRESS">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="25" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="361" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,1094,0" VERSION="0"/>
<STATUS>
<SELECTIONS/>
</STATUS>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">

7415
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system.log
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File diff suppressed because it is too large Load diff

1
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system.make
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@ -245,6 +245,7 @@ $(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm
################## BEHAVIORAL SIMULATION ##################
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
$(WRAPPER_NGC_FILES) \
$(BRAMINIT_ELF_FILES)
@echo "*********************************************"
@echo "Creating behavioral simulation models..."

4
Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system_incl.make
View file

@ -57,9 +57,9 @@ TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
MIX_LANG_SIM_OPT = -mixed yes
MIX_LANG_SIM_OPT = -mixed no
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -sd implementation/ -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/
LIBRARIES = \

6
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
View file

@ -52,6 +52,8 @@
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <xparameters.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
@ -68,12 +70,12 @@
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 )
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 200000000 ) /* Clock setup from start.asm in the demo application. */
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ ) /* Clock setup from start.asm in the demo application. */
#define configTICK_RATE_HZ ( (portTickType) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )
#define configMAX_TASK_NAME_LEN ( 20 )
#define configUSE_16_BIT_TICKS 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_TRACE_FACILITY 0

BIN
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system.ise
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Binary file not shown.

BIN
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock
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Binary file not shown.

2
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
View file

@ -2,7 +2,7 @@ CommandLine-Map
s
CommandLine-Ngdbuild
ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd
s
CommandLine-Par

2
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
View file

@ -2,7 +2,7 @@ ISE_VERSION_CREATED_WITH
11.1
s
ISE_VERSION_LAST_SAVED_WITH
11.1
11.2
s
LastRepoDir
E:\my_projects\Wittenstein\release\svn\main2\FreeRTOS\Demo\PPC440_FPU_Xilinx_Virtex5_GCC\__xps\ise\

2
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version
View file

@ -7,4 +7,4 @@ OBJSTORE_VERSION
ISE_VERSION_CREATED_WITH
11.1
ISE_VERSION_LAST_SAVED_WITH
11.1
11.2

2
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/__xps/system.gui
View file

@ -11,7 +11,7 @@
<VARIABLE COL_INDEX="5" COL_WIDTH="327" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="144,735,295" VERSION="0"/>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="137,696,280" VERSION="0"/>
<STATUS>
<SELECTIONS/>
</STATUS>

4355
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.log
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File diff suppressed because it is too large Load diff

1
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.make
View file

@ -245,6 +245,7 @@ $(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm
################## BEHAVIORAL SIMULATION ##################
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
$(WRAPPER_NGC_FILES) \
$(BRAMINIT_ELF_FILES)
@echo "*********************************************"
@echo "Creating behavioral simulation models..."

4
Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system_incl.make
View file

@ -57,9 +57,9 @@ TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
MIX_LANG_SIM_OPT = -mixed yes
MIX_LANG_SIM_OPT = -mixed no
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -sd implementation/ -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/
LIBRARIES = \

6
Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
View file

@ -52,6 +52,8 @@
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <xparameters.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
@ -68,12 +70,12 @@
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 )
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 200000000 ) /* Clock setup from start.asm in the demo application. */
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ ) /* Clock setup from start.asm in the demo application. */
#define configTICK_RATE_HZ ( (portTickType) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )
#define configMAX_TASK_NAME_LEN ( 20 )
#define configUSE_16_BIT_TICKS 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_TRACE_FACILITY 0

140
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs
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@ -5,107 +5,125 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Map" num="220" delta="new" >The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option.
<msg type="info" file="Map" num="220" delta="old" >The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option.
</msg>
<msg type="warning" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N194</arg> has no load.
<msg type="warning" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N194</arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">1200</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">N195,
<msg type="warning" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">warning</arg> message is repeated <arg fmt="%d" index="2">1200</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N195,
N196,
N197,
N198,
N199</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
To see the details of these <arg fmt="%s" index="4">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="159" delta="new" >Net Timing constraints on signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_CLK_pin</arg> are pushed forward through input buffer.
<msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_CLK_pin</arg> are pushed forward through input buffer.
</msg>
<msg type="info" file="MapLib" num="856" delta="new" >PLL_ADV <arg fmt="%s" index="1">clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg> CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin.
<msg type="info" file="MapLib" num="856" delta="old" >PLL_ADV <arg fmt="%s" index="1">clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg> CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> has been removed.
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">fpga_0_Ethernet_MAC_PHY_col_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_Ethernet_MAC_PHY_col_pin</arg> has been removed.
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">fpga_0_Ethernet_MAC_PHY_col_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_Ethernet_MAC_PHY_col_pin</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="41" delta="new" >All members of TNM group &quot;<arg fmt="%s" index="1">ppc440_0_PPCS0PLBMBUSY</arg>&quot; have been optimized out of the design.
<msg type="warning" file="MapLib" num="41" delta="old" >All members of TNM group &quot;<arg fmt="%s" index="1">ppc440_0_PPCS0PLBMBUSY</arg>&quot; have been optimized out of the design.
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg>
of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg>
of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg>
of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg>
of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg>
of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg>
of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg>
of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg>
of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg>
of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg>
of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
</msg>
<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
<msg type="warning" file="Pack" num="2874" delta="new" >Trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg>
of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
</msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">0.950</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">0.950</arg> to <arg fmt="%0.3f" index="3">1.050</arg> Volts)
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">0.950</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">0.950</arg> to <arg fmt="%0.3f" index="3">1.050</arg> Volts)
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4</arg> ignored during timing analysis.</msg>
<msg type="warning" file="Timing" num="3223" delta="old" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="warning" file="Place" num="838" delta="new" >An IO Bus with more than one IO standard is found.
<msg type="warning" file="Place" num="838" delta="old" >An IO Bus with more than one IO standard is found.
<arg fmt="%s" index="1">Components associated with this bus are as follows:
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;7&gt; IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin&lt;6&gt; IOSTANDARD = LVCMOS25
@ -119,7 +137,7 @@ To see the details of these <arg fmt="%s" index="5">warning</arg> messages, plea
</arg>
</msg>
<msg type="warning" file="Place" num="838" delta="new" >An IO Bus with more than one IO standard is found.
<msg type="warning" file="Place" num="838" delta="old" >An IO Bus with more than one IO standard is found.
<arg fmt="%s" index="1">Components associated with this bus are as follows:
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;31&gt; IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin&lt;30&gt; IOSTANDARD = LVDCI_33
@ -157,79 +175,79 @@ To see the details of these <arg fmt="%s" index="5">warning</arg> messages, plea
</arg>
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="0">One or more GTXs are being used in this design. Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX Transceiver User Guide to ensure that the design SelectIO usage meets the guidelines to minimize the impact on GTX performance.
<msg type="warning" file="PhysDesignRules" num="1842" delta="new" >One or more GTXs are being used in this design. Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX Transceiver User Guide to ensure that the design SelectIO usage meets the guidelines to minimize the impact on GTX performance.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset&lt;0&gt;</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset&lt;0&gt;</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
<msg type="warning" file="PhysDesignRules" num="372" delta="old" >Gated clock. Clock net <arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n&lt;0&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n&lt;0&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn&lt;0&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn&lt;0&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;31&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;30&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;30&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;31&gt;</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
<msg type="warning" file="PhysDesignRules" num="1269" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The Q1 output pin of IFF is not used.
</msg>
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
<msg type="warning" file="PhysDesignRules" num="1273" delta="old" >Dangling pins on block:&lt;<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>&gt;:&lt;<arg fmt="%s" index="2">ILOGIC_IFF</arg>&gt;. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
</msg>
</messages>

708
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngdbuild.xmsgs
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File diff suppressed because it is too large Load diff

30
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/par.xmsgs
View file

@ -5,47 +5,47 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66101)]</arg> overrides constraint <arg fmt="%s" index="2">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66100)]</arg>.
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(65973)]</arg> overrides constraint <arg fmt="%s" index="2">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(65972)]</arg>.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
<msg type="warning" file="Timing" num="3223" delta="old" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn&lt;0&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;31&gt;</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;30&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;30&gt;</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr&lt;31&gt;</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg> has no load. PAR will not attempt to route this signal.
<msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="info" file="Route" num="501" delta="new" >One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation.
<msg type="info" file="Route" num="501" delta="old" >One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation.
</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
<msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="info" file="ParHelpers" num="197" delta="new" >Number of &quot;Exact&quot; mode Directed Routing Constraints: <arg fmt="%d" index="1">128</arg>
<msg type="info" file="ParHelpers" num="197" delta="old" >Number of &quot;Exact&quot; mode Directed Routing Constraints: <arg fmt="%d" index="1">128</arg>
</msg>
<msg type="info" file="ParHelpers" num="199" delta="new" >All &quot;EXACT&quot; mode Directed Routing constrained nets successfully routed. The number of constraints found: <arg fmt="%d" index="1">128</arg>, number successful: <arg fmt="%d" index="2">128</arg>
<msg type="info" file="ParHelpers" num="199" delta="old" >All &quot;EXACT&quot; mode Directed Routing constrained nets successfully routed. The number of constraints found: <arg fmt="%d" index="1">128</arg>, number successful: <arg fmt="%d" index="2">128</arg>
</msg>
</messages>

10
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/trce.xmsgs
View file

@ -5,16 +5,16 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66101)]</arg> overrides constraint <arg fmt="%s" index="2">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(66100)]</arg>.
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(65973)]</arg> overrides constraint <arg fmt="%s" index="2">&lt;NET &quot;PCIe_Bridge/Bridge_Clk&quot; PERIOD = 8 ns HIGH 50%;&gt; [system.pcf(65972)]</arg>.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
<msg type="warning" file="Timing" num="3223" delta="old" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP &quot;TNM_RDEN_SEL_MUX&quot; TO TIMEGRP &quot;TNM_CLK0&quot; TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3386" delta="old" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>

692
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/xst.xmsgs
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Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ise
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4
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ntrc_log
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@ -2,3 +2,7 @@
Xst NTRC: "/" : OUT_OF_DATE
--------------------
Map NTRC: "/" : OUT_OF_DATE
--------------------
Xst NTRC: "/" : OUT_OF_DATE
--------------------
Map NTRC: "/" : OUT_OF_DATE

BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/cst.xbcd
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2
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
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@ -2,7 +2,7 @@ CommandLine-Map
s
CommandLine-Ngdbuild
ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm E:/my_projects/Wittenstein/release/svn/main/FreeRTOS/Demo/PCC440_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd
ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd
s
CommandLine-Par

2
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
View file

@ -2,7 +2,7 @@ ISE_VERSION_CREATED_WITH
11.1
s
ISE_VERSION_LAST_SAVED_WITH
11.1
11.2
s
LastRepoDir
E:\my_projects\Wittenstein\release\svn\main\FreeRTOS\Demo\PCC440_Xilinx_Virtex5_GCC\__xps\ise\

2
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise/version
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@ -7,4 +7,4 @@ OBJSTORE_VERSION
ISE_VERSION_CREATED_WITH
11.1
ISE_VERSION_LAST_SAVED_WITH
11.1
11.2

2
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.gui
View file

@ -11,7 +11,7 @@
<VARIABLE COL_INDEX="5" COL_WIDTH="227" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="127,724,323" VERSION="0"/>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="120,687,306" VERSION="0"/>
<STATUS>
<SELECTIONS/>
</STATUS>

4
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/system.xml
View file

@ -1,7 +1,7 @@
<EDKSYSTEM EDKVERSION="11.2" EDWVERSION="1.1" TIMESTAMP="Mon Jun 29 21:01:36 2009">
<EDKSYSTEM EDKVERSION="11.2" EDWVERSION="1.1" TIMESTAMP="Tue Jun 30 20:53:27 2009">
<SYSTEMINFO ARCH="virtex5" DEVICE="5vfx70t" PACKAGE="ff1136" PART="5vfx70tff1136-1" SOURCE="C:/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/" SPEEDGRADE="-1"/>
<SYSTEMINFO ARCH="virtex5" DEVICE="5vfx70t" PACKAGE="ff1136" PART="5vfx70tff1136-1" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
<PORT DIR="I" MHS_INDEX="0" NAME="fpga_0_RS232_Uart_1_RX_pin" SIGNAME="fpga_0_RS232_Uart_1_RX_pin"/>

32
Demo/PPC440_Xilinx_Virtex5_GCC/psf2Edward.log
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@ -1,28 +1,28 @@
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
Checking platform configuration ...
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
hs line 107 - 1 master(s) : 12 slave(s)
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
107 - 1 master(s) : 12 slave(s)
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
hs line 288 - 1 master(s) : 1 slave(s)
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
288 - 1 master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 446 - floating connection!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
446 - floating connection!
Performing Clock DRCs...
@ -39,7 +39,3 @@ Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING:EDK:494 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\synth
esis\ not found.
WARNING:EDK:2530 - Timing and Resource utilization information not added

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1
Demo/PPC440_Xilinx_Virtex5_GCC/system.make
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@ -245,6 +245,7 @@ $(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm
################## BEHAVIORAL SIMULATION ##################
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
$(WRAPPER_NGC_FILES) \
$(BRAMINIT_ELF_FILES)
@echo "*********************************************"
@echo "Creating behavioral simulation models..."

4
Demo/PPC440_Xilinx_Virtex5_GCC/system_incl.make
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@ -57,9 +57,9 @@ TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
MIX_LANG_SIM_OPT = -mixed yes
MIX_LANG_SIM_OPT = -mixed no
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -sd implementation/ -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/
LIBRARIES = \