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Ready the PPC440 projects for release.

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This commit is contained in:
Richard Barry 2009-07-05 08:41:27 +00:00
parent 3634ebb497
commit f42b1510fa
41 changed files with 16992 additions and 833 deletions
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32
Demo/PPC440_Xilinx_Virtex5_GCC/psf2Edward.log
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@ -1,28 +1,28 @@
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
Checking platform configuration ...
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
hs line 107 - 1 master(s) : 12 slave(s)
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
107 - 1 master(s) : 12 slave(s)
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
hs line 288 - 1 master(s) : 1 slave(s)
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
288 - 1 master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 446 - floating connection!
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
446 - floating connection!
Performing Clock DRCs...
@ -39,7 +39,3 @@ Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING:EDK:494 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\synth
esis\ not found.
WARNING:EDK:2530 - Timing and Resource utilization information not added