mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Update to the latest trace recorder library.
This commit is contained in:
Richard Barry
parent
9f84f353d0
commit
f289bfb388
34 changed files with 12882 additions and 6216 deletions
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@ -1,120 +1,59 @@
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/*******************************************************************************
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* Tracealyzer v3.0.2 Recorder Library
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* Trace Recorder Library for Tracealyzer v3.1.2
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* Percepio AB, www.percepio.com
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*
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* trcHardwarePort.h
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*
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* Contains together with trcHardwarePort.c all hardware portability issues of
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* the trace recorder library.
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* The hardware abstraction layer for the trace recorder.
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*
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* Terms of Use
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* This software is copyright Percepio AB. The recorder library is free for
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* use together with Percepio products. You may distribute the recorder library
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* in its original form, including modifications in trcPort.c and trcPort.h
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* given that these modification are clearly marked as your own modifications
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* and documented in the initial comment section of these source files.
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* This software is the intellectual property of Percepio AB and may not be
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* sold or in other ways commercially redistributed without explicit written
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* permission by Percepio AB.
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* This file is part of the trace recorder library (RECORDER), which is the
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* intellectual property of Percepio AB (PERCEPIO) and provided under a
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* license as follows.
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* The RECORDER may be used free of charge for the purpose of recording data
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* intended for analysis in PERCEPIO products. It may not be used or modified
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* for other purposes without explicit permission from PERCEPIO.
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* You may distribute the RECORDER in its original source code form, assuming
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* this text (terms of use, disclaimer, copyright notice) is unchanged. You are
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* allowed to distribute the RECORDER with minor modifications intended for
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* configuration or porting of the RECORDER, e.g., to allow using it on a
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* specific processor, processor family or with a specific communication
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* interface. Any such modifications should be documented directly below
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* this comment block.
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*
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* Disclaimer
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* The trace tool and recorder library is being delivered to you AS IS and
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* Percepio AB makes no warranty as to its use or performance. Percepio AB does
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* not and cannot warrant the performance or results you may obtain by using the
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* software or documentation. Percepio AB make no warranties, express or
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* implied, as to noninfringement of third party rights, merchantability, or
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* fitness for any particular purpose. In no event will Percepio AB, its
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* technology partners, or distributors be liable to you for any consequential,
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* incidental or special damages, including any lost profits or lost savings,
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* even if a representative of Percepio AB has been advised of the possibility
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||||
* of such damages, or for any claim by any third party. Some jurisdictions do
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* not allow the exclusion or limitation of incidental, consequential or special
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* damages, or the exclusion of implied warranties or limitations on how long an
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* implied warranty may last, so the above limitations may not apply to you.
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* The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty
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* as to its use or performance. PERCEPIO does not and cannot warrant the
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* performance or results you may obtain by using the RECORDER or documentation.
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* PERCEPIO make no warranties, express or implied, as to noninfringement of
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* third party rights, merchantability, or fitness for any particular purpose.
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* In no event will PERCEPIO, its technology partners, or distributors be liable
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* to you for any consequential, incidental or special damages, including any
|
||||
* lost profits or lost savings, even if a representative of PERCEPIO has been
|
||||
* advised of the possibility of such damages, or for any claim by any third
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* party. Some jurisdictions do not allow the exclusion or limitation of
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* incidental, consequential or special damages, or the exclusion of implied
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* warranties or limitations on how long an implied warranty may last, so the
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* above limitations may not apply to you.
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*
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* Tabs are used for indent in this file (1 tab = 4 spaces)
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*
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* Copyright Percepio AB, 2014.
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* Copyright Percepio AB, 2017.
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* www.percepio.com
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******************************************************************************/
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#ifndef TRCPORT_H
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#define TRCPORT_H
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#include <stdint.h>
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#ifndef TRC_HARDWARE_PORT_H
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#define TRC_HARDWARE_PORT_H
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/* If Win32 port */
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#ifdef WIN32
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#include "trcPortDefines.h"
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/* Standard includes. */
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#include <stdio.h>
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#include <windows.h>
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#include <direct.h>
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/*******************************************************************************
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* The Win32 port by default saves the trace to file and then kills the
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* program when the recorder is stopped, to facilitate quick, simple tests
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* of the recorder.
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******************************************************************************/
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#define WIN32_PORT_SAVE_WHEN_STOPPED 1
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#define WIN32_PORT_EXIT_WHEN_STOPPED 1
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#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
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#error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
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#endif
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#define DIRECTION_INCREMENTING 1
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#define DIRECTION_DECREMENTING 2
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/******************************************************************************
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* Supported ports
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*
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* PORT_HWIndependent
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* A hardware independent fallback option for event timestamping. Provides low
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* resolution timestamps based on the OS tick.
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* This may be used on the Win32 port, but may also be used on embedded hardware
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* platforms. All time durations will be truncated to the OS tick frequency,
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* typically 1 KHz. This means that a task or ISR that executes in less than
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* 1 ms get an execution time of zero.
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*
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* PORT_APPLICATION_DEFINED
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* Allows for defining the port macros in other source code files.
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*
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* PORT_Win32
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* "Accurate" timestamping based on the Windows performance counter for Win32
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* builds. Note that this gives the host machine time, not the kernel time.
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*
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* Hardware specific ports
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* To get accurate timestamping, a hardware timer is necessary. Below are the
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* available ports. Some of these are "unofficial", meaning that
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* they have not yet been verified by Percepio but have been contributed by
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* external developers. They should work, otherwise let us know by emailing
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* support@percepio.com. Some work on any OS platform, while other are specific
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* to a certain operating system.
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*****************************************************************************/
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/****** Port Name ********************** Code ***** Official ** OS Platform *********/
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#define PORT_APPLICATION_DEFINED -2 /* - - */
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#define PORT_NOT_SET -1 /* - - */
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#define PORT_HWIndependent 0 /* Yes Any */
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#define PORT_Win32 1 /* Yes FreeRTOS on Win32 */
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#define PORT_Atmel_AT91SAM7 2 /* No Any */
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#define PORT_Atmel_UC3A0 3 /* No Any */
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#define PORT_ARM_CortexM 4 /* Yes Any */
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#define PORT_Renesas_RX600 5 /* Yes Any */
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#define PORT_Microchip_dsPIC_AND_PIC24 6 /* Yes Any */
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#define PORT_TEXAS_INSTRUMENTS_TMS570 7 /* No Any */
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#define PORT_TEXAS_INSTRUMENTS_MSP430 8 /* No Any */
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#define PORT_MICROCHIP_PIC32MX 9 /* Yes Any */
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#define PORT_XILINX_PPC405 10 /* No FreeRTOS */
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#define PORT_XILINX_PPC440 11 /* No FreeRTOS */
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#define PORT_XILINX_MICROBLAZE 12 /* No Any */
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#define PORT_NXP_LPC210X 13 /* No Any */
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#define PORT_MICROCHIP_PIC32MZ 14 /* Yes Any */
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#define PORT_ARM_CORTEX_A9 15 /* No Any */
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#define PORT_ARM_CORTEX_M0 16 /* Yes Any */
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#include "trcConfig.h"
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/*******************************************************************************
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* IRQ_PRIORITY_ORDER
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* TRC_IRQ_PRIORITY_ORDER
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*
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* Macro which should be defined as an integer of 0 or 1.
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*
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@ -130,235 +69,265 @@
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*
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* HWTC Macros
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*
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* These four HWTC macros provides a hardware isolation layer representing a
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* generic hardware timer/counter used for driving the operating system tick,
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* such as the SysTick feature of ARM Cortex M3/M4, or the PIT of the Atmel
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* AT91SAM7X.
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* These macros provides a hardware isolation layer representing the
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* hardware timer/counter used for the event timestamping.
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*
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* HWTC_COUNT: The current value of the counter. This is expected to be reset
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* a each tick interrupt. Thus, when the tick handler starts, the counter has
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* already wrapped.
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* TRC_HWTC_COUNT: How to read the current value of the timer/counter.
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*
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* HWTC_COUNT_DIRECTION: Should be one of:
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* - DIRECTION_INCREMENTING - for hardware timer/counters of incrementing type
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* such as the PIT on Atmel AT91SAM7X.
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* When the counter value reach HWTC_PERIOD, it is reset to zero and the
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* interrupt is signaled.
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* - DIRECTION_DECREMENTING - for hardware timer/counters of decrementing type
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* such as the SysTick on ARM Cortex M3/M4 chips.
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* When the counter value reach 0, it is reset to HWTC_PERIOD and the
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* interrupt is signaled.
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* TRC_HWTC_TYPE: Tells the type of timer/counter used for TRC_HWTC_COUNT:
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*
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* HWTC_PERIOD: The number of increments or decrements of HWTC_COUNT between
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* two OS tick interrupts. This should preferably be mapped to the reload
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* register of the hardware timer, to make it more portable between chips in the
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* same family. The macro should in most cases be (reload register + 1).
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* For FreeRTOS, this can in most cases be defined as
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* #define HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ)
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* - TRC_FREE_RUNNING_32BIT_INCR:
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* Free-running 32-bit timer/counter, counting upwards from 0.
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*
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* HWTC_DIVISOR: If the timer frequency is very high, like on the Cortex M chips
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* (where the SysTick runs at the core clock frequency), the "differential
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* timestamping" used in the recorder will more frequently insert extra XTS
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* events to store the timestamps, which increases the event buffer usage.
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* In such cases, to reduce the number of XTS events and thereby get longer
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* traces, you use HWTC_DIVISOR to scale down the timestamps and frequency.
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* Assuming a OS tick rate of 1 KHz, it is suggested to keep the effective timer
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* frequency below 65 MHz to avoid an excessive amount of XTS events. Thus, a
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* Cortex M chip running at 72 MHZ should use a HWTC_DIVISOR of 2, while a
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* faster chip require a higher HWTC_DIVISOR value.
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* - TRC_FREE_RUNNING_32BIT_DECR
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* Free-running 32-bit timer/counter, counting downwards from 0xFFFFFFFF.
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*
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* The HWTC macros and vTracePortGetTimeStamp is the main porting issue
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* or the trace recorder library. Typically you should not need to change
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* the code of vTracePortGetTimeStamp if using the HWTC macros.
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* - TRC_OS_TIMER_INCR
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* Periodic timer that drives the OS tick interrupt, counting upwards
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* from 0 until (TRC_HWTC_PERIOD-1).
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*
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* - TRC_OS_TIMER_DECR
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* Periodic timer that drives the OS tick interrupt, counting downwards
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* from TRC_HWTC_PERIOD-1 until 0.
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*
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* - TRC_CUSTOM_TIMER_INCR
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* A custom timer or counter independent of the OS tick, counting
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* downwards from TRC_HWTC_PERIOD-1 until 0. (Currently only supported
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* in streaming mode).
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*
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* - TRC_CUSTOM_TIMER_DECR
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* A custom timer independent of the OS tick, counting downwards
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* from TRC_HWTC_PERIOD-1 until 0. (Currently only supported
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* in streaming mode).
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*
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* TRC_HWTC_PERIOD: The number of HWTC_COUNT ticks until the timer wraps
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* around. If using TRC_FREE_RUNNING_32BIT_INCR/DECR, this should be 0.
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*
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* TRC_HWTC_FREQ_HZ: The clock rate of the TRC_HWTC_COUNT counter in Hz. If using
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* TRC_OS_TIMER_INCR/DECR, this is should be TRC_HWTC_PERIOD * TRACE_TICK_RATE_HZ.
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* If using a free-running timer, this is often TRACE_CPU_CLOCK_HZ (if running at
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* the core clock rate). If using TRC_CUSTOM_TIMER_INCR/DECR, this should match
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* the clock rate of your custom timer (i.e., TRC_HWTC_COUNT). If the default value
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* of TRC_HWTC_FREQ_HZ is incorrect for your setup, you can override it by calling
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* vTraceSetFrequency before calling vTraceEnable.
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*
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* TRC_HWTC_DIVISOR (used in snapshot mode only):
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* In snapshot mode, the timestamp resolution is TRC_HWTC_FREQ_HZ/TRC_HWTC_DIVISOR.
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* If the timer frequency is very high (hundreds of MHz), we recommend increasing
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* the TRC_HWTC_DIVISOR prescaler, to reduce the bandwidth needed to store
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* timestamps. This since extra "XTS" events are inserted if the time since the
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* previous event exceeds a certain limit (255 or 65535 depending on event type).
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* It is advised to keep the time between most events below 65535 native ticks
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* (after division by TRC_HWTC_DIVISOR) to avoid frequent XTS events.
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******************************************************************************/
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#if (SELECTED_PORT == PORT_Win32)
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// This can be used as a template for any free-running 32-bit counter
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#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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#define HWTC_COUNT (ulGetRunTimeCounterValue())
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#define HWTC_PERIOD 0
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#define HWTC_DIVISOR 1
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#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
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#error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
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#endif
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// Please update according to your system...
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#define IRQ_PRIORITY_ORDER 1
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#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32)
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/* This can be used as a template for any free-running 32-bit counter */
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#define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
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#define TRC_HWTC_COUNT (ulGetRunTimeCounterValue())
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#define TRC_HWTC_PERIOD 0
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#define TRC_HWTC_DIVISOR 1
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#define TRC_HWTC_FREQ_HZ 100000
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#define TRC_IRQ_PRIORITY_ORDER 1
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#elif (SELECTED_PORT == PORT_HWIndependent)
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// OS Tick only (typically 1 ms resolution)
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#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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#define HWTC_COUNT 0
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#define HWTC_PERIOD 1
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#define HWTC_DIVISOR 1
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#define TRC_PORT_SPECIFIC_INIT()
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// Please update according to your system...
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#define IRQ_PRIORITY_ORDER NOT_SET
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#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent)
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/* Timestamping by OS tick only (typically 1 ms resolution) */
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#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
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#define TRC_HWTC_COUNT 0
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#define TRC_HWTC_PERIOD 1
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#define TRC_HWTC_DIVISOR 1
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#define TRC_HWTC_FREQ_HZ TRACE_TICK_RATE_HZ
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/* Set the meaning of IRQ priorities in ISR tracing - see above */
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#define TRC_IRQ_PRIORITY_ORDER NOT_SET
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#elif (SELECTED_PORT == PORT_ARM_CortexM)
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#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M)
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#ifndef __CORTEX_M
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#error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h"
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#endif
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void prvTraceInitCortexM(void);
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/**************************************************************************
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* For Cortex-M3, M4 and M7, the DWT cycle counter is used for timestamping.
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* For Cortex-M0 and M0+, the SysTick timer is used since DWT is not
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* available. Systick timestamping can also be forced on Cortex-M3, M4 and
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* M7 by defining the preprocessor directive TRC_CFG_ARM_CM_USE_SYSTICK,
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* either directly below or in trcConfig.h.
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*
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* #define TRC_CFG_ARM_CM_USE_SYSTICK
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**************************************************************************/
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#define REG_DEMCR (*(volatile unsigned int*)0xE000EDFC)
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#define REG_DWT_CTRL (*(volatile unsigned int*)0xE0001000)
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#define REG_DWT_CYCCNT (*(volatile unsigned int*)0xE0001004)
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#define REG_DWT_EXCCNT (*(volatile unsigned int*)0xE000100C)
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#if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK))
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void prvTraceInitCortexM(void);
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/* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */
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#define DEMCR_TRCENA (1 << 24)
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#define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC)
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#define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000)
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#define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004)
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#define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C)
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/* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */
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#define DWT_CTRL_NOPRFCNT (1 << 24)
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#define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0)
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#define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55)
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/* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */
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#define TRC_DEMCR_TRCENA (1 << 24)
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/* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */
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#define DWT_CTRL_NOCYCCNT (1 << 25)
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/* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */
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#define TRC_DWT_CTRL_NOPRFCNT (1 << 24)
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/* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */
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#define DWT_CTRL_EXCEVTENA (1 << 18)
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/* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */
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#define TRC_DWT_CTRL_NOCYCCNT (1 << 25)
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/* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */
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#define DWT_CTRL_CYCCNTENA (1)
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/* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */
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#define TRC_DWT_CTRL_EXCEVTENA (1 << 18)
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#define PORT_SPECIFIC_INIT() prvTraceInitCortexM()
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/* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */
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#define TRC_DWT_CTRL_CYCCNTENA (1)
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extern uint32_t DWT_CYCLES_ADDED;
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#define TRC_PORT_SPECIFIC_INIT() prvTraceInitCortexM()
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#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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#define HWTC_COUNT (REG_DWT_CYCCNT + DWT_CYCLES_ADDED)
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#define HWTC_PERIOD 0
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#define HWTC_DIVISOR 4
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#define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
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#define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT
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#define TRC_HWTC_PERIOD 0
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#define TRC_HWTC_DIVISOR 4
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#define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
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#define TRC_IRQ_PRIORITY_ORDER 0
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#else
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#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
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#define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018))
|
||||
#define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1)
|
||||
#define TRC_HWTC_DIVISOR 4
|
||||
#define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#endif
|
||||
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_ARM_CORTEX_M0)
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
|
||||
#define HWTC_COUNT (*((uint32_t*)0xE000E018))
|
||||
#define HWTC_PERIOD ((*(uint32_t*)0xE000E014) + 1)
|
||||
#define HWTC_DIVISOR 2
|
||||
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_Renesas_RX600)
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600)
|
||||
|
||||
#include "iodefine.h"
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT (CMT0.CMCNT)
|
||||
#define HWTC_PERIOD (CMT0.CMCOR + 1)
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
|
||||
#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
|
||||
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT (CMT0.CMCNT)
|
||||
|
||||
#elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)
|
||||
|
||||
/* Decreasing counters better for Tickless Idle? */
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
|
||||
#define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT)
|
||||
|
||||
#endif
|
||||
|
||||
#define TRC_HWTC_PERIOD (CMT0.CMCOR + 1)
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 1
|
||||
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32)
|
||||
|
||||
#elif ((SELECTED_PORT == PORT_MICROCHIP_PIC32MX) || (SELECTED_PORT == PORT_MICROCHIP_PIC32MZ))
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT (TMR1)
|
||||
#define TRC_HWTC_PERIOD (PR1 + 1)
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT (TMR1)
|
||||
#define HWTC_PERIOD (PR1 + 1)
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_Microchip_dsPIC_AND_PIC24)
|
||||
|
||||
/* For Microchip PIC24 and dsPIC (16 bit) */
|
||||
|
||||
/* Note: The trace library is designed for 32-bit MCUs and is slower than
|
||||
intended on 16-bit MCUs. Storing an event on a PIC24 takes about 70 usec.
|
||||
In comparison, this is 10-20 times faster on a 32-bit MCU... */
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT (TMR1)
|
||||
#define HWTC_PERIOD (PR1+1)
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_Atmel_AT91SAM7)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
|
||||
#define HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_Atmel_UC3A0)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
/* For Atmel AVR32 (AT32UC3A).*/
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
|
||||
#define HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_NXP_LPC210X)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
/* Tested with LPC2106, but should work with most LPC21XX chips. */
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT *((uint32_t *)0xE0004008 )
|
||||
#define HWTC_PERIOD *((uint32_t *)0xE0004018 )
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_TMS570)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48)
|
||||
|
||||
#define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)
|
||||
#define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)
|
||||
#define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
|
||||
#define HWTC_PERIOD (RTIUDCP0)
|
||||
#define HWTC_DIVISOR 1
|
||||
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
|
||||
#define TRC_HWTC_PERIOD (TRC_RTIUDCP0)
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_MSP430)
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
|
||||
#define HWTC_COUNT (TA0R)
|
||||
#define HWTC_PERIOD (((uint16_t)TACCR0)+1)
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
|
||||
#define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 1
|
||||
|
||||
#elif (SELECTED_PORT == PORT_XILINX_PPC405)
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO*/
|
||||
|
||||
/* For Atmel AVR32 (AT32UC3A) */
|
||||
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
|
||||
#define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 1
|
||||
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
|
||||
/* Tested with LPC2106, but should work with most LPC21XX chips. */
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
|
||||
#define HWTC_COUNT mfspr(0x3db)
|
||||
#if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS
|
||||
/* For FreeRTOS only - found no generic OS independent solution for the PPC405 architecture. */
|
||||
#define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC405
|
||||
#else
|
||||
/* Not defined for other operating systems yet */
|
||||
#error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.
|
||||
#endif
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 )
|
||||
#define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 )
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#elif (SELECTED_PORT == PORT_XILINX_PPC440)
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED */
|
||||
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
|
||||
#define TRC_HWTC_COUNT (TA0R)
|
||||
#define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1)
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 1
|
||||
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED */
|
||||
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
|
||||
#define TRC_HWTC_COUNT mfspr(0x3db)
|
||||
#define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ)
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440)
|
||||
|
||||
/* UNOFFICIAL PORT */
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
/* This should work with most PowerPC chips */
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
|
||||
#define HWTC_COUNT mfspr(0x016)
|
||||
#if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS
|
||||
/* For FreeRTOS only - found no generic OS independent solution for the PPC440 architecture. */
|
||||
#define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC440
|
||||
#else
|
||||
/* Not defined for other operating systems yet */
|
||||
#error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.
|
||||
#endif
|
||||
#define HWTC_DIVISOR 1
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
|
||||
#define TRC_HWTC_COUNT mfspr(0x016)
|
||||
#define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ)
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#elif (SELECTED_PORT == PORT_XILINX_MICROBLAZE)
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
|
||||
|
|
@ -367,101 +336,128 @@
|
|||
* If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required.
|
||||
*/
|
||||
#include "xtmrctr_l.h"
|
||||
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
|
||||
#define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
|
||||
#define TRC_HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
|
||||
#define TRC_HWTC_DIVISOR 16
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
|
||||
#define HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
|
||||
#define HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
|
||||
#define HWTC_DIVISOR 16
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)
|
||||
/* INPUT YOUR PERIPHERAL BASE ADDRESS HERE */
|
||||
#define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0xSOMETHING
|
||||
|
||||
#define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600
|
||||
#define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00))
|
||||
#define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04))
|
||||
#define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08))
|
||||
|
||||
#define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
|
||||
#define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
|
||||
#define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
|
||||
|
||||
#elif (SELECTED_PORT == PORT_ARM_CORTEX_A9)
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
|
||||
#define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG
|
||||
#define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1)
|
||||
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
/****************************************************************************************
|
||||
NOTE: The private timer ticks with a very high frequency (half the core-clock usually),
|
||||
depending on the prescaler used. If a low prescaler is used, the number of HW ticks between
|
||||
the trace events gets large, and thereby inefficient to store (sometimes extra events are
|
||||
needed). To improve efficiency, you may use the TRC_HWTC_DIVISOR as an additional prescaler.
|
||||
*****************************************************************************************/
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
|
||||
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
|
||||
#define TRC_IRQ_PRIORITY_ORDER 0
|
||||
|
||||
#define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
|
||||
#define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4)
|
||||
|
||||
#define CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(0xF8F00600 + 0))
|
||||
#define CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(0xF8F00600 + 4))
|
||||
#define CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(0xF8F00600 + 8))
|
||||
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
|
||||
|
||||
#define CA9_MPCORE_PRIVCTR_PRESCALER (((CA9_MPCORE_PRIVCTR_CONTROL_REG & CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
|
||||
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
|
||||
//#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
|
||||
#define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R // must be the PIT channel used for the systick
|
||||
#define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U) // TODO FIXME or maybe not -1? what's the right "period" value?
|
||||
#define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#define TRC_IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
|
||||
|
||||
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED)
|
||||
|
||||
#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
|
||||
#define HWTC_COUNT CA9_MPCORE_PRIVCTR_COUNTER_REG
|
||||
#define HWTC_PERIOD ((CA9_MPCORE_PRIVCTR_PERIOD_REG * CA9_MPCORE_PRIVCTR_PRESCALER) + 1)
|
||||
|
||||
//NOTE: The private timer ticks with a very high frequency (half the core-clock usually),
|
||||
//but offers the possibility to apply a prescaler. Depending on the prescaler you set the
|
||||
//HWTC_DIVISOR may need to be raised. Refer to the notes at the beginning of this file
|
||||
//for more information.
|
||||
#define HWTC_DIVISOR 1
|
||||
|
||||
#define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
|
||||
|
||||
#elif (SELECTED_PORT == PORT_APPLICATION_DEFINED)
|
||||
|
||||
#if !( defined (HWTC_COUNT_DIRECTION) && defined (HWTC_COUNT) && defined (HWTC_PERIOD) && defined (HWTC_DIVISOR) && defined (IRQ_PRIORITY_ORDER) )
|
||||
#error SELECTED_PORT is PORT_APPLICATION_DEFINED but not all of the necessary constants have been defined.
|
||||
#if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) )
|
||||
#error "The hardware port is not completely defined!"
|
||||
#endif
|
||||
|
||||
#elif (SELECTED_PORT != PORT_NOT_SET)
|
||||
#elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
|
||||
|
||||
#error "SELECTED_PORT had unsupported value!"
|
||||
#define SELECTED_PORT PORT_NOT_SET
|
||||
#error "TRC_CFG_HARDWARE_PORT had unsupported value!"
|
||||
#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET
|
||||
|
||||
#endif
|
||||
|
||||
#if (SELECTED_PORT != PORT_NOT_SET)
|
||||
#ifndef TRC_HWTC_DIVISOR
|
||||
#define TRC_HWTC_DIVISOR 1
|
||||
#endif
|
||||
|
||||
#ifndef HWTC_COUNT_DIRECTION
|
||||
#error "HWTC_COUNT_DIRECTION is not set!"
|
||||
#endif
|
||||
#ifndef TRC_PORT_SPECIFIC_INIT
|
||||
#define TRC_PORT_SPECIFIC_INIT()
|
||||
#endif
|
||||
|
||||
#ifndef HWTC_COUNT
|
||||
#error "HWTC_COUNT is not set!"
|
||||
#endif
|
||||
/* If Win32 port */
|
||||
#ifdef WIN32
|
||||
|
||||
#ifndef HWTC_PERIOD
|
||||
#error "HWTC_PERIOD is not set!"
|
||||
#endif
|
||||
#undef _WIN32_WINNT
|
||||
#define _WIN32_WINNT 0x0600
|
||||
|
||||
#ifndef HWTC_DIVISOR
|
||||
#error "HWTC_DIVISOR is not set!"
|
||||
#endif
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
#include <windows.h>
|
||||
#include <direct.h>
|
||||
|
||||
#ifndef IRQ_PRIORITY_ORDER
|
||||
#error "IRQ_PRIORITY_ORDER is not set!"
|
||||
#elif (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)
|
||||
#error "IRQ_PRIORITY_ORDER has bad value!"
|
||||
#endif
|
||||
|
||||
#if (HWTC_DIVISOR < 1)
|
||||
#error "HWTC_DIVISOR must be a non-zero positive value!"
|
||||
#endif
|
||||
/***************************************************************************
|
||||
* The Win32 port by default saves the trace to file and then kills the
|
||||
* program when the recorder is stopped, to facilitate quick, simple tests
|
||||
* of the recorder.
|
||||
***************************************************************************/
|
||||
#define WIN32_PORT_SAVE_WHEN_STOPPED 1
|
||||
#define WIN32_PORT_EXIT_WHEN_STOPPED 1
|
||||
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* vTraceConsoleMessage
|
||||
*
|
||||
* A wrapper for your system-specific console "printf" console output function.
|
||||
* This needs to be correctly defined to see status reports from the trace
|
||||
* status monitor task (this is defined in trcUser.c).
|
||||
******************************************************************************/
|
||||
#define vTraceConsoleMessage(x)
|
||||
|
||||
/*******************************************************************************
|
||||
* vTracePortGetTimeStamp
|
||||
*
|
||||
* Returns the current time based on the HWTC macros which provide a hardware
|
||||
* isolation layer towards the hardware timer/counter.
|
||||
*
|
||||
* The HWTC macros and vTracePortGetTimeStamp is the main porting issue
|
||||
* or the trace recorder library. Typically you should not need to change
|
||||
* the code of vTracePortGetTimeStamp if using the HWTC macros.
|
||||
*
|
||||
******************************************************************************/
|
||||
void vTracePortGetTimeStamp(uint32_t *puiTimestamp);
|
||||
#if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
|
||||
|
||||
#ifndef TRC_HWTC_TYPE
|
||||
#error "TRC_HWTC_TYPE is not set!"
|
||||
#endif
|
||||
|
||||
#ifndef TRC_HWTC_COUNT
|
||||
#error "TRC_HWTC_COUNT is not set!"
|
||||
#endif
|
||||
|
||||
#ifndef TRC_HWTC_PERIOD
|
||||
#error "TRC_HWTC_PERIOD is not set!"
|
||||
#endif
|
||||
|
||||
#ifndef TRC_HWTC_DIVISOR
|
||||
#error "TRC_HWTC_DIVISOR is not set!"
|
||||
#endif
|
||||
|
||||
#ifndef TRC_IRQ_PRIORITY_ORDER
|
||||
#error "TRC_IRQ_PRIORITY_ORDER is not set!"
|
||||
#elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1)
|
||||
#error "TRC_IRQ_PRIORITY_ORDER has bad value!"
|
||||
#endif
|
||||
|
||||
#if (TRC_HWTC_DIVISOR < 1)
|
||||
#error "TRC_HWTC_DIVISOR must be a non-zero positive value!"
|
||||
#endif
|
||||
|
||||
#ifndef TRC_HWTC_FREQ_HZ
|
||||
#error "TRC_HWTC_FREQ_HZ not defined!"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif /*TRC_SNAPSHOT_HARDWARE_PORT_H*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue