mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 21:41:59 -04:00
Starting point for XMC4500 IAR demo application.
This commit is contained in:
Richard Barry
parent
4793063ee0
commit
eff1636a94
152
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h
Normal file
152
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h
Normal file
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@ -0,0 +1,152 @@
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/*
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FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
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|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
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||||
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||||
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*
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* See http://www.freertos.org/a00110.html.
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*----------------------------------------------------------*/
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/* Ensure stdint is only used by the compiler, and not the assembler. */
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#ifdef __ICCARM__
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#include <stdint.h>
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extern uint32_t SystemCoreClock;
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#endif /* __ICCARM__ */
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configCPU_CLOCK_HZ ( SystemCoreClock )
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#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )
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#define configMAX_TASK_NAME_LEN ( 10 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 1
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#define configUSE_MUTEXES 1
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#define configQUEUE_REGISTRY_SIZE 8
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#define configUSE_RECURSIVE_MUTEXES 1
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#define configUSE_MALLOC_FAILED_HOOK 1
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#define configUSE_APPLICATION_TASK_TAG 0
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configGENERATE_RUN_TIME_STATS 0
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Software timer definitions. */
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#define configUSE_TIMERS 1
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#define configTIMER_TASK_PRIORITY ( 2 )
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#define configTIMER_QUEUE_LENGTH 5
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#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskCleanUpResources 1
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#define INCLUDE_vTaskSuspend 1
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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/* Cortex-M specific definitions. */
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#ifdef __NVIC_PRIO_BITS
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/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#else
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#define configPRIO_BITS 6 /* 63 priority levels */
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#endif
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/* The lowest interrupt priority that can be used in a call to a "set priority"
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function. */
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f
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/* The highest interrupt priority that can be used by any interrupt service
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routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
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INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
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PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
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/* Interrupt priorities used by the kernel port layer itself. These are generic
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to all Cortex-M ports, and do not rely on any particular library functions. */
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#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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/* Normal assert() semantics without relying on the provision of an assert.h
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header file. */
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#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
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/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
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standard names. */
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#define vPortSVCHandler SVC_Handler
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#define xPortPendSVHandler PendSV_Handler
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#define xPortSysTickHandler SysTick_Handler
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#endif /* FREERTOS_CONFIG_H */
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1957
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd
Normal file
1957
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd
Normal file
File diff suppressed because it is too large
Load diff
1919
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp
Normal file
1919
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp
Normal file
File diff suppressed because it is too large
Load diff
10
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.eww
Normal file
10
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.eww
Normal file
|
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@ -0,0 +1,10 @@
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<?xml version="1.0" encoding="iso-8859-1"?>
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<workspace>
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<project>
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<path>$WS_DIR$\RTOSDemo.ewp</path>
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</project>
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<batchBuild/>
|
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</workspace>
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|
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|
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502
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c
Normal file
502
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c
Normal file
|
|
@ -0,0 +1,502 @@
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|||
/*
|
||||
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
__asm vRegTest1Task( void )
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{
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PRESERVE8
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IMPORT ulRegTest1LoopCounter
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/* Fill the core registers with known values. */
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mov r0, #100
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mov r1, #101
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mov r2, #102
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mov r3, #103
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mov r4, #104
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mov r5, #105
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mov r6, #106
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mov r7, #107
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mov r8, #108
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mov r9, #109
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||||
mov r10, #110
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||||
mov r11, #111
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mov r12, #112
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||||
|
||||
/* Fill the VFP registers with known values. */
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||||
vmov d0, r0, r1
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||||
vmov d1, r2, r3
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||||
vmov d2, r4, r5
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||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
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||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
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||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg1_loop
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
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||||
push { r0-r1 }
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||||
|
||||
vmov r0, r1, d0
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cmp r0, #100
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bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg1_loopf_pass
|
||||
|
||||
reg1_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg1_error_loopf
|
||||
|
||||
reg1_loopf_pass
|
||||
|
||||
cmp r0, #100
|
||||
bne reg1_error_loop
|
||||
cmp r1, #101
|
||||
bne reg1_error_loop
|
||||
cmp r2, #102
|
||||
bne reg1_error_loop
|
||||
cmp r3, #103
|
||||
bne reg1_error_loop
|
||||
cmp r4, #104
|
||||
bne reg1_error_loop
|
||||
cmp r5, #105
|
||||
bne reg1_error_loop
|
||||
cmp r6, #106
|
||||
bne reg1_error_loop
|
||||
cmp r7, #107
|
||||
bne reg1_error_loop
|
||||
cmp r8, #108
|
||||
bne reg1_error_loop
|
||||
cmp r9, #109
|
||||
bne reg1_error_loop
|
||||
cmp r10, #110
|
||||
bne reg1_error_loop
|
||||
cmp r11, #111
|
||||
bne reg1_error_loop
|
||||
cmp r12, #112
|
||||
bne reg1_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest1LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg1_loop
|
||||
|
||||
reg1_error_loop
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg1_error_loop
|
||||
nop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm vRegTest2Task( void )
|
||||
{
|
||||
PRESERVE8
|
||||
IMPORT ulRegTest2LoopCounter
|
||||
|
||||
/* Set all the core registers to known values. */
|
||||
mov r0, #-1
|
||||
mov r1, #1
|
||||
mov r2, #2
|
||||
mov r3, #3
|
||||
mov r4, #4
|
||||
mov r5, #5
|
||||
mov r6, #6
|
||||
mov r7, #7
|
||||
mov r8, #8
|
||||
mov r9, #9
|
||||
mov r10, #10
|
||||
mov r11, #11
|
||||
mov r12, #12
|
||||
|
||||
/* Set all the VFP to known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg2_loop
|
||||
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg2_loopf_pass
|
||||
|
||||
reg2_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg2_error_loopf
|
||||
|
||||
reg2_loopf_pass
|
||||
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loop
|
||||
cmp r1, #1
|
||||
bne reg2_error_loop
|
||||
cmp r2, #2
|
||||
bne reg2_error_loop
|
||||
cmp r3, #3
|
||||
bne reg2_error_loop
|
||||
cmp r4, #4
|
||||
bne reg2_error_loop
|
||||
cmp r5, #5
|
||||
bne reg2_error_loop
|
||||
cmp r6, #6
|
||||
bne reg2_error_loop
|
||||
cmp r7, #7
|
||||
bne reg2_error_loop
|
||||
cmp r8, #8
|
||||
bne reg2_error_loop
|
||||
cmp r9, #9
|
||||
bne reg2_error_loop
|
||||
cmp r10, #10
|
||||
bne reg2_error_loop
|
||||
cmp r11, #11
|
||||
bne reg2_error_loop
|
||||
cmp r12, #12
|
||||
bne reg2_error_loop
|
||||
|
||||
/* Increment the loop counter to indicate this test is still functioning
|
||||
correctly. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest2LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg2_loop
|
||||
|
||||
reg2_error_loop
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
This loop ensures the loop counter variable stops incrementing. */
|
||||
b reg2_error_loop
|
||||
nop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
|
||||
{
|
||||
PRESERVE8
|
||||
|
||||
/* Clobber the auto saved registers. */
|
||||
vmov d0, r0, r0
|
||||
vmov d1, r0, r0
|
||||
vmov d2, r0, r0
|
||||
vmov d3, r0, r0
|
||||
vmov d4, r0, r0
|
||||
vmov d5, r0, r0
|
||||
vmov d6, r0, r0
|
||||
vmov d7, r0, r0
|
||||
bx lr
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
|
||||
{
|
||||
PRESERVE8
|
||||
|
||||
vmov r1, s0
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s1
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s2
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s3
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s4
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s5
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s6
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s7
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s8
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s9
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s10
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s11
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s12
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s13
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s14
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s15
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
|
||||
return_pass
|
||||
mov r0, #1
|
||||
bx lr
|
||||
|
||||
return_error
|
||||
mov r0, #0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
506
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s
Normal file
506
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s
Normal file
|
|
@ -0,0 +1,506 @@
|
|||
/*
|
||||
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
#include <FreeRTOSConfig.h>
|
||||
|
||||
|
||||
RSEG CODE:CODE(2)
|
||||
thumb
|
||||
|
||||
EXTERN ulRegTest1LoopCounter
|
||||
EXTERN ulRegTest2LoopCounter
|
||||
|
||||
PUBLIC vRegTest1Task
|
||||
PUBLIC vRegTest2Task
|
||||
PUBLIC vRegTestClearFlopRegistersToParameterValue
|
||||
PUBLIC ulRegTestCheckFlopRegistersContainParameterValue
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vRegTest1Task
|
||||
|
||||
/* Fill the core registers with known values. */
|
||||
mov r0, #100
|
||||
mov r1, #101
|
||||
mov r2, #102
|
||||
mov r3, #103
|
||||
mov r4, #104
|
||||
mov r5, #105
|
||||
mov r6, #106
|
||||
mov r7, #107
|
||||
mov r8, #108
|
||||
mov r9, #109
|
||||
mov r10, #110
|
||||
mov r11, #111
|
||||
mov r12, #112
|
||||
|
||||
/* Fill the VFP registers with known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg1_loop:
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg1_loopf_pass
|
||||
|
||||
reg1_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg1_error_loopf
|
||||
|
||||
reg1_loopf_pass
|
||||
|
||||
cmp r0, #100
|
||||
bne reg1_error_loop
|
||||
cmp r1, #101
|
||||
bne reg1_error_loop
|
||||
cmp r2, #102
|
||||
bne reg1_error_loop
|
||||
cmp r3, #103
|
||||
bne reg1_error_loop
|
||||
cmp r4, #104
|
||||
bne reg1_error_loop
|
||||
cmp r5, #105
|
||||
bne reg1_error_loop
|
||||
cmp r6, #106
|
||||
bne reg1_error_loop
|
||||
cmp r7, #107
|
||||
bne reg1_error_loop
|
||||
cmp r8, #108
|
||||
bne reg1_error_loop
|
||||
cmp r9, #109
|
||||
bne reg1_error_loop
|
||||
cmp r10, #110
|
||||
bne reg1_error_loop
|
||||
cmp r11, #111
|
||||
bne reg1_error_loop
|
||||
cmp r12, #112
|
||||
bne reg1_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest1LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg1_loop
|
||||
|
||||
reg1_error_loop:
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg1_error_loop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
vRegTest2Task
|
||||
|
||||
/* Set all the core registers to known values. */
|
||||
mov r0, #-1
|
||||
mov r1, #1
|
||||
mov r2, #2
|
||||
mov r3, #3
|
||||
mov r4, #4
|
||||
mov r5, #5
|
||||
mov r6, #6
|
||||
mov r7, #7
|
||||
mov r8, #8
|
||||
mov r9, #9
|
||||
mov r10, #10
|
||||
mov r11, #11
|
||||
mov r12, #12
|
||||
|
||||
/* Set all the VFP to known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg2_loop:
|
||||
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg2_loopf_pass
|
||||
|
||||
reg2_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg2_error_loopf
|
||||
|
||||
reg2_loopf_pass
|
||||
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loop
|
||||
cmp r1, #1
|
||||
bne reg2_error_loop
|
||||
cmp r2, #2
|
||||
bne reg2_error_loop
|
||||
cmp r3, #3
|
||||
bne reg2_error_loop
|
||||
cmp r4, #4
|
||||
bne reg2_error_loop
|
||||
cmp r5, #5
|
||||
bne reg2_error_loop
|
||||
cmp r6, #6
|
||||
bne reg2_error_loop
|
||||
cmp r7, #7
|
||||
bne reg2_error_loop
|
||||
cmp r8, #8
|
||||
bne reg2_error_loop
|
||||
cmp r9, #9
|
||||
bne reg2_error_loop
|
||||
cmp r10, #10
|
||||
bne reg2_error_loop
|
||||
cmp r11, #11
|
||||
bne reg2_error_loop
|
||||
cmp r12, #12
|
||||
bne reg2_error_loop
|
||||
|
||||
/* Increment the loop counter to indicate this test is still functioning
|
||||
correctly. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest2LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg2_loop
|
||||
|
||||
reg2_error_loop:
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
This loop ensures the loop counter variable stops incrementing. */
|
||||
b reg2_error_loop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vRegTestClearFlopRegistersToParameterValue
|
||||
|
||||
/* Clobber the auto saved registers. */
|
||||
vmov d0, r0, r0
|
||||
vmov d1, r0, r0
|
||||
vmov d2, r0, r0
|
||||
vmov d3, r0, r0
|
||||
vmov d4, r0, r0
|
||||
vmov d5, r0, r0
|
||||
vmov d6, r0, r0
|
||||
vmov d7, r0, r0
|
||||
bx lr
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
ulRegTestCheckFlopRegistersContainParameterValue
|
||||
|
||||
vmov r1, s0
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s1
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s2
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s3
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s4
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s5
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s6
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s7
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s8
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s9
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s10
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s11
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s12
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s13
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s14
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
vmov r1, s15
|
||||
cmp r0, r1
|
||||
bne return_error
|
||||
|
||||
return_pass
|
||||
mov r0, #1
|
||||
bx lr
|
||||
|
||||
return_error
|
||||
mov r0, #0
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
||||
41
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/XMC4500_Flash.icf
Normal file
41
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/XMC4500_Flash.icf
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __DRAM1_start__ = 0x20000000;
|
||||
define symbol __DRAM1_end__ = 0x20007FFF;
|
||||
|
||||
define symbol __DRAM2_start__ = 0x30000000;
|
||||
define symbol __DRAM2_end__ = 0x30007FFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region DRAM1_region = mem:[from __DRAM1_start__ to __DRAM1_end__];
|
||||
define region DRAM2_region = mem:[from __DRAM2_start__ to __DRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region {readonly};
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in DRAM1_region{ section .dram1};
|
||||
place in DRAM2_region{ section .dram2};
|
||||
|
||||
223
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c
Normal file
223
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* This project provides two demo applications. A simple blinky style project,
|
||||
* and a more comprehensive test and demo application. The
|
||||
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
|
||||
* select between the two. The simply blinky demo is implemented and described
|
||||
* in main_blinky.c. The more comprehensive test and demo application is
|
||||
* implemented and described in main_full.c.
|
||||
*
|
||||
* This file implements the code that is not demo specific, including the
|
||||
* hardware setup and FreeRTOS hook functions.
|
||||
*
|
||||
*
|
||||
* Additional code:
|
||||
*
|
||||
* This demo does not contain a non-kernel interrupt service routine that
|
||||
* can be used as an example for application writers to use as a reference.
|
||||
* Therefore, the framework of a dummy (not installed) handler is provided
|
||||
* in this file. The dummy function is called Dummy_IRQHandler(). Please
|
||||
* ensure to read the comments in the function itself, but more importantly,
|
||||
* the notes on the function contained on the documentation page for this demo
|
||||
* that is found on the FreeRTOS.org web site.
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Hardware includes. */
|
||||
#include "XMC4500.h"
|
||||
#include "System_XMC4500.h"
|
||||
|
||||
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
|
||||
or 0 to run the more comprehensive test and demo application. */
|
||||
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Set up the hardware ready to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*
|
||||
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
|
||||
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
|
||||
*/
|
||||
extern void main_blinky( void );
|
||||
extern void main_full( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main( void )
|
||||
{
|
||||
/* Prepare the hardware to run this demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
|
||||
of this file. */
|
||||
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
|
||||
{
|
||||
main_blinky();
|
||||
}
|
||||
#else
|
||||
{
|
||||
main_full();
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
extern void SystemCoreClockUpdate( void );
|
||||
|
||||
/* Ensure SystemCoreClock variable is set. */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Configure pin P3.9 for the LED. */
|
||||
PORT3->IOCR8 = 0x00008000;
|
||||
|
||||
/* Ensure all priority bits are assigned as preemption priority bits. */
|
||||
NVIC_SetPriorityGrouping( 0 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook( void )
|
||||
{
|
||||
/* vApplicationMallocFailedHook() will only be called if
|
||||
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
|
||||
function that will get called if a call to pvPortMalloc() fails.
|
||||
pvPortMalloc() is called internally by the kernel whenever a task, queue,
|
||||
timer or semaphore is created. It is also called by various parts of the
|
||||
demo application. If heap_1.c or heap_2.c are used, then the size of the
|
||||
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
|
||||
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
|
||||
to query the size of free heap space that remains (although it does not
|
||||
provide information on how the remaining heap might be fragmented). */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
|
||||
to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
|
||||
task. It is essential that code added to this hook function never attempts
|
||||
to block in any way (for example, call xQueueReceive() with a block time
|
||||
specified, or call vTaskDelay()). If the application makes use of the
|
||||
vTaskDelete() API function (as this demo application does) then it is also
|
||||
important that vApplicationIdleHook() is permitted to return to its calling
|
||||
function, because it is the responsibility of the idle task to clean up
|
||||
memory allocated by the kernel to any task that has since been deleted. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
|
||||
{
|
||||
( void ) pcTaskName;
|
||||
( void ) pxTask;
|
||||
|
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
/* This function will be called by each tick interrupt if
|
||||
configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
|
||||
added here, but the tick hook is called from an interrupt context, so
|
||||
code must not attempt to block, and only the interrupt safe FreeRTOS API
|
||||
functions can be used (those that end in FromISR()). */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef JUST_AN_EXAMPLE_ISR
|
||||
|
||||
void Dummy_IRQHandler(void)
|
||||
{
|
||||
long lHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
/* Clear the interrupt if necessary. */
|
||||
Dummy_ClearITPendingBit();
|
||||
|
||||
/* This interrupt does nothing more than demonstrate how to synchronise a
|
||||
task with an interrupt. A semaphore is used for this purpose. Note
|
||||
lHigherPriorityTaskWoken is initialised to zero. */
|
||||
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
|
||||
|
||||
/* If there was a task that was blocked on the semaphore, and giving the
|
||||
semaphore caused the task to unblock, and the unblocked task has a priority
|
||||
higher than the current Running state task (the task that this interrupt
|
||||
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
|
||||
internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the
|
||||
portEND_SWITCHING_ISR() macro will result in a context switch being pended to
|
||||
ensure this interrupt returns directly to the unblocked, higher priority,
|
||||
task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
|
||||
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
|
||||
}
|
||||
|
||||
#endif /* JUST_AN_EXAMPLE_ISR */
|
||||
233
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c
Normal file
233
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c
Normal file
|
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* NOTE 1: This project provides two demo applications. A simple blinky style
|
||||
* project, and a more comprehensive test and demo application. The
|
||||
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
|
||||
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
|
||||
* in main.c. This file implements the simply blinky style version.
|
||||
*
|
||||
* NOTE 2: This file only contains the source code that is specific to the
|
||||
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
|
||||
* required to configure the hardware, are defined in main.c.
|
||||
******************************************************************************
|
||||
*
|
||||
* main_blinky() creates one queue, and two tasks. It then starts the
|
||||
* scheduler.
|
||||
*
|
||||
* The Queue Send Task:
|
||||
* The queue send task is implemented by the prvQueueSendTask() function in
|
||||
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
|
||||
* block for 200 milliseconds, before sending the value 100 to the queue that
|
||||
* was created within main_blinky(). Once the value is sent, the task loops
|
||||
* back around to block for another 200 milliseconds.
|
||||
*
|
||||
* The Queue Receive Task:
|
||||
* The queue receive task is implemented by the prvQueueReceiveTask() function
|
||||
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
|
||||
* blocks on attempts to read data from the queue that was created within
|
||||
* main_blinky(). When data is received, the task checks the value of the
|
||||
* data, and if the value equals the expected 100, toggles the LED. The 'block
|
||||
* time' parameter passed to the queue receive function specifies that the
|
||||
* task should be held in the Blocked state indefinitely to wait for data to
|
||||
* be available on the queue. The queue receive task will only leave the
|
||||
* Blocked state when the queue send task writes to the queue. As the queue
|
||||
* send task writes to the queue every 200 milliseconds, the queue receive
|
||||
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
|
||||
* the LED every 200 milliseconds.
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Hardware includes. */
|
||||
#include "XMC4500.h"
|
||||
#include "System_XMC4500.h"
|
||||
|
||||
/* Priorities at which the tasks are created. */
|
||||
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
|
||||
|
||||
/* The rate at which data is sent to the queue. The 200ms value is converted
|
||||
to ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
|
||||
|
||||
/* The number of items the queue can hold. This is 1 as the receive task
|
||||
will remove items as they are added, meaning the send task should always find
|
||||
the queue empty. */
|
||||
#define mainQUEUE_LENGTH ( 1 )
|
||||
|
||||
/* Values passed to the two tasks just to check the task parameter
|
||||
functionality. */
|
||||
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
|
||||
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
|
||||
|
||||
/* To toggle the single LED */
|
||||
#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The tasks as described in the comments at the top of this file.
|
||||
*/
|
||||
static void prvQueueReceiveTask( void *pvParameters );
|
||||
static void prvQueueSendTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* Called by main() to create the simply blinky style application if
|
||||
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
|
||||
*/
|
||||
void main_blinky( void );
|
||||
|
||||
/*
|
||||
* The hardware only has a single LED. Simply toggle it.
|
||||
*/
|
||||
extern void vMainToggleLED( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The queue used by both tasks. */
|
||||
static xQueueHandle xQueue = NULL;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void main_blinky( void )
|
||||
{
|
||||
/* Create the queue. */
|
||||
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
|
||||
|
||||
if( xQueue != NULL )
|
||||
{
|
||||
/* Start the two tasks as described in the comments at the top of this
|
||||
file. */
|
||||
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
|
||||
( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
|
||||
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
|
||||
( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
|
||||
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
|
||||
NULL ); /* The task handle is not required, so NULL is passed. */
|
||||
|
||||
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
|
||||
|
||||
/* Start the tasks and timer running. */
|
||||
vTaskStartScheduler();
|
||||
}
|
||||
|
||||
/* If all is well, the scheduler will now be running, and the following
|
||||
line will never be reached. If the following line does execute, then
|
||||
there was insufficient FreeRTOS heap memory available for the idle and/or
|
||||
timer tasks to be created. See the memory management section on the
|
||||
FreeRTOS web site for more details. */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvQueueSendTask( void *pvParameters )
|
||||
{
|
||||
portTickType xNextWakeTime;
|
||||
const unsigned long ulValueToSend = 100UL;
|
||||
|
||||
/* Check the task parameter is as expected. */
|
||||
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
|
||||
|
||||
/* Initialise xNextWakeTime - this only needs to be done once. */
|
||||
xNextWakeTime = xTaskGetTickCount();
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Place this task in the blocked state until it is time to run again.
|
||||
The block time is specified in ticks, the constant used converts ticks
|
||||
to ms. While in the Blocked state this task will not consume any CPU
|
||||
time. */
|
||||
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
|
||||
|
||||
/* Send to the queue - causing the queue receive task to unblock and
|
||||
toggle the LED. 0 is used as the block time so the sending operation
|
||||
will not block - it shouldn't need to block as the queue should always
|
||||
be empty at this point in the code. */
|
||||
xQueueSend( xQueue, &ulValueToSend, 0U );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvQueueReceiveTask( void *pvParameters )
|
||||
{
|
||||
unsigned long ulReceivedValue;
|
||||
|
||||
/* Check the task parameter is as expected. */
|
||||
configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait until something arrives in the queue - this task will block
|
||||
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
|
||||
FreeRTOSConfig.h. */
|
||||
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
|
||||
|
||||
/* To get here something must have been received from the queue, but
|
||||
is it the expected value? If it is, toggle the LED. */
|
||||
if( ulReceivedValue == 100UL )
|
||||
{
|
||||
mainTOGGLE_LED();
|
||||
ulReceivedValue = 0U;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
318
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c
Normal file
318
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c
Normal file
|
|
@ -0,0 +1,318 @@
|
|||
/*
|
||||
FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
* Complete, revised, and edited pdf reference manuals are also *
|
||||
* available. *
|
||||
* *
|
||||
* Purchasing FreeRTOS documentation will not only help you, by *
|
||||
* ensuring you get running as quickly as possible and with an *
|
||||
* in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
* the FreeRTOS project to continue with its mission of providing *
|
||||
* professional grade, cross platform, de facto standard solutions *
|
||||
* for microcontrollers - completely free of charge! *
|
||||
* *
|
||||
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
* *
|
||||
* Thank you for using FreeRTOS, and thank you for your support! *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
>>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
distribute a combined work that includes FreeRTOS without being obliged to
|
||||
provide the source code for proprietary components outside of the FreeRTOS
|
||||
kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details. You should have received a copy of the GNU General Public
|
||||
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
by writing to Richard Barry, contact details for whom are available on the
|
||||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* NOTE 1: This project provides two demo applications. A simple blinky style
|
||||
* project, and a more comprehensive test and demo application. The
|
||||
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
|
||||
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
|
||||
* in main.c. This file implements the comprehensive test and demo version.
|
||||
*
|
||||
* NOTE 2: This file only contains the source code that is specific to the
|
||||
* full demo. Generic functions, such FreeRTOS hook functions, and functions
|
||||
* required to configure the hardware, are defined in main.c.
|
||||
******************************************************************************
|
||||
*
|
||||
* main_full() creates all the demo application tasks and a software timer, then
|
||||
* starts the scheduler. The web documentation provides more details of the
|
||||
* standard demo application tasks, which provide no particular functionality,
|
||||
* but do provide a good example of how to use the FreeRTOS API.
|
||||
*
|
||||
* In addition to the standard demo tasks, the following tasks and tests are
|
||||
* defined and/or created within this file:
|
||||
*
|
||||
* "Reg test" tasks - These fill both the core and floating point registers with
|
||||
* known values, then check that each register maintains its expected value for
|
||||
* the lifetime of the task. Each task uses a different set of values. The reg
|
||||
* test tasks execute with a very low priority, so get preempted very
|
||||
* frequently. A register containing an unexpected value is indicative of an
|
||||
* error in the context switching mechanism.
|
||||
*
|
||||
* "Check" timer - The check software timer period is initially set to three
|
||||
* seconds. The callback function associated with the check software timer
|
||||
* checks that all the standard demo tasks, and the register check tasks, are
|
||||
* not only still executing, but are executing without reporting any errors. If
|
||||
* the check software timer discovers that a task has either stalled, or
|
||||
* reported an error, then it changes its own execution period from the initial
|
||||
* three seconds, to just 200ms. The check software timer callback function
|
||||
* also toggles the single LED each time it is called. This provides a visual
|
||||
* indication of the system status: If the LED toggles every three seconds,
|
||||
* then no issues have been discovered. If the LED toggles every 200ms, then
|
||||
* an issue has been discovered with at least one task.
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "timers.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Standard demo application includes. */
|
||||
#include "flop.h"
|
||||
#include "integer.h"
|
||||
#include "PollQ.h"
|
||||
#include "semtest.h"
|
||||
#include "dynamic.h"
|
||||
#include "BlockQ.h"
|
||||
#include "blocktim.h"
|
||||
#include "countsem.h"
|
||||
#include "GenQTest.h"
|
||||
#include "recmutex.h"
|
||||
#include "death.h"
|
||||
|
||||
/* Hardware includes. */
|
||||
#include "XMC4500.h"
|
||||
#include "System_XMC4500.h"
|
||||
|
||||
/* Priorities for the demo application tasks. */
|
||||
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
|
||||
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
|
||||
|
||||
/* To toggle the single LED */
|
||||
#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )
|
||||
|
||||
/* A block time of zero simply means "don't block". */
|
||||
#define mainDONT_BLOCK ( 0UL )
|
||||
|
||||
/* The period after which the check timer will expire, in ms, provided no errors
|
||||
have been reported by any of the standard demo tasks. ms are converted to the
|
||||
equivalent in ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
|
||||
|
||||
/* The period at which the check timer will expire, in ms, if an error has been
|
||||
reported in one of the standard demo tasks. ms are converted to the equivalent
|
||||
in ticks using the portTICK_RATE_MS constant. */
|
||||
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The check timer callback function, as described at the top of this file.
|
||||
*/
|
||||
static void prvCheckTimerCallback( xTimerHandle xTimer );
|
||||
|
||||
/*
|
||||
* Register check tasks, and the tasks used to write over and check the contents
|
||||
* of the FPU registers, as described at the top of this file. The nature of
|
||||
* these files necessitates that they are written in an assembly file.
|
||||
*/
|
||||
extern void vRegTest1Task( void *pvParameters );
|
||||
extern void vRegTest2Task( void *pvParameters );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The following two variables are used to communicate the status of the
|
||||
register check tasks to the check software timer. If the variables keep
|
||||
incrementing, then the register check tasks has not discovered any errors. If
|
||||
a variable stops incrementing, then an error has been found. */
|
||||
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void main_full( void )
|
||||
{
|
||||
xTimerHandle xCheckTimer = NULL;
|
||||
|
||||
/* Start all the other standard demo/test tasks. The have not particular
|
||||
functionality, but do demonstrate how to use the FreeRTOS API and test the
|
||||
kernel port. */
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vCreateBlockTimeTasks();
|
||||
vStartCountingSemaphoreTasks();
|
||||
vStartGenericQueueTasks( tskIDLE_PRIORITY );
|
||||
vStartRecursiveMutexTasks();
|
||||
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
vStartMathTasks( mainFLOP_TASK_PRIORITY );
|
||||
|
||||
/* Create the register check tasks, as described at the top of this
|
||||
file */
|
||||
xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
|
||||
|
||||
/* Create the software timer that performs the 'check' functionality,
|
||||
as described at the top of this file. */
|
||||
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
|
||||
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
|
||||
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
|
||||
( void * ) 0, /* The ID is not used, so can be set to anything. */
|
||||
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
|
||||
);
|
||||
|
||||
if( xCheckTimer != NULL )
|
||||
{
|
||||
xTimerStart( xCheckTimer, mainDONT_BLOCK );
|
||||
}
|
||||
|
||||
/* The set of tasks created by the following function call have to be
|
||||
created last as they keep account of the number of tasks they expect to see
|
||||
running. */
|
||||
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
|
||||
|
||||
/* Start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* If all is well, the scheduler will now be running, and the following line
|
||||
will never be reached. If the following line does execute, then there was
|
||||
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
|
||||
to be created. See the memory management section on the FreeRTOS web site
|
||||
for more details. */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckTimerCallback( xTimerHandle xTimer )
|
||||
{
|
||||
static long lChangedTimerPeriodAlready = pdFALSE;
|
||||
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
|
||||
unsigned long ulErrorFound = pdFALSE;
|
||||
|
||||
/* Check all the demo tasks (other than the flash tasks) to ensure
|
||||
that they are all still running, and that none have detected an error. */
|
||||
|
||||
if( xAreMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xIsCreateTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xArePollingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
|
||||
/* Check that the register test 1 task is still running. */
|
||||
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
ulLastRegTest1Value = ulRegTest1LoopCounter;
|
||||
|
||||
/* Check that the register test 2 task is still running. */
|
||||
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
|
||||
{
|
||||
ulErrorFound = pdTRUE;
|
||||
}
|
||||
ulLastRegTest2Value = ulRegTest2LoopCounter;
|
||||
|
||||
/* Toggle the check LED to give an indication of the system status. If
|
||||
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
|
||||
everything is ok. A faster toggle indicates an error. */
|
||||
mainTOGGLE_LED();
|
||||
|
||||
/* Have any errors been latch in ulErrorFound? If so, shorten the
|
||||
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
|
||||
This will result in an increase in the rate at which mainCHECK_LED
|
||||
toggles. */
|
||||
if( ulErrorFound != pdFALSE )
|
||||
{
|
||||
if( lChangedTimerPeriodAlready == pdFALSE )
|
||||
{
|
||||
lChangedTimerPeriodAlready = pdTRUE;
|
||||
|
||||
/* This call to xTimerChangePeriod() uses a zero block time.
|
||||
Functions called from inside of a timer callback function must
|
||||
*never* attempt to block. */
|
||||
xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -0,0 +1,412 @@
|
|||
/******************************************************************************
|
||||
* @file system_XMC4500.c
|
||||
* @brief Device specific initialization for the XMC4500-Series according to CMSIS
|
||||
* @version V2.2
|
||||
* @date 20. January 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
|
||||
|
||||
*
|
||||
* @par
|
||||
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
|
||||
* This file can be freely distributed within development tools that are supporting such microcontrollers.
|
||||
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "System_XMC4500.h"
|
||||
#include <XMC4500.h>
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks is located in System_XMC4500.h
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/*!< System Clock Frequency (Core Clock)*/
|
||||
uint32_t SystemCoreClock = CLOCK_OSC_HP;
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*--------------------- Watchdog Configuration -------------------------------
|
||||
//
|
||||
// <e> Watchdog Configuration
|
||||
// <o1.0> Disable Watchdog
|
||||
//
|
||||
// </e>
|
||||
*/
|
||||
#define WDT_SETUP 1
|
||||
#define WDTENB_nVal 0x00000001
|
||||
|
||||
/*--------------------- CLOCK Configuration -------------------------------
|
||||
//
|
||||
// <e> Main Clock Configuration
|
||||
// <o1.0..1> CPU clock divider
|
||||
// <0=> fCPU = fSYS
|
||||
// <1=> fCPU = fSYS / 2
|
||||
// <o2.0..1> Peripheral Bus clock divider
|
||||
// <0=> fPB = fCPU
|
||||
// <1=> fPB = fCPU / 2
|
||||
// <o3.0..1> CCU Bus clock divider
|
||||
// <0=> fCCU = fCPU
|
||||
// <1=> fCCU = fCPU / 2
|
||||
//
|
||||
// </e>
|
||||
//
|
||||
*/
|
||||
|
||||
#define SCU_CLOCK_SETUP 1
|
||||
#define SCU_CPUCLKCR_DIV 0x00000000
|
||||
#define SCU_PBCLKCR_DIV 0x00000000
|
||||
#define SCU_CCUCLKCR_DIV 0x00000000
|
||||
|
||||
|
||||
|
||||
/*--------------------- USB CLOCK Configuration ---------------------------
|
||||
//
|
||||
// <e> USB Clock Configuration
|
||||
//
|
||||
// </e>
|
||||
//
|
||||
*/
|
||||
|
||||
#define SCU_USB_CLOCK_SETUP 0
|
||||
|
||||
|
||||
/*--------------------- CLOCKOUT Configuration -------------------------------
|
||||
//
|
||||
// <e> Clock OUT Configuration
|
||||
// <o1.0..1> Clockout Source Selection
|
||||
// <0=> System Clock
|
||||
// <2=> USB Clock
|
||||
// <3=> Divided value of PLL Clock
|
||||
// <o2.0..1> Clockout Pin Selection
|
||||
// <0=> P1.15
|
||||
// <1=> P0.8
|
||||
//
|
||||
//
|
||||
// </e>
|
||||
//
|
||||
*/
|
||||
|
||||
#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled
|
||||
#define SCU_CLOCKOUT_SOURCE 0x00000000
|
||||
#define SCU_CLOCKOUT_PIN 0x00000000
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
static functions declarations
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (SCU_CLOCK_SETUP == 1)
|
||||
static int SystemClockSetup(void);
|
||||
#endif
|
||||
|
||||
#if (SCU_USB_CLOCK_SETUP == 1)
|
||||
static void USBClockSetup(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the PLL and update the
|
||||
* SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Setup the WDT */
|
||||
#if (WDT_SETUP == 1)
|
||||
WDT->CTR &= ~WDTENB_nVal;
|
||||
#endif
|
||||
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Disable branch prediction - PCON.PBS = 1 */
|
||||
PREF->PCON |= (PREF_PCON_PBS_Msk);
|
||||
|
||||
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
|
||||
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
|
||||
|
||||
/* Setup the clockout */
|
||||
/* README README README README README README README README README README */
|
||||
/*
|
||||
* Please use the CLOCKOUT feature with diligence. Use this only if you know
|
||||
* what you are doing.
|
||||
*
|
||||
* You must be aware that the settings below can potentially be in conflict
|
||||
* with DAVE code generation engine preferences.
|
||||
*
|
||||
* Even worse, the setting below configures the ports as output ports while in
|
||||
* reality, the board on which this chip is mounted may have a source driving
|
||||
* the ports.
|
||||
*
|
||||
* So use this feature only when you are absolutely sure that the port must
|
||||
* indeed be configured as an output AND you are NOT linking this startup code
|
||||
* with code that was generated by DAVE code engine.
|
||||
*/
|
||||
#if (SCU_CLOCKOUT_SETUP == 1)
|
||||
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
|
||||
|
||||
if (SCU_CLOCKOUT_PIN) {
|
||||
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
|
||||
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
|
||||
}
|
||||
else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
|
||||
#endif
|
||||
|
||||
/* Setup the System clock */
|
||||
#if (SCU_CLOCK_SETUP == 1)
|
||||
SystemClockSetup();
|
||||
#endif
|
||||
|
||||
/* Setup the USB PL */
|
||||
#if (SCU_USB_CLOCK_SETUP == 1)
|
||||
USBClockSetup();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock according to Clock Register Values
|
||||
* @note -
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief -
|
||||
* @note -
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#if (SCU_CLOCK_SETUP == 1)
|
||||
static int SystemClockSetup(void)
|
||||
{
|
||||
/* enable PLL first */
|
||||
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk |
|
||||
SCU_PLL_PLLCON0_PLLPWD_Msk);
|
||||
|
||||
/* Enable OSC_HP */
|
||||
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
|
||||
{
|
||||
/* Enable the OSC_HP*/
|
||||
SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);
|
||||
/* Setup OSC WDG devider */
|
||||
SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
|
||||
/* Select external OSC as PLL input */
|
||||
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
|
||||
/* Restart OSC Watchdog */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
|
||||
|
||||
do
|
||||
{
|
||||
; /* here a timeout need to be added */
|
||||
}while(!( (SCU_PLL->PLLSTAT) &
|
||||
(SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |
|
||||
SCU_PLL_PLLSTAT_PLLSP_Msk)
|
||||
)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
/* Setup Main PLL */
|
||||
/* Select FOFI as system clock */
|
||||
if(SCU_CLK->SYSCLKCR != 0X000000)
|
||||
SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/
|
||||
|
||||
/* Go to bypass the Main PLL */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
|
||||
|
||||
/* disconnect OSC_HP to PLL */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
|
||||
|
||||
/* Setup devider settings for main PLL */
|
||||
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
|
||||
(PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));
|
||||
|
||||
/* we may have to set OSCDISCDIS */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
|
||||
|
||||
/* connect OSC_HP to PLL */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
|
||||
|
||||
/* restart PLL Lock detection */
|
||||
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
|
||||
|
||||
/* wait for PLL Lock */
|
||||
while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));
|
||||
|
||||
/* Go back to the Main PLL */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
|
||||
|
||||
/*********************************************************
|
||||
here we need to setup the system clock divider
|
||||
*********************************************************/
|
||||
|
||||
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
|
||||
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
|
||||
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
|
||||
|
||||
/* Switch system clock to PLL */
|
||||
SCU_CLK->SYSCLKCR |= 0x00010000;
|
||||
|
||||
/*********************************************************
|
||||
here the ramp up of the system clock starts
|
||||
*********************************************************/
|
||||
/* Delay for next K2 step ~50µs */
|
||||
/********************************/
|
||||
/* Set reload register */
|
||||
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;
|
||||
|
||||
/* Load the SysTick Counter Value */
|
||||
SysTick->VAL = 0;
|
||||
|
||||
/* Enable SysTick IRQ and SysTick Timer */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* wait for ~50µs */
|
||||
while (SysTick->VAL >= 100);
|
||||
|
||||
/* Stop SysTick Timer */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
/********************************/
|
||||
|
||||
/* Setup devider settings for main PLL */
|
||||
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
|
||||
(PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));
|
||||
|
||||
/* Delay for next K2 step ~50µs */
|
||||
/********************************/
|
||||
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
|
||||
|
||||
/* Load the SysTick Counter Value */
|
||||
SysTick->VAL = 0;
|
||||
|
||||
/* Enable SysTick IRQ and SysTick Timer */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Wait for ~50µs */
|
||||
while (SysTick->VAL >= 100);
|
||||
|
||||
/* Stop SysTick Timer */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
/********************************/
|
||||
|
||||
/* Setup devider settings for main PLL */
|
||||
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
|
||||
(PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));
|
||||
|
||||
/* Delay for next K2 step ~50µs */
|
||||
/********************************/
|
||||
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
|
||||
|
||||
/* Load the SysTick Counter Value */
|
||||
SysTick->VAL = 0;
|
||||
|
||||
/* Enable SysTick IRQ and SysTick Timer */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Wait for ~50µs */
|
||||
while (SysTick->VAL >= 100);
|
||||
|
||||
/* Stop SysTick Timer */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
/********************************/
|
||||
|
||||
/* Setup devider settings for main PLL */
|
||||
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) |
|
||||
(PLL_PDIV<<24));
|
||||
|
||||
/* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
|
||||
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk |
|
||||
SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
|
||||
|
||||
return(1);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief -
|
||||
* @note -
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#if(SCU_USB_CLOCK_SETUP == 1)
|
||||
static void USBClockSetup(void)
|
||||
{
|
||||
/* enable PLL first */
|
||||
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk |
|
||||
SCU_PLL_USBPLLCON_PLLPWD_Msk);
|
||||
|
||||
/* check and if not already running enable OSC_HP */
|
||||
if(!((SCU_PLL->PLLSTAT) &
|
||||
(SCU_PLL_PLLSTAT_PLLHV_Msk |
|
||||
SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))
|
||||
{
|
||||
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
|
||||
{
|
||||
|
||||
SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/
|
||||
/* setup OSC WDG devider */
|
||||
SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
|
||||
/* select external OSC as PLL input */
|
||||
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
|
||||
/* restart OSC Watchdog */
|
||||
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
|
||||
|
||||
do
|
||||
{
|
||||
; /* here a timeout need to be added */
|
||||
}while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk |
|
||||
SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)));
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Setup USB PLL */
|
||||
/* Go to bypass the Main PLL */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
|
||||
/* disconnect OSC_FI to PLL */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
|
||||
/* Setup devider settings for main PLL */
|
||||
SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));
|
||||
/* we may have to set OSCDISCDIS */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
|
||||
/* connect OSC_FI to PLL */
|
||||
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
|
||||
/* restart PLL Lock detection */
|
||||
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
|
||||
/* wait for PLL Lock */
|
||||
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,445 @@
|
|||
;*************************************************
|
||||
;*
|
||||
;* Part one of the system initialization code, contains low-level
|
||||
;* initialization, plain thumb variant.
|
||||
;*
|
||||
;* Copyright 2008 IAR Systems. All rights reserved.
|
||||
;*
|
||||
;* $Revision: 50748 $
|
||||
;*
|
||||
;*************************************************
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version with interrupt handler for XMC4500 from Infineon
|
||||
;
|
||||
|
||||
MODULE ?vector_table
|
||||
|
||||
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
|
||||
PRESERVE8
|
||||
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
|
||||
__iar_init$$done: ; The vector table is not needed
|
||||
; until after copy initialization is done
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemManage_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
|
||||
DCD SCU_0_IRQHandler ; Handler name for SR SCU_0
|
||||
DCD ERU0_0_IRQHandler ; Handler name for SR ERU0_0
|
||||
DCD ERU0_1_IRQHandler ; Handler name for SR ERU0_1
|
||||
DCD ERU0_2_IRQHandler ; Handler name for SR ERU0_2
|
||||
DCD ERU0_3_IRQHandler ; Handler name for SR ERU0_3
|
||||
DCD ERU1_0_IRQHandler ; Handler name for SR ERU1_0
|
||||
DCD ERU1_1_IRQHandler ; Handler name for SR ERU1_1
|
||||
DCD ERU1_2_IRQHandler ; Handler name for SR ERU1_2
|
||||
DCD ERU1_3_IRQHandler ; Handler name for SR ERU1_3
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD PMU0_0_IRQHandler ; Handler name for SR PMU0_0
|
||||
DCD 0 ; Not Available
|
||||
DCD VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
|
||||
DCD VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
DCD VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
|
||||
DCD VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
|
||||
DCD VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
|
||||
DCD VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
|
||||
DCD VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
|
||||
DCD VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
|
||||
DCD VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
|
||||
DCD VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
|
||||
DCD VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
|
||||
DCD VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
|
||||
DCD VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
|
||||
DCD VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
|
||||
DCD VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
|
||||
DCD VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
|
||||
DCD VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
|
||||
DCD VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
|
||||
DCD VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
|
||||
DCD VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
|
||||
DCD DSD0_0_IRQHandler ; Handler name for SR DSD0_0
|
||||
DCD DSD0_1_IRQHandler ; Handler name for SR DSD0_1
|
||||
DCD DSD0_2_IRQHandler ; Handler name for SR DSD0_2
|
||||
DCD DSD0_3_IRQHandler ; Handler name for SR DSD0_3
|
||||
DCD DSD0_4_IRQHandler ; Handler name for SR DSD0_4
|
||||
DCD DSD0_5_IRQHandler ; Handler name for SR DSD0_5
|
||||
DCD DSD0_6_IRQHandler ; Handler name for SR DSD0_6
|
||||
DCD DSD0_7_IRQHandler ; Handler name for SR DSD0_7
|
||||
DCD DAC0_0_IRQHandler ; Handler name for SR DAC0_0
|
||||
DCD DAC0_1_IRQHandler ; Handler name for SR DAC0_0
|
||||
DCD CCU40_0_IRQHandler ; Handler name for SR CCU40_0
|
||||
DCD CCU40_1_IRQHandler ; Handler name for SR CCU40_1
|
||||
DCD CCU40_2_IRQHandler ; Handler name for SR CCU40_2
|
||||
DCD CCU40_3_IRQHandler ; Handler name for SR CCU40_3
|
||||
DCD CCU41_0_IRQHandler ; Handler name for SR CCU41_0
|
||||
DCD CCU41_1_IRQHandler ; Handler name for SR CCU41_1
|
||||
DCD CCU41_2_IRQHandler ; Handler name for SR CCU41_2
|
||||
DCD CCU41_3_IRQHandler ; Handler name for SR CCU41_3
|
||||
DCD CCU42_0_IRQHandler ; Handler name for SR CCU42_0
|
||||
DCD CCU42_1_IRQHandler ; Handler name for SR CCU42_1
|
||||
DCD CCU42_2_IRQHandler ; Handler name for SR CCU42_2
|
||||
DCD CCU42_3_IRQHandler ; Handler name for SR CCU42_3
|
||||
DCD CCU43_0_IRQHandler ; Handler name for SR CCU43_0
|
||||
DCD CCU43_1_IRQHandler ; Handler name for SR CCU43_1
|
||||
DCD CCU43_2_IRQHandler ; Handler name for SR CCU43_2
|
||||
DCD CCU43_3_IRQHandler ; Handler name for SR CCU43_3
|
||||
DCD CCU80_0_IRQHandler ; Handler name for SR CCU80_0
|
||||
DCD CCU80_1_IRQHandler ; Handler name for SR CCU80_1
|
||||
DCD CCU80_2_IRQHandler ; Handler name for SR CCU80_2
|
||||
DCD CCU80_3_IRQHandler ; Handler name for SR CCU80_3
|
||||
DCD CCU81_0_IRQHandler ; Handler name for SR CCU81_0
|
||||
DCD CCU81_1_IRQHandler ; Handler name for SR CCU81_1
|
||||
DCD CCU81_2_IRQHandler ; Handler name for SR CCU81_2
|
||||
DCD CCU81_3_IRQHandler ; Handler name for SR CCU81_3
|
||||
DCD POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
|
||||
DCD POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
|
||||
DCD POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
|
||||
DCD POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD 0 ; Not Available
|
||||
DCD CAN0_0_IRQHandler ; Handler name for SR CAN0_0
|
||||
DCD CAN0_1_IRQHandler ; Handler name for SR CAN0_1
|
||||
DCD CAN0_2_IRQHandler ; Handler name for SR CAN0_2
|
||||
DCD CAN0_3_IRQHandler ; Handler name for SR CAN0_3
|
||||
DCD CAN0_4_IRQHandler ; Handler name for SR CAN0_4
|
||||
DCD CAN0_5_IRQHandler ; Handler name for SR CAN0_5
|
||||
DCD CAN0_6_IRQHandler ; Handler name for SR CAN0_6
|
||||
DCD CAN0_7_IRQHandler ; Handler name for SR CAN0_7
|
||||
DCD USIC0_0_IRQHandler ; Handler name for SR USIC0_0
|
||||
DCD USIC0_1_IRQHandler ; Handler name for SR USIC0_1
|
||||
DCD USIC0_2_IRQHandler ; Handler name for SR USIC0_2
|
||||
DCD USIC0_3_IRQHandler ; Handler name for SR USIC0_3
|
||||
DCD USIC0_4_IRQHandler ; Handler name for SR USIC0_4
|
||||
DCD USIC0_5_IRQHandler ; Handler name for SR USIC0_5
|
||||
DCD USIC1_0_IRQHandler ; Handler name for SR USIC1_0
|
||||
DCD USIC1_1_IRQHandler ; Handler name for SR USIC1_1
|
||||
DCD USIC1_2_IRQHandler ; Handler name for SR USIC1_2
|
||||
DCD USIC1_3_IRQHandler ; Handler name for SR USIC1_3
|
||||
DCD USIC1_4_IRQHandler ; Handler name for SR USIC1_4
|
||||
DCD USIC1_5_IRQHandler ; Handler name for SR USIC1_5
|
||||
DCD USIC2_0_IRQHandler ; Handler name for SR USIC2_0
|
||||
DCD USIC2_1_IRQHandler ; Handler name for SR USIC2_1
|
||||
DCD USIC2_2_IRQHandler ; Handler name for SR USIC2_2
|
||||
DCD USIC2_3_IRQHandler ; Handler name for SR USIC2_3
|
||||
DCD USIC2_4_IRQHandler ; Handler name for SR USIC2_4
|
||||
DCD USIC2_5_IRQHandler ; Handler name for SR USIC2_5
|
||||
DCD LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
|
||||
DCD 0 ; Not Available
|
||||
DCD FCE0_0_IRQHandler ; Handler name for SR FCE0_0
|
||||
DCD GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
|
||||
DCD SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
|
||||
DCD USB0_0_IRQHandler ; Handler name for SR USB0_0
|
||||
DCD ETH0_0_IRQHandler ; Handler name for SR ETH0_0
|
||||
DCD 0 ; Not Available
|
||||
DCD GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0
|
||||
DCD 0 ; Not Available
|
||||
|
||||
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK MemManage_Handler
|
||||
PUBWEAK BusFault_Handler
|
||||
PUBWEAK UsageFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK DebugMon_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
;; XMC4500 interrupt handlers
|
||||
PUBWEAK SCU_0_IRQHandler
|
||||
PUBWEAK ERU0_0_IRQHandler
|
||||
PUBWEAK ERU0_1_IRQHandler
|
||||
PUBWEAK ERU0_2_IRQHandler
|
||||
PUBWEAK ERU0_3_IRQHandler
|
||||
PUBWEAK ERU1_0_IRQHandler
|
||||
PUBWEAK ERU1_1_IRQHandler
|
||||
PUBWEAK ERU1_2_IRQHandler
|
||||
PUBWEAK ERU1_3_IRQHandler
|
||||
PUBWEAK PMU0_0_IRQHandler
|
||||
PUBWEAK PMU0_1_IRQHandler
|
||||
PUBWEAK VADC0_C0_0_IRQHandler
|
||||
PUBWEAK VADC0_C0_1_IRQHandler
|
||||
PUBWEAK VADC0_C0_2_IRQHandler
|
||||
PUBWEAK VADC0_C0_3_IRQHandler
|
||||
PUBWEAK VADC0_G0_0_IRQHandler
|
||||
PUBWEAK VADC0_G0_1_IRQHandler
|
||||
PUBWEAK VADC0_G0_2_IRQHandler
|
||||
PUBWEAK VADC0_G0_3_IRQHandler
|
||||
PUBWEAK VADC0_G1_0_IRQHandler
|
||||
PUBWEAK VADC0_G1_1_IRQHandler
|
||||
PUBWEAK VADC0_G1_2_IRQHandler
|
||||
PUBWEAK VADC0_G1_3_IRQHandler
|
||||
PUBWEAK VADC0_G2_0_IRQHandler
|
||||
PUBWEAK VADC0_G2_1_IRQHandler
|
||||
PUBWEAK VADC0_G2_2_IRQHandler
|
||||
PUBWEAK VADC0_G2_3_IRQHandler
|
||||
PUBWEAK VADC0_G3_0_IRQHandler
|
||||
PUBWEAK VADC0_G3_1_IRQHandler
|
||||
PUBWEAK VADC0_G3_2_IRQHandler
|
||||
PUBWEAK VADC0_G3_3_IRQHandler
|
||||
PUBWEAK DSD0_0_IRQHandler
|
||||
PUBWEAK DSD0_1_IRQHandler
|
||||
PUBWEAK DSD0_2_IRQHandler
|
||||
PUBWEAK DSD0_3_IRQHandler
|
||||
PUBWEAK DSD0_4_IRQHandler
|
||||
PUBWEAK DSD0_5_IRQHandler
|
||||
PUBWEAK DSD0_6_IRQHandler
|
||||
PUBWEAK DSD0_7_IRQHandler
|
||||
PUBWEAK DAC0_0_IRQHandler
|
||||
PUBWEAK DAC0_1_IRQHandler
|
||||
PUBWEAK CCU40_0_IRQHandler
|
||||
PUBWEAK CCU40_1_IRQHandler
|
||||
PUBWEAK CCU40_2_IRQHandler
|
||||
PUBWEAK CCU40_3_IRQHandler
|
||||
PUBWEAK CCU41_0_IRQHandler
|
||||
PUBWEAK CCU41_1_IRQHandler
|
||||
PUBWEAK CCU41_2_IRQHandler
|
||||
PUBWEAK CCU41_3_IRQHandler
|
||||
PUBWEAK CCU42_0_IRQHandler
|
||||
PUBWEAK CCU42_1_IRQHandler
|
||||
PUBWEAK CCU42_2_IRQHandler
|
||||
PUBWEAK CCU42_3_IRQHandler
|
||||
PUBWEAK CCU43_0_IRQHandler
|
||||
PUBWEAK CCU43_1_IRQHandler
|
||||
PUBWEAK CCU43_2_IRQHandler
|
||||
PUBWEAK CCU43_3_IRQHandler
|
||||
PUBWEAK CCU80_0_IRQHandler
|
||||
PUBWEAK CCU80_1_IRQHandler
|
||||
PUBWEAK CCU80_2_IRQHandler
|
||||
PUBWEAK CCU80_3_IRQHandler
|
||||
PUBWEAK CCU81_0_IRQHandler
|
||||
PUBWEAK CCU81_1_IRQHandler
|
||||
PUBWEAK CCU81_2_IRQHandler
|
||||
PUBWEAK CCU81_3_IRQHandler
|
||||
PUBWEAK POSIF0_0_IRQHandler
|
||||
PUBWEAK POSIF0_1_IRQHandler
|
||||
PUBWEAK POSIF1_0_IRQHandler
|
||||
PUBWEAK POSIF1_1_IRQHandler
|
||||
PUBWEAK CAN0_0_IRQHandler
|
||||
PUBWEAK CAN0_1_IRQHandler
|
||||
PUBWEAK CAN0_2_IRQHandler
|
||||
PUBWEAK CAN0_3_IRQHandler
|
||||
PUBWEAK CAN0_4_IRQHandler
|
||||
PUBWEAK CAN0_5_IRQHandler
|
||||
PUBWEAK CAN0_6_IRQHandler
|
||||
PUBWEAK CAN0_7_IRQHandler
|
||||
PUBWEAK USIC0_0_IRQHandler
|
||||
PUBWEAK USIC0_1_IRQHandler
|
||||
PUBWEAK USIC0_2_IRQHandler
|
||||
PUBWEAK USIC0_3_IRQHandler
|
||||
PUBWEAK USIC0_4_IRQHandler
|
||||
PUBWEAK USIC0_5_IRQHandler
|
||||
PUBWEAK USIC1_0_IRQHandler
|
||||
PUBWEAK USIC1_1_IRQHandler
|
||||
PUBWEAK USIC1_2_IRQHandler
|
||||
PUBWEAK USIC1_3_IRQHandler
|
||||
PUBWEAK USIC1_4_IRQHandler
|
||||
PUBWEAK USIC1_5_IRQHandler
|
||||
PUBWEAK USIC2_0_IRQHandler
|
||||
PUBWEAK USIC2_1_IRQHandler
|
||||
PUBWEAK USIC2_2_IRQHandler
|
||||
PUBWEAK USIC2_3_IRQHandler
|
||||
PUBWEAK USIC2_4_IRQHandler
|
||||
PUBWEAK USIC2_5_IRQHandler
|
||||
PUBWEAK LEDTS0_0_IRQHandler
|
||||
PUBWEAK FCE0_0_IRQHandler
|
||||
PUBWEAK GPDMA0_0_IRQHandler
|
||||
PUBWEAK SDMMC0_0_IRQHandler
|
||||
PUBWEAK USB0_0_IRQHandler
|
||||
PUBWEAK ETH0_0_IRQHandler
|
||||
PUBWEAK GPDMA1_0_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
THUMB
|
||||
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
MemManage_Handler
|
||||
BusFault_Handler
|
||||
UsageFault_Handler
|
||||
SVC_Handler
|
||||
DebugMon_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
|
||||
SCU_0_IRQHandler
|
||||
ERU0_0_IRQHandler
|
||||
ERU0_1_IRQHandler
|
||||
ERU0_2_IRQHandler
|
||||
ERU0_3_IRQHandler
|
||||
ERU1_0_IRQHandler
|
||||
ERU1_1_IRQHandler
|
||||
ERU1_2_IRQHandler
|
||||
ERU1_3_IRQHandler
|
||||
PMU0_0_IRQHandler
|
||||
PMU0_1_IRQHandler
|
||||
VADC0_C0_0_IRQHandler
|
||||
VADC0_C0_1_IRQHandler
|
||||
VADC0_C0_2_IRQHandler
|
||||
VADC0_C0_3_IRQHandler
|
||||
VADC0_G0_0_IRQHandler
|
||||
VADC0_G0_1_IRQHandler
|
||||
VADC0_G0_2_IRQHandler
|
||||
VADC0_G0_3_IRQHandler
|
||||
VADC0_G1_0_IRQHandler
|
||||
VADC0_G1_1_IRQHandler
|
||||
VADC0_G1_2_IRQHandler
|
||||
VADC0_G1_3_IRQHandler
|
||||
VADC0_G2_0_IRQHandler
|
||||
VADC0_G2_1_IRQHandler
|
||||
VADC0_G2_2_IRQHandler
|
||||
VADC0_G2_3_IRQHandler
|
||||
VADC0_G3_0_IRQHandler
|
||||
VADC0_G3_1_IRQHandler
|
||||
VADC0_G3_2_IRQHandler
|
||||
VADC0_G3_3_IRQHandler
|
||||
DSD0_0_IRQHandler
|
||||
DSD0_1_IRQHandler
|
||||
DSD0_2_IRQHandler
|
||||
DSD0_3_IRQHandler
|
||||
DSD0_4_IRQHandler
|
||||
DSD0_5_IRQHandler
|
||||
DSD0_6_IRQHandler
|
||||
DSD0_7_IRQHandler
|
||||
DAC0_0_IRQHandler
|
||||
DAC0_1_IRQHandler
|
||||
CCU40_0_IRQHandler
|
||||
CCU40_1_IRQHandler
|
||||
CCU40_2_IRQHandler
|
||||
CCU40_3_IRQHandler
|
||||
CCU41_0_IRQHandler
|
||||
CCU41_1_IRQHandler
|
||||
CCU41_2_IRQHandler
|
||||
CCU41_3_IRQHandler
|
||||
CCU42_0_IRQHandler
|
||||
CCU42_1_IRQHandler
|
||||
CCU42_2_IRQHandler
|
||||
CCU42_3_IRQHandler
|
||||
CCU43_0_IRQHandler
|
||||
CCU43_1_IRQHandler
|
||||
CCU43_2_IRQHandler
|
||||
CCU43_3_IRQHandler
|
||||
CCU80_0_IRQHandler
|
||||
CCU80_1_IRQHandler
|
||||
CCU80_2_IRQHandler
|
||||
CCU80_3_IRQHandler
|
||||
CCU81_0_IRQHandler
|
||||
CCU81_1_IRQHandler
|
||||
CCU81_2_IRQHandler
|
||||
CCU81_3_IRQHandler
|
||||
POSIF0_0_IRQHandler
|
||||
POSIF0_1_IRQHandler
|
||||
POSIF1_0_IRQHandler
|
||||
POSIF1_1_IRQHandler
|
||||
CAN0_0_IRQHandler
|
||||
CAN0_1_IRQHandler
|
||||
CAN0_2_IRQHandler
|
||||
CAN0_3_IRQHandler
|
||||
CAN0_4_IRQHandler
|
||||
CAN0_5_IRQHandler
|
||||
CAN0_6_IRQHandler
|
||||
CAN0_7_IRQHandler
|
||||
USIC0_0_IRQHandler
|
||||
USIC0_1_IRQHandler
|
||||
USIC0_2_IRQHandler
|
||||
USIC0_3_IRQHandler
|
||||
USIC0_4_IRQHandler
|
||||
USIC0_5_IRQHandler
|
||||
USIC1_0_IRQHandler
|
||||
USIC1_1_IRQHandler
|
||||
USIC1_2_IRQHandler
|
||||
USIC1_3_IRQHandler
|
||||
USIC1_4_IRQHandler
|
||||
USIC1_5_IRQHandler
|
||||
USIC2_0_IRQHandler
|
||||
USIC2_1_IRQHandler
|
||||
USIC2_2_IRQHandler
|
||||
USIC2_3_IRQHandler
|
||||
USIC2_4_IRQHandler
|
||||
USIC2_5_IRQHandler
|
||||
LEDTS0_0_IRQHandler
|
||||
FCE0_0_IRQHandler
|
||||
GPDMA0_0_IRQHandler
|
||||
SDMMC0_0_IRQHandler
|
||||
USB0_0_IRQHandler
|
||||
ETH0_0_IRQHandler
|
||||
GPDMA1_0_IRQHandler
|
||||
|
||||
Default_Handler
|
||||
NOCALL Default_Handler
|
||||
B Default_Handler
|
||||
|
||||
PREF_PCON EQU 0x58004000
|
||||
SCU_GCU_PEEN EQU 0x5000413C
|
||||
SCU_GCU_PEFLAG EQU 0x50004150
|
||||
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
THUMB
|
||||
Reset_Handler:
|
||||
; A11 workaround for branch prediction and parity
|
||||
LDR R0,=PREF_PCON /* switch off branch prediction required in A11 step to use cached memory*/
|
||||
LDR R1,[R0]
|
||||
ORR R1,R1,#0x00010000
|
||||
STR R1,[R0]
|
||||
|
||||
/* Clear existing parity errors if any required in A11 step */
|
||||
LDR R0,=SCU_GCU_PEFLAG
|
||||
MOV R1,#0xFFFFFFFF
|
||||
STR R1,[R0]
|
||||
|
||||
/* Disable parity required in A11 step*/
|
||||
LDR R0,=SCU_GCU_PEEN
|
||||
MOV R1,#0
|
||||
STR R1,[R0]
|
||||
B __iar_program_start
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_XMC4500.h
|
||||
* @brief Header file for the XMC4500-Series systeminit
|
||||
*
|
||||
* @version V1.4
|
||||
* @date 31. Januar 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
|
||||
|
||||
*
|
||||
* @par
|
||||
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
|
||||
* This file can be freely distributed within development tools that are supporting such microcontrollers.
|
||||
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_XMC4500_H
|
||||
#define __SYSTEM_XMC4500_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
/* clock definitions, do not modify! */
|
||||
#define SCU_CLOCK_CRYSTAL 1
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* mandatory clock parameters **************************************************
|
||||
*/
|
||||
/* source for clock generation
|
||||
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
|
||||
#define CLOCK_OSC_HP 24000000
|
||||
#define CLOCK_CRYSTAL_FREQUENCY 12000000
|
||||
#define SYSTEM_FREQUENCY 120000000
|
||||
|
||||
/* OSC_HP setup parameters */
|
||||
#define OSC_HP_MODE 0
|
||||
#define OSCHPWDGDIV 2
|
||||
|
||||
/* MAIN PLL setup parameters */
|
||||
|
||||
|
||||
#define PLL_K1DIV 1
|
||||
#define PLL_K2DIV 3
|
||||
#define PLL_PDIV 1
|
||||
#define PLL_NDIV 79
|
||||
|
||||
|
||||
|
||||
#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
|
||||
#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
|
||||
#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
|
||||
|
||||
|
||||
|
||||
#define USBPLL_PDIV 1
|
||||
#define USBPLL_NDIV 15
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
60
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c
Normal file
60
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/**************************************************
|
||||
*
|
||||
* This module contains the function `__low_level_init', a function
|
||||
* that is called before the `main' function of the program. Normally
|
||||
* low-level initializations - such as setting the prefered interrupt
|
||||
* level or setting the watchdog - can be performed here.
|
||||
*
|
||||
* Note that this function is called before the data segments are
|
||||
* initialized, this means that this function cannot rely on the
|
||||
* values of global or static variables.
|
||||
*
|
||||
* When this function returns zero, the startup code will inhibit the
|
||||
* initialization of the data segments. The result is faster startup,
|
||||
* the drawback is that neither global nor static data will be
|
||||
* initialized.
|
||||
*
|
||||
* Copyright 1999-2004 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 50082 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "System_XMC4500.h"
|
||||
|
||||
#pragma language=extended
|
||||
|
||||
__interwork int __low_level_init(void);
|
||||
|
||||
__interwork int __low_level_init(void)
|
||||
{
|
||||
/*==================================*/
|
||||
/* Initialize hardware. */
|
||||
/*==================================*/
|
||||
|
||||
/*==================================*/
|
||||
/* Choose if segment initialization */
|
||||
/* should be done or not. */
|
||||
/* Return: 0 to omit seg_init */
|
||||
/* 1 to run seg_init */
|
||||
/*==================================*/
|
||||
|
||||
|
||||
/* Init clock Sys clk 96MHz, MCU clk 96MHz, PB clk 48MHz */
|
||||
SystemInit();
|
||||
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#pragma language=default
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in a new issue