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Starting point for XMC4500 IAR demo application.

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Richard Barry 2012-04-15 21:04:53 +00:00
parent 4793063ee0
commit eff1636a94
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412
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c Normal file
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/******************************************************************************
* @file system_XMC4500.c
* @brief Device specific initialization for the XMC4500-Series according to CMSIS
* @version V2.2
* @date 20. January 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#include "System_XMC4500.h"
#include <XMC4500.h>
/*----------------------------------------------------------------------------
Define clocks is located in System_XMC4500.h
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock = CLOCK_OSC_HP;
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Watchdog Configuration -------------------------------
//
// <e> Watchdog Configuration
// <o1.0> Disable Watchdog
//
// </e>
*/
#define WDT_SETUP 1
#define WDTENB_nVal 0x00000001
/*--------------------- CLOCK Configuration -------------------------------
//
// <e> Main Clock Configuration
// <o1.0..1> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0..1> Peripheral Bus clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <o3.0..1> CCU Bus clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
//
// </e>
//
*/
#define SCU_CLOCK_SETUP 1
#define SCU_CPUCLKCR_DIV 0x00000000
#define SCU_PBCLKCR_DIV 0x00000000
#define SCU_CCUCLKCR_DIV 0x00000000
/*--------------------- USB CLOCK Configuration ---------------------------
//
// <e> USB Clock Configuration
//
// </e>
//
*/
#define SCU_USB_CLOCK_SETUP 0
/*--------------------- CLOCKOUT Configuration -------------------------------
//
// <e> Clock OUT Configuration
// <o1.0..1> Clockout Source Selection
// <0=> System Clock
// <2=> USB Clock
// <3=> Divided value of PLL Clock
// <o2.0..1> Clockout Pin Selection
// <0=> P1.15
// <1=> P0.8
//
//
// </e>
//
*/
#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled
#define SCU_CLOCKOUT_SOURCE 0x00000000
#define SCU_CLOCKOUT_PIN 0x00000000
/*----------------------------------------------------------------------------
static functions declarations
*----------------------------------------------------------------------------*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void);
#endif
#if (SCU_USB_CLOCK_SETUP == 1)
static void USBClockSetup(void);
#endif
/**
* @brief Setup the microcontroller system.
* Initialize the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Setup the WDT */
#if (WDT_SETUP == 1)
WDT->CTR &= ~WDTENB_nVal;
#endif
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Disable branch prediction - PCON.PBS = 1 */
PREF->PCON |= (PREF_PCON_PBS_Msk);
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
/* Setup the clockout */
/* README README README README README README README README README README */
/*
* Please use the CLOCKOUT feature with diligence. Use this only if you know
* what you are doing.
*
* You must be aware that the settings below can potentially be in conflict
* with DAVE code generation engine preferences.
*
* Even worse, the setting below configures the ports as output ports while in
* reality, the board on which this chip is mounted may have a source driving
* the ports.
*
* So use this feature only when you are absolutely sure that the port must
* indeed be configured as an output AND you are NOT linking this startup code
* with code that was generated by DAVE code engine.
*/
#if (SCU_CLOCKOUT_SETUP == 1)
SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
if (SCU_CLOCKOUT_PIN) {
PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
}
else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
#endif
/* Setup the System clock */
#if (SCU_CLOCK_SETUP == 1)
SystemClockSetup();
#endif
/* Setup the USB PL */
#if (SCU_USB_CLOCK_SETUP == 1)
USBClockSetup();
#endif
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note -
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/
}
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if (SCU_CLOCK_SETUP == 1)
static int SystemClockSetup(void)
{
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk |
SCU_PLL_PLLCON0_PLLPWD_Msk);
/* Enable OSC_HP */
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
/* Enable the OSC_HP*/
SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);
/* Setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
/* Select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* Restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
do
{
; /* here a timeout need to be added */
}while(!( (SCU_PLL->PLLSTAT) &
(SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |
SCU_PLL_PLLSTAT_PLLSP_Msk)
)
);
}
/* Setup Main PLL */
/* Select FOFI as system clock */
if(SCU_CLK->SYSCLKCR != 0X000000)
SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect OSC_HP to PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
(PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect OSC_HP to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));
/* Go back to the Main PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
/*********************************************************
here we need to setup the system clock divider
*********************************************************/
SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= 0x00010000;
/*********************************************************
here the ramp up of the system clock starts
*********************************************************/
/* Delay for next K2 step ~50µs */
/********************************/
/* Set reload register */
SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;
/* Load the SysTick Counter Value */
SysTick->VAL = 0;
/* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk;
/* wait for ~50µs */
while (SysTick->VAL >= 100);
/* Stop SysTick Timer */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
(PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));
/* Delay for next K2 step ~50µs */
/********************************/
SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
/* Load the SysTick Counter Value */
SysTick->VAL = 0;
/* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Wait for ~50µs */
while (SysTick->VAL >= 100);
/* Stop SysTick Timer */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) |
(PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));
/* Delay for next K2 step ~50µs */
/********************************/
SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
/* Load the SysTick Counter Value */
SysTick->VAL = 0;
/* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Wait for ~50µs */
while (SysTick->VAL >= 100);
/* Stop SysTick Timer */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
/********************************/
/* Setup devider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) |
(PLL_PDIV<<24));
/* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk |
SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
return(1);
}
#endif
/**
* @brief -
* @note -
* @param None
* @retval None
*/
#if(SCU_USB_CLOCK_SETUP == 1)
static void USBClockSetup(void)
{
/* enable PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk |
SCU_PLL_USBPLLCON_PLLPWD_Msk);
/* check and if not already running enable OSC_HP */
if(!((SCU_PLL->PLLSTAT) &
(SCU_PLL_PLLSTAT_PLLHV_Msk |
SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))
{
if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
{
SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/
/* setup OSC WDG devider */
SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);
/* select external OSC as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
do
{
; /* here a timeout need to be added */
}while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk |
SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)));
}
}
/* Setup USB PLL */
/* Go to bypass the Main PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect OSC_FI to PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup devider settings for main PLL */
SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));
/* we may have to set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect OSC_FI to PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
/* wait for PLL Lock */
while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
}
#endif

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Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h Normal file
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Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/startup/iar/vector_table_M_forXMC4500.s Normal file
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;*************************************************
;*
;* Part one of the system initialization code, contains low-level
;* initialization, plain thumb variant.
;*
;* Copyright 2008 IAR Systems. All rights reserved.
;*
;* $Revision: 50748 $
;*
;*************************************************
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version with interrupt handler for XMC4500 from Infineon
;
MODULE ?vector_table
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
DCD SCU_0_IRQHandler ; Handler name for SR SCU_0
DCD ERU0_0_IRQHandler ; Handler name for SR ERU0_0
DCD ERU0_1_IRQHandler ; Handler name for SR ERU0_1
DCD ERU0_2_IRQHandler ; Handler name for SR ERU0_2
DCD ERU0_3_IRQHandler ; Handler name for SR ERU0_3
DCD ERU1_0_IRQHandler ; Handler name for SR ERU1_0
DCD ERU1_1_IRQHandler ; Handler name for SR ERU1_1
DCD ERU1_2_IRQHandler ; Handler name for SR ERU1_2
DCD ERU1_3_IRQHandler ; Handler name for SR ERU1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD PMU0_0_IRQHandler ; Handler name for SR PMU0_0
DCD 0 ; Not Available
DCD VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
DCD VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
DCD VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
DCD VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
DCD VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
DCD VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
DCD VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
DCD VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
DCD VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
DCD VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
DCD VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
DCD VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
DCD VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
DCD VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
DCD VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
DCD VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
DCD VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
DCD VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
DCD VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
DCD VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
DCD DSD0_0_IRQHandler ; Handler name for SR DSD0_0
DCD DSD0_1_IRQHandler ; Handler name for SR DSD0_1
DCD DSD0_2_IRQHandler ; Handler name for SR DSD0_2
DCD DSD0_3_IRQHandler ; Handler name for SR DSD0_3
DCD DSD0_4_IRQHandler ; Handler name for SR DSD0_4
DCD DSD0_5_IRQHandler ; Handler name for SR DSD0_5
DCD DSD0_6_IRQHandler ; Handler name for SR DSD0_6
DCD DSD0_7_IRQHandler ; Handler name for SR DSD0_7
DCD DAC0_0_IRQHandler ; Handler name for SR DAC0_0
DCD DAC0_1_IRQHandler ; Handler name for SR DAC0_0
DCD CCU40_0_IRQHandler ; Handler name for SR CCU40_0
DCD CCU40_1_IRQHandler ; Handler name for SR CCU40_1
DCD CCU40_2_IRQHandler ; Handler name for SR CCU40_2
DCD CCU40_3_IRQHandler ; Handler name for SR CCU40_3
DCD CCU41_0_IRQHandler ; Handler name for SR CCU41_0
DCD CCU41_1_IRQHandler ; Handler name for SR CCU41_1
DCD CCU41_2_IRQHandler ; Handler name for SR CCU41_2
DCD CCU41_3_IRQHandler ; Handler name for SR CCU41_3
DCD CCU42_0_IRQHandler ; Handler name for SR CCU42_0
DCD CCU42_1_IRQHandler ; Handler name for SR CCU42_1
DCD CCU42_2_IRQHandler ; Handler name for SR CCU42_2
DCD CCU42_3_IRQHandler ; Handler name for SR CCU42_3
DCD CCU43_0_IRQHandler ; Handler name for SR CCU43_0
DCD CCU43_1_IRQHandler ; Handler name for SR CCU43_1
DCD CCU43_2_IRQHandler ; Handler name for SR CCU43_2
DCD CCU43_3_IRQHandler ; Handler name for SR CCU43_3
DCD CCU80_0_IRQHandler ; Handler name for SR CCU80_0
DCD CCU80_1_IRQHandler ; Handler name for SR CCU80_1
DCD CCU80_2_IRQHandler ; Handler name for SR CCU80_2
DCD CCU80_3_IRQHandler ; Handler name for SR CCU80_3
DCD CCU81_0_IRQHandler ; Handler name for SR CCU81_0
DCD CCU81_1_IRQHandler ; Handler name for SR CCU81_1
DCD CCU81_2_IRQHandler ; Handler name for SR CCU81_2
DCD CCU81_3_IRQHandler ; Handler name for SR CCU81_3
DCD POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
DCD POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
DCD POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
DCD POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD CAN0_0_IRQHandler ; Handler name for SR CAN0_0
DCD CAN0_1_IRQHandler ; Handler name for SR CAN0_1
DCD CAN0_2_IRQHandler ; Handler name for SR CAN0_2
DCD CAN0_3_IRQHandler ; Handler name for SR CAN0_3
DCD CAN0_4_IRQHandler ; Handler name for SR CAN0_4
DCD CAN0_5_IRQHandler ; Handler name for SR CAN0_5
DCD CAN0_6_IRQHandler ; Handler name for SR CAN0_6
DCD CAN0_7_IRQHandler ; Handler name for SR CAN0_7
DCD USIC0_0_IRQHandler ; Handler name for SR USIC0_0
DCD USIC0_1_IRQHandler ; Handler name for SR USIC0_1
DCD USIC0_2_IRQHandler ; Handler name for SR USIC0_2
DCD USIC0_3_IRQHandler ; Handler name for SR USIC0_3
DCD USIC0_4_IRQHandler ; Handler name for SR USIC0_4
DCD USIC0_5_IRQHandler ; Handler name for SR USIC0_5
DCD USIC1_0_IRQHandler ; Handler name for SR USIC1_0
DCD USIC1_1_IRQHandler ; Handler name for SR USIC1_1
DCD USIC1_2_IRQHandler ; Handler name for SR USIC1_2
DCD USIC1_3_IRQHandler ; Handler name for SR USIC1_3
DCD USIC1_4_IRQHandler ; Handler name for SR USIC1_4
DCD USIC1_5_IRQHandler ; Handler name for SR USIC1_5
DCD USIC2_0_IRQHandler ; Handler name for SR USIC2_0
DCD USIC2_1_IRQHandler ; Handler name for SR USIC2_1
DCD USIC2_2_IRQHandler ; Handler name for SR USIC2_2
DCD USIC2_3_IRQHandler ; Handler name for SR USIC2_3
DCD USIC2_4_IRQHandler ; Handler name for SR USIC2_4
DCD USIC2_5_IRQHandler ; Handler name for SR USIC2_5
DCD LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
DCD 0 ; Not Available
DCD FCE0_0_IRQHandler ; Handler name for SR FCE0_0
DCD GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
DCD SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
DCD USB0_0_IRQHandler ; Handler name for SR USB0_0
DCD ETH0_0_IRQHandler ; Handler name for SR ETH0_0
DCD 0 ; Not Available
DCD GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0
DCD 0 ; Not Available
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
;; XMC4500 interrupt handlers
PUBWEAK SCU_0_IRQHandler
PUBWEAK ERU0_0_IRQHandler
PUBWEAK ERU0_1_IRQHandler
PUBWEAK ERU0_2_IRQHandler
PUBWEAK ERU0_3_IRQHandler
PUBWEAK ERU1_0_IRQHandler
PUBWEAK ERU1_1_IRQHandler
PUBWEAK ERU1_2_IRQHandler
PUBWEAK ERU1_3_IRQHandler
PUBWEAK PMU0_0_IRQHandler
PUBWEAK PMU0_1_IRQHandler
PUBWEAK VADC0_C0_0_IRQHandler
PUBWEAK VADC0_C0_1_IRQHandler
PUBWEAK VADC0_C0_2_IRQHandler
PUBWEAK VADC0_C0_3_IRQHandler
PUBWEAK VADC0_G0_0_IRQHandler
PUBWEAK VADC0_G0_1_IRQHandler
PUBWEAK VADC0_G0_2_IRQHandler
PUBWEAK VADC0_G0_3_IRQHandler
PUBWEAK VADC0_G1_0_IRQHandler
PUBWEAK VADC0_G1_1_IRQHandler
PUBWEAK VADC0_G1_2_IRQHandler
PUBWEAK VADC0_G1_3_IRQHandler
PUBWEAK VADC0_G2_0_IRQHandler
PUBWEAK VADC0_G2_1_IRQHandler
PUBWEAK VADC0_G2_2_IRQHandler
PUBWEAK VADC0_G2_3_IRQHandler
PUBWEAK VADC0_G3_0_IRQHandler
PUBWEAK VADC0_G3_1_IRQHandler
PUBWEAK VADC0_G3_2_IRQHandler
PUBWEAK VADC0_G3_3_IRQHandler
PUBWEAK DSD0_0_IRQHandler
PUBWEAK DSD0_1_IRQHandler
PUBWEAK DSD0_2_IRQHandler
PUBWEAK DSD0_3_IRQHandler
PUBWEAK DSD0_4_IRQHandler
PUBWEAK DSD0_5_IRQHandler
PUBWEAK DSD0_6_IRQHandler
PUBWEAK DSD0_7_IRQHandler
PUBWEAK DAC0_0_IRQHandler
PUBWEAK DAC0_1_IRQHandler
PUBWEAK CCU40_0_IRQHandler
PUBWEAK CCU40_1_IRQHandler
PUBWEAK CCU40_2_IRQHandler
PUBWEAK CCU40_3_IRQHandler
PUBWEAK CCU41_0_IRQHandler
PUBWEAK CCU41_1_IRQHandler
PUBWEAK CCU41_2_IRQHandler
PUBWEAK CCU41_3_IRQHandler
PUBWEAK CCU42_0_IRQHandler
PUBWEAK CCU42_1_IRQHandler
PUBWEAK CCU42_2_IRQHandler
PUBWEAK CCU42_3_IRQHandler
PUBWEAK CCU43_0_IRQHandler
PUBWEAK CCU43_1_IRQHandler
PUBWEAK CCU43_2_IRQHandler
PUBWEAK CCU43_3_IRQHandler
PUBWEAK CCU80_0_IRQHandler
PUBWEAK CCU80_1_IRQHandler
PUBWEAK CCU80_2_IRQHandler
PUBWEAK CCU80_3_IRQHandler
PUBWEAK CCU81_0_IRQHandler
PUBWEAK CCU81_1_IRQHandler
PUBWEAK CCU81_2_IRQHandler
PUBWEAK CCU81_3_IRQHandler
PUBWEAK POSIF0_0_IRQHandler
PUBWEAK POSIF0_1_IRQHandler
PUBWEAK POSIF1_0_IRQHandler
PUBWEAK POSIF1_1_IRQHandler
PUBWEAK CAN0_0_IRQHandler
PUBWEAK CAN0_1_IRQHandler
PUBWEAK CAN0_2_IRQHandler
PUBWEAK CAN0_3_IRQHandler
PUBWEAK CAN0_4_IRQHandler
PUBWEAK CAN0_5_IRQHandler
PUBWEAK CAN0_6_IRQHandler
PUBWEAK CAN0_7_IRQHandler
PUBWEAK USIC0_0_IRQHandler
PUBWEAK USIC0_1_IRQHandler
PUBWEAK USIC0_2_IRQHandler
PUBWEAK USIC0_3_IRQHandler
PUBWEAK USIC0_4_IRQHandler
PUBWEAK USIC0_5_IRQHandler
PUBWEAK USIC1_0_IRQHandler
PUBWEAK USIC1_1_IRQHandler
PUBWEAK USIC1_2_IRQHandler
PUBWEAK USIC1_3_IRQHandler
PUBWEAK USIC1_4_IRQHandler
PUBWEAK USIC1_5_IRQHandler
PUBWEAK USIC2_0_IRQHandler
PUBWEAK USIC2_1_IRQHandler
PUBWEAK USIC2_2_IRQHandler
PUBWEAK USIC2_3_IRQHandler
PUBWEAK USIC2_4_IRQHandler
PUBWEAK USIC2_5_IRQHandler
PUBWEAK LEDTS0_0_IRQHandler
PUBWEAK FCE0_0_IRQHandler
PUBWEAK GPDMA0_0_IRQHandler
PUBWEAK SDMMC0_0_IRQHandler
PUBWEAK USB0_0_IRQHandler
PUBWEAK ETH0_0_IRQHandler
PUBWEAK GPDMA1_0_IRQHandler
SECTION .text:CODE:REORDER(2)
THUMB
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
SCU_0_IRQHandler
ERU0_0_IRQHandler
ERU0_1_IRQHandler
ERU0_2_IRQHandler
ERU0_3_IRQHandler
ERU1_0_IRQHandler
ERU1_1_IRQHandler
ERU1_2_IRQHandler
ERU1_3_IRQHandler
PMU0_0_IRQHandler
PMU0_1_IRQHandler
VADC0_C0_0_IRQHandler
VADC0_C0_1_IRQHandler
VADC0_C0_2_IRQHandler
VADC0_C0_3_IRQHandler
VADC0_G0_0_IRQHandler
VADC0_G0_1_IRQHandler
VADC0_G0_2_IRQHandler
VADC0_G0_3_IRQHandler
VADC0_G1_0_IRQHandler
VADC0_G1_1_IRQHandler
VADC0_G1_2_IRQHandler
VADC0_G1_3_IRQHandler
VADC0_G2_0_IRQHandler
VADC0_G2_1_IRQHandler
VADC0_G2_2_IRQHandler
VADC0_G2_3_IRQHandler
VADC0_G3_0_IRQHandler
VADC0_G3_1_IRQHandler
VADC0_G3_2_IRQHandler
VADC0_G3_3_IRQHandler
DSD0_0_IRQHandler
DSD0_1_IRQHandler
DSD0_2_IRQHandler
DSD0_3_IRQHandler
DSD0_4_IRQHandler
DSD0_5_IRQHandler
DSD0_6_IRQHandler
DSD0_7_IRQHandler
DAC0_0_IRQHandler
DAC0_1_IRQHandler
CCU40_0_IRQHandler
CCU40_1_IRQHandler
CCU40_2_IRQHandler
CCU40_3_IRQHandler
CCU41_0_IRQHandler
CCU41_1_IRQHandler
CCU41_2_IRQHandler
CCU41_3_IRQHandler
CCU42_0_IRQHandler
CCU42_1_IRQHandler
CCU42_2_IRQHandler
CCU42_3_IRQHandler
CCU43_0_IRQHandler
CCU43_1_IRQHandler
CCU43_2_IRQHandler
CCU43_3_IRQHandler
CCU80_0_IRQHandler
CCU80_1_IRQHandler
CCU80_2_IRQHandler
CCU80_3_IRQHandler
CCU81_0_IRQHandler
CCU81_1_IRQHandler
CCU81_2_IRQHandler
CCU81_3_IRQHandler
POSIF0_0_IRQHandler
POSIF0_1_IRQHandler
POSIF1_0_IRQHandler
POSIF1_1_IRQHandler
CAN0_0_IRQHandler
CAN0_1_IRQHandler
CAN0_2_IRQHandler
CAN0_3_IRQHandler
CAN0_4_IRQHandler
CAN0_5_IRQHandler
CAN0_6_IRQHandler
CAN0_7_IRQHandler
USIC0_0_IRQHandler
USIC0_1_IRQHandler
USIC0_2_IRQHandler
USIC0_3_IRQHandler
USIC0_4_IRQHandler
USIC0_5_IRQHandler
USIC1_0_IRQHandler
USIC1_1_IRQHandler
USIC1_2_IRQHandler
USIC1_3_IRQHandler
USIC1_4_IRQHandler
USIC1_5_IRQHandler
USIC2_0_IRQHandler
USIC2_1_IRQHandler
USIC2_2_IRQHandler
USIC2_3_IRQHandler
USIC2_4_IRQHandler
USIC2_5_IRQHandler
LEDTS0_0_IRQHandler
FCE0_0_IRQHandler
GPDMA0_0_IRQHandler
SDMMC0_0_IRQHandler
USB0_0_IRQHandler
ETH0_0_IRQHandler
GPDMA1_0_IRQHandler
Default_Handler
NOCALL Default_Handler
B Default_Handler
PREF_PCON EQU 0x58004000
SCU_GCU_PEEN EQU 0x5000413C
SCU_GCU_PEFLAG EQU 0x50004150
SECTION .text:CODE:REORDER(2)
THUMB
Reset_Handler:
; A11 workaround for branch prediction and parity
LDR R0,=PREF_PCON /* switch off branch prediction required in A11 step to use cached memory*/
LDR R1,[R0]
ORR R1,R1,#0x00010000
STR R1,[R0]
/* Clear existing parity errors if any required in A11 step */
LDR R0,=SCU_GCU_PEFLAG
MOV R1,#0xFFFFFFFF
STR R1,[R0]
/* Disable parity required in A11 step*/
LDR R0,=SCU_GCU_PEEN
MOV R1,#0
STR R1,[R0]
B __iar_program_start
END

110
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/system_XMC4500.h Normal file
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/**************************************************************************//**
* @file system_XMC4500.h
* @brief Header file for the XMC4500-Series systeminit
*
* @version V1.4
* @date 31. Januar 2012
*
* @note
* Copyright (C) 2011 Infineon Technologies AG. All rights reserved.
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers.
* This file can be freely distributed within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
*
******************************************************************************/
#ifndef __SYSTEM_XMC4500_H
#define __SYSTEM_XMC4500_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* clock definitions, do not modify! */
#define SCU_CLOCK_CRYSTAL 1
/*
* mandatory clock parameters **************************************************
*/
/* source for clock generation
* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
*
**************************************************************************************/
#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
#define CLOCK_OSC_HP 24000000
#define CLOCK_CRYSTAL_FREQUENCY 12000000
#define SYSTEM_FREQUENCY 120000000
/* OSC_HP setup parameters */
#define OSC_HP_MODE 0
#define OSCHPWDGDIV 2
/* MAIN PLL setup parameters */
#define PLL_K1DIV 1
#define PLL_K2DIV 3
#define PLL_PDIV 1
#define PLL_NDIV 79
#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz
#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz
#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz
#define USBPLL_PDIV 1
#define USBPLL_NDIV 15
#ifdef __cplusplus
}
#endif
#endif

60
Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c Normal file
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/**************************************************
*
* This module contains the function `__low_level_init', a function
* that is called before the `main' function of the program. Normally
* low-level initializations - such as setting the prefered interrupt
* level or setting the watchdog - can be performed here.
*
* Note that this function is called before the data segments are
* initialized, this means that this function cannot rely on the
* values of global or static variables.
*
* When this function returns zero, the startup code will inhibit the
* initialization of the data segments. The result is faster startup,
* the drawback is that neither global nor static data will be
* initialized.
*
* Copyright 1999-2004 IAR Systems. All rights reserved.
*
* $Revision: 50082 $
*
**************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#include "System_XMC4500.h"
#pragma language=extended
__interwork int __low_level_init(void);
__interwork int __low_level_init(void)
{
/*==================================*/
/* Initialize hardware. */
/*==================================*/
/*==================================*/
/* Choose if segment initialization */
/* should be done or not. */
/* Return: 0 to omit seg_init */
/* 1 to run seg_init */
/*==================================*/
/* Init clock Sys clk 96MHz, MCU clk 96MHz, PB clk 48MHz */
SystemInit();
return 1;
}
#pragma language=default
#ifdef __cplusplus
}
#endif