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Update ESP32 port to ESP-IDF release v4.2 and add ESP-IDF version check (#231)
* Revert "Reintroduce Espressif's IDF v4.2 changes to ESP32 port (#193)"
This reverts commit 3d4d17178f.
* Update ESP32 port files to work with ESP-IDF v4.2 as well as ESP-IDF v3.3
Add changes required to support ESP32-S2
* portmacro.h: Change return type of vApplicationSleep to void
This fixes build failure when automatic light sleep is enabled
* prevent header checks for files with different licensing
Co-authored-by: David Chalco <david@chalco.io>
This commit is contained in:
Shubham Kulkarni
GitHub
parent
341e9f06d0
commit
ef4c305244
33 changed files with 327 additions and 6890 deletions
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@ -82,6 +82,7 @@
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#include <xtensa/xtruntime.h>
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#include "esp_timer.h" /* required for FreeRTOS run time stats */
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#include "esp_system.h"
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#include "esp_idf_version.h"
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#include <esp_heap_caps.h>
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@ -134,9 +135,9 @@
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/* owner field values:
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* 0 - Uninitialized (invalid)
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* portMUX_FREE_VAL - Mux is free, can be locked by either CPU
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* CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
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* CORE_ID_REGVAL_PRO / CORE_ID_REGVAL_APP - Mux is locked to the particular core
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*
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* Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
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* Any value other than portMUX_FREE_VAL, CORE_ID_REGVAL_PRO, CORE_ID_REGVAL_APP indicates corruption
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*/
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uint32_t owner;
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@ -283,8 +284,11 @@
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/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
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/*the stack memory to always be internal. */
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#define pvPortMallocTcbMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
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#define pvPortMallocStackMem( size ) heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
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#define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
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#define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
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#define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps)
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#define pvPortMallocStackMem(size) heap_caps_malloc(size, portStackMemoryCaps)
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/*xTaskCreateStatic uses these functions to check incoming memory. */
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#define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
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@ -307,6 +311,14 @@
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uint32_t compare,
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uint32_t * set )
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{
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#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
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__asm__ __volatile__ (
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"WSR %2,SCOMPARE1 \n"
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"S32C1I %0, %1, 0 \n"
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: "=r" ( *set )
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: "r" ( addr ), "r" ( compare ), "0" ( *set )
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);
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#else
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#if ( XCHAL_HAVE_S32C1I > 0 )
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__asm__ __volatile__ (
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"WSR %2,SCOMPARE1 \n"
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@ -333,11 +345,21 @@
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*set = old_value;
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#endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
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#endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
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}
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#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
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void uxPortCompareSetExtram( volatile uint32_t * addr,
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uint32_t compare,
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uint32_t * set );
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#else
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static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
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{
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#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
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compare_and_set_extram(addr, compare, set);
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#endif
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}
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#endif
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/*-----------------------------------------------------------*/
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@ -408,11 +430,37 @@
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#define PRIVILEGED_DATA
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#endif
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bool vApplicationSleep( TickType_t xExpectedIdleTime );
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void vApplicationSleep( TickType_t xExpectedIdleTime );
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void vPortSetStackWatchpoint( void* pxStackStart );
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#define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime )
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/*-----------------------------------------------------------*/
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#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
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/* Architecture specific optimisations. */
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if( configMAX_PRIORITIES > 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
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/*-----------------------------------------------------------*/
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void _xt_coproc_release( volatile void * coproc_sa_base );
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@ -429,6 +477,15 @@
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#define xPortGetFreeHeapSize esp_get_free_heap_size
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#define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size
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#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
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/*
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* Send an interrupt to another core in order to make the task running
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* on it yield for a higher-priority task.
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*/
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void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION;
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#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
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/*
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* Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
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@ -442,6 +499,7 @@
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*/
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BaseType_t xPortInIsrContext();
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/*
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* This function will be called in High prio ISRs. Returns true if the current core was in ISR context
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* before calling into high prio ISR context.
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88
portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h
vendored
Normal file
88
portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h
vendored
Normal file
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@ -0,0 +1,88 @@
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/*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* File adapted to use on IDF FreeRTOS component, extracted
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* originally from zephyr RTOS code base:
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* https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
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*/
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#ifndef __XT_ASM_UTILS_H
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#define __XT_ASM_UTILS_H
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/*
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* SPILL_ALL_WINDOWS
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*
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* Spills all windowed registers (i.e. registers not visible as
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* A0-A15) to their ABI-defined spill regions on the stack.
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*
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* Unlike the Xtensa HAL implementation, this code requires that the
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* EXCM and WOE bit be enabled in PS, and relies on repeated hardware
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* exception handling to do the register spills. The trick is to do a
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* noop write to the high registers, which the hardware will trap
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* (into an overflow exception) in the case where those registers are
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* already used by an existing call frame. Then it rotates the window
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* and repeats until all but the A0-A3 registers of the original frame
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* are guaranteed to be spilled, eventually rotating back around into
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* the original frame. Advantages:
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*
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* - Vastly smaller code size
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*
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* - More easily maintained if changes are needed to window over/underflow
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* exception handling.
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*
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* - Requires no scratch registers to do its work, so can be used safely in any
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* context.
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*
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* - If the WOE bit is not enabled (for example, in code written for
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* the CALL0 ABI), this becomes a silent noop and operates compatbily.
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*
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* - Hilariously it's ACTUALLY FASTER than the HAL routine. And not
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* just a little bit, it's MUCH faster. With a mostly full register
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* file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
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* registers with this vs. 279 (!) to do it with
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* xthal_spill_windows().
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*/
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.macro SPILL_ALL_WINDOWS
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#if XCHAL_NUM_AREGS == 64
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 4
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#elif XCHAL_NUM_AREGS == 32
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a4, a4, a4
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rotw 2
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#else
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#error Unrecognized XCHAL_NUM_AREGS
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#endif
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.endm
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#endif
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@ -45,6 +45,7 @@ NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/xtruntime-frames.h>
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#include <esp_idf_version.h>
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/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
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@ -325,8 +326,19 @@ STRUCT_END(XtSolFrame)
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.endm
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#endif
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#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
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#define CORE_ID_PRO 0xCDCD
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#define CORE_ID_APP 0xABAB
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#else
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#define CORE_ID_REGVAL_PRO 0xCDCD
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#define CORE_ID_REGVAL_APP 0xABAB
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/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */
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#define CORE_ID_PRO CORE_ID_REGVAL_PRO
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/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */
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#define CORE_ID_APP CORE_ID_REGVAL_APP
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#endif
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/*
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-------------------------------------------------------------------------------
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