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Add MB91460 port and demo files.
This commit is contained in:
Richard Barry
parent
e6e5add7d8
commit
eed758709c
30 changed files with 31710 additions and 0 deletions
352
Demo/MB91460_Softune/SRC/vectors.c
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352
Demo/MB91460_Softune/SRC/vectors.c
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/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
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/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
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/* ELIGIBILITY FOR ANY PURPOSES. */
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/* (C) Fujitsu Microelectronics Europe GmbH */
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/*------------------------------------------------------------------------
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VECTORS.C
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- Interrupt level (priority) setting
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- Interrupt vector definition
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31.04.05 1.00 UMa Initial Version
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08.11.05 1.01 MSt SWB Mondeb switch for ICR00 Register added
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27.02.06 1.02 UMa added comment in DefaultIRQHandler
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17.03.06 1.03 UMa comment out ICR01
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28.07.06 1.04 UMa changed comment
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06.10.06 1.05 UMa changed DefaultIRQHandler
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-------------------------------------------------------------------------*/
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#include "mb91467d.h"
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#include "watchdog.h"
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/*------------------------------------------------------------------------
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InitIrqLevels()
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This function pre-sets all interrupt control registers. It can be used
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to set all interrupt priorities in static applications. If this file
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contains assignments to dedicated resources, verify that the
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appropriate controller is used. Not all devices of the MB91460 Series
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offer all recources.
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NOTE: value 31 disables the interrupt and value 16 sets highest priority.
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-------------------------------------------------------------------------*/
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void InitIrqLevels(void)
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{
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/* ICRxx */
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/* Softune Workbench Monitor Debugger is using ext int0 for abort function */
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/* ICR00 = 31; *//* External Interrupt 0 */
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/* External Interrupt 1 */
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ICR01 = 31; /* External Interrupt 2 */
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/* External Interrupt 3 */
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ICR02 = 31; /* External Interrupt 4 */
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/* External Interrupt 5 */
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ICR03 = 31; /* External Interrupt 6 */
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/* External Interrupt 7 */
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ICR04 = 31; /* External Interrupt 8 */
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/* External Interrupt 9 */
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ICR05 = 31; /* External Interrupt 10 */
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/* External Interrupt 11 */
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ICR06 = 31; /* External Interrupt 12 */
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/* External Interrupt 13 */
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ICR07 = 31; /* External Interrupt 14 */
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/* External Interrupt 15 */
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ICR08 = 23; /* Reload Timer 0 */
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/* Reload Timer 1 */
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ICR09 = 31; /* Reload Timer 2 */
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/* Reload Timer 3 */
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ICR10 = 31; /* Reload Timer 4 */
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/* Reload Timer 5 */
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ICR11 = 31; /* Reload Timer 6 */
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/* Reload Timer 7 */
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ICR12 = 31; /* Free Run Timer 0 */
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/* Free Run Timer 1 */
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ICR13 = 31; /* Free Run Timer 2 */
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/* Free Run Timer 3 */
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ICR14 = 31; /* Free Run Timer 4 */
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/* Free Run Timer 5 */
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ICR15 = 31; /* Free Run Timer 6 */
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/* Free Run Timer 7 */
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ICR16 = 31; /* CAN 0 */
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/* CAN 1 */
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ICR17 = 31; /* CAN 2 */
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/* CAN 3 */
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ICR18 = 31; /* CAN 4 */
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/* CAN 5 */
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ICR19 = 31; /* USART (LIN) 0 RX */
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/* USART (LIN) 0 TX */
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ICR20 = 31; /* USART (LIN) 1 RX */
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/* USART (LIN) 1 TX */
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ICR21 = 21; /* USART (LIN) 2 RX */
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/* USART (LIN) 2 TX */
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ICR22 = 31; /* USART (LIN) 3 RX */
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/* USART (LIN) 3 TX */
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ICR23 = 23; /* System Reserved */
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/* Delayed Interrupt */
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ICR24 = 31; /* System Reserved */
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/* System Reserved */
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ICR25 = 31; /* USART (LIN, FIFO) 4 RX */
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/* USART (LIN, FIFO) 4 TX */
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ICR26 = 21; /* USART (LIN, FIFO) 5 RX */
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/* USART (LIN, FIFO) 5 TX */
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ICR27 = 31; /* USART (LIN, FIFO) 6 RX */
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/* USART (LIN, FIFO) 6 TX */
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ICR28 = 31; /* USART (LIN, FIFO) 7 RX */
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/* USART (LIN, FIFO) 7 TX */
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ICR29 = 31; /* I2C 0 / I2C 2 */
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/* I2C 1 / I2C 3 */
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ICR30 = 31; /* USART (LIN, FIFO) 8 RX */
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/* USART (LIN, FIFO) 8 TX */
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ICR31 = 31; /* USART (LIN, FIFO) 9 RX */
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/* USART (LIN, FIFO) 9 TX */
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ICR32 = 31; /* USART (LIN, FIFO) 10 RX */
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/* USART (LIN, FIFO) 10 TX */
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ICR33 = 31; /* USART (LIN, FIFO) 11 RX */
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/* USART (LIN, FIFO) 11 TX */
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ICR34 = 31; /* USART (LIN, FIFO) 12 RX */
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/* USART (LIN, FIFO) 12 TX */
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ICR35 = 31; /* USART (LIN, FIFO) 13 RX */
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/* USART (LIN, FIFO) 13 TX */
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ICR36 = 31; /* USART (LIN, FIFO) 14 RX */
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/* USART (LIN, FIFO) 14 TX */
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ICR37 = 31; /* USART (LIN, FIFO) 15 RX */
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/* USART (LIN, FIFO) 15 TX */
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ICR38 = 31; /* Input Capture 0 */
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/* Input Capture 1 */
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ICR39 = 31; /* Input Capture 2 */
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/* Input Capture 3 */
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ICR40 = 31; /* Input Capture 4 */
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/* Input Capture 5 */
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ICR41 = 31; /* Input Capture 6 */
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/* Input Capture 7 */
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ICR42 = 31; /* Output Compare 0 */
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/* Output Compare 1 */
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ICR43 = 31; /* Output Compare 2 */
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/* Output Compare 3 */
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ICR44 = 31; /* Output Compare 4 */
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/* Output Compare 5 */
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ICR45 = 31; /* Output Compare 6 */
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/* Output Compare 7 */
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ICR46 = 31; /* Sound Generator */
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/* Phase Frequ. Modulator */
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ICR47 = 31; /* System Reserved */
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/* System Reserved */
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ICR48 = 31; /* Prog. Pulse Gen. 0 */
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/* Prog. Pulse Gen. 1 */
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ICR49 = 31; /* Prog. Pulse Gen. 2 */
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/* Prog. Pulse Gen. 3 */
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ICR50 = 31; /* Prog. Pulse Gen. 4 */
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/* Prog. Pulse Gen. 5 */
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ICR51 = 31; /* Prog. Pulse Gen. 6 */
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/* Prog. Pulse Gen. 7 */
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ICR52 = 31; /* Prog. Pulse Gen. 8 */
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/* Prog. Pulse Gen. 9 */
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ICR53 = 31; /* Prog. Pulse Gen. 10 */
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/* Prog. Pulse Gen. 11 */
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ICR54 = 31; /* Prog. Pulse Gen. 12 */
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/* Prog. Pulse Gen. 13 */
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ICR55 = 31; /* Prog. Pulse Gen. 14 */
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/* Prog. Pulse Gen. 15 */
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ICR56 = 31; /* Up/Down Counter 0 */
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/* Up/Down Counter 1 */
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ICR57 = 31; /* Up/Down Counter 2 */
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/* Up/Down Counter 3 */
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ICR58 = 31; /* Real Time Clock */
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/* Calibration Unit */
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ICR59 = 31; /* A/D Converter 0 */
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/* - */
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ICR60 = 31; /* Alarm Comperator 0 */
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/* Alarm Comperator 1 */
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ICR61 = 31; /* Low Volage Detector */
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/* SMC Zero Point 0-5 */
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ICR62 = 31; /* Timebase Overflow */
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/* PLL Clock Gear */
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ICR63 = 31; /* DMA Controller */
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/* Main/Sub OSC stability wait */
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}
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/*------------------------------------------------------------------------
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Prototypes
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Add your own prototypes here. Each vector definition needs is proto-
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type. Either do it here or include a header file containing them.
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-------------------------------------------------------------------------*/
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__interrupt void DefaultIRQHandler (void);
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extern __interrupt void ReloadTimer0_IRQHandler ( void );
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extern __interrupt void vPortYield ( void );
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extern __interrupt void vPortYieldDelayed (void);
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extern __interrupt void UART2_RxISR(void);
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extern __interrupt void UART2_TxISR(void);
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extern __interrupt void UART5_RxISR(void);
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/*------------------------------------------------------------------------
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Vector definiton
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Use following statements to define vectors. All resource related
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vectors are predefined. Remaining software interrupts can be added here
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as well.
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------------------------------------------------------------------------*/
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#pragma intvect 0xBFF8 0 /* (fixed) reset vector */
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#pragma intvect 0x06000000 1 /* (fixed) Mode Byte */
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#pragma intvect DefaultIRQHandler 15 /* Non Maskable Interrupt */
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#pragma intvect DefaultIRQHandler 16 /* External Interrupt 0 */
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#pragma intvect DefaultIRQHandler 17 /* External Interrupt 1 */
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#pragma intvect DefaultIRQHandler 18 /* External Interrupt 2 */
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#pragma intvect DefaultIRQHandler 19 /* External Interrupt 3 */
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#pragma intvect DefaultIRQHandler 20 /* External Interrupt 4 */
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#pragma intvect DefaultIRQHandler 21 /* External Interrupt 5 */
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#pragma intvect DefaultIRQHandler 22 /* External Interrupt 6 */
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#pragma intvect DefaultIRQHandler 23 /* External Interrupt 7 */
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#pragma intvect DefaultIRQHandler 24 /* External Interrupt 8 */
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#pragma intvect DefaultIRQHandler 25 /* External Interrupt 9 */
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#pragma intvect DefaultIRQHandler 26 /* External Interrupt 10 */
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#pragma intvect DefaultIRQHandler 27 /* External Interrupt 11 */
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#pragma intvect DefaultIRQHandler 28 /* External Interrupt 12 */
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#pragma intvect DefaultIRQHandler 29 /* External Interrupt 13 */
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#pragma intvect DefaultIRQHandler 30 /* External Interrupt 14 */
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#pragma intvect DefaultIRQHandler 31 /* External Interrupt 15 */
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#pragma intvect ReloadTimer0_IRQHandler 32 /* Reload Timer 0 */
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#pragma intvect DefaultIRQHandler 33 /* Reload Timer 1 */
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#pragma intvect DefaultIRQHandler 34 /* Reload Timer 2 */
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#pragma intvect DefaultIRQHandler 35 /* Reload Timer 3 */
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#pragma intvect DefaultIRQHandler 36 /* Reload Timer 4 */
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#pragma intvect DefaultIRQHandler 37 /* Reload Timer 5 */
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#pragma intvect DefaultIRQHandler 38 /* Reload Timer 6 */
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#pragma intvect DefaultIRQHandler 39 /* Reload Timer 7 */
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#pragma intvect DefaultIRQHandler 40 /* Free Run Timer 0 */
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#pragma intvect DefaultIRQHandler 41 /* Free Run Timer 1 */
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#pragma intvect DefaultIRQHandler 42 /* Free Run Timer 2 */
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#pragma intvect DefaultIRQHandler 43 /* Free Run Timer 3 */
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#pragma intvect DefaultIRQHandler 44 /* Free Run Timer 4 */
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#pragma intvect DefaultIRQHandler 45 /* Free Run Timer 5 */
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#pragma intvect DefaultIRQHandler 46 /* Free Run Timer 6 */
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#pragma intvect DefaultIRQHandler 47 /* Free Run Timer 7 */
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#pragma intvect DefaultIRQHandler 48 /* CAN 0 */
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#pragma intvect DefaultIRQHandler 49 /* CAN 1 */
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#pragma intvect DefaultIRQHandler 50 /* CAN 2 */
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#pragma intvect DefaultIRQHandler 51 /* CAN 3 */
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#pragma intvect DefaultIRQHandler 52 /* CAN 4 */
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#pragma intvect DefaultIRQHandler 53 /* CAN 5 */
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#pragma intvect DefaultIRQHandler 54 /* USART (LIN) 0 RX */
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#pragma intvect DefaultIRQHandler 55 /* USART (LIN) 0 TX */
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#pragma intvect DefaultIRQHandler 56 /* USART (LIN) 1 RX */
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#pragma intvect DefaultIRQHandler 57 /* USART (LIN) 1 TX */
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#pragma intvect UART2_RxISR 58 /* USART (LIN) 2 RX */
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#pragma intvect UART2_TxISR 59 /* USART (LIN) 2 TX */
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#pragma intvect DefaultIRQHandler 60 /* USART (LIN) 3 RX */
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#pragma intvect DefaultIRQHandler 61 /* USART (LIN) 3 TX */
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#pragma intvect DefaultIRQHandler 62 /* System Reserved */
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#pragma intvect vPortYieldDelayed 63 /* Delayed Interrupt */
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#pragma intvect vPortYield 64 /* INT 64 */
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#pragma intvect DefaultIRQHandler 65 /* System Reserved */
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#pragma intvect DefaultIRQHandler 66 /* USART (LIN, FIFO) 4 RX */
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#pragma intvect DefaultIRQHandler 67 /* USART (LIN, FIFO) 4 TX */
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#pragma intvect UART5_RxISR 68 /* USART (LIN, FIFO) 5 RX */
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#pragma intvect DefaultIRQHandler 69 /* USART (LIN, FIFO) 5 TX */
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#pragma intvect DefaultIRQHandler 70 /* USART (LIN, FIFO) 6 RX */
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#pragma intvect DefaultIRQHandler 71 /* USART (LIN, FIFO) 6 TX */
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#pragma intvect DefaultIRQHandler 72 /* USART (LIN, FIFO) 7 RX */
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#pragma intvect DefaultIRQHandler 73 /* USART (LIN, FIFO) 7 TX */
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#pragma intvect DefaultIRQHandler 74 /* I2C 0 / I2C 2 */
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#pragma intvect DefaultIRQHandler 75 /* I2C 1 / I2C 3 */
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#pragma intvect DefaultIRQHandler 76 /* USART (LIN, FIFO) 8 RX */
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#pragma intvect DefaultIRQHandler 77 /* USART (LIN, FIFO) 8 TX */
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#pragma intvect DefaultIRQHandler 78 /* USART (LIN, FIFO) 9 RX */
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#pragma intvect DefaultIRQHandler 79 /* USART (LIN, FIFO) 9 TX */
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#pragma intvect DefaultIRQHandler 80 /* USART (LIN, FIFO) 10 RX */
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#pragma intvect DefaultIRQHandler 81 /* USART (LIN, FIFO) 10 TX */
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#pragma intvect DefaultIRQHandler 82 /* USART (LIN, FIFO) 11 RX */
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#pragma intvect DefaultIRQHandler 83 /* USART (LIN, FIFO) 11 TX */
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#pragma intvect DefaultIRQHandler 84 /* USART (LIN, FIFO) 12 RX */
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#pragma intvect DefaultIRQHandler 85 /* USART (LIN, FIFO) 12 TX */
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#pragma intvect DefaultIRQHandler 86 /* USART (LIN, FIFO) 13 RX */
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#pragma intvect DefaultIRQHandler 87 /* USART (LIN, FIFO) 13 TX */
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#pragma intvect DefaultIRQHandler 88 /* USART (LIN, FIFO) 14 RX */
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#pragma intvect DefaultIRQHandler 89 /* USART (LIN, FIFO) 14 TX */
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#pragma intvect DefaultIRQHandler 90 /* USART (LIN, FIFO) 15 RX */
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#pragma intvect DefaultIRQHandler 91 /* USART (LIN, FIFO) 15 TX */
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#pragma intvect DefaultIRQHandler 92 /* Input Capture 0 */
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#pragma intvect DefaultIRQHandler 93 /* Input Capture 1 */
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#pragma intvect DefaultIRQHandler 94 /* Input Capture 2 */
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#pragma intvect DefaultIRQHandler 95 /* Input Capture 3 */
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#pragma intvect DefaultIRQHandler 96 /* Input Capture 4 */
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#pragma intvect DefaultIRQHandler 97 /* Input Capture 5 */
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#pragma intvect DefaultIRQHandler 98 /* Input Capture 6 */
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#pragma intvect DefaultIRQHandler 99 /* Input Capture 7 */
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#pragma intvect DefaultIRQHandler 100 /* Output Compare 0 */
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#pragma intvect DefaultIRQHandler 101 /* Output Compare 1 */
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#pragma intvect DefaultIRQHandler 102 /* Output Compare 2 */
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#pragma intvect DefaultIRQHandler 103 /* Output Compare 3 */
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#pragma intvect DefaultIRQHandler 104 /* Output Compare 4 */
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#pragma intvect DefaultIRQHandler 105 /* Output Compare 5 */
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#pragma intvect DefaultIRQHandler 106 /* Output Compare 6 */
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#pragma intvect DefaultIRQHandler 107 /* Output Compare 7 */
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#pragma intvect DefaultIRQHandler 108 /* Sound Generator */
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#pragma intvect DefaultIRQHandler 109 /* Phase Frequ. Modulator */
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#pragma intvect DefaultIRQHandler 110 /* System Reserved */
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#pragma intvect DefaultIRQHandler 111 /* System Reserved */
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#pragma intvect DefaultIRQHandler 112 /* Prog. Pulse Gen. 0 */
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#pragma intvect DefaultIRQHandler 113 /* Prog. Pulse Gen. 1 */
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#pragma intvect DefaultIRQHandler 114 /* Prog. Pulse Gen. 2 */
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#pragma intvect DefaultIRQHandler 115 /* Prog. Pulse Gen. 3 */
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#pragma intvect DefaultIRQHandler 116 /* Prog. Pulse Gen. 4 */
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#pragma intvect DefaultIRQHandler 117 /* Prog. Pulse Gen. 5 */
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#pragma intvect DefaultIRQHandler 118 /* Prog. Pulse Gen. 6 */
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#pragma intvect DefaultIRQHandler 119 /* Prog. Pulse Gen. 7 */
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#pragma intvect DefaultIRQHandler 120 /* Prog. Pulse Gen. 8 */
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#pragma intvect DefaultIRQHandler 121 /* Prog. Pulse Gen. 9 */
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#pragma intvect DefaultIRQHandler 122 /* Prog. Pulse Gen. 10 */
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#pragma intvect DefaultIRQHandler 123 /* Prog. Pulse Gen. 11 */
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#pragma intvect DefaultIRQHandler 124 /* Prog. Pulse Gen. 12 */
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#pragma intvect DefaultIRQHandler 125 /* Prog. Pulse Gen. 13 */
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#pragma intvect DefaultIRQHandler 126 /* Prog. Pulse Gen. 14 */
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#pragma intvect DefaultIRQHandler 127 /* Prog. Pulse Gen. 15 */
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#pragma intvect DefaultIRQHandler 128 /* Up/Down Counter 0 */
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#pragma intvect DefaultIRQHandler 129 /* Up/Down Counter 1 */
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#pragma intvect DefaultIRQHandler 130 /* Up/Down Counter 2 */
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#pragma intvect DefaultIRQHandler 131 /* Up/Down Counter 3 */
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#pragma intvect DefaultIRQHandler 132 /* Real Time Clock */
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#pragma intvect DefaultIRQHandler 133 /* Calibration Unit */
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#pragma intvect DefaultIRQHandler 134 /* A/D Converter 0 */
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#pragma intvect DefaultIRQHandler 135 /* - */
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#pragma intvect DefaultIRQHandler 136 /* Alarm Comperator 0 */
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#pragma intvect DefaultIRQHandler 137 /* Alarm Comperator 1 */
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#pragma intvect DefaultIRQHandler 138 /* Low Volage Detector */
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#pragma intvect DefaultIRQHandler 139 /* SMC Zero Point 0-5 */
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#pragma intvect DefaultIRQHandler 140 /* Timebase Overflow */
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#pragma intvect DefaultIRQHandler 141 /* PLL Clock Gear */
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#pragma intvect DefaultIRQHandler 142 /* DMA Controller */
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#pragma intvect DefaultIRQHandler 143 /* Main/Sub OSC stability wait */
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#pragma intvect 0xFFFFFFFF 144 /* Boot Sec. Vector (MB91V460A) */
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/*------------------------------------------------------------------------
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DefaultIRQHandler()
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This function is a placeholder for all vector definitions. Either use
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your own placeholder or add necessary code here.
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-------------------------------------------------------------------------*/
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__interrupt
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void DefaultIRQHandler (void)
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{
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/* RB_SYNC; */ /* Synchronisation with R-Bus */
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/* May be required, if there is */
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/* no R-Bus access after the */
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/* reset of the interrupt flag */
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__DI(); /* disable interrupts */
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while(1)
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Kick_Watchdog(); /* feed hardware watchdog */
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/* halt system */
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}
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