mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Add autogenerated test source code to the new MicroBlaze project.
This commit is contained in:
Richard Barry
parent
d4670870fb
commit
ee4659b678
41 changed files with 12318 additions and 121 deletions
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@ -1,2 +1,2 @@
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<SAV MODE="TREE" VIEW="ADDRESS"/>
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<SAV MODE="TREE" VIEW="BUSINTERFACE"/>
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@ -31,7 +31,7 @@
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_ethernetlite</arg>, INSTANCE: <arg fmt="%s" index="2">Ethernet_Lite</arg> - <arg fmt="%s" index="3">This design requires design constraints to guarantee performance.
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Please refer to the data sheet for details.
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The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation.</arg> - <arg fmt="%s" index="4">C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\system.mhs line 324</arg>
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The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation.</arg> - <arg fmt="%s" index="4">C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.mhs line 324</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_v10</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_ilmb</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_LMB_NUM_SLAVES</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70</arg>
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@ -121,7 +121,7 @@ The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethe
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_NUM_INTR_INPUTS</arg> value to <arg fmt="%s" index="6">4</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 71</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_INTR</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111011</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72</arg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_INTR</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111110111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_EDGE</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 73</arg>
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@ -1,9 +1,9 @@
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<?xml version='1.0' encoding='UTF-8'?>
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<report-views version="2.0" >
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<header>
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<DateModified>2011-05-31T10:04:43</DateModified>
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<DateModified>2011-05-31T17:38:56</DateModified>
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<ModuleName>system</ModuleName>
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<SummaryTimeStamp>2011-05-31T10:04:43</SummaryTimeStamp>
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<SummaryTimeStamp>2011-05-31T17:38:55</SummaryTimeStamp>
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<SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
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<FilterFile>filter.filter</FilterFile>
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<SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>
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@ -1,48 +1,8 @@
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<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Tue May 31 10:04:42 2011">
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<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Tue May 31 17:38:54 2011">
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<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
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<EXTERNALPORTS>
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<PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
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<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
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<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
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<PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
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<PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
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<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
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<PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
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<PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
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<PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
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<PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
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<PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
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<PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
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<PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
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<PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
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<PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
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<PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
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<PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
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<PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
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<PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
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<PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
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<PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
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<PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
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<PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
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<PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
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<PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
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<PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
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<PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
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<PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
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<PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
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<PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
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<PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
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<PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
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<PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
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<PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
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<PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
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</EXTERNALPORTS>
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<MODULES>
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<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
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<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
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@ -50,7 +10,6 @@
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
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@ -271,6 +230,7 @@
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</SLAVES>
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</MEMRANGE>
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</MEMORYMAP>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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</MODULE>
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<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
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<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
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@ -278,7 +238,6 @@
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
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@ -499,6 +458,7 @@
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</SLAVES>
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</MEMRANGE>
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</MEMORYMAP>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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</MODULE>
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<MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
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<DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
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@ -506,7 +466,6 @@
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
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@ -2519,6 +2478,9 @@
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</PORTMAPS>
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</BUSINTERFACE>
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</BUSINTERFACES>
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<INTERRUPTINFO TYPE="TARGET">
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<SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
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</INTERRUPTINFO>
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<MEMORYMAP>
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<MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
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<ACCESSROUTE>
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@ -2583,9 +2545,7 @@
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<PERIPHERAL INSTANCE="microblaze_0_intc"/>
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<PERIPHERAL INSTANCE="MCB_DDR3"/>
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</PERIPHERALS>
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<INTERRUPTINFO TYPE="TARGET">
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<SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
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</INTERRUPTINFO>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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</MODULE>
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<MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
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<DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
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@ -2593,7 +2553,6 @@
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
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<PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
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@ -2631,6 +2590,7 @@
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<IOINTERFACES>
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<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
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</IOINTERFACES>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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</MODULE>
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<MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
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<DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
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<PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
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@ -2676,6 +2635,7 @@
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<IOINTERFACES>
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<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
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</IOINTERFACES>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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</MODULE>
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<MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
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<DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
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<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
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</SLAVES>
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</MEMRANGE>
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</MEMORYMAP>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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</MODULE>
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<MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
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<DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
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@ -2921,7 +2881,6 @@
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<DOCUMENTATION>
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<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
|
||||
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
|
||||
|
|
@ -3152,6 +3111,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
|
||||
<DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
|
||||
|
|
@ -3159,7 +3119,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"/>
|
||||
<PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
|
||||
|
|
@ -3207,6 +3166,7 @@
|
|||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
|
||||
<DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
|
||||
|
|
@ -3214,7 +3174,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t"/>
|
||||
<PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
|
||||
|
|
@ -3276,6 +3235,7 @@
|
|||
<IOINTERFACES>
|
||||
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
|
||||
</IOINTERFACES>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
|
||||
<DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
|
||||
|
|
@ -3283,7 +3243,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t"/>
|
||||
|
|
@ -3409,6 +3368,7 @@
|
|||
<PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
|
||||
</PORTS>
|
||||
<BUSINTERFACES/>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
|
||||
<DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
|
||||
|
|
@ -3416,7 +3376,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
<PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/>
|
||||
|
|
@ -3775,6 +3734,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
|
||||
<DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
|
||||
|
|
@ -3782,7 +3742,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
|
||||
|
|
@ -3862,6 +3821,9 @@
|
|||
</PORTMAPS>
|
||||
</IOINTERFACE>
|
||||
</IOINTERFACES>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
|
||||
</INTERRUPTINFO>
|
||||
<MEMORYMAP>
|
||||
<MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
||||
<SLAVES>
|
||||
|
|
@ -3869,9 +3831,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
|
||||
</INTERRUPTINFO>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
|
||||
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
|
||||
|
|
@ -3879,7 +3839,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/>
|
||||
|
|
@ -3983,6 +3942,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
|
||||
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
|
||||
|
|
@ -3990,7 +3950,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/>
|
||||
|
|
@ -4087,6 +4046,9 @@
|
|||
</PORTMAPS>
|
||||
</IOINTERFACE>
|
||||
</IOINTERFACES>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
|
||||
</INTERRUPTINFO>
|
||||
<MEMORYMAP>
|
||||
<MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
||||
<SLAVES>
|
||||
|
|
@ -4094,9 +4056,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
|
||||
</INTERRUPTINFO>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
|
||||
<DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
|
||||
|
|
@ -4104,7 +4064,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
|
||||
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
|
||||
|
|
@ -4856,6 +4815,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
|
||||
<DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
|
||||
|
|
@ -4863,7 +4823,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
|
|
@ -5024,6 +4983,9 @@
|
|||
</PORTMAPS>
|
||||
</IOINTERFACE>
|
||||
</IOINTERFACES>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
|
||||
</INTERRUPTINFO>
|
||||
<MEMORYMAP>
|
||||
<MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
|
||||
<SLAVES>
|
||||
|
|
@ -5031,9 +4993,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
|
||||
</INTERRUPTINFO>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
|
||||
<DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
|
||||
|
|
@ -5041,7 +5001,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
|
|
@ -5124,6 +5083,9 @@
|
|||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
|
||||
</INTERRUPTINFO>
|
||||
<MEMORYMAP>
|
||||
<MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
||||
<SLAVES>
|
||||
|
|
@ -5131,9 +5093,7 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<INTERRUPTINFO TYPE="SOURCE">
|
||||
<TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
|
||||
</INTERRUPTINFO>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
<MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
|
||||
<DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
|
||||
|
|
@ -5141,7 +5101,6 @@
|
|||
<DOCUMENTATION>
|
||||
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
|
||||
</DOCUMENTATION>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
|
||||
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000"/>
|
||||
|
|
@ -5170,7 +5129,7 @@
|
|||
<DESCRIPTION>Interrupt Request Output</DESCRIPTION>
|
||||
</PORT>
|
||||
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
|
||||
<PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt & Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
|
||||
<PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
|
||||
<SIGNALS>
|
||||
<SIGNAL NAME="RS232_Uart_1_Interrupt"/>
|
||||
<SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
|
||||
|
|
@ -5223,6 +5182,13 @@
|
|||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
<INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
|
||||
<SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="0" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
|
||||
<SOURCE INSTANCE="Ethernet_Lite" PRIORITY="1" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
|
||||
<SOURCE INSTANCE="axi_timer_0" PRIORITY="2" SIGNAME="axi_timer_0_Interrupt"/>
|
||||
<SOURCE INSTANCE="RS232_Uart_1" PRIORITY="3" SIGNAME="RS232_Uart_1_Interrupt"/>
|
||||
<TARGET INSTANCE="microblaze_0"/>
|
||||
</INTERRUPTINFO>
|
||||
<MEMORYMAP>
|
||||
<MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
||||
<SLAVES>
|
||||
|
|
@ -5230,14 +5196,49 @@
|
|||
</SLAVES>
|
||||
</MEMRANGE>
|
||||
</MEMORYMAP>
|
||||
<INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
|
||||
<SOURCE INSTANCE="RS232_Uart_1" PRIORITY="0" SIGNAME="RS232_Uart_1_Interrupt"/>
|
||||
<SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="1" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
|
||||
<SOURCE INSTANCE="Ethernet_Lite" PRIORITY="2" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
|
||||
<SOURCE INSTANCE="axi_timer_0" PRIORITY="3" SIGNAME="axi_timer_0_Interrupt"/>
|
||||
<TARGET INSTANCE="microblaze_0"/>
|
||||
</INTERRUPTINFO>
|
||||
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
||||
</MODULE>
|
||||
</MODULES>
|
||||
|
||||
<EXTERNALPORTS>
|
||||
<PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
|
||||
<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
|
||||
<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
|
||||
<PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
|
||||
<PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
|
||||
<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
|
||||
<PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
|
||||
<PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
|
||||
<PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
|
||||
<PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
|
||||
<PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
|
||||
<PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
|
||||
<PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
|
||||
<PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
|
||||
<PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
|
||||
<PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
|
||||
<PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
|
||||
<PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
|
||||
<PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
|
||||
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
|
||||
<PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
|
||||
<PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
|
||||
<PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
|
||||
<PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
|
||||
<PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
|
||||
<PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
|
||||
<PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
|
||||
<PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
|
||||
<PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
|
||||
<PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
|
||||
<PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
|
||||
<PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
|
||||
<PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
|
||||
<PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
|
||||
<PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
|
||||
<PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
|
||||
<PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
|
||||
<PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
|
||||
</EXTERNALPORTS>
|
||||
|
||||
</EDKSYSTEM>
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
|
||||
<FILTERS>
|
||||
|
||||
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
|
||||
|
|
@ -93,8 +94,8 @@
|
|||
</SET>
|
||||
|
||||
<SET CLASS="PROJECT" VIEW_ID="PORT">
|
||||
<HEADERS>
|
||||
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
|
||||
<HEADERS HSCROLL="0" VSCROLL="0">
|
||||
<VARIABLE COL_INDEX="0" COL_WIDTH="400" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
|
||||
</HEADERS>
|
||||
<SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
|
||||
<VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
|
||||
|
|
|
|||
|
|
@ -9,14 +9,14 @@
|
|||
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="4" COL_WIDTH="154" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="4" COL_WIDTH="492" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
|
||||
</HEADERS>
|
||||
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
|
||||
<STATUS>
|
||||
<SELECTIONS>
|
||||
<VARIABLE ID="microblaze_0"/>
|
||||
<VARIABLE ID="microblaze_0_intc"/>
|
||||
</SELECTIONS>
|
||||
</STATUS>
|
||||
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
|
||||
|
|
@ -83,37 +83,74 @@
|
|||
</SET>
|
||||
|
||||
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
|
||||
<HEADERS>
|
||||
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
|
||||
<HEADERS HSCROLL="0" VSCROLL="0">
|
||||
<VARIABLE COL_INDEX="0" COL_WIDTH="217" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="1" COL_WIDTH="652" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
|
||||
</HEADERS>
|
||||
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
|
||||
<SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
|
||||
<SET ID="RS232_Uart_1" IS_EXPANDED="TRUE"/>
|
||||
<SET ID="microblaze_0_intc" IS_EXPANDED="TRUE">
|
||||
<SET ID="S_AXI" IS_EXPANDED="TRUE"/>
|
||||
</SET>
|
||||
<STATUS>
|
||||
<SELECTIONS>
|
||||
<VARIABLE ID="IRQ" PARENT="microblaze_0_intc"/>
|
||||
</SELECTIONS>
|
||||
</STATUS>
|
||||
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
|
||||
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
|
||||
<VARIABLE ID="axi4_0" ROW_INDEX="1"/>
|
||||
<VARIABLE ID="axi4lite_0" ROW_INDEX="2"/>
|
||||
<VARIABLE ID="microblaze_0" IS_EXPANDED="TRUE" ROW_INDEX="5"/>
|
||||
<VARIABLE ID="microblaze_0_ilmb" ROW_INDEX="4"/>
|
||||
<VARIABLE ID="microblaze_0_dlmb" ROW_INDEX="3"/>
|
||||
<VARIABLE ID="microblaze_0_i_bram_ctrl" ROW_INDEX="8"/>
|
||||
<VARIABLE ID="microblaze_0_d_bram_ctrl" ROW_INDEX="7"/>
|
||||
<VARIABLE ID="microblaze_0_bram_block" ROW_INDEX="6"/>
|
||||
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="18"/>
|
||||
<VARIABLE ID="clock_generator_0" ROW_INDEX="17"/>
|
||||
<VARIABLE ID="debug_module" ROW_INDEX="10"/>
|
||||
<VARIABLE ID="RS232_Uart_1" IS_EXPANDED="TRUE" ROW_INDEX="16"/>
|
||||
<VARIABLE ID="LEDs_4Bits" ROW_INDEX="13"/>
|
||||
<VARIABLE ID="Push_Buttons_4Bits" ROW_INDEX="14"/>
|
||||
<VARIABLE ID="MCB_DDR3" ROW_INDEX="9"/>
|
||||
<VARIABLE ID="Ethernet_Lite" ROW_INDEX="12"/>
|
||||
<VARIABLE ID="axi_timer_0" ROW_INDEX="15"/>
|
||||
<VARIABLE ID="microblaze_0_intc" IS_EXPANDED="TRUE" ROW_INDEX="11"/>
|
||||
</SEQUENCES>
|
||||
</SET>
|
||||
|
||||
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
|
||||
<HEADERS>
|
||||
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
|
||||
<HEADERS HSCROLL="0" VSCROLL="0">
|
||||
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="7" COL_WIDTH="192" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="8" COL_WIDTH="200" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
|
||||
</HEADERS>
|
||||
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
|
||||
<SET ID="microblaze_0_intc" IS_EXPANDED="TRUE"/>
|
||||
<STATUS>
|
||||
<SELECTIONS>
|
||||
<VARIABLE ID="microblaze_0_intc"/>
|
||||
</SELECTIONS>
|
||||
</STATUS>
|
||||
</SET>
|
||||
|
||||
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
|
||||
|
|
@ -166,10 +203,11 @@
|
|||
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="9" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
|
||||
<VARIABLE COL_INDEX="9" COL_WIDTH="605" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
|
||||
</HEADERS>
|
||||
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
|
||||
<SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
|
||||
<STATUS IS_EXPANDED="TRUE">
|
||||
<STATUS>
|
||||
<SELECTIONS/>
|
||||
</STATUS>
|
||||
</SET>
|
||||
|
|
|
|||
|
|
@ -32,11 +32,7 @@
|
|||
<TR ALIGN=LEFT><TD>Libgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>System Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject\system.log'>System Log File</A></TD><TD>Tue 31. May 18:23:42 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
|
@ -62,5 +58,5 @@
|
|||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 05/31/2011 - 10:04:43</center>
|
||||
<br><center><b>Date Generated:</b> 05/31/2011 - 18:23:42</center>
|
||||
</BODY></HTML>
|
||||
|
|
@ -382,6 +382,6 @@ BEGIN axi_intc
|
|||
BUS_INTERFACE S_AXI = axi4lite_0
|
||||
PORT IRQ = microblaze_0_interrupt
|
||||
PORT S_AXI_ACLK = clk_50_0000MHzPLL0
|
||||
PORT INTR = RS232_Uart_1_Interrupt & Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt
|
||||
PORT INTR = Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt & RS232_Uart_1_Interrupt
|
||||
END
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue