mirror of
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Update header files to include CMSIS files.
This commit is contained in:
Richard Barry
parent
fe9d735641
commit
ec5827a601
109
Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev.h
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109
Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev.h
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@ -0,0 +1,109 @@
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/*
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* @file: EthDev.h
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* @purpose: Ethernet Device Definitions
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* @version: V1.10
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* @date: 24. Feb. 2009
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*----------------------------------------------------------------------------
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-M3
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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#ifndef _ETHDEV__H
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#define _ETHDEV__H
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#ifndef NULL
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#define NULL 0
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#endif
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/*----------------------------------------------------------------------------
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Ethernet Device Defines
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*----------------------------------------------------------------------------*/
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#define EthDev_ADDR_SIZE 6 /*!< Ethernet Address size in bytes */
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#define EthDev_MTU_SIZE 1514 /*!< Maximum Transmission Unit */
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/*----------------------------------------------------------------------------
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Ethernet Device Configuration and Control Command Defines
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*----------------------------------------------------------------------------*/
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typedef enum {
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EthDev_LINK_DOWN = 0, /*!< Ethernet link not established */
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EthDev_LINK_UP = 1, /*!< Ethernet link established */
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} EthDev_LINK;
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typedef enum {
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EthDev_SPEED_10M = 0, /*!< 10.0 Mbps link speed */
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EthDev_SPEED_100M = 1, /*!< 100.0 Mbps link speed */
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EthDev_SPEED_1000M = 2, /*!< 1.0 Gbps link speed */
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} EthDev_SPEED;
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typedef enum {
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EthDev_DUPLEX_HALF = 0, /*!< Link half duplex */
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EthDev_DUPLEX_FULL = 1, /*!< Link full duplex */
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} EthDev_DUPLEX;
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typedef enum {
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EthDev_MODE_AUTO = 0,
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EthDev_MODE_10M_FULL = 1,
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EthDev_MODE_10M_HALF = 2,
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EthDev_MODE_100M_FULL = 3,
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EthDev_MODE_100M_HALF = 4,
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EthDev_MODE_1000M_FULL = 5,
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EthDev_MODE_1000M_HALF = 6,
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} EthDev_MODE;
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typedef struct {
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EthDev_LINK Link : 1;
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EthDev_DUPLEX Duplex : 1;
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EthDev_SPEED Speed : 2;
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} EthDev_STATUS;
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/*----------------------------------------------------------------------------
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Ethernet Device IO Block Structure
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*----------------------------------------------------------------------------*/
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typedef struct {
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/* Initialized by the user application before call to Init. */
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EthDev_MODE Mode;
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unsigned char HwAddr[EthDev_ADDR_SIZE];
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void *(*RxFrame) (int size);
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void (*RxFrameReady) (int size);
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/* Initialized by Ethernet driver. */
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int (*Init) (void);
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int (*UnInit) (void);
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int (*SetMCFilter)(int NumHwAddr, unsigned char *pHwAddr);
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int (*TxFrame) (void *pData, int size);
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void (*Lock) (void);
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void (*UnLock) (void);
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EthDev_STATUS (*LinkChk) (void);
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} EthDev_IOB;
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// prototypes
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portBASE_TYPE Init_EMAC(void);
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unsigned short ReadFrameBE_EMAC(void);
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void CopyToFrame_EMAC(void *Source, unsigned int Size);
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void CopyFromFrame_EMAC(void *Dest, unsigned short Size);
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void DummyReadFrame_EMAC(unsigned short Size);
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unsigned short StartReadFrame(void);
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void EndReadFrame(void);
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unsigned int CheckFrameReceived(void);
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void RequestSend(void);
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unsigned int Rdy4Tx(void);
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void DoSend_EMAC(unsigned short FrameSize);
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void vEMACWaitForInput( void );
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unsigned int uiGetEMACRxData( unsigned char *ucBuffer );
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#endif
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@ -1,39 +1,64 @@
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/*----------------------------------------------------------------------------
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* LPC2378 Ethernet Definitions
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/*
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* @file: EthDev_LPC17xx.h
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* @purpose: Ethernet Device Definitions for NXP LPC17xx
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* @version: V0.01
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* @date: 14. May 2009
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*----------------------------------------------------------------------------
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* Name: EMAC.H
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* Purpose: Philips LPC2378 EMAC hardware definitions
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*----------------------------------------------------------------------------
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* Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.
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*---------------------------------------------------------------------------*/
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#ifndef __EMAC_H
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#define __EMAC_H
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-M3
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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/* MAC address definition. The MAC address must be unique on the network. */
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#define emacETHADDR0 0
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#define emacETHADDR1 0xbd
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#define emacETHADDR2 0x33
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#define emacETHADDR3 0x02
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#define emacETHADDR4 0x64
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#define emacETHADDR5 0x24
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#ifndef __ETHDEV_LPC17XX_H
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#define __ETHDEV_LPC17XX_H
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#include <stdint.h>
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/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
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#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
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#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */
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#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
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#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
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#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
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/* EMAC variables located in 16K Ethernet SRAM */
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//extern unsigned char xEthDescriptors[];
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#define RX_DESC_BASE (0x2007c000UL)
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#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
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#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
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#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
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#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
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typedef struct { /* RX Descriptor struct */
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uint32_t Packet;
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uint32_t Ctrl;
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} RX_DESC_TypeDef;
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typedef struct { /* RX Status struct */
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uint32_t Info;
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uint32_t HashCRC;
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} RX_STAT_TypeDef;
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typedef struct { /* TX Descriptor struct */
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uint32_t Packet;
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uint32_t Ctrl;
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} TX_DESC_TypeDef;
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typedef struct { /* TX Status struct */
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uint32_t Info;
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} TX_STAT_TypeDef;
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/* EMAC variables located in AHB SRAM bank 1*/
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#define AHB_SRAM_BANK1_BASE 0x2007c000UL
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#define RX_DESC_BASE (AHB_SRAM_BANK1_BASE )
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#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_DESC_TypeDef */
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#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_STAT_TypeDef */
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#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*(2*4)) /* 2 * uint32_t, see TX_DESC_TypeDef */
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#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*(1*4)) /* 1 * uint32_t, see TX_STAT_TypeDef */
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#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
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#define TX_BUF_END (TX_BUF_BASE + NUM_TX_FRAG*ETH_FRAG_SIZE)
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/* RX and TX descriptor and status definitions. */
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#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
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@ -46,6 +71,8 @@
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#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
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#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
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/* MAC Configuration Register 1 */
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#define MAC1_REC_EN 0x00000001 /* Receive Enable */
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#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
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@ -70,7 +97,6 @@
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#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
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#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
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#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
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#undef MAC2_NO_BACKOFF /* Remove compiler warning. */
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#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
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#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
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#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
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@ -86,7 +112,6 @@
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#define CLRT_DEF 0x0000370F /* Default value */
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/* PHY Support Register */
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#undef SUPP_SPEED /* Remove compiler warning. */
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#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
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#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
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@ -98,13 +123,11 @@
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/* MII Management Configuration Register */
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#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
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#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
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#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
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#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
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#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
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/* MII Management Command Register */
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#undef MCMD_READ /* Remove compiler warning. */
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#define MCMD_READ 0x00000001 /* MII Read */
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#undef MCMD_SCAN /* Remove compiler warning. */
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#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
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#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
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@ -115,7 +138,6 @@
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#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
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/* MII Management Indicators Register */
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#undef MIND_BUSY /* Remove compiler warning. */
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#define MIND_BUSY 0x00000001 /* MII is Busy */
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#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
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#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
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@ -267,6 +289,9 @@
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#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
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#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
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/* ENET Device Revision ID */
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#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
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/* DP83848C PHY Registers */
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#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
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#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
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@ -300,25 +325,8 @@
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#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
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#define DP83848C_ID 0x20005C90 /* PHY Identifier */
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// prototypes
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portBASE_TYPE Init_EMAC(void);
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unsigned short ReadFrameBE_EMAC(void);
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void CopyToFrame_EMAC(void *Source, unsigned int Size);
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void CopyFromFrame_EMAC(void *Dest, unsigned short Size);
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void DummyReadFrame_EMAC(unsigned short Size);
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unsigned short StartReadFrame(void);
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void EndReadFrame(void);
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unsigned int CheckFrameReceived(void);
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void RequestSend(void);
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unsigned int Rdy4Tx(void);
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void DoSend_EMAC(unsigned short FrameSize);
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void vEMACWaitForInput( void );
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unsigned int uiGetEMACRxData( unsigned char *ucBuffer );
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#endif
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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@ -1,465 +0,0 @@
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/******************************************************************
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***** *****
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***** Ver.: 1.0 *****
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***** Date: 07/05/2001 *****
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***** Auth: Andreas Dannenberg *****
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***** HTWK Leipzig *****
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***** university of applied sciences *****
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***** Germany *****
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***** Func: ethernet packet-driver for use with LAN- *****
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***** controller CS8900 from Crystal/Cirrus Logic *****
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***** *****
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***** Keil: Module modified for use with Philips *****
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***** LPC2378 EMAC Ethernet controller *****
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***** *****
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******************************************************************/
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/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#include "emac.h"
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#include "LPC17xx_defs.h"
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#define configPINSEL2_VALUE 0x50150105
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/* The semaphore used to wake the uIP task when data arives. */
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xSemaphoreHandle xEMACSemaphore = NULL;
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static unsigned short *rptr;
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static unsigned short *tptr;
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static unsigned short SwapBytes( unsigned short Data )
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{
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return( Data >> 8 ) | ( Data << 8 );
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}
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// Keil: function added to write PHY
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int write_PHY( int PhyReg, int Value )
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{
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MWTD = Value;
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/* Wait utill operation completed */
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tout = 0;
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for( tout = 0; tout < uiMaxTime; tout++ )
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{
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if( (MAC_MIND & MIND_BUSY) == 0 )
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{
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break;
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}
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vTaskDelay( 2 );
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}
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if( tout < uiMaxTime )
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{
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return pdPASS;
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}
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else
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{
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return pdFAIL;
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}
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}
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// Keil: function added to read PHY
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unsigned short read_PHY( unsigned char PhyReg, portBASE_TYPE *pxStatus )
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{
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MCMD = MCMD_READ;
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/* Wait until operation completed */
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tout = 0;
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for( tout = 0; tout < uiMaxTime; tout++ )
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{
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if( (MAC_MIND & MIND_BUSY) == 0 )
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{
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break;
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}
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vTaskDelay( 2 );
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}
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MAC_MCMD = 0;
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if( tout >= uiMaxTime )
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{
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*pxStatus = pdFAIL;
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}
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return( MAC_MRDD );
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}
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// Keil: function added to initialize Rx Descriptors
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void rx_descr_init( void )
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{
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unsigned int i;
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for( i = 0; i < NUM_RX_FRAG; i++ )
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{
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RX_DESC_PACKET( i ) = RX_BUF( i );
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RX_DESC_CTRL( i ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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RX_STAT_INFO( i ) = 0;
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RX_STAT_HASHCRC( i ) = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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MAC_RXDESCRIPTOR = RX_DESC_BASE;
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MAC_RXSTATUS = RX_STAT_BASE;
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MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;
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/* Rx Descriptors Point to 0 */
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MAC_RXCONSUMEINDEX = 0;
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}
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||||
// Keil: function added to initialize Tx Descriptors
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void tx_descr_init( void )
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{
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unsigned int i;
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for( i = 0; i < NUM_TX_FRAG; i++ )
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{
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TX_DESC_PACKET( i ) = TX_BUF( i );
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TX_DESC_CTRL( i ) = 0;
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TX_STAT_INFO( i ) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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MAC_TXDESCRIPTOR = TX_DESC_BASE;
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MAC_TXSTATUS = TX_STAT_BASE;
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MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;
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/* Tx Descriptors Point to 0 */
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MAC_TXPRODUCEINDEX = 0;
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}
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// configure port-pins for use with LAN-controller,
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// reset it and send the configuration-sequence
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portBASE_TYPE Init_EMAC( void )
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{
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portBASE_TYPE xReturn = pdPASS;
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// Keil: function modified to access the EMAC
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// Initializes the EMAC ethernet controller
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volatile unsigned int regv, tout, id1, id2;
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/* Enable P1 Ethernet Pins. */
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PINSEL2 = configPINSEL2_VALUE;
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PINSEL3 = ( PINSEL3 &~0x0000000F ) | 0x00000005;
|
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/* Power Up the EMAC controller. */
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PCONP |= PCONP_PCENET;
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vTaskDelay( 2 );
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||||
|
||||
/* Reset all EMAC internal modules. */
|
||||
MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
|
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MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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||||
|
||||
/* A short delay after reset. */
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||||
vTaskDelay( 2 );
|
||||
|
||||
/* Initialize MAC control registers. */
|
||||
MAC_MAC1 = MAC1_PASS_ALL;
|
||||
MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
|
||||
MAC_MAXF = ETH_MAX_FLEN;
|
||||
MAC_CLRT = CLRT_DEF;
|
||||
MAC_IPGR = IPGR_DEF;
|
||||
|
||||
/* Enable Reduced MII interface. */
|
||||
MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
|
||||
|
||||
/* Reset Reduced MII Logic. */
|
||||
MAC_SUPP = SUPP_RES_RMII;
|
||||
vTaskDelay( 2 );
|
||||
MAC_SUPP = 0;
|
||||
|
||||
/* Put the PHY in reset mode */
|
||||
write_PHY( PHY_REG_BMCR, 0x8000 );
|
||||
xReturn = write_PHY( PHY_REG_BMCR, 0x8000 );
|
||||
|
||||
/* Wait for hardware reset to end. */
|
||||
for( tout = 0; tout < 100; tout++ )
|
||||
{
|
||||
vTaskDelay( 10 );
|
||||
regv = read_PHY( PHY_REG_BMCR, &xReturn );
|
||||
if( !(regv & 0x8000) )
|
||||
{
|
||||
/* Reset complete */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if this is a DP83848C PHY. */
|
||||
id1 = read_PHY( PHY_REG_IDR1, &xReturn );
|
||||
id2 = read_PHY( PHY_REG_IDR2, &xReturn );
|
||||
if( ((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID )
|
||||
{
|
||||
/* Set the Ethernet MAC Address registers */
|
||||
MAC_SA0 = ( emacETHADDR0 << 8 ) | emacETHADDR1;
|
||||
MAC_SA1 = ( emacETHADDR2 << 8 ) | emacETHADDR3;
|
||||
MAC_SA2 = ( emacETHADDR4 << 8 ) | emacETHADDR5;
|
||||
|
||||
/* Initialize Tx and Rx DMA Descriptors */
|
||||
rx_descr_init();
|
||||
tx_descr_init();
|
||||
|
||||
/* Receive Broadcast and Perfect Match Packets */
|
||||
MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
|
||||
|
||||
/* Create the semaphore used ot wake the uIP task. */
|
||||
vSemaphoreCreateBinary( xEMACSemaphore );
|
||||
|
||||
/* Configure the PHY device */
|
||||
|
||||
/* Use autonegotiation about the link speed. */
|
||||
if( write_PHY(PHY_REG_BMCR, PHY_AUTO_NEG) )
|
||||
{
|
||||
/* Wait to complete Auto_Negotiation. */
|
||||
for( tout = 0; tout < 10; tout++ )
|
||||
{
|
||||
vTaskDelay( 100 );
|
||||
regv = read_PHY( PHY_REG_BMSR, &xReturn );
|
||||
if( regv & 0x0020 )
|
||||
{
|
||||
/* Autonegotiation Complete. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
}
|
||||
|
||||
/* Check the link status. */
|
||||
if( xReturn == pdPASS )
|
||||
{
|
||||
xReturn = pdFAIL;
|
||||
for( tout = 0; tout < 10; tout++ )
|
||||
{
|
||||
vTaskDelay( 100 );
|
||||
regv = read_PHY( PHY_REG_STS, &xReturn );
|
||||
if( regv & 0x0001 )
|
||||
{
|
||||
/* Link is on. */
|
||||
xReturn = pdPASS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if( xReturn == pdPASS )
|
||||
{
|
||||
/* Configure Full/Half Duplex mode. */
|
||||
if( regv & 0x0004 )
|
||||
{
|
||||
/* Full duplex is enabled. */
|
||||
MAC_MAC2 |= MAC2_FULL_DUP;
|
||||
MAC_COMMAND |= CR_FULL_DUP;
|
||||
MAC_IPGT = IPGT_FULL_DUP;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half duplex mode. */
|
||||
MAC_IPGT = IPGT_HALF_DUP;
|
||||
}
|
||||
|
||||
/* Configure 100MBit/10MBit mode. */
|
||||
if( regv & 0x0002 )
|
||||
{
|
||||
/* 10MBit mode. */
|
||||
MAC_SUPP = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 100MBit mode. */
|
||||
MAC_SUPP = SUPP_SPEED;
|
||||
}
|
||||
|
||||
/* Reset all interrupts */
|
||||
MAC_INTCLEAR = 0xFFFF;
|
||||
|
||||
/* Enable receive and transmit mode of MAC Ethernet core */
|
||||
MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
|
||||
MAC_MAC1 |= MAC1_REC_EN;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
// reads a word in little-endian byte order from RX_BUFFER
|
||||
unsigned short ReadFrame_EMAC( void )
|
||||
{
|
||||
return( *rptr++ );
|
||||
}
|
||||
|
||||
// reads a word in big-endian byte order from RX_FRAME_PORT
|
||||
// (useful to avoid permanent byte-swapping while reading
|
||||
// TCP/IP-data)
|
||||
unsigned short ReadFrameBE_EMAC( void )
|
||||
{
|
||||
unsigned short ReturnValue;
|
||||
|
||||
ReturnValue = SwapBytes( *rptr++ );
|
||||
return( ReturnValue );
|
||||
}
|
||||
|
||||
// copies bytes from frame port to MCU-memory
|
||||
// NOTES: * an odd number of byte may only be transfered
|
||||
// if the frame is read to the end!
|
||||
// * MCU-memory MUST start at word-boundary
|
||||
void CopyFromFrame_EMAC( void *Dest, unsigned short Size )
|
||||
{
|
||||
unsigned short *piDest; // Keil: Pointer added to correct expression
|
||||
piDest = Dest; // Keil: Line added
|
||||
while( Size > 1 )
|
||||
{
|
||||
*piDest++ = ReadFrame_EMAC();
|
||||
Size -= 2;
|
||||
}
|
||||
|
||||
if( Size )
|
||||
{ // check for leftover byte...
|
||||
*( unsigned char * ) piDest = ( char ) ReadFrame_EMAC(); // the LAN-Controller will return 0
|
||||
} // for the highbyte
|
||||
}
|
||||
|
||||
// does a dummy read on frame-I/O-port
|
||||
// NOTE: only an even number of bytes is read!
|
||||
void DummyReadFrame_EMAC( unsigned short Size ) // discards an EVEN number of bytes
|
||||
{ // from RX-fifo
|
||||
while( Size > 1 )
|
||||
{
|
||||
ReadFrame_EMAC();
|
||||
Size -= 2;
|
||||
}
|
||||
}
|
||||
|
||||
// Reads the length of the received ethernet frame and checks if the
|
||||
// destination address is a broadcast message or not
|
||||
// returns the frame length
|
||||
unsigned short StartReadFrame( void )
|
||||
{
|
||||
unsigned short RxLen;
|
||||
unsigned int idx;
|
||||
|
||||
idx = MAC_RXCONSUMEINDEX;
|
||||
RxLen = ( RX_STAT_INFO(idx) & RINFO_SIZE ) - 3;
|
||||
rptr = ( unsigned short * ) RX_DESC_PACKET( idx );
|
||||
return( RxLen );
|
||||
}
|
||||
|
||||
void EndReadFrame( void )
|
||||
{
|
||||
unsigned int idx;
|
||||
|
||||
/* DMA free packet. */
|
||||
idx = MAC_RXCONSUMEINDEX;
|
||||
|
||||
if( ++idx == NUM_RX_FRAG )
|
||||
{
|
||||
idx = 0;
|
||||
}
|
||||
|
||||
MAC_RXCONSUMEINDEX = idx;
|
||||
}
|
||||
|
||||
unsigned int CheckFrameReceived( void )
|
||||
{
|
||||
// Packet received ?
|
||||
if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
|
||||
{ // more packets received ?
|
||||
return( 1 );
|
||||
}
|
||||
else
|
||||
{
|
||||
return( 0 );
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
|
||||
{
|
||||
unsigned int uiLen = 0;
|
||||
|
||||
if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
|
||||
{
|
||||
uiLen = StartReadFrame();
|
||||
CopyFromFrame_EMAC( ucBuffer, uiLen );
|
||||
EndReadFrame();
|
||||
}
|
||||
|
||||
return uiLen;
|
||||
}
|
||||
|
||||
// requests space in EMAC memory for storing an outgoing frame
|
||||
void RequestSend( void )
|
||||
{
|
||||
unsigned int idx;
|
||||
|
||||
idx = MAC_TXPRODUCEINDEX;
|
||||
tptr = ( unsigned short * ) TX_DESC_PACKET( idx );
|
||||
}
|
||||
|
||||
// check if ethernet controller is ready to accept the
|
||||
// frame we want to send
|
||||
unsigned int Rdy4Tx( void )
|
||||
{
|
||||
return( 1 ); // the ethernet controller transmits much faster
|
||||
} // than the CPU can load its buffers
|
||||
|
||||
// writes a word in little-endian byte order to TX_BUFFER
|
||||
void WriteFrame_EMAC( unsigned short Data )
|
||||
{
|
||||
*tptr++ = Data;
|
||||
}
|
||||
|
||||
// copies bytes from MCU-memory to frame port
|
||||
// NOTES: * an odd number of byte may only be transfered
|
||||
// if the frame is written to the end!
|
||||
// * MCU-memory MUST start at word-boundary
|
||||
void CopyToFrame_EMAC( void *Source, unsigned int Size )
|
||||
{
|
||||
unsigned short *piSource;
|
||||
|
||||
piSource = Source;
|
||||
Size = ( Size + 1 ) & 0xFFFE; // round Size up to next even number
|
||||
while( Size > 0 )
|
||||
{
|
||||
WriteFrame_EMAC( *piSource++ );
|
||||
Size -= 2;
|
||||
}
|
||||
}
|
||||
|
||||
void DoSend_EMAC( unsigned short FrameSize )
|
||||
{
|
||||
unsigned int idx;
|
||||
|
||||
idx = MAC_TXPRODUCEINDEX;
|
||||
TX_DESC_CTRL( idx ) = FrameSize | TCTRL_LAST;
|
||||
if( ++idx == NUM_TX_FRAG )
|
||||
{
|
||||
idx = 0;
|
||||
}
|
||||
|
||||
MAC_TXPRODUCEINDEX = idx;
|
||||
}
|
||||
|
||||
void vEMAC_ISR( void )
|
||||
{
|
||||
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
/* Clear the interrupt. */
|
||||
MAC_INTCLEAR = 0xffff;
|
||||
|
||||
/* Ensure the uIP task is not blocked as data has arrived. */
|
||||
xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
|
||||
|
||||
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
|
|
@ -66,6 +66,7 @@
|
|||
|
||||
/* Demo includes. */
|
||||
#include "emac.h"
|
||||
#include "EthDev_LPC17xx.h"
|
||||
#include "LED.h"
|
||||
|
||||
#include "LPC17xx.h"
|
||||
|
|
@ -81,7 +82,6 @@
|
|||
/* Standard constant. */
|
||||
#define uipTOTAL_FRAME_HEADER_SIZE 54
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue