mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-02 12:24:07 -04:00
Added flop support.
This commit is contained in:
Richard Barry
parent
094945625d
commit
ebffeb7ae4
11 changed files with 706 additions and 132 deletions
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@ -62,15 +62,11 @@
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.section P, code, align=4
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_vRegTest1Error:
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bra _vRegTest1Error
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nop
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;-----------------------------------------------------------
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_vRegTest1Task:
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; Fill the registers with known values.
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mov #2, r1
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mov #3, r2
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mov #4, r3
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mov #5, r4
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@ -83,92 +79,193 @@ _vRegTest1Task:
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mov #12, r11
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mov #13, r12
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mov #14, r13
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mov #15, r14
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mov #15, r0
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lds r0, macl
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mov #16, r0
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lds r0, mach
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lds r0, macl
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mov #17, r0
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lds r0, mach
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mov #18, r0
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ldc r0, gbr
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; Also fill the flop registers with known values.
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lds r1, fpul
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fsts fpul, fr1
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lds r2, fpul
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fsts fpul, fr2
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lds r3, fpul
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fsts fpul, fr3
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lds r4, fpul
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fsts fpul, fr4
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lds r5, fpul
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fsts fpul, fr5
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lds r6, fpul
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fsts fpul, fr6
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lds r7, fpul
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fsts fpul, fr7
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lds r8, fpul
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fsts fpul, fr8
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lds r9, fpul
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fsts fpul, fr9
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lds r10, fpul
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fsts fpul, fr10
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lds r11, fpul
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fsts fpul, fr11
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lds r12, fpul
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fsts fpul, fr12
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lds r13, fpul
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fsts fpul, fr13
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lds r14, fpul
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fsts fpul, fr14
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_vRegTest1Loop:
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; Set FPUL to a known value before the yield.
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mov #123, r0
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lds r0, fpul
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; Perform a yield, just for extra test coverage.
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trapa #33
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; Check fpul still contains the expected value.
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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; Reset r1 which was used in the tests.
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mov #2, r1
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; Test that the registers still contain the expected values. If not, jump to
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; vRegTestError, which will stop this function looping and so cause it to stop
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; incrementing its loop counter.
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; incrementing its loop counter. Both the standard and flop registers are
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; checked.
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mov #2, r0
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cmp/eq r0, r1
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bf _vRegTest1Error
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flds fr1, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #3, r0
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cmp/eq r0, r2
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bf _vRegTest1Error
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flds fr2, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #4, r0
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cmp/eq r0, r3
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bf _vRegTest1Error
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flds fr3, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #5, r0
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cmp/eq r0, r4
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bf _vRegTest1Error
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flds fr4, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #6, r0
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cmp/eq r0, r5
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bf _vRegTest1Error
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flds fr5, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #7, r0
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cmp/eq r0, r6
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bf _vRegTest1Error
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flds fr6, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #8, r0
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cmp/eq r0, r7
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bf _vRegTest1Error
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flds fr7, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #9, r0
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cmp/eq r0, r8
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bf _vRegTest1Error
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flds fr8, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #10, r0
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cmp/eq r0, r9
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bf _vRegTest1Error
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flds fr9, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #11, r0
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cmp/eq r0, r10
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bf _vRegTest1Error
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flds fr10, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #12, r0
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cmp/eq r0, r11
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bf _vRegTest1Error
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flds fr11, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #13, r0
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cmp/eq r0, r12
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bf _vRegTest1Error
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flds fr12, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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mov #14, r0
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cmp/eq r0, r13
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bf _vRegTest1Error
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sts macl, r0
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mov #15, r1
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flds fr13, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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sts mach, r0
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mov #15, r0
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cmp/eq r0, r14
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bf _vRegTest1Error
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flds fr14, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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sts macl, r0
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mov #16, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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stc gbr, r0
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sts mach, r0
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mov #17, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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stc gbr, r0
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mov #18, r1
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cmp/eq r0, r1
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bf _vRegTest1Error
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; Increment the loop counter to indicate that this task is still running and
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; still healthy.
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mov.l #_ulRegTest1CycleCount, r0
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@ -182,16 +279,16 @@ _vRegTest1Loop:
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;-----------------------------------------------------------
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_vRegTest2Error:
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bra _vRegTest2Error
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nop
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_vRegTest1Error:
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bra _vRegTest1Error
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nop
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;-----------------------------------------------------------
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_vRegTest2Task:
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; Fill the registers with known values.
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; Fill the standard registers with known values.
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mov #12, r1
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mov #13, r2
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mov #14, r3
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mov #15, r4
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@ -212,6 +309,36 @@ _vRegTest2Task:
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mov #117, r0
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ldc r0, gbr
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; Also fill the flop registers with known values.
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lds r1, fpul
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fsts fpul, fr1
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lds r2, fpul
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fsts fpul, fr2
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lds r3, fpul
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fsts fpul, fr3
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lds r4, fpul
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fsts fpul, fr4
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lds r5, fpul
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fsts fpul, fr5
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lds r6, fpul
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fsts fpul, fr6
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lds r7, fpul
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fsts fpul, fr7
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lds r8, fpul
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fsts fpul, fr8
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lds r9, fpul
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fsts fpul, fr9
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lds r10, fpul
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fsts fpul, fr10
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lds r11, fpul
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fsts fpul, fr11
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lds r12, fpul
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fsts fpul, fr12
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lds r13, fpul
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fsts fpul, fr13
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lds r14, fpul
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fsts fpul, fr14
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_vRegTest2Loop:
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; Reset r1 which was used in the tests.
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@ -219,58 +346,111 @@ _vRegTest2Loop:
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; Test that the registers still contain the expected values. If not, jump to
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; vRegTestError, which will stop this function looping and so cause it to stop
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; incrementing its loop counter.
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; incrementing its loop counter. Both the standard and flop registers are
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; checked.
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mov #12, r0
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cmp/eq r0, r1
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bf _vRegTest2Error
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flds fr1, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #13, r0
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cmp/eq r0, r2
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bf _vRegTest2Error
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flds fr2, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #14, r0
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cmp/eq r0, r3
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bf _vRegTest2Error
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flds fr3, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #15, r0
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cmp/eq r0, r4
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bf _vRegTest2Error
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flds fr4, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #16, r0
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cmp/eq r0, r5
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bf _vRegTest2Error
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flds fr5, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #17, r0
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cmp/eq r0, r6
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bf _vRegTest2Error
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flds fr6, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #18, r0
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cmp/eq r0, r7
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bf _vRegTest2Error
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flds fr7, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #19, r0
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cmp/eq r0, r8
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bf _vRegTest2Error
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flds fr8, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #110, r0
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cmp/eq r0, r9
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bf _vRegTest2Error
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flds fr9, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #111, r0
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cmp/eq r0, r10
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bf _vRegTest2Error
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flds fr10, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #112, r0
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cmp/eq r0, r11
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bf _vRegTest2Error
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flds fr11, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #113, r0
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cmp/eq r0, r12
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bf _vRegTest2Error
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flds fr12, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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mov #114, r0
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cmp/eq r0, r13
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bf _vRegTest2Error
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flds fr13, fpul
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sts fpul, r1
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cmp/eq r0, r1
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bf _vRegTest2Error
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sts macl, r0
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mov #115, r1
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@ -298,6 +478,12 @@ _vRegTest2Loop:
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bra _vRegTest2Loop
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nop
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;-----------------------------------------------------------
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_vRegTest2Error:
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bra _vRegTest2Error
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nop
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.end
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