mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-10 08:07:46 -04:00
freertos-mpu: Add privileged execute never MPU attribute
A new MPU region attribute Privileged eXecute Never (PXN) is introduced in Armv8.1-M architecture, where if an MPU region has PXN attribute set and the processor attempts to execute the code inside with privileged level, the Memory Management Fault exception would be triggered, with IACCVIOL bit in MemManage Fault State Register set to 1. The PXN feature allows privileged software to ensure specific application tasks (threads) to execute in unprivileged level only. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
This commit is contained in:
parent
0c79e74eaa
commit
ea60cd130a
56 changed files with 1267 additions and 957 deletions
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@ -65,6 +65,9 @@
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#define tskMPU_REGION_EXECUTE_NEVER ( 1U << 2U )
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#define tskMPU_REGION_NORMAL_MEMORY ( 1U << 3U )
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#define tskMPU_REGION_DEVICE_MEMORY ( 1U << 4U )
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#if ( portHAS_ARMV8_1_M_EXTENSION == 1 )
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#define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* MPU region permissions stored in MPU settings to
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* authorize access requests. */
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -55,6 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M55"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -55,6 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M85"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -50,6 +50,7 @@
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*/
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -55,6 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M55"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -55,6 +55,7 @@
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*/
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#define portARCH_NAME "Cortex-M85"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 1
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#define portDONT_DISCARD __root
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/*-----------------------------------------------------------*/
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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*/
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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*/
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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*/
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Enable privileged access to unmapped region. */
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#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
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@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
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( portMPU_RLAR_REGION_ENABLE );
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/* PXN. */
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
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{
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xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
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}
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#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
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/* Normal memory/ Device memory. */
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if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
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{
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*/
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#define portARCH_NAME "Cortex-M35P"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
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#define portHAS_ARMV8_1_M_EXTENSION 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
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#define portMPU_RLAR_REGION_ENABLE ( 1UL )
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#if (portHAS_ARMV8_1_M_EXTENSION == 1)
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/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
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||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
@ -225,6 +225,11 @@ typedef void ( * portISR_t )( void );
|
|||
|
||||
#define portMPU_RLAR_REGION_ENABLE ( 1UL )
|
||||
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
/* Enable Privileged eXecute Never MPU attribute for the selected memory region. */
|
||||
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Enable privileged access to unmapped region. */
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
|
||||
|
||||
|
@ -1880,6 +1885,14 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
|
||||
( portMPU_RLAR_REGION_ENABLE );
|
||||
|
||||
/* PXN. */
|
||||
#if (portHAS_ARMV8_1_M_EXTENSION == 1)
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
|
||||
{
|
||||
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
|
||||
}
|
||||
#endif /* portHAS_ARMV8_1_M_EXTENSION == 1 */
|
||||
|
||||
/* Normal memory/ Device memory. */
|
||||
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
|
||||
{
|
||||
|
|
|
@ -55,6 +55,7 @@
|
|||
*/
|
||||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portHAS_ARMV8_1_M_EXTENSION 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue