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Minor updates to demo projects to ensure correct building with V8 rc1.

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This commit is contained in:
Richard Barry 2013-12-30 11:24:34 +00:00
parent f9072e7bac
commit e95b482f56
18 changed files with 206 additions and 142 deletions
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12
FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
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@ -129,7 +129,7 @@ typedef unsigned long UBaseType_t;
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portNOP() asm volatile ( "NOP" );
#define portNOP() __asm volatile ( "NOP" );
/*-----------------------------------------------------------*/
@ -148,7 +148,7 @@ extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Set the LR to the task stack. */ \
asm volatile ( \
__asm volatile ( \
"LDR R0, =pxCurrentTCB \n\t" \
"LDR R0, [R0] \n\t" \
"LDR LR, [R0] \n\t" \
@ -185,7 +185,7 @@ extern volatile void * volatile pxCurrentTCB; \
extern volatile uint32_t ulCriticalNesting; \
\
/* Push R0 as we are going to use the register. */ \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" \
\
/* Set R0 to point to the task stack pointer. */ \
@ -227,7 +227,7 @@ extern volatile uint32_t ulCriticalNesting; \
#define portYIELD_FROM_ISR() vTaskSwitchContext()
#define portYIELD() asm volatile ( "SWI 0" )
#define portYIELD() __asm volatile ( "SWI 0" )
/*-----------------------------------------------------------*/
@ -251,7 +251,7 @@ extern volatile uint32_t ulCriticalNesting; \
#else
#define portDISABLE_INTERRUPTS() \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
@ -259,7 +259,7 @@ extern volatile uint32_t ulCriticalNesting; \
"LDMIA SP!, {R0} " ) /* Pop R0. */
#define portENABLE_INTERRUPTS() \
asm volatile ( \
__asm volatile ( \
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \