len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-19 17:48:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add the SAM7X Eclipse files.

Browse source
This commit is contained in:
Richard Barry 2007-11-21 18:29:41 +00:00
parent 620d3999ef
commit e8ddef1d93
110 changed files with 7813 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

68
Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Board.h Normal file
View file

@ -0,0 +1,68 @@
/*----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support - ROUSSET -
*----------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*----------------------------------------------------------------------------
* File Name : Board.h
* Object : AT91SAM7X Evaluation Board Features Definition File.
*
* Creation : JG 20/Jun/2005
*----------------------------------------------------------------------------
*/
#ifndef Board_h
#define Board_h
#include "AT91SAM7X256.h"
#include "ioat91sam7x256.h"
#define true -1
#define false 0
/*-------------------------------*/
/* SAM7Board Memories Definition */
/*-------------------------------*/
// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
#define FLASH_PAGE_NB 256
#define FLASH_PAGE_SIZE 128
/*-----------------*/
/* Leds Definition */
/*-----------------*/
#define LED1 (1<<19) // PB19
#define LED2 (1<<20) // PB20
#define LED3 (1<<21) // PB21
#define LED4 (1<<22) // PB22
#define NB_LED 4
#define LED_MASK (LED1|LED2|LED3|LED4)
/*-------------------------*/
/* Push Buttons Definition */
/*-------------------------*/
#define SW1_MASK (1<<21) // PA21
#define SW2_MASK (1<<22) // PA22
#define SW3_MASK (1<<23) // PA23
#define SW4_MASK (1<<24) // PA24
#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
#define SW1 (1<<21) // PA21
#define SW2 (1<<22) // PA22
#define SW3 (1<<23) // PA23
#define SW4 (1<<24) // PA24
#define SWPUSH (1<<25) // PA25
/*--------------*/
/* Master Clock */
/*--------------*/
#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
#define MCK 47923200 // MCK (PLLRC div by 2)
#define MCKKHz (MCK/1000) //
#endif /* Board_h */

223
Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup.s79 Normal file
View file

@ -0,0 +1,223 @@
;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : Cstartup.s79
;- Object : Generic CStartup for IAR No Use REMAP
;- Compilation flag : None
;-
;- 1.0 15/Jun/04 JPP : Creation
;------------------------------------------------------------------------------
#include "AT91SAM7X256_inc.h"
;------------------------------------------------------------------------------
;- Area Definition
;------------------------------------------------------------------------------
;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;-------------------------------------------------------------
PROGRAM ?RESET
RSEG INTRAMSTART_REMAP
RSEG INTRAMEND_REMAP
EXTERN vPortYieldProcessor
RSEG ICODE:CODE:ROOT(2)
CODE32 ; Always ARM mode after reset
org 0
reset
;------------------------------------------------------------------------------
;- Exception vectors
;--------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite loop.
;- To ensure if a exeption occurs before start application to infinite loop.
;------------------------------------------------------------------------------
B InitReset ; 0x00 Reset handler
undefvec:
B undefvec ; 0x04 Undefined Instruction
swivec:
B vPortYieldProcessor ; 0x08 Software Interrupt
pabtvec:
B pabtvec ; 0x0C Prefetch Abort
dabtvec:
B dabtvec ; 0x10 Data Abort
rsvdvec:
B rsvdvec ; 0x14 reserved
irqvec:
LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC
fiqvec: ; 0x1c FIQ
;------------------------------------------------------------------------------
;- Function : FIQ_Handler_Entry
;- Treatments : FIQ Controller Interrupt Handler.
;- Called Functions : AIC_FVR[interrupt]
;------------------------------------------------------------------------------
FIQ_Handler_Entry:
;- Switch in SVC/User Mode to allow User Stack access for C code
; because the FIQ is not yet acknowledged
;- Save and r0 in FIQ_Register
mov r9,r0
ldr r0 , [r8, #AIC_FVR]
msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
;- Save scratch/used registers and LR in User Stack
stmfd sp!, { r1-r3, r12, lr}
;- Branch to the routine pointed by the AIC_FVR
mov r14, pc
bx r0
;- Restore scratch/used registers and LR from User Stack
ldmia sp!, { r1-r3, r12, lr}
;- Leave Interrupts disabled and switch back in FIQ mode
msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
;- Restore the R0 ARM_MODE_SVC register
mov r0,r9
;- Restore the Program Counter using the LR_fiq directly in the PC
subs pc,lr,#4
InitReset:
;------------------------------------------------------------------------------
;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
;------------------------------------------------------------------------------
EXTERN AT91F_LowLevelInit
#define __iramend SFB(INTRAMEND_REMAP)
;- minumum C initialization
;- call AT91F_LowLevelInit( void)
ldr r13,=__iramend ; temporary stack in internal RAM
;--Call Low level init function in ABSOLUTE through the Interworking
ldr r0,=AT91F_LowLevelInit
mov lr, pc
bx r0
;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ management.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt not requires stack If in your application it required you must
;- be definehere.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Interrupt and Supervisor Stack are located at the top of internal memory in
;- order to speed the exception handling context saving and restoring.
;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------
IRQ_STACK_SIZE EQU 300
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
I_BIT EQU 0x80
F_BIT EQU 0x40
;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
ldr r0, =__iramend
;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
;- Init the FIQ register
ldr r8, =AT91C_BASE_AIC
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #ARM_MODE_SVC
mov r13, r0
;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
EXTERN __segment_init
EXTERN main
; Initialize segments.
; __segment_init is assumed to use
; instruction set and to be reachable by BL from the ICODE segment
; (it is safest to link them in segment ICODE).
ldr r0,=__segment_init
mov lr, pc
bx r0
PUBLIC __main
?jump_to_main:
ldr lr,=?call_exit
ldr r0,=main
__main:
bx r0
;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
?call_exit:
End
b End
;---------------------------------------------------------------
; ?EXEPTION_VECTOR
; This module is only linked if needed for closing files.
;---------------------------------------------------------------
PUBLIC AT91F_Default_FIQ_handler
PUBLIC AT91F_Default_IRQ_handler
PUBLIC AT91F_Spurious_handler
CODE32 ; Always ARM mode after exeption
AT91F_Default_FIQ_handler
b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler
b AT91F_Default_IRQ_handler
AT91F_Spurious_handler
b AT91F_Spurious_handler
ENDMOD
END

69
Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup_SAM7.c Normal file
View file

@ -0,0 +1,69 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : Cstartup_SAM7.c
//* Object : Low level initializations written in C for IAR
//* tools
//* 1.0 08/Sep/04 JPP : Creation
//* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
//*----------------------------------------------------------------------------
// Include the board file description
#include "Board.h"
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void);
void AT91F_LowLevelInit( void )
{
AT91PS_PMC pPMC = AT91C_BASE_PMC;
//* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
//* Watchdog Disable
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
//* Set MCK at 47 923 200
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSeconde
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
// 2 Checking the Main Oscillator Frequency (Optional)
// 3 Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
//eld out NOT USED = 0 Fi
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
(AT91C_CKGR_PLLCOUNT & (28<<8)) |
(AT91C_CKGR_MUL & (25<<16)));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
// 4. Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
}

195
Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Emac.h Normal file
View file

@ -0,0 +1,195 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : Emac.h
//* Object : Emac header file
//* Creation : Hi 11/18/2002
//*
//*----------------------------------------------------------------------------
#ifndef AT91C_EMAC_H
#define AT91C_EMAC_H
//* Allows to display all IP header in the main.c
//* If not defined, only ICMP packets are displayed
#define AT91C_DISPLAY_ALL_IPHEADER 0
#define NB_RX_BUFFERS 25 //* Number of receive buffers
#define ETH_RX_BUFFER_SIZE 128 //*
#define NB_TX_BUFFERS 2 //* Number of Transmit buffers
#define ETH_TX_BUFFER_SIZE UIP_BUFSIZE //*
#define AT91C_NO_IPPACKET 0
#define AT91C_IPPACKET 1
#define ARP_REQUEST 0x0001
#define ARP_REPLY 0x0002
#define PROT_ARP 0x0806
#define PROT_IP 0x0800
#define PROT_ICMP 0x01
#define ICMP_ECHO_REQUEST 0x08
#define ICMP_ECHO_REPLY 0x00
#define AT91C_EMAC_CLKEN 0x2
#define SWAP16(x) (((x & 0xff) << 8) | (x >> 8))
#if 0
//* Transfer descriptor structure
typedef struct _AT91S_TdDescriptor {
unsigned int addr;
unsigned int status;
}AT91S_TdDescriptor, *AT91PS_TdDescriptor;
#endif
//* Receive Transfer descriptor structure
typedef struct _AT91S_RxTdDescriptor {
unsigned int addr;
union
{
unsigned int status;
struct {
unsigned int Length:11;
unsigned int Res0:1;
unsigned int Rxbuf_off:2;
unsigned int StartOfFrame:1;
unsigned int EndOfFrame:1;
unsigned int Cfi:1;
unsigned int VlanPriority:3;
unsigned int PriorityTag:1;
unsigned int VlanTag:1;
unsigned int TypeID:1;
unsigned int Sa4Match:1;
unsigned int Sa3Match:1;
unsigned int Sa2Match:1;
unsigned int Sa1Match:1;
unsigned int Res1:1;
unsigned int ExternalAdd:1;
unsigned int UniCast:1;
unsigned int MultiCast:1;
unsigned int BroadCast:1;
}S_Status;
}U_Status;
}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
//* Transmit Transfer descriptor structure
typedef struct _AT91S_TxTdDescriptor {
unsigned int addr;
union
{
unsigned int status;
struct {
unsigned int Length:11;
unsigned int Res0:4;
unsigned int LastBuff:1;
unsigned int NoCrc:1;
unsigned int Res1:10;
unsigned int BufExhausted:1;
unsigned int TransmitUnderrun:1;
unsigned int TransmitError:1;
unsigned int Wrap:1;
unsigned int BuffUsed:1;
}S_Status;
}U_Status;
}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
#define AT91C_OWNERSHIP_BIT 0x00000001
/* Receive status defintion */
#define AT91C_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected
#define AT91C_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match
#define AT91C_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match
#define AT91C_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match
#define AT91C_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match
#define AT91C_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match
#define AT91C_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match
#define AT91C_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match
#define AT91C_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match
#define AT91C_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected
#define AT91C_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected
#define AT91C_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask
#define AT91C_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator
#define AT91C_EOF ((unsigned int) (1 << 15)) //* EOF
#define AT91C_SOF ((unsigned int) (1 << 14)) //* SOF
#define AT91C_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask
#define AT91C_LENGTH_FRAME ((unsigned int) 0x07FF) //* Length of frame
/* Transmit Status definition */
#define AT91C_TRANSMIT_OK ((unsigned int) (1 << 31)) //*
#define AT91C_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor
#define AT91C_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error
#define AT91C_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun
#define AT91C_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame
#define AT91C_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame
#define AT91C_LAST_BUFFER ((unsigned int) (1 << 15)) //*
#define ARP_ETHER 1 /* Ethernet hardware address */
#define ARPOP_REQUEST 1 /* Request to resolve address */
#define ARPOP_REPLY 2 /* Response to previous request */
#define RARPOP_REQUEST 3 /* Request to resolve address */
#define RARPOP_REPLY 4 /* Response to previous request */
typedef struct _AT91S_EthHdr
{
unsigned char et_dest[6]; /* Destination node */
unsigned char et_src[6]; /* Source node */
unsigned short et_protlen; /* Protocol or length */
} AT91S_EthHdr, *AT91PS_EthHdr;
typedef struct _AT91S_ArpHdr
{
unsigned short ar_hrd; /* Format of hardware address */
unsigned short ar_pro; /* Format of protocol address */
unsigned char ar_hln; /* Length of hardware address */
unsigned char ar_pln; /* Length of protocol address */
unsigned short ar_op; /* Operation */
unsigned char ar_sha[6]; /* Sender hardware address */
unsigned char ar_spa[4]; /* Sender protocol address */
unsigned char ar_tha[6]; /* Target hardware address */
unsigned char ar_tpa[4]; /* Target protocol address */
} AT91S_ArpHdr, *AT91PS_ArpHdr;
//* IP Header structure
typedef struct _AT91S_IPheader {
unsigned char ip_hl_v; /* header length and version */
unsigned char ip_tos; /* type of service */
unsigned short ip_len; /* total length */
unsigned short ip_id; /* identification */
unsigned short ip_off; /* fragment offset field */
unsigned char ip_ttl; /* time to live */
unsigned char ip_p; /* protocol */
unsigned short ip_sum; /* checksum */
unsigned char ip_src[4]; /* Source IP address */
unsigned char ip_dst[4]; /* Destination IP address */
unsigned short udp_src; /* UDP source port */
unsigned short udp_dst; /* UDP destination port */
unsigned short udp_len; /* Length of UDP packet */
unsigned short udp_xsum; /* Checksum */
} AT91S_IPheader, *AT91PS_IPheader;
//* ICMP echo header structure
typedef struct _AT91S_IcmpEchoHdr {
unsigned char type; /* type of message */
unsigned char code; /* type subcode */
unsigned short cksum; /* ones complement cksum of struct */
unsigned short id; /* identifier */
unsigned short seq; /* sequence number */
}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;
typedef struct _AT91S_EthPack
{
AT91S_EthHdr EthHdr;
AT91S_ArpHdr ArpHdr;
} AT91S_EthPack, *AT91PS_EthPack;
#endif //* AT91C_EMAC_H

105
Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/mii.h Normal file
View file

@ -0,0 +1,105 @@
/* Generic MII registers. */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
/* Basic mode control register. */
#define BMCR_RESV 0x007f /* Unused... */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x07c0 /* Unused... */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_RESV 0x1c00 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
#define LPA_RESV 0x1c00 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
#define SPEED_10 10
#define SPEED_100 100
/* Duplex, half or full. */
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
/* PHY ID */
#define MII_DM9161_ID 0x0181b8a0
#define MII_AM79C875_ID 0x00225540 /* 0x00225541 */
#define AT91C_PHY_ADDR 31