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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Some efficiency improvements in Risc-V port.
This commit is contained in:
Richard Barry
parent
dc99300fa9
commit
e85ea96f78
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@ -49,9 +49,10 @@ static void prvTaskExitError( void );
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/*-----------------------------------------------------------*/
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/* Used to program the machine timer compare register. */
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static uint64_t ullNextTime = 0ULL;
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static const uint64_t ullTimerIncrementsForOneTick = ( uint64_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
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static volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );
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uint64_t ullNextTime = 0ULL;
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const uint64_t *pullNextTime = &ullNextTime;
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const uint32_t ulTimerIncrementsForOneTick = ( uint32_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */
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volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );
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/*-----------------------------------------------------------*/
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@ -187,11 +188,11 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLI
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ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
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ullNextTime <<= 32ULL;
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ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
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ullNextTime += ullTimerIncrementsForOneTick;
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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*pullMachineTimerCompareRegister = ullNextTime;
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/* Prepare the time to use after the next tick interrupt. */
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ullNextTime += ullTimerIncrementsForOneTick;
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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/* Enable timer interrupt */
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__asm volatile( "csrs mie, %0" :: "r"(0x80) ); /* 1<<7 for timer interrupt. */
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@ -209,21 +210,6 @@ volatile uint32_t * const ulSoftInterrupt = ( uint32_t * ) configCLINT_BASE_ADDR
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}
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/*-----------------------------------------------------------*/
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void Timer_IRQHandler( void )
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{
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extern void vTaskSwitchContext( void );
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/* Reload for the next timer interrupt. */
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*pullMachineTimerCompareRegister = ullNextTime;
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ullNextTime += ullTimerIncrementsForOneTick;
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if( xTaskIncrementTick() != pdFALSE )
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{
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vTaskSwitchContext();
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}
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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extern void xPortStartFirstTask( void );
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@ -28,12 +28,12 @@
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*/
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define WORD_SIZE 8
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define WORD_SIZE 8
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#elif __riscv_xlen == 32
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#define WORD_SIZE 4
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#define WORD_SIZE 4
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#else
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#error Assembler has not defined __riscv_xlen
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#error Assembler has not defined __riscv_xlen
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#endif
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#define CONTEXT_SIZE ( 30 * WORD_SIZE )
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@ -42,6 +42,14 @@
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.global vPortTrapHandler
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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.extern Timer_IRQHandler
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.extern pullMachineTimerCompareRegister
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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/*-----------------------------------------------------------*/
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@ -51,18 +59,18 @@ xPortStartFirstTask:
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la t0, vPortTrapHandler
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csrw mtvec, t0
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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@ -82,8 +90,8 @@ xPortStartFirstTask:
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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ret
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/*-----------------------------------------------------------*/
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@ -120,24 +128,56 @@ vPortTrapHandler:
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sw x30, 27 * WORD_SIZE( sp )
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sw x31, 28 * WORD_SIZE( sp )
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csrr t0, mstatus /* Required for MPIE bit. */
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * WORD_SIZE( sp )
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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test_if_environment_call:
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li t0, 11 /* 11 == environment call when using qemu. */
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bne a0, t0, test_if_timer
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addi a1, a1, 4 /* Synchronous so return to the instruction after the environment call. */
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sw a1, 0( sp ) /* Save updated exception return address. */
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/*_RB_ Does stack need aligning here? */
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jal ulPortTrapHandler
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csrw mepc, a0
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/* Save exception return address. */
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sw a0, 0( sp )
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jal vTaskSwitchContext
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j processed_source
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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test_if_timer:
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sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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lui t0, 0x80000
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addi t1,t0, 7 /* 0x80000007 == machine timer interrupt. */
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bne a0, t1, as_yet_unhandled
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lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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lw t1, pullNextTime /* Load the address of ullNextTime into t1. */
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lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */
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lw t0, ulTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */
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sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
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add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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sw t4, 0(t1) /* Store new low word of ullNextTime. */
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sw t6, 4(t1) /* Store new high word of ullNextTime. */
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jal xTaskIncrementTick
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beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
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jal vTaskSwitchContext
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j processed_source
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as_yet_unhandled:
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j as_yet_unhandled /* External interrupt? */
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processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next task. */
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lw t0, 0( sp )
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@ -145,37 +185,37 @@ vPortTrapHandler:
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * WORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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csrw mstatus, t0 /* Required for MPIE bit. */
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lw x1, 1 * WORD_SIZE( sp )
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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mret
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