diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index c104064f3..8bf1ac184 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -22,7 +22,6 @@ * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * - * 1 tab == 4 spaces! */ /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining @@ -55,13 +54,13 @@ * on the secure side. The following are the valid configuration seetings: * * 1. Run FreeRTOS on the Secure Side: - * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 * * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: - * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 * * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: - * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 */ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. @@ -612,7 +611,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +801,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +834,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -876,7 +875,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } } /*-----------------------------------------------------------*/ - +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -887,8 +886,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ @@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1091,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 3f39bc3b1..9ee28cde2 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -882,12 +882,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ { /* Simulate the stack frame as it would be created by a context switch @@ -1051,7 +1051,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1081,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1091,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index c104064f3..4d483d4b7 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -55,13 +55,13 @@ * on the secure side. The following are the valid configuration seetings: * * 1. Run FreeRTOS on the Secure Side: - * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 * * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: - * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 * * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: - * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 */ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -887,8 +888,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ @@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1093,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index c104064f3..e0a0c7ef7 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -887,8 +888,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ @@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1093,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index c104064f3..151ea8b1f 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO TaskFunction_t pxCode, void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ @@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1093,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index d1cf78133..34ce94ee2 100644 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -360,14 +360,14 @@ static void prvRestoreContextOfFirstTask( void ) " str r3, [r2] \n"/* Disable MPU. */ " \n" " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ " \n" #if ( portTOTAL_NUM_REGIONS == 16 ) - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ - " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* portTOTAL_NUM_REGIONS == 16. */ " \n" " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ @@ -584,14 +584,14 @@ void xPortPendSVHandler( void ) " str r3, [r2] \n"/* Disable MPU. */ " \n" " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ " \n" #if ( portTOTAL_NUM_REGIONS == 16 ) - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ - " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ + " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* portTOTAL_NUM_REGIONS == 16. */ " \n" " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c index 474c3b824..0e62131c9 100644 --- a/portable/GCC/ARM_CR5/port.c +++ b/portable/GCC/ARM_CR5/port.c @@ -149,17 +149,18 @@ /* Adding the necessary stuff in order to be able to determine from C code wheter or not the IRQs are enabled at the processor level (not interrupt controller level) */ -#define GET_CPSR() ({u32 rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define GET_CPSR() \ + ( { u32 rval = 0U; \ + __asm__ __volatile__ ( \ + "mrs %0, cpsr\n"\ + : "=r" ( rval ) \ + ); \ + rval; \ + } ) -#define CPSR_IRQ_ENABLE_MASK 0x80U +#define CPSR_IRQ_ENABLE_MASK 0x80U -#define IS_IRQ_DISABLED() ({unsigned int val = 0; val = (GET_CPSR() & CPSR_IRQ_ENABLE_MASK) ? 1 : 0; val;}) +#define IS_IRQ_DISABLED() ( { unsigned int val = 0; val = ( GET_CPSR() & CPSR_IRQ_ENABLE_MASK ) ? 1 : 0; val; } ) /*-----------------------------------------------------------*/ /* @@ -505,18 +506,20 @@ uint32_t ulPortSetInterruptMask( void ) "isb \n"::: "memory" ); } - /* Just like this function returns a value of wether or not the interrupts where masked in the interrupt controller in order to avoid race condition when + /* Just like this function returns a value of wether or not the interrupts where masked in the interrupt controller in order to avoid race condition when * calling its matching vPortClearInterruptMask function, we needed a 'wasIRQDisabled' variable holding the state of the IRQ Enable bit in the CPSR in order - * to leave that bit in it's original state. Like mentioned above, hardware automatically clear the IRQEnable bit upon trapping into IRQ Mode, so the programmer + * to leave that bit in it's original state. Like mentioned above, hardware automatically clear the IRQEnable bit upon trapping into IRQ Mode, so the programmer * cannot make assumption about it's state. Very rare, but very important race condition is avoided with this when this function is called in an ISR. The race * condition in question was discovered when integrating tracealyzer code. Inside the function 'void vTaskSwitchContext( void )' in tasks.c, there is a macro 'traceTASK_SWITCHED_IN();' - * which gets replaced by something when using the tracing capabilities. That macro protects some critical section with matching calls to 'ulPortSetInterruptMask' + * which gets replaced by something when using the tracing capabilities. That macro protects some critical section with matching calls to 'ulPortSetInterruptMask' * and 'vPortClearInterruptMask'. At the time of calling those functions, the interrupt mask is not set in the interrupt controller, thus the only protecting barrier - * against the CPU traping into recursive interrupt was the IRQ Enable bit in the CPSR. By not taking it into acount, the very code that protects the CPU against - * critical section violation just enabled it to happen : A SysTick was waiting to happen, and calling 'portCPU_IRQ_ENABLE' would enable it to occur... Thus triggering a + * against the CPU traping into recursive interrupt was the IRQ Enable bit in the CPSR. By not taking it into acount, the very code that protects the CPU against + * critical section violation just enabled it to happen : A SysTick was waiting to happen, and calling 'portCPU_IRQ_ENABLE' would enable it to occur... Thus triggering a * switch of context while already performing a switch context. */ - if(!wasIRQDisabled) - portCPU_IRQ_ENABLE(); + if( !wasIRQDisabled ) + { + portCPU_IRQ_ENABLE(); + } return ulReturn; } diff --git a/portable/GCC/AVR_AVRDx/port.c b/portable/GCC/AVR_AVRDx/port.c index 42e03de69..0a995d875 100644 --- a/portable/GCC/AVR_AVRDx/port.c +++ b/portable/GCC/AVR_AVRDx/port.c @@ -34,18 +34,18 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enables. */ -#define portFLAGS_INT_ENABLED ((StackType_t) 0x80) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) /*-----------------------------------------------------------*/ /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void RTOS_TCB_t; -extern volatile RTOS_TCB_t *volatile pxCurrentTCB; +extern volatile RTOS_TCB_t * volatile pxCurrentTCB; /*-----------------------------------------------------------*/ @@ -65,161 +65,163 @@ extern volatile RTOS_TCB_t *volatile pxCurrentTCB; * so we need not worry about reading/writing to the stack pointer. */ -#define portSAVE_CONTEXT() \ - asm volatile("push r0 \n\t" \ - "in r0, __SREG__ \n\t" \ - "cli \n\t" \ - "push r0 \n\t" \ - "in r0, __RAMPZ__ \n\t" \ - "push r0 \n\t" \ - "push r1 \n\t" \ - "clr r1 \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in r0, __SP_L__ \n\t" \ - "st x+, r0 \n\t" \ - "in r0, __SP_H__ \n\t" \ - "st x+, r0 \n\t"); +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "in r0, __RAMPZ__ \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, __SP_L__ \n\t" \ + "st x+, r0 \n\t" \ + "in r0, __SP_H__ \n\t" \ + "st x+, r0 \n\t" ); /* * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during * the context save so we can write to the stack pointer. */ -#define portRESTORE_CONTEXT() \ - asm volatile("lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop r1 \n\t" \ - "pop r0 \n\t" \ - "out __RAMPZ__, r0 \n\t" \ - "pop r0 \n\t" \ - "out __SREG__, r0 \n\t" \ - "pop r0 \n\t"); +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __RAMPZ__, r0 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" ); /*-----------------------------------------------------------*/ /* * Perform hardware setup to enable ticks from timer. */ -static void prvSetupTimerInterrupt(void); +static void prvSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { uint16_t usAddress; /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. Uncomment if needed. */ - // *pxTopOfStack = 0x11; - // pxTopOfStack--; - // *pxTopOfStack = 0x22; - // pxTopOfStack--; - // *pxTopOfStack = 0x33; - // pxTopOfStack--; + * This is just useful for debugging. Uncomment if needed. */ + /* *pxTopOfStack = 0x11; */ + /* pxTopOfStack--; */ + /* *pxTopOfStack = 0x22; */ + /* pxTopOfStack--; */ + /* *pxTopOfStack = 0x33; */ + /* pxTopOfStack--; */ /* The start of the task code will be popped off the stack last, so place - it on first. */ - usAddress = (uint16_t)pxCode; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + * it on first. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = (StackType_t)0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ pxTopOfStack--; /* Now the remaining registers. The compiler expects R1 to be 0. */ - *pxTopOfStack = (StackType_t)0x00; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ /* Leave R2 - R23 untouched */ pxTopOfStack -= 23; /* Place the parameter on the stack in the expected location. */ - usAddress = (uint16_t)pvParameters; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); /* Leave register R26 - R31 untouched */ pxTopOfStack -= 7; @@ -230,7 +232,7 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC } /*-----------------------------------------------------------*/ -BaseType_t xPortStartScheduler(void) +BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. */ prvSetupTimerInterrupt(); @@ -239,15 +241,15 @@ BaseType_t xPortStartScheduler(void) portRESTORE_CONTEXT(); /* Simulate a function call end as generated by the compiler. We will now - jump to the start of the task the context of which we have just restored. */ - asm volatile("ret"); + * jump to the start of the task the context of which we have just restored. */ + asm volatile ( "ret" ); /* Should not get here. */ return pdTRUE; } /*-----------------------------------------------------------*/ -void vPortEndScheduler(void) +void vPortEndScheduler( void ) { /* vPortEndScheduler is not implemented in this port. */ } @@ -257,13 +259,13 @@ void vPortEndScheduler(void) * Manual context switch. The first thing we do is save the registers so we * can use a naked attribute. */ -void vPortYield(void) __attribute__((naked)); -void vPortYield(void) +void vPortYield( void ) __attribute__( ( naked ) ); +void vPortYield( void ) { portSAVE_CONTEXT(); vTaskSwitchContext(); portRESTORE_CONTEXT(); - asm volatile("ret"); + asm volatile ( "ret" ); } /*-----------------------------------------------------------*/ @@ -271,13 +273,13 @@ void vPortYield(void) * Manual context switch callable from ISRs. The first thing * we do is save the registers so we can use a naked attribute. */ -void vPortYieldFromISR(void) __attribute__((naked)); -void vPortYieldFromISR(void) +void vPortYieldFromISR( void ) __attribute__( ( naked ) ); +void vPortYieldFromISR( void ) { portSAVE_CONTEXT(); vTaskSwitchContext(); portRESTORE_CONTEXT(); - asm volatile("reti"); + asm volatile ( "reti" ); } /*-----------------------------------------------------------*/ @@ -287,24 +289,26 @@ void vPortYieldFromISR(void) * difference from vPortYield() is the tick count is incremented as the * call comes from the tick ISR. */ -void vPortYieldFromTick(void) __attribute__((naked)); -void vPortYieldFromTick(void) +void vPortYieldFromTick( void ) __attribute__( ( naked ) ); +void vPortYieldFromTick( void ) { portSAVE_CONTEXT(); - if (xTaskIncrementTick() != pdFALSE) { + + if( xTaskIncrementTick() != pdFALSE ) + { vTaskSwitchContext(); } portRESTORE_CONTEXT(); - asm volatile("reti"); + asm volatile ( "reti" ); } /*-----------------------------------------------------------*/ /* * Setup timer to generate a tick interrupt. */ -static void prvSetupTimerInterrupt(void) +static void prvSetupTimerInterrupt( void ) { TICK_init(); } @@ -317,26 +321,26 @@ static void prvSetupTimerInterrupt(void) * the context is saved at the start of vPortYieldFromTick(). The tick * count is incremented after the context is saved. */ -ISR(TICK_INT_vect, ISR_NAKED) -{ - /* Clear tick interrupt flag. */ - CLR_INT(INT_FLAGS, INT_MASK); + ISR( TICK_INT_vect, ISR_NAKED ) + { + /* Clear tick interrupt flag. */ + CLR_INT( INT_FLAGS, INT_MASK ); - vPortYieldFromTick(); + vPortYieldFromTick(); - asm volatile("reti"); -} -#else + asm volatile ( "reti" ); + } +#else /* if configUSE_PREEMPTION == 1 */ /* * Tick ISR for the cooperative scheduler. All this does is increment the * tick count. We don't need to switch context, this can only be done by * manual calls to taskYIELD(); */ -ISR(TICK_INT_vect) -{ - /* Clear tick interrupt flag. */ - INT_FLAGS = INT_MASK; - xTaskIncrementTick(); -} -#endif + ISR( TICK_INT_vect ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/portable/GCC/AVR_AVRDx/porthardware.h b/portable/GCC/AVR_AVRDx/porthardware.h index cf2377844..7e670d933 100644 --- a/portable/GCC/AVR_AVRDx/porthardware.h +++ b/portable/GCC/AVR_AVRDx/porthardware.h @@ -5,98 +5,104 @@ /*-----------------------------------------------------------*/ -#define CLR_INT(FLAG_REG, FLAG_MASK) \ - asm volatile( \ - "push r16\n\t" \ - "ldi r16, %1\n\t" \ - "sts %0, r16\n\t" \ - "pop r16\n\t" \ - : \ - : "i"(_SFR_MEM_ADDR(FLAG_REG)),"i"((uint8_t)(FLAG_MASK)) \ +#define CLR_INT( FLAG_REG, FLAG_MASK ) \ + asm volatile ( \ + "push r16\n\t" \ + "ldi r16, %1\n\t" \ + "sts %0, r16\n\t" \ + "pop r16\n\t" \ + : \ + : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \ ); #if ( configUSE_TIMER_INSTANCE == 0 ) - #define TICK_INT_vect TCB0_INT_vect - #define INT_FLAGS TCB0_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB0.INTCTRL = TCB_CAPT_bm; \ - TCB0.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 1 ) - #define TICK_INT_vect TCB1_INT_vect - #define INT_FLAGS TCB1_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } - #define TICK_init() { \ - TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB1.INTCTRL = TCB_CAPT_bm; \ - TCB1.CTRLA = TCB_ENABLE_bm; \ - } - #elif ( configUSE_TIMER_INSTANCE == 2 ) - #define TICK_INT_vect TCB2_INT_vect - #define INT_FLAGS TCB2_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } - #define TICK_init() { \ - TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB2.INTCTRL = TCB_CAPT_bm; \ - TCB2.CTRLA = TCB_ENABLE_bm; \ - } - #elif ( configUSE_TIMER_INSTANCE == 3 ) - #define TICK_INT_vect TCB3_INT_vect - #define INT_FLAGS TCB3_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } - #define TICK_init() { \ - TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB3.INTCTRL = TCB_CAPT_bm; \ - TCB3.CTRLA = TCB_ENABLE_bm; \ - } - #elif ( configUSE_TIMER_INSTANCE == 4 ) - #define TICK_INT_vect TCB4_INT_vect - #define INT_FLAGS TCB4_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB4_INT_vect + #define INT_FLAGS TCB4_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB4.INTCTRL = TCB_CAPT_bm; \ - TCB4.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB4.INTCTRL = TCB_CAPT_bm; \ + TCB4.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 5 ) - #define TICK_INT_vect RTC_CNT_vect - #define INT_FLAGS RTC_INTFLAGS - #define INT_MASK RTC_OVF_bm + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm - /* Hertz to period for RTC setup */ - #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) ) - #define TICK_init() { \ - while (RTC.STATUS > 0); \ - RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ - RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \ - RTC.INTCTRL |= 1 << RTC_OVF_bp; \ - } +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } -#else +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ #undef TICK_INT_vect #undef INT_FLAGS #undef INT_MASK #undef TICK_init() #error Invalid timer setting. -#endif +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ /*-----------------------------------------------------------*/ diff --git a/portable/GCC/AVR_Mega0/port.c b/portable/GCC/AVR_Mega0/port.c index 83d36da12..c27b7ccd5 100644 --- a/portable/GCC/AVR_Mega0/port.c +++ b/portable/GCC/AVR_Mega0/port.c @@ -34,18 +34,18 @@ #include "task.h" /*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ /* Start tasks with interrupts enables. */ -#define portFLAGS_INT_ENABLED ((StackType_t) 0x80) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) /*-----------------------------------------------------------*/ /* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ + * any details of its type. */ typedef void RTOS_TCB_t; -extern volatile RTOS_TCB_t *volatile pxCurrentTCB; +extern volatile RTOS_TCB_t * volatile pxCurrentTCB; /*-----------------------------------------------------------*/ @@ -65,155 +65,157 @@ extern volatile RTOS_TCB_t *volatile pxCurrentTCB; * so we need not worry about reading/writing to the stack pointer. */ -#define portSAVE_CONTEXT() \ - asm volatile("push r0 \n\t" \ - "in r0, __SREG__ \n\t" \ - "cli \n\t" \ - "push r0 \n\t" \ - "push r1 \n\t" \ - "clr r1 \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in r0, __SP_L__ \n\t" \ - "st x+, r0 \n\t" \ - "in r0, __SP_H__ \n\t" \ - "st x+, r0 \n\t"); +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, __SP_L__ \n\t" \ + "st x+, r0 \n\t" \ + "in r0, __SP_H__ \n\t" \ + "st x+, r0 \n\t" ); /* * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during * the context save so we can write to the stack pointer. */ -#define portRESTORE_CONTEXT() \ - asm volatile("lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop r1 \n\t" \ - "pop r0 \n\t" \ - "out __SREG__, r0 \n\t" \ - "pop r0 \n\t"); +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" ); /*-----------------------------------------------------------*/ /* * Perform hardware setup to enable ticks from timer. */ -static void prvSetupTimerInterrupt(void); +static void prvSetupTimerInterrupt( void ); /*-----------------------------------------------------------*/ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { uint16_t usAddress; /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. Uncomment if needed. */ - // *pxTopOfStack = 0x11; - // pxTopOfStack--; - // *pxTopOfStack = 0x22; - // pxTopOfStack--; - // *pxTopOfStack = 0x33; - // pxTopOfStack--; + * This is just useful for debugging. Uncomment if needed. */ + /* *pxTopOfStack = 0x11; */ + /* pxTopOfStack--; */ + /* *pxTopOfStack = 0x22; */ + /* pxTopOfStack--; */ + /* *pxTopOfStack = 0x33; */ + /* pxTopOfStack--; */ /* The start of the task code will be popped off the stack last, so place - it on first. */ - usAddress = (uint16_t)pxCode; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + * it on first. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = (StackType_t)0x00; /* R0 */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; pxTopOfStack--; /* Now the remaining registers. The compiler expects R1 to be 0. */ - *pxTopOfStack = (StackType_t)0x00; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ /* Leave R2 - R23 untouched */ pxTopOfStack -= 23; /* Place the parameter on the stack in the expected location. */ - usAddress = (uint16_t)pvParameters; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); pxTopOfStack--; usAddress >>= 8; - *pxTopOfStack = (StackType_t)(usAddress & (uint16_t)0x00ff); + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); /* Leave register R26 - R31 untouched */ pxTopOfStack -= 7; @@ -224,7 +226,7 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC } /*-----------------------------------------------------------*/ -BaseType_t xPortStartScheduler(void) +BaseType_t xPortStartScheduler( void ) { /* Setup the hardware to generate the tick. */ prvSetupTimerInterrupt(); @@ -233,15 +235,15 @@ BaseType_t xPortStartScheduler(void) portRESTORE_CONTEXT(); /* Simulate a function call end as generated by the compiler. We will now - jump to the start of the task the context of which we have just restored. */ - asm volatile("ret"); + * jump to the start of the task the context of which we have just restored. */ + asm volatile ( "ret" ); /* Should not get here. */ return pdTRUE; } /*-----------------------------------------------------------*/ -void vPortEndScheduler(void) +void vPortEndScheduler( void ) { /* vPortEndScheduler is not implemented in this port. */ } @@ -251,13 +253,13 @@ void vPortEndScheduler(void) * Manual context switch. The first thing we do is save the registers so we * can use a naked attribute. */ -void vPortYield(void) __attribute__((naked)); -void vPortYield(void) +void vPortYield( void ) __attribute__( ( naked ) ); +void vPortYield( void ) { portSAVE_CONTEXT(); vTaskSwitchContext(); portRESTORE_CONTEXT(); - asm volatile("ret"); + asm volatile ( "ret" ); } /*-----------------------------------------------------------*/ @@ -265,13 +267,13 @@ void vPortYield(void) * Manual context switch callable from ISRs. The first thing * we do is save the registers so we can use a naked attribute. */ -void vPortYieldFromISR(void) __attribute__((naked)); -void vPortYieldFromISR(void) +void vPortYieldFromISR( void ) __attribute__( ( naked ) ); +void vPortYieldFromISR( void ) { portSAVE_CONTEXT(); vTaskSwitchContext(); portRESTORE_CONTEXT(); - asm volatile("reti"); + asm volatile ( "reti" ); } /*-----------------------------------------------------------*/ @@ -281,24 +283,26 @@ void vPortYieldFromISR(void) * difference from vPortYield() is the tick count is incremented as the * call comes from the tick ISR. */ -void vPortYieldFromTick(void) __attribute__((naked)); -void vPortYieldFromTick(void) +void vPortYieldFromTick( void ) __attribute__( ( naked ) ); +void vPortYieldFromTick( void ) { portSAVE_CONTEXT(); - if (xTaskIncrementTick() != pdFALSE) { + + if( xTaskIncrementTick() != pdFALSE ) + { vTaskSwitchContext(); } portRESTORE_CONTEXT(); - asm volatile("reti"); + asm volatile ( "reti" ); } /*-----------------------------------------------------------*/ /* * Setup timer to generate a tick interrupt. */ -static void prvSetupTimerInterrupt(void) +static void prvSetupTimerInterrupt( void ) { TICK_init(); } @@ -311,26 +315,26 @@ static void prvSetupTimerInterrupt(void) * the context is saved at the start of vPortYieldFromTick(). The tick * count is incremented after the context is saved. */ -ISR(TICK_INT_vect, ISR_NAKED) -{ - /* Clear tick interrupt flag. */ - CLR_INT(INT_FLAGS, INT_MASK); + ISR( TICK_INT_vect, ISR_NAKED ) + { + /* Clear tick interrupt flag. */ + CLR_INT( INT_FLAGS, INT_MASK ); - vPortYieldFromTick(); + vPortYieldFromTick(); - asm volatile("reti"); -} -#else + asm volatile ( "reti" ); + } +#else /* if configUSE_PREEMPTION == 1 */ /* * Tick ISR for the cooperative scheduler. All this does is increment the * tick count. We don't need to switch context, this can only be done by * manual calls to taskYIELD(); */ -ISR(TICK_INT_vect) -{ - /* Clear tick interrupt flag. */ - INT_FLAGS = INT_MASK; - xTaskIncrementTick(); -} -#endif + ISR( TICK_INT_vect ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/portable/GCC/AVR_Mega0/porthardware.h b/portable/GCC/AVR_Mega0/porthardware.h index aeeccf534..8d4f1bcc3 100644 --- a/portable/GCC/AVR_Mega0/porthardware.h +++ b/portable/GCC/AVR_Mega0/porthardware.h @@ -5,86 +5,91 @@ /*-----------------------------------------------------------*/ -#define CLR_INT(FLAG_REG, FLAG_MASK) \ - asm volatile( \ - "push r16\n\t" \ - "ldi r16, %1\n\t" \ - "sts %0, r16\n\t" \ - "pop r16\n\t" \ - : \ - : "i"(_SFR_MEM_ADDR(FLAG_REG)),"i"((uint8_t)(FLAG_MASK)) \ +#define CLR_INT( FLAG_REG, FLAG_MASK ) \ + asm volatile ( \ + "push r16\n\t" \ + "ldi r16, %1\n\t" \ + "sts %0, r16\n\t" \ + "pop r16\n\t" \ + : \ + : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \ ); #if ( configUSE_TIMER_INSTANCE == 0 ) - #define TICK_INT_vect TCB0_INT_vect - #define INT_FLAGS TCB0_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB0.INTCTRL = TCB_CAPT_bm; \ - TCB0.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 1 ) - #define TICK_INT_vect TCB1_INT_vect - #define INT_FLAGS TCB1_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB1.INTCTRL = TCB_CAPT_bm; \ - TCB1.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 2 ) - #define TICK_INT_vect TCB2_INT_vect - #define INT_FLAGS TCB2_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB2.INTCTRL = TCB_CAPT_bm; \ - TCB2.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 3 ) - #define TICK_INT_vect TCB3_INT_vect - #define INT_FLAGS TCB3_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB3.INTCTRL = TCB_CAPT_bm; \ - TCB3.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 4 ) - #define TICK_INT_vect RTC_CNT_vect - #define INT_FLAGS RTC_INTFLAGS - #define INT_MASK RTC_OVF_bm + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm - /* Hertz to period for RTC setup */ - #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) ) - #define TICK_init() { \ - while (RTC.STATUS > 0); \ - RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ - RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \ - RTC.INTCTRL |= 1 << RTC_OVF_bp; \ - } +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } -#else +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ #undef TICK_INT_vect #undef INT_FLAGS #undef INT_MASK #undef TICK_init() #error Invalid timer setting. -#endif +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 3f39bc3b1..e0a0c7ef7 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -612,7 +612,7 @@ static void prvTaskExitError( void ) extern uint32_t * __unprivileged_flash_end__; extern uint32_t * __privileged_sram_start__; extern uint32_t * __privileged_sram_end__; - #else /* if defined( __ARMCC_VERSION ) */ + #else /* if defined( __ARMCC_VERSION ) */ /* Declaration when these variable are exported from linker scripts. */ extern uint32_t __privileged_functions_start__[]; extern uint32_t __privileged_functions_end__[]; @@ -802,22 +802,22 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO ulR0 = pulCallerStackAddress[ 0 ]; #if ( configENABLE_MPU == 1 ) - { - /* Read the CONTROL register value. */ - __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); - /* The task that raised the SVC is privileged if Bit[0] - * in the CONTROL register is 0. */ - ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); - } - #else /* if ( configENABLE_MPU == 1 ) */ - { - /* Allocate and load a context for the secure task. */ - xSecureContext = SecureContext_AllocateContext( ulR0 ); - } + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } #endif /* configENABLE_MPU */ configASSERT( xSecureContext != NULL ); @@ -835,21 +835,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO case portSVC_START_SCHEDULER: #if ( configENABLE_TRUSTZONE == 1 ) - { - /* De-prioritize the non-secure exceptions so that the - * non-secure pendSV runs at the lowest priority. */ - SecureInit_DePrioritizeNSExceptions(); + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); - /* Initialize the secure context management system. */ - SecureContext_Init(); - } + /* Initialize the secure context management system. */ + SecureContext_Init(); + } #endif /* configENABLE_TRUSTZONE */ #if ( configENABLE_FPU == 1 ) - { - /* Setup the Floating Point Unit (FPU). */ - prvSetupFPU(); - } + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } #endif /* configENABLE_FPU */ /* Setup the context of the first task so that the first task starts @@ -877,18 +877,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, void * pvParameters, - BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ #else StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, TaskFunction_t pxCode, - void * pvParameters ) /* PRIVILEGED_FUNCTION */ + void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ @@ -1051,7 +1053,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1079,8 +1083,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ * using a separate MPU region. This is needed because privileged * SRAM is already protected using an MPU region and ARMv8-M does * not allow overlapping MPU regions. */ - if( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ && - ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) { xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; @@ -1089,7 +1093,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Define the region that allows access to the stack. */ ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; - ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | ( portMPU_REGION_NON_SHAREABLE ) | diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 9ee28cde2..e0a0c7ef7 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO TaskFunction_t pxCode, void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 9ee28cde2..e0a0c7ef7 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO TaskFunction_t pxCode, void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 9ee28cde2..e0a0c7ef7 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -877,6 +877,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO } /*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ #if ( configENABLE_MPU == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -889,6 +890,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO TaskFunction_t pxCode, void * pvParameters ) /* PRIVILEGED_FUNCTION */ #endif /* configENABLE_MPU */ +/* *INDENT-ON* */ { /* Simulate the stack frame as it would be created by a context switch * interrupt. */ diff --git a/portable/IAR/AVR_AVRDx/port.c b/portable/IAR/AVR_AVRDx/port.c index 6c4d79fcc..e723603ff 100644 --- a/portable/IAR/AVR_AVRDx/port.c +++ b/portable/IAR/AVR_AVRDx/port.c @@ -115,9 +115,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - * portSAVE_CONTEXT places the flags on the stack immediately after r0 - * to ensure the interrupts get disabled as soon as possible, and so ensuring - * the stack use is minimal should a context switch interrupt occur. */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; diff --git a/portable/IAR/AVR_AVRDx/porthardware.h b/portable/IAR/AVR_AVRDx/porthardware.h index 195d881aa..2d17b4202 100644 --- a/portable/IAR/AVR_AVRDx/porthardware.h +++ b/portable/IAR/AVR_AVRDx/porthardware.h @@ -8,86 +8,92 @@ #if ( configUSE_TIMER_INSTANCE == 0 ) - #define TICK_INT_vect TCB0_INT_vect - #define INT_FLAGS TCB0_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB0.INTCTRL = TCB_CAPT_bm; \ - TCB0.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 1 ) - #define TICK_INT_vect TCB1_INT_vect - #define INT_FLAGS TCB1_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB1.INTCTRL = TCB_CAPT_bm; \ - TCB1.CTRLA = TCB_ENABLE_bm; \ - } - + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } + #elif ( configUSE_TIMER_INSTANCE == 2 ) - #define TICK_INT_vect TCB2_INT_vect - #define INT_FLAGS TCB2_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } - #define TICK_init() { \ - TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB2.INTCTRL = TCB_CAPT_bm; \ - TCB2.CTRLA = TCB_ENABLE_bm; \ - } - #elif ( configUSE_TIMER_INSTANCE == 3 ) - #define TICK_INT_vect TCB3_INT_vect - #define INT_FLAGS TCB3_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB3.INTCTRL = TCB_CAPT_bm; \ - TCB3.CTRLA = TCB_ENABLE_bm; \ - } - + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } + #elif ( configUSE_TIMER_INSTANCE == 4 ) - #define TICK_INT_vect TCB4_INT_vect - #define INT_FLAGS TCB4_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB4.INTCTRL = TCB_CAPT_bm; \ - TCB4.CTRLA = TCB_ENABLE_bm; \ - } - -#elif ( configUSE_TIMER_INSTANCE == 5 ) - - #define TICK_INT_vect RTC_CNT_vect - #define INT_FLAGS RTC_INTFLAGS - #define INT_MASK RTC_OVF_bm - - /* Hertz to period for RTC setup */ - #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) ) - #define TICK_init() { \ - while (RTC.STATUS > 0); \ - RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ - RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \ - RTC.INTCTRL |= 1 << RTC_OVF_bp; \ - } + #define TICK_INT_vect TCB4_INT_vect + #define INT_FLAGS TCB4_INTFLAGS + #define INT_MASK TCB_CAPT_bm -#else + #define TICK_init() \ + { \ + TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB4.INTCTRL = TCB_CAPT_bm; \ + TCB4.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 5 ) + + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm + +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } + +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ #undef TICK_INT_vect #undef INT_FLAGS #undef INT_MASK #undef TICK_init() #error Invalid timer setting. -#endif +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/AVR_Mega0/port.c b/portable/IAR/AVR_Mega0/port.c index 5af99c1ad..b2d35638d 100644 --- a/portable/IAR/AVR_Mega0/port.c +++ b/portable/IAR/AVR_Mega0/port.c @@ -115,9 +115,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - * portSAVE_CONTEXT places the flags on the stack immediately after r0 - * to ensure the interrupts get disabled as soon as possible, and so ensuring - * the stack use is minimal should a context switch interrupt occur. */ + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ pxTopOfStack--; *pxTopOfStack = portFLAGS_INT_ENABLED; diff --git a/portable/IAR/AVR_Mega0/porthardware.h b/portable/IAR/AVR_Mega0/porthardware.h index 5468bdabe..4188ae274 100644 --- a/portable/IAR/AVR_Mega0/porthardware.h +++ b/portable/IAR/AVR_Mega0/porthardware.h @@ -8,74 +8,79 @@ #if ( configUSE_TIMER_INSTANCE == 0 ) - #define TICK_INT_vect TCB0_INT_vect - #define INT_FLAGS TCB0_INTFLAGS - #define INT_MASK TCB_CAPT_bm + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm - #define TICK_init() { \ - TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB0.INTCTRL = TCB_CAPT_bm; \ - TCB0.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 1 ) - #define TICK_INT_vect TCB1_INT_vect - #define INT_FLAGS TCB1_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB1.INTCTRL = TCB_CAPT_bm; \ - TCB1.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 2 ) - #define TICK_INT_vect TCB2_INT_vect - #define INT_FLAGS TCB2_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB2.INTCTRL = TCB_CAPT_bm; \ - TCB2.CTRLA = TCB_ENABLE_bm; \ - } - + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } + #elif ( configUSE_TIMER_INSTANCE == 3 ) - #define TICK_INT_vect TCB3_INT_vect - #define INT_FLAGS TCB3_INTFLAGS - #define INT_MASK TCB_CAPT_bm - - #define TICK_init() { \ - TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ - TCB3.INTCTRL = TCB_CAPT_bm; \ - TCB3.CTRLA = TCB_ENABLE_bm; \ - } + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } #elif ( configUSE_TIMER_INSTANCE == 4 ) - #define TICK_INT_vect RTC_CNT_vect - #define INT_FLAGS RTC_INTFLAGS - #define INT_MASK RTC_OVF_bm - - /* Hertz to period for RTC setup */ - #define RTC_PERIOD_HZ(x) ( 32768 * ( ( 1.0 / x ) ) ) - #define TICK_init() { \ - while (RTC.STATUS > 0); \ - RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ - RTC.PER = RTC_PERIOD_HZ(configTICK_RATE_HZ); \ - RTC.INTCTRL |= 1 << RTC_OVF_bp; \ - } + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm -#else +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } + +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ #undef TICK_INT_vect #undef INT_FLAGS #undef INT_MASK #undef TICK_init() #error Invalid timer setting. -#endif +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ /*-----------------------------------------------------------*/ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c index b2e371623..360202a47 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/port.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -41,6 +41,7 @@ volatile unsigned int ulCriticalNesting = 999UL; volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */ + /** * \var exc_nest_count * \brief the counter for exc/int processing, =0 no int/exc diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c index 414dbfdc0..70bccf1aa 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c @@ -154,6 +154,7 @@ void _xt_user_exit( void ); /* * Stack initialization */ +/* *INDENT-OFF* */ #if portUSING_MPU_WRAPPERS StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, @@ -164,6 +165,7 @@ void _xt_user_exit( void ); TaskFunction_t pxCode, void * pvParameters ) #endif +/* *INDENT-ON* */ { StackType_t * sp, * tp; XtExcFrame * frame; @@ -409,7 +411,7 @@ void vPortCPUInitializeMutex( portMUX_TYPE * mux ) return result; } -#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ +#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ void vPortCPUAcquireMutex( portMUX_TYPE * mux ) { unsigned int irqStatus = portENTER_CRITICAL_NESTED(); diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c index 2bf1da7ef..63789951d 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c @@ -35,9 +35,9 @@ #include "xtensa_rtos.h" #if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/clk.h" + #include "esp32s2/clk.h" #elif CONFIG_IDF_TARGET_ESP32 -#include "esp32/clk.h" + #include "esp32/clk.h" #endif #ifdef XT_RTOS_TIMER_INT diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c index 93e416068..8e1465df5 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c @@ -35,9 +35,9 @@ #include "freertos/portable.h" #if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/ets_sys.h" + #include "esp32s2/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" + #include "esp32/rom/ets_sys.h" #endif #if XCHAL_HAVE_EXCEPTIONS