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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Add support for double precision floating point.
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@ -80,6 +80,10 @@
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#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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extern const unsigned _SDA_BASE_;
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extern const unsigned _SDA2_BASE_;
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/*
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/*
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@ -123,12 +127,18 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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pxTopOfStack--;
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pxTopOfStack--;
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/* EABI stack frame. */
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/* EABI stack frame. */
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pxTopOfStack -= 30; /* Previous backchain and LR, R31 to R4 inclusive. */
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pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
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/* Parameters in R13. */
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*pxTopOfStack = ( portSTACK_TYPE ) &_SDA_BASE_; /* address of the first small data area */
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pxTopOfStack -= 10;
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/* Parameters in R3. */
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/* Parameters in R3. */
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
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pxTopOfStack--;
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pxTopOfStack--;
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*pxTopOfStack = 0x02020202UL; /* R2. */
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/* Parameters in R2. */
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*pxTopOfStack = ( portSTACK_TYPE ) &_SDA2_BASE_; /* address of the second small data area */
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pxTopOfStack--;
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pxTopOfStack--;
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/* R1 is the stack pointer so is omitted. */
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/* R1 is the stack pointer so is omitted. */
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@ -212,6 +212,49 @@ vPortSaveFPURegisters:
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or r0, r0, r30
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or r0, r0, r30
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mtmsr r0
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mtmsr r0
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#ifdef USE_DP_FPU
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/* Buffer address is in r3. Save each flop register into an offset from
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this buffer address. */
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stfd f0, 0(r3)
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stfd f1, 8(r3)
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stfd f2, 16(r3)
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stfd f3, 24(r3)
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stfd f4, 32(r3)
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stfd f5, 40(r3)
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stfd f6, 48(r3)
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stfd f7, 56(r3)
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stfd f8, 64(r3)
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stfd f9, 72(r3)
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stfd f10, 80(r3)
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stfd f11, 88(r3)
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stfd f12, 96(r3)
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stfd f13, 104(r3)
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stfd f14, 112(r3)
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stfd f15, 120(r3)
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stfd f16, 128(r3)
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stfd f17, 136(r3)
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stfd f18, 144(r3)
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stfd f19, 152(r3)
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stfd f20, 160(r3)
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stfd f21, 168(r3)
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stfd f22, 176(r3)
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stfd f23, 184(r3)
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stfd f24, 192(r3)
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stfd f25, 200(r3)
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stfd f26, 208(r3)
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stfd f27, 216(r3)
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stfd f28, 224(r3)
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stfd f29, 232(r3)
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stfd f30, 240(r3)
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stfd f31, 248(r3)
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/* Also save the FPSCR. */
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mffs f31
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stfs f31, 256(r3)
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#else
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/* Buffer address is in r3. Save each flop register into an offset from
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/* Buffer address is in r3. Save each flop register into an offset from
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this buffer address. */
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this buffer address. */
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stfs f0, 0(r3)
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stfs f0, 0(r3)
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@ -250,6 +293,8 @@ vPortSaveFPURegisters:
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/* Also save the FPSCR. */
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/* Also save the FPSCR. */
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mffs f31
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mffs f31
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stfs f31, 128(r3)
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stfs f31, 128(r3)
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#endif
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blr
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blr
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@ -268,6 +313,49 @@ vPortRestoreFPURegisters:
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or r0, r0, r30
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or r0, r0, r30
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mtmsr r0
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mtmsr r0
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#ifdef USE_DP_FPU
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/* Buffer address is in r3. Restore each flop register from an offset
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into this buffer.
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First the FPSCR. */
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lfs f31, 256(r3)
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mtfsf f31, 7
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lfd f0, 0(r3)
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lfd f1, 8(r3)
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lfd f2, 16(r3)
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lfd f3, 24(r3)
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lfd f4, 32(r3)
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lfd f5, 40(r3)
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lfd f6, 48(r3)
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lfd f7, 56(r3)
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lfd f8, 64(r3)
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lfd f9, 72(r3)
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lfd f10, 80(r3)
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lfd f11, 88(r3)
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lfd f12, 96(r3)
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lfd f13, 104(r3)
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lfd f14, 112(r3)
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lfd f15, 120(r3)
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lfd f16, 128(r3)
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lfd f17, 136(r3)
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lfd f18, 144(r3)
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lfd f19, 152(r3)
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lfd f20, 160(r3)
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lfd f21, 168(r3)
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lfd f22, 176(r3)
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lfd f23, 184(r3)
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lfd f24, 192(r3)
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lfd f25, 200(r3)
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lfd f26, 208(r3)
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lfd f27, 216(r3)
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lfd f28, 224(r3)
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lfd f29, 232(r3)
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lfd f30, 240(r3)
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lfd f31, 248(r3)
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#else
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/* Buffer address is in r3. Restore each flop register from an offset
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/* Buffer address is in r3. Restore each flop register from an offset
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into this buffer.
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into this buffer.
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@ -309,6 +397,8 @@ vPortRestoreFPURegisters:
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lfs f30, 120(r3)
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lfs f30, 120(r3)
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lfs f31, 124(r3)
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lfs f31, 124(r3)
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#endif
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blr
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blr
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#endif /* configUSE_FPU. */
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#endif /* configUSE_FPU. */
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