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- - Overview - - - Block Diagram - - - External Ports - - - - - -  - memory map - - Debuggers - - - Interrupt Controllers - - - Busses - - - Bridges - - - Memory - - - Memory Controllers - - - Peripherals - - - IP - - - Timing Information - |
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| EXTERNAL PORTS | -
| - - These are the external ports defined in the MHS file. - - | - -
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- Attributes Key
- - The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file - - CLK - indicates Clock ports, (SIGIS = CLK) - - INTR - indicates Interrupt ports,(SIGIS = INTR) - - RESET - indicates Reset ports, (SIGIS = RST) - - BUF or REG - Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) - |
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- These are the post synthesis clock frequencies. The critical frequencies are marked with
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- - - The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system. - - |
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| Parameters | -
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| Resource Type | -Used | -Available | -Percent | - -
| PORT LIST | -
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- The ports listed here are only those connected in the MHS file.
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| # | -NAME | -DIR | -[LSB:MSB] | -SIGNAL | -
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| - Bus Interfaces - | -
| MASTERSHIP | -NAME | -STD | -BUS | -P2P | -
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| TYPE | -NAME | -BIF | -
| - Interrupt Priorities - |
| Priority | -SIG | -MODULE | -
| - - MEMORY MAP - | -
| D=DATA ADDRESSABLE I=INSTRUCTION ADDRESSABLE | -
| D | -I | -BASE | -HIGH | -MODULE | -
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| TABLE OF CONTENTS | -
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- - Overview - - - Block Diagram - - - External Ports - - -
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- Debuggers
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- Interrupt Controllers
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- Busses
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- Bridges
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- Memory
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- IP
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| EXTERNAL PORTS | -
| - These are the external ports defined in the MHS file. - | -
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-Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLKÂ Â indicates Clock ports, (SIGIS = CLK)Â INTRÂ Â indicates Interrupt ports,(SIGIS = INTR)Â RESETÂ Â indicates Reset ports, (SIGIS = RST)Â BUF or REGÂ Â Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)Â - |
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- - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg deleted file mode 100644 index 5991ebf29..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg +++ /dev/null @@ -1,1473 +0,0 @@ - - - - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf deleted file mode 100644 index 0b81c8ff8..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf +++ /dev/null @@ -1,398 +0,0 @@ -############################################################################ -## This system.ucf file is generated by Base System Builder based on the -## settings in the selected Xilinx Board Definition file. Please add other -## user constraints to this file based on customer design specifications. -############################################################################ - -Net sys_clk_pin LOC=AE14; -Net sys_clk_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin LOC=D6; -Net sys_rst_pin PULLUP; -## System level constraints -Net sys_clk_pin TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; -Net sys_rst_pin TIG; -NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; -TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; -Net fpga_0_SRAM_CLOCK LOC=AF7; -Net fpga_0_SRAM_CLOCK SLEW = FAST; -Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_CLOCK DRIVE = 16; - -## IO Devices constraints - -#### Module RS232_Uart constraints - -Net fpga_0_RS232_Uart_RX_pin LOC=W2; -Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_RS232_Uart_TX_pin LOC=W1; -Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; - -#### Module LEDs_4Bit constraints - -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; - -#### Module LEDs_Positions constraints - -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; - -#### Module SysACE_CompactFlash constraints - -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF11; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=Y10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AA10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AC7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=Y7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AB7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AC9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AE6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AD6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AF9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AE9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AD8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AC8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AF4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AC3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AF6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AF5; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AD5; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AA8; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=Y8; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG; - -#### Module SRAM constraints - -Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; -Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; -Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; -Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; -Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; -Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; -Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; -Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; -Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; -Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; -Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; -Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; -Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; -Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; -Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; -Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; -Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; -Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; -Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; -Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; -Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; -Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; -Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; -Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; -Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; -Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; -Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; -Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; -Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; -Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; -Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; -Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; -Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; -Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; -Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; -Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; -Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; -Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; -Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; -Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; -Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; -Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; -Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; -Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; -Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; -Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; -Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; -Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; -Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; -Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; -Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; -Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; -Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; -Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; -Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; -Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; -Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; -Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; -Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; -Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; -Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; -Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; -Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; -Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; - diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut deleted file mode 100644 index 976536332..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut +++ /dev/null @@ -1,20 +0,0 @@ --g CclkPin:PULLUP --g TdoPin:PULLNONE --g M1Pin:PULLDOWN --g DonePin:PULLUP --g DriveDone:No --g StartUpClk:JTAGCLK --g DONE_cycle:4 --g GTS_cycle:5 --g M0Pin:PULLUP --g M2Pin:PULLUP --g ProgPin:PULLUP --g TckPin:PULLUP --g TdiPin:PULLUP --g TmsPin:PULLUP --g DonePipe:No --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:NONE -#-m --g Persist:No diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd deleted file mode 100644 index 15728dcff..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 3 -file implementation/download.bit -program -p 3 -quit diff --git a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt deleted file mode 100644 index 6cc2599ab..000000000 --- a/FreeRTOS/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt +++ /dev/null @@ -1,82 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p
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| TABLE OF CONTENTS | -
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- - Overview - - - Block Diagram - - - External Ports - - - - - - - memory map - - Debuggers - - - Interrupt Controllers - - - Busses - - - Bridges - - - Memory - - - Memory Controllers - - - Peripherals - - - IP - - - Timing Information - |
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| EXTERNAL PORTS | -
| - - These are the external ports defined in the MHS file. - - | - -
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- Attributes Key
- - The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file - - CLK - indicates Clock ports, (SIGIS = CLK) - - INTR - indicates Interrupt ports,(SIGIS = INTR) - - RESET - indicates Reset ports, (SIGIS = RST) - - BUF or REG - Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) - |
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- These are the post synthesis clock frequencies. The critical frequencies are marked with
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- - - The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system. - - |
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| MODULE | -CLK Port | -MAX FREQ | - -
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- These are parameters set for this module.
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| Post Synthesis Device Utilization | -
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| Resource Type | -Used | -Available | -Percent | - -
| PORT LIST | -
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- The ports listed here are only those connected in the MHS file.
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| # | -NAME | -DIR | -[LSB:MSB] | -SIGNAL | -
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| - Bus Interfaces - | -
| MASTERSHIP | -NAME | -STD | -BUS | -P2P | -
| Bus Connections | -
| TYPE | -NAME | -BIF | -
| - Interrupt Priorities - |
| Priority | -SIG | -MODULE | -
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| D | -I | -BASE | -HIGH | -MODULE | -
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| TABLE OF CONTENTS | -
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- - Overview - - - Block Diagram - - - External Ports - - -
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| EXTERNAL PORTS | -
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-Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLKÂ Â indicates Clock ports, (SIGIS = CLK)Â INTRÂ Â indicates Interrupt ports,(SIGIS = INTR)Â RESETÂ Â indicates Reset ports, (SIGIS = RST)Â BUF or REGÂ Â Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)Â - |
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-
- - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg deleted file mode 100644 index 182a3ecff..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg +++ /dev/null @@ -1,1452 +0,0 @@ - - - - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf deleted file mode 100644 index 0b81c8ff8..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf +++ /dev/null @@ -1,398 +0,0 @@ -############################################################################ -## This system.ucf file is generated by Base System Builder based on the -## settings in the selected Xilinx Board Definition file. Please add other -## user constraints to this file based on customer design specifications. -############################################################################ - -Net sys_clk_pin LOC=AE14; -Net sys_clk_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin LOC=D6; -Net sys_rst_pin PULLUP; -## System level constraints -Net sys_clk_pin TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; -Net sys_rst_pin TIG; -NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; -NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; -TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; -Net fpga_0_SRAM_CLOCK LOC=AF7; -Net fpga_0_SRAM_CLOCK SLEW = FAST; -Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_CLOCK DRIVE = 16; - -## IO Devices constraints - -#### Module RS232_Uart constraints - -Net fpga_0_RS232_Uart_RX_pin LOC=W2; -Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_RS232_Uart_TX_pin LOC=W1; -Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; - -#### Module LEDs_4Bit constraints - -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; - -#### Module LEDs_Positions constraints - -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; - -#### Module SysACE_CompactFlash constraints - -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF11; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=Y10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AA10; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AC7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=Y7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AB7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AC9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AE6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AD6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AF9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AE9; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AD8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AC8; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AF4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AC3; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AF6; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AF5; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA7; -Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AD5; -Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AA8; -Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=Y8; -Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD4; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG; - -#### Module SRAM constraints - -Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; -Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; -Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; -Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; -Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; -Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; -Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; -Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; -Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; -Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; -Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; -Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; -Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; -Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; -Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; -Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; -Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; -Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; -Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; -Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; -Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; -Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; -Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; -Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; -Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; -Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; -Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; -Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; -Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; -Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; -Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; -Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; -Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; -Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; -Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; -Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; -Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; -Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; -Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; -Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; -Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; -Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; -Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; -Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; -Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; -Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; -Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; -Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; -Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; -Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; -Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; -Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; -Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; -Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; -Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; -Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; -Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; -Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; -Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; -Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; -Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; -Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; -Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; -Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; -Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; -Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; -Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; -Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; -Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; -Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; - diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut deleted file mode 100644 index 976536332..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut +++ /dev/null @@ -1,20 +0,0 @@ --g CclkPin:PULLUP --g TdoPin:PULLNONE --g M1Pin:PULLDOWN --g DonePin:PULLUP --g DriveDone:No --g StartUpClk:JTAGCLK --g DONE_cycle:4 --g GTS_cycle:5 --g M0Pin:PULLUP --g M2Pin:PULLUP --g ProgPin:PULLUP --g TckPin:PULLUP --g TdiPin:PULLUP --g TmsPin:PULLUP --g DonePipe:No --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:NONE -#-m --g Persist:No diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd deleted file mode 100644 index 15728dcff..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 3 -file implementation/download.bit -program -p 3 -quit diff --git a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt deleted file mode 100644 index 6cc2599ab..000000000 --- a/FreeRTOS/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt +++ /dev/null @@ -1,82 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p
404 - file not found
AT91SAM7X Embedded WEB Server Demo
Using uIP and the FreeRTOS real time kernel
These pages are being served by an Atmel AT91SAM7X256 microcontroller, using Adam Dunkels open source uIP TCP/IP stack.
The uIP stack is executing from a single task under control of the FreeRTOS real time kernel. The table below shows the statistics for all the tasks in the demo applicaiton.
Task State Priority Stack #-. - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats deleted file mode 100644 index 2c71c90dc..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats +++ /dev/null @@ -1,4 +0,0 @@ -i /stats_header.html -c a -i /stats_footer.plain -. diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp deleted file mode 100644 index 14efd3700..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp +++ /dev/null @@ -1,4 +0,0 @@ -i /tcp_header.html -c c -i /tcp_footer.plain -. \ No newline at end of file diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html deleted file mode 100644 index 0d9352ce7..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html +++ /dev/null @@ -1,20 +0,0 @@ - - -
************************************************
-c d -t
-Tasks |
-Connections |
-Files |
-Statistics-
- - - - - - - - diff --git a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain b/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/FreeRTOS/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ - -