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Work in progress - checked in for backup only.

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This commit is contained in:
Richard Barry 2010-06-07 15:24:50 +00:00
parent 02db572328
commit e03f239692
13 changed files with 1240 additions and 336 deletions
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34
Demo/CORTEX_STM32F103_GCC_Rowley/main.c
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@ -100,28 +100,16 @@ check task has detected an error or not. */
#define mainCHECK_DELAY_ERROR ( ( portTickType ) 500 / portTICK_RATE_MS )
/* The LED controlled by the 'check' task. */
#define mainCHECK_LED ( 7 )
#define mainCHECK_LED ( 3 )
/* Task priorities. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
/* The WEB server has a larger stack as it utilises stack hungry string
handling library calls. */
#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 4 )
/* The length of the queue used to send messages to the LCD task. */
#define mainQUEUE_SIZE ( 3 )
/* The period of the system clock in nano seconds. This is used to calculate
the jitter time in nano seconds. */
#define mainNS_PER_CLOCK ( ( unsigned long ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )
/*-----------------------------------------------------------*/
/*
@ -222,31 +210,31 @@ static void prvSetupHardware( void )
RCC_DeInit ();
/* Enable HSE. */
RCC_HSEConfig (RCC_HSE_ON);
RCC_HSEConfig( RCC_HSE_ON );
/* Wait till HSE is ready. */
while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);
/* HCLK = SYSCLK. */
RCC_HCLKConfig (RCC_SYSCLK_Div1);
RCC_HCLKConfig( RCC_SYSCLK_Div1 );
/* PCLK2 = HCLK. */
RCC_PCLK2Config (RCC_HCLK_Div1);
RCC_PCLK2Config( RCC_HCLK_Div1 );
/* PCLK1 = HCLK/2. */
RCC_PCLK1Config (RCC_HCLK_Div2);
RCC_PCLK1Config( RCC_HCLK_Div2 );
/* ADCCLK = PCLK2/4. */
RCC_ADCCLKConfig (RCC_PCLK2_Div4);
RCC_ADCCLKConfig( RCC_PCLK2_Div4 );
/* Flash 2 wait state. */
*( volatile unsigned long * )0x40022000 = 0x01;
/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLConfig (RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_9 );
/* Enable PLL. */
RCC_PLLCmd (ENABLE);
RCC_PLLCmd( ENABLE );
/* Wait till PLL is ready. */
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
@ -271,6 +259,12 @@ static void prvSetupHardware( void )
/* Initialise the IO used for the LED outputs. */
vParTestInitialise();
/* SPI2 Periph clock enable */
RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE );
/* Initialize the SPI FLASH driver */
SPI_FLASH_Init();
}
/*-----------------------------------------------------------*/