mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Add tickless idle support in Cortex-M ports.
Change CCS R4 directory name.
This commit is contained in:
Richard Barry
parent
6ec4c7cecb
commit
e03ab659f3
21 changed files with 2395 additions and 596 deletions
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@ -1,6 +1,6 @@
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/*
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FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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***************************************************************************
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* *
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@ -40,7 +40,7 @@
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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||||
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||||
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***************************************************************************
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||||
* *
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* Having a problem? Start by reading the FAQ "My application does *
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||||
|
|
@ -50,17 +50,17 @@
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* *
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||||
***************************************************************************
|
||||
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http://www.FreeRTOS.org - Documentation, training, latest information,
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, training, latest information,
|
||||
license and contact details.
|
||||
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool.
|
||||
|
||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
|
||||
the code with commercial support, indemnification, and middleware, under
|
||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
|
||||
the code with commercial support, indemnification, and middleware, under
|
||||
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
|
||||
provide a safety engineered and independently SIL3 certified version under
|
||||
provide a safety engineered and independently SIL3 certified version under
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||||
the SafeRTOS brand: http://www.SafeRTOS.com.
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*/
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@ -76,15 +76,33 @@
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#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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#endif
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/* Constants required to manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )
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#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )
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#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )
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#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )
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#define portNVIC_SYSTICK_CLK 0x00000004
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#define portNVIC_SYSTICK_INT 0x00000002
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#define portNVIC_SYSTICK_ENABLE 0x00000001
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#define portNVIC_PENDSVSET 0x10000000
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#ifndef configSYSTICK_CLOCK_HZ
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#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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#if configUSE_TICKLESS_IDLE == 1
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static const unsigned long ulStoppedTimerCompensation = 45UL;
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#endif
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#else /* configSYSTICK_CLOCK_HZ */
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#if configUSE_TICKLESS_IDLE == 1
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/* Assumes the SysTick clock is slower than the CPU clock. */
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static const unsigned long ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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#endif
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#endif /* configSYSTICK_CLOCK_HZ */
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/* Constants required to manipulate the core. Registers first... */
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#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
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#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
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#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
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/* ...then bits in the registers. */
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
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#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
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@ -119,6 +137,21 @@ extern void vPortStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/*
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* The number of SysTick increments that make up one tick period.
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*/
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static unsigned long ulTimerReloadValueForOneTick = 0;
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/*
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* The maximum number of tick periods that can be suppressed is limited by the
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* 24 bit resolution of the SysTick timer.
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*/
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#if configUSE_TICKLESS_IDLE == 1
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static unsigned long xMaximumPossibleSuppressedTicks = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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@ -146,13 +179,13 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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portBASE_TYPE xPortStartScheduler( void )
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{
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/* Make PendSV and SysTick the lowest priority interrupts. */
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*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
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*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
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portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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@ -174,7 +207,7 @@ void vPortEndScheduler( void )
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void vPortYieldFromISR( void )
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{
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/* Set a PendSV to request a context switch. */
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*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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/*-----------------------------------------------------------*/
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@ -197,30 +230,142 @@ void vPortExitCritical( void )
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void xPortSysTickHandler( void )
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{
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unsigned long ulDummy;
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/* If using preemption, also force a context switch. */
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#if configUSE_PREEMPTION == 1
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*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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#endif
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ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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#if configUSE_TICKLESS_IDLE == 1
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portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;
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#endif
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( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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{
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vTaskIncrementTick();
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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}
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/*-----------------------------------------------------------*/
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#if configUSE_TICKLESS_IDLE == 1
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__weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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{
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unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;
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/* Make sure the SysTick reload value does not overflow the counter. */
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if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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{
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xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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}
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/* Calculate the reload value required to wait xExpectedIdleTime
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tick periods. -1 is used because this code will execute part way
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through one of the tick periods, and the fraction of a tick period is
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accounted for later. */
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ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );
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if( ulReloadValue > ulStoppedTimerCompensation )
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{
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ulReloadValue -= ulStoppedTimerCompensation;
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}
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/* Stop the SysTick momentarily. The time the SysTick is stopped for
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is accounted for as best it can be, but using the tickless mode will
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inevitably result in some tiny drift of the time maintained by the
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kernel with respect to calendar time. */
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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/* If a context switch is pending then abandon the low power entry as
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the context switch might have been pended by an external interrupt that
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requires processing. */
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if( ( portNVIC_INT_CTRL_REG & portNVIC_PENDSVSET_BIT ) != 0 )
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{
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/* Restart SysTick. */
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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}
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else
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{
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/* Adjust the reload value to take into account that the current
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time slice is already partially complete. */
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ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );
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portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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/* Clear the SysTick count flag and set the count value back to
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zero. */
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Restart SysTick. */
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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/* Sleep until something happens. */
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portPRE_SLEEP_PROCESSING();
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__WFI();
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portPOST_SLEEP_PROCESSING();
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/* Stop SysTick. Again, the time the SysTick is stopped for is
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accounted for as best it can be, but using the tickless mode will
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inevitably result in some tiny drift of the time maintained by the
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kernel with respect to calendar time. */
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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{
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/* The tick interrupt has already executed, and the SysTick
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count reloaded with the portNVIC_SYSTICK_LOAD_REG value.
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Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of
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this tick period. */
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portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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/* The tick interrupt handler will already have pended the tick
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processing in the kernel. As the pending tick will be
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processed as soon as this function exits, the tick value
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maintained by the tick is stepped forward by one less than the
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time spent waiting. */
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ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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}
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else
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{
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/* Something other than the tick interrupt ended the sleep.
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Work out how long the sleep lasted. */
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ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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/* How many complete tick periods passed while the processor
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was waiting? */
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ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;
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/* The reload value is set to whatever fraction of a single tick
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period remains. */
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portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;
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}
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/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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value. */
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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vTaskStepTick( ulCompleteTickPeriods );
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}
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}
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#endif /* #if configUSE_TICKLESS_IDLE */
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/*-----------------------------------------------------------*/
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/*
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* Setup the systick timer to generate the tick interrupts at the required
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* frequency.
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*/
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void prvSetupTimerInterrupt( void )
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{
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/* Configure the constants required to setup the tick interrupt. */
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ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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#if configUSE_TICKLESS_IDLE == 1
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xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
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#endif /* configUSE_TICKLESS_IDLE */
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/* Configure SysTick to interrupt at the requested rate. */
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*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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}
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/*-----------------------------------------------------------*/
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@ -40,7 +40,7 @@
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FreeRTOS WEB site.
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||||
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||||
1 tab == 4 spaces!
|
||||
|
||||
|
||||
***************************************************************************
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||||
* *
|
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* Having a problem? Start by reading the FAQ "My application does *
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||||
|
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@ -50,51 +50,36 @@
|
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* *
|
||||
***************************************************************************
|
||||
|
||||
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http://www.FreeRTOS.org - Documentation, training, latest information,
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, training, latest information,
|
||||
license and contact details.
|
||||
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool.
|
||||
|
||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
|
||||
the code with commercial support, indemnification, and middleware, under
|
||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
|
||||
the code with commercial support, indemnification, and middleware, under
|
||||
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
|
||||
provide a safety engineered and independently SIL3 certified version under
|
||||
provide a safety engineered and independently SIL3 certified version under
|
||||
the SafeRTOS brand: http://www.SafeRTOS.com.
|
||||
*/
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#include <FreeRTOSConfig.h>
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/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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defined. The value zero should also ensure backward compatibility.
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FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
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#ifndef configKERNEL_INTERRUPT_PRIORITY
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#define configKERNEL_INTERRUPT_PRIORITY 0
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#endif
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RSEG CODE:CODE(2)
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thumb
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EXTERN vPortYieldFromISR
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EXTERN pxCurrentTCB
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EXTERN vTaskSwitchContext
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PUBLIC vSetMSP
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PUBLIC xPortPendSVHandler
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PUBLIC vPortSetInterruptMask
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PUBLIC ulPortSetInterruptMask
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PUBLIC vPortClearInterruptMask
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PUBLIC vPortSVCHandler
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PUBLIC vPortStartFirstTask
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/*-----------------------------------------------------------*/
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vSetMSP
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msr msp, r0
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bx lr
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/*-----------------------------------------------------------*/
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xPortPendSVHandler:
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@ -122,28 +107,26 @@ xPortPendSVHandler:
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/*-----------------------------------------------------------*/
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vPortSetInterruptMask:
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mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr BASEPRI, r0
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ulPortSetInterruptMask:
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mrs r0, basepri
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mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r1
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bx r14
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/*-----------------------------------------------------------*/
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vPortClearInterruptMask:
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
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http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
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mov r0, #0
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msr BASEPRI, r0
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msr basepri, r0
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bx r14
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/*-----------------------------------------------------------*/
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vPortSVCHandler;
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vPortSVCHandler:
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/* Get the location of the current TCB. */
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ldr r3, =pxCurrentTCB
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ldr r1, [r3]
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ldr r0, [r1]
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/* Pop the core registers. */
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ldmia r0!, {r4-r11}
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msr psp, r0
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mov r0, #0
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|
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@ -106,15 +106,13 @@ extern "C" {
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#define portBYTE_ALIGNMENT 8
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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extern void vPortYieldFromISR( void );
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#define portYIELD() vPortYieldFromISR()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
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/*-----------------------------------------------------------*/
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/* Architecture specific optimisations. */
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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@ -131,32 +129,36 @@ extern void vPortYieldFromISR( void );
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#include <intrinsics.h>
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( ( uxReadyPriorities ) ) )
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#endif /* taskRECORD_READY_PRIORITY */
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/* Critical section management. */
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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extern void vPortSetInterruptMask( void );
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extern void vPortClearInterruptMask( void );
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#define portDISABLE_INTERRUPTS() vPortSetInterruptMask()
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#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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|
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/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
/* Critical section management. */
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
extern unsigned long ulPortSetInterruptMask( void );
|
||||
extern void vPortClearInterruptMask( unsigned long ulNewMask );
|
||||
|
||||
#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
|
||||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Tickless/low power functionality. */
|
||||
extern void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime );
|
||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||
not necessary for to use this port. They are defined so the common demo files
|
||||
(which build with all the ports) will build. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* portNOP() is not required by this port. */
|
||||
#define portNOP()
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
|
||||
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
FreeRTOS WEB site.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Having a problem? Start by reading the FAQ "My application does *
|
||||
|
|
@ -50,17 +50,17 @@
|
|||
* *
|
||||
***************************************************************************
|
||||
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, training, latest information,
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, training, latest information,
|
||||
license and contact details.
|
||||
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool.
|
||||
|
||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
|
||||
the code with commercial support, indemnification, and middleware, under
|
||||
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
|
||||
the code with commercial support, indemnification, and middleware, under
|
||||
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
|
||||
provide a safety engineered and independently SIL3 certified version under
|
||||
provide a safety engineered and independently SIL3 certified version under
|
||||
the SafeRTOS brand: http://www.SafeRTOS.com.
|
||||
*/
|
||||
|
||||
|
|
@ -80,15 +80,33 @@
|
|||
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
|
||||
#endif
|
||||
|
||||
/* Constants required to manipulate the NVIC. */
|
||||
#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 )
|
||||
#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 )
|
||||
#define portNVIC_INT_CTRL ( ( volatile unsigned long * ) 0xe000ed04 )
|
||||
#define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 )
|
||||
#define portNVIC_SYSTICK_CLK 0x00000004
|
||||
#define portNVIC_SYSTICK_INT 0x00000002
|
||||
#define portNVIC_SYSTICK_ENABLE 0x00000001
|
||||
#define portNVIC_PENDSVSET 0x10000000
|
||||
#ifndef configSYSTICK_CLOCK_HZ
|
||||
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
|
||||
#if configUSE_TICKLESS_IDLE == 1
|
||||
static const unsigned long ulStoppedTimerCompensation = 45UL;
|
||||
#endif
|
||||
#else /* configSYSTICK_CLOCK_HZ */
|
||||
#if configUSE_TICKLESS_IDLE == 1
|
||||
/* Assumes the SysTick clock is slower than the CPU clock. */
|
||||
static const unsigned long ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
||||
#endif
|
||||
#endif /* configSYSTICK_CLOCK_HZ */
|
||||
|
||||
/* Constants required to manipulate the core. Registers first... */
|
||||
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
|
||||
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
|
||||
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
|
||||
#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
|
||||
#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
|
||||
/* ...then bits in the registers. */
|
||||
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
|
||||
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
|
||||
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
|
||||
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
|
||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
||||
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
|
||||
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
|
||||
|
||||
#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
|
||||
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
|
||||
|
||||
|
|
@ -120,12 +138,27 @@ void xPortSysTickHandler( void );
|
|||
extern void vPortStartFirstTask( void );
|
||||
|
||||
/*
|
||||
* Functions defined in portasm.s to enable the VFP.
|
||||
* Turn the VFP on.
|
||||
*/
|
||||
extern void vPortEnableVFP( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The number of SysTick increments that make up one tick period.
|
||||
*/
|
||||
static unsigned long ulTimerReloadValueForOneTick = 0;
|
||||
|
||||
/*
|
||||
* The maximum number of tick periods that can be suppressed is limited by the
|
||||
* 24 bit resolution of the SysTick timer.
|
||||
*/
|
||||
#if configUSE_TICKLESS_IDLE == 1
|
||||
static unsigned long xMaximumPossibleSuppressedTicks = 0;
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
|
|
@ -133,17 +166,17 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
|
|||
{
|
||||
/* Simulate the stack frame as it would be created by a context switch
|
||||
interrupt. */
|
||||
|
||||
|
||||
/* Offset added to account for the way the MCU uses the stack on entry/exit
|
||||
of interrupts, and to ensure alignment. */
|
||||
pxTopOfStack--;
|
||||
|
||||
|
||||
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
|
||||
pxTopOfStack--;
|
||||
*pxTopOfStack = 0; /* LR */
|
||||
|
||||
|
||||
/* Save code space by skipping register initialisation. */
|
||||
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
||||
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
|
||||
|
|
@ -154,7 +187,7 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
|
|||
*pxTopOfStack = portINITIAL_EXEC_RETURN;
|
||||
|
||||
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
|
||||
|
||||
|
||||
return pxTopOfStack;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -165,22 +198,22 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
|
|||
portBASE_TYPE xPortStartScheduler( void )
|
||||
{
|
||||
/* Make PendSV and SysTick the lowest priority interrupts. */
|
||||
*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
|
||||
*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
||||
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
||||
|
||||
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
||||
here already. */
|
||||
prvSetupTimerInterrupt();
|
||||
|
||||
|
||||
/* Initialise the critical nesting count ready for the first task. */
|
||||
uxCriticalNesting = 0;
|
||||
|
||||
/* Ensure the VFP is enabled - it should be anyway. */
|
||||
vPortEnableVFP();
|
||||
|
||||
|
||||
/* Lazy save always. */
|
||||
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
||||
|
||||
|
||||
/* Start the first task. */
|
||||
vPortStartFirstTask();
|
||||
|
||||
|
|
@ -199,7 +232,7 @@ void vPortEndScheduler( void )
|
|||
void vPortYieldFromISR( void )
|
||||
{
|
||||
/* Set a PendSV to request a context switch. */
|
||||
*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -222,30 +255,142 @@ void vPortExitCritical( void )
|
|||
|
||||
void xPortSysTickHandler( void )
|
||||
{
|
||||
unsigned long ulDummy;
|
||||
|
||||
/* If using preemption, also force a context switch. */
|
||||
#if configUSE_PREEMPTION == 1
|
||||
*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
||||
#endif
|
||||
|
||||
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
#if configUSE_TICKLESS_IDLE == 1
|
||||
portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;
|
||||
#endif
|
||||
|
||||
( void ) portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
{
|
||||
vTaskIncrementTick();
|
||||
}
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if configUSE_TICKLESS_IDLE == 1
|
||||
|
||||
__weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
|
||||
{
|
||||
unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;
|
||||
|
||||
/* Make sure the SysTick reload value does not overflow the counter. */
|
||||
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
|
||||
{
|
||||
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
|
||||
}
|
||||
|
||||
/* Calculate the reload value required to wait xExpectedIdleTime
|
||||
tick periods. -1 is used because this code will execute part way
|
||||
through one of the tick periods, and the fraction of a tick period is
|
||||
accounted for later. */
|
||||
ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );
|
||||
if( ulReloadValue > ulStoppedTimerCompensation )
|
||||
{
|
||||
ulReloadValue -= ulStoppedTimerCompensation;
|
||||
}
|
||||
|
||||
/* Stop the SysTick momentarily. The time the SysTick is stopped for
|
||||
is accounted for as best it can be, but using the tickless mode will
|
||||
inevitably result in some tiny drift of the time maintained by the
|
||||
kernel with respect to calendar time. */
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
|
||||
|
||||
/* If a context switch is pending then abandon the low power entry as
|
||||
the context switch might have been pended by an external interrupt that
|
||||
requires processing. */
|
||||
if( ( portNVIC_INT_CTRL_REG & portNVIC_PENDSVSET_BIT ) != 0 )
|
||||
{
|
||||
/* Restart SysTick. */
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Adjust the reload value to take into account that the current
|
||||
time slice is already partially complete. */
|
||||
ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );
|
||||
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
|
||||
|
||||
/* Clear the SysTick count flag and set the count value back to
|
||||
zero. */
|
||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||||
|
||||
/* Restart SysTick. */
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
|
||||
|
||||
/* Sleep until something happens. */
|
||||
portPRE_SLEEP_PROCESSING();
|
||||
__WFI();
|
||||
portPOST_SLEEP_PROCESSING();
|
||||
|
||||
/* Stop SysTick. Again, the time the SysTick is stopped for is
|
||||
accounted for as best it can be, but using the tickless mode will
|
||||
inevitably result in some tiny drift of the time maintained by the
|
||||
kernel with respect to calendar time. */
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
|
||||
|
||||
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
|
||||
{
|
||||
/* The tick interrupt has already executed, and the SysTick
|
||||
count reloaded with the portNVIC_SYSTICK_LOAD_REG value.
|
||||
Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of
|
||||
this tick period. */
|
||||
portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
|
||||
|
||||
/* The tick interrupt handler will already have pended the tick
|
||||
processing in the kernel. As the pending tick will be
|
||||
processed as soon as this function exits, the tick value
|
||||
maintained by the tick is stepped forward by one less than the
|
||||
time spent waiting. */
|
||||
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Something other than the tick interrupt ended the sleep.
|
||||
Work out how long the sleep lasted. */
|
||||
ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
||||
|
||||
/* How many complete tick periods passed while the processor
|
||||
was waiting? */
|
||||
ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;
|
||||
|
||||
/* The reload value is set to whatever fraction of a single tick
|
||||
period remains. */
|
||||
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;
|
||||
}
|
||||
|
||||
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
|
||||
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
|
||||
value. */
|
||||
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
|
||||
|
||||
vTaskStepTick( ulCompleteTickPeriods );
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* #if configUSE_TICKLESS_IDLE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Setup the systick timer to generate the tick interrupts at the required
|
||||
* frequency.
|
||||
*/
|
||||
void prvSetupTimerInterrupt( void )
|
||||
{
|
||||
/* Configure the constants required to setup the tick interrupt. */
|
||||
ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
||||
#if configUSE_TICKLESS_IDLE == 1
|
||||
xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
|
||||
#endif /* configUSE_TICKLESS_IDLE */
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate. */
|
||||
*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
||||
*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
|
||||
portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;
|
||||
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@
|
|||
EXTERN vTaskSwitchContext
|
||||
|
||||
PUBLIC xPortPendSVHandler
|
||||
PUBLIC vPortSetInterruptMask
|
||||
PUBLIC ulPortSetInterruptMask
|
||||
PUBLIC vPortClearInterruptMask
|
||||
PUBLIC vPortSVCHandler
|
||||
PUBLIC vPortStartFirstTask
|
||||
|
|
@ -127,20 +127,16 @@ xPortPendSVHandler:
|
|||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vPortSetInterruptMask:
|
||||
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
|
||||
msr BASEPRI, r0
|
||||
|
||||
ulPortSetInterruptMask:
|
||||
mrs r0, basepri
|
||||
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
|
||||
msr basepri, r1
|
||||
bx r14
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vPortClearInterruptMask:
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
mov r0, #0
|
||||
msr BASEPRI, r0
|
||||
|
||||
msr basepri, r0
|
||||
bx r14
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -159,7 +155,7 @@ vPortSVCHandler:
|
|||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
vPortStartFirstTask:
|
||||
vPortStartFirstTask
|
||||
/* Use the NVIC offset register to locate the stack. */
|
||||
ldr r0, =0xE000ED08
|
||||
ldr r0, [r0]
|
||||
|
|
|
|||
|
|
@ -106,15 +106,13 @@ extern "C" {
|
|||
#define portBYTE_ALIGNMENT 8
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Scheduler utilities. */
|
||||
extern void vPortYieldFromISR( void );
|
||||
|
||||
#define portYIELD() vPortYieldFromISR()
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specific optimisations. */
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
|
|
@ -131,36 +129,42 @@ extern void vPortYieldFromISR( void );
|
|||
#include <intrinsics.h>
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
extern void vPortSetInterruptMask( void );
|
||||
extern void vPortClearInterruptMask( void );
|
||||
extern unsigned long ulPortSetInterruptMask( void );
|
||||
extern void vPortClearInterruptMask( unsigned long ulNewMask );
|
||||
|
||||
#define portDISABLE_INTERRUPTS() vPortSetInterruptMask()
|
||||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask()
|
||||
#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
|
||||
#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
/* FAQ: Setting BASEPRI to 0 is not a bug. Please see
|
||||
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* There are an uneven number of items on the initial stack, so
|
||||
portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */
|
||||
#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Tickless/low power functionality. */
|
||||
extern void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime );
|
||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||
not necessary for to use this port. They are defined so the common demo files
|
||||
(which build with all the ports) will build. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* portNOP() is not required by this port. */
|
||||
#define portNOP()
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue