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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Add simple USB CDC task.
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15 changed files with 2756 additions and 49 deletions
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@ -62,6 +62,11 @@
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*
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* "uIP" task - This is the task that handles the uIP stack. All TCP/IP
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* processing is performed in this task.
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*
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* "USB" task - Enumerates the USB device as a CDC class, then echoes back all
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* received characters with a configurable offset (for example, if the offset
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* is 1 and 'A' is received then 'B' will be sent back). A dumb terminal such
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* as Hyperterminal can be used to talk to the USB task.
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*/
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/* Scheduler includes. */
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@ -116,6 +121,11 @@ static void prvSetupHardware( void );
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*/
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extern void vuIP_Task( void *pvParameters );
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/*
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* The task that handles the USB stack.
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*/
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extern void vUSBTask( void *pvParameters );
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/*
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* Simply returns the current status message for display on served WEB pages.
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*/
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@ -145,6 +155,9 @@ int main( void )
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vStartRecursiveMutexTasks();
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vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
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/* Create the USB task. */
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xTaskCreate( vUSBTask, ( signed char * ) "USB", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );
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/* Create the uIP task. The WEB server runs in this task. */
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xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, ( void * ) NULL, mainUIP_TASK_PRIORITY, NULL );
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@ -228,49 +241,6 @@ void prvSetupHardware( void )
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/* Disable TPIU. */
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PINCON->PINSEL10 = 0;
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/* Disconnect the main PLL. */
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SC->PLL0CON &= ~PLLCON_PLLC;
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SC->PLL0FEED = PLLFEED_FEED1;
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SC->PLL0FEED = PLLFEED_FEED2;
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while ((SC->PLL0STAT & PLLSTAT_PLLC) != 0);
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/* Turn off the main PLL. */
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SC->PLL0CON &= ~PLLCON_PLLE;
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SC->PLL0FEED = PLLFEED_FEED1;
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SC->PLL0FEED = PLLFEED_FEED2;
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while ((SC->PLL0STAT & PLLSTAT_PLLE) != 0);
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/* No CPU clock divider. */
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SC->CCLKCFG = 0;
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/* OSCEN. */
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SC->SCS = 0x20;
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while ((SC->SCS & 0x40) == 0);
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/* Use main oscillator. */
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SC->CLKSRCSEL = 1;
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SC->PLL0CFG = (PLLCFG_MUL16 | PLLCFG_DIV1);
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SC->PLL0FEED = PLLFEED_FEED1;
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SC->PLL0FEED = PLLFEED_FEED2;
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/* Activate the PLL by turning it on then feeding the correct
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sequence of bytes. */
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SC->PLL0CON = PLLCON_PLLE;
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SC->PLL0FEED = PLLFEED_FEED1;
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SC->PLL0FEED = PLLFEED_FEED2;
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/* 6x CPU clock divider (64 MHz) */
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SC->CCLKCFG = 5;
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/* Wait for the PLL to lock. */
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while ((SC->PLL0STAT & PLLSTAT_PLOCK) == 0);
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/* Connect the PLL. */
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SC->PLL0CON = PLLCON_PLLC | PLLCON_PLLE;
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SC->PLL0FEED = PLLFEED_FEED1;
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SC->PLL0FEED = PLLFEED_FEED2;
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/* Setup the peripheral bus to be the same as the PLL output (64 MHz). */
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SC->PCLKSEL0 = 0x05555555;
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