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port: riscv: Apply @aggarg's sugestions
This commit is contained in:
Jonathan Cubides
parent
1198daba4d
commit
dec30a8193
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@ -3,8 +3,7 @@ if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" )
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"Pulpino_Vega_RV32M1RM"
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"RISCV_MTIME_CLINT_no_extensions"
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"RISCV_no_extensions"
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"RV32I_CLINT_no_extensions"
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"RV32IF_CLINT")
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"RV32I_CLINT_no_extensions" )
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if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) )
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message(FATAL_ERROR
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@ -80,22 +80,22 @@ csrr t2, lpcount0
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csrr t3, lpstart1
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csrr t4, lpend1
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csrr t5, lpcount1
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sw t0, 1 * portWORD_SIZE( sp )
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sw t1, 2 * portWORD_SIZE( sp )
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sw t2, 3 * portWORD_SIZE( sp )
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sw t3, 4 * portWORD_SIZE( sp )
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sw t4, 5 * portWORD_SIZE( sp )
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sw t5, 6 * portWORD_SIZE( sp )
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sw t0, 2 * portWORD_SIZE( sp )
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sw t1, 3 * portWORD_SIZE( sp )
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sw t2, 4 * portWORD_SIZE( sp )
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sw t3, 5 * portWORD_SIZE( sp )
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sw t4, 6 * portWORD_SIZE( sp )
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sw t5, 7 * portWORD_SIZE( sp )
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.endm
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/* Restore the additional registers found on the Pulpino. */
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
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lw t1, 2 * portWORD_SIZE( sp )
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lw t2, 3 * portWORD_SIZE( sp )
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lw t3, 4 * portWORD_SIZE( sp )
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lw t4, 5 * portWORD_SIZE( sp )
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lw t5, 6 * portWORD_SIZE( sp )
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lw t0, 2 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
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lw t1, 3 * portWORD_SIZE( sp )
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lw t2, 4 * portWORD_SIZE( sp )
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lw t3, 5 * portWORD_SIZE( sp )
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lw t4, 6 * portWORD_SIZE( sp )
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lw t5, 7 * portWORD_SIZE( sp )
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csrw lpstart0, t0
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csrw lpend0, t1
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csrw lpcount0, t2
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@ -1,70 +0,0 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_SIFIVE_CLINT 1
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#define portasmHAS_MTIME 1
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#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
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#define portasmSTORE_FPU_CONTEXT 1
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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/* No additional registers to save, so this macro does nothing. */
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* No additional registers to restore, so this macro does nothing. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -162,8 +162,6 @@ definitions. */
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* where the global and thread pointers are currently assumed to be constant so
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* are not saved:
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*
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* [FPU registers (when enabled/available) go here]
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* mstatus
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* xCriticalNesting
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* x31
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* x30
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@ -193,19 +191,12 @@ definitions. */
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* x6
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* x5
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* portTASK_RETURN_ADDRESS
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* [FPU registers (when enabled/available) go here]
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* [chip specific registers go here]
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* mstatus
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* pxCode
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*/
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pxPortInitialiseStack:
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addi a0, a0, -portFPUCONTEXT_SIZE
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csrr t0, mstatus /* Obtain current mstatus value. */
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andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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slli t1, t1, 4
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or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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addi a0, a0, -portWORD_SIZE
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store_x t0, 0(a0) /* mstatus onto the stack. */
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addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
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store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
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@ -214,10 +205,12 @@ pxPortInitialiseStack:
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#else
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addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
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#endif
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store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
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addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
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store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register x10/a0 on the stack. */
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addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress (register x1). */
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load_x t0, xTaskReturnAddress
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store_x t0, 0(a0) /* Return address onto the stack. */
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addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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beq t0, x0, 1f /* No more chip specific registers to save. */
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@ -226,6 +219,23 @@ chip_specific_stack_frame: /* First add any chip specific registers
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addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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j chip_specific_stack_frame /* Until no more chip specific registers. */
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1:
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csrr t0, mstatus /* Obtain current mstatus value. */
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andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE=1 and MPP=M_Mode in mstatus. */
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slli t1, t1, 4
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or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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#if( configENABLE_FPU == 1 )
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/* Mark the FPU as clean in the mstatus value. */
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li t1, ~MSTATUS_FS_MASK
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and t0, t0, t1
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li t1, MSTATUS_FS_CLEAN
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or t0, t0, t1
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#endif
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addi a0, a0, -portWORD_SIZE
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store_x t0, 0(a0) /* mstatus onto the stack. */
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addi a0, a0, -portWORD_SIZE
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store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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ret
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@ -237,46 +247,46 @@ xPortStartFirstTask:
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load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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load_x x5, 1 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
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addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrw mstatus, x5 /* Interrupts enabled from here! */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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load_x x7, 5 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 6 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 7 * portWORD_SIZE( sp ) /* s1 */
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load_x x10, 8 * portWORD_SIZE( sp ) /* a0 */
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load_x x11, 9 * portWORD_SIZE( sp ) /* a1 */
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load_x x12, 10 * portWORD_SIZE( sp ) /* a2 */
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load_x x13, 11 * portWORD_SIZE( sp ) /* a3 */
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load_x x14, 12 * portWORD_SIZE( sp ) /* a4 */
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load_x x15, 13 * portWORD_SIZE( sp ) /* a5 */
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#ifndef __riscv_32e
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load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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load_x x16, 14 * portWORD_SIZE( sp ) /* a6 */
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load_x x17, 15 * portWORD_SIZE( sp ) /* a7 */
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load_x x18, 16 * portWORD_SIZE( sp ) /* s2 */
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load_x x19, 17 * portWORD_SIZE( sp ) /* s3 */
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load_x x20, 18 * portWORD_SIZE( sp ) /* s4 */
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load_x x21, 19 * portWORD_SIZE( sp ) /* s5 */
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load_x x22, 20 * portWORD_SIZE( sp ) /* s6 */
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load_x x23, 21 * portWORD_SIZE( sp ) /* s7 */
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load_x x24, 22 * portWORD_SIZE( sp ) /* s8 */
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load_x x25, 23 * portWORD_SIZE( sp ) /* s9 */
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load_x x26, 24 * portWORD_SIZE( sp ) /* s10 */
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load_x x27, 25 * portWORD_SIZE( sp ) /* s11 */
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load_x x28, 26 * portWORD_SIZE( sp ) /* t3 */
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load_x x29, 27 * portWORD_SIZE( sp ) /* t4 */
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load_x x30, 28 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 29 * portWORD_SIZE( sp ) /* t6 */
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#endif
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load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
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store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
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load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
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addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
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load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
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load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
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load_x x5, 3 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
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load_x x6, 4 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
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addi sp, sp, portCONTEXT_SIZE
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ret
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@ -29,6 +29,10 @@
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#ifndef PORTCONTEXT_H
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#define PORTCONTEXT_H
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#ifndef configENABLE_FPU
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#define configENABLE_FPU 0
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#endif
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#if __riscv_xlen == 64
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#define portWORD_SIZE 8
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#define store_x sd
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@ -49,191 +53,200 @@
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* specific version of freertos_risc_v_chip_specific_extensions.h. See the
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* notes at the top of portASM.S file. */
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#ifdef __riscv_32e
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#define portIREG_COUNT 15
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#define portCRITICAL_NESTING_OFFSET 13
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#define portMSTATUS_OFFSET 14
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#define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 14
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#else
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#define portIREG_COUNT 31
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#define portCRITICAL_NESTING_OFFSET 29
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#define portMSTATUS_OFFSET 30
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#endif
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#define portICONTEXT_SIZE ( portIREG_COUNT * portWORD_SIZE )
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/* Provide a value for the reserved size for the FPU registers. portFPUCONTEXT_SIZE is always defined,
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* but it may be 0 if the FPU is not used */
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#ifdef portasmSTORE_FPU_CONTEXT
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#define MSTATUS_FS_MASK 0x6000 /* Floating-point Unit Status in mstatus register */
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#define MSTATUS_FS_INITIAL 0x2000
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#define MSTATUS_FS_CLEAN 0x4000
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#define MSTATUS_FS_DIRTY 0x6000
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#define MSTATUS_FS_USED_OFFSET 14
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#ifdef __riscv_fdiv
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#define portFPUREG_SIZE (__riscv_flen / 8)
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#if __riscv_flen == 32
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#define load_f flw
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#define store_f fsw
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#elif __riscv_flen == 64
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#define load_f fld
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#define store_f fsd
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#else
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#error Assembler did not define __riscv_flen
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#endif
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#define portFPUREG_COUNT 33 /* 32 Floating point registers plus one CSR */
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#define portFPUREG_OFFSET(_fpureg_) (_fpureg_ * portFPUREG_SIZE + portICONTEXT_SIZE)
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#define portFPUCONTEXT_SIZE (portFPUREG_SIZE * portFPUREG_COUNT)
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#else
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#define portFPUCONTEXT_SIZE 0
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#endif
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#else
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#define portFPUCONTEXT_SIZE 0
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 30
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#endif
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#define portCONTEXT_SIZE ( portICONTEXT_SIZE + portFPUCONTEXT_SIZE )
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#if ( configENABLE_FPU == 1 )
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/* Bit [14:13] in the mstatus encode the status of FPU state which is one of
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* the following values:
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* 1. Value: 0, Meaning: Off.
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* 2. Value: 1, Meaning: Initial.
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* 3. Value: 2, Meaning: Clean.
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* 4. Value: 3, Meaning: Dirty.
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*/
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#define MSTATUS_FS_MASK 0x6000
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#define MSTATUS_FS_INITIAL 0x2000
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#define MSTATUS_FS_CLEAN 0x4000
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#define MSTATUS_FS_DIRTY 0x6000
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#define MSTATUS_FS_OFFSET 13
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#ifdef __riscv_fdiv
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#if __riscv_flen == 32
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#define load_f flw
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#define store_f fsw
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#elif __riscv_flen == 64
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#define load_f fld
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#define store_f fsd
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#else
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#error Assembler did not define __riscv_flen
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#endif
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#define portFPU_REG_SIZE ( __riscv_flen / 8 )
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#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */
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#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
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#else
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#error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
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#endif
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#endif
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/*-----------------------------------------------------------*/
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.extern pxCurrentTCB
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.extern xISRStackTop
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.extern xCriticalNesting
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.extern pxCriticalNesting
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.extern xISRStackTop
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.extern xCriticalNesting
|
||||
.extern pxCriticalNesting
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
.macro portcontextSAVE_FPU_CONTEXT_INTERNAL
|
||||
/* Check if the FPU has been used, if it has not, skip the context save */
|
||||
srl t1, t0, MSTATUS_FS_USED_OFFSET
|
||||
andi t1, t1, 1
|
||||
beqz t1, 1f /* The FPU has not been used (FS either initial or clean), skip context save */
|
||||
/* Store the fp registers */
|
||||
store_f f0, portFPUREG_OFFSET(0)( sp )
|
||||
store_f f1, portFPUREG_OFFSET(1)( sp )
|
||||
store_f f2, portFPUREG_OFFSET(2)( sp )
|
||||
store_f f3, portFPUREG_OFFSET(3)( sp )
|
||||
store_f f4, portFPUREG_OFFSET(4)( sp )
|
||||
store_f f5, portFPUREG_OFFSET(5)( sp )
|
||||
store_f f6, portFPUREG_OFFSET(6)( sp )
|
||||
store_f f7, portFPUREG_OFFSET(7)( sp )
|
||||
store_f f8, portFPUREG_OFFSET(8)( sp )
|
||||
store_f f9, portFPUREG_OFFSET(9)( sp )
|
||||
store_f f10, portFPUREG_OFFSET(10)( sp )
|
||||
store_f f11, portFPUREG_OFFSET(11)( sp )
|
||||
store_f f12, portFPUREG_OFFSET(12)( sp )
|
||||
store_f f13, portFPUREG_OFFSET(13)( sp )
|
||||
store_f f14, portFPUREG_OFFSET(14)( sp )
|
||||
store_f f15, portFPUREG_OFFSET(15)( sp )
|
||||
store_f f16, portFPUREG_OFFSET(16)( sp )
|
||||
store_f f17, portFPUREG_OFFSET(17)( sp )
|
||||
store_f f18, portFPUREG_OFFSET(18)( sp )
|
||||
store_f f19, portFPUREG_OFFSET(19)( sp )
|
||||
store_f f20, portFPUREG_OFFSET(20)( sp )
|
||||
store_f f21, portFPUREG_OFFSET(21)( sp )
|
||||
store_f f22, portFPUREG_OFFSET(22)( sp )
|
||||
store_f f23, portFPUREG_OFFSET(23)( sp )
|
||||
store_f f24, portFPUREG_OFFSET(24)( sp )
|
||||
store_f f25, portFPUREG_OFFSET(25)( sp )
|
||||
store_f f26, portFPUREG_OFFSET(26)( sp )
|
||||
store_f f27, portFPUREG_OFFSET(27)( sp )
|
||||
store_f f28, portFPUREG_OFFSET(28)( sp )
|
||||
store_f f29, portFPUREG_OFFSET(29)( sp )
|
||||
store_f f30, portFPUREG_OFFSET(30)( sp )
|
||||
store_f f31, portFPUREG_OFFSET(31)( sp )
|
||||
.macro portcontexSAVE_FPU_CONTEXT
|
||||
addi sp, sp, -( portFPU_CONTEXT_SIZE )
|
||||
/* Store the FPU registers. */
|
||||
store_f f0, 2 * portWORD_SIZE( sp )
|
||||
store_f f1, 3 * portWORD_SIZE( sp )
|
||||
store_f f2, 4 * portWORD_SIZE( sp )
|
||||
store_f f3, 5 * portWORD_SIZE( sp )
|
||||
store_f f4, 6 * portWORD_SIZE( sp )
|
||||
store_f f5, 7 * portWORD_SIZE( sp )
|
||||
store_f f6, 8 * portWORD_SIZE( sp )
|
||||
store_f f7, 9 * portWORD_SIZE( sp )
|
||||
store_f f8, 10 * portWORD_SIZE( sp )
|
||||
store_f f9, 11 * portWORD_SIZE( sp )
|
||||
store_f f10, 12 * portWORD_SIZE( sp )
|
||||
store_f f11, 13 * portWORD_SIZE( sp )
|
||||
store_f f12, 14 * portWORD_SIZE( sp )
|
||||
store_f f13, 15 * portWORD_SIZE( sp )
|
||||
store_f f14, 16 * portWORD_SIZE( sp )
|
||||
store_f f15, 17 * portWORD_SIZE( sp )
|
||||
store_f f16, 18 * portWORD_SIZE( sp )
|
||||
store_f f17, 19 * portWORD_SIZE( sp )
|
||||
store_f f18, 20 * portWORD_SIZE( sp )
|
||||
store_f f19, 21 * portWORD_SIZE( sp )
|
||||
store_f f20, 22 * portWORD_SIZE( sp )
|
||||
store_f f21, 23 * portWORD_SIZE( sp )
|
||||
store_f f22, 24 * portWORD_SIZE( sp )
|
||||
store_f f23, 25 * portWORD_SIZE( sp )
|
||||
store_f f24, 26 * portWORD_SIZE( sp )
|
||||
store_f f25, 27 * portWORD_SIZE( sp )
|
||||
store_f f26, 28 * portWORD_SIZE( sp )
|
||||
store_f f27, 29 * portWORD_SIZE( sp )
|
||||
store_f f28, 30 * portWORD_SIZE( sp )
|
||||
store_f f29, 31 * portWORD_SIZE( sp )
|
||||
store_f f30, 32 * portWORD_SIZE( sp )
|
||||
store_f f31, 33 * portWORD_SIZE( sp )
|
||||
csrr t0, fcsr
|
||||
store_x t0, portFPUREG_OFFSET(32)( sp )
|
||||
/* Mark the FPU as clean */
|
||||
li t1, ~MSTATUS_FS_MASK
|
||||
and t0, t0, t1
|
||||
li t1, MSTATUS_FS_CLEAN
|
||||
or t0, t0, t1
|
||||
csrw mstatus, t0
|
||||
1:
|
||||
store_x t0, 34 * portWORD_SIZE( sp )
|
||||
.endm
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
.macro portcontextRESTORE_FPU_CONTEXT_INTERNAL
|
||||
/* Restore fp registers from context */
|
||||
load_f f0, portFPUREG_OFFSET(0)( sp )
|
||||
load_f f1, portFPUREG_OFFSET(0)( sp )
|
||||
load_f f1, portFPUREG_OFFSET(1)( sp )
|
||||
load_f f2, portFPUREG_OFFSET(2)( sp )
|
||||
load_f f3, portFPUREG_OFFSET(3)( sp )
|
||||
load_f f4, portFPUREG_OFFSET(4)( sp )
|
||||
load_f f5, portFPUREG_OFFSET(5)( sp )
|
||||
load_f f6, portFPUREG_OFFSET(6)( sp )
|
||||
load_f f7, portFPUREG_OFFSET(7)( sp )
|
||||
load_f f8, portFPUREG_OFFSET(8)( sp )
|
||||
load_f f9, portFPUREG_OFFSET(9)( sp )
|
||||
load_f f10, portFPUREG_OFFSET(10)( sp )
|
||||
load_f f11, portFPUREG_OFFSET(11)( sp )
|
||||
load_f f12, portFPUREG_OFFSET(12)( sp )
|
||||
load_f f13, portFPUREG_OFFSET(13)( sp )
|
||||
load_f f14, portFPUREG_OFFSET(14)( sp )
|
||||
load_f f15, portFPUREG_OFFSET(15)( sp )
|
||||
load_f f16, portFPUREG_OFFSET(16)( sp )
|
||||
load_f f17, portFPUREG_OFFSET(17)( sp )
|
||||
load_f f18, portFPUREG_OFFSET(18)( sp )
|
||||
load_f f19, portFPUREG_OFFSET(19)( sp )
|
||||
load_f f20, portFPUREG_OFFSET(20)( sp )
|
||||
load_f f21, portFPUREG_OFFSET(21)( sp )
|
||||
load_f f22, portFPUREG_OFFSET(22)( sp )
|
||||
load_f f23, portFPUREG_OFFSET(23)( sp )
|
||||
load_f f24, portFPUREG_OFFSET(24)( sp )
|
||||
load_f f25, portFPUREG_OFFSET(25)( sp )
|
||||
load_f f26, portFPUREG_OFFSET(26)( sp )
|
||||
load_f f27, portFPUREG_OFFSET(27)( sp )
|
||||
load_f f28, portFPUREG_OFFSET(28)( sp )
|
||||
load_f f29, portFPUREG_OFFSET(29)( sp )
|
||||
load_f f30, portFPUREG_OFFSET(30)( sp )
|
||||
load_f f31, portFPUREG_OFFSET(31)( sp )
|
||||
load_x t0, portFPUREG_OFFSET(32)( sp )
|
||||
.macro portcontextRESTORE_FPU_CONTEXT
|
||||
/* Restore the FPU registers. */
|
||||
load_f f0, 2 * portWORD_SIZE( sp )
|
||||
load_f f1, 3 * portWORD_SIZE( sp )
|
||||
load_f f2, 4 * portWORD_SIZE( sp )
|
||||
load_f f3, 5 * portWORD_SIZE( sp )
|
||||
load_f f4, 6 * portWORD_SIZE( sp )
|
||||
load_f f5, 7 * portWORD_SIZE( sp )
|
||||
load_f f6, 8 * portWORD_SIZE( sp )
|
||||
load_f f7, 9 * portWORD_SIZE( sp )
|
||||
load_f f8, 10 * portWORD_SIZE( sp )
|
||||
load_f f9, 11 * portWORD_SIZE( sp )
|
||||
load_f f10, 12 * portWORD_SIZE( sp )
|
||||
load_f f11, 13 * portWORD_SIZE( sp )
|
||||
load_f f12, 14 * portWORD_SIZE( sp )
|
||||
load_f f13, 15 * portWORD_SIZE( sp )
|
||||
load_f f14, 16 * portWORD_SIZE( sp )
|
||||
load_f f15, 17 * portWORD_SIZE( sp )
|
||||
load_f f16, 18 * portWORD_SIZE( sp )
|
||||
load_f f17, 19 * portWORD_SIZE( sp )
|
||||
load_f f18, 20 * portWORD_SIZE( sp )
|
||||
load_f f19, 21 * portWORD_SIZE( sp )
|
||||
load_f f20, 22 * portWORD_SIZE( sp )
|
||||
load_f f21, 23 * portWORD_SIZE( sp )
|
||||
load_f f22, 24 * portWORD_SIZE( sp )
|
||||
load_f f23, 25 * portWORD_SIZE( sp )
|
||||
load_f f24, 26 * portWORD_SIZE( sp )
|
||||
load_f f25, 27 * portWORD_SIZE( sp )
|
||||
load_f f26, 28 * portWORD_SIZE( sp )
|
||||
load_f f27, 29 * portWORD_SIZE( sp )
|
||||
load_f f28, 30 * portWORD_SIZE( sp )
|
||||
load_f f29, 31 * portWORD_SIZE( sp )
|
||||
load_f f30, 32 * portWORD_SIZE( sp )
|
||||
load_f f31, 33 * portWORD_SIZE( sp )
|
||||
load_x t0, 34 * portWORD_SIZE( sp )
|
||||
csrw fcsr, t0
|
||||
1:
|
||||
addi sp, sp, ( portFPU_CONTEXT_SIZE )
|
||||
.endm
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
.macro portcontextSAVE_CONTEXT_INTERNAL
|
||||
addi sp, sp, -portCONTEXT_SIZE
|
||||
store_x x1, 1 * portWORD_SIZE( sp )
|
||||
store_x x5, 2 * portWORD_SIZE( sp )
|
||||
store_x x6, 3 * portWORD_SIZE( sp )
|
||||
store_x x7, 4 * portWORD_SIZE( sp )
|
||||
store_x x8, 5 * portWORD_SIZE( sp )
|
||||
store_x x9, 6 * portWORD_SIZE( sp )
|
||||
store_x x10, 7 * portWORD_SIZE( sp )
|
||||
store_x x11, 8 * portWORD_SIZE( sp )
|
||||
store_x x12, 9 * portWORD_SIZE( sp )
|
||||
store_x x13, 10 * portWORD_SIZE( sp )
|
||||
store_x x14, 11 * portWORD_SIZE( sp )
|
||||
store_x x15, 12 * portWORD_SIZE( sp )
|
||||
store_x x1, 2 * portWORD_SIZE( sp )
|
||||
store_x x5, 3 * portWORD_SIZE( sp )
|
||||
store_x x6, 4 * portWORD_SIZE( sp )
|
||||
store_x x7, 5 * portWORD_SIZE( sp )
|
||||
store_x x8, 6 * portWORD_SIZE( sp )
|
||||
store_x x9, 7 * portWORD_SIZE( sp )
|
||||
store_x x10, 8 * portWORD_SIZE( sp )
|
||||
store_x x11, 9 * portWORD_SIZE( sp )
|
||||
store_x x12, 10 * portWORD_SIZE( sp )
|
||||
store_x x13, 11 * portWORD_SIZE( sp )
|
||||
store_x x14, 12 * portWORD_SIZE( sp )
|
||||
store_x x15, 13 * portWORD_SIZE( sp )
|
||||
#ifndef __riscv_32e
|
||||
store_x x16, 13 * portWORD_SIZE( sp )
|
||||
store_x x17, 14 * portWORD_SIZE( sp )
|
||||
store_x x18, 15 * portWORD_SIZE( sp )
|
||||
store_x x19, 16 * portWORD_SIZE( sp )
|
||||
store_x x20, 17 * portWORD_SIZE( sp )
|
||||
store_x x21, 18 * portWORD_SIZE( sp )
|
||||
store_x x22, 19 * portWORD_SIZE( sp )
|
||||
store_x x23, 20 * portWORD_SIZE( sp )
|
||||
store_x x24, 21 * portWORD_SIZE( sp )
|
||||
store_x x25, 22 * portWORD_SIZE( sp )
|
||||
store_x x26, 23 * portWORD_SIZE( sp )
|
||||
store_x x27, 24 * portWORD_SIZE( sp )
|
||||
store_x x28, 25 * portWORD_SIZE( sp )
|
||||
store_x x29, 26 * portWORD_SIZE( sp )
|
||||
store_x x30, 27 * portWORD_SIZE( sp )
|
||||
store_x x31, 28 * portWORD_SIZE( sp )
|
||||
store_x x16, 14 * portWORD_SIZE( sp )
|
||||
store_x x17, 15 * portWORD_SIZE( sp )
|
||||
store_x x18, 16 * portWORD_SIZE( sp )
|
||||
store_x x19, 17 * portWORD_SIZE( sp )
|
||||
store_x x20, 18 * portWORD_SIZE( sp )
|
||||
store_x x21, 19 * portWORD_SIZE( sp )
|
||||
store_x x22, 20 * portWORD_SIZE( sp )
|
||||
store_x x23, 21 * portWORD_SIZE( sp )
|
||||
store_x x24, 22 * portWORD_SIZE( sp )
|
||||
store_x x25, 23 * portWORD_SIZE( sp )
|
||||
store_x x26, 24 * portWORD_SIZE( sp )
|
||||
store_x x27, 25 * portWORD_SIZE( sp )
|
||||
store_x x28, 26 * portWORD_SIZE( sp )
|
||||
store_x x29, 27 * portWORD_SIZE( sp )
|
||||
store_x x30, 28 * portWORD_SIZE( sp )
|
||||
store_x x31, 29 * portWORD_SIZE( sp )
|
||||
#endif /* ifndef __riscv_32e */
|
||||
|
||||
load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
|
||||
store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
|
||||
|
||||
#if( configENABLE_FPU == 1 )
|
||||
csrr t0, mstatus
|
||||
srl t1, t0, MSTATUS_FS_OFFSET
|
||||
andi t1, t1, 3
|
||||
addi t2, x0, 3
|
||||
bne t1, t2, 1f /* If FPU status is not dirty, do not save FPU registers. */
|
||||
|
||||
csrr t0, mstatus /* Required for MPIE bit. */
|
||||
store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
|
||||
#ifdef portasmSTORE_FPU_CONTEXT
|
||||
portcontextSAVE_FPU_CONTEXT_INTERNAL
|
||||
#endif /* ifdef portasmSTORE_FPU_CONTEXT */
|
||||
|
||||
portcontexSAVE_FPU_CONTEXT
|
||||
1:
|
||||
#endif
|
||||
|
||||
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
|
||||
|
||||
csrr t0, mstatus
|
||||
store_x t0, 1 * portWORD_SIZE( sp )
|
||||
|
||||
#if( configENABLE_FPU == 1 )
|
||||
/* Mark the FPU as clean, if it was dirty and we saved FPU registers. */
|
||||
srl t1, t0, MSTATUS_FS_OFFSET
|
||||
andi t1, t1, 3
|
||||
addi t2, x0, 3
|
||||
bne t1, t2, 2f
|
||||
|
||||
li t1, ~MSTATUS_FS_MASK
|
||||
and t0, t0, t1
|
||||
li t1, MSTATUS_FS_CLEAN
|
||||
or t0, t0, t1
|
||||
csrw mstatus, t0
|
||||
2:
|
||||
#endif
|
||||
|
||||
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||
store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */
|
||||
|
||||
|
|
@ -267,50 +280,57 @@ load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */
|
|||
load_x t0, 0 ( sp )
|
||||
csrw mepc, t0
|
||||
|
||||
/* Restore mstatus register. */
|
||||
load_x t0, 1 * portWORD_SIZE( sp )
|
||||
csrw mstatus, t0
|
||||
|
||||
/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||
portasmRESTORE_ADDITIONAL_REGISTERS
|
||||
|
||||
#ifdef portasmSTORE_FPU_CONTEXT
|
||||
portcontextRESTORE_FPU_CONTEXT_INTERNAL
|
||||
#endif /* ifdef portasmSTORE_FPU_CONTEXT */
|
||||
#if( configENABLE_FPU == 1 )
|
||||
csrr t0, mstatus
|
||||
srl t1, t0, MSTATUS_FS_OFFSET
|
||||
andi t1, t1, 3
|
||||
addi t2, x0, 3
|
||||
bne t1, t2, 3f /* If FPU status is not dirty, do not restore FPU registers. */
|
||||
|
||||
/* Load mstatus with the interrupt enable bits used by the task. */
|
||||
load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
|
||||
csrw mstatus, t0 /* Required for MPIE bit. */
|
||||
portcontextRESTORE_FPU_CONTEXT
|
||||
3:
|
||||
#endif /* ifdef portasmSTORE_FPU_CONTEXT */
|
||||
|
||||
load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
|
||||
load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
|
||||
store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */
|
||||
|
||||
load_x x1, 1 * portWORD_SIZE( sp )
|
||||
load_x x5, 2 * portWORD_SIZE( sp )
|
||||
load_x x6, 3 * portWORD_SIZE( sp )
|
||||
load_x x7, 4 * portWORD_SIZE( sp )
|
||||
load_x x8, 5 * portWORD_SIZE( sp )
|
||||
load_x x9, 6 * portWORD_SIZE( sp )
|
||||
load_x x10, 7 * portWORD_SIZE( sp )
|
||||
load_x x11, 8 * portWORD_SIZE( sp )
|
||||
load_x x12, 9 * portWORD_SIZE( sp )
|
||||
load_x x13, 10 * portWORD_SIZE( sp )
|
||||
load_x x14, 11 * portWORD_SIZE( sp )
|
||||
load_x x15, 12 * portWORD_SIZE( sp )
|
||||
load_x x1, 2 * portWORD_SIZE( sp )
|
||||
load_x x5, 3 * portWORD_SIZE( sp )
|
||||
load_x x6, 4 * portWORD_SIZE( sp )
|
||||
load_x x7, 5 * portWORD_SIZE( sp )
|
||||
load_x x8, 6 * portWORD_SIZE( sp )
|
||||
load_x x9, 7 * portWORD_SIZE( sp )
|
||||
load_x x10, 8 * portWORD_SIZE( sp )
|
||||
load_x x11, 9 * portWORD_SIZE( sp )
|
||||
load_x x12, 10 * portWORD_SIZE( sp )
|
||||
load_x x13, 11 * portWORD_SIZE( sp )
|
||||
load_x x14, 12 * portWORD_SIZE( sp )
|
||||
load_x x15, 13 * portWORD_SIZE( sp )
|
||||
#ifndef __riscv_32e
|
||||
load_x x16, 13 * portWORD_SIZE( sp )
|
||||
load_x x17, 14 * portWORD_SIZE( sp )
|
||||
load_x x18, 15 * portWORD_SIZE( sp )
|
||||
load_x x19, 16 * portWORD_SIZE( sp )
|
||||
load_x x20, 17 * portWORD_SIZE( sp )
|
||||
load_x x21, 18 * portWORD_SIZE( sp )
|
||||
load_x x22, 19 * portWORD_SIZE( sp )
|
||||
load_x x23, 20 * portWORD_SIZE( sp )
|
||||
load_x x24, 21 * portWORD_SIZE( sp )
|
||||
load_x x25, 22 * portWORD_SIZE( sp )
|
||||
load_x x26, 23 * portWORD_SIZE( sp )
|
||||
load_x x27, 24 * portWORD_SIZE( sp )
|
||||
load_x x28, 25 * portWORD_SIZE( sp )
|
||||
load_x x29, 26 * portWORD_SIZE( sp )
|
||||
load_x x30, 27 * portWORD_SIZE( sp )
|
||||
load_x x31, 28 * portWORD_SIZE( sp )
|
||||
load_x x16, 14 * portWORD_SIZE( sp )
|
||||
load_x x17, 15 * portWORD_SIZE( sp )
|
||||
load_x x18, 16 * portWORD_SIZE( sp )
|
||||
load_x x19, 17 * portWORD_SIZE( sp )
|
||||
load_x x20, 18 * portWORD_SIZE( sp )
|
||||
load_x x21, 19 * portWORD_SIZE( sp )
|
||||
load_x x22, 20 * portWORD_SIZE( sp )
|
||||
load_x x23, 21 * portWORD_SIZE( sp )
|
||||
load_x x24, 22 * portWORD_SIZE( sp )
|
||||
load_x x25, 23 * portWORD_SIZE( sp )
|
||||
load_x x26, 24 * portWORD_SIZE( sp )
|
||||
load_x x27, 25 * portWORD_SIZE( sp )
|
||||
load_x x28, 26 * portWORD_SIZE( sp )
|
||||
load_x x29, 27 * portWORD_SIZE( sp )
|
||||
load_x x30, 28 * portWORD_SIZE( sp )
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load_x x31, 29 * portWORD_SIZE( sp )
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#endif /* ifndef __riscv_32e */
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addi sp, sp, portCONTEXT_SIZE
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||||
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Reference in a new issue