From dea347fb9a3ee1758daf5763b94cad3d9641345b Mon Sep 17 00:00:00 2001 From: "NoMaY (a user of Japan.RenesasRulz.com)" Date: Wed, 23 Sep 2020 04:46:11 +0900 Subject: [PATCH] Add Renesas RX72N Envision Kit RTOS Demo using Renesas RXv3 port layer (#167) * Add Renesas RX72N Envision Kit RTOS Demo using Renesas RXv3 port layer * Refactor the workaround which makes CC-RX linker optimization working better To be robust for future updates of Renesas RX SmartConfigurator until the cause of the problem is fixed by Renesas. * Fix vApplicationMallocFailedHook()'s argument type generated by e2 studio. No changes are caused in the MOT and SREC files which are built. * Merge update of submodule (submodule's commit id) Changes are caused in the MOT and SREC files which are built for Renesas RX72N Envision Kit RTOS Demo. Theses RTOS Demo programs work after changes. * Fix: Add checking DPFPU register in RegTest inline asm functions in main_full.c * Fix and sync kernel pointer (submodule's commit id) to the same as 'upstream/master' * Revert "Fix and sync kernel pointer (submodule's commit id) to the same as 'upstream/master'" This reverts commit d684f749bc40fa34c6b87b943f3b866fbe33acd1. * Revert "Merge remote-tracking branch 'upstream/master' into rx700v3dpfpu" This reverts commit 3a44473b4ed76a5450eb45febc39a96454b6f5e0, reversing changes made to 0f4f024fe212617355224989cb37e96d4a28523b. * Merge remote-tracking branch 'upstream/master' into rx700v3dpfpu * Fix and sync kernel pointer (submodule's commit id) to the same as 'upstream/master' * Test: Fix unnecessary update of SiFive_HiFive1_RTOS_demo.url. * Fix? unnecessary update of SiFive_HiFive1_RTOS_demo.url. * Fix unnecessary update of SiFive_HiFive1_RTOS_demo.url. --- .../.cproject | 152 + .../.project | 242 + .../.settings/fittemp/r_sci_rx.ftl | 85 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100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CG_patch.h create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.c create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.h create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch2.h create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/IDE_patch.h create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/platform.h create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/resetprg.c create mode 100644 FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c create mode 100644 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+1,242 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS + 2 + virtual:/virtual + + + src/FreeRTOS/Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/FreeRTOS_Demo/Full_Demo/FreeRTOS-Plus-CLI + 2 + FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI + + + src/FreeRTOS_Demo/Full_Demo/Sample-CLI-commands.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c + + + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/FreeRTOS_Demo/Full_Demo/UARTCommandConsole.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c + + + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 0 + src/FreeRTOS/Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 0 + src/FreeRTOS/Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 0 + src/FreeRTOS/Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1442773470090 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442773470090 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442773470100 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442773470100 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442773470110 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442773470110 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442773470120 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442773470120 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442773470130 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442773470130 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442773470140 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442773470140 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442773470150 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442773470150 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442773470160 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 0 + src/FreeRTOS/Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX700v3_DPFPU + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/fittemp/r_sci_rx.ftl b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/fittemp/r_sci_rx.ftl new file mode 100644 index 000000000..a505f3edd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/fittemp/r_sci_rx.ftl @@ -0,0 +1,85 @@ +<#-- + Copyright(C) 2015 Renesas Electronics Corporation + RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + This program must be used solely for the purpose for which it was furnished + by Renesas Electronics Corporation. No part of this program may be reproduced + or disclosed to others, in any form, without the prior written permission of + Renesas Electronics Corporation. +--> +<#-- = DECLARE FUNCTION INFORMATION HERE =================== --> +<#-- + (Step 1) Explanation: These variables are necessary information for the function header. + Please fill up or leave blank, but do not delete +--> +<#assign Function_Base_Name = "R_SCI_PinSet"> +<#assign Function_Description = "This function initializes pins for r_sci_rx module"> +<#assign Function_Arg = "none"> +<#assign Function_Ret = "none"> +<#assign Version = 1.00> + +<#-- = DECLARE FUNCTION CONTENT HERE ======================= --> +<#-- + (Step 2) Explanation: Function content. + - Macro [initialsection] : + Any text that goes into this section will be printed out 1 time per function + input [postfix] :Use this variable to add the channel number to the function base name. +--> +<#macro initialsection postfix> +<#assign Function_Name = "${Function_Base_Name}${postfix}"> +<#include "lib/functionheader.ftl"> +void ${Function_Name}() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + +<#-- + (Step 3) Explanation: Function content. + - Macro [peripheralpincode] : Any text that goes into this section will be printed out 1 time per peripheral + - input [pin] : Available info includes: + pin.pinName :The name of pin, eg “SSLA0” + pin.assignedPinName :The pin assigned to, eg “P32” + pin.pinMPC :The port number of assigned pin, eg “P32” has portNume = “3” + pin.portNum :The bit number of the assigned pin, eg “P32” has pinBitNum = “2” + pin.pinBitNum :The value of MPC +--> +<#macro peripheralpincode pin> + + +<#-- + (Step 4) Explanation: Function content. + - Macro [channelpincode] : Any text that goes into this section will be printed out 1 time per channel + - input [pin] : Same as above +--> +<#macro channelpincode pin> + + /* Set ${pin.pinName} pin */ + MPC.${pin.assignedPinName}PFS.BYTE = 0x${pin.pinMPC}U; + PORT${pin.portNum}.PMR.BIT.B${pin.pinBitNum} = 1U; + + +<#macro channelpincodeextra pin postfix> + + +<#-- + (Step 5) Explanation: Function content. + - Macro [endsection] : Any text that goes into this section will be printed out 1 time last +--> +<#macro endsection> + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + + +<#-- + (Step 6) Explanation: Header file content + - Macro [headerfilesection] : Any text that goes into this section will be printed out 1 time in the header file + - input [postfix] :Use this variable to add the channel number to the function base name. +--> +<#macro headerfilesection postfix> +void ${Function_Base_Name}${postfix}(); + + +<#macro headerfilesectionExtra postfix> + + +<#-- = END OF FILE ========================================= --> \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/org.eclipse.cdt.core.prefs b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 000000000..0b8fbc2fb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,14 @@ +eclipse.preferences.version=1 +indexer/indexAllFiles=false +indexer/indexAllHeaderVersions=true +indexer/indexAllVersionsSpecificHeaders= +indexer/indexOnOpen=false +indexer/indexUnusedHeadersWithDefaultLang=false +indexer/indexerId=org.eclipse.cdt.core.fastIndexer +indexer/skipFilesLargerThanMB=8 +indexer/skipImplicitReferences=false +indexer/skipIncludedFilesLargerThanMB=16 +indexer/skipMacroReferences=false +indexer/skipReferences=false +indexer/skipTypeReferences=false +indexer/useHeuristicIncludeResolution=false diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/smartconfigurator/generate_skeleton.xml b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/smartconfigurator/generate_skeleton.xml new file mode 100644 index 000000000..ed82f286e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/.settings/smartconfigurator/generate_skeleton.xml @@ -0,0 +1,4 @@ + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..15c37cff1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/RTOSDemo HardwareDebug.launch @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/RTOSDemo_GNURX.scfg b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/RTOSDemo_GNURX.scfg new file mode 100644 index 000000000..50086fdb9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/RTOSDemo_GNURX.scfg @@ -0,0 +1,867 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..4f08d0f62 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It sends the value 100 to the queue every 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. It blocks on the queue to wait for data to arrive from the + * queue send task - toggling the LED each time it receives the value 100. The + * queue send task writes to the queue every 200ms, so the LED should toggle + * every 200ms. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "platform.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200UL ) ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..0d900caa8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c @@ -0,0 +1,130 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This file contains the non-portable and therefore RX specific parts of the + * IntQueue standard demo task - namely the configuration of the timers that + * generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Renesas includes. */ +#include "platform.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2000UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_2_3_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set priority and enable interrupt. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IEN( PERIB, INTB128 ) = 1; + + /* Ensure that the flag is set to 0, otherwise the interrupt will not be + accepted. */ + IR( PERIB, INTB128 ) = 0; + + /* Do the same for TMR2, but to vector 129. */ + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IEN( PERIB, INTB129 ) = 1; + IR( PERIB, INTB129 ) = 0; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +R_BSP_PRAGMA_STATIC_INTERRUPT( prvIntQTimer_0_1_ISR, VECT( PERIB, INTB128) ) +R_BSP_ATTRIB_STATIC_INTERRUPT void prvIntQTimer_0_1_ISR( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + setpsw_i(); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +R_BSP_PRAGMA_STATIC_INTERRUPT( prvIntQTimer_2_3_ISR, VECT( PERIB, INTB129) ) +R_BSP_ATTRIB_STATIC_INTERRUPT void prvIntQTimer_2_3_ISR( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + setpsw_i(); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..49c2351d8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c new file mode 100644 index 000000000..05eda5290 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/main_full.c @@ -0,0 +1,847 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates a set of demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "FreeRTOS+CLI command console" - The command console uses SCI1 for its + * input and output. The baud rate is set to 19200. Type "help" to see a list + * of registered commands. The FreeRTOS+CLI license is different to the + * FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage + * details. + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks are not only still executing, + * but are executing without reporting any errors. If the check task discovers + * that a task has either stalled, or reported an error, then it changes its own + * execution period from the initial three seconds, to just 200ms. The check + * task also toggles an LED on each iteration of its loop. This provides a + * visual indication of the system status: If the LED toggles every three + * seconds, then no issues have been discovered. If the LED toggles every + * 200ms, then an issue has been discovered with at least one task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include "platform.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The period of the check task, in ms, provided no errors have been reported by +any of the standard demo tasks. ms are converted to the equivalent in ticks +using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) + +/* The period of the check task, in ms, if an error has been reported in one of +the standard demo tasks. ms are converted to the equivalent in ticks using the +portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL ); + + /* Start the tasks that implements the command console on the UART, as + described above. */ + vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); + + /* Register the standard CLI commands. */ + vRegisterSampleCLICommands(); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = pdMS_TO_TICKS( 35 ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + +#if defined(__DPFPU) + + /* Tell the kernel that this task require a DPFPU context before any DPFPU + instructions are executed. */ + portTASK_USES_DPFPU(); + +#endif /* defined(__DPFPU) */ + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + +#if defined(__DPFPU) + + /* Tell the kernel that this task require a DPFPU context before any DPFPU + instructions are executed. */ + portTASK_USES_DPFPU(); + +#endif /* defined(__DPFPU) */ + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +R_BSP_PRAGMA_STATIC_INLINE_ASM( prvRegTest1Implementation ) +void prvRegTest1Implementation( void ) +{ +R_BSP_ASM_BEGIN + + /* Put a known value in each register. */ + R_BSP_ASM( MOV.L #1, R1 ) + R_BSP_ASM( MOV.L #2, R2 ) + R_BSP_ASM( MOV.L #3, R3 ) + R_BSP_ASM( MOV.L #4, R4 ) + R_BSP_ASM( MOV.L #5, R5 ) + R_BSP_ASM( MOV.L #6, R6 ) + R_BSP_ASM( MOV.L #7, R7 ) + R_BSP_ASM( MOV.L #8, R8 ) + R_BSP_ASM( MOV.L #9, R9 ) + R_BSP_ASM( MOV.L #10, R10 ) + R_BSP_ASM( MOV.L #11, R11 ) + R_BSP_ASM( MOV.L #12, R12 ) + R_BSP_ASM( MOV.L #13, R13 ) + R_BSP_ASM( MOV.L #14, R14 ) + R_BSP_ASM( MOV.L #15, R15 ) + +#if defined(__DPFPU) + /* Put a known value in each DPFPU register. (DR0 is the same value as DR15.) */ + R_BSP_ASM( ITOD R1, DR1 ) + R_BSP_ASM( ITOD R2, DR2 ) + R_BSP_ASM( ITOD R3, DR3 ) + R_BSP_ASM( ITOD R4, DR4 ) + R_BSP_ASM( ITOD R5, DR5 ) + R_BSP_ASM( ITOD R6, DR6 ) + R_BSP_ASM( ITOD R7, DR7 ) + R_BSP_ASM( ITOD R8, DR8 ) + R_BSP_ASM( ITOD R9, DR9 ) + R_BSP_ASM( ITOD R10, DR10 ) + R_BSP_ASM( ITOD R11, DR11 ) + R_BSP_ASM( ITOD R12, DR12 ) + R_BSP_ASM( ITOD R13, DR13 ) + R_BSP_ASM( ITOD R14, DR14 ) + R_BSP_ASM( ITOD R15, DR15 ) + R_BSP_ASM( ITOD R15, DR0 ) +#endif /* defined(__DPFPU) */ + + /* Loop, checking each iteration that each register still contains the + expected value. */ +R_BSP_ASM_LAB(1:) /* TestLoop1: */ + + /* Push the registers that are going to get clobbered. */ + R_BSP_ASM( PUSHM R14-R15 ) + + /* Increment the loop counter to show this task is still getting CPU time. */ + R_BSP_ASM( MOV.L #_ulRegTest1LoopCounter, R14 ) + R_BSP_ASM( MOV.L [ R14 ], R15 ) + R_BSP_ASM( ADD #1, R15 ) + R_BSP_ASM( MOV.L R15, [ R14 ] ) + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + R_BSP_ASM( MOV.L #1, R14 ) + R_BSP_ASM( MOV.L #0872E0H, R15 ) + R_BSP_ASM( MOV.B R14, [R15] ) + R_BSP_ASM( NOP ) + R_BSP_ASM( NOP ) + + /* Restore the clobbered registers. */ + R_BSP_ASM( POPM R14-R15 ) + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + R_BSP_ASM( CMP #1, R1 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #2, R2 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #3, R3 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #4, R4 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #5, R5 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #6, R6 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #7, R7 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #8, R8 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #9, R9 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #10, R10 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #11, R11 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #12, R12 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #13, R13 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #14, R14 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #15, R15 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + +#if defined(__DPFPU) + /* Now compare each DPFPU register to ensure it still contains the value that was + set before this loop was entered. (DR0 is the same value as DR15.) */ + R_BSP_ASM( DCMPEQ DR0, DR15 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R1, DR0 ) + R_BSP_ASM( DCMPEQ DR1, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R2, DR0 ) + R_BSP_ASM( DCMPEQ DR2, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R3, DR0 ) + R_BSP_ASM( DCMPEQ DR3, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R4, DR0 ) + R_BSP_ASM( DCMPEQ DR4, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R5, DR0 ) + R_BSP_ASM( DCMPEQ DR5, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R6, DR0 ) + R_BSP_ASM( DCMPEQ DR6, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R7, DR0 ) + R_BSP_ASM( DCMPEQ DR7, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R8, DR0 ) + R_BSP_ASM( DCMPEQ DR8, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R9, DR0 ) + R_BSP_ASM( DCMPEQ DR9, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R10, DR0 ) + R_BSP_ASM( DCMPEQ DR10, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R11, DR0 ) + R_BSP_ASM( DCMPEQ DR11, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R12, DR0 ) + R_BSP_ASM( DCMPEQ DR12, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R13, DR0 ) + R_BSP_ASM( DCMPEQ DR13, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R14, DR0 ) + R_BSP_ASM( DCMPEQ DR14, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R15, DR0 ) + R_BSP_ASM( DCMPEQ DR15, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ +#endif /* defined(__DPFPU) */ + + /* All comparisons passed, start a new itteratio of this loop. */ + R_BSP_ASM( BRA.W R_BSP_ASM_LAB_PREV(1) ) /* BRA TestLoop1 */ + +R_BSP_ASM_LAB(11:) /* RegTest1Error: */ + /* A compare failed, just loop here so the loop counter stops incrementing + causing the check task to indicate the error. */ + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_PREV(11) ) /* BRA RegTest1Error */ + +R_BSP_ASM_END +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +R_BSP_PRAGMA_STATIC_INLINE_ASM( prvRegTest2Implementation ) +void prvRegTest2Implementation( void ) +{ +R_BSP_ASM_BEGIN + + /* Put a known value in each register. */ + R_BSP_ASM( MOV.L #10, R1 ) + R_BSP_ASM( MOV.L #20, R2 ) + R_BSP_ASM( MOV.L #30, R3 ) + R_BSP_ASM( MOV.L #40, R4 ) + R_BSP_ASM( MOV.L #50, R5 ) + R_BSP_ASM( MOV.L #60, R6 ) + R_BSP_ASM( MOV.L #70, R7 ) + R_BSP_ASM( MOV.L #80, R8 ) + R_BSP_ASM( MOV.L #90, R9 ) + R_BSP_ASM( MOV.L #100, R10 ) + R_BSP_ASM( MOV.L #110, R11 ) + R_BSP_ASM( MOV.L #120, R12 ) + R_BSP_ASM( MOV.L #130, R13 ) + R_BSP_ASM( MOV.L #140, R14 ) + R_BSP_ASM( MOV.L #150, R15 ) + +#if defined(__DPFPU) + /* Put a known value in each DPFPU register. (DR0 is the same value as DR15.) */ + R_BSP_ASM( ITOD R1, DR1 ) + R_BSP_ASM( ITOD R2, DR2 ) + R_BSP_ASM( ITOD R3, DR3 ) + R_BSP_ASM( ITOD R4, DR4 ) + R_BSP_ASM( ITOD R5, DR5 ) + R_BSP_ASM( ITOD R6, DR6 ) + R_BSP_ASM( ITOD R7, DR7 ) + R_BSP_ASM( ITOD R8, DR8 ) + R_BSP_ASM( ITOD R9, DR9 ) + R_BSP_ASM( ITOD R10, DR10 ) + R_BSP_ASM( ITOD R11, DR11 ) + R_BSP_ASM( ITOD R12, DR12 ) + R_BSP_ASM( ITOD R13, DR13 ) + R_BSP_ASM( ITOD R14, DR14 ) + R_BSP_ASM( ITOD R15, DR15 ) + R_BSP_ASM( ITOD R15, DR0 ) +#endif /* defined(__DPFPU) */ + + /* Loop, checking on each iteration that each register still contains the + expected value. */ +R_BSP_ASM_LAB(2:) /* TestLoop2: */ + + /* Push the registers that are going to get clobbered. */ + R_BSP_ASM( PUSHM R14-R15 ) + + /* Increment the loop counter to show this task is still getting CPU time. */ + R_BSP_ASM( MOV.L #_ulRegTest2LoopCounter, R14 ) + R_BSP_ASM( MOV.L [ R14 ], R15 ) + R_BSP_ASM( ADD #1, R15 ) + R_BSP_ASM( MOV.L R15, [ R14 ] ) + + /* Restore the clobbered registers. */ + R_BSP_ASM( POPM R14-R15 ) + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + R_BSP_ASM( CMP #10, R1 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #20, R2 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #30, R3 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #40, R4 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #50, R5 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #60, R6 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #70, R7 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #80, R8 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #90, R9 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #100, R10 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #110, R11 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #120, R12 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #130, R13 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #140, R14 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #150, R15 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + +#if defined(__DPFPU) + /* Now compare each DPFPU register to ensure it still contains the value that was + set before this loop was entered. (DR0 is the same value as DR15.) */ + R_BSP_ASM( DCMPEQ DR0, DR15 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R1, DR0 ) + R_BSP_ASM( DCMPEQ DR1, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R2, DR0 ) + R_BSP_ASM( DCMPEQ DR2, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R3, DR0 ) + R_BSP_ASM( DCMPEQ DR3, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R4, DR0 ) + R_BSP_ASM( DCMPEQ DR4, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R5, DR0 ) + R_BSP_ASM( DCMPEQ DR5, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R6, DR0 ) + R_BSP_ASM( DCMPEQ DR6, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R7, DR0 ) + R_BSP_ASM( DCMPEQ DR7, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R8, DR0 ) + R_BSP_ASM( DCMPEQ DR8, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R9, DR0 ) + R_BSP_ASM( DCMPEQ DR9, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R10, DR0 ) + R_BSP_ASM( DCMPEQ DR10, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R11, DR0 ) + R_BSP_ASM( DCMPEQ DR11, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R12, DR0 ) + R_BSP_ASM( DCMPEQ DR12, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R13, DR0 ) + R_BSP_ASM( DCMPEQ DR13, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R14, DR0 ) + R_BSP_ASM( DCMPEQ DR14, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R15, DR0 ) + R_BSP_ASM( DCMPEQ DR15, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ +#endif /* defined(__DPFPU) */ + + /* All comparisons passed, start a new itteratio of this loop. */ + R_BSP_ASM( BRA.W R_BSP_ASM_LAB_PREV(2) ) /* BRA TestLoop2 */ + +R_BSP_ASM_LAB(22:) /* RegTest2Error: */ + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_PREV(22) ) /* BRA RegTest2Error */ + +R_BSP_ASM_END +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c new file mode 100644 index 000000000..330530546 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/Full_Demo/serial.c @@ -0,0 +1,208 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program includes. */ +#include "serial.h" + +/* Renesas includes. */ +#include "platform.h" +#include "r_dtc_rx_if.h" +#include "r_sci_rx_if.h" +#include "r_byteq_if.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Characters received from the UART are stored in this queue, ready to be +received by the application. ***NOTE*** Using a queue in this way is very +convenient, but also very inefficient. It can be used here because characters +will only arrive slowly. In a higher bandwidth system a circular RAM buffer or +DMA should be used in place of this queue. */ +static QueueHandle_t xRxQueue = NULL; + +/* When a task calls vSerialPutString() its handle is stored in xSendingTask, +before being placed into the Blocked state (so does not use any CPU time) to +wait for the transmission to end. The task handle is then used from the UART +transmit end interrupt to remove the task from the Blocked state. */ +static TaskHandle_t xSendingTask = NULL; + +/* Callback function which is called from Renesas API's interrupt service routine. */ +void vSerialSciCallback( void *pvArgs ) +{ +sci_cb_args_t *pxArgs = (sci_cb_args_t *)pvArgs; + + /* Renesas API has a built-in queue but we will ignore it. If the queue is not + full, a received character is passed with SCI_EVT_RX_CHAR event. If the queue + is full, a received character is passed with SCI_EVT_RXBUF_OVFL event. */ + if( SCI_EVT_RX_CHAR == pxArgs->event || SCI_EVT_RXBUF_OVFL == pxArgs->event ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + configASSERT( xRxQueue ); + + /* Characters received from the UART are stored in this queue, ready to be + received by the application. ***NOTE*** Using a queue in this way is very + convenient, but also very inefficient. It can be used here because + characters will only arrive slowly. In a higher bandwidth system a circular + RAM buffer or DMA should be used in place of this queue. */ + xQueueSendFromISR( xRxQueue, &pxArgs->byte, &xHigherPriorityTaskWoken ); + + /* See http://www.freertos.org/xQueueOverwriteFromISR.html for information + on the semantics of this ISR. */ + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + /* Renesas API notifies the completion of transmission by SCI_EVT_TEI event. */ + else if( SCI_EVT_TEI == pxArgs->event ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + if( xSendingTask != NULL ) + { + /* A task is waiting for the end of the Tx, unblock it now. + http://www.freertos.org/vTaskNotifyGiveFromISR.html */ + vTaskNotifyGiveFromISR( xSendingTask, &xHigherPriorityTaskWoken ); + xSendingTask = NULL; + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + } +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + ( void ) ulWantedBaud; + ( void ) uxQueueLength; + + /* Characters received from the UART are stored in this queue, ready to be + received by the application. ***NOTE*** Using a queue in this way is very + convenient, but also very inefficient. It can be used here because + characters will only arrive slowly. In a higher bandwidth system a circular + RAM buffer or DMA should be used in place of this queue. */ + xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) ); + configASSERT( xRxQueue ); + + /* Set interrupt priority. (Other UART settings had been initialized in the + src/smc_gen/general/r_cg_hardware_setup.c.) */ + uint8_t ucInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + R_SCI_Control( xSerialSciHandle, SCI_CMD_SET_RXI_PRIORITY, ( void * ) &ucInterruptPriority ); + R_SCI_Control( xSerialSciHandle, SCI_CMD_SET_TXI_PRIORITY, ( void * ) &ucInterruptPriority ); + + /* Only one UART is supported, so it doesn't matter what is returned + here. */ + return 0; +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength ) +{ +const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 5000 ); + + /* Only one port is supported. */ + ( void ) pxPort; + + /* Don't send the string unless the previous string has been sent. */ + if( ( xSendingTask == NULL ) && ( usStringLength > 0 ) ) + { + /* Ensure the calling task's notification state is not already + pending. */ + xTaskNotifyStateClear( NULL ); + + /* Store the handle of the transmitting task. This is used to unblock + the task when the transmission has completed. */ + xSendingTask = xTaskGetCurrentTaskHandle(); + + /* Send the string using the Renesas API with a workaround. */ + if( usStringLength > 1 ) + { + /* Set up Data Transfer Control. */ + dtc_cmd_arg_t xSerialTxDtcArg; + dtc_transfer_data_cfg_t xSerialTxDtcConfig; + + xSerialTxDtcArg.act_src = U_DTC_UART_CLI_TX_ACT; + xSerialTxDtcConfig.transfer_mode = DTC_TRANSFER_MODE_NORMAL; + xSerialTxDtcConfig.data_size = DTC_DATA_SIZE_BYTE; + xSerialTxDtcConfig.src_addr_mode = DTC_SRC_ADDR_INCR; + xSerialTxDtcConfig.dest_addr_mode = DTC_DES_ADDR_FIXED; + xSerialTxDtcConfig.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + xSerialTxDtcConfig.repeat_block_side = DTC_REPEAT_BLOCK_SOURCE; + xSerialTxDtcConfig.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + xSerialTxDtcConfig.chain_transfer_mode = (dtc_chain_transfer_mode_t)0; + xSerialTxDtcConfig.source_addr = ( uint32_t ) pcString; + xSerialTxDtcConfig.dest_addr = ( uint32_t ) &U_DTC_UART_CLI_TX_DR; + xSerialTxDtcConfig.transfer_count = ( uint32_t ) usStringLength - 1; + xSerialTxDtcArg.chain_transfer_nr = 0; + xSerialTxDtcArg.p_transfer_data = &xSerialTxDtcInfo; + xSerialTxDtcArg.p_data_cfg = &xSerialTxDtcConfig; + + R_DTC_Create( xSerialTxDtcArg.act_src, &xSerialTxDtcInfo, &xSerialTxDtcConfig, 0 ); + R_DTC_Control( DTC_CMD_ACT_SRC_ENABLE, NULL, &xSerialTxDtcArg ); + R_SCI_Send( xSerialSciHandle, ( uint8_t * ) (pcString + usStringLength - 1), 1 ); + } + else + { + R_SCI_Send( xSerialSciHandle, ( uint8_t * ) pcString, 1 ); + } + + /* Wait in the Blocked state (so not using any CPU time) until the + transmission has completed. */ + ulTaskNotifyTake( pdTRUE, xMaxBlockTime ); + + /* A breakpoint can be set here for debugging. */ + nop(); + } +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime ) +{ + /* Only one UART is supported. */ + ( void ) pxPort; + + /* Return a received character, if any are available. Otherwise block to + wait for a character. */ + return xQueueReceive( xRxQueue, pcRxedChar, xBlockTime ); +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime ) +{ + /* Just mapped to vSerialPutString() so the block time is not used. */ + ( void ) xBlockTime; + + vSerialPutString( pxPort, &cOutChar, sizeof( cOutChar ) ); + return pdPASS; +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_main.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_main.h new file mode 100644 index 000000000..caa38e9d4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_main.h @@ -0,0 +1,13 @@ +#ifndef DEMO_MAIN_H +#define DEMO_MAIN_H + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/* demo_main() is placed in the src/frtos_startup/freertos_start.c and it calls +main_blinky() or main_full() according to the mainCREATE_SIMPLE_BLINKY_DEMO_ONLY +setting. */ +extern void demo_main( void ); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h new file mode 100644 index 000000000..f3a19fa11 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/FreeRTOS_Demo/demo_specific_io.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef LED_IO_H +#define LED_IO_H + + #define EnvisionRX72N + +/* Board support settings. */ + + #ifdef EnvisionRX72N + + /* R5F572NDHDFB 144pin LQFP */ + + /* General Values */ + #define LED_ON (0) + #define LED_OFF (1) + #define SW_PUSH (0) + #define SW_RELEASE (1) + + /* Switches (and its notation in the User's Manual) */ + #define SW1/*(SW2)*/ (PORT0.PIDR.BIT.B7) + #define U_GPIO_PIN_SW1/*(SW2)*/ (GPIO_PORT_0_PIN_7) + + /* LED port settings (and its notation in the User's Manual) */ + #define LED0/*(LED2)*/ (PORT4.PODR.BIT.B0) + #define U_GPIO_PIN_LED0/*(LED2)*/ (GPIO_PORT_4_PIN_0) + + /* FreeRTOS CLI Command Console */ + #define U_SCI_UART_CLI_PINSET() R_SCI_PinSet_SCI2() + #define U_SCI_UART_CLI_SCI_CH (SCI_CH2) + #define U_DTC_UART_CLI_TX_ACT ((dtc_activation_source_t)VECT(SCI2,TXI2)) + #define U_DTC_UART_CLI_TX_DR (SCI2.TDR) + + #endif /* EnvisionRX72N */ + + #ifndef LED0 + #error The hardware platform is not defined + #endif + +/* Board Support Data Structures. */ + +#include "r_sci_rx_if.h" +#include "r_dtc_rx_if.h" + +extern sci_hdl_t xSerialSciHandle; +extern dtc_transfer_data_t xSerialTxDtcInfo; + +/* Board Support Callback Functions. */ + +extern void vSerialSciCallback( void *pvArgs ); + +#endif /* LED_IO_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h new file mode 100644 index 000000000..0b8a0ea27 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_config/FreeRTOSConfig.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ (BSP_ICLK_HZ) +#define configPERIPHERAL_CLOCK_HZ (BSP_PCLKB_HZ) +#define configTICK_RATE_HZ (( TickType_t ) 1000) +#define configMINIMAL_STACK_SIZE (( unsigned short ) 170) +#define configTOTAL_HEAP_SIZE_N (60) +#define configTOTAL_HEAP_SIZE (( size_t ) ( configTOTAL_HEAP_SIZE_N * 1024 )) +#define configMAX_TASK_NAME_LEN (12) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES (7) +#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_TASK_NOTIFICATIONS 1 +#define configRECORD_STACK_HIGH_ADDRESS 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + +/* Dynamic allocation and static allocation. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 0 + +/* Run time stats gathering definitions. */ +unsigned long ulGetRunTimeCounterValue( void ); +void vConfigureTimerForRunTimeStats( void ); +#define configGENERATE_RUN_TIME_STATS 0 +//#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() +//#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (6) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will +be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before +making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then +tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has +no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care +of any DPFPU context (even if DPFPU registers are used). */ +#define configUSE_TASK_DPFPU_SUPPORT 1 + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() + +/* The buffer into which output generated by FreeRTOS+CLI is placed. This must +be at least big enough to contain the output of the task-stats command, as the +example implementation does not include buffer overlow checking. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 3500 +#define configINCLUDE_QUERY_HEAP_COMMAND 1 + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY (( configMAX_PRIORITIES - 3 )) +#define bktSECONDARY_PRIORITY (( configMAX_PRIORITIES - 4 )) +#define intqHIGHER_PRIORITY (( configMAX_PRIORITIES - 3 )) + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be used. */ +#define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_skeleton/task_function.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_skeleton/task_function.h new file mode 100644 index 000000000..c25944146 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_skeleton/task_function.h @@ -0,0 +1,23 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef TASK_FUNCTION_H_ +#define TASK_FUNCTION_H_ + +#endif /* TASK_FUNCTION_H_ */ \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_object_init.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_object_init.c new file mode 100644 index 000000000..829831d0f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_object_init.c @@ -0,0 +1,80 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name : freertos_object_init.c + * Version : 1.0 + * Description : + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 07.12.2018 1.00 First Release + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "FreeRTOS.h" +#include "freertos_start.h" +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Kernel_Object_init (void); +void Object_init_manual (void); +/*********************************************************************************************************************** + * Function Name: Kernel_Object_init + * Description : This function initializes FreeRTOS objects. + * Arguments : None. + * Return Value : None. + **********************************************************************************************************************/ +void Kernel_Object_init (void) +{ + /************** task creation ****************************/ + + /************** semaphore creation ***********************/ + + /************** queue creation ***************************/ + + /************** software time creation **************************/ + + /************** event groups creation ********************/ + + /************** stream buffer creation *************************/ + + /************** message buffer creation *********************/ + +} /* End of function Kernel_Object_init()*/ + +/*********************************************************************************************************************** + * Function Name : Object_init_manual + * Description : This function re-initializes FreeRTOS objects and should be called at runtime. + * Arguments : None. + * Return value : None. + **********************************************************************************************************************/ +void Object_init_manual (void) +{ + /************** task creation ****************************/ +} /* End of function Object_init_manual()*/ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_start.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_start.c new file mode 100644 index 000000000..25a9af682 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_start.c @@ -0,0 +1,483 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : freertos_start.c +* Version : 1.0 +* Description : Contains FreeRTOS user-defined functions. +******************************************************************************/ +/***************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2016 1.00 First Release +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" +#include "freertos_start.h" +#include "demo_main.h" +#include "demo_specific_io.h" + +#if (BSP_CFG_RTOS_USED == 1) + +#if (RTOS_USB_SUPPORT == 1) +#include "r_usb_basic_if.h" +#include "r_usb_cstd_rtos.h" +#endif + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/************* semaphore initialization *****************/ + +/****************************************************************************** +Exported global variables (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ + +/* FreeRTOS's system timer. */ +void vApplicationSetupTimerInterrupt(void); + +/* Hook functions used by FreeRTOS. */ +void vAssertCalled(void); +void vApplicationIdleHook(void); +void vApplicationTickHook(void); +void vApplicationMallocFailedHook(void); +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName); + +/* FreeRTOS's processing before start the kernel. */ +void Processing_Before_Start_Kernel(void); + +/* Main task. */ +extern void main_task(void *pvParameters); + + +/****************************************************************************** +* Function Name: vApplicationSetupTimerInterrupt +* Description : Initialize system timer for FreeRTOS with tick interrupt 1ms. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationSetupTimerInterrupt(void) +{ + /* CMT channel 0 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 0) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Stop counter. */ + CMT.CMSTR0.BIT.STR0 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT0.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT0, CMI0) = 0; + + /* Enable the interrupt. */ + IEN(CMT0, CMI0) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 0. */ + CMT.CMSTR0.BIT.STR0 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 0) */ + + /* CMT channel 1 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 1) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 1. */ + MSTP( CMT1 ) = 0; + + /* Stop counter. */ + CMT.CMSTR0.BIT.STR1 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT1.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT1.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT1.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT1, CMI1) = 0; + + /* Enable the interrupt. */ + IEN(CMT1, CMI1) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT1, CMI1) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 1. */ + CMT.CMSTR0.BIT.STR1 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 1) */ + + /* CMT channel 2 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 2) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 2. */ + MSTP( CMT2 ) = 0; + + /* Stop counter. */ + CMT.CMSTR1.BIT.STR2 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT2.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT2.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT2, CMI2) = 0; + + /* Enable the interrupt. */ + IEN(CMT2, CMI2) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT2, CMI2) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 2. */ + CMT.CMSTR1.BIT.STR2 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 2) */ + + /* CMT channel 3 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 3) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 3. */ + MSTP( CMT3 ) = 0; + + /* Stop counter. */ + CMT.CMSTR1.BIT.STR3 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT3.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT3.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT3.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT3, CMI3) = 0; + + /* Enable the interrupt. */ + IEN(CMT3, CMI3) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT3, CMI3) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 3. */ + CMT.CMSTR1.BIT.STR3 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 3) */ + +} /* End of function vApplicationSetupTimerInterrupt() */ + +/****************************************************************************** +* Function Name: vAssertCalled +* Description : This function is used to validate the input parameters. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vAssertCalled(void) +{ + volatile unsigned long ul = 0; + + taskENTER_CRITICAL(); + { + /* Use the debugger to set ul to a non-zero value in order to step out + of this function to determine why it was called. */ + while( 0 == ul ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); + +} /* End of function vAssertCalled() */ + +/****************************************************************************** +* Function Name: vApplicationIdleHook +* Description : This function will be called on each cycle of the idle task. +* NOTE: vApplicationIdleHook() MUST NOT CALL A FUNCTION +* THAT MIGHT BLOCK UNDER ANY CIRCUMSTANCES. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationIdleHook(void) +{ + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; + +} /* End of function vApplicationIdleHook() */ + +/****************************************************************************** +* Function Name: vApplicationTickHook +* Description : This function will be called every tick interrupt. +* NOTE: vApplicationTickHook() EXECUTES FROM WITHIN AN ISR, +* SO MUST BE VERY SHORT AND NOT USE MUCH STACK. +* IN ADDITION, NOT CALL ANY APIs WITHOUT "FromISR" OR +* "FROM_ISR" AT THE END. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationTickHook(void) +{ + /* The tick hook is not used by the blinky demo, but is by the full demo. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif + +} /* End of function vApplicationTickHook() */ + +/****************************************************************************** +* Function Name: vApplicationMallocFailedHook +* Description : This function is to capture the failure while +* memory allocation. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationMallocFailedHook(void) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); + + taskDISABLE_INTERRUPTS(); + for( ; ; ) + { + /* Loop here */ + }; + +} /* End of function vApplicationMallocFailedHook() */ + +/****************************************************************************** +* Function Name: vApplicationStackOverflowHook +* Description : Hook function is to capture the failure when the stack size +* is insufficient for processing. +* Arguments : pxTask - +* Task handler +* pcTaskName - +* Pointer of where to store the task's name +* Return Value : None. +******************************************************************************/ +void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); + + taskDISABLE_INTERRUPTS(); + for( ; ; ) + { + /* Loop here */ + }; + +} /* End of function vApplicationStackOverflowHook() */ + +/****************************************************************************** +* Function Name : Processing_Before_Start_Kernel +* Description : Create a main task, FreeRTOS's objects (e.g. mailbox, task, +* semaphore, mutex...) if required. +* Arguments : None. +* Return value : None. +******************************************************************************/ +void Processing_Before_Start_Kernel(void) +{ +#if 0 /* Generated Renesas Code */ + + BaseType_t ret; + + /************** semaphore creation ***********************/ + + + + /************** mutex creation ***************************/ + + + /************** queues creation **************************/ + + + /************** event groups creation ********************/ + + + /************** mailbox creation *************************/ + + + /************** memory pool creation *********************/ + + /** USB RTOS Configuration **/ +#if (RTOS_USB_SUPPORT == 1) + usb_rtos_err_t err = usb_rtos_configuration(); + if (UsbRtos_Success != err) + { + while(1) + { + /** Failure of UsbRtos Configuration **/ + } + } +#endif + + Kernel_Object_init(); + + /************** task creation ****************************/ + /* Main task. */ + ret = xTaskCreate(main_task, "MAIN_TASK", 512, NULL, 3, NULL); + if (pdPASS != ret) + { + while(1) + { + /* Failed! Task can not be created. */ + } + } + +#else /* Run FreeRTOS Demo */ + + demo_main(); + +#endif + +} /* End of function Processing_Before_Start_Kernel() */ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +void demo_main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + /* Should never get reached. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Turn on LED0 at start. (The system initialization had been done in the + src/smc_gen/general/r_cg_hardware_setup.c.) */ + LED0 = LED_ON; +} +/*-----------------------------------------------------------*/ + +#endif /* (BSP_CFG_RTOS_USED == 1) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_start.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_start.h new file mode 100644 index 000000000..f91a1efb7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/frtos_startup/freertos_start.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : freertos_start.h +* Version : 1.0 +* Description : FreeRTOS's user-defined functions header file. +******************************************************************************/ +/***************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2016 1.00 First Release +******************************************************************************/ + +#ifndef FREERTOS_START_H_ +#define FREERTOS_START_H_ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* USB FIT module support macro */ +#define RTOS_USB_SUPPORT 0 + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global variables +******************************************************************************/ +/************* semaphore handler *****************/ + + + +/************* mutex handler *********************/ + + +/************** queues handler *******************/ + + +/************** event groups handler *************/ + + +/************** mailbox handler ******************/ + + +/************** memory pool handler **************/ + + +/************** task handler *********************/ + + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +extern void Processing_Before_Start_Kernel(void); +extern void Kernel_Object_init(void); + +#endif /* FREERTOS_START_H_ */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/linker_script.ld b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/linker_script.ld new file mode 100644 index 000000000..46c2bdf16 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/linker_script.ld @@ -0,0 +1,176 @@ +MEMORY +{ + RAM : ORIGIN = 0x4, LENGTH = 0x7fffc + RAM2 : ORIGIN = 0x00800000, LENGTH = 524288 + ROM : ORIGIN = 0xFFC00000, LENGTH = 4194304 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128 +} +SECTIONS +{ + .exvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + _exvectors_start = .; + KEEP(*(.exvectors)) + _exvectors_end = .; + } >ROM + .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) + { + KEEP(*(.fvectors)) + } > ROM + .text 0xFFC00000: AT(0xFFC00000) + { + *(.text) + KEEP(*(.text.*ISR)) + KEEP(*(.text.*_isr)) + KEEP(*(.text.*_interrupt)) + *(.text.*) + *(P) + etext = .; + } > ROM + .rvectors ALIGN(4): + { + _rvectors_start = .; + INCLUDE ../src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc + _rvectors_end = .; + } > ROM + .init : + { + KEEP(*(.init)) + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = (. + 3) & ~ 3; + KEEP(*(.init_array)) + KEEP(*(SORT(.init_array.*))) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > ROM + .fini : + { + KEEP(*(.fini)) + } > ROM + .got : + { + *(.got) + *(.got.plt) + } > ROM + .rodata : + { + *(.rodata) + *(.rodata.*) + *(C_1) + *(C_2) + *(C) + _erodata = .; + } > ROM + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > ROM + .eh_frame : + { + *(.eh_frame) + } > ROM + .jcr : + { + *(.jcr) + } > ROM + .tors : + { + __CTOR_LIST__ = .; + . = ALIGN(2); + ___ctors = .; + *(.ctors) + ___ctors_end = .; + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___dtors = .; + *(.dtors) + ___dtors_end = .; + __DTOR_END__ = .; + . = ALIGN(2); + _mdata = .; + } > ROM + .data : AT(_mdata) + { + _data = .; + *(.data) + *(.data.*) + *(D) + *(D_1) + *(D_2) + _edata = .; + } > RAM + .gcc_exc : + { + *(.gcc_exc) + } > RAM + .bss : + { + _bss = .; + *(.bss) + *(.bss.**) + *(COMMON) + *(B) + *(B_1) + *(B_2) + _ebss = .; + _end = .; + } > RAM + .ofs1 0xFE7F5D00: AT(0xFE7F5D00) + { + KEEP(*(.ofs1)) + } > OFS + .ofs2 0xFE7F5D10: AT(0xFE7F5D10) + { + KEEP(*(.ofs2)) + } > OFS + .ofs3 0xFE7F5D20: AT(0xFE7F5D20) + { + KEEP(*(.ofs3)) + } > OFS + .ofs4 0xFE7F5D40: AT(0xFE7F5D40) + { + KEEP(*(.ofs4)) + } > OFS + .ofs5 0xFE7F5D48: AT(0xFE7F5D48) + { + KEEP(*(.ofs5)) + } > OFS + .ofs6 0xFE7F5D50: AT(0xFE7F5D50) + { + KEEP(*(.ofs6)) + } > OFS + .ofs7 0xFE7F5D64: AT(0xFE7F5D64) + { + KEEP(*(.ofs7)) + } > OFS + .ofs8 0xFE7F5D70: AT(0xFE7F5D70) + { + KEEP(*(.ofs8)) + } > OFS + .r_bsp_NULL : + { + . += 0x100; + "_r_bsp_NULL_end" = .; + } >RAM +.r_bsp_istack BLOCK(0x4) (NOLOAD) : + { + KEEP(*(.r_bsp_istack)) + } >RAM +.istack : + { + "_istack" = .; + } >RAM +.r_bsp_ustack BLOCK(0x4) (NOLOAD) : + { + KEEP(*(.r_bsp_ustack)) + } >RAM +.ustack : + { + "_ustack" = .; + } >RAM +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_hardware_setup.c new file mode 100644 index 000000000..094ae6dd4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_hardware_setup.c @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : Initialization file for code generation configurations. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_cgc.h" +#include "r_smc_interrupt.h" +/* Start user code for include. Do not edit comment generated here */ +#include "r_gpio_rx_if.h" +#include "r_sci_rx_pinset.h" +#include "r_sci_rx_if.h" +#include "r_dtc_rx_if.h" +#include "demo_specific_io.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +/* Board Support Data Structures. */ +sci_hdl_t xSerialSciHandle; +dtc_transfer_data_t xSerialTxDtcInfo; + +/* Workaround to execute FIT Board Support Settings */ +void R_CG_Config_Create(void); +void R_FIT_Board_Support_Settings(void); +void R_Systeminit(void) +{ + R_CG_Config_Create(); + R_FIT_Board_Support_Settings(); +} +#define R_Systeminit R_CG_Config_Create + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_undefined_exception +* Description : This function is undefined interrupt service routine +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void r_undefined_exception(void) +{ + /* Start user code for r_undefined_exception. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every configuration +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50BU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Write 0 to the target bits in the POECR2 registers */ + POE3.POECR2.WORD = 0x0000U; + + /* Initialize clocks settings */ + R_CGC_Create(); + + /* Register undefined interrupt */ + R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} + +/* Start user code for adding. Do not edit comment generated here */ + +void R_FIT_Board_Support_Settings(void) +{ + /* Do not call any functions which enables generating any interrupt requests. */ + + /* GPIO for LED */ + R_GPIO_PinWrite(U_GPIO_PIN_LED0, (gpio_level_t)LED_OFF); // for the initial level after input --> output + R_GPIO_PinDirectionSet(U_GPIO_PIN_LED0, GPIO_DIRECTION_OUTPUT); + + /* GPIO for SW */ + R_GPIO_PinDirectionSet(U_GPIO_PIN_SW1, GPIO_DIRECTION_INPUT ); + + /* FreeRTOS CLI Command Console */ + U_SCI_UART_CLI_PINSET(); + sci_cfg_t xSerialSciConfig; + xSerialSciConfig.async.baud_rate = 115200; + xSerialSciConfig.async.clk_src = SCI_CLK_INT; + xSerialSciConfig.async.data_size = SCI_DATA_8BIT; + xSerialSciConfig.async.parity_en = SCI_PARITY_OFF; + xSerialSciConfig.async.parity_type = SCI_EVEN_PARITY; + xSerialSciConfig.async.stop_bits = SCI_STOPBITS_1; + xSerialSciConfig.async.int_priority = 1; /* lowest at first. */ + R_SCI_Open(U_SCI_UART_CLI_SCI_CH, SCI_MODE_ASYNC, &xSerialSciConfig, vSerialSciCallback, &xSerialSciHandle); + R_DTC_Open(); + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); +} + +/* End user code. Do not edit comment generated here */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_interrupt_handlers.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_interrupt_handlers.h new file mode 100644 index 000000000..a042c403e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_interrupt_handlers.h @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_interrupt_handlers.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : This file declares interrupt handlers. +***********************************************************************************************************************/ + +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_macrodriver.h new file mode 100644 index 000000000..ed8ddd2fb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_macrodriver.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : Macro header file for code generation. +***********************************************************************************************************************/ + +#ifndef MACRODRIVER_H +#define MACRODRIVER_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "platform.h" +#include "r_smc_interrupt.h" +#include "r_cg_interrupt_handlers.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ +#define nop() R_BSP_NOP() +#define wait() R_BSP_WAIT() + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Systeminit(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_userdefine.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_userdefine.h new file mode 100644 index 000000000..660ad8706 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_cg_userdefine.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : User header file for code generation. +***********************************************************************************************************************/ + +#ifndef CG_USER_DEF_H +#define CG_USER_DEF_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* Start user code for register. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Start user code for macro define. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Start user code for type define. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc.c new file mode 100644 index 000000000..9b97e088f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc.c @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc.c +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : This file implements CGC setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_CGC_Create(void) +{ + /* Set CLKOUT25M pin */ + MPC.P56PFS.BYTE = 0x2AU; + PORT5.DSCR2.BYTE |= 0x40U; + PORT5.PMR.BYTE |= 0x40U; + + R_CGC_Create_UserInit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc.h new file mode 100644 index 000000000..0a594c2a8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc.h @@ -0,0 +1,174 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc.h +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : CGC setting header file. +***********************************************************************************************************************/ + +#ifndef SMC_CGC_H +#define SMC_CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PLL Clock Source Select (PLLSRCSEL) */ +#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */ +#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */ +#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */ +#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Clock Oscillator Forced Oscillation (MOFXIN) */ +#define _00_CGC_MAINOSC_NOT_CONTROLLED (0x00U) /* Oscillator is not controlled by this bit */ +#define _01_CGC_MAINOSC_FORCE_OSCILLATED (0x01U) /* The main clock oscillator is forcedly oscillated */ +/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */ +#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */ +#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */ +#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */ +#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + PPLL Control Register (PPLLCR) +*/ +/* PPLL Input Pulse Frequency Division Ratio Select (PPLIDIV[1:0]) */ +#define _0000_CGC_PPLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PPLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PPLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PPLL Frequency Multiplier Setting (PPLSTC[5:0]) */ +#define _1300_CGC_PPLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PPLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PPLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PPLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PPLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PPLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PPLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PPLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PPLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PPLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PPLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PPLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PPLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PPLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PPLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PPLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PPLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PPLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PPLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PPLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PPLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PPLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PPLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PPLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PPLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PPLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PPLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PPLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PPLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PPLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PPLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PPLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PPLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PPLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PPLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PPLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PPLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PPLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PPLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PPLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PPLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); +void R_CGC_Create_UserInit(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc_user.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc_user.c new file mode 100644 index 000000000..378321ff7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_cgc_user.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc_user.c +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : This file implements CGC setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create_UserInit +* Description : This function adds user code after initializing CGC +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_CGC_Create_UserInit(void) +{ + /* Start user code for user init. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_entry.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_entry.h new file mode 100644 index 000000000..e91c0784e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_entry.h @@ -0,0 +1,53 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_entry.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : SMC platform header file. +***********************************************************************************************************************/ + +#ifndef SMC_ENTRY_H +#define SMC_ENTRY_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_interrupt.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_interrupt.c new file mode 100644 index 000000000..59f2a4533 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_interrupt.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_interrupt.c +* Version : 1.1.0 +* Device(s) : R5F572NNHxFB +* Description : This file implements interrupt setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_interrupt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Interrupt_Create +* Description : This function Used to set the fast interrupt or group interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Interrupt_Create(void) +{ + /* No fast interrupt and group settings have been configured in the Interrupts tab. */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_interrupt.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_interrupt.h new file mode 100644 index 000000000..5182f04cc --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/general/r_smc_interrupt.h @@ -0,0 +1,293 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_interrupt.h +* Version : 1.1.0 +* Device(s) : R5F572NNHxFB +* Description : This file implements interrupt setting. +***********************************************************************************************************************/ + +#ifndef SMC_INTERRUPT_H +#define SMC_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* Priority level of interrupt source. + * These macro definitions are used to set the IPR register directly + */ +#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (disabled) */ +#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab + * Please do not modify this file manually + */ +#define ICU_BSC_BUSERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPIE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RAM_RAMERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_FCU_FIFERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_FCU_FRDYI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_SWINT2_PRIORITY (_01_ICU_PRIORITY_LEVEL1) +#define ICU_ICU_SWINT_PRIORITY (_01_ICU_PRIORITY_LEVEL1) +#define ICU_CMT0_CMI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT1_CMI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_CMWI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_CMWI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_D0FIFO0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_D1FIFO0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI0_SPRI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI0_SPTI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI1_SPRI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI1_SPTI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_QSPI_SPRI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_QSPI_SPTI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SDHI_SBFAI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MMCIF_MBFAI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE0_SSITXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE0_SSIRXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE1_SSIRTI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC1_RXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC1_TXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC0_RXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC0_TXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC2_RXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC2_TXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI0_RXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI0_TXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI1_RXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI1_TXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI2_RXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI2_TXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ13_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ14_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ15_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI3_RXI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI3_TXI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI4_RXI4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI4_TXI4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI5_RXI5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI5_TXI5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI6_RXI6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI6_TXI6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_LVD1_LVD1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_LVD2_LVD2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_USBR0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_ALM_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_PRD_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_IWDT_IWUNI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_WDT_WUNI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PDC_PCDFI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI7_RXI7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI7_TXI7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI8_RXI8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI8_TXI8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI9_RXI9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI9_TXI9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI10_RXI10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI10_TXI10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI2_SPRI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI2_SPTI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPAL0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPAL1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI11_RXI11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI11_TXI11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI12_RXI12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI12_TXI12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC2I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC3I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC74I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_OST_OSTDI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EXDMAC_EXDMAC0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EXDMAC_EXDMAC1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT2_CMI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT3_CMI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0C_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0D_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TCI0V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TGI1B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TCI1V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TCI1U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TGI2A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TGI2B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TCI2V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TCI2U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TGI1A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3C_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_CMIA0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_CMIB0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_OVI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_CMIA1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_CMIB1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_OVI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_CMIA2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_CMIB2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_OVI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_CMIA3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_CMIB3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_OVI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3D_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TCI3V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TGI4A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TGI4B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TCI4V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TCI4U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TGI5A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TGI5B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TCI5V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TCI5U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_IC0I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_IC1I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_OC0I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_OC1I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_IC0I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_IC1I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_OC0I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_OC1I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_CUP_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_RXF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_TXF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_RXM0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_TXM0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_RXF1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_TXF1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_RXM1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_TXM1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_USBI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12ADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12GBADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12GCADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12ADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12GBADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12GCADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ELC_ELSR18I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ELC_ELSR19I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_PROC_BUSY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_ROMOK_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_LONG_PLG_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_TEST_BUSY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_RDRDY0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_RDRDY1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB205_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB206_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB207_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TGIA1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIA0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIB0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIC0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGID0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TCIV0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TGIB1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TCIV1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TCIU1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TGIA2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TGIB2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TCIV2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TCIU2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIA3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIB3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIC3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGID3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TCIV3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIA4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIB4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIC4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGID4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TCIV4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIU5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIV5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIW5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIA6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIB6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIC6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGID6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TCIV6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIA7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIB7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIC7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGID7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TCIV7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIA8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIB8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIC8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGID8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TCIV8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EPTPC_IPLS_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PMGI0_PMGI0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PMGI1_PMGI1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIA_INTA254_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIA_INTA255_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Interrupt_Create(void); +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c new file mode 100644 index 000000000..0620d7fe2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c @@ -0,0 +1,414 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.c +* Device(s) : RX +* H/W Platform : GENERIC_RX72N +* Description : Defines the initialization routines used each time the MCU is restarted. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* I/O Register and board definitions */ +#include "platform.h" +#if BSP_CFG_CONFIGURATOR_SELECT == 1 +#include "r_cg_macrodriver.h" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +R_BSP_PRAGMA_UNPACK +typedef struct bsp_bsc { + union { + uint32_t u_long; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13( + uint32_t prerr:1, + uint32_t :1, + uint32_t rpstop:1, + uint32_t :10, + uint32_t pr5sel:3, + uint32_t :1, + uint32_t pr4sel:3, + uint32_t :1, + uint32_t pr3sel:3, + uint32_t :1, + uint32_t pr2sel:3, + uint32_t :1, + uint32_t pr1sel:3 + ) bit; + } ebmapcr; +} st_bsp_bsc_t; +R_BSP_PRAGMA_PACKOPTION + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +/* ROM cache configuration function declaration */ +#if BSP_CFG_ROM_CACHE_ENABLE == 1 +static void rom_cache_function_set(void); +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 +static void rom_cache_noncacheable_area0_set(void); +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 +static void rom_cache_noncacheable_area1_set(void); +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/* MCU I/O port configuration function declaration */ +static void output_ports_configure(void); + +/* Interrupt configuration function declaration */ +static void interrupts_configure(void); + +/* MCU peripheral module configuration function declaration */ +static void peripheral_modules_enable(void); + +/* ADC initial configuration function declaration */ +static void bsp_adc_initial_configure(void); + +/* BUS initial configuration function declaration */ +static void bsp_bsc_initial_configure(void); + +/*********************************************************************************************************************** +* Function name: hardware_setup +* Description : Contains setup functions called at device restart +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void hardware_setup(void) +{ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +#if BSP_CFG_ROM_CACHE_ENABLE == 1 + /* Initialize ROM cache function */ + rom_cache_function_set(); +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + + output_ports_configure(); + interrupts_configure(); + peripheral_modules_enable(); + bsp_non_existent_port_init(); + bsp_adc_initial_configure(); + bsp_bsc_initial_configure(); +} /* End of function hardware_setup() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +#if BSP_CFG_ROM_CACHE_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_function_set +* Description : Configures the rom cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_function_set (void) +{ +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 + rom_cache_noncacheable_area0_set(); +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ + +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 + rom_cache_noncacheable_area1_set(); +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ + + /* Invalidates the contents of the ROM cache. */ + FLASH.ROMCIV.WORD = 0x0001; + + /* Enables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0001; +} /* End of function rom_cache_function_set() */ + +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_noncacheable_area0_set +* Description : Configures non-cacheable area 0 of the ROM cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_noncacheable_area0_set (void) +{ + /* Used to specify the value written to the NCRC0 register. */ + uint32_t tmp_ncrc = 0; + + /* Disables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0000; + + /* Makes settings to the NCRG0 register. */ +#if (BSP_CFG_NONCACHEABLE_AREA0_ADDR >= 0xFFC00000) \ + && ((BSP_CFG_NONCACHEABLE_AREA0_ADDR & 0x0000000F) == 0x00000000) + FLASH.NCRG0 = BSP_CFG_NONCACHEABLE_AREA0_ADDR; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA0_ADDR in r_bsp_config.h" +#endif + + /* Sets the value of the NCSZ bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x0 + /* Do nothing since NCRC0 bits should be 0. */ +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x1 + tmp_ncrc |= 0x00000010; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x2 + tmp_ncrc |= 0x00000030; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x3 + tmp_ncrc |= 0x00000070; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x4 + tmp_ncrc |= 0x000000F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x5 + tmp_ncrc |= 0x000001F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x6 + tmp_ncrc |= 0x000003F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x7 + tmp_ncrc |= 0x000007F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x8 + tmp_ncrc |= 0x00000FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x9 + tmp_ncrc |= 0x00001FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xA + tmp_ncrc |= 0x00003FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xB + tmp_ncrc |= 0x00007FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xC + tmp_ncrc |= 0x0000FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xD + tmp_ncrc |= 0x0001FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xE + tmp_ncrc |= 0x0003FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xF + tmp_ncrc |= 0x0007FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x10 + tmp_ncrc |= 0x000FFFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x11 + tmp_ncrc |= 0x001FFFF0; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA0_SIZE in r_bsp_config.h" +#endif + + /* Sets the value of the NC1E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE == 1 + tmp_ncrc |= 0x00000002; +#endif + + /* Sets the value of the NC2E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE == 1 + tmp_ncrc |= 0x00000004; +#endif + + /* Sets the value of the NC3E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE == 1 + tmp_ncrc |= 0x00000008; +#endif + + /* Makes settings to the NCRC0 register. */ + FLASH.NCRC0.LONG = tmp_ncrc; +} /* End of function rom_cache_noncacheable_area0_set() */ +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ + +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_noncacheable_area1_set +* Description : Configures non-cacheable area 1 of the ROM cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_noncacheable_area1_set (void) +{ + /* Used to specify the value written to the NCRC1 register. */ + uint32_t tmp_ncrc = 0; + + /* Disables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0000; + + /* Makes settings to the NCRG1 register. */ +#if (BSP_CFG_NONCACHEABLE_AREA1_ADDR >= 0xFFC00000) \ + && ((BSP_CFG_NONCACHEABLE_AREA1_ADDR & 0x0000000F) == 0x00000000) + FLASH.NCRG1 = BSP_CFG_NONCACHEABLE_AREA1_ADDR; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA1_ADDR in r_bsp_config.h" +#endif + + /* Sets the value of the NCSZ bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x0 + /* Do nothing since NCRC1 bits should be 0. */ +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x1 + tmp_ncrc |= 0x00000010; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x2 + tmp_ncrc |= 0x00000030; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x3 + tmp_ncrc |= 0x00000070; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x4 + tmp_ncrc |= 0x000000F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x5 + tmp_ncrc |= 0x000001F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x6 + tmp_ncrc |= 0x000003F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x7 + tmp_ncrc |= 0x000007F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x8 + tmp_ncrc |= 0x00000FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x9 + tmp_ncrc |= 0x00001FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xA + tmp_ncrc |= 0x00003FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xB + tmp_ncrc |= 0x00007FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xC + tmp_ncrc |= 0x0000FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xD + tmp_ncrc |= 0x0001FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xE + tmp_ncrc |= 0x0003FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xF + tmp_ncrc |= 0x0007FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x10 + tmp_ncrc |= 0x000FFFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x11 + tmp_ncrc |= 0x001FFFF0; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA1_SIZE in r_bsp_config.h" +#endif + + /* Sets the value of the NC1E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE == 1 + tmp_ncrc |= 0x00000002; +#endif + + /* Sets the value of the NC2E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE == 1 + tmp_ncrc |= 0x00000004; +#endif + + /* Sets the value of the NC3E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE == 1 + tmp_ncrc |= 0x00000008; +#endif + + /* Makes settings to the NCRC1 register. */ + FLASH.NCRC1.LONG = tmp_ncrc; +} /* End of function rom_cache_noncacheable_area1_set() */ +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function name: output_ports_configure +* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void output_ports_configure(void) +{ + /* Add code here to setup additional output ports */ + R_BSP_NOP(); +} /* End of function output_ports_configure() */ + +/*********************************************************************************************************************** +* Function name: interrupts_configure +* Description : Configures interrupts used +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void interrupts_configure(void) +{ + /* Add code here to setup additional interrupts */ + R_BSP_NOP(); +} /* End of function interrupts_configure() */ + +/*********************************************************************************************************************** +* Function name: peripheral_modules_enable +* Description : Enables and configures peripheral devices on the MCU +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void peripheral_modules_enable(void) +{ + /* Add code here to enable peripherals used by the application */ +#if BSP_CFG_CONFIGURATOR_SELECT == 1 + /* Smart Configurator initialization function */ + R_Systeminit(); +#endif +} /* End of function peripheral_modules_enable() */ + +/*********************************************************************************************************************** +* Function name: bsp_adc_initial_configure +* Description : Configures the ADC initial settings +* Arguments : none +* Return value : none +* Note : This function should be called when the PSW.I bit is 0 (interrupt disabled). +* This function should be called when the ADCSR.ADST bit is 0. +***********************************************************************************************************************/ +static void bsp_adc_initial_configure(void) +{ + uint32_t tmp_mstp; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Store the value of the MSTPCR. */ + tmp_mstp = MSTP(S12AD1); + + /* Release from the module-stop state */ + MSTP(S12AD1) = 0; + + /* Writing to the A/D conversion time setting register is enabled. */ + S12AD1.ADSAMPR.BYTE = 0x03; + + /* Sets conversion time for middle-speed for S12AD unit 1. */ + S12AD1.ADSAM.WORD = 0x0020; + + /* Writing to the A/D conversion time setting register is disabled. */ + S12AD1.ADSAMPR.BYTE = 0x02; + + /* Restore the value of the MSTPCR. */ + MSTP(S12AD1) = tmp_mstp; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_adc_initial_configure() */ + +/*********************************************************************************************************************** +* Function name: bsp_bsc_initial_configure +* Description : Configures the BUS initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_bsc_initial_configure(void) +{ + st_bsp_bsc_t bsp_bsc; + + /* Setting priority when bus right request contention occurs. */ + bsp_bsc.ebmapcr.u_long = BSC.EBMAPCR.LONG; + bsp_bsc.ebmapcr.bit.pr1sel = BSP_CFG_EBMAPCR_1ST_PRIORITY; + bsp_bsc.ebmapcr.bit.pr2sel = BSP_CFG_EBMAPCR_2ND_PRIORITY; + bsp_bsc.ebmapcr.bit.pr3sel = BSP_CFG_EBMAPCR_3RD_PRIORITY; + bsp_bsc.ebmapcr.bit.pr4sel = BSP_CFG_EBMAPCR_4TH_PRIORITY; + bsp_bsc.ebmapcr.bit.pr5sel = BSP_CFG_EBMAPCR_5TH_PRIORITY; + + /* Set to EBMAPCR register */ + BSC.EBMAPCR.LONG = bsp_bsc.ebmapcr.u_long; +} /* End of function bsp_bsc_initial_configure() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h new file mode 100644 index 000000000..6c25e0f30 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.h +* Description : Hardware setup header file. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef HWSETUP_H +#define HWSETUP_H + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void hardware_setup(void); //r_bsp internal function. DO NOT CALL. + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h new file mode 100644 index 000000000..28180a97e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* H/W Platform : GENERIC_RX72N +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +#include "mcu/all/r_bsp_common.h" +#include "r_bsp_config.h" +#include "mcu/all/r_rx_compiler.h" + +#include "r_bsp_interrupt_config.h" + +#include "mcu/all/lowlvl.h" +#include "mcu/all/lowsrc.h" +#include "mcu/all/r_bsp_mcu_startup.h" + +#if defined(__CCRX__) +#include "mcu/rx72n/register_access/ccrx/iodefine.h" +#elif defined(__GNUC__) +#include "mcu/rx72n/register_access/gnuc/iodefine.h" +#elif defined(__ICCRX__) +#include "mcu/rx72n/register_access/iccrx/iodefine.h" +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "mcu/rx72n/r_bsp_cpu.h" +#include "mcu/rx72n/r_bsp_locking.h" +#include "mcu/rx72n/mcu_clocks.h" +#include "mcu/rx72n/mcu_info.h" +#include "mcu/rx72n/mcu_init.h" +#include "mcu/rx72n/mcu_interrupts.h" +#include "mcu/rx72n/mcu_locks.h" +#include "mcu/rx72n/mcu_mapped_interrupts_private.h" +#include "mcu/rx72n/mcu_mapped_interrupts.h" +#include "mcu/rx72n/vecttbl.h" + +#include "board/generic_rx72n/hwsetup.h" + +#include "mcu/all/r_bsp_interrupts.h" +#include "mcu/all/r_bsp_software_interrupt.h" +#include "mcu/all/r_rx_intrinsic_functions.h" +#include "mcu/all/r_rtos.h" + +#ifdef __cplusplus +} +#endif + +#ifndef BSP_BOARD_GENERIC_RX72N +#define BSP_BOARD_GENERIC_RX72N + +#endif /* BSP_BOARD_GENERIC_RX72N */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h new file mode 100644 index 000000000..be9268128 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h @@ -0,0 +1,766 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX72N +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release. +***********************************************************************************************************************/ +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX72N. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 57 2N N D D BD + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FC = 0x0 = LFQFP/176/0.50 + BG = 0x1 = LFBGA/176/0.80 + BD = 0x2 = LFBGA/224/0.80 + FB = 0x3 = LFQFP/144/0.50 + LK = 0x4 = TFLGA/145/0.50 + FP = 0x5 = LFQFP/100/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x2) + +/* Whether Encryption is included or not. + Character(s) = Value for macro = Description + D = 0xD = Encryption module not included + H = 0x11 = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0xD) + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + D = 0xD = 2MB/1MB/32KB + N = 0x17 = 4MB/1MB/32KB +NOTE: The RAM areas are not contiguous.It is separated by 512 KB each. +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x17) + +/* Group name. + Character(s) = Value for macro = Description + 2N = 0x0 = RX72N Group +*/ +#define BSP_CFG_MCU_PART_GROUP (0x0) + +/* Series name. + Character(s) = Value for macro = Description + 57 = 0x0 = RX700 Series +*/ +#define BSP_CFG_MCU_PART_SERIES (0x0) + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (1) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x1000) +#endif + +/* Interrupt Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x400) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit (default) +*/ +#define BSP_CFG_CLOCK_SOURCE (4) + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator (default) + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (0) + +/* USB Clock source select (UPLLSEL). Choose which clock source to input to the USB circuit. + 0 = System Clock (PLL Circuit/No division) (This is not available.) + 1 = USB PLL Circuit (This is not available.) + 2 = PLL Circuit (UDIVCLK) (default) + 3 = PPLL Circuit (PPLLDIVCLK) +*/ +#define BSP_CFG_USB_CLOCK_SOURCE (2) + +/* Ethernet-PHY clock source (OUTCKSEL). Choose which clock source to input to the Ethernet PHY LSI. + Available clock sources: + 0 = PLL circuit + 1 = PPLL circuit (default) + 2 = Ethernet-PHY not use +*/ +#define BSP_CFG_PHY_CLOCK_SOURCE (1) + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 6 = PPLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE (2) + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE (0) + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP (0) + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, BCLK is 80MHz, + USB Clock is 48MHz, ESC Clock is 100MHz, Ether-Phy Clock is 25MHz then the settings would be: + + BSP_CFG_XTAL_HZ = 24000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz) + BSP_CFG_PPLL_DIV = 3 (divide by 3) + BSP_CFG_PPLL_MUL = 25.0 (8MHz x 25.0 = 200MHz) + BSP_CFG_PPLCK_DIV = 2 (divide by 2) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 240MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_BCK_DIV = 3 : External Bus Clock (BCK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 80MHz + BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (24000000) + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#define BSP_CFG_HOCO_FREQUENCY (0) + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC (0) + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (1) + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL (10.0) + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (1) + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (2) + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (4) + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (4) + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (4) + +/* External Bus Clock Divider (BCLK). + Available divisors = /1 (no division), /2, /3, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_BCK_DIV (3) + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (4) + +/* USB Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_UCK_DIV (5) + +/* PPLL Input Frequency Division Ratio Select (PPLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PPLL_DIV (3) + +/* PPLL Frequency Multiplication Factor Select (PPLSTC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PPLL_MUL (25.0) + +/* PPLL Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_PPLCK_DIV (2) + +/* Configure BCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency +*/ +#define BSP_CFG_BCLK_OUTPUT (0) + +/* Configure SDCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency + NOTE: The definition is invalid. +*/ +#define BSP_CFG_SDCLK_OUTPUT (0) + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV (0) + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT (0) + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) + +/* Sub-Clock Oscillator Wait Time (SOSCWTCR). + The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation + by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384 + (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h). +*/ +#define BSP_CFG_SOSC_WAIT_TIME (0x21) + +/* ROM Cache Enable Register (ROMCE). + 0 = ROM cache operation disabled. + 1 = ROM cache operation enabled. +*/ +#define BSP_CFG_ROM_CACHE_ENABLE (1) + +/* Configure non-cacheable area 0 of the ROM cache function. + 0 = Non-cacheable area 0 settings disabled. + 1 = Non-cacheable area 0 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ENABLE (0) + +/* Specifies the start address of non-cacheable area 0. + Selects the start address of non-cacheable area 0. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 0. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of IF cache disabled. + 1 = Non-cacheable area 0 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of OA cache disabled. + 1 = Non-cacheable area 0 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of DM cache disabled. + 1 = Non-cacheable area 0 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE (1) + +/* Configure non-cacheable area 1 of the ROM cache function. + 0 = Non-cacheable area 1 settings disabled. + 1 = Non-cacheable area 1 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ENABLE (0) + +/* Specifies the start address of non-cacheable area 1. + Selects the start address of non-cacheable area 1. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 1. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of IF cache disabled. + 1 = Non-cacheable area 1 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of OA cache disabled. + 1 = Non-cacheable area 1 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of DM cache disabled. + 1 = Non-cacheable area 1 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE (1) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 78 and 79 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEFF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b26] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area + - 1: FFFF E000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory + when the flash programmer is used during off-board programming. + ROMCODE - ROM Code Protection Register + b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1). + 0000 0001h: ROM code protection enabled (ROM code protection 2). + Other than above: ROM code protection disabled. + Note: The ROMCODE register should be set in 32-bit units. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. +*/ +#define BSP_CFG_RTOS_USED (0) + +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC + graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and + display list data read). + The default priority order in bsp is below + GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC. + Priority can be changed with this macro. + + Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */ +#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */ +#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */ +#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */ +#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */ + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (0) + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (1) +#define BSP_CFG_SWINT_UNIT2_ENABLE (1) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h new file mode 100644 index 000000000..697280fd6 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h @@ -0,0 +1,222 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupt_config.h +* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ +#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE +#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you + * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you + * would do the following: + * + * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 + */ + +/* Interrupt B Sources. + * -Valid vector numbers are 128-207. + * -There are more vector slots for B sources than actual B sources. By default none of the CAN2 interrupts are + * mapped. + * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default. + * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be + * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0' + * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots. + */ +#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128 +#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175 +#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 192 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 193 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 194 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 195 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 196 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 197 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 198 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 199 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 200 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 201 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 202 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 203 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 204 + +/* Interrupt A Sources. + * -Valid vector numbers are 208-255. + * -There are more A sources than A vector slots. By default none of the GPTW interrupts and the ESC interrupts are + * mapped. + * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default. + */ +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3 +#define BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS 251 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I 252 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I 253 + +#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/user/r_bsp.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/user/r_bsp.h new file mode 100644 index 000000000..94ecab164 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/board/user/r_bsp.h @@ -0,0 +1,54 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 13.01.2012 1.00 First Release +* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure. +***********************************************************************************************************************/ + +#ifndef BSP_BOARD_USER +#define BSP_BOARD_USER + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +/* This is a user defined board. Start off by: + 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group). + 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h. + 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier. + 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h. + 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h. + You can also add your own include files here as well. */ +#include "r_bsp_config.h" +#include "mcu/*MCU Group*/mcu_info.h" + +#endif /* BSP_BOARD_USER */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/dbsct.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/dbsct.c new file mode 100644 index 000000000..9f71dec6c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/dbsct.c @@ -0,0 +1,133 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : dbsct.c +* Description : Defines the structure of the ROM and RAM areas. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Added definition for section of D_8, B_8, and C_8. +* : 08.10.2019 3.01 Added section for Renesas RTOS (RI600V4 or RI600PX). +* : 14.02.2020 3.02 Corrected pragma declaration of unpack. +***********************************************************************************************************************/ + +#if defined(__CCRX__) +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/* Preprocessor directive */ +#pragma unpack + +/* MCU ROM and RAM structure definition */ +typedef struct +{ + uint8_t *rom_s; /* Start address of the initialized data section in ROM */ + uint8_t *rom_e; /* End address of the initialized data section in ROM */ + uint8_t *ram_s; /* Start address of the initialized data section in RAM */ +} st_dtbl_t; + +typedef struct +{ + uint8_t *b_s; /* Start address of non-initialized data section */ + uint8_t *b_e; /* End address of non-initialized data section */ +} st_btbl_t; + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/* Section start */ +#pragma section C C$DSEC + +extern st_dtbl_t const _DTBL[] = { +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + { __sectop("D_8"), __secend("D_8"), __sectop("R_8") }, +#endif + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX) + ,{ __sectop("DRI_ROM"), __secend("DRI_ROM"), __sectop("RRI_RAM") } +#endif /* Renesas RI600PX */ +}; + +/* Section start */ +#pragma section C C$BSEC + +extern st_btbl_t const _BTBL[] = { +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + { __sectop("B_8"), __secend("B_8") }, +#endif + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4) + ,{ __sectop("BRI_RAM"), __secend("BRI_RAM") } +#endif /* Renesas RI600V4 */ +}; + +/* Section start */ +#pragma section + +#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX) +#pragma section C CS +#endif /* Renesas RI600PX */ + +/* CTBL prevents excessive output of L1100 messages when linking. + Even if CTBL is deleted, the operation of the program does not change. */ +uint8_t * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + __sectop("C_8"), +#endif + __sectop("W_1"), __sectop("W_2"), __sectop("W") +}; + +/* Preprocessor directive */ +#pragma packoption + +/* This is to ensure compatibility with new L section in version 1.1 and up of the RXC compiler. Do not remove! */ +#pragma section C L +const uint32_t deadSpace = 0xDEADDEAD; +#pragma section + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +#endif /* defined(__CCRX__) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc new file mode 100644 index 000000000..d30ad475d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/linker_script_rvectors.inc @@ -0,0 +1,283 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : linker_script_rvectors.inc +* Description : This module is used to set the interrupt table. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +LONG(DEFINED($tableentry$0$.rvectors) ? $tableentry$0$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$1$.rvectors) ? $tableentry$1$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$2$.rvectors) ? $tableentry$2$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$3$.rvectors) ? $tableentry$3$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$4$.rvectors) ? $tableentry$4$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$5$.rvectors) ? $tableentry$5$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$6$.rvectors) ? $tableentry$6$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$7$.rvectors) ? $tableentry$7$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$8$.rvectors) ? $tableentry$8$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$9$.rvectors) ? $tableentry$9$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$10$.rvectors) ? $tableentry$10$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$11$.rvectors) ? $tableentry$11$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$12$.rvectors) ? $tableentry$12$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$13$.rvectors) ? $tableentry$13$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$14$.rvectors) ? $tableentry$14$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$15$.rvectors) ? $tableentry$15$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$16$.rvectors) ? $tableentry$16$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$17$.rvectors) ? $tableentry$17$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$18$.rvectors) ? $tableentry$18$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$19$.rvectors) ? $tableentry$19$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$20$.rvectors) ? $tableentry$20$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$21$.rvectors) ? $tableentry$21$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$22$.rvectors) ? $tableentry$22$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$23$.rvectors) ? $tableentry$23$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$24$.rvectors) ? $tableentry$24$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$25$.rvectors) ? $tableentry$25$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$26$.rvectors) ? $tableentry$26$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$27$.rvectors) ? $tableentry$27$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$28$.rvectors) ? $tableentry$28$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$29$.rvectors) ? $tableentry$29$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$30$.rvectors) ? $tableentry$30$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$31$.rvectors) ? $tableentry$31$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$32$.rvectors) ? $tableentry$32$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$33$.rvectors) ? $tableentry$33$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$34$.rvectors) ? $tableentry$34$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$35$.rvectors) ? $tableentry$35$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$36$.rvectors) ? $tableentry$36$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$37$.rvectors) ? $tableentry$37$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$38$.rvectors) ? $tableentry$38$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$39$.rvectors) ? $tableentry$39$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$40$.rvectors) ? $tableentry$40$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$41$.rvectors) ? $tableentry$41$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$42$.rvectors) ? $tableentry$42$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$43$.rvectors) ? $tableentry$43$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$44$.rvectors) ? $tableentry$44$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$45$.rvectors) ? $tableentry$45$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$46$.rvectors) ? $tableentry$46$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$47$.rvectors) ? $tableentry$47$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$48$.rvectors) ? $tableentry$48$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$49$.rvectors) ? $tableentry$49$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$50$.rvectors) ? $tableentry$50$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$51$.rvectors) ? $tableentry$51$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$52$.rvectors) ? $tableentry$52$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$53$.rvectors) ? $tableentry$53$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$54$.rvectors) ? $tableentry$54$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$55$.rvectors) ? $tableentry$55$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$56$.rvectors) ? $tableentry$56$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$57$.rvectors) ? $tableentry$57$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$58$.rvectors) ? $tableentry$58$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$59$.rvectors) ? $tableentry$59$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$60$.rvectors) ? $tableentry$60$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$61$.rvectors) ? $tableentry$61$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$62$.rvectors) ? $tableentry$62$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$63$.rvectors) ? $tableentry$63$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$64$.rvectors) ? $tableentry$64$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$65$.rvectors) ? $tableentry$65$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$66$.rvectors) ? $tableentry$66$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$67$.rvectors) ? $tableentry$67$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$68$.rvectors) ? $tableentry$68$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$69$.rvectors) ? $tableentry$69$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$70$.rvectors) ? $tableentry$70$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$71$.rvectors) ? $tableentry$71$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$72$.rvectors) ? $tableentry$72$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$73$.rvectors) ? $tableentry$73$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$74$.rvectors) ? $tableentry$74$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$75$.rvectors) ? $tableentry$75$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$76$.rvectors) ? $tableentry$76$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$77$.rvectors) ? $tableentry$77$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$78$.rvectors) ? $tableentry$78$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$79$.rvectors) ? $tableentry$79$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$80$.rvectors) ? $tableentry$80$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$81$.rvectors) ? $tableentry$81$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$82$.rvectors) ? $tableentry$82$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$83$.rvectors) ? $tableentry$83$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$84$.rvectors) ? $tableentry$84$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$85$.rvectors) ? $tableentry$85$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$86$.rvectors) ? $tableentry$86$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$87$.rvectors) ? $tableentry$87$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$88$.rvectors) ? $tableentry$88$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$89$.rvectors) ? $tableentry$89$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$90$.rvectors) ? $tableentry$90$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$91$.rvectors) ? $tableentry$91$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$92$.rvectors) ? $tableentry$92$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$93$.rvectors) ? $tableentry$93$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$94$.rvectors) ? $tableentry$94$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$95$.rvectors) ? $tableentry$95$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$96$.rvectors) ? $tableentry$96$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$97$.rvectors) ? $tableentry$97$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$98$.rvectors) ? $tableentry$98$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$99$.rvectors) ? $tableentry$99$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$100$.rvectors) ? $tableentry$100$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$101$.rvectors) ? $tableentry$101$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$102$.rvectors) ? $tableentry$102$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$103$.rvectors) ? $tableentry$103$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$104$.rvectors) ? $tableentry$104$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$105$.rvectors) ? $tableentry$105$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$106$.rvectors) ? $tableentry$106$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$107$.rvectors) ? $tableentry$107$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$108$.rvectors) ? $tableentry$108$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$109$.rvectors) ? $tableentry$109$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$110$.rvectors) ? $tableentry$110$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$111$.rvectors) ? $tableentry$111$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$112$.rvectors) ? $tableentry$112$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$113$.rvectors) ? $tableentry$113$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$114$.rvectors) ? $tableentry$114$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$115$.rvectors) ? $tableentry$115$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$116$.rvectors) ? $tableentry$116$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$117$.rvectors) ? $tableentry$117$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$118$.rvectors) ? $tableentry$118$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$119$.rvectors) ? $tableentry$119$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$120$.rvectors) ? $tableentry$120$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$121$.rvectors) ? $tableentry$121$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$122$.rvectors) ? $tableentry$122$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$123$.rvectors) ? $tableentry$123$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$124$.rvectors) ? $tableentry$124$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$125$.rvectors) ? $tableentry$125$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$126$.rvectors) ? $tableentry$126$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$127$.rvectors) ? $tableentry$127$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$128$.rvectors) ? $tableentry$128$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$129$.rvectors) ? $tableentry$129$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$130$.rvectors) ? $tableentry$130$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$131$.rvectors) ? $tableentry$131$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$132$.rvectors) ? $tableentry$132$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$133$.rvectors) ? $tableentry$133$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$134$.rvectors) ? $tableentry$134$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$135$.rvectors) ? $tableentry$135$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$136$.rvectors) ? $tableentry$136$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$137$.rvectors) ? $tableentry$137$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$138$.rvectors) ? $tableentry$138$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$139$.rvectors) ? $tableentry$139$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$140$.rvectors) ? $tableentry$140$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$141$.rvectors) ? $tableentry$141$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$142$.rvectors) ? $tableentry$142$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$143$.rvectors) ? $tableentry$143$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$144$.rvectors) ? $tableentry$144$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$145$.rvectors) ? $tableentry$145$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$146$.rvectors) ? $tableentry$146$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$147$.rvectors) ? $tableentry$147$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$148$.rvectors) ? $tableentry$148$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$149$.rvectors) ? $tableentry$149$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$150$.rvectors) ? $tableentry$150$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$151$.rvectors) ? $tableentry$151$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$152$.rvectors) ? $tableentry$152$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$153$.rvectors) ? $tableentry$153$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$154$.rvectors) ? $tableentry$154$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$155$.rvectors) ? $tableentry$155$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$156$.rvectors) ? $tableentry$156$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$157$.rvectors) ? $tableentry$157$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$158$.rvectors) ? $tableentry$158$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$159$.rvectors) ? $tableentry$159$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$160$.rvectors) ? $tableentry$160$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$161$.rvectors) ? $tableentry$161$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$162$.rvectors) ? $tableentry$162$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$163$.rvectors) ? $tableentry$163$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$164$.rvectors) ? $tableentry$164$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$165$.rvectors) ? $tableentry$165$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$166$.rvectors) ? $tableentry$166$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$167$.rvectors) ? $tableentry$167$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$168$.rvectors) ? $tableentry$168$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$169$.rvectors) ? $tableentry$169$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$170$.rvectors) ? $tableentry$170$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$171$.rvectors) ? $tableentry$171$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$172$.rvectors) ? $tableentry$172$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$173$.rvectors) ? $tableentry$173$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$174$.rvectors) ? $tableentry$174$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$175$.rvectors) ? $tableentry$175$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$176$.rvectors) ? $tableentry$176$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$177$.rvectors) ? $tableentry$177$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$178$.rvectors) ? $tableentry$178$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$179$.rvectors) ? $tableentry$179$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$180$.rvectors) ? $tableentry$180$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$181$.rvectors) ? $tableentry$181$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$182$.rvectors) ? $tableentry$182$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$183$.rvectors) ? $tableentry$183$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$184$.rvectors) ? $tableentry$184$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$185$.rvectors) ? $tableentry$185$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$186$.rvectors) ? $tableentry$186$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$187$.rvectors) ? $tableentry$187$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$188$.rvectors) ? $tableentry$188$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$189$.rvectors) ? $tableentry$189$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$190$.rvectors) ? $tableentry$190$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$191$.rvectors) ? $tableentry$191$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$192$.rvectors) ? $tableentry$192$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$193$.rvectors) ? $tableentry$193$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$194$.rvectors) ? $tableentry$194$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$195$.rvectors) ? $tableentry$195$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$196$.rvectors) ? $tableentry$196$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$197$.rvectors) ? $tableentry$197$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$198$.rvectors) ? $tableentry$198$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$199$.rvectors) ? $tableentry$199$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$200$.rvectors) ? $tableentry$200$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$201$.rvectors) ? $tableentry$201$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$202$.rvectors) ? $tableentry$202$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$203$.rvectors) ? $tableentry$203$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$204$.rvectors) ? $tableentry$204$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$205$.rvectors) ? $tableentry$205$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$206$.rvectors) ? $tableentry$206$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$207$.rvectors) ? $tableentry$207$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$208$.rvectors) ? $tableentry$208$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$209$.rvectors) ? $tableentry$209$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$210$.rvectors) ? $tableentry$210$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$211$.rvectors) ? $tableentry$211$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$212$.rvectors) ? $tableentry$212$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$213$.rvectors) ? $tableentry$213$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$214$.rvectors) ? $tableentry$214$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$215$.rvectors) ? $tableentry$215$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$216$.rvectors) ? $tableentry$216$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$217$.rvectors) ? $tableentry$217$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$218$.rvectors) ? $tableentry$218$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$219$.rvectors) ? $tableentry$219$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$220$.rvectors) ? $tableentry$220$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$221$.rvectors) ? $tableentry$221$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$222$.rvectors) ? $tableentry$222$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$223$.rvectors) ? $tableentry$223$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$224$.rvectors) ? $tableentry$224$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$225$.rvectors) ? $tableentry$225$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$226$.rvectors) ? $tableentry$226$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$227$.rvectors) ? $tableentry$227$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$228$.rvectors) ? $tableentry$228$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$229$.rvectors) ? $tableentry$229$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$230$.rvectors) ? $tableentry$230$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$231$.rvectors) ? $tableentry$231$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$232$.rvectors) ? $tableentry$232$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$233$.rvectors) ? $tableentry$233$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$234$.rvectors) ? $tableentry$234$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$235$.rvectors) ? $tableentry$235$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$236$.rvectors) ? $tableentry$236$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$237$.rvectors) ? $tableentry$237$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$238$.rvectors) ? $tableentry$238$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$239$.rvectors) ? $tableentry$239$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$240$.rvectors) ? $tableentry$240$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$241$.rvectors) ? $tableentry$241$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$242$.rvectors) ? $tableentry$242$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$243$.rvectors) ? $tableentry$243$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$244$.rvectors) ? $tableentry$244$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$245$.rvectors) ? $tableentry$245$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$246$.rvectors) ? $tableentry$246$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$247$.rvectors) ? $tableentry$247$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$248$.rvectors) ? $tableentry$248$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$249$.rvectors) ? $tableentry$249$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$250$.rvectors) ? $tableentry$250$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$251$.rvectors) ? $tableentry$251$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$252$.rvectors) ? $tableentry$252$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$253$.rvectors) ? $tableentry$253$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$254$.rvectors) ? $tableentry$254$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); +LONG(DEFINED($tableentry$255$.rvectors) ? $tableentry$255$.rvectors : DEFINED($tableentry$default$.rvectors) ? $tableentry$default$.rvectors : 0xFFFFFFFF); diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowlvl.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowlvl.c new file mode 100644 index 000000000..b17b9c02b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowlvl.c @@ -0,0 +1,126 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowlvl.c +* Description : Functions to support stream I/O to the E1 virtual Console +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_E1_DBG_PORT (*(volatile st_dbg_t R_BSP_EVENACCESS_SFR *)0x84080) +#define BSP_PRV_TXFL0EN (0x00000100) /* debug tx flow control bit */ +#define BSP_PRV_RXFL0EN (0x00001000) /* debug RX flow control bit */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef struct +{ + uint32_t tx_data; /* Debug Virtual Console TX data */ + char wk1[12]; /* spacer */ + uint32_t rx_data; /* Debug Virtual Console RX data */ + char wk2[44]; /* spacer */ + uint32_t dbgstat; /* Debug Virtual Console Status */ +} st_dbg_t; + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +#if BSP_CFG_USER_CHARPUT_ENABLED != 0 +/* If user has indicated they want to provide their own charput function then this is the prototype. */ +void BSP_CFG_USER_CHARPUT_FUNCTION(char output_char); +#endif + +#if BSP_CFG_USER_CHARGET_ENABLED != 0 +/* If user has indicated they want to provide their own charget function then this is the prototype. */ +char BSP_CFG_USER_CHARGET_FUNCTION(void); +#endif + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: charput +* Description : Outputs a character on a serial port +* Arguments : character to output +* Return Value : none +***********************************************************************************************************************/ +void charput (char output_char) +{ + /* If user has provided their own charput() function, then call it. */ +#if BSP_CFG_USER_CHARPUT_ENABLED == 1 + BSP_CFG_USER_CHARPUT_FUNCTION(output_char); +#else + /* Wait for transmit buffer to be empty */ + /* WAIT_LOOP */ + while(0 != (BSP_PRV_E1_DBG_PORT.dbgstat & BSP_PRV_TXFL0EN)) + { + /* do nothing */ + R_BSP_NOP(); + } + + /* Write the character out */ + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_E1_DBG_PORT.tx_data = (int32_t)output_char; +#endif +} /* End of function charput() */ + +/*********************************************************************************************************************** +* Function Name: charget +* Description : Gets a character on a serial port +* Arguments : none +* Return Value : received character +***********************************************************************************************************************/ +char charget (void) +{ + /* If user has provided their own charget() function, then call it. */ +#if BSP_CFG_USER_CHARGET_ENABLED == 1 + return BSP_CFG_USER_CHARGET_FUNCTION(); +#else + /* Wait for rx buffer buffer to be ready */ + /* WAIT_LOOP */ + while(0 == (BSP_PRV_E1_DBG_PORT.dbgstat & BSP_PRV_RXFL0EN)) + { + /* do nothing */ + R_BSP_NOP(); + } + + /* Read data, send back up */ + /* Casting is valid because it matches the type to the retern value. */ + return (char)BSP_PRV_E1_DBG_PORT.rx_data; +#endif +} /* End of function charget() */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowlvl.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowlvl.h new file mode 100644 index 000000000..9ca8db79d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowlvl.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowlvl.h +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef LOWLVL_H +#define LOWLVL_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/* Output one character to standard output (the E1 Virtual Console or a serial port via user own charput function) */ +void charput (char output_char); + +/* Input one character from standard input (the E1 Virtual Console or a serial port via user own charget function) */ +char charget (void); + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowsrc.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowsrc.c new file mode 100644 index 000000000..36078db9c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowsrc.c @@ -0,0 +1,571 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowsrc.c +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) +#include +#include +#endif /* defined(__CCRX__) */ +#include "r_bsp_common.h" +#include "r_bsp_config.h" +#include "lowlvl.h" +#include "lowsrc.h" + + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/* Do not include this file if stdio is disabled in r_bsp_config. */ +#if BSP_CFG_IO_LIB_ENABLE == 1 + +#if defined(__CCRX__) + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/*Number of I/O Stream*/ +#define BSP_PRV_IOSTREAM (20) + +/* file number */ +#define BSP_PRV_STDIN (0) /* Standard input (console) */ +#define BSP_PRV_STDOUT (1) /* Standard output (console) */ +#define BSP_PRV_STDERR (2) /* Standard error output (console) */ + +#define BSP_PRV_FLMIN (0) /* Minimum file number */ +#define BSP_PRV_MOPENR (0x1) +#define BSP_PRV_MOPENW (0x2) +#define BSP_PRV_MOPENA (0x4) +#define BSP_PRV_MTRUNC (0x8) +#define BSP_PRV_MCREAT (0x10) +#define BSP_PRV_MBIN (0x20) +#define BSP_PRV_MEXCL (0x40) +#define BSP_PRV_MALBUF (0x40) +#define BSP_PRV_MALFIL (0x80) +#define BSP_PRV_MEOF (0x100) +#define BSP_PRV_MERR (0x200) +#define BSP_PRV_MLBF (0x400) +#define BSP_PRV_MNBF (0x800) +#define BSP_PRV_MREAD (0x1000) +#define BSP_PRV_MWRITE (0x2000) +#define BSP_PRV_MBYTE (0x4000) +#define BSP_PRV_MWIDE (0x8000) +/* File Flags */ +#define BSP_PRV_O_RDONLY (0x0001) /* Read only */ +#define BSP_PRV_O_WRONLY (0x0002) /* Write only */ +#define BSP_PRV_O_RDWR (0x0004) /* Both read and Write */ +#define BSP_PRV_O_CREAT (0x0008) /* A file is created if it is not existed */ +#define BSP_PRV_O_TRUNC (0x0010) /* The file size is changed to 0 if it is existed. */ +#define BSP_PRV_O_APPEND (0x0020) /* The position is set for next reading/writing + 0: Top of the file 1: End of file */ + +/* Special character code */ +#define BSP_PRV_CR (0x0d) /* Carriage return */ +#define BSP_PRV_LF (0x0a) /* Line feed */ + +#define BSP_PRV_FPATH_STDIN "C:\\stdin" +#define BSP_PRV_FPATH_STDOUT "C:\\stdout" +#define BSP_PRV_FPATH_STDERR "C:\\stderr" + +#ifdef _REENTRANT +// For Reentrant Library (generated lbgrx with -reent option) +#define BSP_PRV_MALLOC_SEM (1) /* Semaphore No. for malloc */ +#define BSP_PRV_STRTOK_SEM (2) /* Semaphore No. for strtok */ +#define BSP_PRV_FILE_TBL_SEM (3) /* Semaphore No. for fopen */ +#define BSP_PRV_MBRLEN_SEM (4) /* Semaphore No. for mbrlen */ +#define BSP_PRV_FPSWREG_SEM (5) /* Semaphore No. for FPSW register */ +#define BSP_PRV_FILES_SEM (6) /* Semaphore No. for _Files */ +#define BSP_PRV_SEMSIZE (26) /* BSP_PRV_FILES_SEM + _nfiles (assumed _nfiles=20) */ + +#define BSP_PRV_TRUE (1) +#define BSP_PRV_FALSE (0) +#define BSP_PRV_OK (1) +#define BSP_PRV_NG (0) +#endif /* _REENTRANT */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern const long _nfiles; /* The number of files for input/output files */ +char flmod[BSP_PRV_IOSTREAM]; /* The location for the mode of opened file. */ + +unsigned char sml_buf[BSP_PRV_IOSTREAM]; + +FILE *_Files[BSP_PRV_IOSTREAM]; /* structure for FILE */ +char *env_list[] = { /* Array for environment variables(**environ) */ + "ENV1=temp01", + "ENV2=temp02", + "ENV9=end", + '\0' /* Terminal for environment variables */ +}; + +char **environ = env_list; + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +#ifdef _REENTRANT +static long sem_errno; +static int force_fail_signal_sem = BSP_PRV_FALSE; +static int semaphore[BSP_PRV_SEMSIZE]; +#endif /* _REENTRANT */ + +/*********************************************************************************************************************** +* Function Name: init_iolib +* Description : Initialize C library Functions, if necessary. Define USES_SIMIO on Assembler Option. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void init_iolib(void) +{ + /* A file for standard input/output is opened or created. Each FILE + * structure members are initialized by the library. Each _Buf member + * in it is re-set the end of buffer pointer. + */ + + /* Initializations of File Stream Table */ + _Files[0] = stdin; + _Files[1] = stdout; + _Files[2] = stderr; + + /* Standard Input File */ + if( freopen( BSP_PRV_FPATH_STDIN, "r", stdin ) == NULL ) + { + stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */ + } + stdin->_Mode = BSP_PRV_MOPENR; /* Read only attribute */ + stdin->_Mode |= BSP_PRV_MNBF; /* Non-buffering for data */ + stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */ + + /* Standard Output File */ + if( freopen( BSP_PRV_FPATH_STDOUT, "w", stdout ) == NULL ) + { + stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */ + } + stdout->_Mode |= BSP_PRV_MNBF; /* Non-buffering for data */ + stdout->_Bend = stdout->_Buf + 1; /* Re-set pointer to the end of buffer */ + + /* Standard Error File */ + if( freopen( BSP_PRV_FPATH_STDERR, "w", stderr ) == NULL ) + { + stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */ + } + stderr->_Mode |= BSP_PRV_MNBF; /* Non-buffering for data */ + stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */ +} /* End of function init_iolib() */ + +/*********************************************************************************************************************** +* Function Name: close_all +* Description : Colses the file +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void close_all(void) +{ + long i; + + /* WAIT_LOOP */ + for( i=0; i < _nfiles; i++ ) + { + /* Checks if the file is opened or not */ + if( _Files[i]->_Mode & (BSP_PRV_MOPENR | BSP_PRV_MOPENW | BSP_PRV_MOPENA ) ) + { + fclose( _Files[i] ); /* Closes the file */ + } + } +} /* End of function close_all() */ + +/*********************************************************************************************************************** +* Function Name: open +* Description : file open +* Arguments : name - File name +* mode - Open mode +* flg - Open flag +* Return Value : File number (Pass) +* -1 (Failure) +***********************************************************************************************************************/ +long open(const char *name, long mode, long flg) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(flg); + + if( 0 == strcmp( name, BSP_PRV_FPATH_STDIN ) ) /* Standard Input file? */ + { + if( 0 == ( mode & BSP_PRV_O_RDONLY ) ) + { + return -1; + } + flmod[BSP_PRV_STDIN] = mode; + return BSP_PRV_STDIN; + } + else if( 0 == strcmp( name, BSP_PRV_FPATH_STDOUT ) ) /* Standard Output file? */ + { + if( 0 == ( mode & BSP_PRV_O_WRONLY ) ) + { + return -1; + } + flmod[BSP_PRV_STDOUT] = mode; + return BSP_PRV_STDOUT; + } + else if( 0 == strcmp(name, BSP_PRV_FPATH_STDERR ) ) /* Standard Error file? */ + { + if( 0 == ( mode & BSP_PRV_O_WRONLY ) ) + { + return -1; + } + flmod[BSP_PRV_STDERR] = mode; + return BSP_PRV_STDERR; + } + else + { + return -1; /*Others */ + } +} /* End of function open() */ + +/*********************************************************************************************************************** +* Function Name: close +* Description : dummy +* Arguments : fileno - File number +* Return Value : 1 +***********************************************************************************************************************/ +long close(long fileno) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + return 1; +} /* End of function close() */ + +/*********************************************************************************************************************** +* Function Name: write +* Description : Data write +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to write +* Return Value : Number of write characters (Pass) +* -1 (Failure) +***********************************************************************************************************************/ +long write(long fileno, const unsigned char *buf, long count) +{ + long i; /* A variable for counter */ + unsigned char c; /* An output character */ + + /* Checking the mode of file , output each character + * Checking the attribute for Write-Only, Read-Only or Read-Write + */ + if((flmod[fileno]&BSP_PRV_O_WRONLY) || (flmod[fileno]&BSP_PRV_O_RDWR)) + { + if( BSP_PRV_STDIN == fileno ) + { + return -1; /* Standard Input */ + } + else if( (BSP_PRV_STDOUT == fileno) || (BSP_PRV_STDERR == fileno) ) /* Standard Error/output */ + { + /* WAIT_LOOP */ + for( i = count; i > 0; --i ) + { + c = *buf++; + charput(c); + } + return count; /*Return the number of written characters */ + } + else + { + return -1; /* Incorrect file number */ + } + } + else + { + return -1; /* An error */ + } +} /* End of function write() */ + +/*********************************************************************************************************************** +* Function Name: read +* Description : Data read +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to read +* Return Value : Number of read characters (Pass) +* -1 (Failure) +***********************************************************************************************************************/ +long read(long fileno, unsigned char *buf, long count) +{ + long i; + + /* Checking the file mode with the file number, each character is input and stored the buffer */ + + if((flmod[fileno]&BSP_PRV_MOPENR) || (flmod[fileno]&BSP_PRV_O_RDWR)) + { + /* WAIT_LOOP */ + for(i = count; i > 0; i--) + { + *buf = charget(); + if(BSP_PRV_CR == (*buf)) + { + *buf = BSP_PRV_LF; /* Replace the new line character */ + } + buf++; + } + return count; + } + else + { + return -1; + } +} /* End of function read() */ + +/*********************************************************************************************************************** +* Function Name: lseek +* Description : dummy +* Arguments : fileno - File number +* offset - Offset indicating reading / writing position +* base - Offset starting point +* Return Value : -1L +***********************************************************************************************************************/ +long lseek(long fileno, long offset, long base) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(offset); + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(base); + + return -1L; +} /* End of function lseek() */ + +#ifdef _REENTRANT +/*********************************************************************************************************************** +* Function Name: errno_addr +* Description : Acquisition of errno address +* Arguments : none +* Return Value : errno address +***********************************************************************************************************************/ +long *errno_addr(void) +{ + /* Return the errno address of the current task */ + return (&sem_errno); +} + +/*********************************************************************************************************************** +* Function Name: wait_sem +* Description : Defines the specified numbers of semaphores +* Arguments : semnum - Semaphore ID +* Return Value : BSP_PRV_OK(=1) (Normal) +* BSP_PRV_NG(=0) (Error) +***********************************************************************************************************************/ +long wait_sem(long semnum) /* Semaphore ID */ +{ + if((0 < semnum) && (semnum < BSP_PRV_SEMSIZE)) { + if(semaphore[semnum] == BSP_PRV_FALSE) { + semaphore[semnum] = BSP_PRV_TRUE; + return(BSP_PRV_OK); + } + } + return(BSP_PRV_NG); +} + +/*********************************************************************************************************************** +* Function Name: signal_sem +* Description : Releases the specified numbers of semaphores +* Arguments : semnum - Semaphore ID +* Return Value : BSP_PRV_OK(=1) (Normal) +* BSP_PRV_NG(=0) (Error) +***********************************************************************************************************************/ +long signal_sem(long semnum) /* Semaphore ID */ +{ + if(!force_fail_signal_sem) { + if((0 <= semnum) && (semnum < BSP_PRV_SEMSIZE)) { + if( semaphore[semnum] == BSP_PRV_TRUE ) { + semaphore[semnum] = BSP_PRV_FALSE; + return(BSP_PRV_OK); + } + } + } + return(BSP_PRV_NG); +} +#endif /* _REENTRANT */ + +#endif /* defined(__CCRX__) */ + +#endif /* BSP_CFG_IO_LIB_ENABLE */ + +#if defined(__GNUC__) +/*********************************************************************************************************************** +* Function Name: write +* Description : Data write (for GNURX+NEWLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to write +* Return Value : Number of write characters (Pass) +***********************************************************************************************************************/ +int write(int fileno, char *buf, int count) +{ + int i; + char c; + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + /* WAIT_LOOP */ + for(i = count; i > 0; --i) + { + c = *buf++; + charput(c); + } + + return count; +} + +/*********************************************************************************************************************** +* Function Name: read +* Description : Data read (for GNURX+NEWLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to read +* Return Value : 1 (Pass) +***********************************************************************************************************************/ +int read(int fileno, char *buf, int count) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + INTERNAL_NOT_USED(count); + + *buf = charget(); + return 1; +} + +/*********************************************************************************************************************** +* Function Name: _write +* Description : Data write (for GNURX+OPTLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to write +* Return Value : Number of write characters (Pass) +***********************************************************************************************************************/ +int _write(int fileno, char *buf, int count) +{ + int i; + char c; + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + /* WAIT_LOOP */ + for(i = count; i > 0; --i) + { + c = *buf++; + charput(c); + } + + return count; +} + +/*********************************************************************************************************************** +* Function Name: read +* Description : Data read (for GNURX+OPTLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to read +* Return Value : 1 (Pass) +***********************************************************************************************************************/ +int _read(int fileno, char *buf, int count) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + INTERNAL_NOT_USED(count); + + *buf = charget(); + return 1; +} + +/*********************************************************************************************************************** +* Function Name: close +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void close (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +/*********************************************************************************************************************** +* Function Name: fstat +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void fstat (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +/*********************************************************************************************************************** +* Function Name: isatty +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void isatty (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +/*********************************************************************************************************************** +* Function Name: lseek +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void lseek (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +#endif /* defined(__GNUC__) */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowsrc.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowsrc.h new file mode 100644 index 000000000..15b2426fd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/lowsrc.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowsrc.h +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOWSRC_H +#define LOWSRC_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__CCRX__) +void init_iolib(void); +void close_all(void); +long open(const char *name, long mode, long flg); +long close(long fileno); +long write(long fileno, const unsigned char *buf, long count); +long read(long fileno, unsigned char *buf, long count); +long lseek(long fileno, long offset, long base); +#ifdef _REENTRANT +long *errno_addr(void) +long wait_sem(long semnum) +long signal_sem(long semnum) +#endif +#endif /* defined(__CCRX__) */ + +#if defined(__GNUC__) +int write(int fileno, char *buf, int count); +int read(int fileno, char *buf, int count); +int _write(int fileno, char *buf, int count); +int _read(int fileno, char *buf, int count); +void close(void); +void fstat(void); +void isatty(void); +void lseek(void); +#endif /* defined(__GNUC__) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/mcu_locks.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/mcu_locks.c new file mode 100644 index 000000000..4fb5c24b3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/mcu_locks.c @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.c +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Used for getting MCU information to accurately reflect available MCU resources. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +/* Below are locks for controlling access to MCU resources. */ +BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[BSP_NUM_LOCKS]; + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c new file mode 100644 index 000000000..ab902b064 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c @@ -0,0 +1,225 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.c +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 26.03.2014 1.10 Added R_BSP_SoftwareDelay() function +* : 03.09.2014 1.20 Corrected R_BSP_SoftwareDelay() timing when using an RX64M +* : 30.09.2015 1.30 Added RX23T +* : 01.02.2016 1.40 Added RX24T +* Changed the value of the following macro definition. +* - OVERHEAD_CYCLES +* - OVERHEAD_CYCLES_64 +* : 29.02.2016 1.50 Added RX230 +* : 01.10.2016 1.60 Added RX65N +* : 22.08.2016 1.70 Added RX24U +* : 15.05.2017 1.80 Changed method of selecting the number of CPU cycles required to execute +* the delayWait() loop. +* : 27.07.2018 1.90 Changed the value of the following macro definition, because added RX66T. +* - CPU_CYCLES_PER_LOOP +* : 28.02.2019 2.00 Deleted the following definition. +* (The following definition moved to the common file (mcu_info.h).) +* - CPU_CYCLES_PER_LOOP +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_OVERHEAD_CYCLES +* - BSP_PRV_OVERHEAD_CYCLES_64 +* - BSP_PRV_CKSEL_LOCO +* Renamed following function. +* - delay_wait +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get information about current board and MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_OVERHEAD_CYCLES (2) /* R_BSP_SoftwareDelay() overhead per call */ +#define BSP_PRV_OVERHEAD_CYCLES_64 (2) /* R_BSP_SoftwareDelay() overhead per call using 64-bit ints */ + +#define BSP_PRV_CKSEL_LOCO (0x0) /* SCKCR3 register setting for LOCO */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_GetVersion + ******************************************************************************************************************//** + * @brief Returns the current version of the r_bsp. + * @return Version of the r_bsp. + * @details This function will return the version of the currently installed r_bsp. The version number is encoded + * where the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For + * example, Version 4.25 would be returned as 0x00040019. + */ +uint32_t R_BSP_GetVersion (void) +{ + /* These version macros are defined in platform.h. */ + return ((((uint32_t)R_BSP_VERSION_MAJOR) << 16) | (uint32_t)R_BSP_VERSION_MINOR); +} /* End of function R_BSP_GetVersion() */ + + +/*********************************************************************************************************************** +* Function Name: delay_wait +* Description : This asm loop executes a known number (5) of CPU cycles. If a value of '4' is passed +* in as an argument, then this function would consume 20 CPU cycles before returning. +* Arguments : loop_cnt - A single 32-bit value is provided as the number of loops to execute. +* Return Value : None +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(delay_wait) +void delay_wait (unsigned long loop_cnt) +{ + R_BSP_ASM_INTERNAL_USED(loop_cnt) + R_BSP_ASM_BEGIN + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_NEXT(0) ) + R_BSP_ASM( NOP ) + R_BSP_ASM_LAB(0: ) + R_BSP_ASM( NOP ) + R_BSP_ASM( SUB #01H, R1 ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_PREV(0) ) + R_BSP_ASM_END +} /* End of function delay_wait() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_GetIClkFreqHz + ******************************************************************************************************************//** + * @brief Returns the system clock frequency. + * @return System clock frequency specified by the r_bsp. + * @details This function returns the system clock frequency. For example, when the system clock is set to 120 MHz in + * r_bsp_config_h and the r_bsp has completed to specify the clock setting, then even if the user changed the system + * clock frequency to 60 MHz, the return value is '60000000'. + */ +uint32_t R_BSP_GetIClkFreqHz(void) +{ + return get_iclk_freq_hz(); // Get the MCU specific ICLK frequency +} /* End of function R_BSP_GetIClkFreqHz() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareDelay + ******************************************************************************************************************//** + * @brief Delay the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' for the units specified. + * @retval true True if delay executed. + * @retval false False if delay/units combination resulted in overflow/underflow. + * @details This is function that may be called for all MCU targets to implement a specific wait time. + * The actual delay time is plus the overhead at a specified duration. The overhead changes under the influence of + * the compiler, operating frequency and ROM cache. When the operating frequency is low, or the specified duration in + * units of microsecond level, please note that the error becomes large. + */ +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units) +{ + volatile uint32_t iclk_rate; + volatile uint32_t delay_cycles; + volatile uint32_t loop_cnt; + volatile uint64_t delay_cycles_64; + volatile uint64_t loop_cnt_64; + +#ifdef BSP_CFG_PARAM_CHECKING_ENABLE + if ((BSP_DELAY_MICROSECS != units) && (BSP_DELAY_MILLISECS != units) && (BSP_DELAY_SECS != units)) + { + return(false); + } +#endif + + iclk_rate = R_BSP_GetIClkFreqHz(); /* Get the current ICLK frequency */ + + /* + * In order to handle all possible combinations of delay/ICLK it is necessary to use 64-bit + * integers (not all MCUs have floating point support). However, there is no native hw support + * for 64 bit integers so it requires many more clock cycles. This is not an issue if the + * requested delay is long enough and the ICLK is fast, but for delays in the low microseconds + * and/or a slow ICLK we use 32 bit integers to reduce the overhead cycles of this function + * by approximately a third and stand the best chance of achieving the requested delay. + */ + if ( (BSP_DELAY_MICROSECS == units) && + (delay <= (0xFFFFFFFFUL / iclk_rate)) ) /* Ensure (iclk_rate * delay) will not exceed 32 bits */ + { + delay_cycles = ((iclk_rate * delay) / units); + + if (delay_cycles > BSP_PRV_OVERHEAD_CYCLES) + { + delay_cycles -= BSP_PRV_OVERHEAD_CYCLES; + } + else + { + delay_cycles = 0; + } + + loop_cnt = delay_cycles / CPU_CYCLES_PER_LOOP; + + if (0 == loop_cnt) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + } + else + { + /* Casting is valid because it matches the type to the right side or argument. */ + delay_cycles_64 = (((uint64_t)iclk_rate * (uint64_t)delay) / units); + + if (delay_cycles_64 > BSP_PRV_OVERHEAD_CYCLES_64) + { + delay_cycles_64 -= BSP_PRV_OVERHEAD_CYCLES_64; + } + else + { + delay_cycles = 0; + } + + loop_cnt_64 = delay_cycles_64 / CPU_CYCLES_PER_LOOP; + + if ((loop_cnt_64 > 0xFFFFFFFFUL) || (0 == loop_cnt_64)) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + + /* Casting is valid because it matches the type to the right side or argument. */ + loop_cnt = (uint32_t)loop_cnt_64; + } + + delay_wait(loop_cnt); + + return(true); +} /* End of function R_BSP_SoftwareDelay() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h new file mode 100644 index 000000000..f5146b7ce --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.h +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 25.06.2013 1.10 Now contains standard includes (stdint.h, stdbool.h, etc) as well as include for +* r_typedefs.h when needed. +* : 02.07.2013 1.11 Added #include for machine.h. +* : 10.02.2014 1.12 Changed minor version to '40'. +* : 24.03.2014 1.12 Changed minor version to '60'. +* : 14.04.2014 1.12 Added typedef for fit_callback_t. +* : 30.09.2015 1.13 Changed Major/Minor version to 3.00 +* : 30.09.2015 1.14 Changed Minor version to 3.01 +* : 01.12.2015 1.15 Changed Minor version to 3.10 +* : 01.02.2016 1.16 Changed Minor version to 3.20 +* : 29.02.2016 1.17 Changed Minor version to 3.30 +* : 13.04.2016 1.18 Changed Minor version to 3.31 +* : 01.10.2016 1.19 Changed Minor version to 3.40 +* : 04.11.2016 1.20 Changed Minor version to 3.50 +* : 15.05.2017 1.21 Changed Minor version to 3.60 +* : 01.11.2017 1.22 Changed Minor version to 3.70 +* : 01.12.2017 1.23 Changed Minor version to 3.71 +* : 01.07.2018 1.24 Changed Minor version to 3.80 +* : 27.07.2018 1.25 Changed Minor version to 3.90. +* : 31.08.2018 1.26 Changed Minor version to 3.91. +* : 31.10.2018 1.27 Changed Major/Minor version to 4.00. +* : 11.01.2019 1.28 Changed Minor version to 4.01. +* : 28.02.2019 1.29 Changed Major version to 5.00. +* Added the following macro definition. +* - INTERNAL_NOT_USED(p) +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 29.03.2019 1.30 Changed Minor version to 5.10. +* : 08.04.2019 1.31 Changed Minor version to 5.20. +* : 23.07.2019 1.32 Changed Minor version to 5.21. +* : 26.07.2019 1.33 Changed Minor version to 5.30. +* : 31.07.2019 1.34 Changed Minor version to 5.40. +* : 08.10.2019 1.35 Changed Minor version to 5.50. +* : 10.12.2019 1.36 Changed Minor version to 5.51. +* : 14.02.2020 1.37 Changed Minor version to 5.52. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* C99 (or later) is necessary because r_rx_compiler.h uses Pragma operator and variadic macros. + * This means that r_typedefs.h is not used in any case. */ +#if !defined(__cplusplus) && !defined(CPPAPP) +/* All implementation is C99 (or later) */ +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#include +#include +#include +#include +#else +#error "This version of FIT needs C99 (or later)." +#endif +#else /* defined(__cplusplus) || defined(CPPAPP) */ +/* Interface might be referred from C++ */ +#include +#include +#include +#include +#endif /* !defined(__cplusplus) && !defined(CPPAPP) */ + +#if defined(__CCRX__) || defined(__ICCRX__) +/* Intrinsic functions provided by compiler. */ +#include +#elif defined(__GNUC__) +/* No header file for intrinsic functions. */ +#else +/* PORT: Use header file for other compiler and port r_rx_compiler.h. */ +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_BSP_COMMON_H +#define R_BSP_COMMON_H + +/* Version Number of r_bsp. */ +#define R_BSP_VERSION_MAJOR (5) +#define R_BSP_VERSION_MINOR (52) + +/* This macro is used to suppress compiler messages about not only a parameter but also a auto variable not being used + * in a function. The nice thing about using this implementation is that it does not take any extra RAM or ROM. + * This macro is available for the followings: + * CC-RX's 'M0520826:Parameter "XXXX" was never referenced' + * CC-RX's 'W0520550:Variable "XXXX" was set but never used' + * GNURX's 'unused parameter 'XXXX' [-Wunused-parameter]' + * GNURX's 'variable 'XXXX' set but not used [-Wunused-but-set-variable]' + * When the variable is declared as volatile, the '&' can be applied like 'R_INTERNAL_NOT_USED(&volatile_variable);'. + */ +#define INTERNAL_NOT_USED(p) ((void)(p)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available delay units. */ +typedef enum +{ + BSP_DELAY_MICROSECS = 1000000, // Requested delay amount is in microseconds + BSP_DELAY_MILLISECS = 1000, // Requested delay amount is in milliseconds + BSP_DELAY_SECS = 1 // Requested delay amount is in seconds +} bsp_delay_units_t; + +/* Easy to use typedef for FIT module callback functions. */ +typedef void (*fit_callback_t)(void *p_args); + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t R_BSP_GetVersion(void); +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +uint32_t R_BSP_GetIClkFreqHz(void); + +/* End of multiple inclusion prevention macro */ +#endif /* R_BSP_COMMON_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c new file mode 100644 index 000000000..b575b5736 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c @@ -0,0 +1,672 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.c +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 3.10 Added the API function(R_BSP_SoftwareReset). +* Modified comment of API function to Doxygen style. +* Added the vbatt_voltage_stability_wait function. +* Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +* : 31.07.2019 3.11 Deleted the compile condition for R_BSP_SoftwareReset. +* : 08.10.2019 3.12 Changed the following functions. +* - R_BSP_InterruptsDisable +* - R_BSP_InterruptsEnable +* - R_BSP_CpuInterruptLevelWrite +* : 10.12.2019 3.13 Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500) +#endif + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/* The macro definition for combinations where settings of USBVON bit conflict. */ +#define BSP_PRV_USBVON_CONFLICT (BSP_VOL_USB_POWEROFF | BSP_VOL_USB_POWERON) +/* The macro definition for combinations where settings of PGAVLS bit conflict. */ +#define BSP_PRV_PGAVLS_CONFLICT (BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT | BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT) +/* The macro definition for combinations where settings of RICVLS bit conflict. */ +#define BSP_PRV_RICVLS_CONFLICT (BSP_VOL_RIIC_4_5V_OROVER | BSP_VOL_RIIC_UNDER_4_5V) +/* Bit number of VOLSR register. */ +#define BSP_PRV_VOLSR_RICVLS_BIT_NUM (7) +#define BSP_PRV_VOLSR_PGAVLS_BIT_NUM (6) +#define BSP_PRV_VOLSR_USBVON_BIT_NUM (2) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Used for holding reference counters for protection bits. */ +static volatile uint16_t s_protect_counters[BSP_REG_PROTECT_TOTAL_ITEMS]; + +/* Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t s_prcr_masks[BSP_REG_PROTECT_TOTAL_ITEMS-1] = +{ +#ifdef BSP_MCU_RCPC_PRC0 + 0x0001, /* PRC0. */ +#endif +#ifdef BSP_MCU_RCPC_PRC1 + 0x0002, /* PRC1. */ +#endif +#ifdef BSP_MCU_RCPC_PRC2 + 0x0004, /* PRC2. */ +#endif +#ifdef BSP_MCU_RCPC_PRC3 + 0x0008, /* PRC3. */ +#endif +}; +#endif + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsDisable + ******************************************************************************************************************//** + * @brief Globally disables interrupts. + * @details This function globally disables interrupts. This is performed by clearing the 'I' bit in the CPU's + * Processor Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsDisable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to clear the I flag. */ + R_BSP_CLRPSW_I(); + } + +} /* End of function R_BSP_InterruptsDisable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsEnable + ******************************************************************************************************************//** + * @brief Globally enable interrupts. + * @details This function globally enables interrupts. This is performed by setting the 'I' bit in the CPU's Processor + * Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsEnable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to set the I flag. */ + R_BSP_SETPSW_I(); + } + +} /* End of function R_BSP_InterruptsEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelRead + ******************************************************************************************************************//** + * @brief Reads the CPU's Interrupt Priority Level. + * @return The CPU's Interrupt Priority Level. + * @details This function reads the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. + */ +uint32_t R_BSP_CpuInterruptLevelRead (void) +{ + /* Use the compiler intrinsic function to read the CPU IPL. */ + uint32_t psw_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + psw_value = (uint32_t)R_BSP_GET_PSW(); + psw_value = psw_value & 0x0f000000; + psw_value = psw_value >> 24; + + return psw_value; +} /* End of function R_BSP_CpuInterruptLevelRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelWrite + ******************************************************************************************************************//** + * @brief Writes the CPU's Interrupt Priority Level. + * @param[in] level The level to write to the CPU's IPL. + * @retval true Successful, CPU's IPL has been written. + * @retval false Failure, provided 'level' has invalid IPL value or called when the CPU is in User Mode. + * @details This function writes the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. This function does check to make sure that the IPL being written is valid. + * The maximum and minimum valid settings for the CPU IPL are defined in mcu_info.h using the BSP_MCU_IPL_MAX and + * BSP_MCU_IPL_MIN macros. + * @note The CPU's IPL can only be modified by the user when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does not control IPL and return false. + */ +bool R_BSP_CpuInterruptLevelWrite (uint32_t level) +{ + bool ret; + uint32_t pmode; + + /* The R_BSP_SET_IPL() function use the MVTIPL instruction. + The MVTIPL instruction needs to set an immediate value to src. */ + + ret = false; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + ret = true; + + /* Use the compiler intrinsic function to set the CPU IPL. */ + switch (level) + { + case (0): + + /* IPL = 0 */ + R_BSP_SET_IPL(0); + break; + + case (1): + + /* IPL = 1 */ + R_BSP_SET_IPL(1); + break; + + case (2): + + /* IPL = 2 */ + R_BSP_SET_IPL(2); + break; + + case (3): + + /* IPL = 3 */ + R_BSP_SET_IPL(3); + break; + + case (4): + + /* IPL = 4 */ + R_BSP_SET_IPL(4); + break; + + case (5): + + /* IPL = 5 */ + R_BSP_SET_IPL(5); + break; + + case (6): + + /* IPL = 6 */ + R_BSP_SET_IPL(6); + break; + + case (7): + + /* IPL = 7 */ + R_BSP_SET_IPL(7); + break; + + #if 7 < BSP_MCU_IPL_MAX + case (8): + + /* IPL = 8 */ + R_BSP_SET_IPL(8); + break; + + case (9): + + /* IPL = 9 */ + R_BSP_SET_IPL(9); + break; + + case (10): + + /* IPL = 10 */ + R_BSP_SET_IPL(10); + break; + + case (11): + + /* IPL = 11 */ + R_BSP_SET_IPL(11); + break; + + case (12): + + /* IPL = 12 */ + R_BSP_SET_IPL(12); + break; + + case (13): + + /* IPL = 13 */ + R_BSP_SET_IPL(13); + break; + + case (14): + + /* IPL = 14 */ + R_BSP_SET_IPL(14); + break; + + case (15): + + /* IPL = 15 */ + R_BSP_SET_IPL(15); + break; + #endif /* BSP_MCU_IPL_MAX */ + + default: + ret = false; + break; + } + } + + return ret; +} /* End of function R_BSP_CpuInterruptLevelWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectEnable + ******************************************************************************************************************//** + * @brief Enables write protection for selected registers. + * @param[in] regs_to_protect Which registers to enable write protection for. + * @details This function enables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectDisable(), use counters for each entry in the bsp_reg_protect_t enum so + * that users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. An + * example of why this is needed is shown below in the Special Notes section below. + * @note + * (1) About why counters are needed. \n + * See Section 5.7 in the application note for details.\n + * (2) Notes on user mode \n + * The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control with + * this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* Is it safe to disable write access? */ + if (0 != s_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + s_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0 == s_protect_counters[regs_to_protect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_protect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + disable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) & (~s_prcr_masks[regs_to_protect])); + } + else + { + /* Enable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. It could be assumed that the B0WI bit is still cleared from a call to + protection disable function, but it is written here to make sure that the PFSWE bit always gets + cleared. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Disable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 0; + + /* Disable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 1; + } + } + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_protect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectDisable + ******************************************************************************************************************//** + * @brief Disables write protection for selected registers. + * @param[in] regs_to_unprotect Which registers to disable write protection for. + * @details This function disables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectEnable(), use counters for each entry in the bsp_reg_protect_t enum so that + * users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. + * @note The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control + * with this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* If this is first entry then disable protection. */ + if (0 == s_protect_counters[regs_to_unprotect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_unprotect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. + Set lower bits to 1 to enable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) | s_prcr_masks[regs_to_unprotect]); + } + else + { + /* Disable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Enable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 1; + } + } + + /* Increment the protect counter */ + s_protect_counters[regs_to_unprotect]++; + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_unprotect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectDisable() */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/********************************************************************************************************************** + * Function Name: R_BSP_VoltageLevelSetting + ******************************************************************************************************************//** + * @brief This API function is used excessively with the RX66T and RX72T. It makes settings to the voltage level + * setting register (VOLSR) that are necessary in order to use the USB, AD, and RIIC peripheral modules. Call this + * function only when it is necessary to change the register settings. + * @param[in] ctrl_ptn Register Setting Patterns + * The following setting patterns cannot be selected at the same time. + * When specifying more than one pattern at the same time, use the "|" (OR) operator. + * - BSP_VOL_USB_POWEROFF and BSP_VOL_USB_POWERON + * - BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT and BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT + * - BSP_VOL_RIIC_4_5V_OROVER and BSP_VOL_RIIC_UNDER_4_5V + * + * BSP_VOL_USB_POWEROFF: Updates the USBVON bit to 0. + * + * BSP_VOL_USB_POWERON: Updates the USBVON bit to 1. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT: Updates the PGAVLS bit to 0. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT: Updates the PGAVLS bit to 1. + * + * BSP_VOL_RIIC_4_5V_OROVER: Updates the RICVLS bit to 0. + * + * BSP_VOL_RIIC_UNDER_4_5V: Updates the RICVLS bit to 1. + * @retval true Processing completed, register successfully updated. + * @retval false The function was called under the following conditions, so the register setting was not updated. + * - Setting patterns that cannot be selected at the same time were selected. + * - A setting pattern related to the USB was selected when the USB was not in the module stop state. + * - A setting pattern related to the AD was selected when the AD was not in the module stop state. + * - A setting pattern related to the RIIC was selected when the RIIC was not in the module stop state. + * @details This function initializes the voltage level setting register (VOLSR), which is necessary in order to use + * the USB, AD and RIIC peripheral modules. When specifying a setting pattern related to the USB, call this function + * before the USB is released from the module stop state. When specifying a setting pattern related to the AD, call + * this function before the AD (unit 0 and unit 1) is released from the module stop state. When specifying a setting + * pattern related to the RIIC, call this function before the RIIC is released from the module stop state. If the + * function is called with a setting pattern related to the USB specified after the USB is released from the module + * stop state, the function returns "false" as the return value and does not update the register settings. If the + * function is called with a setting pattern related to the AD specified after the AD (unit 0 and unit 1) is released + * from the module stop state, the function returns "false" as the return value and does not update the register + * settings. Finally, if the function is called with a setting pattern related to the RIIC specified after the RIIC is + * released from the module stop state, the function returns "false" as the return value and does not update the + * register settings. + */ +bool R_BSP_VoltageLevelSetting (uint8_t ctrl_ptn) +{ + uint8_t *p_volsr_addr; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* ---- CHECK ARGUMENTS ---- */ + if (BSP_PRV_USBVON_CONFLICT == (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + return false; + } + + if (BSP_PRV_PGAVLS_CONFLICT == (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + return false; + } + + if (BSP_PRV_RICVLS_CONFLICT == (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + return false; + } +#endif + + /* Check USB module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(USB0)) + { + return false; + } + } + + /* Check AD module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if((0 == MSTP(S12AD)) || (0 == MSTP(S12AD1))) + { + return false; + } + } + + /* Check RIIC module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(RIIC0)) + { + return false; + } + } + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_volsr_addr = (uint8_t *)&SYSTEM.VOLSR.BYTE; + + /* Updated the RICVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_RIIC_UNDER_4_5V)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_RIIC_4_5V_OROVER)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + /* Updated the PGAVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + /* Updated the USBVON bit. */ + if(0 != (ctrl_ptn & BSP_VOL_USB_POWERON)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_USB_POWEROFF)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + return true; +} /* End of function R_BSP_VoltageLevelSetting() */ +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareReset + ******************************************************************************************************************//** + * @details Reset the MCU by Software Reset. + */ +void R_BSP_SoftwareReset(void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + /* Protect off. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); +#endif + + /* Resets the MCU. */ + SYSTEM.SWRR = 0xA501; + + /* WAIT_LOOP */ + while(1) + { + R_BSP_NOP(); + } +} /* End of function R_BSP_SoftwareReset() */ + +/*********************************************************************************************************************** +* Function Name: bsp_register_protect_open +* Description : Initializes variables needed for register protection functionality. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_register_protect_open (void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + uint32_t i; + + /* Initialize reference counters to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_REG_PROTECT_TOTAL_ITEMS; i++) + { + s_protect_counters[i] = 0; + } +#else + /* No registers to protect. */ +#endif +} /* End of function bsp_register_protect_open() */ + +/*********************************************************************************************************************** +* Function Name: bsp_ram_initialize +* Description : Initialize ram variable. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_ram_initialize (void) +{ + uint32_t i; + + /* Initialize g_bsp_Locks to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_NUM_LOCKS; i++) + { + g_bsp_Locks[i].lock = 0; + } +} /* End of function bsp_ram_initialize() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c new file mode 100644 index 000000000..a72ade038 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c @@ -0,0 +1,1085 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.c +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.04.2019 1.01 Added process for Group IE0 interrupts. +* Added process for EXNMI interrupts. +* : 26.07.2019 1.10 Modified comment of API function to Doxygen style. +* Modified the following function for added function. +* - R_BSP_InterruptControl +* Added the following functions. +* - bsp_fit_interrupts_control +* - bsp_fit_interrupt_enable +* - bsp_fit_interrupt_disable +* Fixed coding style. +* : 08.10.2019 1.11 Added process for software interrupt. +* : 10.12.2019 1.12 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_FLOATING_POINT +/* Defines CV, CO, CZ, CU, CX, and CE bits. */ +#define BSP_PRV_FPU_CAUSE_FLAGS (0x000000FC) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* This array holds callback functions. */ +static void (* g_bsp_vectors[BSP_INT_SRC_TOTAL_ITEMS])(void * pdata); + +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata); + +#ifdef BSP_MCU_GROUP_INTERRUPT +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl); +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestEnable + ******************************************************************************************************************//** + * @brief Enable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Enable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector number + * of the argument, and set "1" to that bit. The macro defined in iodefine.h can be used to the setting of the + * argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestEnable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_SET(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestDisable + ******************************************************************************************************************//** + * @brief Disable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Disable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector + * number of the argument, and clear "0" to that bit. The macro defined in iodefine.h can be used to the setting of + * the argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestDisable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_CLEAR(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestDisable() */ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_open +* Description : Initialize callback function array. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_interrupt_open (void) +{ + uint32_t i; + + /* WAIT_LOOP */ + for (i = 0; i < BSP_INT_SRC_TOTAL_ITEMS; i++) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[i] = FIT_NO_FUNC; + } + +#ifdef BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT + /* Initialize mapped interrupts. */ + bsp_mapped_interrupt_open(); +#endif + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT1); +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT2); +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ +} /* End of function bsp_interrupt_open() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptWrite + ******************************************************************************************************************//** + * @brief Registers a callback function for an interrupt. + * @param[in] vector Which interrupt to register a callback for. + * @param[in] callback Pointer to function to call when interrupt occurs. + * @retval BSP_INT_SUCCESS Successful, callback has been registered. + * @retval BSP_INT_ERR_INVALID_ARG Invalid function address input, any previous function has been unregistered. + * @details This function registers a callback function for an interrupt. If FIT_NO_FUNC, NULL, or any other invalid + * function address is passed for the callback argument then any previously registered callbacks are unregistered. + * If one of the interrupts that is handled by this code is triggered then the interrupt handler will query this code + * to see if a valid callback function is registered. If one is found then the callback function will be called. + * If one is not found then the interrupt handler will clear the appropriate flag(s) and exit. If the user has a + * callback function registered and wishes to no longer handle the interrupt then the user should call this function + * again with FIT_NO_FUNC as the vector parameter. + * @note Use of FIT_NO_FUNC is preferred over NULL since access to the address defined by FIT_NO_FUNC will cause a + * bus error which is easy for the user to catch. NULL typically resolves to 0 which is a valid address on RX MCUs. + */ +bsp_int_err_t R_BSP_InterruptWrite (bsp_int_src_t vector, bsp_int_cb_t callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)callback == (uint32_t)NULL) || ((uint32_t)callback == (uint32_t)FIT_NO_FUNC)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[vector] = FIT_NO_FUNC; + } + else + { + g_bsp_vectors[vector] = callback; + } + + return err; +} /* End of function R_BSP_InterruptWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRead + ******************************************************************************************************************//** + * @brief Gets the callback for an interrupt if one is registered. + * @param[in] vector Which interrupt to read the callback for. + * @param[out] callback Pointer to where to store callback address. + * @retval BSP_INT_SUCCESS Successful, callback address has been returned. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @details This function returns the callback function address for an interrupt if one has been registered. If a + * callback function has not been registered then an error is returned and nothing is stored to the callback address. + */ +bsp_int_err_t R_BSP_InterruptRead (bsp_int_src_t vector, bsp_int_cb_t * callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)g_bsp_vectors[vector] == (uint32_t)NULL) || ((uint32_t)g_bsp_vectors[vector] == (uint32_t)FIT_NO_FUNC)) + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + else + { + *callback = g_bsp_vectors[vector]; + } + + return err; +} /* End of function R_BSP_InterruptRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptControl + ******************************************************************************************************************//** + * @brief Controls various interrupt operations. + * @param[in] vector Which interrupt to control for.\n + * If the interrupt control commands is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE or the BSP_INT_CMD_FIT_INTERRUPT_DISABLE + * commands, set BSP_INT_SRC_EMPTY to "vector" because no arguments are used. + * @param[in] cmd Interrupt control command. + * @param[in,out] pdata Pointer to the argument for each interrupt control command. Typecasted to void*. See typedef + * defines of bsp_int_ctrl_t. \n + * Most of the interrupt control commands do not need the argument and take FIT_NO_PTR for + * this parameter. If the interrupt control command is the BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command, set the + * interrupt priority level for group interrupts as the argument. If the interrupt control command is the + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE command, set the address of a variable for saving the current processor interrupt + * priority level in the argument. If the interrupt control command is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE command, + * set the address of a variable used in the BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + * @retval BSP_INT_SUCCESS Successful. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @retval BSP_INT_ERR_INVALID_ARG The command passed is invalid. + * @retval BSP_INT_ERR_UNSUPPORTED This processing is not supported. + * @retval BSP_INT_ERR_GROUP_STILL_ENABLED Group interrupt request remains enabled. + * @retval BSP_INT_ERR_INVALID_IPL Illegal IPL value input. + * @details This function controls the interrupt callback function call and enabling/disabling interrupts such as bus + * error interrupt, floating-point exception, NMI pin interrupt, and group interrupts, and enabling/disabling + * interrupts by controlling the Processor Interrupt Priority Level. When BSP_INT_CMD_GROUP_INTERRUPT_ENABLE is set as + * the interrupt control command, the interrupt request (IER) for group interrupts is enabled and also the interrupt + * priority level is set. The interrupt priority level set must be higher than the current level. When + * BSP_INT_CMD_GROUP_INTERRUPT_DISABLE is set as the interrupt control command, the interrupt request (IER) for group + * interrupts is disabled. Note that the interrupt request (IER) for group interrupts cannot be disabled as long as + * all interrupt requests (GEN) caused by grouped interrupt sources are disabled. When + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE is set as the interrupt control command, the current processor interrupt priority + * level (IPL) is saved to the address specified by pdata as an argument, and disables interrupts by controlling the + * IPL. The value of IPL to be set is the value of BSP_CFG_FIT_IPL_MAX. When BSP_INT_CMD_FIT_INTERRUPT_ENABLE is set + * as the interrupt control command, the interrupt is enabled by setting the value stored in the address specified by + * pdata to IPL. These two commands are valid only in supervisor mode. When BSP_INT_CMD_FIT_INTERRUPT_DISABLE and + * BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands are executed in user mode, Controlling IPL is not executed and an error + * code BSP_INT_ERR_UNSUPPORTED is returned. + * @note BSP_INT_CMD_FIT_INTERRUPT_DISABLE and BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands can be used to secure + * atomicity of critical sections. However, these commands are valid only in supervisor mode. When these commands are + * executed in user mode, atomicity is not to secure.\n + * See Section 5.15 in the application note for more information. + */ +bsp_int_err_t R_BSP_InterruptControl (bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata) +{ + bsp_int_err_t err; + bsp_int_cb_args_t cb_args; + + err = BSP_INT_SUCCESS; + +#ifdef BSP_MCU_GROUP_INTERRUPT + /* nothing */ +#else + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(pdata); +#endif + + switch (cmd) + { + case (BSP_INT_CMD_CALL_CALLBACK): + + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)g_bsp_vectors[vector] != (uint32_t)NULL) && ((uint32_t)g_bsp_vectors[vector] != (uint32_t)FIT_NO_FUNC)) + { + /* Fill in callback info. */ + cb_args.vector = vector; + + g_bsp_vectors[vector](&cb_args); + } + else + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + break; + + case (BSP_INT_CMD_INTERRUPT_ENABLE): + err = bsp_interrupt_enable_disable(vector, true); + break; + + case (BSP_INT_CMD_INTERRUPT_DISABLE): + err = bsp_interrupt_enable_disable(vector, false); + break; + +#ifdef BSP_MCU_GROUP_INTERRUPT + case (BSP_INT_CMD_GROUP_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_gr_int_enable_disable(vector, true, ((bsp_int_ctrl_t *)pdata)->ipl); + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + break; + + case (BSP_INT_CMD_GROUP_INTERRUPT_DISABLE): + err = bsp_gr_int_enable_disable(vector, false, 0); + break; +#endif + + case (BSP_INT_CMD_FIT_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(true, (bsp_int_ctrl_t *)pdata); + break; + + case (BSP_INT_CMD_FIT_INTERRUPT_DISABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(false, (bsp_int_ctrl_t *)pdata); + break; + + default: + err = BSP_INT_ERR_INVALID_ARG; + break; + } + + return err; +} /* End of function R_BSP_InterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_fit_interrupts_control +* Description : +* Arguments : enable - +* Whether to enable or disable the interrupt. +* pdata - +* Pointer to variable for saves ipl or restore ipl. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid argument input. +* BSP_INT_ERR_INVALID_IPL - +* Invalid IPL input. +* BSP_INT_ERR_UNSUPPORTED - +* This processing is not supported. (Executed in user mode.) +***********************************************************************************************************************/ +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata) +{ + bsp_int_err_t err; + uint32_t pmode; + bool ret; + uint32_t ipl_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + err = BSP_INT_SUCCESS; + + if (true == enable) + { + ipl_value = pdata->ipl; + } + else + { + /* Get the current Processor Interrupt Priority Level (IPL) and save IPL value. */ + pdata->ipl = R_BSP_CpuInterruptLevelRead(); + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + ipl_value = BSP_CFG_FIT_IPL_MAX; + } + + if (pdata->ipl < BSP_CFG_FIT_IPL_MAX) + { + ret = R_BSP_CpuInterruptLevelWrite(ipl_value); + if (false == ret) + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_UNSUPPORTED; + } + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_fit_interrupts_control() */ + +#ifdef BSP_MCU_GROUP_INTERRUPT +/*********************************************************************************************************************** +* Function Name: bsp_gr_int_enable_disable +* Description : Either enables or disables a group interrupt. If a group interrupt is called multiple times to be +* enabled then it will use the highest given IPL. A group interrupt will only be disabled when all +* interrupt sources for that group are already disabled. +* Arguments : vector - +* An interrupt source inside the group that is to be enabled/disabled. +* enable - +* Whether to enable or disable the interrupt. +* ipl - +* If enabling a group interrupt, what IPL to use. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid IPL or vector +* BSP_INT_ERR_GROUP_STILL_ENABLED - +* Not all group interrupts were disabled so group interrupt was not disabled. +***********************************************************************************************************************/ +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl) +{ + bsp_int_err_t err = BSP_INT_SUCCESS; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* If interrupt is going to be enabled, verify that IPL is valid. */ + if ((true == enable) && ((BSP_MCU_IPL_MIN == ipl) || (ipl > BSP_MCU_IPL_MAX))) + { + return BSP_INT_ERR_INVALID_ARG; + } +#endif + + if ((vector > BSP_INT_SRC_GR_INT_IE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BE0_TOP)) + { + /* Group IE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_IE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPIE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = (uint8_t)((ipl > IPR(ICU, GROUPIE0)) ? ipl : IPR(ICU, GROUPIE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPIE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENIE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL0_TOP)) + { + /* Group BE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = (uint8_t)((ipl > IPR(ICU, GROUPBE0)) ? ipl : IPR(ICU, GROUPBE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL1_TOP)) + { + /* Group BL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = (uint8_t)((ipl > IPR(ICU, GROUPBL0)) ? ipl : IPR(ICU, GROUPBL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL1_TOP) && (vector < BSP_INT_SRC_GR_INT_BL2_TOP)) + { + /* Group BL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = (uint8_t)((ipl > IPR(ICU, GROUPBL1)) ? ipl : IPR(ICU, GROUPBL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL2_TOP) && (vector < BSP_INT_SRC_GR_INT_AL0_TOP)) + { + /* Group BL2. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL2 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL2) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = (uint8_t)((ipl > IPR(ICU, GROUPBL2)) ? ipl : IPR(ICU, GROUPBL2)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL2)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL2.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL0_TOP) && (vector < BSP_INT_SRC_GR_INT_AL1_TOP)) + { + /* Group AL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = (uint8_t)((ipl > IPR(ICU, GROUPAL0)) ? ipl : IPR(ICU, GROUPAL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL1_TOP) && (vector < BSP_INT_SRC_GR_INT_END)) + { + /* Group AL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = (uint8_t)((ipl > IPR(ICU, GROUPAL1)) ? ipl : IPR(ICU, GROUPAL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + } + else + { + /* Vector given was not part of a group. */ + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_gr_int_enable_disable() */ +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_supervisor_inst_isr +* Description : Supervisor Instruction Violation ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_supervisor_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_SUPERVISOR_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_supervisor_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +/*********************************************************************************************************************** +* Function name: excep_access_isr +* Description : Access exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_access_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_ACCESS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_access_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_undefined_inst_isr +* Description : Undefined instruction exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_undefined_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_UNDEFINED_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_undefined_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +/*********************************************************************************************************************** +* Function name: excep_floating_point_isr +* Description : Floating point exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_floating_point_isr(void) +{ +#ifdef __FPU + /* Used for reading FPSW register. */ + uint32_t tmp_fpsw; +#endif + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_FPU, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + +#ifdef __FPU + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW(tmp_fpsw & ((uint32_t)~BSP_PRV_FPU_CAUSE_FLAGS)); +#endif +} /* End of function excep_floating_point_isr() */ +#endif + +#ifdef BSP_MCU_NON_MASKABLE_ISR +/*********************************************************************************************************************** +* Function name: non_maskable_isr +* Description : Non-maskable interrupt ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void non_maskable_isr(void) +{ + /* Determine what is the cause of this interrupt. */ + +#ifdef BSP_MCU_NMI_EXC_NMI_PIN + /* EXC_NMI_PIN */ + if ((1 == ICU.NMISR.BIT.NMIST) && (1 == ICU.NMIER.BIT.NMIEN)) + { + /* NMI pin interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_NMI_PIN, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear NMI pin interrupt flag. */ + ICU.NMICLR.BIT.NMICLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_OSC_STOP_DETECT + /* OSC_STOP_DETECT */ + if ((1 == ICU.NMISR.BIT.OSTST) && (1 == ICU.NMIER.BIT.OSTEN)) + { + /* Oscillation stop detection interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_OSC_STOP_DETECT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear oscillation stop detect flag. */ + ICU.NMICLR.BIT.OSTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_WDT_ERROR + /* WDT_ERROR */ + if ((1 == ICU.NMISR.BIT.WDTST) && (1 == ICU.NMIER.BIT.WDTEN)) + { + /* WDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_WDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear WDT flag. */ + ICU.NMICLR.BIT.WDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD + /* LVD */ + if ((1 == ICU.NMISR.BIT.LVDST) && (1 == ICU.NMIER.BIT.LVDEN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +#endif + +#ifdef BSP_MCU_NMI_IWDT_ERROR + /* IWDT_ERROR */ + if ((1 == ICU.NMISR.BIT.IWDTST) && (1 == ICU.NMIER.BIT.IWDTEN)) + { + /* IWDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_IWDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear IWDT flag. */ + ICU.NMICLR.BIT.IWDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD1 + /* LVD1 */ + if ((1 == ICU.NMISR.BIT.LVD1ST) && (1 == ICU.NMIER.BIT.LVD1EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD1 flag. */ + ICU.NMICLR.BIT.LVD1CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD2 + /* LVD2 */ + if ((1 == ICU.NMISR.BIT.LVD2ST) && (1 == ICU.NMIER.BIT.LVD2EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.LVD2CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_VBATT + /* VBATT */ + if ((1 == ICU.NMISR.BIT.VBATST) && (1 == ICU.NMIER.BIT.VBATEN)) + { + /* VBATT monitoring interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_VBATT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.VBATCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_ECCRAM + /* ECCRAM */ + if ((1 == ICU.NMISR.BIT.ECCRAMST) && (1 == ICU.NMIER.BIT.ECCRAMEN)) + { + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + } +#endif + +#ifdef BSP_MCU_NMI_RAM + /* RAM */ + if ((1 == ICU.NMISR.BIT.RAMST) && (1 == ICU.NMIER.BIT.RAMEN)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_ECCRAM */ + } +#endif /* BSP_MCU_NMI_RAM */ + +#ifdef BSP_MCU_NMI_EXNMI + /* EXNMI */ + if ((1 == ICU.NMISR.BIT.EXNMIST) && (1 == ICU.NMIER.BIT.EXNMIEN)) + { + #ifdef BSP_MCU_NMI_EXNMI_RAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.RAMST) && (1 == ICU.EXNMIER.BIT.RAMEN)) + { + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_EXNMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_EXNMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_ECCRAM */ + } + #endif /* BSP_MCU_NMI_EXNMI_RAM */ + + #ifdef BSP_MCU_NMI_EXNMI_DPFPUEX + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.DPFPUST) && (1 == ICU.EXNMIER.BIT.DPFPUEN)) + { + /* Double-Precision Floating-Point Exception interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear DPFPUST flag. */ + ICU.EXNMICLR.BIT.DPFPUCLR = 1; + } + #endif /* BSP_MCU_NMI_EXNMI_DPFPUEX */ + } +#endif /* BSP_MCU_NMI_EXNMI */ + + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Return from Non-maskable interrupt handlling routine is prohibited. + Never use the non-maskable interrupt with an attempt to return to the program that was being executed at + the time of interrupt generation after the exception handling routine is ended. + */ + R_BSP_NOP(); + } +} /* End of function non_maskable_isr() */ +#endif /* BSP_MCU_NON_MASKABLE_ISR */ + +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +/*********************************************************************************************************************** +* Function name: undefined_interrupt_source_isr +* Description : All undefined interrupt vectors point to this function. +* Set a breakpoint in this function to determine which source is creating unwanted interrupts. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void undefined_interrupt_source_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_UNDEFINED_INTERRUPT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function undefined_interrupt_source_isr() */ +#endif + +#ifdef BSP_MCU_BUS_ERROR_ISR +/*********************************************************************************************************************** +* Function name: bus_error_isr +* Description : By default, this demo code enables the Bus Error Interrupt. This interrupt will fire if the user tries +* to access code or data from one of the reserved areas in the memory map, including the areas covered +* by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint +* during debugging and development, and further handling should be added by the user for their +* application. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void bus_error_isr (void) +{ + /* Clear the bus error */ + BSC.BERCLR.BIT.STSCLR = 1; + + /* + To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD. + The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units) + */ + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function bus_error_isr() */ +#endif + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h new file mode 100644 index 000000000..d6de101be --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.h +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptRequestEnable(uint32_t vector); +void R_BSP_InterruptRequestDisable(uint32_t vector); +bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector, bsp_int_cb_t callback); +bsp_int_err_t R_BSP_InterruptRead(bsp_int_src_t vector, bsp_int_cb_t * callback); +bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata); + +void bsp_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_supervisor_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_access_isr) +#endif +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_undefined_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_floating_point_isr) +#endif +#ifdef BSP_MCU_NON_MASKABLE_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(non_maskable_isr) +#endif +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +R_BSP_PRAGMA_INTERRUPT_DEFAULT(undefined_interrupt_source_isr) +#endif +#ifdef BSP_MCU_BUS_ERROR_ISR +R_BSP_PRAGMA_INTERRUPT(bus_error_isr, VECT(BSC,BUSERR)) +#endif + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c new file mode 100644 index 000000000..6170397d7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c @@ -0,0 +1,187 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.c +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* : 10.12.2019 2.02 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform configuration. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareLock + ******************************************************************************************************************//** + * @brief Attempts to reserve a lock. + * @param[out] plock Pointer to lock structure with lock to try and acquire. + * @retval true Successful, lock was available and acquired. + * @retval false Failure, lock was already acquired and is not available. + * @details This function implements an atomic locking mechanism. Locks can be used in numerous ways. Two common uses + * of locks are to protect critical sections of code and to protect against duplicate resource allocation. + * For protecting critical sections of code the user would require that the code first obtain the critical section's + * lock before executing. An example of protecting against duplicate resource allocation would be if the user had two + * FIT modules that used the same peripheral. For example, the user may have one FIT module that uses the SCI + * peripheral in UART mode and another FIT module that uses the SCI peripheral in I2C mode. To make sure that both + * modules cannot use the same SCI channel, locks can be used. + * Care should be taken when using locks as they do not provide advanced features one might expect from an RTOS + * semaphore or mutex. If used improperly locks can lead to deadlock in the user's system. + * Users can override the default locking mechanisms. + */ +bool R_BSP_SoftwareLock (BSP_CFG_USER_LOCKING_TYPE * const plock) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + bool ret = false; + + /* Variable used in trying to acquire lock. Using the xchg instruction makes this atomic */ + int32_t is_locked = true; + + /* This example uses the RX MCU's atomic xchg() instruction. plock->lock is the lock we are trying to reserve. + The way this works is that 'is_locked' gets the value of the plock->lock and plock->lock gets the value of + 'is_locked' which we just set to 'true'. Basically this is an atomic 'swap' command. If the lock had not yet been + reserved then its value would be 'false' and after the xchg() instruction finished 'is_locked' would have + 'false'. If it had already been reserved then 'is_locked' would have 'true' after the xchg() instruction. Since + plock->lock was already 'true' and we just set it back to 'true' everything is ok. To see if we reserved the lock + we just need to check the value of 'is_locked' after this instruction finishes. */ + + /* Try to acquire semaphore to obtain lock */ + R_BSP_EXCHANGE(&is_locked, &plock->lock); + + /* Check to see if semaphore was successfully taken */ + if (false == is_locked) + { + /* Lock obtained, return success. */ + ret = true; + } + else + { + /* Lock was not obtained, another task already has it. */ + R_BSP_NOP(); + } + + return ret; +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(plock); +#endif +} /* End of function R_BSP_SoftwareLock() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareUnlock + ******************************************************************************************************************//** + * @brief Releases a lock. + * @param[out] plock Pointer to lock structure with lock to release. + * @retval true Successful, lock was released. Or the lock has been already released. + * @retval false Failure, lock could not be released. + * @details This function releases a lock that was previously acquired using the R_BSP_SoftwareLock() function. + */ +bool R_BSP_SoftwareUnlock (BSP_CFG_USER_LOCKING_TYPE * const plock) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Set lock back to unlocked. */ + plock->lock = false; + + return true; +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(plock); +#endif +} /* End of function R_BSP_SoftwareUnlock() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_HardwareLock + ******************************************************************************************************************//** + * @brief Attempts to reserve a hardware peripheral lock. + * @param[in] hw_index Index of lock to acquire from the hardware lock array. + * @retval true Successful, lock was available and acquired. + * @retval false Failure, lock was already acquired and is not available. + * @details This function attempts to acquire the lock for a hardware resource of the MCU. Instead of sending in a + * pointer to a lock as with the R_BSP_SoftwareLock() function, the user sends in an index to an array that holds 1 + * lock per MCU hardware resource. This array is shared amongst all FIT modules and user code therefore allowing + * multiple FIT modules (and user code) to use the same locks. The user can see the available hardware resources by + * looking at the mcu_lock_t enum in mcu_locks.h. These enum values are also the index into the hardware lock array. + * The same atomic locking mechanisms from the R_BSP_SoftwareLock() function are used with this function as well. + * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required + * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum they are not + * using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. The + * user will save 4-bytes per deleted entry. + */ +bool R_BSP_HardwareLock (mcu_lock_t const hw_index) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Pass actual lock to software lock function. */ + return R_BSP_SoftwareLock(&g_bsp_Locks[hw_index]); +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(hw_index); +#endif +} /* End of function R_BSP_HardwareLock() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_HardwareUnlock + ******************************************************************************************************************//** + * @brief Releases a hardware peripheral lock. + * @param[in] hw_index Index of lock to release from the hardware lock array. + * @retval true Successful, lock was released. + * @retval false Failure, lock could not be released. + * @details This function attempts to release the lock for a hardware resource of the MCU that was previously acquired + * using the R_BSP_HardwareLock() function. + * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required + * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum that they are + * not using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. + * The user will save 4-bytes per deleted entry. + */ +bool R_BSP_HardwareUnlock (mcu_lock_t const hw_index) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Pass actual lock to software unlock function. */ + return R_BSP_SoftwareUnlock(&g_bsp_Locks[hw_index]); +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(hw_index); +#endif +} /* End of function R_BSP_HardwareUnlock() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c new file mode 100644 index 000000000..69a22da8f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c @@ -0,0 +1,93 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_mcu_startup.c +* Description : This module implements user startup specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* Added Initialization the trigonometric function unit in R_BSP_StartupOpen function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE != 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_StartupOpen + ******************************************************************************************************************//** + * @brief Specifies settings to use the BSP and peripheral FIT modules. Call this function only when the BSP startup + * is disabled. + * @details This function performs initialization for the interrupt callback, register protection, and the hardware + * and pins. These processing are needed for using the BSP and peripheral FIT modules. Thus, this function must be + * called in the beginning of the main function. Call this function only when the BSP startup is disabled. + * @note The R_BSP_StartupOpen function performs a part of processing in the startup function. + * See Section 5.18 in the application note for more information. + */ +void R_BSP_StartupOpen (void) +{ + /* Initializes the trigonometric function unit. */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU + R_BSP_INIT_TFU(); +#endif +#endif + /* Initialize RAM. */ + bsp_ram_initialize(); + + /* Initialize MCU interrupt callbacks. */ + bsp_interrupt_open(); + + /* Initialize register protection functionality. */ + bsp_register_protect_open(); + + /* Configure the MCU and board hardware */ + hardware_setup(); +} /* End of function R_BSP_StartupOpen() */ + +#endif /* BSP_CFG_STARTUP_DISABLE != 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h new file mode 100644 index 000000000..50a8304da --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_mcu_startup.h +* Description : This module implements user startup specific functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_STARTUP_H +#define MCU_STARTUP_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_StartupOpen(void); + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c new file mode 100644 index 000000000..203210da9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c @@ -0,0 +1,1053 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.c +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_SWINT_TASK_BUFFER_MAX (BSP_CFG_SWINT_TASK_BUFFER_NUMBER + 1) +#define BSP_PRV_SWINT_ACCESS_ACCEPTATION (1) +#define BSP_PRV_SWINT_ACCESS_REJECTION (0) +#define BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT (1) +#define BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +st_bsp_swint_access_control_t g_bsp_swint_access_ctrl[BSP_SWINT_UNIT_MAX]; + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Interrupt functions */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint_isr, VECT(ICU, SWINT)) +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint2_isr, VECT(ICU, SWINT2)) +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + +/* Functions */ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args); +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit); +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args); +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit); +static void bsp_swint_dummy_task(void * p_dummy_context); + +/* Variables */ +static st_bsp_swint_task_t s_bsp_swint_task[BSP_SWINT_UNIT_MAX][BSP_PRV_SWINT_TASK_BUFFER_MAX]; +static uint8_t s_bsp_swint_buf_used[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_top[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_bottom[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_nested_int_status[BSP_SWINT_UNIT_MAX]; + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptOpen + ******************************************************************************************************************//** + * @brief This function initializes software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function locks the hardware, resets the access control status, clears the interrupt request (IR), + * initializes the interrupt priority level (IPR), enables nested-interrupt status, initializes the task buffer, and + * enables interrupts (IEN). + * @note This function is available only when use of software interrupts is enabled in a configuration macro. + * This function is called automatically at BSP startup when the value of BSP_CFG_SWINT_UNITn_ENABLE in r_bsp_config.h + * is 1. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + uint8_t swint_ipr; + + swint_ret = BSP_SWINT_SUCCESS; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + break; + } + + if (BSP_SWINT_SUCCESS == swint_ret) + { + if (true == lock_ret) + { + /* Reset Access Control Status */ + g_bsp_swint_access_ctrl[unit].status = BSP_PRV_SWINT_ACCESS_ACCEPTATION; + + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Set Interrupt Priority(IPR) */ + swint_ipr = BSP_CFG_SWINT_IPR_INITIAL_VALUE; + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, &swint_ipr); + + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Enable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_ENABLE_INTERRUPT, FIT_NO_PTR); + } + else + { + swint_ret = BSP_SWINT_ERR_ALREADY_OPEN; + } + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptOpen() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptClose + ******************************************************************************************************************//** + * @brief This function terminates software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function unlocks the hardware, disables interrupts (IEN), clears the interrupt request (IR), + * initializes the task buffer, and disables nested-interrupt status. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the R_BSP_SoftwareInterruptSetTask function or software interrupt function (bsp_swint_execute_task) is acquiring + * acces control rights and an interrupt is generated and this function is called within the interrupt, the task + * buffer may not be controlled correctly. If this function is used in an interrupt, clear the all task by the + * R_BSP_SoftwareInterruptControl function with the BSP_SWINT_CMD_CLEAR_ALL_TASK command before call this function. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + if (true == lock_ret) + { + swint_ret = BSP_SWINT_SUCCESS; + } + else + { + swint_ret = BSP_SWINT_ERR_NOT_CLOSED; + } + } + else + { + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptClose() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptSetTask + ******************************************************************************************************************//** + * @brief This function sets a task in the software interrupt task buffer. + * @param[in] unit Software interrupt unit + * @param[in] set_task Software interrupt task + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_TASK Invalid task pointer specified. + * @retval BSP_SWINT_ERR_FULL_BUFFER Task buffer full. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function sets the task specified by an argument in the software interrupt task buffer. After setting + * the task, the software interrupt occurs. If the task buffer is full, the task is not set. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_access_control_t access_control; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)FIT_NO_FUNC == (uint32_t)set_task.p_taskAddr) || ((uint32_t)NULL == (uint32_t)set_task.p_taskAddr)) + { + ret = BSP_SWINT_ERR_INVALID_TASK; + } + else if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_used[unit]) + { + ret = BSP_SWINT_ERR_FULL_BUFFER; + } + else + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_top[unit]) + { + s_bsp_swint_buf_top[unit] = 0; + } + else + { + s_bsp_swint_buf_top[unit]++; + } + + s_bsp_swint_buf_used[unit]++; + + /* Set Task Buffer */ + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].status = BSP_SWINT_TASK_STATUS_REQUESTED; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_taskAddr = set_task.p_taskAddr; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_context = set_task.p_context; + + ret = BSP_SWINT_SUCCESS; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptSetTask() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_interrupt_information +* Description : Get the software interrupt information. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args) +{ + st_bsp_swint_int_info_t *p_swint_int_info; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_int_info = (st_bsp_swint_int_info_t *)p_args; + + switch (unit) + { + /* Get Interrupt Information */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + p_swint_int_info->ipr = IPR(ICU, SWINT); + p_swint_int_info->ien = IEN(ICU, SWINT); + p_swint_int_info->ir = IR(ICU, SWINT); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + p_swint_int_info->ipr = IPR(ICU, SWINT2); + p_swint_int_info->ien = IEN(ICU, SWINT2); + p_swint_int_info->ir = IR(ICU, SWINT2); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_get_interrupt_information() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_interrupt +* Description : Enable interrupt. (Set the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Enable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_enable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_interrupt +* Description : Disable interrupt. (Clear the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Disable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_disable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_priority +* Description : Set interrupt priority. (Set the IPR register.) +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_INVALID_IPR - Overflow interrupt priority. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_ipr; + uint8_t ien; + bsp_int_ctrl_t int_ctrl; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_ipr = (uint8_t *)p_args; + + /* Check Interrupt Priority */ + if (BSP_MCU_IPL_MAX < (*p_swint_ipr)) + { + ret = BSP_SWINT_ERR_INVALID_IPR; + } + else + { + /* Set IPL to the maximum value to disable all interrupts*/ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + switch (unit) + { + /* Set Interrupt Priority */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ien = IEN(ICU, SWINT); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ien = IEN(ICU, SWINT2); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT2) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + /* Restore the IPL */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + + ret = BSP_SWINT_SUCCESS; + } + + return ret; +} /* End of function bsp_swint_set_interrupt_priority() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_request +* Description : Set interrupt request. (Set the SWINTR register.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Set Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ICU.SWINTR.BIT.SWINT = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ICU.SWINT2R.BIT.SWINT2 = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_set_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_interrupt_request +* Description : Clear interrupt request. (Clear the IR bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Clear Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + IR(ICU, SWINT) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + IR(ICU, SWINT2) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_clear_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_nested_interrupt +* Description : Set nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_enable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_nested_interrupt +* Description : Clear nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_disable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_task +* Description : Clear the task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +* BSP_SWINT_ERR_INVALID_BUFFER_NUMBER - Set invalid buffer number. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_task_buffer_t *p_swint_task_buffer; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task_buffer = (st_bsp_swint_task_buffer_t *)p_args; + + if (BSP_PRV_SWINT_TASK_BUFFER_MAX > p_swint_task_buffer->number) + { + /* Clear Task Buffer */ + if (BSP_SWINT_TASK_STATUS_EXECUTING != s_bsp_swint_task[unit][p_swint_task_buffer->number].status) + { + s_bsp_swint_task[unit][p_swint_task_buffer->number].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_context = FIT_NO_PTR; + ret = BSP_SWINT_SUCCESS; + } + else + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_BUFFER_NUMBER; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_all_task +* Description : Clear the all task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit) +{ + e_bsp_swint_err_t ret; + uint8_t buf_num; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + ret = BSP_SWINT_SUCCESS; + + /* Check Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][buf_num].status) + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + break; + } + } + + if (BSP_SWINT_SUCCESS == ret) + { + /* Clear ALL Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } + else + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_all_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_all_task_status +* Description : Get the task status of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args) +{ + uint8_t buf_num; + st_bsp_swint_task_t *p_swint_task; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task = (st_bsp_swint_task_t *)p_args; + + /* Clear Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + p_swint_task->status = s_bsp_swint_task[unit][buf_num].status; + p_swint_task->p_taskAddr = s_bsp_swint_task[unit][buf_num].p_taskAddr; + p_swint_task->p_context = s_bsp_swint_task[unit][buf_num].p_context; + p_swint_task++; + } +} /* End of function bsp_swint_get_all_task_status() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptControl + ******************************************************************************************************************//** + * @brief This function controls software interrupts. + * @param[in] unit Software interrupt unit + * @param[in] cmd Software interrupt control command + * @param[in, out] p_args Pointer to arguments for software interrupt control commands. Set the argument type to match + * each software interrupt control command. For commands that do not require arguments, use the setting FIT_NO_PTR. + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_IPR Invalid interrupt priority level specified. + * @retval BSP_SWINT_ERR_INVALID_CMD Invalid command specified. + * @retval BSP_SWINT_ERR_INVALID_BUFFER_NUMBER Invalid task buffer number specified. + * @retval BSP_SWINT_ERR_TASK_EXECUTING Attempt to manipulate a task that is running. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function performs software interrupt control in response to commands. Refer the application note for + * the operation of each command. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * Do not change the interrupt priority level (IPR) while a software interrupt is being processed.\n + * When the BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY command is run, interrupts are disabled temporarily in order to set + * the interrupt priority level (IPR).\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right.\n + * If a software interrupt is generated while this function has the access control right, the software interrupt + * cannot obtain the access control right and interrupt processing ends with the task remaining unexecuted. For this + * reason, after returning from a software interrupt the interrupt request is cleared regardless of whether a task has + * been set in the task buffer. To avoid this, setting of the interrupt request occurs at the end of the processing of + * the BSP_SWINT_CMD_CLEAR_TASK and BSP_SWINT_CMD_CLEAR_ALL_TASK commands. Nevertheless, since all task buffers are + * cleared when processing of the BSP_SWINT_CMD_CLEAR_ALL_TASK command completes successfully, the interrupt request + * is not set. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + ret = BSP_SWINT_SUCCESS; + + /* Execute Command */ + switch (cmd) + { + case BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION: + bsp_swint_get_interrupt_information(unit, p_args); + break; + + case BSP_SWINT_CMD_ENABLE_INTERRUPT: + bsp_swint_enable_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_INTERRUPT: + bsp_swint_disable_interrupt(unit); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY: + ret = bsp_swint_set_interrupt_priority(unit, p_args); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_REQUEST: + bsp_swint_set_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST: + bsp_swint_clear_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT: + bsp_swint_enable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT: + bsp_swint_disable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_CLEAR_TASK: + ret = bsp_swint_clear_task(unit, p_args); + break; + + case BSP_SWINT_CMD_CLEAR_ALL_TASK: + ret = bsp_swint_clear_all_task(unit); + break; + + case BSP_SWINT_CMD_GET_ALL_TASK_STATUS: + bsp_swint_get_all_task_status(unit, p_args); + break; + + case BSP_SWINT_CMD_GET_USED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)s_bsp_swint_buf_used[unit]; + break; + + case BSP_SWINT_CMD_GET_UNUSED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)(BSP_CFG_SWINT_TASK_BUFFER_NUMBER - s_bsp_swint_buf_used[unit]); + break; + + default: + ret = BSP_SWINT_ERR_INVALID_CMD; + break; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_access_control +* Description : Get access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Get access. +* false - Failed to get access. +***********************************************************************************************************************/ +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Get Access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == p_args->status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_get_access_control() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_release_access_control +* Description : Release access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Release access. +* false - Failed to release access. +***********************************************************************************************************************/ +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Release access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == g_bsp_swint_access_ctrl[unit].status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_release_access_control() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_dummy_task +* Description : Dummy task. +* Arguments : p_dummy_context - Dummy arguments. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_dummy_task(void * p_dummy_context) +{ + R_BSP_NOP(); +} /* End of function bsp_swint_dummy_task() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_execute_task +* Description : Execute task of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit) +{ + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Enable Multiple Interrupt */ + if (BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT == s_bsp_swint_nested_int_status[unit]) + { + R_BSP_InterruptsEnable(); + } + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + /* WAIT_LOOP */ + while (0 != s_bsp_swint_buf_used[unit]) + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_bottom[unit]) + { + s_bsp_swint_buf_bottom[unit] = 0; + } + else + { + s_bsp_swint_buf_bottom[unit]++; + } + + if (BSP_SWINT_TASK_STATUS_REQUESTED == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "EXECUTING" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_EXECUTING; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Execute Task */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_taskAddr(s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_context); + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "COMPLETED" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_COMPLETED; + } + } + + if (0 != s_bsp_swint_buf_used[unit]) + { + s_bsp_swint_buf_used[unit]--; + } + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } +} /* End of function bsp_swint_execute_task() */ + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint_isr +* Description : Software interrupt function. (Unit1) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT1); +} /* End of function bsp_swint_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint2_isr +* Description : Software interrupt function. (Unit2) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint2_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT2); +} /* End of function bsp_swint2_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h new file mode 100644 index 000000000..0ce9ba056 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h @@ -0,0 +1,138 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.h +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* Multiple inclusion prevention macro */ +#ifndef SOFTWARE_INTERRUPT_H +#define SOFTWARE_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +typedef enum e_bsp_swint_unit +{ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + BSP_SWINT_UNIT1, +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + BSP_SWINT_UNIT2, +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + BSP_SWINT_UNIT_MAX +} e_bsp_swint_unit_t; + +typedef enum e_bsp_swint_err +{ + BSP_SWINT_SUCCESS = 0, + BSP_SWINT_ERR_ALREADY_OPEN, + BSP_SWINT_ERR_NOT_CLOSED, + BSP_SWINT_ERR_INVALID_UNIT, + BSP_SWINT_ERR_INVALID_IPR, + BSP_SWINT_ERR_INVALID_CMD, + BSP_SWINT_ERR_INVALID_TASK, + BSP_SWINT_ERR_INVALID_BUFFER_NUMBER, + BSP_SWINT_ERR_TASK_EXECUTING, + BSP_SWINT_ERR_FULL_BUFFER, + BSP_SWINT_ERR_ACCESS_REJECTION +} e_bsp_swint_err_t; + +typedef enum e_bsp_swint_cmd +{ + BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION = 0, + BSP_SWINT_CMD_ENABLE_INTERRUPT, + BSP_SWINT_CMD_DISABLE_INTERRUPT, + BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, + BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, + BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, + BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_CLEAR_TASK, + BSP_SWINT_CMD_CLEAR_ALL_TASK, + BSP_SWINT_CMD_GET_ALL_TASK_STATUS, + BSP_SWINT_CMD_GET_USED_BUFFER, + BSP_SWINT_CMD_GET_UNUSED_BUFFER +} e_bsp_swint_cmd_t; + +typedef struct st_bsp_swint_int_info +{ + uint8_t ipr; + uint8_t ien; + uint8_t ir; + uint8_t nested_int; +} st_bsp_swint_int_info_t; + +typedef enum e_bsp_swint_task_status +{ + BSP_SWINT_TASK_STATUS_NO_REQUEST = 0, + BSP_SWINT_TASK_STATUS_REQUESTED, + BSP_SWINT_TASK_STATUS_EXECUTING, + BSP_SWINT_TASK_STATUS_COMPLETED +} e_bsp_swint_task_status_t; + +typedef struct st_bsp_swint_task +{ + e_bsp_swint_task_status_t status; + void (*p_taskAddr)(void *p_task_args); + void *p_context; +} st_bsp_swint_task_t; + +typedef struct st_bsp_swint_task_buffer +{ + uint8_t number; +} st_bsp_swint_task_buffer_t; + +typedef struct st_bsp_swint_access_control +{ + int32_t status; +} st_bsp_swint_access_control_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task); +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args); + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rtos.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rtos.h new file mode 100644 index 000000000..6d4d8268d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rtos.h @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rtos.h +* Description : This module implements functions of rtos. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.10 Added include file and macro definitions for Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_config.h" + +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ +#elif BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "queue.h" +#include "croutine.h" +#include "timers.h" +#include "event_groups.h" +#include "freertos_start.h" +#elif BSP_CFG_RTOS_USED == 2 /* SEGGER embOS */ +#elif BSP_CFG_RTOS_USED == 3 /* Micrium MicroC/OS */ +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#include "kernel.h" +#include "kernel_id.h" + +#define RENESAS_RI600V4 0 +#define RENESAS_RI600PX 1 + +#undef BSP_CFG_RTOS_SYSTEM_TIMER +#define BSP_CFG_RTOS_SYSTEM_TIMER _RI_CLOCK_TIMER +#else +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RTOS_H +#define R_RTOS_H + +#endif /* R_RTOS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h new file mode 100644 index 000000000..d03359072 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h @@ -0,0 +1,1638 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_compiler.h +* Description : This is a file for integrating the definitions of different functions for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.01 Modified definition of __RX_DPFPU_INSNS__ to __RX_DFPU_INSNS__ for GNUC. +* Modified definition of TFU for GNUC. +* Modified comment of TFU for ICCRX. +* Added include of r_bsp_config.h. +* Changed the following definitions for added support of Renesas RTOS(RI600V4 or RI600PX). +* - R_BSP_SECNAME_INTVECTTBL +* - R_BSP_SECNAME_EXCEPTVECTTBL +* - R_BSP_SECNAME_FIXEDVECTTBL +* - R_BSP_PRAGMA_INTERRUPT +* - R_BSP_PRAGMA_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_FUNCTION +* - R_BSP_ATTRIB_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_DEFAULT +* - R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT +* Changed the following definitions to definition without __no_init for ICCRX so that +* there is no warning when the initial value is specified. +* - _R_BSP_ATTRIB_SECTION_CHANGE_C1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C8 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D8 +* : 17.12.2019 1.02 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_common.h" +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_COMPILER_H +#define R_RX_COMPILER_H + +/* ========== Check Compiler ========== */ +#if defined(__CCRX__) + /* supported */ +#elif defined(__GNUC__) + /* supported */ +#elif defined(__ICCRX__) + /* supported */ +#else + #error "Unrecognized compiler" +#endif + + +/* ========== Macros ========== */ +#if defined(__CCRX__) + +/* #define __RX 1 */ /* This is automatically defined by CCRX. */ +/* #define __LIT 1 */ /* This is automatically defined by CCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by CCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by CCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by CCRX. */ +/* #define __DPFPU 1 */ /* This is automatically defined by CCRX. */ + +#elif defined(__GNUC__) + +#if !defined(__RX) +#define __RX 1 +#endif + +#if defined(__RX_LITTLE_ENDIAN__) +#if !defined(__LIT) +#define __LIT 1 +#endif +#elif defined(__RX_BIG_ENDIAN__) +#if !defined(__BIG) +#define __BIG 1 +#endif +#endif + +#if defined(__RX_FPU_INSNS__) +#if !defined(__FPU) +#define __FPU 1 +#endif +#endif + +#if defined(__RXv1__) +#if !defined(__RXV1) +#define __RXV1 1 +#endif +#endif + +#if defined(__RXv2__) +#if !defined(__RXV2) +#define __RXV2 1 +#endif +#endif + +#if defined(__RXv3__) +#if !defined(__RXV3) +#define __RXV3 1 +#endif +#endif + +/* #define __TFU 1 */ /* This is automatically defined by GNUC. */ + +#if defined(__RX_DFPU_INSNS__) +#if !defined(__DPFPU) +#define __DPFPU 1 +#endif +#endif + +#elif defined(__ICCRX__) + +#if !defined(__RX) +#define __RX 1 +#endif + +/* #define __LIT 1 */ /* This is automatically defined by ICCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by ICCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by ICCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __DPFPU 1 */ /* Not yet supported. */ + +#endif + + +/* ========== Keywords ========== */ +#if !(defined(__CCRX__) && defined(__cplusplus)) +#define R_BSP_PRAGMA(...) _Pragma(#__VA_ARGS__) +#else +/* CC-RX' C++ mode does not support Pragma operator and variadic macros */ +#define R_BSP_PRAGMA(x) +#endif + +#if defined(__CCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile __evenaccess +#define R_BSP_EVENACCESS __evenaccess +#define R_BSP_EVENACCESS_SFR __evenaccess +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS /* none */ +#define R_BSP_EVENACCESS_SFR /* none */ +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__ICCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS volatile +#define R_BSP_EVENACCESS_SFR __sfr +#define R_BSP_VOLATILE_SFR volatile __sfr +#define R_BSP_SFR __sfr + +#endif + + +/* ========== Sections ========== */ + +/* ---------- Operators ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP(name) __sectop(#name) +#define R_BSP_SECEND(name) __secend(#name) +#define R_BSP_SECSIZE(name) __secsize(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP(name) ((void *)name##_start) +#define R_BSP_SECEND(name) ((void *)name##_end) +#define R_BSP_SECSIZE(name) ((size_t)((uint8_t *)R_BSP_SECEND(name) - (uint8_t *)R_BSP_SECTOP(name))) + +#define R_BSP_SECTION_OPERATORS_INIT(name) extern uint8_t name##_start[], name##_end[]; + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP(name) __section_begin(#name) +#define R_BSP_SECEND(name) __section_end(#name) +#define R_BSP_SECSIZE(name) __section_size(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) R_BSP_PRAGMA(section = #name); + +#endif + +/* ---------- Names ---------- */ +#if defined(__CCRX__) + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_INTVECTTBL "INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_INTVECTTBL "C$VECT" +#endif /* BSP_CFG_RTOS_USED */ + +#if defined(__RXV2) || defined(__RXV3) +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "EXCEPTVECT" +#endif /* BSP_CFG_RTOS_USED */ +#define R_BSP_SECNAME_RESETVECT "RESETVECT" +#else /* __RXV1 */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIXEDVECT" +#endif /* BSP_CFG_RTOS_USED */ +#endif /* defined(__RXV2) || defined(__RXV3) */ +#define R_BSP_SECNAME_UBSETTINGS "UBSETTINGS" + +#elif defined(__GNUC__) + +#define R_BSP_SECNAME_INTVECTTBL ".rvectors" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exvectors" +#define R_BSP_SECNAME_RESETVECT ".fvectors" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".fvectors" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#elif defined(__ICCRX__) + +#define R_BSP_SECNAME_INTVECTTBL ".inttable" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exceptvect" +#define R_BSP_SECNAME_RESETVECT ".resetvect" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".exceptvect" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#endif + +/* ---------- Addresses ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP_INTVECTTBL __sectop(R_BSP_SECNAME_INTVECTTBL) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL __sectop(R_BSP_SECNAME_EXCEPTVECTTBL) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP_INTVECTTBL ((void *)rvectors_start) +extern void * const rvectors_start[]; +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL ((void *)exvectors_start) +extern void * const exvectors_start[]; +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP_INTVECTTBL /* none */ +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL /* none */ +#endif + +#endif + + +/* ========== #pragma Directive ========== */ + +/* ---------- Stack Size ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(_size) _R_BSP_PRAGMA_STACKSIZE_SI(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SI(_size) __R_BSP_PRAGMA_STACKSIZE_SI##_size +#define __R_BSP_PRAGMA_STACKSIZE_SI(size) R_BSP_PRAGMA(stacksize si=size) +#define R_BSP_PRAGMA_STACKSIZE_SU(_size) _R_BSP_PRAGMA_STACKSIZE_SU(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SU(_size) __R_BSP_PRAGMA_STACKSIZE_SU##_size +#define __R_BSP_PRAGMA_STACKSIZE_SU(size) R_BSP_PRAGMA(stacksize su=size) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) static uint8_t istack_area[size] __attribute__((section(".r_bsp_istack"), used)); +#define R_BSP_PRAGMA_STACKSIZE_SU(size) static uint8_t ustack_area[size] __attribute__((section(".r_bsp_ustack"), used)); + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) /* none */ +#define R_BSP_PRAGMA_STACKSIZE_SU(size) /* none */ + +#endif + +/* ---------- Section Switch (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(section C UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT R_BSP_PRAGMA(section C EXCEPTVECT) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT R_BSP_PRAGMA(section C RESETVECT) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT R_BSP_PRAGMA(section C FIXEDVECT) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS __attribute__((section(R_BSP_SECNAME_UBSETTINGS))) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT __attribute__((section(R_BSP_SECNAME_EXCEPTVECTTBL))) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT __attribute__((section(R_BSP_SECNAME_RESETVECT))) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT __attribute__((section(R_BSP_SECNAME_FIXEDVECTTBL))) +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(location=R_BSP_SECNAME_UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT /* none */ +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT /* none */ +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT /* none */ +#endif +#endif + +/* ---------- Section Switch (part2) ---------- */ +#if defined(__CCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(type, section_name) R_BSP_PRAGMA(section type section_name) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(type, section_name) R_BSP_PRAGMA(section type section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P, P##section_tag) + +#if !defined(__cplusplus) +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#else +/* CC-RX' C++ mode does not support variadic macros */ +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, align) _R_BSP_ATTRIB_SECTION_CHANGE_##type##align(section_tag) +#endif + +#define R_BSP_ATTRIB_SECTION_CHANGE_END R_BSP_PRAGMA(section) + +#elif defined(__GNUC__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) __attribute__((section(#section_name))) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) __attribute__((section(#section_name))) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#elif defined(__ICCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) R_BSP_PRAGMA(location=#section_name)\ + __no_init +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) R_BSP_PRAGMA(location=#section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#endif + +/* ---------- Interrupt Function Creation ---------- */ +#if defined(__CCRX__) + +/* Standard */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void); + +#else /* BSP_CFG_RTOS_USED != 4*/ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + static void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because of no corresponding keyword */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT +#else /* BSP_CFG_RTOS_USED !=4 */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because of no corresponding keyword */ +#endif /* BSP_CFG_RTOS_USED */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + static void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + static void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* only this one because of no corresponding keyword */ + +/* Default */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) void function_name(void); +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#elif defined(__GNUC__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((interrupt)); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((interrupt, used)); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because __attribute__((interrupt)) prevents GNURX from generating vector */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because __attribute__((interrupt, used)) prevents GNURX from generating vector */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))) \ + __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)) \ + __attribute__((fast_interrupt, used)); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((fast_interrupt, used)); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* __attribute__((interrupt(fast))) Not necessary, + but Don't forget a R_BSP_PRAGMA_FAST_INTERRUPT() declaration */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* __attribute__((interrupt(fast)), used) Not necessary, + but Don't forget a R_BSP_PRAGMA_STATIC_FAST_INTERRUPT() declaration */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"), used)); + +#elif defined(__ICCRX__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __interrupt void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static __interrupt void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __fast_interrupt void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static __fast_interrupt void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static __interrupt void function_name(void); + +#endif + +/* ---------- Inline Expansion of Function ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + static + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_INLINE(function_name) inline extern __attribute__((always_inline)) +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) inline static __attribute__((always_inline)) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + static + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__GNUC__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) extern __attribute__((naked, noinline)) +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) static __attribute__((naked, noinline)) + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__ICCRX__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* ICCRX requires __task not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* ICCRX requires __task not only at a function declaration but also at a function definition */ + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part2) ---------- */ +#if defined(__CDT_PARSER__) + +#define R_BSP_ASM(...) /* none */ +#define R_BSP_ASM_LAB_NEXT(n) /* none */ +#define R_BSP_ASM_LAB_PREV(n) /* none */ +#define R_BSP_ASM_LAB(n_colon) /* none */ +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#else + +#if defined(__CCRX__) + +#if !defined(__cplusplus) +#define R_BSP_ASM(...) __VA_ARGS__ +#else +/* CC-RX' C++ mode does not support variadic macros */ +#endif +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#elif defined(__GNUC__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN __asm__ volatile ( +#define R_BSP_ASM_END R_BSP_ASM(rts)); + +#elif defined(__ICCRX__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) _lab##n +#define R_BSP_ASM_LAB_PREV(n) _lab##n +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) +#define R_BSP_ASM_BEGIN asm( +#define R_BSP_ASM_END ); + +#endif + +#endif /* defined(__CDT_PARSER__) */ + +/* ---------- Inline Expansion of Assembly-Language Function (part3) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) /* no way */ +#define R_BSP_ASM_INTERNAL_NOT_USED(p) /* no way */ + +#elif defined(__GNUC__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#elif defined(__ICCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#endif + +/* ---------- Bit Field Order Specification ---------- */ + +/* ---------- bit_order=left ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order left)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=reversed_disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- bit_order=right ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order right)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- Alignment Value Specification for Structure Members and Class Members ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(unpack) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(packoption) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#endif + +/* ========== Rename Functions ========== */ + +#if defined(__CCRX__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ + +#elif defined(__GNUC__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC_Prg + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ + +#elif defined(__ICCRX__) + +#define R_BSP_POR_FUNCTION(name) extern int name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION _iar_program_start +#define R_BSP_STARTUP_FUNCTION __low_level_init + +#define R_BSP_UB_POR_FUNCTION(name) extern int name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION _iar_program_start + +#define R_BSP_MAIN_FUNCTION _iar_main_call + +#define _INITSCT __iar_data_init2 +#define excep_supervisor_inst_isr __privileged_handler +#define excep_access_isr __excep_access_inst +#define excep_undefined_inst_isr __undefined_handler +#define excep_floating_point_isr _float_placeholder +#define non_maskable_isr __NMI_handler +#define undefined_interrupt_source_isr __undefined_interrupt_source_handler + +#endif + +#endif /* R_RX_COMPILER_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c new file mode 100644 index 000000000..d344aed03 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c @@ -0,0 +1,994 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.c +* Description : Defines built-in functions that are in CCRX but not in the GCC and IAR compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.01 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* Added the below functions. +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.02 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 10.12.2019 1.03 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* : 17.12.2019 1.04 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_rx_compiler.h" +#include "r_rx_intrinsic_functions.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpc(uint32_t *data); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_extb(uint32_t *data); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_hi_long(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_mi_long(uint32_t *data); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_dpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_decnt(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_depc(uint32_t *ret); +#endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_BSP_Max +* Description : Selects the greater of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The greater value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2) +{ + return (data1 > data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_Min +* Description : Selects the smaller of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The smaller value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Min(signed long data1, signed long data2) +{ + return (data1 < data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_B +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_W +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_L +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeftWithCarry +* Description : Rotates data including the C flag to left by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* Return Value : data - Result of 1-bit left rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) +{ + __asm("rolc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRightWithCarry +* Description : Rotates data including the C flag to right by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* Return Value : data - Result of 1-bit right rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRightWithCarry(unsigned long data) +{ + __asm("rorc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeft +* Description : Rotates data to left by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* num - Number of bits to be rotated. +* Return Value : data - Result of num-bit left rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) +{ + __asm("rotl %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRight +* Description : Rotates data to right by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* num - Number of bits to be rotated. +* Return Value : result - Result of num-bit right rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num) +{ + __asm("rotr %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SignedMultiplication +* Description : Performs signed multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of signed multiplication. (signed 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) +{ + return ((signed long long)data1) * ((signed long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_UnsignedMultiplication +* Description : Performs unsigned multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of unsigned multiplication. (unsigned 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) +{ + return ((unsigned long long)data1) * ((unsigned long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function name: R_BSP_ChangeToUserMode +* Description : Switches to user mode. The PSW will be changed as following. +* Before Execution After Execution +* PSW.PM PSW.U PSW.PM PSW.U +* 0 (supervisor mode) 0 (interrupt stack) --> 1 (user mode) 1 (user stack) +* 0 (supervisor mode) 1 (user stack) --> 1 (user mode) 1 (user stack) +* 1 (user mode) 1 (user stack) --> NO CHANGE +* 1 (user mode) 0 (interrupt stack)) <== N/A +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_ChangeToUserMode) +void R_BSP_ChangeToUserMode(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM(;_R_BSP_Change_PSW_PM_to_UserMode: ) + R_BSP_ASM( PUSH.L R1 ; push the R1 value ) + R_BSP_ASM( MVFC PSW, R1 ; get the current PSW value ) + R_BSP_ASM( BTST #20, R1 ; check PSW.PM ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_NEXT(0);_psw_pm_is_user_mode ) + R_BSP_ASM(;_psw_pm_is_supervisor_mode: ) + R_BSP_ASM( BSET #20, R1 ; change PM = 0(Supervisor Mode) --> 1(User Mode) ) + R_BSP_ASM( PUSH.L R2 ; push the R2 value ) + R_BSP_ASM( MOV.L R0, R2 ; move the current SP value to the R2 value ) + R_BSP_ASM( XCHG 8[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the return address value of caller and the PSW value) ) + R_BSP_ASM( XCHG 4[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the R1 value of stack and the return address value of caller) ) + R_BSP_ASM( POP R2 ; pop the R2 value of stack ) + R_BSP_ASM( RTE ) + R_BSP_ASM_LAB(0:;_psw_pm_is_user_mode: ) + R_BSP_ASM( POP R1 ; pop the R1 value of stack ) + R_BSP_ASM( ;RTS ) + R_BSP_ASM_END +} /* End of function R_BSP_ChangeToUserMode() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetACC +* Description : Sets a value to ACC. +* Arguments : data - Value to be set to ACC. +* Return Value : none +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +void R_BSP_SetACC(signed long long data) +{ +#if defined(__GNUC__) + __builtin_rx_mvtachi(data >> 32); + __builtin_rx_mvtaclo(data & 0xFFFFFFFF); +#elif defined(__ICCRX__) + int32_t data_hi; + int32_t data_lo; + + data_hi = (int32_t)(data >> 32); + data_lo = (int32_t)(data & 0x00000000FFFFFFFF); + + R_BSP_MoveToAccHiLong(data_hi); + R_BSP_MoveToAccLoLong(data_lo); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetACC +* Description : Refers to the ACC value. +* Arguments : none +* Return Value : result - ACC value. +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_GetACC(void) +{ +#if defined(__GNUC__) + signed long long result = ((signed long long)__builtin_rx_mvfachi()) << 32; + result |= (((signed long long)__builtin_rx_mvfacmi()) << 16) & 0xFFFF0000; + return result; +#elif defined(__ICCRX__) + int64_t result; + + result = ((int64_t)R_BSP_MoveFromAccHiLong()) << 32; + result |= (((int64_t)R_BSP_MoveFromAccMiLong()) << 16) & 0xFFFF0000; + + return result; +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_2byte +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* four bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, the contents of ACC are +* fetched by the MVFACMI instruction and used as the return value of the intrinsic function. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : S(data1[n] * data2[n]) result. +***********************************************************************************************************************/ +#if defined(__GNUC__) +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + return __builtin_rx_mvfacmi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint1 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* The macw1 function performs rounding with the "RACW #1" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(1); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint2 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* the macw2 function performs rounding with the "RACW #2" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(2); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPSW +* Description : Sets a value to BPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPSW) +void R_BSP_SetBPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpsw +* Description : Refers to the BPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpsw) +void bsp_get_bpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPSW +* Description : Refers to the BPSW value. +* Arguments : none +* Return Value : BPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetBPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPC +* Description : Sets a value to BPC. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPC) +void R_BSP_SetBPC(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPC ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPC() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpc +* Description : Refers to the BPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpc) +void bsp_get_bpc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpc() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPC +* Description : Refers to the BPC value. +* Arguments : none +* Return Value : BPC value +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetBPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpc((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetBPC() */ + +#ifdef BSP_MCU_EXCEPTION_TABLE +/*********************************************************************************************************************** +* Function Name: R_BSP_SetEXTB +* Description : Sets a value for EXTB. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetEXTB) +void R_BSP_SetEXTB(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, EXTB ) + R_BSP_ASM_END +} /* End of function R_BSP_SetEXTB() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_extb +* Description : Refers to the EXTB value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_extb) +void bsp_get_extb(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC EXTB, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_extb() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetEXTB +* Description : Refers to the EXTB value. +* Arguments : none +* Return Value : EXTB value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetEXTB(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_extb((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetEXTB() */ +#endif /* BSP_MCU_EXCEPTION_TABLE */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccHiLong +* Description : This function moves the contents of src to the higher-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccHiLong) +void R_BSP_MoveToAccHiLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACHI R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccLoLong +* Description : This function moves the contents of src to the lower-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccLoLong) +void R_BSP_MoveToAccLoLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACLO R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccLoLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_hi_long +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_hi_long) +void bsp_move_from_acc_hi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACHI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_hi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccHiLong +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : none +* Return Value : The higher-order 32 bits of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccHiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_hi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_mi_long +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_mi_long) +void bsp_move_from_acc_mi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACMI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_mi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccMiLong +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : none +* Return Value : The contents of bits 47 to 16 of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccMiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_mi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccMiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitSet +* Description : Sets the specified one bit in the specified 1-byte area to 1. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitSet) +void R_BSP_BitSet(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BSET R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitSet() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitClear +* Description : Sets the specified one bit in the specified 1-byte area to 0. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitClear) +void R_BSP_BitClear(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BCLR R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitClear() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitReverse +* Description : Reverses the value of the specified one bit in the specified 1-byte area. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitReverse) +void R_BSP_BitReverse(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BNOT R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitReverse() */ + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDPSW +* Description : Sets a value to DPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDPSW) +void R_BSP_SetDPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_dpsw +* Description : Refers to the DPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_dpsw) +void bsp_get_dpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_dpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDPSW +* Description : Refers to the DPSW value. +* Arguments : none +* Return Value : DPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_dpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDECNT +* Description : Sets a value to DECNT. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDECNT) +void R_BSP_SetDECNT(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DECNT ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_decnt +* Description : Refers to the DECNT value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_decnt) +void bsp_get_decnt(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DECNT, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDECNT +* Description : Refers to the DECNT value. +* Arguments : none +* Return Value : DECNT value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDECNT(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_decnt((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_depc +* Description : Refers to the DEPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_depc) +void bsp_get_depc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DEPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDEPC +* Description : Refers to the DEPC value. +* Arguments : none +* Return Value : DEPC value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetDEPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_depc((uint32_t *)&ret); + return (void *)ret; +} /* End of function R_BSP_GetDECNT() */ +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +/*********************************************************************************************************************** +* Function Name: R_BSP_InitTFU +* Description : Initialize arithmetic unit for trigonometric functions. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_InitTFU) +void R_BSP_InitTFU(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R1 ) + R_BSP_ASM( MOV.L #81400H, R1 ) + R_BSP_ASM( MOV.B #7, [R1] ) + R_BSP_ASM( MOV.B #7, 1[R1] ) + R_BSP_ASM( POP R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_InitTFU() */ + +#ifdef __FPU +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSine_Cosine +* Description : Uses the trigonometric function unit to calculate the sine and cosine of an angle at the same time +* (single precision). +* Arguments : f - Value in radians from which to calculate the sine and cosine +* : sin - Address for storing the result of the sine operation +* : cos - Address for storing the result of the cosine operation +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcSine_Cosine) +void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R4 ) + R_BSP_ASM( MOV.L #81410H, R4 ) + R_BSP_ASM( MOV.L R1, 4[R4] ) + R_BSP_ASM( MOV.L 4[R4], [R2] ) + R_BSP_ASM( MOV.L [R4], [R3] ) + R_BSP_ASM( POP R4 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcSine_Cosine() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcAtan_SquareRoot +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of +* the sum of squares of these values at the same time (single precision). +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* atan2 - Address for storing the result of the arc tangent operation for y/x +* hypot - Address for storing the result of the square root of the sum of squares of x and y +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcAtan_SquareRoot) +void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSHM R5-R6 ) + R_BSP_ASM( MOV.L #81418H, R5 ) + R_BSP_ASM( MOV.L R2, [R5] ) + R_BSP_ASM( MOV.L R1, 4[R5] ) + R_BSP_ASM( MOV.L 4[R5], [R3] ) + R_BSP_ASM( MOV.L [R5], R6 ) + R_BSP_ASM( FMUL #3F1B74EEH, R6 ) + R_BSP_ASM( MOV.L R6, [R4] ) + R_BSP_ASM( POPM R5-R6 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcAtan_SquareRoot() */ +#endif /* __FPU */ +#endif /* __TFU */ +#endif /* BSP_MCU_TRIGONOMETRIC */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h new file mode 100644 index 000000000..1f418eaa4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.h +* Description : This is a file for integrating the definitions of built-in functions that differ for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.10 Added the following function. +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.11 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 08.10.2019 1.12 Modified the followind definition of intrinsic function of TFU for ICCRX. +* - R_BSP_INIT_TFU +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* : 17.12.2019 1.13 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_INTRINSIC_FUNCTIONS_H +#define R_RX_INTRINSIC_FUNCTIONS_H + +/* ---------- Maximum value and minimum value ---------- */ +#if defined(__CCRX__) + +/* signed long max(signed long data1, signed long data2) */ +#define R_BSP_MAX(x, y) max((signed long)(x), (signed long)(y)) +/* signed long min(signed long data1, signed long data2) */ +#define R_BSP_MIN(x, y) min((signed long)(x), (signed long)(y)) + +#elif defined(__GNUC__) + +/* signed long R_BSP_Max(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MAX(x, y) R_BSP_Max((signed long)(x), (signed long)(y)) +/* signed long R_BSP_Min(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MIN(x, y) R_BSP_Min((signed long)(x), (signed long)(y)) + +#elif defined(__ICCRX__) + +/* signed long __MAX(signed long, signed long) */ +#define R_BSP_MAX(x, y) __MAX((signed long)(x), (signed long)(y)) +/* signed long __MIN(signed long, signed long) */ +#define R_BSP_MIN(x, y) __MIN((signed long)(x), (signed long)(y)) + +#endif + +/* ---------- Byte switch ---------- */ +#if defined(__CCRX__) + +/* unsigned long revl(unsigned long data) */ +#define R_BSP_REVL(x) revl((unsigned long)(x)) +/* unsigned long revw(unsigned long data) */ +#define R_BSP_REVW(x) revw((unsigned long)(x)) + +#elif defined(__GNUC__) + +/* uint32_t __builtin_bswap32(uint32_t x) */ +#define R_BSP_REVL(x) __builtin_bswap32((uint32_t)(x)) +/* int __builtin_rx_revw(int) */ +#define R_BSP_REVW(x) (unsigned long)__builtin_rx_revw((int)(x)) + +#elif defined(__ICCRX__) + +/* unsigned long __REVL(unsigned long) */ +#define R_BSP_REVL(x) __REVL((unsigned long)(x)) +/* unsigned long __REVW(unsigned long) */ +#define R_BSP_REVW(x) __REVW((unsigned long)(x)) + +#endif + +/* ---------- Data Exchange ---------- */ +#if defined(__CCRX__) + +/* void xchg(signed long *data1, signed long *data2) */ +#define R_BSP_EXCHANGE(x, y) xchg((signed long *)(x), (signed long *)(y)) + +#elif defined(__GNUC__) + +/* void __builtin_rx_xchg (int *, int *) */ +#define R_BSP_EXCHANGE(x, y) __builtin_rx_xchg((int *)(x), (int *)(y)) + +#elif defined(__ICCRX__) + +/* void _builtin_xchg(signed long *, signed long *) */ +#define R_BSP_EXCHANGE(x, y) _builtin_xchg((signed long *)(x), (signed long *)(y)) + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__GNUC__) + +/* long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAB(w, x, y, z) R_BSP_MulAndAccOperation_B((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAW(w, x, y, z) R_BSP_MulAndAccOperation_W((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAL(w, x, y, z) R_BSP_MulAndAccOperation_L((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__ICCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#endif + +/* ---------- Rotation ---------- */ +#if defined(__CCRX__) + +/* unsigned long rolc(unsigned long data) */ +#define R_BSP_ROLC(x) rolc((unsigned long)(x)) +/* unsigned long rorc(unsigned long data) */ +#define R_BSP_RORC(x) rorc((unsigned long)(x)) +/* unsigned long rotl(unsigned long data, unsigned long num) */ +#define R_BSP_ROTL(x, y) rotl((unsigned long)(x), (unsigned long)(y)) +/* unsigned long rotr (unsigned long data, unsigned long num) */ +#define R_BSP_ROTR(x, y) rotr((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_ROLC(x) R_BSP_RotateLeftWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateRightWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_RORC(x) R_BSP_RotateRightWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTL(x, y) R_BSP_RotateLeft((unsigned long)(x), (unsigned long)(y)) +/* unsigned long R_BSP_RotateRight (unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTR(x, y) R_BSP_RotateRight((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* unsigned long __ROLC(unsigned long) */ +#define R_BSP_ROLC(x) __ROLC((unsigned long)(x)) +/* unsigned long __RORC(unsigned long) */ +#define R_BSP_RORC(x) __RORC((unsigned long)(x)) +/* unsigned long __ROTL(unsigned long, unsigned long) */ +#define R_BSP_ROTL(x, y) __ROTL((unsigned long)(y), (unsigned long)(x)) +/* unsigned long __ROTR(unsigned long, unsigned long) */ +#define R_BSP_ROTR(x, y) __ROTR((unsigned long)(y), (unsigned long)(x)) + +#endif + +/* ---------- Special Instructions ---------- */ +#if defined(__CCRX__) + +/* void brk(void) */ +#define R_BSP_BRK() brk() +/* void int_exception(signed long num) */ +#define R_BSP_INT(x) int_exception((signed long)(x)) +/* void wait(void) */ +#define R_BSP_WAIT() wait() +/* void nop(void) */ +#define R_BSP_NOP() nop() + +#elif defined(__GNUC__) + +/* void __builtin_rx_brk (void) */ +#define R_BSP_BRK() __builtin_rx_brk() +/* void __builtin_rx_int (int) */ +#define R_BSP_INT(x) __builtin_rx_int((int)(x)) +/* void __builtin_rx_wait (void) */ +#define R_BSP_WAIT() __builtin_rx_wait() +/* __asm("nop") */ +#define R_BSP_NOP() __asm("nop") + +#elif defined(__ICCRX__) + +/* void __break(void) */ +#define R_BSP_BRK() __break() +/* void __software_interrupt(unsigned char) */ +#define R_BSP_INT(x) __software_interrupt((unsigned char)(x)) +/* void __wait_for_interrupt(void) */ +#define R_BSP_WAIT() __wait_for_interrupt() +/* void __no_operation(void) */ +#define R_BSP_NOP() __no_operation() + +#endif + +/* ---------- Processor interrupt priority level (IPL) ---------- */ +#if defined(__CCRX__) + +/* void set_ipl(signed long level) */ +#define R_BSP_SET_IPL(x) set_ipl((signed long)(x)) +/* unsigned char get_ipl(void) */ +#define R_BSP_GET_IPL() get_ipl() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtipl (int) */ +#define R_BSP_SET_IPL(x) __builtin_rx_mvtipl((int)(x)) +/* uint32_t R_BSP_CpuInterruptLevelRead (void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_IPL() (unsigned char)R_BSP_CpuInterruptLevelRead() + +#elif defined(__ICCRX__) + +/* void __set_interrupt_level(__ilevel_t) */ +#define R_BSP_SET_IPL(x) __set_interrupt_level((__ilevel_t)(x)) +/* __ilevel_t __get_interrupt_level(void) */ +#define R_BSP_GET_IPL() (unsigned char)__get_interrupt_level() + +#endif + +/* ---------- Processor status word (PSW) ---------- */ +#if defined(__CCRX__) + +/* void set_psw(unsigned long data) */ +#define R_BSP_SET_PSW(x) set_psw((unsigned long)(x)) +/* unsigned long get_psw(void) */ +#define R_BSP_GET_PSW() get_psw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_PSW(x) __builtin_rx_mvtc(0x0, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_PSW() (unsigned long)__builtin_rx_mvfc(0x0) + +#elif defined(__ICCRX__) + +/* void __set_PSW_register(unsigned long) */ +#define R_BSP_SET_PSW(x) __set_PSW_register((unsigned long)(x)) +/* unsigned long __get_PSW_register(void) */ +#define R_BSP_GET_PSW() __get_PSW_register() + +#endif + +/* ---------- Floating-point status word (FPSW) ---------- */ +#ifdef __FPU +#if defined(__CCRX__) + +/* void set_fpsw(unsigned long data) */ +#define R_BSP_SET_FPSW(x) set_fpsw((unsigned long)(x)) +/* unsigned long get_fpsw(void) */ +#define R_BSP_GET_FPSW() get_fpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FPSW(x) __builtin_rx_mvtc(0x3, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FPSW() (unsigned long)__builtin_rx_mvfc(0x3) + +#elif defined(__ICCRX__) + +/* void __set_FPSW_register(unsigned long) */ +#define R_BSP_SET_FPSW(x) __set_FPSW_register((unsigned long)(x)) +/* unsigned long __get_FPSW_register(void) */ +#define R_BSP_GET_FPSW() __get_FPSW_register() + +#endif +#endif + +/* ---------- User Stack Pointer (USP) ---------- */ +#if defined(__CCRX__) + +/* void set_usp(void *data) */ +#define R_BSP_SET_USP(x) set_usp((void *)(x)) +/* void *get_usp(void) */ +#define R_BSP_GET_USP() get_usp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_USP(x) __builtin_rx_mvtc(0x2, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_USP() (void *)__builtin_rx_mvfc(0x2) + +#elif defined(__ICCRX__) + +/* void __set_USP_register(unsigned long) */ +#define R_BSP_SET_USP(x) __set_USP_register((unsigned long)(x)) +/* unsigned long __get_USP_register(void) */ +#define R_BSP_GET_USP() (void *)__get_USP_register() + +#endif + +/* ---------- Interrupt Stack Pointer (ISP) ---------- */ +#if defined(__CCRX__) + +/* void set_isp(void *data) */ +#define R_BSP_SET_ISP(x) set_isp((void *)(x)) +/* void *get_isp(void) */ +#define R_BSP_GET_ISP() get_isp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_ISP(x) __builtin_rx_mvtc(0xA, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_ISP() (void *)__builtin_rx_mvfc(0xA) + +#elif defined(__ICCRX__) + +/* void __set_ISP_register(unsigned long) */ +#define R_BSP_SET_ISP(x) __set_ISP_register((unsigned long)(x)) +/* unsigned long __get_ISP_register(void) */ +#define R_BSP_GET_ISP() (void *)__get_ISP_register() + +#endif + +/* ---------- Interrupt Table Register (INTB) ---------- */ +#if defined(__CCRX__) + +/* void set_intb(void *data) */ +#define R_BSP_SET_INTB(x) set_intb((void *)(x)) +/* void *get_intb(void) */ +#define R_BSP_GET_INTB() get_intb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_INTB(x) __builtin_rx_mvtc(0xC, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_INTB() (void *)__builtin_rx_mvfc(0xC) + +#elif defined(__ICCRX__) + +/* void __set_interrupt_table(unsigned long address) */ +#define R_BSP_SET_INTB(x) __set_interrupt_table((unsigned long)(x)) +/* unsigned long __get_interrupt_table(void); */ +#define R_BSP_GET_INTB() (void *)__get_interrupt_table() + +#endif + +/* ---------- Backup PSW (BPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_bpsw(unsigned long data) */ +#define R_BSP_SET_BPSW(x) set_bpsw((unsigned long)(x)) +/* unsigned long get_bpsw(void) */ +#define R_BSP_GET_BPSW() get_bpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPSW(x) __builtin_rx_mvtc(0x8, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPSW() (unsigned long)__builtin_rx_mvfc(0x8) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPSW(x) R_BSP_SetBPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetBPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPSW() R_BSP_GetBPSW() + +#endif + +/* ---------- Backup PC (BPC) ---------- */ +#if defined(__CCRX__) + +/* void set_bpc(void *data) */ +#define R_BSP_SET_BPC(x) set_bpc((void *)(x)) +/* void *get_bpc(void) */ +#define R_BSP_GET_BPC() get_bpc() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPC(x) __builtin_rx_mvtc(0x9, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPC() (void *)__builtin_rx_mvfc(0x9) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPC(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPC(x) R_BSP_SetBPC((void *)(x)) +/* void *R_BSP_GetBPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPC() R_BSP_GetBPC() + +#endif + +/* ---------- Fast Interrupt Vector Register (FINTV) ---------- */ +#if defined(__CCRX__) + +/* void set_fintv(void *data) */ +#define R_BSP_SET_FINTV(x) set_fintv((void *)(x)) +/* void *get_fintv(void) */ +#define R_BSP_GET_FINTV() get_fintv() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FINTV(x) __builtin_rx_mvtc(0xB, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FINTV() (void *)__builtin_rx_mvfc(0xB) + +#elif defined(__ICCRX__) + +/* void __set_FINTV_register(__fast_int_f) */ +#define R_BSP_SET_FINTV(x) __set_FINTV_register((__fast_int_f)(x)) +/* __fast_int_f __get_FINTV_register(void) */ +#define R_BSP_GET_FINTV() (void *)__get_FINTV_register() + +#endif + +/* ---------- Significant 64-bit multiplication ---------- */ +#if defined(__CCRX__) + +/* signed long long emul(signed long data1, signed long data2) */ +#define R_BSP_EMUL(x, y) emul((signed long)(x), (signed long)(y)) +/* unsigned long long emulu(unsigned long data1, unsigned long data2) */ +#define R_BSP_EMULU(x, y) emulu((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#endif + +/* ---------- Processor mode (PM) ---------- */ +#if defined(__CCRX__) + +/* void chg_pmusr(void) */ +#define R_BSP_CHG_PMUSR() chg_pmusr() + +#elif defined(__GNUC__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#elif defined(__ICCRX__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#endif + +/* ---------- Accumulator (ACC) ---------- */ +#if defined(__CCRX__) + +/* void set_acc(signed long long data) */ +#define R_BSP_SET_ACC(x) set_acc((signed long long)(x)) +/* signed long long get_acc(void) */ +#define R_BSP_GET_ACC() get_acc() + +#elif defined(__GNUC__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#endif + +/* ---------- Control of the interrupt enable bits ---------- */ +#if defined(__CCRX__) + +/* void setpsw_i(void) */ +#define R_BSP_SETPSW_I() setpsw_i() +/* void clrpsw_i(void) */ +#define R_BSP_CLRPSW_I() clrpsw_i() + +#elif defined(__GNUC__) + +/* void __builtin_rx_setpsw (int) */ +#define R_BSP_SETPSW_I() __builtin_rx_setpsw('I') +/* void __builtin_rx_clrpsw (int) */ +#define R_BSP_CLRPSW_I() __builtin_rx_clrpsw('I') + +#elif defined(__ICCRX__) + +/* void __enable_interrupt(void) */ +#define R_BSP_SETPSW_I() __enable_interrupt() +/* void __disable_interrupt(void) */ +#define R_BSP_CLRPSW_I() __disable_interrupt() + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long macl(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw1(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw2(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__GNUC__) + +/* long R_BSP_MulAndAccOperation_2byte(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACL(x, y, z) R_BSP_MulAndAccOperation_2byte((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint1(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW1(x, y, z) R_BSP_MulAndAccOperation_FixedPoint1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint2(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW2(x, y, z) R_BSP_MulAndAccOperation_FixedPoint2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__ICCRX__) + +/* long __macl(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) __macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw1(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) __macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw2(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) __macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#endif + +/* ---------- Exception Table Register (EXTB) ---------- */ +#ifdef BSP_MCU_EXCEPTION_TABLE +#if defined(__CCRX__) + +/* void set_extb(void *data) */ +#define R_BSP_SET_EXTB(x) set_extb((void *)(x)) +/* void *get_extb(void) */ +#define R_BSP_GET_EXTB() get_extb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_EXTB(x) __builtin_rx_mvtc(0xD, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_EXTB() (void *)__builtin_rx_mvfc(0xD) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetEXTB(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_EXTB(x) R_BSP_SetEXTB((void *)(x)) +/* void *R_BSP_GetEXTB(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_EXTB() R_BSP_GetEXTB() + +#endif +#endif + +/* ---------- Bit Manipulation ---------- */ +#if defined(__CCRX__) + +/* void __bclr(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_CLEAR(x, y) __bclr((unsigned char *)(x), (unsigned long)(y)) +/* void __bset(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_SET(x, y) __bset((unsigned char *)(x), (unsigned long)(y)) +/* void __bnot(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_REVERSE(x, y) __bnot((unsigned char *)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#elif defined(__ICCRX__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/* ---------- Double-Precision Floating-Point Status Word (DPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_dpsw(unsigned long data) */ +#define R_BSP_SET_DPSW(x) __set_dpsw((unsigned long)(x)) +/* unsigned long get_dpsw(void) */ +#define R_BSP_GET_DPSW() __get_dpsw() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#endif + +/* ---------- Double-precision floating-point exception handling operation control register (DECNT) ---------- */ +#if defined(__CCRX__) + +/* void __set_decnt(unsigned long data) */ +#define R_BSP_SET_DECNT(x) __set_decnt((unsigned long)(x)) +/* unsigned long __get_decnt(void) */ +#define R_BSP_GET_DECNT() __get_decnt() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#endif + +/* ---------- Double-precision floating-point exception program counter (DEPC) ---------- */ +#if defined(__CCRX__) + +/* void *__get_depc(void) */ +#define R_BSP_GET_DEPC() __get_depc() + +#elif defined(__GNUC__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#elif defined(__ICCRX__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#endif +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */ +#ifdef BSP_MCU_TRIGONOMETRIC +#if defined(__CCRX__) + +/* void __init_tfu(void) */ +#define R_BSP_INIT_TFU() __init_tfu() + +#elif defined(__GNUC__) + +/* void R_BSP_InitTFU(void) (This macro uses API function of BSP.) */ +#define R_BSP_INIT_TFU() R_BSP_InitTFU() + +#elif defined(__ICCRX__) + +/* Invalid for ICCRX. + Because the initilaze function of TFU is called automatically when the TFU function is called. */ +#define R_BSP_INIT_TFU() + +#endif + +/* ---------- Calculating the Sine and Cosine of an angle at the same time(single precision) ---------- */ +#if defined(__CCRX__) + +/* void __sincosf(float f, float *sin, float *cos) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) R_BSP_CalcSine_Cosine((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#endif + +/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */ +#if defined(__CCRX__) + +/* void __atan2hypotf(float y, float x, float *atan2, float *hypot) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) R_BSP_CalcAtan_SquareRoot((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#endif +#endif /* BSP_MCU_TRIGONOMETRIC */ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2); +signed long R_BSP_Min(signed long data1, signed long data2); +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2); +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2); +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2); +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data); +unsigned long R_BSP_RotateRightWithCarry(unsigned long data); +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num); +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num); +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count); +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2); +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2); +void R_BSP_SetACC(signed long long data); +signed long long R_BSP_GetACC(void); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +R_BSP_ATTRIB_INLINE_ASM void R_BSP_ChangeToUserMode(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPSW(uint32_t data); +uint32_t R_BSP_GetBPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPC(void * data); +void *R_BSP_GetBPC(void); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetEXTB(void * data); +void *R_BSP_GetEXTB(void); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitSet(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitClear(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitReverse(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccHiLong(int32_t data); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccLoLong(int32_t data); +int32_t R_BSP_MoveFromAccHiLong(void); +int32_t R_BSP_MoveFromAccMiLong(void); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDPSW(uint32_t data); +uint32_t R_BSP_GetDPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDECNT(uint32_t data); +uint32_t R_BSP_GetDECNT(void); +void *R_BSP_GetDEPC(void); +#endif +#endif +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_InitTFU(void); +#ifdef __FPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot); +#endif /* __FPU */ +#endif /* __TFU */ +#endif + +/* End of multiple inclusion prevention macro */ +#endif /* R_RX_INTRINSIC_FUNCTIONS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_typedefs.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_typedefs.h new file mode 100644 index 000000000..34f975d0b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/r_typedefs.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_typedefs.h +* Description : This has fixed-width integer and bool support for compilers that are not C99 compliant and do not have +* the header files stdint.h, stdbool.h, and stddef.h. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 18.09.2012 1.00 First Release +* : 21.06.2013 1.10 Added NULL and size_t support. +* : 22.11.2013 1.11 Changed size_t to 'unsigned long' from 'unsigned int'. +* : 28.02.2019 1.12 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +#define bool (_Bool) +#define false (0) +#define true (1) +#define NULL (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef signed long long int64_t; +typedef unsigned long long uint64_t; +typedef unsigned int _Bool; +typedef unsigned long size_t; + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/reset_program.S b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/reset_program.S new file mode 100644 index 000000000..9b753709a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/reset_program.S @@ -0,0 +1,183 @@ +;;/*********************************************************************************************************************** +;;* DISCLAIMER +;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +;;* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +;;* applicable laws, including copyright laws. +;;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +;;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +;;* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +;;* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +;;* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +;;* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;;* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +;;* this software. By using this software, you agree to the additional terms and conditions found by accessing the +;;* following link: +;;* http://www.renesas.com/disclaimer +;;* +;;* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +;;***********************************************************************************************************************/ +;;/*********************************************************************************************************************** +;;* File Name : reset_program.asm +;;* Description : Defines post-reset routines that are used to configure the MCU prior to the main program starting. +;;* This is where the program counter starts on power-up or reset. +;;***********************************************************************************************************************/ +;;/*********************************************************************************************************************** +;;* History : DD.MM.YYYY Version Description +;;* : 28.02.2019 1.00 First Release +;;***********************************************************************************************************************/ + + .if __GNUC__ + +;;reset_program.asm + + .list + .section .text + .global _PowerON_Reset_PC ;;global Start routine + .global _PowerON_Reset ;;for backward compatibility + + .extern _PowerON_Reset_PC_Prg ;;external Power ON Reset main function in RESETPRG.C + .extern _data + .extern _mdata + .extern _ebss + .extern _bss + .extern _edata + .extern _ustack + .extern _istack + .extern _exit + + +_PowerON_Reset_PC : +_PowerON_Reset : +;;initialise user stack pointer + mvtc #_ustack,USP + +;;initialise interrupt stack pointer + mvtc #_istack,ISP + +;;jump to Power ON Reset main function in RESETPRG.C + bra _PowerON_Reset_PC_Prg + +;;init section + .global __INITSCT + .type __INITSCT,@function +__INITSCT: + +;;load data section from ROM to RAM + pushm r1-r3 + mov #_mdata,r2 ;;src ROM address of data section in R2 + mov #_data,r1 ;;dest start RAM address of data section in R1 + mov #_edata,r3 ;;end RAM address of data section in R3 + sub r1,r3 ;;size of data section in R3 (R3=R3-R1) + smovf ;;block copy R3 bytes from R2 to R1 + +;;bss initialisation : zero out bss + mov #00h,r2 ;;load R2 reg with zero + mov #_ebss, r3 ;;store the end address of bss in R3 + mov #_bss, r1 ;;store the start address of bss in R1 + sub r1,r3 ;;size of bss section in R3 (R3=R3-R1) + sstr.b + popm r1-r3 + rts + +#ifdef CPPAPP + +;;init global class object + .global __CALL_INIT + .type __CALL_INIT,@function +__CALL_INIT: + bra __rx_init + + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + bra.a _rx_run_inilist + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + bra.a _rx_run_inilist + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + ;;fall through + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + bra.b next_inilist +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + bsr.a _rx_run_fini_array + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + bsr.a _rx_run_preinit_array + bsr.a _rx_run_init_array + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +;;call to exit +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + + .endif + + .end + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/resetprg.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/resetprg.c new file mode 100644 index 000000000..d6fa1bfcd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/resetprg.c @@ -0,0 +1,365 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : resetprg.c +* Description : Defines post-reset routines that are used to configure the MCU prior to the main program starting. +* This is where the program counter starts on power-up or reset. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_PSW_INIT +* - BSP_PRV_FPSW_INIT +* - BSP_PRV_FPU_ROUND +* - BSP_PRV_FPU_DENOM +* Added following macro definitions. +* - BSP_PRV_DPSW_INIT +* : 26.07.2019 3.01 Added vbatt_voltage_stability_wait function. +* : 08.10.2019 3.10 Changed for added support of Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) +/* Defines MCU configuration functions used in this file */ +#include <_h_c_lib.h> +#endif /* defined(__CCRX__) */ + +/* Define the target platform */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + +#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX +#pragma section P PS +#pragma section B BS +#pragma section C CS +#pragma section D DS +#else +#include "ri_cmt.h" /* Generated by cfg600 */ +#endif /* BSP_CFG_RENESAS_RTOS_USED */ + +#else /* BSP_CFG_RTOS_USED!=4 */ + +/* Declaration of stack size. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +R_BSP_PRAGMA_STACKSIZE_SU(BSP_CFG_USTACK_BYTES) +#endif +R_BSP_PRAGMA_STACKSIZE_SI(BSP_CFG_ISTACK_BYTES) + +#endif/* BSP_CFG_RTOS_USED */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + #define BSP_PRV_PSW_INIT (0x00000000) /* Supervisor mode & Disable Interrupt */ +#else /* BSP_CFG_RTOS_USED!=4 */ +/* If the user chooses only 1 stack then the 'U' bit will not be set and the CPU will always use the interrupt stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 + #define BSP_PRV_PSW_INIT (0x00030000) +#else + #define BSP_PRV_PSW_INIT (0x00010000) +#endif +#endif/* BSP_CFG_RTOS_USED */ + +#if defined(__CCRX__) || defined(__GNUC__) + +#ifdef BSP_MCU_FLOATING_POINT + /* Initialize FPSW for floating-point operations */ +#define BSP_PRV_FPSW_INIT (0x00000000) /* Currently nothing set by default. */ +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + /* Initialize DPSW for double-precision floating-point operations */ +#define BSP_PRV_DPSW_INIT (0x00000000) /* Currently nothing set by default. */ +#endif + +#ifdef __ROZ +#define BSP_PRV_FPU_ROUND (0x00000001) /* Let FPSW RMbits=01 (round to zero) */ +#else +#define BSP_PRV_FPU_ROUND (0x00000000) /* Let FPSW RMbits=00 (round to nearest) */ +#endif +#ifdef __DOFF +#define BSP_PRV_FPU_DENOM (0x00000100) /* Let FPSW DNbit=1 (denormal as zero) */ +#else +#define BSP_PRV_FPU_DENOM (0x00000000) /* Let FPSW DNbit=0 (denormal as is) */ +#endif +#endif + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +Pre-processor Directives +***********************************************************************************************************************/ +/* Set this as the entry point from a power-on reset */ +#if defined(__CCRX__) +#pragma entry PowerON_Reset_PC +#endif /* defined(__CCRX__) */ + +/*********************************************************************************************************************** +External function Prototypes +***********************************************************************************************************************/ +/* Initialize C runtime environment */ +extern void _INITSCT(void); + +#if defined(CPPAPP) +/* Initialize C++ global class object */ +extern void _CALL_INIT(void); +#endif + +#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED != 0 +/* If user is requesting warm start callback functions then these are the prototypes. */ +void BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(void); +#endif + +#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED != 0 +/* If user is requesting warm start callback functions then these are the prototypes. */ +void BSP_CFG_USER_WARM_START_POST_C_FUNCTION(void); +#endif + +#if BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ +/* A function is used to create a main task, rtos's objects required to be available in advance. */ +extern void Processing_Before_Start_Kernel(void); +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +/* kernel initialization routine */ +extern void vsta_knl(void); +#endif/* BSP_CFG_RTOS_USED */ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Power-on reset function declaration */ +R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION); + +/* Main program function declaration */ +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ +extern void R_BSP_MAIN_FUNCTION(void); +#endif + +/*********************************************************************************************************************** +* Function name: PowerON_Reset_PC +* Description : This function is the MCU's entry point from a power-on reset. +* The following steps are taken in the startup code: +* 1. The User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) are both set immediately after entry +* to this function. The USP and ISP stack sizes are set in the file bsp_config.h. +* 2. The interrupt vector base register is set to point to the beginning of the relocatable interrupt +* vector table. +* 3. The MCU is setup for floating point operations by setting the initial value of the Floating Point +* Status Word (FPSW). +* 4. The MCU operating frequency is set by configuring the Clock Generation Circuit (CGC) in +* operating_frequency_set. +* 5. Calls are made to functions to setup the C runtime environment which involves initializing all +* initialed data, zeroing all uninitialized variables, and configuring STDIO if used +* (calls to _INITSCT and init_iolib). +* 6. Board-specific hardware setup, including configuring I/O pins on the MCU, in hardware_setup. +* 7. Global interrupts are enabled by setting the I bit in the Program Status Word (PSW), and the stack +* is switched from the ISP to the USP. The initial Interrupt Priority Level is set to zero, enabling +* any interrupts with a priority greater than zero to be serviced. +* 8. The processor is optionally switched to user mode. To run in user mode, set the macro +* BSP_CFG_RUN_IN_USER_MODE above to a 1. +* 9. The bus error interrupt is enabled to catch any accesses to invalid or reserved areas of memory. +* +* Once this initialization is complete, the user's main() function is called. It should not return. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION) +{ + /* Stack pointers are setup prior to calling this function - see comments above */ + + /* You can use auto variables in this function but such variables other than register variables + * will be unavailable after you change the stack from the I stack to the U stack (if change). */ + + /* The bss sections have not been cleared and the data sections have not been initialized + * and constructors of C++ objects have not been executed until the _INITSCT() is executed. */ +#if defined(__GNUC__) +#if BSP_CFG_USER_STACK_ENABLE == 1 + INTERNAL_NOT_USED(ustack_area); +#endif + INTERNAL_NOT_USED(istack_area); +#endif + +#if defined(__CCRX__) || defined(__GNUC__) + + /* Initialize the Interrupt Table Register */ + R_BSP_SET_INTB(R_BSP_SECTOP_INTVECTTBL); + +#ifdef BSP_MCU_EXCEPTION_TABLE + /* Initialize the Exception Table Register */ + R_BSP_SET_EXTB(R_BSP_SECTOP_EXCEPTVECTTBL); +#endif + +#ifdef BSP_MCU_FLOATING_POINT +#ifdef __FPU + /* Initialize the Floating-Point Status Word Register. */ + R_BSP_SET_FPSW(BSP_PRV_FPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM); +#endif +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU + /* Initialize the Double-Precision Floating-Point Status Word Register. */ + R_BSP_SET_DPSW(BSP_PRV_DPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM); +#endif +#endif + + /* Initializes the trigonometric function unit. */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU + R_BSP_INIT_TFU(); +#endif +#endif + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + + /* Wait for power voltage stabilization of VBATT function. */ +#if (defined(BSP_CFG_VBATT_ENABLE) && (BSP_CFG_VBATT_ENABLE == 0)) + vbatt_voltage_stability_wait(); +#endif + + /* Switch to high-speed operation */ + mcu_clock_setup(); + + /* If the warm start Pre C runtime callback is enabled, then call it. */ +#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED == 1 + BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(); +#endif + + /* Initialize C runtime environment */ + _INITSCT(); + +#if defined(CPPAPP) + /* Initialize C++ global class object */ + _CALL_INIT(); +#endif + + /* Initialize RAM */ + bsp_ram_initialize(); + + /* If the warm start Post C runtime callback is enabled, then call it. */ +#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED == 1 + BSP_CFG_USER_WARM_START_POST_C_FUNCTION(); +#endif + +#if BSP_CFG_IO_LIB_ENABLE == 1 + /* Comment this out if not using I/O lib */ +#if defined(__CCRX__) + init_iolib(); +#endif /* defined(__CCRX__) */ +#endif + + /* Initialize MCU interrupt callbacks. */ + bsp_interrupt_open(); + + /* Initialize register protection functionality. */ + bsp_register_protect_open(); + + /* Configure the MCU and board hardware */ + hardware_setup(); + + /* Enable interrupt and select the I stack or the U stack */ + R_BSP_SET_PSW(BSP_PRV_PSW_INIT); + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* Does not change the MCU's user mode to user in Renesas RTOS. */ +#else /* BSP_CFG_RTOS_USED != 4 */ +#if BSP_CFG_RUN_IN_USER_MODE == 1 + /* Change the MCU's user mode from supervisor to user */ + #if BSP_CFG_USER_STACK_ENABLE == 1 + R_BSP_CHG_PMUSR(); + #else + #error "Settings of BSP_CFG_RUN_IN_USER_MODE and BSP_CFG_USER_STACK_ENABLE are inconsistent with each other." + #endif +#endif /* BSP_CFG_RUN_IN_USER_MODE */ +#endif /* BSP_CFG_RTOS_USED */ + + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR); + +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ + /* Call the main program function (should not return) */ + R_BSP_MAIN_FUNCTION(); +#elif BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ + /* Lock the channel that system timer of RTOS is using. */ + #if (((BSP_CFG_RTOS_SYSTEM_TIMER) >=0) && ((BSP_CFG_RTOS_SYSTEM_TIMER) <= 3)) + if (R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + BSP_CFG_RTOS_SYSTEM_TIMER)) == false) + { + /* WAIT_LOOP */ + while(1); + } + #else + #error "Setting BSP_CFG_RTOS_SYSTEM_TIMER is invalid." + #endif + + /* Prepare the necessary tasks, FreeRTOS's resources... required to be executed at the beginning + * after vTaskStarScheduler() is called. Other tasks can also be created after starting scheduler at any time */ + Processing_Before_Start_Kernel(); + + /* Call the kernel startup (should not return) */ + vTaskStartScheduler(); +#elif BSP_CFG_RTOS_USED == 2 /* SEGGER embOS */ +#elif BSP_CFG_RTOS_USED == 3 /* Micrium MicroC/OS */ +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4 + /* Lock a timer resource by r_bsp, if using time function on RTOS. */ + if(R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + _RI_CLOCK_TIMER)) == false) + { + /* WAIT_LOOP */ + while(1); + } + /* Initialize CMT for RI600V4 */ + _RI_init_cmt(); +#else + /* When RI600PX, the above are in _RI_init_cmt_knl called from the kernel. */ +#endif + /* Make sure to disable interrupt. */ + R_BSP_CLRPSW_I();/* clrpsw_i() */ + vsta_knl(); +#endif/* BSP_CFG_RTOS_USED */ + +#if BSP_CFG_IO_LIB_ENABLE == 1 + /* Comment this out if not using I/O lib - cleans up open files */ +#if defined(__CCRX__) + close_all(); +#endif /* defined(__CCRX__) */ +#endif + + /* Infinite loop is intended here. */ + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Put a breakpoint here if you want to catch an exit of main(). */ + R_BSP_NOP(); + } +} /* End of function PowerON_Reset_PC() */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +/* Definition of Kernel data section */ +#include "kernel_ram.h" /* generated by cfg600 */ +#include "kernel_rom.h" /* generated by cfg600 */ +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/sbrk.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/sbrk.c new file mode 100644 index 000000000..30bf1038f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/sbrk.c @@ -0,0 +1,120 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : sbrk.c +* Description : Configures the MCU heap memory. The size of the heap is defined by the macro HEAPSIZE below. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 3.01 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "sbrk.h" + +/* Only use this file if heap is enabled in r_bsp_config. */ +#if BSP_CFG_HEAP_BYTES > 0 + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if defined(__CCRX__) || defined(__GNUC__) + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Declare memory heap area */ +static u_heap_type_t s_heap_area; + +/* End address allocated by sbrk (CC-RX and GNURX+NEWLIB) */ +static int8_t *sp_brk=(int8_t *)&s_heap_area; + +#if defined(__GNUC__) +/* Start address of allocated heap area (GNURX+OPTLIB only) */ +int8_t *_heap_of_memory=(int8_t *)&s_heap_area; +/* End address of allocated heap area (GNURX+OPTLIB only) */ +int8_t *_last_heap_object=(int8_t *)&s_heap_area; +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function name: sbrk +* Description : This function configures MCU memory area allocation. (CC-RX and GNURX+NEWLIB) +* Arguments : size - +* assigned area size +* Return value : Start address of allocated area (pass) +* -1 (failure) +***********************************************************************************************************************/ +int8_t *sbrk(size_t size) +{ + int8_t *p_area; + + if ((sp_brk + size) > (s_heap_area.heap + BSP_CFG_HEAP_BYTES)) + { + /* Empty area size */ + p_area = (int8_t *)-1; + } + else + { + /* Area assignment */ + p_area = sp_brk; + + /* End address update */ + sp_brk += size; + } + + /* Return result */ + return p_area; +} /* End of function sbrk() */ + +#if defined(__GNUC__) +/*********************************************************************************************************************** +* Function name: _top_of_heap +* Description : This function returns end address of reserved heap area. (GNURX+OPTLIB only) +* Arguments : none +* Return value : End address of reserved heap area +***********************************************************************************************************************/ +int8_t *_top_of_heap(void) +{ + return (int8_t *)(s_heap_area.heap + BSP_CFG_HEAP_BYTES); +} /* End of function End of function sbrk()() */ +#endif /* defined(__GNUC__) */ + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +#endif /* BSP_CFG_HEAP_BYTES */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/sbrk.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/sbrk.h new file mode 100644 index 000000000..c05b6d191 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/all/sbrk.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : sbrk.h +* Description : Configures the MCU heap memory. The size of the heap is defined by the macro HEAPSIZE below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_common.h" +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef SBRK_H +#define SBRK_H + +/* Only use this file if heap is enabled in r_bsp_config. */ +#if BSP_CFG_HEAP_BYTES > 0 + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if defined(__CCRX__) || defined(__GNUC__) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef union +{ + int32_t dummy; /* Dummy for 4-byte boundary */ + int8_t heap[BSP_CFG_HEAP_BYTES]; /* Declaration of the area managed by sbrk*/ +} u_heap_type_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/* const size_t _sbrk_size= // Specifies the minimum unit of */ +/* the defined heap area */ +int8_t *_s1ptr; + +/* Memory allocation function prototype declaration (CC-RX and GNURX+NEWLIB) */ +int8_t *sbrk(size_t size); + +#if defined(__GNUC__) +/* Memory address function prototype declaration (GNURX+OPTLIB only) */ +int8_t *_top_of_heap(void); +#endif /* defined(__GNUC__) */ + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +#endif /* BSP_CFG_HEAP_BYTES */ + +#endif /* SBRK_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c new file mode 100644 index 000000000..f8c4a0f3c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c @@ -0,0 +1,1082 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.c +* Description : Contains clock specific routines +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Removed unnecessary processing from the clock_source_select fucntion. +* : 17.12.2019 1.02 Fixed warning of clock_source_select function with IAR compiler. +* : 14.02.2020 1.03 Fixed warning of clock_source_select function with CCRX and IAR compiler. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_CKSEL_LOCO (0x0) +#define BSP_PRV_CKSEL_HOCO (0x1) +#define BSP_PRV_CKSEL_MAIN_OSC (0x2) +#define BSP_PRV_CKSEL_SUBCLOCK (0x3) +#define BSP_PRV_CKSEL_PLL (0x4) + +#define BSP_PRV_NORMALIZE_X10 (10) /* used to avoid floating point arithmetic */ + +/* This macro runs or stops the low-speed on-chip oscillator(LOCO). + If the following conditions are satisfied, LOCO will operate. + 1. System clock source is LOCO. + 2. Clock output enable and CLKOUT source is LOCO. + */ +#if (BSP_CFG_CLOCK_SOURCE == 0) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 0)) + #define BSP_PRV_LOCO_CLK_OPERATING (1) /* LOCO is operating. */ +#else + #define BSP_PRV_LOCO_CLK_OPERATING (0) /* LOCO is stopped. */ +#endif + +/* This macro runs or stops the high-speed on-chip oscillator(HOCO). + If the following conditions are satisfied, HOCO will operate. + 1. System clock source is HOCO. + 2. System clock source is PLL circuit. PLL source is HOCO. + 3. PHY clock source is PLL circuit. PLL source is HOCO. + 4. PHY clock source is PPLL circuit. PPLL source is HOCO. + 5. Clock output enable and clock output source is HOCO. + 6. Clock output enable and clock output source is PLL circuit. PLL source is HOCO. + 7. Clock output enable and clock output source is PPLL circuit. PPLL source is HOCO. + */ +#if (BSP_CFG_CLOCK_SOURCE == 1) \ + || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 0) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 1) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6) && (BSP_CFG_PLL_SRC == 1)) + #define BSP_PRV_HOCO_CLK_OPERATING (1) /* HOCO is operating. */ +#else + #define BSP_PRV_HOCO_CLK_OPERATING (0) /* HOCO is stopped. */ +#endif + +/* This macro runs or stops the Main-clock oscillator. + If the following conditions are satisfied, Main-clock oscillator will operate. + 1. System clock source is Main-clock oscillator. + 2. System clock source is PLL circuit. PLL source is Main-clock oscillator. + 3. USB clock source is PPLL circuit. PPLL source is Main-clock oscillator. + 4. PHY clock source is PLL circuit. PLL source is Main-clock oscillator. + 5. PHY clock source is PPLL circuit. PPLL source is Main-clock oscillator. + 6. Clock output enable and clock output source is Main-clock oscillator. + 7. Clock output enable and clock output source is PLL circuit. PLL source is Main-clock oscillator. + 8. Clock output enable and clock output source is PPLL circuit. PPLL source is Main-clock oscillator. + */ +#if (BSP_CFG_CLOCK_SOURCE == 2) \ + || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_USB_CLOCK_SOURCE == 3) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 0) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 1) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 2)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6) && (BSP_CFG_PLL_SRC == 0)) + #define BSP_PRV_MAIN_CLK_OPERATING (1) /* Main-clock oscillator is operating. */ +#else + #define BSP_PRV_MAIN_CLK_OPERATING (0) /* Main-clock oscillator is stopped. */ +#endif + +/* This macro runs or stops the Sub-clock oscillator. + If the following conditions are satisfied, Sub-clock oscillator will operate. + 1. System clock source is Sub-clock oscillator. + 2. Clock output enable and clock output source is Sub-clock oscillator. + */ +#if (BSP_CFG_CLOCK_SOURCE == 3) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 3)) + #define BSP_PRV_SUB_CLK_OPERATING (1) /* Sub-clock oscillator is operating. */ +#else /* Clock source is not Sub-clock oscillator. */ + #define BSP_PRV_SUB_CLK_OPERATING (0) /* Sub-clock oscillator is stopped. */ +#endif + +/* This macro runs or stops the PLL circuit. + If the following conditions are satisfied, PLL circuit will operate. + 1. System clock source is PLL circuit. + 2. PHY clock source is PLL circuit. + 3. Clock output enable and clock output source is PLL circuit. + */ +#if (BSP_CFG_CLOCK_SOURCE == 4) \ + || (BSP_CFG_PHY_CLOCK_SOURCE == 0) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4)) + #define BSP_PRV_PLL_CLK_OPERATING (1) /* PLL circuit is operating. */ +#else /* PLL is not used as clock source. */ + #define BSP_PRV_PLL_CLK_OPERATING (0) /* PLL circuit is stopped. */ +#endif + +/* This macro runs or stops the PPLL circuit. + If the following conditions are satisfied, PPLL circuit will operate. + 1. USB clock source is PPLL circuit. + 2. PHY clock source is PPLL circuit. + 3. Clock output enable and clock output source is PPLL circuit. + */ +#if (BSP_CFG_USB_CLOCK_SOURCE == 3) \ + || (BSP_CFG_PHY_CLOCK_SOURCE == 1) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6)) + #define BSP_PRV_PPLL_CLK_OPERATING (1) /* PPLL circuit is operating. */ +#else /* PPLL is not used for USB clock. */ + #define BSP_PRV_PPLL_CLK_OPERATING (0) /* PPLL circuit is stopped. */ +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +static void operating_frequency_set(void); +static void clock_source_select(void); +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/* CLKOUT initial configuration function declaration */ +static void bsp_clkout_initial_configure(void); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function Name: get_iclk_freq_hz +* Description : Return the current ICLK frequency in Hz. Called by R_BSP_GetIClkFreqHz(). +* The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to +* determine the ICLK frequency we need to first find the current system clock source and then, +* in some cases where the clock source can be configured for multiple frequencies, calculate the +* frequency at which it is currently running. +* Arguments : None +* Return Value : uint32_t - the iclk frequency in Hz +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void) +{ + uint32_t sys_clock_src_freq; + uint32_t pll_multiplier; + uint32_t pll_source_freq; + uint32_t hoco_frequency[3] = {16000000, 18000000, 20000000}; + + /* Casting is valid because it matches the type to the retern value. */ + uint8_t cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL; + + switch (cksel) + { + case BSP_PRV_CKSEL_LOCO: + sys_clock_src_freq = BSP_LOCO_HZ; + break; + + case BSP_PRV_CKSEL_HOCO: + + /* Set HOCO frequency. */ + sys_clock_src_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + break; + + case BSP_PRV_CKSEL_MAIN_OSC: + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + + case BSP_PRV_CKSEL_SUBCLOCK: + sys_clock_src_freq = BSP_SUB_CLOCK_HZ; + break; + + case BSP_PRV_CKSEL_PLL: + + /* The RX72N have two possible sources for the PLL */ + + /* Casting is valid because it matches the type to the retern value. */ + pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2); + + /* Default to the MAIN OSC as the PLL source */ + pll_source_freq = BSP_CFG_XTAL_HZ; + + /* If 1 then the HOCO is the PLL source */ + if (0x1 == SYSTEM.PLLCR.BIT.PLLSRCSEL) + { + /* Set HOCO frequency. */ + pll_source_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + } + + /* Casting is valid because it matches the type to the retern value. */ + sys_clock_src_freq = ((pll_source_freq / (((uint32_t)(SYSTEM.PLLCR.BIT.PLIDIV + 1)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier); + break; + + default: + + /* Should never arrive here. Use the Main OSC freq as a default... */ + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + } + + /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */ + return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK)); +} /* End of function get_iclk_freq_hz() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +* Function name: mcu_clock_setup +* Description : Contains clock functions called at device restart. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void mcu_clock_setup(void) +{ + /* Switch to high-speed operation */ + operating_frequency_set(); + +#if BSP_CFG_CLKOUT_OUTPUT != 0 + bsp_clkout_initial_configure(); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +} /* End of function mcu_clock_setup() */ + +/*********************************************************************************************************************** +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void operating_frequency_set (void) +{ + /* Used for constructing value to write to SCKCR, SCKCR2, and SCKCR3 registers. */ + uint32_t tmp_clock = 0; + uint32_t tmp_restore_clock = 0; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Select the clock based upon user's choice. */ + clock_source_select(); + + /* Figure out setting for FCK bits. */ +#if BSP_CFG_FCK_DIV == 1 + /* Do nothing since FCK bits should be 0. */ +#elif BSP_CFG_FCK_DIV == 2 + tmp_clock |= 0x10000000; +#elif BSP_CFG_FCK_DIV == 4 + tmp_clock |= 0x20000000; +#elif BSP_CFG_FCK_DIV == 8 + tmp_clock |= 0x30000000; +#elif BSP_CFG_FCK_DIV == 16 + tmp_clock |= 0x40000000; +#elif BSP_CFG_FCK_DIV == 32 + tmp_clock |= 0x50000000; +#elif BSP_CFG_FCK_DIV == 64 + tmp_clock |= 0x60000000; +#else + #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for ICK bits. */ +#if BSP_CFG_ICK_DIV == 1 + /* Do nothing since ICK bits should be 0. */ +#elif BSP_CFG_ICK_DIV == 2 + tmp_clock |= 0x01000000; +#elif BSP_CFG_ICK_DIV == 4 + tmp_clock |= 0x02000000; +#elif BSP_CFG_ICK_DIV == 8 + tmp_clock |= 0x03000000; +#elif BSP_CFG_ICK_DIV == 16 + tmp_clock |= 0x04000000; +#elif BSP_CFG_ICK_DIV == 32 + tmp_clock |= 0x05000000; +#elif BSP_CFG_ICK_DIV == 64 + tmp_clock |= 0x06000000; +#else + #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for BCK bits. */ +#if BSP_CFG_BCK_DIV == 1 + /* Do nothing since BCK bits should be 0. */ +#elif BSP_CFG_BCK_DIV == 2 + tmp_clock |= 0x00010000; +#elif BSP_CFG_BCK_DIV == 3 + tmp_clock |= 0x00090000; +#elif BSP_CFG_BCK_DIV == 4 + tmp_clock |= 0x00020000; +#elif BSP_CFG_BCK_DIV == 8 + tmp_clock |= 0x00030000; +#elif BSP_CFG_BCK_DIV == 16 + tmp_clock |= 0x00040000; +#elif BSP_CFG_BCK_DIV == 32 + tmp_clock |= 0x00050000; +#elif BSP_CFG_BCK_DIV == 64 + tmp_clock |= 0x00060000; +#else + #error "Error! Invalid setting for BSP_CFG_BCK_DIV in r_bsp_config.h" +#endif + + /* Configure PSTOP1 bit for BCLK output. */ +#if BSP_CFG_BCLK_OUTPUT == 0 + /* Set PSTOP1 bit */ + tmp_clock |= 0x00800000; +#elif BSP_CFG_BCLK_OUTPUT == 1 + /* Clear PSTOP1 bit */ + tmp_clock &= ~0x00800000; +#elif BSP_CFG_BCLK_OUTPUT == 2 + /* Clear PSTOP1 bit */ + tmp_clock &= ~0x00800000; + /* Set BCLK divider bit */ + SYSTEM.BCKCR.BIT.BCLKDIV = 1; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(1 == SYSTEM.BCKCR.BIT.BCLKDIV) + { + R_BSP_NOP(); + } +#else + #error "Error! Invalid setting for BSP_CFG_BCLK_OUTPUT in r_bsp_config.h" +#endif + + /* Figure out setting for PCKA bits. */ +#if BSP_CFG_PCKA_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKA_DIV == 2 + tmp_clock |= 0x00001000; +#elif BSP_CFG_PCKA_DIV == 4 + tmp_clock |= 0x00002000; +#elif BSP_CFG_PCKA_DIV == 8 + tmp_clock |= 0x00003000; +#elif BSP_CFG_PCKA_DIV == 16 + tmp_clock |= 0x00004000; +#elif BSP_CFG_PCKA_DIV == 32 + tmp_clock |= 0x00005000; +#elif BSP_CFG_PCKA_DIV == 64 + tmp_clock |= 0x00006000; +#else + #error "Error! Invalid setting for BSP_CFG_PCKA_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKB bits. */ +#if BSP_CFG_PCKB_DIV == 1 + /* Do nothing since PCKB bits should be 0. */ +#elif BSP_CFG_PCKB_DIV == 2 + tmp_clock |= 0x00000100; +#elif BSP_CFG_PCKB_DIV == 4 + tmp_clock |= 0x00000200; +#elif BSP_CFG_PCKB_DIV == 8 + tmp_clock |= 0x00000300; +#elif BSP_CFG_PCKB_DIV == 16 + tmp_clock |= 0x00000400; +#elif BSP_CFG_PCKB_DIV == 32 + tmp_clock |= 0x00000500; +#elif BSP_CFG_PCKB_DIV == 64 + tmp_clock |= 0x00000600; +#else + #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKC bits. */ +#if BSP_CFG_PCKC_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKC_DIV == 2 + tmp_clock |= 0x00000010; +#elif BSP_CFG_PCKC_DIV == 4 + tmp_clock |= 0x00000020; +#elif BSP_CFG_PCKC_DIV == 8 + tmp_clock |= 0x00000030; +#elif BSP_CFG_PCKC_DIV == 16 + tmp_clock |= 0x00000040; +#elif BSP_CFG_PCKC_DIV == 32 + tmp_clock |= 0x00000050; +#elif BSP_CFG_PCKC_DIV == 64 + tmp_clock |= 0x00000060; +#else + #error "Error! Invalid setting for BSP_CFG_PCKC_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKD bits. */ +#if BSP_CFG_PCKD_DIV == 1 + /* Do nothing since PCKD bits should be 0. */ +#elif BSP_CFG_PCKD_DIV == 2 + tmp_clock |= 0x00000001; +#elif BSP_CFG_PCKD_DIV == 4 + tmp_clock |= 0x00000002; +#elif BSP_CFG_PCKD_DIV == 8 + tmp_clock |= 0x00000003; +#elif BSP_CFG_PCKD_DIV == 16 + tmp_clock |= 0x00000004; +#elif BSP_CFG_PCKD_DIV == 32 + tmp_clock |= 0x00000005; +#elif BSP_CFG_PCKD_DIV == 64 + tmp_clock |= 0x00000006; +#else + #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h" +#endif + + /* To change the ICLK frequency from less than 70 MHz to 70 MHz or higher such that the ratio of the frequency + after the change to that before the change is greater than four, start by setting the frequency to one quarter + of the intended frequency, wait for 3 us, and then change it to the intended frequency. + (Refer User's Manual: 9.10.7 Notes on Changing the ICLK Frequency.) */ + /* Confirm whether to change ICLK frequency from less than 70 MHz to 70 MHz or higher. */ + if(BSP_ICLK_HZ >= BSP_MCU_ICLK_FREQ_THRESHOLD) + { + /* The clock source after reset is LOCO. The frequency of LOCO is 240 kHz. + When the target clock frequency is 70 MHz or higher, it always exceeds 4 times the current clock frequency. + Therefore, this process does not check whether the target clock frequency exceeds 4 times the current + clock frequency. */ + + /* Backup of tmp_clock */ + tmp_restore_clock = tmp_clock; + + /* Clear the setting for ICK and BCK bits. */ + tmp_clock &= 0xF0F0FFFF; +#if BSP_CFG_ICK_DIV == 1 + /* Set ICK and BCK bits to divide by 4. */ + tmp_clock |= 0x02020000; +#elif BSP_CFG_ICK_DIV == 2 + /* Set ICK and BCK bits to divide by 8. */ + tmp_clock |= 0x03030000; +#endif + } + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + + /* Re-init tmp_clock to use to set SCKCR2. */ + tmp_clock = 0; + + /* Figure out setting for UCK bits. */ +#if BSP_CFG_UCK_DIV == 2 + tmp_clock |= 0x00000011; +#elif BSP_CFG_UCK_DIV == 3 + tmp_clock |= 0x00000021; +#elif BSP_CFG_UCK_DIV == 4 + tmp_clock |= 0x00000031; +#elif BSP_CFG_UCK_DIV == 5 + tmp_clock |= 0x00000041; +#else + #error "Error! Invalid setting for BSP_CFG_UCK_DIV in r_bsp_config.h" +#endif + + /* Set SCKCR2 register. */ + SYSTEM.SCKCR2.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR2.WORD) + { + R_BSP_NOP(); + } + + /* Choose clock source. Default for r_bsp_config.h is PLL. */ + tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8; + + /* Casting is valid because it matches the type to the retern value. */ + SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + + /* Set ICLK frequency to target ICLK. */ + if(BSP_ICLK_HZ >= BSP_MCU_ICLK_FREQ_THRESHOLD) + { + /* Wait for 3 us. */ + R_BSP_SoftwareDelay((uint32_t)3, BSP_DELAY_MICROSECS); + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_restore_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_restore_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + } + +#if BSP_PRV_LOCO_CLK_OPERATING == 0 + /* We can now turn LOCO off since it is not going to be used. */ + SYSTEM.LOCOCR.BYTE = 0x01; + + /* Wait for five the LOCO cycles */ + /* 5 count of LOCO : (1000000/216000)*5 = 23.148148148us + 23 + 2 = 25us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)25, BSP_DELAY_MICROSECS); +#endif + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function operating_frequency_set() */ + +/*********************************************************************************************************************** +* Function name: clock_source_select +* Description : Enables and disables clocks as chosen by the user. This function also implements the delays +* needed for the clocks to stabilize. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void clock_source_select (void) +{ + volatile uint8_t i; + volatile uint8_t dummy; +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + uint8_t tmp; +#endif + volatile uint16_t tmp_packcr; + + /* Main clock will be not oscillate in software standby or deep software standby modes. */ + SYSTEM.MOFCR.BIT.MOFXIN = 0; + + /* Set the oscillation source of the main clock oscillator. */ + SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE; + +#if BSP_PRV_HOCO_CLK_OPERATING == 1 + /* HOCO is chosen. Start it operating if it is not already operating. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn on power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x00; + + /* Stop HOCO. */ + SYSTEM.HOCOCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stopped. */ + R_BSP_NOP(); + } + + /* Set HOCO frequency. */ + #if (BSP_CFG_HOCO_FREQUENCY == 0) + SYSTEM.HOCOCR2.BYTE = 0x00; //16MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 1) + SYSTEM.HOCOCR2.BYTE = 0x01; //18MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 2) + SYSTEM.HOCOCR2.BYTE = 0x02; //20MHz + #else + #error "Error! Invalid setting for BSP_CFG_HOCO_FREQUENCY in r_bsp_config.h" + #endif + + /* HOCO is chosen. Start it operating. */ + SYSTEM.HOCOCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.HOCOCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. */ + R_BSP_NOP(); + } +#else /* (BSP_PRV_HOCO_CLK_OPERATING == 0) */ + /* If HOCO is already operating, it doesn't stop. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn off power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x01; + } + else + { + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. */ + R_BSP_NOP(); + } + } +#endif /* BSP_PRV_HOCO_CLK_OPERATING == 1 */ + +#if BSP_PRV_MAIN_CLK_OPERATING == 1 + /* Main clock oscillator is chosen. Start it operating. */ + + /* If the main oscillator is >10MHz then the main clock oscillator forced oscillation control register (MOFCR) must + be changed. */ + if (BSP_CFG_XTAL_HZ > 20000000) + { + /* 20 - 24MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 0; + } + else if (BSP_CFG_XTAL_HZ > 16000000) + { + /* 16 - 20MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 1; + } + else if (BSP_CFG_XTAL_HZ > 8000000) + { + /* 8 - 16MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 2; + } + else + { + /* 8MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 3; + } + + /* Set the oscillation stabilization wait time of the main clock oscillator. */ +#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */ + SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME; +#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */ + SYSTEM.MOSCWTCR.BYTE = 0x00; +#else + #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h" +#endif + + /* Set the main clock to operating. */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. */ + R_BSP_NOP(); + } +#else /* (BSP_PRV_MAIN_CLK_OPERATING == 0) */ + /* Main clock is stopped after reset. */ +#endif /* BSP_PRV_MAIN_CLK_OPERATING == 1 */ + + /* Sub-clock setting. */ + + /* Cold start setting */ + if (0 == SYSTEM.RSTSR1.BIT.CWSF) + { + /* Stop the sub-clock oscillator */ + /* RCR4 - RTC Control Register 4 + b7:b1 Reserved - The write value should be 0. + b0 RCKSEL - Count Source Select - Sub-clock oscillator is selected. */ + RTC.RCR4.BIT.RCKSEL = 0; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR4.BYTE; + } + + /* Confirm that the written */ + if (0 != RTC.RCR4.BIT.RCKSEL) + { + R_BSP_NOP(); + } + + /* RCR3 - RTC Control Register 3 + b7:b4 Reserved - The write value should be 0. + b3:b1 RTCDV - Sub-clock oscillator Drive Ability Control. + b0 RTCEN - Sub-clock oscillator is stopped. */ + RTC.RCR3.BIT.RTCEN = 0; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BYTE; + } + + /* Confirm that the written */ + if (0 != RTC.RCR3.BIT.RTCEN) + { + R_BSP_NOP(); + } + + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stopped. */ + R_BSP_NOP(); + } + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Set the drive capacity of the sub-clock oscillator */ + #if (BSP_CFG_SOSC_DRV_CAP == 0) /* Standard CL */ + tmp = 0x06; + #elif (BSP_CFG_SOSC_DRV_CAP == 1) /* Low CL */ + tmp = 0x01; + #else + #error "Error! Invalid setting for BSP_CFG_SOSC_DRV_CAP in r_bsp_config.h" + #endif + + /* Set the Sub-Clock Oscillator Drive Capacity Control. */ + RTC.RCR3.BIT.RTCDV = tmp; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BYTE; + } + + /* Confirm that the written */ + if (tmp != RTC.RCR3.BIT.RTCDV) + { + R_BSP_NOP(); + } + + /* Set wait time until the sub-clock oscillator stabilizes */ + /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register + b7:b5 Reserved - The write value should be 0. + b4:b0 SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */ + SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME; + + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x00 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stabilized. */ + R_BSP_NOP(); + } +#endif /* (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) */ + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */ + SYSTEM.SOSCWTCR.BYTE = 0x00; + + /* ---- Operate the sub-clock oscillator ---- */ + RTC.RCR3.BIT.RTCEN = 1; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BIT.RTCEN; + } + + /* Confirm that the written value can be read correctly. */ + if (1 != RTC.RCR3.BIT.RTCEN) + { + R_BSP_NOP(); + } +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for six the sub-clock cycles */ + /* 6 count of sub-clock : (1000000/32768)*6=183.10546875us + In the case of LOCO frequency is 264kHz : 183.10546875/(1000000/264000)=48.33984375cycle + (48.33984375+2)*(1000000/240000)=209.7493489583333us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)210, BSP_DELAY_MICROSECS); +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) && (BSP_CFG_RTC_ENABLE == 0) + /* Stop prescaler and counter */ + /* RCR2 - RTC Control Register 2 + b7 CNTMD - Count Mode Select - The calendar count mode. + b6 HR24 - Hours Mode - The RTC operates in 24-hour mode. + b5 AADJP - Automatic Adjustment Period Select - The RADJ.ADJ[5:0] setting value is adjusted from + the count value of the prescaler every 10 seconds. + b4 AADJE - Automatic Adjustment Enable - Automatic adjustment is enabled. + b3 RTCOE - RTCOUT Output Enable - RTCOUT output enabled. + b2 ADJ30 - 30-Second Adjustment - 30-second adjustment is executed. + b1 RESET - RTC Software Reset - The prescaler and the target registers for RTC software reset are initialized. + b0 START - start - Prescaler is stopped. */ + RTC.RCR2.BYTE &= 0x7E; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.START) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* RTC Software Reset */ + RTC.RCR2.BIT.RESET = 1; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.RESET) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* An alarm interrupt request is disabled */ + /* RCR1 - RTC Control Register 1 + b7:b4 PES - Periodic Interrupt Select - These bits specify the period for the periodic interrupt. + b3 RTCOS - RTCOUT Output Select - RTCOUT outputs 1 Hz. + b2 PIE - Periodic Interrupt Enable - A periodic interrupt request is disabled. + b1 CIE - Carry Interrupt Enable - A carry interrupt request is disabled. + b0 AIE - Alarm Interrupt Enable - An alarm interrupt request is disabled. */ + RTC.RCR1.BYTE &= 0xF8; + + /* Wait for one the sub-clock cycles */ + /* 1 count of sub-clock : (1000000/32768)=30.517578125us + In the case of LOCO frequency is 264kHz : 30.517578125/(1000000/264000)=8.056640625cycle + (8.056640625+2)*(1000000/240000)=41.902669270833us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)42, BSP_DELAY_MICROSECS); + + /* Confirm that the written value can be read correctly. */ + if (0x00 != (RTC.RCR1.BYTE & 0x07)) + { + R_BSP_NOP(); + } +#endif /* (BSP_PRV_SUB_CLK_OPERATING == 1) && (BSP_CFG_RTC_ENABLE == 0) */ + } + /* Warm start setting */ + else + { +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || ((BSP_PRV_SUB_CLK_OPERATING == 0) && (BSP_CFG_RTC_ENABLE == 0)) + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* Confirm that the Sub clock stopped. */ + R_BSP_NOP(); + } +#endif + +#if BSP_PRV_SUB_CLK_OPERATING == 1 + /* Set wait time until the sub-clock oscillator stabilizes */ + /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register + b7:b5 Reserved - The write value should be 0. + b4:b0 SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */ + SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME; + + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x00 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stabilized. */ + R_BSP_NOP(); + } +#endif + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */ + SYSTEM.SOSCWTCR.BYTE = 0x00; +#endif + } + +#if (BSP_CFG_PHY_CLOCK_SOURCE == 1) || (BSP_CFG_USB_CLOCK_SOURCE == 3) + /* initialize */ + tmp_packcr = SYSTEM.PACKCR.WORD; + +#if BSP_CFG_PHY_CLOCK_SOURCE == 1 + /* Set value of OUTCKSEL bit. */ + tmp_packcr |= 0x0010; +#endif + +#if BSP_CFG_USB_CLOCK_SOURCE == 3 + /* Set value of UPLLSEL bit. */ + tmp_packcr |= 0x1000; +#endif + + /* Set value to PACLCR register. */ + SYSTEM.PACKCR.WORD = tmp_packcr; +#endif + +#if (BSP_PRV_PLL_CLK_OPERATING == 1) || (BSP_PRV_PPLL_CLK_OPERATING == 1) + /* Set PLL clock source. */ + #if BSP_CFG_PLL_SRC == 0 + /* Clear PLL clock source if PLL clock source is Main clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 0; + #else + /* Set PLL clock source if PLL clock source is HOCO clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 1; + #endif +#endif + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + + /* Set PLL Input Divisor. */ + SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV - 1; + + /* Set PLL Multiplier. */ + SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0)) - 1; + + /* Set the PLL to operating. */ + SYSTEM.PLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. */ + R_BSP_NOP(); + } +#else + /* PLL is stopped after reset. */ +#endif + +#if BSP_PRV_PPLL_CLK_OPERATING == 1 + /* Set PPLL Input Divisor. */ + SYSTEM.PPLLCR.BIT.PPLIDIV = BSP_CFG_PPLL_DIV - 1; + + /* Set PPLL Multiplier. */ + SYSTEM.PPLLCR.BIT.PPLSTC = ((uint8_t)((float)BSP_CFG_PPLL_MUL * 2.0)) - 1; + + /* Set the PPLL to operating. */ + SYSTEM.PPLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PPLOVF) + { + /* The delay period needed is to make sure that the PPLL has stabilized. */ + R_BSP_NOP(); + } + + /* Set PPLCK Input Divisor. */ + SYSTEM.PPLLCR3.BIT.PPLCK = BSP_CFG_PPLCK_DIV - 1; +#endif + + /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn + it off until another clock has been enabled and is ready to use. */ +#if BSP_PRV_LOCO_CLK_OPERATING == 1 + /* LOCO is chosen. This is the default out of reset. */ +#else + /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */ +#endif + + /* RX72N has a MEMWAIT register which controls the cycle waiting for access to code flash memory. + It is set as zero coming out of reset. We only want to set this if we are > 120 MHz. + */ + if (BSP_ICLK_HZ > BSP_MCU_MEMWAIT_FREQ_THRESHOLD) + { + /* Set MEMWAIT */ + SYSTEM.MEMWAIT.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x01 == SYSTEM.MEMWAIT.BYTE) + { + R_BSP_NOP(); + } + } +} /* End of function clock_source_select() */ + +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/*********************************************************************************************************************** +* Function name: bsp_clkout_initial_configure +* Description : Configures the CLKOUT initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_clkout_initial_configure(void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Set the CLKOUT Output Divisor Select. */ + SYSTEM.CKOCR.BIT.CKODIV = BSP_CFG_CLKOUT_DIV; + + /* Set the CLKOUT Output Source Select. */ + SYSTEM.CKOCR.BIT.CKOSEL = BSP_CFG_CLKOUT_SOURCE; +#if BSP_CFG_CLKOUT_OUTPUT == 1 + + /* Set the CLKOUT Output Stop Control. */ + SYSTEM.CKOCR.BIT.CKOSTP = 0; +#elif BSP_CFG_CLKOUT_OUTPUT == 0 + /* do nothing */ +#else + #error "Error! Invalid setting for BSP_CFG_CLKOUT_OUTPUT in r_bsp_config.h" +#endif + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_clkout_initial_configure() */ +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h new file mode 100644 index 000000000..61c2ab378 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.h +* Description : Contains clock specific routines. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_CLOCKS_H +#define MCU_CLOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void); +void mcu_clock_setup(void); + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h new file mode 100644 index 000000000..075b2d313 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h @@ -0,0 +1,269 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_info.h +* Device(s) : RX72N +* Description : Information about the MCU. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INFO +#define MCU_INFO + +/* MCU CPU Version */ +#define BSP_MCU_CPU_VERSION (3) + +/* CPU cycles. Known number of RXv3 CPU cycles required to execute the delay_wait() loop */ +#define CPU_CYCLES_PER_LOOP (3) + +/* MCU Series. */ +#if BSP_CFG_MCU_PART_SERIES == 0x0 + #define BSP_MCU_SERIES_RX700 (1) +#else + #error "ERROR - BSP_CFG_MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h" +#endif + +/* This macro means that this MCU is part of the RX72x collection of MCUs (i.e. RX72N). */ +#define BSP_MCU_RX72_ALL (1) + +/* MCU Group name. */ +#if BSP_CFG_MCU_PART_GROUP == 0x0 + #define BSP_MCU_RX72N (1) +#else + #error "ERROR - BSP_CFG_MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h" +#endif + +/* Package. */ +#if BSP_CFG_MCU_PART_PACKAGE == 0x0 + #define BSP_PACKAGE_LFQFP176 (1) + #define BSP_PACKAGE_PINS (176) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x1 + #define BSP_PACKAGE_LFBGA176 (1) + #define BSP_PACKAGE_PINS (176) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x2 + #define BSP_PACKAGE_LFBGA224 (1) + #define BSP_PACKAGE_PINS (224) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x3 + #define BSP_PACKAGE_LFQFP144 (1) + #define BSP_PACKAGE_PINS (144) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x4 + #define BSP_PACKAGE_TFLGA145 (1) + #define BSP_PACKAGE_PINS (145) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x5 + #define BSP_PACKAGE_LFQFP100 (1) + #define BSP_PACKAGE_PINS (100) +#else + #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h" +#endif + +/* Memory size of your MCU. */ +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xD + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (1048576) + #define BSP_DATA_FLASH_SIZE_BYTES (32768) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x17 + #define BSP_ROM_SIZE_BYTES (4194304) + #define BSP_RAM_SIZE_BYTES (1048576) + #define BSP_DATA_FLASH_SIZE_BYTES (32768) +#else + #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h" +#endif + +/* These macros define clock speeds for fixed speed clocks. */ +#define BSP_LOCO_HZ (240000) +#define BSP_SUB_CLOCK_HZ (32768) + +/* Define frequency of HOCO. */ +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "ERROR - Invalid HOCO frequency chosen in r_bsp_config.h! Set valid value for BSP_CFG_HOCO_FREQUENCY." +#endif + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#if BSP_CFG_CLOCK_SOURCE == 0 + #define BSP_SELECTED_CLOCK_HZ (BSP_LOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 1 + #define BSP_SELECTED_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 2 + #define BSP_SELECTED_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 3 + #define BSP_SELECTED_CLOCK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 4 + #if BSP_CFG_PLL_SRC == 0 + #define BSP_SELECTED_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #elif BSP_CFG_PLL_SRC == 1 + #define BSP_SELECTED_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." + #endif +#else + #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h" +#endif + +/* Define frequency of PPLL clock. */ +#if BSP_CFG_PLL_SRC == 0 + #define BSP_PPLL_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PPLL_DIV) * BSP_CFG_PPLL_MUL) +#elif BSP_CFG_PLL_SRC == 1 + #define BSP_PPLL_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PPLL_DIV) * BSP_CFG_PPLL_MUL) +#else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." +#endif + +/* Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#if (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_4TH_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) + #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY" +#endif +#if (5 <= BSP_CFG_EBMAPCR_1ST_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_5TH_PRIORITY) + #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY" +#endif + +/* System clock speed in Hz. */ +#define BSP_ICLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) +/* Peripheral Module Clock A speed in Hz. Used for ETHERC and EDMAC. */ +#define BSP_PCLKA_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKA_DIV) +/* Peripheral Module Clock B speed in Hz. */ +#define BSP_PCLKB_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) +/* Peripheral Module Clock C speed in Hz. */ +#define BSP_PCLKC_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKC_DIV) +/* Peripheral Module Clock D speed in Hz. */ +#define BSP_PCLKD_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) +/* External bus clock speed in Hz. */ +#define BSP_BCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_BCK_DIV) +/* FlashIF clock speed in Hz. */ +#define BSP_FCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) +/* USB clock speed in Hz. */ +#if BSP_CFG_USB_CLOCK_SOURCE == 2 + #define BSP_UCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_UCK_DIV) +#elif BSP_CFG_USB_CLOCK_SOURCE == 3 + #define BSP_UCLK_HZ (BSP_PPLL_CLOCK_HZ / BSP_CFG_PPLCK_DIV) +#else + #error "ERROR - BSP_CFG_USB_CLOCK_SOURCE - Unknown usb clock source chosen in r_bsp_config.h" +#endif + +/* CLKOUT25M clock speed in Hz. */ +#if BSP_CFG_PHY_CLOCK_SOURCE == 0 + #define BSP_CLKOUT25M_HZ (BSP_SELECTED_CLOCK_HZ/8) +#elif BSP_CFG_PHY_CLOCK_SOURCE == 1 + #define BSP_CLKOUT25M_HZ (BSP_PPLL_CLOCK_HZ / 8) +#elif BSP_CFG_PHY_CLOCK_SOURCE == 2 + /* Ethernet-PHY not use */ +#else + #error "ERROR - BSP_CFG_PHY_CLOCK_SOURCE - Unknown Ethernet-PHY clock source chosen in r_bsp_config.h" +#endif + +/* Null argument definitions. */ +#define FIT_NO_FUNC ((void (*)(void *))0x10000000) /* Reserved space on RX */ +#define FIT_NO_PTR ((void *)0x10000000) /* Reserved space on RX */ + +/* Mininum and maximum IPL levels available for this MCU. */ +#define BSP_MCU_IPL_MAX (0xF) +#define BSP_MCU_IPL_MIN (0) + +/* Frequency threshold of memory wait cycle setting. */ +#define BSP_MCU_MEMWAIT_FREQ_THRESHOLD (120000000) /* ICLK > 120MHz requires MEMWAIT register update */ + +/* Frequency threshold of iclk. */ +#define BSP_MCU_ICLK_FREQ_THRESHOLD (70000000) + +/* MCU functions */ +#define BSP_MCU_REGISTER_WRITE_PROTECTION +#define BSP_MCU_RCPC_PRC0 +#define BSP_MCU_RCPC_PRC1 +#define BSP_MCU_RCPC_PRC3 +#define BSP_MCU_FLOATING_POINT +#define BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#define BSP_MCU_EXCEPTION_TABLE +#define BSP_MCU_GROUP_INTERRUPT +#define BSP_MCU_GROUP_INTERRUPT_IE0 +#define BSP_MCU_GROUP_INTERRUPT_BE0 +#define BSP_MCU_GROUP_INTERRUPT_BL0 +#define BSP_MCU_GROUP_INTERRUPT_BL1 +#define BSP_MCU_GROUP_INTERRUPT_BL2 +#define BSP_MCU_GROUP_INTERRUPT_AL0 +#define BSP_MCU_GROUP_INTERRUPT_AL1 +#define BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT +#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +#define BSP_MCU_EXCEP_ACCESS_ISR +#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR +#define BSP_MCU_EXCEP_FLOATING_POINT_ISR +#define BSP_MCU_NON_MASKABLE_ISR +#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +#define BSP_MCU_BUS_ERROR_ISR +#define BSP_MCU_TRIGONOMETRIC + +#define BSP_MCU_NMI_EXC_NMI_PIN +#define BSP_MCU_NMI_OSC_STOP_DETECT +#define BSP_MCU_NMI_WDT_ERROR +#define BSP_MCU_NMI_IWDT_ERROR +#define BSP_MCU_NMI_LVD1 +#define BSP_MCU_NMI_LVD2 +#define BSP_MCU_NMI_EXNMI +#define BSP_MCU_NMI_EXNMI_RAM +#define BSP_MCU_NMI_EXNMI_RAM_EXRAM +#define BSP_MCU_NMI_EXNMI_RAM_ECCRAM +#define BSP_MCU_NMI_EXNMI_DPFPUEX + +#endif /* MCU_INFO */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c new file mode 100644 index 000000000..d9b0c1025 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.c +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get specifics on this MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* RX MCUs come in different packages and different pin counts. + Each bit of PORTm.PDR corresponds to each pin of port m; I/O direction can be specified in 1-bit units. + Each bit of PDR corresponding to port m that does not exist is reserved. + Also, each bit of PDR corresponding to P35 pins is reserved, because such pins are input only. + Make settings of the reserved bit according to the description in section 22.4, Initialization of the Port Direction + Register (PDR). These values are then ORed into the direction registers to set non-existent pins as outputs or + inputs, which can help save power. + */ +#if BSP_PACKAGE_PINS == 224 + /* Refer User's Manual: Hardware Table 22.4. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTH_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD0) + #define BSP_PRV_PORTK_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTL_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTM_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0x00) +#elif BSP_PACKAGE_PINS == 176 + /* Refer User's Manual: Hardware Table 22.5. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD0) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#elif (BSP_PACKAGE_PINS == 145) || (BSP_PACKAGE_PINS == 144) + /* Refer User's Manual: Hardware Table 22.6. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x80) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x30) + #define BSP_PRV_PORT9_NE_PIN_MASK (0xF0) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xDF) + #define BSP_PRV_PORTG_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD7) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#elif BSP_PACKAGE_PINS == 100 + /* Refer User's Manual: Hardware Table 22.7. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x5F) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORT6_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT7_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT8_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT9_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTG_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xF7) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#else + #error "ERROR - This package is not defined in mcu_init.c" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_non_existent_port_init +* Description : For MCUs that do not have the maximum number of pins for their group (e.g. MCU with 176 pins when +* maximum is 224 pins) these 'non-existent' pins that are not bonded out need to be initialized to save +* power. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_non_existent_port_init (void) +{ + /* OR in missing pin masks from above. */ + + /* Set PORT0.PDR */ + PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK; + + /* Set PORT1.PDR */ + PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK; + + /* Set PORT2.PDR */ + PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK; + + /* Set PORT3.PDR */ + PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK; + + /* Set PORT4.PDR */ + PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK; + + /* Set PORT5.PDR */ + PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK; + + /* Set PORT6.PDR */ + PORT6.PDR.BYTE |= BSP_PRV_PORT6_NE_PIN_MASK; + + /* Set PORT7.PDR */ + PORT7.PDR.BYTE |= BSP_PRV_PORT7_NE_PIN_MASK; + + /* Set PORT8.PDR */ + PORT8.PDR.BYTE |= BSP_PRV_PORT8_NE_PIN_MASK; + + /* Set PORT9.PDR */ + PORT9.PDR.BYTE |= BSP_PRV_PORT9_NE_PIN_MASK; + + /* Set PORTA.PDR */ + PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK; + + /* Set PORTB.PDR */ + PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK; + + /* Set PORTC.PDR */ + PORTC.PDR.BYTE |= BSP_PRV_PORTC_NE_PIN_MASK; + + /* Set PORTD.PDR */ + PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK; + + /* Set PORTE.PDR */ + PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK; + + /* Set PORTF.PDR */ + PORTF.PDR.BYTE |= BSP_PRV_PORTF_NE_PIN_MASK; + + /* Set PORTG.PDR */ + PORTG.PDR.BYTE |= BSP_PRV_PORTG_NE_PIN_MASK; + + /* Set PORTH.PDR */ + PORTH.PDR.BYTE |= BSP_PRV_PORTH_NE_PIN_MASK; + + /* Set PORTJ.PDR */ + PORTJ.PDR.BYTE |= BSP_PRV_PORTJ_NE_PIN_MASK; + + /* Set PORTK.PDR */ + PORTK.PDR.BYTE |= BSP_PRV_PORTK_NE_PIN_MASK; + + /* Set PORTL.PDR */ + PORTL.PDR.BYTE |= BSP_PRV_PORTL_NE_PIN_MASK; + + /* Set PORTM.PDR */ + PORTM.PDR.BYTE |= BSP_PRV_PORTM_NE_PIN_MASK; + + /* Set PORTN.PDR */ + PORTN.PDR.BYTE |= BSP_PRV_PORTN_NE_PIN_MASK; + + /* Set PORTQ.PDR */ + PORTQ.PDR.BYTE |= BSP_PRV_PORTQ_NE_PIN_MASK; +} /* End of function bsp_non_existent_port_init() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h new file mode 100644 index 000000000..115c6b869 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.h +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INIT_H +#define MCU_INIT_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_non_existent_port_init(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_INIT_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c new file mode 100644 index 000000000..faba267c7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ +#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl2_handler_isr, VECT(ICU,GROUPBL2)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al1_handler_isr, VECT(ICU,GROUPAL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_ie0_handler_isr, VECT(ICU,GROUPIE0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_be0_handler_isr, VECT(ICU,GROUPBE0)) + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ +#ifdef __FPU + uint32_t tmp_fpsw; +#endif + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + +#ifdef __FPU + case (BSP_INT_SRC_EXC_FPU): + + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + if (true == enable) + { + /* Set the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + else + { + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + break; +#endif + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + +/*********************************************************************************************************************** +* Function Name: group_bl0_handler_isr +* Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void) +{ + /* BL0 IS1 */ + if (1 == ICU.GRPBL0.BIT.IS1) + { + /* BSP_INT_SRC_BL0_SCI0_ERI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_ERI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS0 */ + if (1 == ICU.GRPBL0.BIT.IS0) + { + /* BSP_INT_SRC_BL0_SCI0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS3 */ + if (1 == ICU.GRPBL0.BIT.IS3) + { + /* BSP_INT_SRC_BL0_SCI1_ERI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS2 */ + if (1 == ICU.GRPBL0.BIT.IS2) + { + /* BSP_INT_SRC_BL0_SCI1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS5 */ + if (1 == ICU.GRPBL0.BIT.IS5) + { + /* BSP_INT_SRC_BL0_SCI2_ERI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_ERI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS4 */ + if (1 == ICU.GRPBL0.BIT.IS4) + { + /* BSP_INT_SRC_BL0_SCI2_TEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS7 */ + if (1 == ICU.GRPBL0.BIT.IS7) + { + /* BSP_INT_SRC_BL0_SCI3_ERI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_ERI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS6 */ + if (1 == ICU.GRPBL0.BIT.IS6) + { + /* BSP_INT_SRC_BL0_SCI3_TEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_TEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS9 */ + if (1 == ICU.GRPBL0.BIT.IS9) + { + /* BSP_INT_SRC_BL0_SCI4_ERI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_ERI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS8 */ + if (1 == ICU.GRPBL0.BIT.IS8) + { + /* BSP_INT_SRC_BL0_SCI4_TEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_TEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS11 */ + if (1 == ICU.GRPBL0.BIT.IS11) + { + /* BSP_INT_SRC_BL0_SCI5_ERI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS10 */ + if (1 == ICU.GRPBL0.BIT.IS10) + { + /* BSP_INT_SRC_BL0_SCI5_TEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS13 */ + if (1 == ICU.GRPBL0.BIT.IS13) + { + /* BSP_INT_SRC_BL0_SCI6_ERI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS12 */ + if (1 == ICU.GRPBL0.BIT.IS12) + { + /* BSP_INT_SRC_BL0_SCI6_TEI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS17 */ + if (1 == ICU.GRPBL0.BIT.IS17) + { + /* BSP_INT_SRC_BL0_SCI12_ERI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS16 */ + if (1 == ICU.GRPBL0.BIT.IS16) + { + /* BSP_INT_SRC_BL0_SCI12_TEI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS18 */ + if (1 == ICU.GRPBL0.BIT.IS18) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS19 */ + if (1 == ICU.GRPBL0.BIT.IS19) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS20 */ + if (1 == ICU.GRPBL0.BIT.IS20) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS21 */ + if (1 == ICU.GRPBL0.BIT.IS21) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS24 */ + if (1 == ICU.GRPBL0.BIT.IS24) + { + /* BSP_INT_SRC_BL0_QSPI_QSPSSLI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_QSPI_QSPSSLI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS26 */ + if (1 == ICU.GRPBL0.BIT.IS26) + { + /* BSP_INT_SRC_BL0_CAC_FERRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS27 */ + if (1 == ICU.GRPBL0.BIT.IS27) + { + /* BSP_INT_SRC_BL0_CAC_MENDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS28 */ + if (1 == ICU.GRPBL0.BIT.IS28) + { + /* BSP_INT_SRC_BL0_CAC_OVFI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS29 */ + if (1 == ICU.GRPBL0.BIT.IS29) + { + /* BSP_INT_SRC_BL0_DOC_DOPCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS31 */ + if (1 == ICU.GRPBL0.BIT.IS31) + { + /* BSP_INT_SRC_BL0_PDC_PCERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS30 */ + if (1 == ICU.GRPBL0.BIT.IS30) + { + /* BSP_INT_SRC_BL0_PDC_PCFEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCFEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl1_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void) +{ + /* BL1 IS3 */ + if (1 == ICU.GRPBL1.BIT.IS3) + { + /* BSP_INT_SRC_BL1_SDHI_CDETI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CDETI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS4 */ + if (1 == ICU.GRPBL1.BIT.IS4) + { + /* BSP_INT_SRC_BL1_SDHI_CACI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS5 */ + if (1 == ICU.GRPBL1.BIT.IS5) + { + /* BSP_INT_SRC_BL1_SDHI_SDACI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_SDACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS6 */ + if (1 == ICU.GRPBL1.BIT.IS6) + { + /* BSP_INT_SRC_BL1_MMCIF_CDETIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_CDETIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS7 */ + if (1 == ICU.GRPBL1.BIT.IS7) + { + /* BSP_INT_SRC_BL1_MMCIF_ERRIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ERRIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS8 */ + if (1 == ICU.GRPBL1.BIT.IS8) + { + /* BSP_INT_SRC_BL1_MMCIF_ACCIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ACCIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS9 */ + if (1 == ICU.GRPBL1.BIT.IS9) + { + /* BSP_INT_SRC_BL1_POE3_OEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS10 */ + if (1 == ICU.GRPBL1.BIT.IS10) + { + /* BSP_INT_SRC_BL1_POE3_OEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS11 */ + if (1 == ICU.GRPBL1.BIT.IS11) + { + /* BSP_INT_SRC_BL1_POE3_OEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS12 */ + if (1 == ICU.GRPBL1.BIT.IS12) + { + /* BSP_INT_SRC_BL1_POE3_OEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS14 */ + if (1 == ICU.GRPBL1.BIT.IS14) + { + /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS13 */ + if (1 == ICU.GRPBL1.BIT.IS13) + { + /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS16 */ + if (1 == ICU.GRPBL1.BIT.IS16) + { + /* BSP_INT_SRC_BL1_RIIC2_EEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_EEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS15 */ + if (1 == ICU.GRPBL1.BIT.IS15) + { + /* BSP_INT_SRC_BL1_RIIC2_TEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS17 */ + if (1 == ICU.GRPBL1.BIT.IS17) + { + /* BSP_INT_SRC_BL1_SSIE0_SSIF0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SSIE0_SSIF0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS18 */ + if (1 == ICU.GRPBL1.BIT.IS18) + { + /* BSP_INT_SRC_BL1_SSIE1_SSIF1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SSIE1_SSIF1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS20 */ + if (1 == ICU.GRPBL1.BIT.IS20) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS21 */ + if (1 == ICU.GRPBL1.BIT.IS21) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS22 */ + if (1 == ICU.GRPBL1.BIT.IS22) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS23 */ + if (1 == ICU.GRPBL1.BIT.IS23) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS29 */ + if (1 == ICU.GRPBL1.BIT.IS29) + { + /* BSP_INT_SRC_BL1_RIIC1_EEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_EEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS28 */ + if (1 == ICU.GRPBL1.BIT.IS28) + { + /* BSP_INT_SRC_BL1_RIIC1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl2_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl2_handler_isr (void) +{ + /* BL2 IS7 */ + if (1 == ICU.GRPBL2.BIT.IS7) + { + /* BSP_INT_SRC_BL2_POEG_POEGGAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS8 */ + if (1 == ICU.GRPBL2.BIT.IS8) + { + /* BSP_INT_SRC_BL2_POEG_POEGGBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS9 */ + if (1 == ICU.GRPBL2.BIT.IS9) + { + /* BSP_INT_SRC_BL2_POEG_POEGGCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS10 */ + if (1 == ICU.GRPBL2.BIT.IS10) + { + /* BSP_INT_SRC_BL2_POEG_POEGGDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl2_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al0_handler_isr +* Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void) +{ + /* AL0 IS1 */ + if (1 == ICU.GRPAL0.BIT.IS1) + { + /* BSP_INT_SRC_AL0_SCI8_ERI8 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI8_ERI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS0 */ + if (1 == ICU.GRPAL0.BIT.IS0) + { + /* BSP_INT_SRC_AL0_SCI8_TEI8 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI8_TEI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS5 */ + if (1 == ICU.GRPAL0.BIT.IS5) + { + /* BSP_INT_SRC_AL0_SCI9_ERI9 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI9_ERI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS4 */ + if (1 == ICU.GRPAL0.BIT.IS4) + { + /* BSP_INT_SRC_AL0_SCI9_TEI9 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI9_TEI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS9 */ + if (1 == ICU.GRPAL0.BIT.IS9) + { + /* BSP_INT_SRC_AL0_SCI10_ERI10 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_ERI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS8 */ + if (1 == ICU.GRPAL0.BIT.IS8) + { + /* BSP_INT_SRC_AL0_SCI10_TEI10 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_TEI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS13 */ + if (1 == ICU.GRPAL0.BIT.IS13) + { + /* BSP_INT_SRC_AL0_SCI11_ERI11 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_ERI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS12 */ + if (1 == ICU.GRPAL0.BIT.IS12) + { + /* BSP_INT_SRC_AL0_SCI11_TEI11 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_TEI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS17 */ + if (1 == ICU.GRPAL0.BIT.IS17) + { + /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS16 */ + if (1 == ICU.GRPAL0.BIT.IS16) + { + /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS19 */ + if (1 == ICU.GRPAL0.BIT.IS19) + { + /* BSP_INT_SRC_AL0_RSPI1_SPEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS18 */ + if (1 == ICU.GRPAL0.BIT.IS18) + { + /* BSP_INT_SRC_AL0_RSPI1_SPII1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPII1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS21 */ + if (1 == ICU.GRPAL0.BIT.IS21) + { + /* BSP_INT_SRC_AL0_RSPI2_SPEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS20 */ + if (1 == ICU.GRPAL0.BIT.IS20) + { + /* BSP_INT_SRC_AL0_RSPI2_SPII2 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPII2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS23 */ + if (1 == ICU.GRPAL0.BIT.IS23) + { + /* BSP_INT_SRC_AL0_SCI7_ERI7 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI7_ERI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS22 */ + if (1 == ICU.GRPAL0.BIT.IS22) + { + /* BSP_INT_SRC_AL0_SCI7_TEI7 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI7_TEI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al1_handler_isr +* Description : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al1_handler_isr (void) +{ + /* AL1 IS0 */ + if (1 == ICU.GRPAL1.BIT.IS0) + { + /* BSP_INT_SRC_AL1_EPTPC_MINT */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EPTPC_MINT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS1 */ + if (1 == ICU.GRPAL1.BIT.IS1) + { + /* BSP_INT_SRC_AL1_PTPEDMAC_PINT */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_PTPEDMAC_PINT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS4 */ + if (1 == ICU.GRPAL1.BIT.IS4) + { + /* BSP_INT_SRC_AL1_EDMAC0_EINT0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC0_EINT0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS5 */ + if (1 == ICU.GRPAL1.BIT.IS5) + { + /* BSP_INT_SRC_AL1_EDMAC1_EINT1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC1_EINT1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS9 */ + if (1 == ICU.GRPAL1.BIT.IS9) + { + /* BSP_INT_SRC_AL1_GLCDC_GR1UF */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR1UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS10 */ + if (1 == ICU.GRPAL1.BIT.IS10) + { + /* BSP_INT_SRC_AL1_GLCDC_GR2UF */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR2UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS8 */ + if (1 == ICU.GRPAL1.BIT.IS8) + { + /* BSP_INT_SRC_AL1_GLCDC_VPOS */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_VPOS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS11 */ + if (1 == ICU.GRPAL1.BIT.IS11) + { + /* BSP_INT_SRC_AL1_DRW2D_DRW_IRQ */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_ie0_handler_isr +* Description : Interrupt handler for Group IE0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_ie0_handler_isr (void) +{ + /* IE0 IS0 */ + if (1 == ICU.GRPIE0.BIT.IS0) + { + /* Clear the interrupt status flag. */ + ICU.GCRIE0.BIT.CLR0 = 1; + + /* BSP_INT_SRC_IE0_DPFPU_DPFPUEX */ + R_BSP_InterruptControl(BSP_INT_SRC_IE0_DPFPU_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_ie0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_be0_handler_isr +* Description : Interrupt handler for Group BE0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_be0_handler_isr (void) +{ + /* BE0 IS0 */ + if (1 == ICU.GRPBE0.BIT.IS0) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR0 = 1; + + /* BSP_INT_SRC_BE0_CAN0_ERS0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN0_ERS0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BE0 IS1 */ + if (1 == ICU.GRPBE0.BIT.IS1) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR1 = 1; + + /* BSP_INT_SRC_BE0_CAN1_ERS1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN1_ERS1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BE0 IS2 */ + if (1 == ICU.GRPBE0.BIT.IS2) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR2 = 1; + + /* BSP_INT_SRC_BE0_CAN2_ERS2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN2_ERS2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_be0_handler_isr() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h new file mode 100644 index 000000000..14c6960d4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h @@ -0,0 +1,230 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_GROUP_STILL_ENABLED, /* Not all group interrupts were disabled so group interrupt was not + disabled */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_EXC_FPU, /* FPU exception */ + BSP_INT_SRC_EXC_ACCESS, /* Access exception */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_WDT_ERROR, /* WDT underflow/refresh error has occurred */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_RAM, /* RAM error interrupt */ + BSP_INT_SRC_EXRAM, /* EXRAM error interrupt */ + BSP_INT_SRC_ECCRAM_1BIT, /* ECCRAM 1-bit error interrupt */ + BSP_INT_SRC_ECCRAM_2BIT, /* ECCRAM 2-bit error interrupt */ + BSP_INT_SRC_DPFPUEX, /* Double-Precision Floating-Point Exception interrupt */ + + BSP_INT_SRC_GR_INT_TOP, + + /* IE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_IE0_TOP, + BSP_INT_SRC_IE0_DPFPU_DPFPUEX, + + /* BE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_BE0_TOP, + BSP_INT_SRC_BE0_CAN0_ERS0, + BSP_INT_SRC_BE0_CAN1_ERS1, + BSP_INT_SRC_BE0_CAN2_ERS2, + + /* BL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL0_TOP, + BSP_INT_SRC_BL0_SCI0_TEI0, + BSP_INT_SRC_BL0_SCI0_ERI0, + BSP_INT_SRC_BL0_SCI1_TEI1, + BSP_INT_SRC_BL0_SCI1_ERI1, + BSP_INT_SRC_BL0_SCI2_TEI2, + BSP_INT_SRC_BL0_SCI2_ERI2, + BSP_INT_SRC_BL0_SCI3_TEI3, + BSP_INT_SRC_BL0_SCI3_ERI3, + BSP_INT_SRC_BL0_SCI4_TEI4, + BSP_INT_SRC_BL0_SCI4_ERI4, + BSP_INT_SRC_BL0_SCI5_TEI5, + BSP_INT_SRC_BL0_SCI5_ERI5, + BSP_INT_SRC_BL0_SCI6_TEI6, + BSP_INT_SRC_BL0_SCI6_ERI6, + BSP_INT_SRC_BL0_SCI12_TEI12, + BSP_INT_SRC_BL0_SCI12_ERI12, + BSP_INT_SRC_BL0_SCI12_SCIX0, + BSP_INT_SRC_BL0_SCI12_SCIX1, + BSP_INT_SRC_BL0_SCI12_SCIX2, + BSP_INT_SRC_BL0_SCI12_SCIX3, + BSP_INT_SRC_BL0_QSPI_QSPSSLI, + BSP_INT_SRC_BL0_CAC_FERRI, + BSP_INT_SRC_BL0_CAC_MENDI, + BSP_INT_SRC_BL0_CAC_OVFI, + BSP_INT_SRC_BL0_DOC_DOPCI, + BSP_INT_SRC_BL0_PDC_PCFEI, + BSP_INT_SRC_BL0_PDC_PCERI, + + /* BL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL1_TOP, + BSP_INT_SRC_BL1_SDHI_CDETI, + BSP_INT_SRC_BL1_SDHI_CACI, + BSP_INT_SRC_BL1_SDHI_SDACI, + BSP_INT_SRC_BL1_MMCIF_CDETIO, + BSP_INT_SRC_BL1_MMCIF_ERRIO, + BSP_INT_SRC_BL1_MMCIF_ACCIO, + BSP_INT_SRC_BL1_POE3_OEI1, + BSP_INT_SRC_BL1_POE3_OEI2, + BSP_INT_SRC_BL1_POE3_OEI3, + BSP_INT_SRC_BL1_POE3_OEI4, + BSP_INT_SRC_BL1_RIIC0_TEI0, + BSP_INT_SRC_BL1_RIIC0_EEI0, + BSP_INT_SRC_BL1_RIIC2_TEI2, + BSP_INT_SRC_BL1_RIIC2_EEI2, + BSP_INT_SRC_BL1_SSIE0_SSIF0, + BSP_INT_SRC_BL1_SSIE1_SSIF1, + BSP_INT_SRC_BL1_S12AD0_S12CMPAI, + BSP_INT_SRC_BL1_S12AD0_S12CMPBI, + BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, + BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, + BSP_INT_SRC_BL1_RIIC1_TEI1, + BSP_INT_SRC_BL1_RIIC1_EEI1, + + /* BL2 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL2_TOP, + BSP_INT_SRC_BL2_POEG_POEGGAI, + BSP_INT_SRC_BL2_POEG_POEGGBI, + BSP_INT_SRC_BL2_POEG_POEGGCI, + BSP_INT_SRC_BL2_POEG_POEGGDI, + + /* AL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL0_TOP, + BSP_INT_SRC_AL0_SCI8_TEI8, + BSP_INT_SRC_AL0_SCI8_ERI8, + BSP_INT_SRC_AL0_SCI9_TEI9, + BSP_INT_SRC_AL0_SCI9_ERI9, + BSP_INT_SRC_AL0_SCI10_TEI10, + BSP_INT_SRC_AL0_SCI10_ERI10, + BSP_INT_SRC_AL0_SCI11_TEI11, + BSP_INT_SRC_AL0_SCI11_ERI11, + BSP_INT_SRC_AL0_RSPI0_SPII0, + BSP_INT_SRC_AL0_RSPI0_SPEI0, + BSP_INT_SRC_AL0_RSPI1_SPII1, + BSP_INT_SRC_AL0_RSPI1_SPEI1, + BSP_INT_SRC_AL0_RSPI2_SPII2, + BSP_INT_SRC_AL0_RSPI2_SPEI2, + BSP_INT_SRC_AL0_SCI7_TEI7, + BSP_INT_SRC_AL0_SCI7_ERI7, + + /* AL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL1_TOP, + BSP_INT_SRC_AL1_EPTPC_MINT, + BSP_INT_SRC_AL1_PTPEDMAC_PINT, + BSP_INT_SRC_AL1_EDMAC0_EINT0, + BSP_INT_SRC_AL1_EDMAC1_EINT1, + BSP_INT_SRC_AL1_GLCDC_VPOS, + BSP_INT_SRC_AL1_GLCDC_GR1UF, + BSP_INT_SRC_AL1_GLCDC_GR2UF, + BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, + + BSP_INT_SRC_GR_INT_END, + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for FPU, and Bus Error) */ + BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, /* Enables a group interrupt when a group interrupt source is given. The + pdata argument should give the IPL to be used using the bsp_int_ctrl_t + type. If a group interrupt is enabled multiple times with different IPL + levels it will use the highest given IPL. */ + BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, /* Disables a group interrupt when a group interrupt source is given. + This will only disable a group interrupt when all interrupt + sources for that group are already disabled. */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h new file mode 100644 index 000000000..c3fadfc4a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h @@ -0,0 +1,211 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.h +* Device(s) : RX72N +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_LOCKS_H +#define MCU_LOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you + will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not + using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */ +typedef enum +{ + BSP_LOCK_BSC = 0, + BSP_LOCK_CAC, + BSP_LOCK_CAN0, + BSP_LOCK_CAN1, + BSP_LOCK_CAN2, + BSP_LOCK_CMT, + BSP_LOCK_CMT0, + BSP_LOCK_CMT1, + BSP_LOCK_CMT2, + BSP_LOCK_CMT3, + BSP_LOCK_CMTW0, + BSP_LOCK_CMTW1, + BSP_LOCK_CRC, + BSP_LOCK_DA, + BSP_LOCK_DMAC, + BSP_LOCK_DMAC0, + BSP_LOCK_DMAC1, + BSP_LOCK_DMAC2, + BSP_LOCK_DMAC3, + BSP_LOCK_DMAC4, + BSP_LOCK_DMAC5, + BSP_LOCK_DMAC6, + BSP_LOCK_DMAC7, + BSP_LOCK_DOC, + BSP_LOCK_DRW2D, + BSP_LOCK_DTC, + BSP_LOCK_ECCRAM, + BSP_LOCK_EDMAC0, + BSP_LOCK_EDMAC1, + BSP_LOCK_ELC, + BSP_LOCK_EPTPC, + BSP_LOCK_EPTPC0, + BSP_LOCK_EPTPC1, + BSP_LOCK_ETHERC0, + BSP_LOCK_ETHERC1, + BSP_LOCK_EXDMAC, + BSP_LOCK_EXDMAC0, + BSP_LOCK_EXDMAC1, + BSP_LOCK_FLASH, + BSP_LOCK_GLCDC, + BSP_LOCK_GPTW0, + BSP_LOCK_GPTW1, + BSP_LOCK_GPTW2, + BSP_LOCK_GPTW3, + BSP_LOCK_IRQ0, + BSP_LOCK_IRQ1, + BSP_LOCK_IRQ2, + BSP_LOCK_IRQ3, + BSP_LOCK_IRQ4, + BSP_LOCK_IRQ5, + BSP_LOCK_IRQ6, + BSP_LOCK_IRQ7, + BSP_LOCK_IRQ8, + BSP_LOCK_IRQ9, + BSP_LOCK_IRQ10, + BSP_LOCK_IRQ11, + BSP_LOCK_IRQ12, + BSP_LOCK_IRQ13, + BSP_LOCK_IRQ14, + BSP_LOCK_IRQ15, + BSP_LOCK_ICU, + BSP_LOCK_IWDT, + BSP_LOCK_MMC, + BSP_LOCK_MPC, + BSP_LOCK_MPU, + BSP_LOCK_MTU, + BSP_LOCK_MTU0, + BSP_LOCK_MTU1, + BSP_LOCK_MTU2, + BSP_LOCK_MTU3, + BSP_LOCK_MTU4, + BSP_LOCK_MTU5, + BSP_LOCK_MTU6, + BSP_LOCK_MTU7, + BSP_LOCK_MTU8, + BSP_LOCK_PDC, + BSP_LOCK_PMGI0, + BSP_LOCK_PMGI1, + BSP_LOCK_POE, + BSP_LOCK_POEG, + BSP_LOCK_PPG0, + BSP_LOCK_PPG1, + BSP_LOCK_PTPEDMAC, + BSP_LOCK_QSPI, + BSP_LOCK_RAM, + BSP_LOCK_RIIC0, + BSP_LOCK_RIIC1, + BSP_LOCK_RIIC2, + BSP_LOCK_RSPI0, + BSP_LOCK_RSPI1, + BSP_LOCK_RSPI2, + BSP_LOCK_RTC, + BSP_LOCK_S12AD, + BSP_LOCK_S12AD1, + BSP_LOCK_SCI0, + BSP_LOCK_SCI1, + BSP_LOCK_SCI2, + BSP_LOCK_SCI3, + BSP_LOCK_SCI4, + BSP_LOCK_SCI5, + BSP_LOCK_SCI6, + BSP_LOCK_SCI7, + BSP_LOCK_SCI8, + BSP_LOCK_SCI9, + BSP_LOCK_SCI10, + BSP_LOCK_SCI11, + BSP_LOCK_SCI12, + BSP_LOCK_SDHI, + BSP_LOCK_SSIE0, + BSP_LOCK_SSIE1, + BSP_LOCK_SYSTEM, + BSP_LOCK_TEMPS, + BSP_LOCK_TMR0, + BSP_LOCK_TMR1, + BSP_LOCK_TMR2, + BSP_LOCK_TMR3, + BSP_LOCK_TMR01, + BSP_LOCK_TMR23, + BSP_LOCK_TPU0, + BSP_LOCK_TPU1, + BSP_LOCK_TPU2, + BSP_LOCK_TPU3, + BSP_LOCK_TPU4, + BSP_LOCK_TPU5, + BSP_LOCK_TPUA, + BSP_LOCK_USB, + BSP_LOCK_USB0, + BSP_LOCK_WDT, + BSP_LOCK_FLASHCONST, + BSP_LOCK_TEMPSCONST, + BSP_LOCK_SWINT, + BSP_LOCK_SWINT2, + BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch! +} mcu_lock_t; + +typedef struct +{ + /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */ + int32_t lock; + + /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */ +} bsp_lock_t; + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 +#undef BSP_CFG_USER_LOCKING_TYPE +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t +#else + #if !defined(BSP_CFG_USER_LOCKING_TYPE) + #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h." + #endif +#endif + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[]; + +#endif /* MCU_LOCKS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c new file mode 100644 index 000000000..5d26263b2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c @@ -0,0 +1,877 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_mapped_interrupt_open +* Description : Initializes mapped interrupts. This code does the following for each possible mapped interrupt: +* 1) PREPROCCESOR - Test to see if this interrupt is chosen to be used +* 2) PREPROCESSOR - Figure out which interrupt select register needs to be written to +* 3) RUNTIME C - Set the appropriate select register with the number of this mapped interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open (void) +{ +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) = BSP_PRV_INT_B_NUM_CMT2_CMI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) = BSP_PRV_INT_B_NUM_CMT3_CMI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) = BSP_PRV_INT_B_NUM_TMR0_CMIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) = BSP_PRV_INT_B_NUM_TMR0_CMIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) = BSP_PRV_INT_B_NUM_TMR0_OVI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) = BSP_PRV_INT_B_NUM_TMR1_CMIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) = BSP_PRV_INT_B_NUM_TMR1_CMIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) = BSP_PRV_INT_B_NUM_TMR1_OVI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) = BSP_PRV_INT_B_NUM_TMR2_CMIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) = BSP_PRV_INT_B_NUM_TMR2_CMIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) = BSP_PRV_INT_B_NUM_TMR2_OVI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) = BSP_PRV_INT_B_NUM_TMR3_CMIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) = BSP_PRV_INT_B_NUM_TMR3_CMIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) = BSP_PRV_INT_B_NUM_TMR3_OVI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) = BSP_PRV_INT_B_NUM_TPU0_TGI0A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) = BSP_PRV_INT_B_NUM_TPU0_TGI0B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) = BSP_PRV_INT_B_NUM_TPU0_TGI0C; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) = BSP_PRV_INT_B_NUM_TPU0_TGI0D; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) = BSP_PRV_INT_B_NUM_TPU0_TCI0V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) = BSP_PRV_INT_B_NUM_TPU1_TGI1A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) = BSP_PRV_INT_B_NUM_TPU1_TGI1B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) = BSP_PRV_INT_B_NUM_TPU1_TCI1V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) = BSP_PRV_INT_B_NUM_TPU1_TCI1U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) = BSP_PRV_INT_B_NUM_TPU2_TGI2A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) = BSP_PRV_INT_B_NUM_TPU2_TGI2B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) = BSP_PRV_INT_B_NUM_TPU2_TCI2V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) = BSP_PRV_INT_B_NUM_TPU2_TCI2U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) = BSP_PRV_INT_B_NUM_TPU3_TGI3A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) = BSP_PRV_INT_B_NUM_TPU3_TGI3B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) = BSP_PRV_INT_B_NUM_TPU3_TGI3C; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) = BSP_PRV_INT_B_NUM_TPU3_TGI3D; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) = BSP_PRV_INT_B_NUM_TPU3_TCI3V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) = BSP_PRV_INT_B_NUM_TPU4_TGI4A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) = BSP_PRV_INT_B_NUM_TPU4_TGI4B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) = BSP_PRV_INT_B_NUM_TPU4_TCI4V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) = BSP_PRV_INT_B_NUM_TPU4_TCI4U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) = BSP_PRV_INT_B_NUM_TPU5_TGI5A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) = BSP_PRV_INT_B_NUM_TPU5_TGI5B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) = BSP_PRV_INT_B_NUM_TPU5_TCI5V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) = BSP_PRV_INT_B_NUM_TPU5_TCI5U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) = BSP_PRV_INT_B_NUM_CMTW0_IC0I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) = BSP_PRV_INT_B_NUM_CMTW0_IC1I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) = BSP_PRV_INT_B_NUM_CMTW0_OC0I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) = BSP_PRV_INT_B_NUM_CMTW0_OC1I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) = BSP_PRV_INT_B_NUM_CMTW1_IC0I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) = BSP_PRV_INT_B_NUM_CMTW1_IC1I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) = BSP_PRV_INT_B_NUM_CMTW1_OC0I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) = BSP_PRV_INT_B_NUM_CMTW1_OC1I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) = BSP_PRV_INT_B_NUM_RTC_CUP; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) = BSP_PRV_INT_B_NUM_CAN0_RXF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) = BSP_PRV_INT_B_NUM_CAN0_TXF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) = BSP_PRV_INT_B_NUM_CAN0_RXM0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) = BSP_PRV_INT_B_NUM_CAN0_TXM0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) = BSP_PRV_INT_B_NUM_CAN1_RXF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) = BSP_PRV_INT_B_NUM_CAN1_TXF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) = BSP_PRV_INT_B_NUM_CAN1_RXM1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) = BSP_PRV_INT_B_NUM_CAN1_TXM1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) = BSP_PRV_INT_B_NUM_CAN2_RXF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) = BSP_PRV_INT_B_NUM_CAN2_TXF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) = BSP_PRV_INT_B_NUM_CAN2_RXM2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) = BSP_PRV_INT_B_NUM_CAN2_TXM2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) = BSP_PRV_INT_B_NUM_USB0_USBI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) = BSP_PRV_INT_B_NUM_ELC_ELSR18I; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) = BSP_PRV_INT_B_NUM_ELC_ELSR19I; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) = BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) = BSP_PRV_INT_B_NUM_TSIP_ROMOK; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) = BSP_PRV_INT_B_NUM_TSIP_LONG_PLG; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) = BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) = BSP_PRV_INT_B_NUM_TSIP_WRRDY0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) = BSP_PRV_INT_B_NUM_TSIP_WRRDY1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) = BSP_PRV_INT_B_NUM_TSIP_WRRDY4; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) = BSP_PRV_INT_B_NUM_TSIP_RDRDY0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) = BSP_PRV_INT_B_NUM_TSIP_RDRDY1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) = BSP_PRV_INT_A_NUM_MTU0_TGIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) = BSP_PRV_INT_A_NUM_MTU0_TGIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) = BSP_PRV_INT_A_NUM_MTU0_TGIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) = BSP_PRV_INT_A_NUM_MTU0_TGID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) = BSP_PRV_INT_A_NUM_MTU0_TCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) = BSP_PRV_INT_A_NUM_MTU0_TGIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) = BSP_PRV_INT_A_NUM_MTU0_TGIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) = BSP_PRV_INT_A_NUM_MTU1_TGIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) = BSP_PRV_INT_A_NUM_MTU1_TGIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) = BSP_PRV_INT_A_NUM_MTU1_TCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) = BSP_PRV_INT_A_NUM_MTU1_TCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) = BSP_PRV_INT_A_NUM_MTU2_TGIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) = BSP_PRV_INT_A_NUM_MTU2_TGIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) = BSP_PRV_INT_A_NUM_MTU2_TCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) = BSP_PRV_INT_A_NUM_MTU2_TCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) = BSP_PRV_INT_A_NUM_MTU3_TGIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) = BSP_PRV_INT_A_NUM_MTU3_TGIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) = BSP_PRV_INT_A_NUM_MTU3_TGIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) = BSP_PRV_INT_A_NUM_MTU3_TGID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) = BSP_PRV_INT_A_NUM_MTU3_TCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) = BSP_PRV_INT_A_NUM_MTU4_TGIA4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) = BSP_PRV_INT_A_NUM_MTU4_TGIB4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) = BSP_PRV_INT_A_NUM_MTU4_TGIC4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) = BSP_PRV_INT_A_NUM_MTU4_TGID4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) = BSP_PRV_INT_A_NUM_MTU4_TCIV4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) = BSP_PRV_INT_A_NUM_MTU5_TGIU5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) = BSP_PRV_INT_A_NUM_MTU5_TGIV5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) = BSP_PRV_INT_A_NUM_MTU5_TGIW5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) = BSP_PRV_INT_A_NUM_MTU6_TGIA6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) = BSP_PRV_INT_A_NUM_MTU6_TGIB6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) = BSP_PRV_INT_A_NUM_MTU6_TGIC6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) = BSP_PRV_INT_A_NUM_MTU6_TGID6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) = BSP_PRV_INT_A_NUM_MTU6_TCIV6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) = BSP_PRV_INT_A_NUM_MTU7_TGIA7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) = BSP_PRV_INT_A_NUM_MTU7_TGIB7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) = BSP_PRV_INT_A_NUM_MTU7_TGIC7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) = BSP_PRV_INT_A_NUM_MTU7_TGID7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) = BSP_PRV_INT_A_NUM_MTU7_TCIV7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) = BSP_PRV_INT_A_NUM_MTU8_TGIA8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) = BSP_PRV_INT_A_NUM_MTU8_TGIB8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) = BSP_PRV_INT_A_NUM_MTU8_TGIC8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) = BSP_PRV_INT_A_NUM_MTU8_TGID8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) = BSP_PRV_INT_A_NUM_MTU8_TCIV8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) = BSP_PRV_INT_A_NUM_GPTW0_GTCID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) = BSP_PRV_INT_A_NUM_GPTW0_GDTE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIU0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIC1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) = BSP_PRV_INT_A_NUM_GPTW1_GTCID1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) = BSP_PRV_INT_A_NUM_GPTW1_GDTE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIC2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) = BSP_PRV_INT_A_NUM_GPTW2_GTCID2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) = BSP_PRV_INT_A_NUM_GPTW2_GDTE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) = BSP_PRV_INT_A_NUM_GPTW3_GTCID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) = BSP_PRV_INT_A_NUM_GPTW3_GDTE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIF3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIU3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) = BSP_PRV_INT_A_NUM_EPTPC_IPLS; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) = BSP_PRV_INT_A_NUM_PMGI0_PMGI0I; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) = BSP_PRV_INT_A_NUM_PMGI1_PMGI1I; +#endif +} /* End of function bsp_mapped_interrupt_open() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h new file mode 100644 index 000000000..aed97bbcd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h @@ -0,0 +1,1692 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_H +#define MCU_MAPPED_INTERRUPTS_H + +/* The following macros define the number for each interrupt request source as it pertains to being an Interrupt B or + * Interrupt A interrupt. These values are used when setting the interrupt select registers (i.e. SLIBXRn, SLIBrn, and + * SLIARn). + */ +/* Available Interrupt B Sources. */ +#define BSP_PRV_INT_B_NUM_CMT2_CMI2 1 +#define BSP_PRV_INT_B_NUM_CMT3_CMI3 2 +#define BSP_PRV_INT_B_NUM_TMR0_CMIA0 3 +#define BSP_PRV_INT_B_NUM_TMR0_CMIB0 4 +#define BSP_PRV_INT_B_NUM_TMR0_OVI0 5 +#define BSP_PRV_INT_B_NUM_TMR1_CMIA1 6 +#define BSP_PRV_INT_B_NUM_TMR1_CMIB1 7 +#define BSP_PRV_INT_B_NUM_TMR1_OVI1 8 +#define BSP_PRV_INT_B_NUM_TMR2_CMIA2 9 +#define BSP_PRV_INT_B_NUM_TMR2_CMIB2 10 +#define BSP_PRV_INT_B_NUM_TMR2_OVI2 11 +#define BSP_PRV_INT_B_NUM_TMR3_CMIA3 12 +#define BSP_PRV_INT_B_NUM_TMR3_CMIB3 13 +#define BSP_PRV_INT_B_NUM_TMR3_OVI3 14 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0A 15 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0B 16 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0C 17 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0D 18 +#define BSP_PRV_INT_B_NUM_TPU0_TCI0V 19 +#define BSP_PRV_INT_B_NUM_TPU1_TGI1A 20 +#define BSP_PRV_INT_B_NUM_TPU1_TGI1B 21 +#define BSP_PRV_INT_B_NUM_TPU1_TCI1V 22 +#define BSP_PRV_INT_B_NUM_TPU1_TCI1U 23 +#define BSP_PRV_INT_B_NUM_TPU2_TGI2A 24 +#define BSP_PRV_INT_B_NUM_TPU2_TGI2B 25 +#define BSP_PRV_INT_B_NUM_TPU2_TCI2V 26 +#define BSP_PRV_INT_B_NUM_TPU2_TCI2U 27 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3A 28 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3B 29 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3C 30 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3D 31 +#define BSP_PRV_INT_B_NUM_TPU3_TCI3V 32 +#define BSP_PRV_INT_B_NUM_TPU4_TGI4A 33 +#define BSP_PRV_INT_B_NUM_TPU4_TGI4B 34 +#define BSP_PRV_INT_B_NUM_TPU4_TCI4V 35 +#define BSP_PRV_INT_B_NUM_TPU4_TCI4U 36 +#define BSP_PRV_INT_B_NUM_TPU5_TGI5A 37 +#define BSP_PRV_INT_B_NUM_TPU5_TGI5B 38 +#define BSP_PRV_INT_B_NUM_TPU5_TCI5V 39 +#define BSP_PRV_INT_B_NUM_TPU5_TCI5U 40 +#define BSP_PRV_INT_B_NUM_CMTW0_IC0I0 41 +#define BSP_PRV_INT_B_NUM_CMTW0_IC1I0 42 +#define BSP_PRV_INT_B_NUM_CMTW0_OC0I0 43 +#define BSP_PRV_INT_B_NUM_CMTW0_OC1I0 44 +#define BSP_PRV_INT_B_NUM_CMTW1_IC0I1 45 +#define BSP_PRV_INT_B_NUM_CMTW1_IC1I1 46 +#define BSP_PRV_INT_B_NUM_CMTW1_OC0I1 47 +#define BSP_PRV_INT_B_NUM_CMTW1_OC1I1 48 +#define BSP_PRV_INT_B_NUM_RTC_CUP 49 +#define BSP_PRV_INT_B_NUM_CAN0_RXF0 50 +#define BSP_PRV_INT_B_NUM_CAN0_TXF0 51 +#define BSP_PRV_INT_B_NUM_CAN0_RXM0 52 +#define BSP_PRV_INT_B_NUM_CAN0_TXM0 53 +#define BSP_PRV_INT_B_NUM_CAN1_RXF1 54 +#define BSP_PRV_INT_B_NUM_CAN1_TXF1 55 +#define BSP_PRV_INT_B_NUM_CAN1_RXM1 56 +#define BSP_PRV_INT_B_NUM_CAN1_TXM1 57 +#define BSP_PRV_INT_B_NUM_CAN2_RXF2 58 +#define BSP_PRV_INT_B_NUM_CAN2_TXF2 59 +#define BSP_PRV_INT_B_NUM_CAN2_RXM2 60 +#define BSP_PRV_INT_B_NUM_CAN2_TXM2 61 +#define BSP_PRV_INT_B_NUM_USB0_USBI0 62 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0 64 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0 65 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0 66 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1 68 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1 69 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1 70 +#define BSP_PRV_INT_B_NUM_ELC_ELSR18I 79 +#define BSP_PRV_INT_B_NUM_ELC_ELSR19I 80 +#define BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY 85 +#define BSP_PRV_INT_B_NUM_TSIP_ROMOK 86 +#define BSP_PRV_INT_B_NUM_TSIP_LONG_PLG 87 +#define BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY 88 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY0 89 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY1 90 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY4 91 +#define BSP_PRV_INT_B_NUM_TSIP_RDRDY0 92 +#define BSP_PRV_INT_B_NUM_TSIP_RDRDY1 93 +#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY 94 +#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY 95 + +/* Available Interrupt A Sources. */ +#define BSP_PRV_INT_A_NUM_MTU0_TGIA0 1 +#define BSP_PRV_INT_A_NUM_MTU0_TGIB0 2 +#define BSP_PRV_INT_A_NUM_MTU0_TGIC0 3 +#define BSP_PRV_INT_A_NUM_MTU0_TGID0 4 +#define BSP_PRV_INT_A_NUM_MTU0_TCIV0 5 +#define BSP_PRV_INT_A_NUM_MTU0_TGIE0 6 +#define BSP_PRV_INT_A_NUM_MTU0_TGIF0 7 +#define BSP_PRV_INT_A_NUM_MTU1_TGIA1 8 +#define BSP_PRV_INT_A_NUM_MTU1_TGIB1 9 +#define BSP_PRV_INT_A_NUM_MTU1_TCIV1 10 +#define BSP_PRV_INT_A_NUM_MTU1_TCIU1 11 +#define BSP_PRV_INT_A_NUM_MTU2_TGIA2 12 +#define BSP_PRV_INT_A_NUM_MTU2_TGIB2 13 +#define BSP_PRV_INT_A_NUM_MTU2_TCIV2 14 +#define BSP_PRV_INT_A_NUM_MTU2_TCIU2 15 +#define BSP_PRV_INT_A_NUM_MTU3_TGIA3 16 +#define BSP_PRV_INT_A_NUM_MTU3_TGIB3 17 +#define BSP_PRV_INT_A_NUM_MTU3_TGIC3 18 +#define BSP_PRV_INT_A_NUM_MTU3_TGID3 19 +#define BSP_PRV_INT_A_NUM_MTU3_TCIV3 20 +#define BSP_PRV_INT_A_NUM_MTU4_TGIA4 21 +#define BSP_PRV_INT_A_NUM_MTU4_TGIB4 22 +#define BSP_PRV_INT_A_NUM_MTU4_TGIC4 23 +#define BSP_PRV_INT_A_NUM_MTU4_TGID4 24 +#define BSP_PRV_INT_A_NUM_MTU4_TCIV4 25 +#define BSP_PRV_INT_A_NUM_MTU5_TGIU5 27 +#define BSP_PRV_INT_A_NUM_MTU5_TGIV5 28 +#define BSP_PRV_INT_A_NUM_MTU5_TGIW5 29 +#define BSP_PRV_INT_A_NUM_MTU6_TGIA6 30 +#define BSP_PRV_INT_A_NUM_MTU6_TGIB6 31 +#define BSP_PRV_INT_A_NUM_MTU6_TGIC6 32 +#define BSP_PRV_INT_A_NUM_MTU6_TGID6 33 +#define BSP_PRV_INT_A_NUM_MTU6_TCIV6 34 +#define BSP_PRV_INT_A_NUM_MTU7_TGIA7 35 +#define BSP_PRV_INT_A_NUM_MTU7_TGIB7 36 +#define BSP_PRV_INT_A_NUM_MTU7_TGIC7 37 +#define BSP_PRV_INT_A_NUM_MTU7_TGID7 38 +#define BSP_PRV_INT_A_NUM_MTU7_TCIV7 39 +#define BSP_PRV_INT_A_NUM_MTU8_TGIA8 41 +#define BSP_PRV_INT_A_NUM_MTU8_TGIB8 42 +#define BSP_PRV_INT_A_NUM_MTU8_TGIC8 43 +#define BSP_PRV_INT_A_NUM_MTU8_TGID8 44 +#define BSP_PRV_INT_A_NUM_MTU8_TCIV8 45 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIA0 47 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIB0 48 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIC0 49 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCID0 50 +#define BSP_PRV_INT_A_NUM_GPTW0_GDTE0 51 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIE0 52 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIF0 53 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIV0 54 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIU0 55 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIA1 58 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIB1 59 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIC1 60 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCID1 61 +#define BSP_PRV_INT_A_NUM_GPTW1_GDTE1 62 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIE1 63 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIF1 64 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIV1 65 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIU1 66 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIA2 67 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIB2 68 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIC2 69 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCID2 70 +#define BSP_PRV_INT_A_NUM_GPTW2_GDTE2 71 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIE2 72 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIF2 73 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIV2 74 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIU2 75 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIA3 76 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIB3 77 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIC3 78 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCID3 79 +#define BSP_PRV_INT_A_NUM_GPTW3_GDTE3 80 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIE3 81 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIF3 82 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIV3 83 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIU3 84 +#define BSP_PRV_INT_A_NUM_EPTPC_IPLS 86 +#define BSP_PRV_INT_A_NUM_PMGI0_PMGI0I 98 +#define BSP_PRV_INT_A_NUM_PMGI1_PMGI1I 99 + +/* The appropriate macros will now be defined based on the vector selections made by the user. + * These are the same macros that are defined for constant-mapped interrupts (vectors 0-127). This means that the + * code can define, setup, and use mapped interrupts the same as would be done for constant-mapped interrupts. + */ +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IR_CMT2_CMI2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define DTCE_CMT2_CMI2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IER_CMT2_CMI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IPR_CMT2_CMI2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IEN_CMT2_CMI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define VECT_CMT2_CMI2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IR_CMT3_CMI3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define DTCE_CMT3_CMI3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IER_CMT3_CMI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IPR_CMT3_CMI3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IEN_CMT3_CMI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define VECT_CMT3_CMI3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IR_TPU0_TGI0A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define DTCE_TPU0_TGI0A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IER_TPU0_TGI0A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IPR_TPU0_TGI0A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IEN_TPU0_TGI0A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define VECT_TPU0_TGI0A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IR_TPU0_TGI0B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define DTCE_TPU0_TGI0B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IER_TPU0_TGI0B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IPR_TPU0_TGI0B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IEN_TPU0_TGI0B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define VECT_TPU0_TGI0B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IR_TPU0_TGI0C BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define DTCE_TPU0_TGI0C BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IER_TPU0_TGI0C BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IPR_TPU0_TGI0C BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IEN_TPU0_TGI0C BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define VECT_TPU0_TGI0C BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IR_TPU0_TGI0D BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define DTCE_TPU0_TGI0D BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IER_TPU0_TGI0D BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IPR_TPU0_TGI0D BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IEN_TPU0_TGI0D BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define VECT_TPU0_TGI0D BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IR_TPU0_TCI0V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define DTCE_TPU0_TCI0V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IER_TPU0_TCI0V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IPR_TPU0_TCI0V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IEN_TPU0_TCI0V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define VECT_TPU0_TCI0V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IR_TPU1_TGI1B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define DTCE_TPU1_TGI1B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IER_TPU1_TGI1B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IPR_TPU1_TGI1B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IEN_TPU1_TGI1B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define VECT_TPU1_TGI1B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IR_TPU1_TCI1V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define DTCE_TPU1_TCI1V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IER_TPU1_TCI1V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IPR_TPU1_TCI1V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IEN_TPU1_TCI1V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define VECT_TPU1_TCI1V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IR_TPU1_TCI1U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define DTCE_TPU1_TCI1U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IER_TPU1_TCI1U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IPR_TPU1_TCI1U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IEN_TPU1_TCI1U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define VECT_TPU1_TCI1U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IR_TPU2_TGI2A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define DTCE_TPU2_TGI2A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IER_TPU2_TGI2A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IPR_TPU2_TGI2A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IEN_TPU2_TGI2A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define VECT_TPU2_TGI2A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IR_TPU2_TGI2B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define DTCE_TPU2_TGI2B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IER_TPU2_TGI2B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IPR_TPU2_TGI2B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IEN_TPU2_TGI2B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define VECT_TPU2_TGI2B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IR_TPU2_TCI2V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define DTCE_TPU2_TCI2V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IER_TPU2_TCI2V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IPR_TPU2_TCI2V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IEN_TPU2_TCI2V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define VECT_TPU2_TCI2V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IR_TPU2_TCI2U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define DTCE_TPU2_TCI2U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IER_TPU2_TCI2U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IPR_TPU2_TCI2U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IEN_TPU2_TCI2U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define VECT_TPU2_TCI2U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IR_TPU3_TGI3A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define DTCE_TPU3_TGI3A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IER_TPU3_TGI3A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IPR_TPU3_TGI3A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IEN_TPU3_TGI3A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define VECT_TPU3_TGI3A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IR_TPU3_TGI3B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define DTCE_TPU3_TGI3B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IER_TPU3_TGI3B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IPR_TPU3_TGI3B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IEN_TPU3_TGI3B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define VECT_TPU3_TGI3B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IR_TPU1_TGI1A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define DTCE_TPU1_TGI1A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IER_TPU1_TGI1A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IPR_TPU1_TGI1A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IEN_TPU1_TGI1A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define VECT_TPU1_TGI1A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IR_TPU3_TGI3C BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define DTCE_TPU3_TGI3C BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IER_TPU3_TGI3C BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IPR_TPU3_TGI3C BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IEN_TPU3_TGI3C BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define VECT_TPU3_TGI3C BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IR_TMR0_CMIA0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define DTCE_TMR0_CMIA0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IER_TMR0_CMIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IPR_TMR0_CMIA0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IEN_TMR0_CMIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define VECT_TMR0_CMIA0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IR_TMR0_CMIB0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define DTCE_TMR0_CMIB0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IER_TMR0_CMIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IPR_TMR0_CMIB0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IEN_TMR0_CMIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define VECT_TMR0_CMIB0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IR_TMR0_OVI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define DTCE_TMR0_OVI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IER_TMR0_OVI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IPR_TMR0_OVI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IEN_TMR0_OVI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define VECT_TMR0_OVI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IR_TMR1_CMIA1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define DTCE_TMR1_CMIA1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IER_TMR1_CMIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IPR_TMR1_CMIA1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IEN_TMR1_CMIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define VECT_TMR1_CMIA1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IR_TMR1_CMIB1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define DTCE_TMR1_CMIB1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IER_TMR1_CMIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IPR_TMR1_CMIB1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IEN_TMR1_CMIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define VECT_TMR1_CMIB1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IR_TMR1_OVI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define DTCE_TMR1_OVI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IER_TMR1_OVI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IPR_TMR1_OVI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IEN_TMR1_OVI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define VECT_TMR1_OVI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IR_TMR2_CMIA2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define DTCE_TMR2_CMIA2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IER_TMR2_CMIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IPR_TMR2_CMIA2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IEN_TMR2_CMIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define VECT_TMR2_CMIA2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IR_TMR2_CMIB2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define DTCE_TMR2_CMIB2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IER_TMR2_CMIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IPR_TMR2_CMIB2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IEN_TMR2_CMIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define VECT_TMR2_CMIB2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IR_TMR2_OVI2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define DTCE_TMR2_OVI2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IER_TMR2_OVI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IPR_TMR2_OVI2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IEN_TMR2_OVI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define VECT_TMR2_OVI2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IR_TMR3_CMIA3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define DTCE_TMR3_CMIA3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IER_TMR3_CMIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IPR_TMR3_CMIA3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IEN_TMR3_CMIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define VECT_TMR3_CMIA3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IR_TMR3_CMIB3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define DTCE_TMR3_CMIB3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IER_TMR3_CMIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IPR_TMR3_CMIB3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IEN_TMR3_CMIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define VECT_TMR3_CMIB3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IR_TMR3_OVI3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define DTCE_TMR3_OVI3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IER_TMR3_OVI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IPR_TMR3_OVI3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IEN_TMR3_OVI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define VECT_TMR3_OVI3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IR_TPU3_TGI3D BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define DTCE_TPU3_TGI3D BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IER_TPU3_TGI3D BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IPR_TPU3_TGI3D BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IEN_TPU3_TGI3D BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define VECT_TPU3_TGI3D BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IR_TPU3_TCI3V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define DTCE_TPU3_TCI3V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IER_TPU3_TCI3V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IPR_TPU3_TCI3V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IEN_TPU3_TCI3V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define VECT_TPU3_TCI3V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IR_TPU4_TGI4A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define DTCE_TPU4_TGI4A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IER_TPU4_TGI4A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IPR_TPU4_TGI4A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IEN_TPU4_TGI4A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define VECT_TPU4_TGI4A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IR_TPU4_TGI4B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define DTCE_TPU4_TGI4B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IER_TPU4_TGI4B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IPR_TPU4_TGI4B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IEN_TPU4_TGI4B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define VECT_TPU4_TGI4B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IR_TPU4_TCI4V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define DTCE_TPU4_TCI4V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IER_TPU4_TCI4V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IPR_TPU4_TCI4V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IEN_TPU4_TCI4V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define VECT_TPU4_TCI4V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IR_TPU4_TCI4U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define DTCE_TPU4_TCI4U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IER_TPU4_TCI4U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IPR_TPU4_TCI4U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IEN_TPU4_TCI4U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define VECT_TPU4_TCI4U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IR_TPU5_TGI5A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define DTCE_TPU5_TGI5A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IER_TPU5_TGI5A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IPR_TPU5_TGI5A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IEN_TPU5_TGI5A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define VECT_TPU5_TGI5A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IR_TPU5_TGI5B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define DTCE_TPU5_TGI5B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IER_TPU5_TGI5B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IPR_TPU5_TGI5B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IEN_TPU5_TGI5B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define VECT_TPU5_TGI5B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IR_TPU5_TCI5V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define DTCE_TPU5_TCI5V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IER_TPU5_TCI5V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IPR_TPU5_TCI5V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IEN_TPU5_TCI5V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define VECT_TPU5_TCI5V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IR_TPU5_TCI5U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define DTCE_TPU5_TCI5U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IER_TPU5_TCI5U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IPR_TPU5_TCI5U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IEN_TPU5_TCI5U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define VECT_TPU5_TCI5U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IR_CMTW0_IC0I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define DTCE_CMTW0_IC0I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IER_CMTW0_IC0I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IPR_CMTW0_IC0I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IEN_CMTW0_IC0I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define VECT_CMTW0_IC0I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IR_CMTW0_IC1I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define DTCE_CMTW0_IC1I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IER_CMTW0_IC1I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IPR_CMTW0_IC1I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IEN_CMTW0_IC1I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define VECT_CMTW0_IC1I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IR_CMTW0_OC0I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define DTCE_CMTW0_OC0I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IER_CMTW0_OC0I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IPR_CMTW0_OC0I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IEN_CMTW0_OC0I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define VECT_CMTW0_OC0I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IR_CMTW0_OC1I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define DTCE_CMTW0_OC1I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IER_CMTW0_OC1I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IPR_CMTW0_OC1I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IEN_CMTW0_OC1I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define VECT_CMTW0_OC1I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IR_CMTW1_IC0I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define DTCE_CMTW1_IC0I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IER_CMTW1_IC0I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IPR_CMTW1_IC0I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IEN_CMTW1_IC0I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define VECT_CMTW1_IC0I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IR_CMTW1_IC1I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define DTCE_CMTW1_IC1I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IER_CMTW1_IC1I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IPR_CMTW1_IC1I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IEN_CMTW1_IC1I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define VECT_CMTW1_IC1I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IR_CMTW1_OC0I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define DTCE_CMTW1_OC0I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IER_CMTW1_OC0I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IPR_CMTW1_OC0I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IEN_CMTW1_OC0I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define VECT_CMTW1_OC0I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IR_CMTW1_OC1I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define DTCE_CMTW1_OC1I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IER_CMTW1_OC1I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IPR_CMTW1_OC1I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IEN_CMTW1_OC1I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define VECT_CMTW1_OC1I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IR_RTC_CUP BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define DTCE_RTC_CUP BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IER_RTC_CUP BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IPR_RTC_CUP BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IEN_RTC_CUP BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define VECT_RTC_CUP BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IR_CAN0_RXF0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define DTCE_CAN0_RXF0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IER_CAN0_RXF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IPR_CAN0_RXF0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IEN_CAN0_RXF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define VECT_CAN0_RXF0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IR_CAN0_TXF0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define DTCE_CAN0_TXF0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IER_CAN0_TXF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IPR_CAN0_TXF0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IEN_CAN0_TXF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define VECT_CAN0_TXF0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IR_CAN0_RXM0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define DTCE_CAN0_RXM0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IER_CAN0_RXM0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IPR_CAN0_RXM0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IEN_CAN0_RXM0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define VECT_CAN0_RXM0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IR_CAN0_TXM0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define DTCE_CAN0_TXM0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IER_CAN0_TXM0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IPR_CAN0_TXM0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IEN_CAN0_TXM0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define VECT_CAN0_TXM0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IR_CAN1_RXF1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define DTCE_CAN1_RXF1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IER_CAN1_RXF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IPR_CAN1_RXF1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IEN_CAN1_RXF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define VECT_CAN1_RXF1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IR_CAN1_TXF1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define DTCE_CAN1_TXF1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IER_CAN1_TXF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IPR_CAN1_TXF1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IEN_CAN1_TXF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define VECT_CAN1_TXF1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IR_CAN1_RXM1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define DTCE_CAN1_RXM1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IER_CAN1_RXM1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IPR_CAN1_RXM1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IEN_CAN1_RXM1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define VECT_CAN1_RXM1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IR_CAN1_TXM1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define DTCE_CAN1_TXM1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IER_CAN1_TXM1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IPR_CAN1_TXM1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IEN_CAN1_TXM1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define VECT_CAN1_TXM1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IR_CAN2_RXF2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define DTCE_CAN2_RXF2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IER_CAN2_RXF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IPR_CAN2_RXF2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IEN_CAN2_RXF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define VECT_CAN2_RXF2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IR_CAN2_TXF2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define DTCE_CAN2_TXF2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IER_CAN2_TXF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IPR_CAN2_TXF2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IEN_CAN2_TXF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define VECT_CAN2_TXF2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IR_CAN2_RXM2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define DTCE_CAN2_RXM2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IER_CAN2_RXM2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IPR_CAN2_RXM2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IEN_CAN2_RXM2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define VECT_CAN2_RXM2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IR_CAN2_TXM2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define DTCE_CAN2_TXM2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IER_CAN2_TXM2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IPR_CAN2_TXM2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IEN_CAN2_TXM2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define VECT_CAN2_TXM2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IR_USB0_USBI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define DTCE_USB0_USBI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IER_USB0_USBI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IPR_USB0_USBI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IEN_USB0_USBI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define VECT_USB0_USBI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IR_S12ADC0_S12ADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define DTCE_S12ADC0_S12ADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IER_S12ADC0_S12ADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IPR_S12ADC0_S12ADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IEN_S12ADC0_S12ADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define VECT_S12ADC0_S12ADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IR_S12ADC0_S12GBADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define DTCE_S12ADC0_S12GBADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IER_S12ADC0_S12GBADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IPR_S12ADC0_S12GBADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IEN_S12ADC0_S12GBADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define VECT_S12ADC0_S12GBADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IR_S12ADC0_S12GCADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define DTCE_S12ADC0_S12GCADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IER_S12ADC0_S12GCADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IPR_S12ADC0_S12GCADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IEN_S12ADC0_S12GCADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define VECT_S12ADC0_S12GCADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IR_S12ADC1_S12ADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define DTCE_S12ADC1_S12ADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IER_S12ADC1_S12ADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IPR_S12ADC1_S12ADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IEN_S12ADC1_S12ADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define VECT_S12ADC1_S12ADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IR_S12ADC1_S12GBADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define DTCE_S12ADC1_S12GBADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IER_S12ADC1_S12GBADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IPR_S12ADC1_S12GBADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IEN_S12ADC1_S12GBADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define VECT_S12ADC1_S12GBADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IR_S12ADC1_S12GCADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define DTCE_S12ADC1_S12GCADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IER_S12ADC1_S12GCADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IPR_S12ADC1_S12GCADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IEN_S12ADC1_S12GCADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define VECT_S12ADC1_S12GCADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IR_ELC_ELSR18I BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define DTCE_ELC_ELSR18I BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IER_ELC_ELSR18I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IPR_ELC_ELSR18I BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IEN_ELC_ELSR18I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define VECT_ELC_ELSR18I BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IR_ELC_ELSR19I BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define DTCE_ELC_ELSR19I BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IER_ELC_ELSR19I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IPR_ELC_ELSR19I BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IEN_ELC_ELSR19I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define VECT_ELC_ELSR19I BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IR_TSIP_PROC_BUSY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define DTCE_TSIP_PROC_BUSY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IER_TSIP_PROC_BUSY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IPR_TSIP_PROC_BUSY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IEN_TSIP_PROC_BUSY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define VECT_TSIP_PROC_BUSY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IR_TSIP_ROMOK BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define DTCE_TSIP_ROMOK BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IER_TSIP_ROMOK BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IPR_TSIP_ROMOK BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IEN_TSIP_ROMOK BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define VECT_TSIP_ROMOK BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IR_TSIP_LONG_PLG BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define DTCE_TSIP_LONG_PLG BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IER_TSIP_LONG_PLG BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IPR_TSIP_LONG_PLG BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IEN_TSIP_LONG_PLG BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define VECT_TSIP_LONG_PLG BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IR_TSIP_TEST_BUSY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define DTCE_TSIP_TEST_BUSY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IER_TSIP_TEST_BUSY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IPR_TSIP_TEST_BUSY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IEN_TSIP_TEST_BUSY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define VECT_TSIP_TEST_BUSY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IR_TSIP_WRRDY0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define DTCE_TSIP_WRRDY0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IER_TSIP_WRRDY0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IPR_TSIP_WRRDY0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IEN_TSIP_WRRDY0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define VECT_TSIP_WRRDY0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IR_TSIP_WRRDY1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define DTCE_TSIP_WRRDY1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IER_TSIP_WRRDY1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IPR_TSIP_WRRDY1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IEN_TSIP_WRRDY1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define VECT_TSIP_WRRDY1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IR_TSIP_WRRDY4 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define DTCE_TSIP_WRRDY4 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IER_TSIP_WRRDY4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IPR_TSIP_WRRDY4 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IEN_TSIP_WRRDY4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define VECT_TSIP_WRRDY4 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IR_TSIP_RDRDY0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define DTCE_TSIP_RDRDY0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IER_TSIP_RDRDY0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IPR_TSIP_RDRDY0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IEN_TSIP_RDRDY0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define VECT_TSIP_RDRDY0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IR_TSIP_RDRDY1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define DTCE_TSIP_RDRDY1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IER_TSIP_RDRDY1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IPR_TSIP_RDRDY1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IEN_TSIP_RDRDY1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define VECT_TSIP_RDRDY1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IR_TSIP_INTEGRATE_WRRDY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define DTCE_TSIP_INTEGRATE_WRRDY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IER_TSIP_INTEGRATE_WRRDY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IPR_TSIP_INTEGRATE_WRRDY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IEN_TSIP_INTEGRATE_WRRDY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define VECT_TSIP_INTEGRATE_WRRDY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IR_TSIP_INTEGRATE_RDRDY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define DTCE_TSIP_INTEGRATE_RDRDY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IER_TSIP_INTEGRATE_RDRDY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IPR_TSIP_INTEGRATE_RDRDY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IEN_TSIP_INTEGRATE_RDRDY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define VECT_TSIP_INTEGRATE_RDRDY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IR_MTU1_TGIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define DTCE_MTU1_TGIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IER_MTU1_TGIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IPR_MTU1_TGIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IEN_MTU1_TGIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define VECT_MTU1_TGIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IR_MTU0_TGIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define DTCE_MTU0_TGIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IER_MTU0_TGIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IPR_MTU0_TGIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IEN_MTU0_TGIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define VECT_MTU0_TGIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IR_MTU0_TGIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define DTCE_MTU0_TGIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IER_MTU0_TGIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IPR_MTU0_TGIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IEN_MTU0_TGIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define VECT_MTU0_TGIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IR_MTU0_TGIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define DTCE_MTU0_TGIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IER_MTU0_TGIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IPR_MTU0_TGIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IEN_MTU0_TGIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define VECT_MTU0_TGIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IR_MTU0_TGID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define DTCE_MTU0_TGID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IER_MTU0_TGID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IPR_MTU0_TGID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IEN_MTU0_TGID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define VECT_MTU0_TGID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IR_MTU0_TCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define DTCE_MTU0_TCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IER_MTU0_TCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IPR_MTU0_TCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IEN_MTU0_TCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define VECT_MTU0_TCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IR_MTU0_TGIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define DTCE_MTU0_TGIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IER_MTU0_TGIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IPR_MTU0_TGIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IEN_MTU0_TGIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define VECT_MTU0_TGIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IR_MTU0_TGIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define DTCE_MTU0_TGIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IER_MTU0_TGIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IPR_MTU0_TGIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IEN_MTU0_TGIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define VECT_MTU0_TGIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IR_MTU1_TGIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define DTCE_MTU1_TGIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IER_MTU1_TGIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IPR_MTU1_TGIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IEN_MTU1_TGIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define VECT_MTU1_TGIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IR_MTU1_TCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define DTCE_MTU1_TCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IER_MTU1_TCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IPR_MTU1_TCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IEN_MTU1_TCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define VECT_MTU1_TCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IR_MTU1_TCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define DTCE_MTU1_TCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IER_MTU1_TCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IPR_MTU1_TCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IEN_MTU1_TCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define VECT_MTU1_TCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IR_MTU2_TGIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define DTCE_MTU2_TGIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IER_MTU2_TGIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IPR_MTU2_TGIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IEN_MTU2_TGIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define VECT_MTU2_TGIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IR_MTU2_TGIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define DTCE_MTU2_TGIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IER_MTU2_TGIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IPR_MTU2_TGIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IEN_MTU2_TGIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define VECT_MTU2_TGIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IR_MTU2_TCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define DTCE_MTU2_TCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IER_MTU2_TCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IPR_MTU2_TCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IEN_MTU2_TCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define VECT_MTU2_TCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IR_MTU2_TCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define DTCE_MTU2_TCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IER_MTU2_TCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IPR_MTU2_TCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IEN_MTU2_TCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define VECT_MTU2_TCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IR_MTU3_TGIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define DTCE_MTU3_TGIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IER_MTU3_TGIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IPR_MTU3_TGIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IEN_MTU3_TGIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define VECT_MTU3_TGIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IR_MTU3_TGIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define DTCE_MTU3_TGIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IER_MTU3_TGIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IPR_MTU3_TGIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IEN_MTU3_TGIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define VECT_MTU3_TGIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IR_MTU3_TGIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define DTCE_MTU3_TGIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IER_MTU3_TGIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IPR_MTU3_TGIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IEN_MTU3_TGIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define VECT_MTU3_TGIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IR_MTU3_TGID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define DTCE_MTU3_TGID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IER_MTU3_TGID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IPR_MTU3_TGID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IEN_MTU3_TGID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define VECT_MTU3_TGID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IR_MTU3_TCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define DTCE_MTU3_TCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IER_MTU3_TCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IPR_MTU3_TCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IEN_MTU3_TCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define VECT_MTU3_TCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IR_MTU4_TGIA4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define DTCE_MTU4_TGIA4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IER_MTU4_TGIA4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IPR_MTU4_TGIA4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IEN_MTU4_TGIA4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define VECT_MTU4_TGIA4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IR_MTU4_TGIB4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define DTCE_MTU4_TGIB4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IER_MTU4_TGIB4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IPR_MTU4_TGIB4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IEN_MTU4_TGIB4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define VECT_MTU4_TGIB4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IR_MTU4_TGIC4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define DTCE_MTU4_TGIC4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IER_MTU4_TGIC4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IPR_MTU4_TGIC4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IEN_MTU4_TGIC4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define VECT_MTU4_TGIC4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IR_MTU4_TGID4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define DTCE_MTU4_TGID4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IER_MTU4_TGID4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IPR_MTU4_TGID4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IEN_MTU4_TGID4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define VECT_MTU4_TGID4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IR_MTU4_TCIV4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define DTCE_MTU4_TCIV4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IER_MTU4_TCIV4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IPR_MTU4_TCIV4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IEN_MTU4_TCIV4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define VECT_MTU4_TCIV4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IR_MTU5_TGIU5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define DTCE_MTU5_TGIU5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IER_MTU5_TGIU5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IPR_MTU5_TGIU5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IEN_MTU5_TGIU5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define VECT_MTU5_TGIU5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IR_MTU5_TGIV5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define DTCE_MTU5_TGIV5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IER_MTU5_TGIV5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IPR_MTU5_TGIV5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IEN_MTU5_TGIV5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define VECT_MTU5_TGIV5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IR_MTU5_TGIW5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define DTCE_MTU5_TGIW5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IER_MTU5_TGIW5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IPR_MTU5_TGIW5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IEN_MTU5_TGIW5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define VECT_MTU5_TGIW5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IR_MTU6_TGIA6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define DTCE_MTU6_TGIA6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IER_MTU6_TGIA6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IPR_MTU6_TGIA6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IEN_MTU6_TGIA6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define VECT_MTU6_TGIA6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IR_MTU6_TGIB6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define DTCE_MTU6_TGIB6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IER_MTU6_TGIB6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IPR_MTU6_TGIB6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IEN_MTU6_TGIB6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define VECT_MTU6_TGIB6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IR_MTU6_TGIC6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define DTCE_MTU6_TGIC6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IER_MTU6_TGIC6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IPR_MTU6_TGIC6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IEN_MTU6_TGIC6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define VECT_MTU6_TGIC6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IR_MTU6_TGID6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define DTCE_MTU6_TGID6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IER_MTU6_TGID6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IPR_MTU6_TGID6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IEN_MTU6_TGID6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define VECT_MTU6_TGID6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IR_MTU6_TCIV6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define DTCE_MTU6_TCIV6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IER_MTU6_TCIV6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IPR_MTU6_TCIV6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IEN_MTU6_TCIV6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define VECT_MTU6_TCIV6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IR_MTU7_TGIA7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define DTCE_MTU7_TGIA7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IER_MTU7_TGIA7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IPR_MTU7_TGIA7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IEN_MTU7_TGIA7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define VECT_MTU7_TGIA7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IR_MTU7_TGIB7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define DTCE_MTU7_TGIB7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IER_MTU7_TGIB7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IPR_MTU7_TGIB7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IEN_MTU7_TGIB7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define VECT_MTU7_TGIB7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IR_MTU7_TGIC7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define DTCE_MTU7_TGIC7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IER_MTU7_TGIC7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IPR_MTU7_TGIC7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IEN_MTU7_TGIC7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define VECT_MTU7_TGIC7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IR_MTU7_TGID7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define DTCE_MTU7_TGID7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IER_MTU7_TGID7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IPR_MTU7_TGID7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IEN_MTU7_TGID7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define VECT_MTU7_TGID7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IR_MTU7_TCIV7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define DTCE_MTU7_TCIV7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IER_MTU7_TCIV7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IPR_MTU7_TCIV7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IEN_MTU7_TCIV7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define VECT_MTU7_TCIV7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IR_MTU8_TGIA8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define DTCE_MTU8_TGIA8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IER_MTU8_TGIA8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IPR_MTU8_TGIA8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IEN_MTU8_TGIA8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define VECT_MTU8_TGIA8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IR_MTU8_TGIB8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define DTCE_MTU8_TGIB8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IER_MTU8_TGIB8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IPR_MTU8_TGIB8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IEN_MTU8_TGIB8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define VECT_MTU8_TGIB8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IR_MTU8_TGIC8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define DTCE_MTU8_TGIC8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IER_MTU8_TGIC8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IPR_MTU8_TGIC8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IEN_MTU8_TGIC8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define VECT_MTU8_TGIC8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IR_MTU8_TGID8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define DTCE_MTU8_TGID8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IER_MTU8_TGID8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IPR_MTU8_TGID8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IEN_MTU8_TGID8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define VECT_MTU8_TGID8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IR_MTU8_TCIV8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define DTCE_MTU8_TCIV8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IER_MTU8_TCIV8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IPR_MTU8_TCIV8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IEN_MTU8_TCIV8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define VECT_MTU8_TCIV8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IR_GPTW0_GTCIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define DTCE_GPTW0_GTCIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IER_GPTW0_GTCIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IPR_GPTW0_GTCIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IEN_GPTW0_GTCIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define VECT_GPTW0_GTCIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IR_GPTW0_GTCIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define DTCE_GPTW0_GTCIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IER_GPTW0_GTCIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IPR_GPTW0_GTCIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IEN_GPTW0_GTCIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define VECT_GPTW0_GTCIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IR_GPTW0_GTCIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define DTCE_GPTW0_GTCIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IER_GPTW0_GTCIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IPR_GPTW0_GTCIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IEN_GPTW0_GTCIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define VECT_GPTW0_GTCIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IR_GPTW0_GTCID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define DTCE_GPTW0_GTCID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IER_GPTW0_GTCID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IPR_GPTW0_GTCID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IEN_GPTW0_GTCID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define VECT_GPTW0_GTCID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IR_GPTW0_GDTE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define DTCE_GPTW0_GDTE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IER_GPTW0_GDTE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IPR_GPTW0_GDTE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IEN_GPTW0_GDTE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define VECT_GPTW0_GDTE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IR_GPTW0_GTCIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define DTCE_GPTW0_GTCIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IER_GPTW0_GTCIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IPR_GPTW0_GTCIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IEN_GPTW0_GTCIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define VECT_GPTW0_GTCIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IR_GPTW0_GTCIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define DTCE_GPTW0_GTCIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IER_GPTW0_GTCIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IPR_GPTW0_GTCIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IEN_GPTW0_GTCIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define VECT_GPTW0_GTCIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IR_GPTW0_GTCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define DTCE_GPTW0_GTCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IER_GPTW0_GTCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IPR_GPTW0_GTCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IEN_GPTW0_GTCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define VECT_GPTW0_GTCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IR_GPTW0_GTCIU0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define DTCE_GPTW0_GTCIU0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IER_GPTW0_GTCIU0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IPR_GPTW0_GTCIU0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IEN_GPTW0_GTCIU0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define VECT_GPTW0_GTCIU0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IR_GPTW1_GTCIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define DTCE_GPTW1_GTCIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IER_GPTW1_GTCIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IPR_GPTW1_GTCIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IEN_GPTW1_GTCIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define VECT_GPTW1_GTCIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IR_GPTW1_GTCIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define DTCE_GPTW1_GTCIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IER_GPTW1_GTCIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IPR_GPTW1_GTCIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IEN_GPTW1_GTCIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define VECT_GPTW1_GTCIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IR_GPTW1_GTCIC1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define DTCE_GPTW1_GTCIC1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IER_GPTW1_GTCIC1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IPR_GPTW1_GTCIC1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IEN_GPTW1_GTCIC1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define VECT_GPTW1_GTCIC1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IR_GPTW1_GTCID1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define DTCE_GPTW1_GTCID1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IER_GPTW1_GTCID1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IPR_GPTW1_GTCID1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IEN_GPTW1_GTCID1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define VECT_GPTW1_GTCID1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IR_GPTW1_GDTE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define DTCE_GPTW1_GDTE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IER_GPTW1_GDTE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IPR_GPTW1_GDTE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IEN_GPTW1_GDTE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define VECT_GPTW1_GDTE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IR_GPTW1_GTCIE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define DTCE_GPTW1_GTCIE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IER_GPTW1_GTCIE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IPR_GPTW1_GTCIE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IEN_GPTW1_GTCIE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define VECT_GPTW1_GTCIE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IR_GPTW1_GTCIF1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define DTCE_GPTW1_GTCIF1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IER_GPTW1_GTCIF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IPR_GPTW1_GTCIF1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IEN_GPTW1_GTCIF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define VECT_GPTW1_GTCIF1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IR_GPTW1_GTCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define DTCE_GPTW1_GTCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IER_GPTW1_GTCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IPR_GPTW1_GTCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IEN_GPTW1_GTCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define VECT_GPTW1_GTCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IR_GPTW1_GTCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define DTCE_GPTW1_GTCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IER_GPTW1_GTCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IPR_GPTW1_GTCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IEN_GPTW1_GTCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define VECT_GPTW1_GTCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IR_GPTW2_GTCIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define DTCE_GPTW2_GTCIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IER_GPTW2_GTCIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IPR_GPTW2_GTCIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IEN_GPTW2_GTCIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define VECT_GPTW2_GTCIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IR_GPTW2_GTCIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define DTCE_GPTW2_GTCIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IER_GPTW2_GTCIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IPR_GPTW2_GTCIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IEN_GPTW2_GTCIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define VECT_GPTW2_GTCIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IR_GPTW2_GTCIC2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define DTCE_GPTW2_GTCIC2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IER_GPTW2_GTCIC2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IPR_GPTW2_GTCIC2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IEN_GPTW2_GTCIC2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define VECT_GPTW2_GTCIC2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IR_GPTW2_GTCID2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define DTCE_GPTW2_GTCID2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IER_GPTW2_GTCID2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IPR_GPTW2_GTCID2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IEN_GPTW2_GTCID2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define VECT_GPTW2_GTCID2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IR_GPTW2_GDTE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define DTCE_GPTW2_GDTE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IER_GPTW2_GDTE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IPR_GPTW2_GDTE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IEN_GPTW2_GDTE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define VECT_GPTW2_GDTE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IR_GPTW2_GTCIE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define DTCE_GPTW2_GTCIE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IER_GPTW2_GTCIE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IPR_GPTW2_GTCIE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IEN_GPTW2_GTCIE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define VECT_GPTW2_GTCIE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IR_GPTW2_GTCIF2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define DTCE_GPTW2_GTCIF2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IER_GPTW2_GTCIF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IPR_GPTW2_GTCIF2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IEN_GPTW2_GTCIF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define VECT_GPTW2_GTCIF2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IR_GPTW2_GTCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define DTCE_GPTW2_GTCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IER_GPTW2_GTCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IPR_GPTW2_GTCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IEN_GPTW2_GTCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define VECT_GPTW2_GTCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IR_GPTW2_GTCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define DTCE_GPTW2_GTCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IER_GPTW2_GTCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IPR_GPTW2_GTCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IEN_GPTW2_GTCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define VECT_GPTW2_GTCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IR_GPTW3_GTCIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define DTCE_GPTW3_GTCIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IER_GPTW3_GTCIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IPR_GPTW3_GTCIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IEN_GPTW3_GTCIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define VECT_GPTW3_GTCIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IR_GPTW3_GTCIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define DTCE_GPTW3_GTCIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IER_GPTW3_GTCIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IPR_GPTW3_GTCIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IEN_GPTW3_GTCIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define VECT_GPTW3_GTCIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IR_GPTW3_GTCIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define DTCE_GPTW3_GTCIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IER_GPTW3_GTCIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IPR_GPTW3_GTCIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IEN_GPTW3_GTCIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define VECT_GPTW3_GTCIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IR_GPTW3_GTCID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define DTCE_GPTW3_GTCID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IER_GPTW3_GTCID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IPR_GPTW3_GTCID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IEN_GPTW3_GTCID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define VECT_GPTW3_GTCID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IR_GPTW3_GDTE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define DTCE_GPTW3_GDTE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IER_GPTW3_GDTE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IPR_GPTW3_GDTE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IEN_GPTW3_GDTE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define VECT_GPTW3_GDTE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IR_GPTW3_GTCIE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define DTCE_GPTW3_GTCIE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IER_GPTW3_GTCIE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IPR_GPTW3_GTCIE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IEN_GPTW3_GTCIE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define VECT_GPTW3_GTCIE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IR_GPTW3_GTCIF3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define DTCE_GPTW3_GTCIF3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IER_GPTW3_GTCIF3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IPR_GPTW3_GTCIF3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IEN_GPTW3_GTCIF3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define VECT_GPTW3_GTCIF3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IR_GPTW3_GTCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define DTCE_GPTW3_GTCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IER_GPTW3_GTCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IPR_GPTW3_GTCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IEN_GPTW3_GTCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define VECT_GPTW3_GTCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IR_GPTW3_GTCIU3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define DTCE_GPTW3_GTCIU3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IER_GPTW3_GTCIU3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IPR_GPTW3_GTCIU3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IEN_GPTW3_GTCIU3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define VECT_GPTW3_GTCIU3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IR_EPTPC_IPLS BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define DTCE_EPTPC_IPLS BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IER_EPTPC_IPLS BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IPR_EPTPC_IPLS BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IEN_EPTPC_IPLS BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define VECT_EPTPC_IPLS BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IR_PMGI0_PMGI0I BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define DTCE_PMGI0_PMGI0I BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IER_PMGI0_PMGI0I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IPR_PMGI0_PMGI0I BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IEN_PMGI0_PMGI0I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define VECT_PMGI0_PMGI0I BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IR_PMGI1_PMGI1I BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define DTCE_PMGI1_PMGI1I BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IER_PMGI1_PMGI1I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IPR_PMGI1_PMGI1I BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IEN_PMGI1_PMGI1I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define VECT_PMGI1_PMGI1I BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_MAPPED_INTERRUPTS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h new file mode 100644 index 000000000..edd0636ae --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h @@ -0,0 +1,360 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts_private.h +* Description : This module contains macros used for mapping interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_PRIVATE_H +#define MCU_MAPPED_INTERRUPTS_PRIVATE_H + +/* These macros are calculated values for x % 8. These macros are used when preprocessor arithmetic cannot be used. + * For example, 'IEN0'-'IEN7' needs to be defined for a macro based on 'vector_number % 8' but preprocessor arithmetic + * is only evaluated at compile-time when it is used in a preprocessor conditional. For this reason the calculated + * value of 'vector_number % 8' must be calculated before compile-time. + */ +#define BSP_PRV_CALC_128_MOD_8 0 +#define BSP_PRV_CALC_129_MOD_8 1 +#define BSP_PRV_CALC_130_MOD_8 2 +#define BSP_PRV_CALC_131_MOD_8 3 +#define BSP_PRV_CALC_132_MOD_8 4 +#define BSP_PRV_CALC_133_MOD_8 5 +#define BSP_PRV_CALC_134_MOD_8 6 +#define BSP_PRV_CALC_135_MOD_8 7 +#define BSP_PRV_CALC_136_MOD_8 0 +#define BSP_PRV_CALC_137_MOD_8 1 +#define BSP_PRV_CALC_138_MOD_8 2 +#define BSP_PRV_CALC_139_MOD_8 3 +#define BSP_PRV_CALC_140_MOD_8 4 +#define BSP_PRV_CALC_141_MOD_8 5 +#define BSP_PRV_CALC_142_MOD_8 6 +#define BSP_PRV_CALC_143_MOD_8 7 +#define BSP_PRV_CALC_144_MOD_8 0 +#define BSP_PRV_CALC_145_MOD_8 1 +#define BSP_PRV_CALC_146_MOD_8 2 +#define BSP_PRV_CALC_147_MOD_8 3 +#define BSP_PRV_CALC_148_MOD_8 4 +#define BSP_PRV_CALC_149_MOD_8 5 +#define BSP_PRV_CALC_150_MOD_8 6 +#define BSP_PRV_CALC_151_MOD_8 7 +#define BSP_PRV_CALC_152_MOD_8 0 +#define BSP_PRV_CALC_153_MOD_8 1 +#define BSP_PRV_CALC_154_MOD_8 2 +#define BSP_PRV_CALC_155_MOD_8 3 +#define BSP_PRV_CALC_156_MOD_8 4 +#define BSP_PRV_CALC_157_MOD_8 5 +#define BSP_PRV_CALC_158_MOD_8 6 +#define BSP_PRV_CALC_159_MOD_8 7 +#define BSP_PRV_CALC_160_MOD_8 0 +#define BSP_PRV_CALC_161_MOD_8 1 +#define BSP_PRV_CALC_162_MOD_8 2 +#define BSP_PRV_CALC_163_MOD_8 3 +#define BSP_PRV_CALC_164_MOD_8 4 +#define BSP_PRV_CALC_165_MOD_8 5 +#define BSP_PRV_CALC_166_MOD_8 6 +#define BSP_PRV_CALC_167_MOD_8 7 +#define BSP_PRV_CALC_168_MOD_8 0 +#define BSP_PRV_CALC_169_MOD_8 1 +#define BSP_PRV_CALC_170_MOD_8 2 +#define BSP_PRV_CALC_171_MOD_8 3 +#define BSP_PRV_CALC_172_MOD_8 4 +#define BSP_PRV_CALC_173_MOD_8 5 +#define BSP_PRV_CALC_174_MOD_8 6 +#define BSP_PRV_CALC_175_MOD_8 7 +#define BSP_PRV_CALC_176_MOD_8 0 +#define BSP_PRV_CALC_177_MOD_8 1 +#define BSP_PRV_CALC_178_MOD_8 2 +#define BSP_PRV_CALC_179_MOD_8 3 +#define BSP_PRV_CALC_180_MOD_8 4 +#define BSP_PRV_CALC_181_MOD_8 5 +#define BSP_PRV_CALC_182_MOD_8 6 +#define BSP_PRV_CALC_183_MOD_8 7 +#define BSP_PRV_CALC_184_MOD_8 0 +#define BSP_PRV_CALC_185_MOD_8 1 +#define BSP_PRV_CALC_186_MOD_8 2 +#define BSP_PRV_CALC_187_MOD_8 3 +#define BSP_PRV_CALC_188_MOD_8 4 +#define BSP_PRV_CALC_189_MOD_8 5 +#define BSP_PRV_CALC_190_MOD_8 6 +#define BSP_PRV_CALC_191_MOD_8 7 +#define BSP_PRV_CALC_192_MOD_8 0 +#define BSP_PRV_CALC_193_MOD_8 1 +#define BSP_PRV_CALC_194_MOD_8 2 +#define BSP_PRV_CALC_195_MOD_8 3 +#define BSP_PRV_CALC_196_MOD_8 4 +#define BSP_PRV_CALC_197_MOD_8 5 +#define BSP_PRV_CALC_198_MOD_8 6 +#define BSP_PRV_CALC_199_MOD_8 7 +#define BSP_PRV_CALC_200_MOD_8 0 +#define BSP_PRV_CALC_201_MOD_8 1 +#define BSP_PRV_CALC_202_MOD_8 2 +#define BSP_PRV_CALC_203_MOD_8 3 +#define BSP_PRV_CALC_204_MOD_8 4 +#define BSP_PRV_CALC_205_MOD_8 5 +#define BSP_PRV_CALC_206_MOD_8 6 +#define BSP_PRV_CALC_207_MOD_8 7 +#define BSP_PRV_CALC_208_MOD_8 0 +#define BSP_PRV_CALC_209_MOD_8 1 +#define BSP_PRV_CALC_210_MOD_8 2 +#define BSP_PRV_CALC_211_MOD_8 3 +#define BSP_PRV_CALC_212_MOD_8 4 +#define BSP_PRV_CALC_213_MOD_8 5 +#define BSP_PRV_CALC_214_MOD_8 6 +#define BSP_PRV_CALC_215_MOD_8 7 +#define BSP_PRV_CALC_216_MOD_8 0 +#define BSP_PRV_CALC_217_MOD_8 1 +#define BSP_PRV_CALC_218_MOD_8 2 +#define BSP_PRV_CALC_219_MOD_8 3 +#define BSP_PRV_CALC_220_MOD_8 4 +#define BSP_PRV_CALC_221_MOD_8 5 +#define BSP_PRV_CALC_222_MOD_8 6 +#define BSP_PRV_CALC_223_MOD_8 7 +#define BSP_PRV_CALC_224_MOD_8 0 +#define BSP_PRV_CALC_225_MOD_8 1 +#define BSP_PRV_CALC_226_MOD_8 2 +#define BSP_PRV_CALC_227_MOD_8 3 +#define BSP_PRV_CALC_228_MOD_8 4 +#define BSP_PRV_CALC_229_MOD_8 5 +#define BSP_PRV_CALC_230_MOD_8 6 +#define BSP_PRV_CALC_231_MOD_8 7 +#define BSP_PRV_CALC_232_MOD_8 0 +#define BSP_PRV_CALC_233_MOD_8 1 +#define BSP_PRV_CALC_234_MOD_8 2 +#define BSP_PRV_CALC_235_MOD_8 3 +#define BSP_PRV_CALC_236_MOD_8 4 +#define BSP_PRV_CALC_237_MOD_8 5 +#define BSP_PRV_CALC_238_MOD_8 6 +#define BSP_PRV_CALC_239_MOD_8 7 +#define BSP_PRV_CALC_240_MOD_8 0 +#define BSP_PRV_CALC_241_MOD_8 1 +#define BSP_PRV_CALC_242_MOD_8 2 +#define BSP_PRV_CALC_243_MOD_8 3 +#define BSP_PRV_CALC_244_MOD_8 4 +#define BSP_PRV_CALC_245_MOD_8 5 +#define BSP_PRV_CALC_246_MOD_8 6 +#define BSP_PRV_CALC_247_MOD_8 7 +#define BSP_PRV_CALC_248_MOD_8 0 +#define BSP_PRV_CALC_249_MOD_8 1 +#define BSP_PRV_CALC_250_MOD_8 2 +#define BSP_PRV_CALC_251_MOD_8 3 +#define BSP_PRV_CALC_252_MOD_8 4 +#define BSP_PRV_CALC_253_MOD_8 5 +#define BSP_PRV_CALC_254_MOD_8 6 +#define BSP_PRV_CALC_255_MOD_8 7 + +/* These macros are used to determine if the SLIBXRn or SLIBRn select register should be written to. */ +#define BSP_PRV_INT_B_SELECT_128 ICU.SLIBXR128.BYTE +#define BSP_PRV_INT_B_SELECT_129 ICU.SLIBXR129.BYTE +#define BSP_PRV_INT_B_SELECT_130 ICU.SLIBXR130.BYTE +#define BSP_PRV_INT_B_SELECT_131 ICU.SLIBXR131.BYTE +#define BSP_PRV_INT_B_SELECT_132 ICU.SLIBXR132.BYTE +#define BSP_PRV_INT_B_SELECT_133 ICU.SLIBXR133.BYTE +#define BSP_PRV_INT_B_SELECT_134 ICU.SLIBXR134.BYTE +#define BSP_PRV_INT_B_SELECT_135 ICU.SLIBXR135.BYTE +#define BSP_PRV_INT_B_SELECT_136 ICU.SLIBXR136.BYTE +#define BSP_PRV_INT_B_SELECT_137 ICU.SLIBXR137.BYTE +#define BSP_PRV_INT_B_SELECT_138 ICU.SLIBXR138.BYTE +#define BSP_PRV_INT_B_SELECT_139 ICU.SLIBXR139.BYTE +#define BSP_PRV_INT_B_SELECT_140 ICU.SLIBXR140.BYTE +#define BSP_PRV_INT_B_SELECT_141 ICU.SLIBXR141.BYTE +#define BSP_PRV_INT_B_SELECT_142 ICU.SLIBXR142.BYTE +#define BSP_PRV_INT_B_SELECT_143 ICU.SLIBXR143.BYTE +#define BSP_PRV_INT_B_SELECT_144 ICU.SLIBR144.BYTE +#define BSP_PRV_INT_B_SELECT_145 ICU.SLIBR145.BYTE +#define BSP_PRV_INT_B_SELECT_146 ICU.SLIBR146.BYTE +#define BSP_PRV_INT_B_SELECT_147 ICU.SLIBR147.BYTE +#define BSP_PRV_INT_B_SELECT_148 ICU.SLIBR148.BYTE +#define BSP_PRV_INT_B_SELECT_149 ICU.SLIBR149.BYTE +#define BSP_PRV_INT_B_SELECT_150 ICU.SLIBR150.BYTE +#define BSP_PRV_INT_B_SELECT_151 ICU.SLIBR151.BYTE +#define BSP_PRV_INT_B_SELECT_152 ICU.SLIBR152.BYTE +#define BSP_PRV_INT_B_SELECT_153 ICU.SLIBR153.BYTE +#define BSP_PRV_INT_B_SELECT_154 ICU.SLIBR154.BYTE +#define BSP_PRV_INT_B_SELECT_155 ICU.SLIBR155.BYTE +#define BSP_PRV_INT_B_SELECT_156 ICU.SLIBR156.BYTE +#define BSP_PRV_INT_B_SELECT_157 ICU.SLIBR157.BYTE +#define BSP_PRV_INT_B_SELECT_158 ICU.SLIBR158.BYTE +#define BSP_PRV_INT_B_SELECT_159 ICU.SLIBR159.BYTE +#define BSP_PRV_INT_B_SELECT_160 ICU.SLIBR160.BYTE +#define BSP_PRV_INT_B_SELECT_161 ICU.SLIBR161.BYTE +#define BSP_PRV_INT_B_SELECT_162 ICU.SLIBR162.BYTE +#define BSP_PRV_INT_B_SELECT_163 ICU.SLIBR163.BYTE +#define BSP_PRV_INT_B_SELECT_164 ICU.SLIBR164.BYTE +#define BSP_PRV_INT_B_SELECT_165 ICU.SLIBR165.BYTE +#define BSP_PRV_INT_B_SELECT_166 ICU.SLIBR166.BYTE +#define BSP_PRV_INT_B_SELECT_167 ICU.SLIBR167.BYTE +#define BSP_PRV_INT_B_SELECT_168 ICU.SLIBR168.BYTE +#define BSP_PRV_INT_B_SELECT_169 ICU.SLIBR169.BYTE +#define BSP_PRV_INT_B_SELECT_170 ICU.SLIBR170.BYTE +#define BSP_PRV_INT_B_SELECT_171 ICU.SLIBR171.BYTE +#define BSP_PRV_INT_B_SELECT_172 ICU.SLIBR172.BYTE +#define BSP_PRV_INT_B_SELECT_173 ICU.SLIBR173.BYTE +#define BSP_PRV_INT_B_SELECT_174 ICU.SLIBR174.BYTE +#define BSP_PRV_INT_B_SELECT_175 ICU.SLIBR175.BYTE +#define BSP_PRV_INT_B_SELECT_176 ICU.SLIBR176.BYTE +#define BSP_PRV_INT_B_SELECT_177 ICU.SLIBR177.BYTE +#define BSP_PRV_INT_B_SELECT_178 ICU.SLIBR178.BYTE +#define BSP_PRV_INT_B_SELECT_179 ICU.SLIBR179.BYTE +#define BSP_PRV_INT_B_SELECT_180 ICU.SLIBR180.BYTE +#define BSP_PRV_INT_B_SELECT_181 ICU.SLIBR181.BYTE +#define BSP_PRV_INT_B_SELECT_182 ICU.SLIBR182.BYTE +#define BSP_PRV_INT_B_SELECT_183 ICU.SLIBR183.BYTE +#define BSP_PRV_INT_B_SELECT_184 ICU.SLIBR184.BYTE +#define BSP_PRV_INT_B_SELECT_185 ICU.SLIBR185.BYTE +#define BSP_PRV_INT_B_SELECT_186 ICU.SLIBR186.BYTE +#define BSP_PRV_INT_B_SELECT_187 ICU.SLIBR187.BYTE +#define BSP_PRV_INT_B_SELECT_188 ICU.SLIBR188.BYTE +#define BSP_PRV_INT_B_SELECT_189 ICU.SLIBR189.BYTE +#define BSP_PRV_INT_B_SELECT_190 ICU.SLIBR190.BYTE +#define BSP_PRV_INT_B_SELECT_191 ICU.SLIBR191.BYTE +#define BSP_PRV_INT_B_SELECT_192 ICU.SLIBR192.BYTE +#define BSP_PRV_INT_B_SELECT_193 ICU.SLIBR193.BYTE +#define BSP_PRV_INT_B_SELECT_194 ICU.SLIBR194.BYTE +#define BSP_PRV_INT_B_SELECT_195 ICU.SLIBR195.BYTE +#define BSP_PRV_INT_B_SELECT_196 ICU.SLIBR196.BYTE +#define BSP_PRV_INT_B_SELECT_197 ICU.SLIBR197.BYTE +#define BSP_PRV_INT_B_SELECT_198 ICU.SLIBR198.BYTE +#define BSP_PRV_INT_B_SELECT_199 ICU.SLIBR199.BYTE +#define BSP_PRV_INT_B_SELECT_200 ICU.SLIBR200.BYTE +#define BSP_PRV_INT_B_SELECT_201 ICU.SLIBR201.BYTE +#define BSP_PRV_INT_B_SELECT_202 ICU.SLIBR202.BYTE +#define BSP_PRV_INT_B_SELECT_203 ICU.SLIBR203.BYTE +#define BSP_PRV_INT_B_SELECT_204 ICU.SLIBR204.BYTE +#define BSP_PRV_INT_B_SELECT_205 ICU.SLIBR205.BYTE +#define BSP_PRV_INT_B_SELECT_206 ICU.SLIBR206.BYTE +#define BSP_PRV_INT_B_SELECT_207 ICU.SLIBR207.BYTE +/* Interrupt A interrupts are also defined even though there is only 1 select register. */ +#define BSP_PRV_INT_A_SELECT_208 ICU.SLIAR208.BYTE +#define BSP_PRV_INT_A_SELECT_209 ICU.SLIAR209.BYTE +#define BSP_PRV_INT_A_SELECT_210 ICU.SLIAR210.BYTE +#define BSP_PRV_INT_A_SELECT_211 ICU.SLIAR211.BYTE +#define BSP_PRV_INT_A_SELECT_212 ICU.SLIAR212.BYTE +#define BSP_PRV_INT_A_SELECT_213 ICU.SLIAR213.BYTE +#define BSP_PRV_INT_A_SELECT_214 ICU.SLIAR214.BYTE +#define BSP_PRV_INT_A_SELECT_215 ICU.SLIAR215.BYTE +#define BSP_PRV_INT_A_SELECT_216 ICU.SLIAR216.BYTE +#define BSP_PRV_INT_A_SELECT_217 ICU.SLIAR217.BYTE +#define BSP_PRV_INT_A_SELECT_218 ICU.SLIAR218.BYTE +#define BSP_PRV_INT_A_SELECT_219 ICU.SLIAR219.BYTE +#define BSP_PRV_INT_A_SELECT_220 ICU.SLIAR220.BYTE +#define BSP_PRV_INT_A_SELECT_221 ICU.SLIAR221.BYTE +#define BSP_PRV_INT_A_SELECT_222 ICU.SLIAR222.BYTE +#define BSP_PRV_INT_A_SELECT_223 ICU.SLIAR223.BYTE +#define BSP_PRV_INT_A_SELECT_224 ICU.SLIAR224.BYTE +#define BSP_PRV_INT_A_SELECT_225 ICU.SLIAR225.BYTE +#define BSP_PRV_INT_A_SELECT_226 ICU.SLIAR226.BYTE +#define BSP_PRV_INT_A_SELECT_227 ICU.SLIAR227.BYTE +#define BSP_PRV_INT_A_SELECT_228 ICU.SLIAR228.BYTE +#define BSP_PRV_INT_A_SELECT_229 ICU.SLIAR229.BYTE +#define BSP_PRV_INT_A_SELECT_230 ICU.SLIAR230.BYTE +#define BSP_PRV_INT_A_SELECT_231 ICU.SLIAR231.BYTE +#define BSP_PRV_INT_A_SELECT_232 ICU.SLIAR232.BYTE +#define BSP_PRV_INT_A_SELECT_233 ICU.SLIAR233.BYTE +#define BSP_PRV_INT_A_SELECT_234 ICU.SLIAR234.BYTE +#define BSP_PRV_INT_A_SELECT_235 ICU.SLIAR235.BYTE +#define BSP_PRV_INT_A_SELECT_236 ICU.SLIAR236.BYTE +#define BSP_PRV_INT_A_SELECT_237 ICU.SLIAR237.BYTE +#define BSP_PRV_INT_A_SELECT_238 ICU.SLIAR238.BYTE +#define BSP_PRV_INT_A_SELECT_239 ICU.SLIAR239.BYTE +#define BSP_PRV_INT_A_SELECT_240 ICU.SLIAR240.BYTE +#define BSP_PRV_INT_A_SELECT_241 ICU.SLIAR241.BYTE +#define BSP_PRV_INT_A_SELECT_242 ICU.SLIAR242.BYTE +#define BSP_PRV_INT_A_SELECT_243 ICU.SLIAR243.BYTE +#define BSP_PRV_INT_A_SELECT_244 ICU.SLIAR244.BYTE +#define BSP_PRV_INT_A_SELECT_245 ICU.SLIAR245.BYTE +#define BSP_PRV_INT_A_SELECT_246 ICU.SLIAR246.BYTE +#define BSP_PRV_INT_A_SELECT_247 ICU.SLIAR247.BYTE +#define BSP_PRV_INT_A_SELECT_248 ICU.SLIAR248.BYTE +#define BSP_PRV_INT_A_SELECT_249 ICU.SLIAR249.BYTE +#define BSP_PRV_INT_A_SELECT_250 ICU.SLIAR250.BYTE +#define BSP_PRV_INT_A_SELECT_251 ICU.SLIAR251.BYTE +#define BSP_PRV_INT_A_SELECT_252 ICU.SLIAR252.BYTE +#define BSP_PRV_INT_A_SELECT_253 ICU.SLIAR253.BYTE +#define BSP_PRV_INT_A_SELECT_254 ICU.SLIAR254.BYTE +#define BSP_PRV_INT_A_SELECT_255 ICU.SLIAR255.BYTE + +/* Start and end of Interrupt B and A vectors. */ +#define BSP_PRV_B_INT_VECTOR_START (128) +#define BSP_PRV_B_INT_VECTOR_END (207) +#define BSP_PRV_A_INT_VECTOR_START (208) +#define BSP_PRV_A_INT_VECTOR_END (255) + +/* Start and end of Interrupt B select registers. */ +#define BSP_PRV_SLIBXR_START (128) +#define BSP_PRV_SLIBXR_END (143) +#define BSP_PRV_SLIBR_START (144) +#define BSP_PRV_SLIBR_END (207) + +/* Starting IER register for mapped interrupts. This is used for calculating the IER register based on the + * given vector number. + */ +#define BSP_PRV_MAP_INT_IER_START (0x10) + +/* These are used in function-like macros to expand to letters. */ +#define BSP_PRV_A A +#define BSP_PRV_B B + +/* Test to see if chosen vector is valid for a mapped interrupt. */ +#define BSP_PRV_VALID_MAP_INT(x, y) (((y + 0) >= BSP_PRV_ ## x ## _INT_VECTOR_START) && \ + ((y + 0) <= BSP_PRV_ ## x ## _INT_VECTOR_END)) + +/* Calculation for getting IER register. */ +#define BSP_PRIV_CALC_IER_REG(x) (((x - BSP_PRV_B_INT_VECTOR_START)/8) + BSP_PRV_MAP_INT_IER_START) + +/* These macros generate the macros needed to use the function-like macros from iodefine.h */ +#define BSP_PRV_IR(x, y) _BSP_PRV_IR(x, y) +#define _BSP_PRV_IR(x, y) IR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_DTCE(x, y) _BSP_PRV_DTCE(x, y) +#define _BSP_PRV_DTCE(x, y) DTCE_PERI ## x ## _INT ## x ## y +#define BSP_PRV_IPR(x, y) _BSP_PRV_IPR(x, y) +#define _BSP_PRV_IPR(x, y) IPR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_VECT(x, y) _BSP_PRV_VECT(x, y) +#define _BSP_PRV_VECT(x, y) VECT_PERI ## x ## _INT ## x ## y + +#define BSP_PRV_IEN(x) _BSP_PRV_IEN(x) +#define _BSP_PRV_IEN(x) __BSP_PRV_IEN(BSP_PRV_CALC_ ## x ## _MOD_8) +#define __BSP_PRV_IEN(x) ___BSP_PRV_IEN(x) +#define ___BSP_PRV_IEN(x) IEN ## x + +/* Chooses the correct interrupt select register. */ +#define BSP_PRV_INT_SELECT(x, y) _BSP_PRV_INT_SELECT(x, y) +#define _BSP_PRV_INT_SELECT(x, y) BSP_PRV_INT_ ## x ## _SELECT_ ## y + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* MCU_MAPPED_INTERRUPTS_PRIVATE_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h new file mode 100644 index 000000000..3e389b0f0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.h +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef CPU_H +#define CPU_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The different types of registers that can be protected. */ +typedef enum +{ + /* PRC0 + Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR2, SCKCR3, PACKCR, PLLCR, + PLLCR2, PPLLCR, PPLLCR2, BCKCR, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOCOCR2, OSTDCR, OSTDSR, CKOCR. */ + BSP_REG_PROTECT_CGC = 0, + + /* PRC1 + Enables writing to the registers related to operating modes, low power consumption, the clock generation circuit, + and software reset: SYSCR0, SYSCR1, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD, OPCCR, RSTCKCR, + DPSBYCR, DPSIER0, DPSIER1, DPSIER2, DPSIER3, DPSIFR0, DPSIFR1, DPSIFR2, DPSIFR3, + DPSIEGR0, DPSIEGR1, DPSIEGR2, DPSIEGR3, MOSCWTCR, SOSCWTCR, MOFCR, HOCOPCR, SWRR. */ + BSP_REG_PROTECT_LPC_CGC_SWR, + + /* PRC3 + Enables writing to the registers related to the LVD:LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /* MPC.PWPR + Enables writing to MPC's PFS registers. */ + BSP_REG_PROTECT_MPC, + + /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/ + BSP_REG_PROTECT_TOTAL_ITEMS +} bsp_reg_protect_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptsDisable(void); +void R_BSP_InterruptsEnable(void); +uint32_t R_BSP_CpuInterruptLevelRead(void); +bool R_BSP_CpuInterruptLevelWrite(uint32_t level); +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareReset(void); + +void bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL. +void bsp_ram_initialize(void); + +#endif /* CPU_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h new file mode 100644 index 000000000..184e6624a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.h +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Lock types. */ +#include "mcu_locks.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOCKING_H +#define LOCKING_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bool R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_HardwareLock(mcu_lock_t const hw_index); +bool R_BSP_HardwareUnlock(mcu_lock_t const hw_index); + +#if BSP_CFG_USER_LOCKING_ENABLED != 0 +/* Is user is using their own lock functions then these are the prototypes. */ +bool BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t const hw_index); +bool BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t const hw_index); +#endif + +#endif /* LOCKING_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/register_access/gnuc/iodefine.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/register_access/gnuc/iodefine.h new file mode 100644 index 000000000..be21f91a7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/register_access/gnuc/iodefine.h @@ -0,0 +1,36689 @@ + + + + + + + + + + + + + + +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/******************************************************************************* +* +* Device : RX/RX700/RX72N +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : V0.50 (2019-03-15) [Hardware Manual Revision : 0.50] +* V1.00C (2019-07-17) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2019 Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX72N */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(BSC,BUSERR) = 0; expands to : */ +/* ICU.IR[16].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(ICU,SWINT2) = 2; expands to : */ +/* IPR(ICU,SWI ) = 2; // SWINT2,SWINT share IPR level. */ +/* ICU.IPR[3].BIT.IPR = 2; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,... expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5,TPUA expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX72NIODEFINE_HEADER__ +#define __RX72NIODEFINE_HEADER__ + +#define IEN_BSC_BUSERR IEN0 +#define IEN_ICU_GROUPIE0 IEN1 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_SSIE0_SSITXI0 IEN6 +#define IEN_SSIE0_SSIRXI0 IEN7 +#define IEN_SSIE1_SSIRTI1 IEN0 +#define IEN_RIIC1_RXI1 IEN2 +#define IEN_RIIC1_TXI1 IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCI8_RXI8 IEN4 +#define IEN_SCI8_TXI8 IEN5 +#define IEN_SCI9_RXI9 IEN6 +#define IEN_SCI9_TXI9 IEN7 +#define IEN_SCI10_RXI10 IEN0 +#define IEN_SCI10_TXI10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL2 IEN3 +#define IEN_RSPI2_SPRI2 IEN4 +#define IEN_RSPI2_SPTI2 IEN5 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCI11_RXI11 IEN2 +#define IEN_SCI11_TXI11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OSTDI IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_ICU_GROUPIE0 17 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_SSIE0_SSITXI0 46 +#define VECT_SSIE0_SSIRXI0 47 +#define VECT_SSIE1_SSIRTI1 48 +#define VECT_RIIC1_RXI1 50 +#define VECT_RIIC1_TXI1 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCI8_RXI8 100 +#define VECT_SCI8_TXI8 101 +#define VECT_SCI9_RXI9 102 +#define VECT_SCI9_TXI9 103 +#define VECT_SCI10_RXI10 104 +#define VECT_SCI10_TXI10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL2 107 +#define VECT_RSPI2_SPRI2 108 +#define VECT_RSPI2_SPTI2 109 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCI11_RXI11 114 +#define VECT_SCI11_TXI11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OSTDI 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPUA SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_GPTW SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW0 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW1 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW2 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW3 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_POEG SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_ETHERC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_PMGI0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ETHERC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_EDMAC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_PMGI1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_EPTPC SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_EPTPC0 SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_EPTPC1 SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_PTPEDMAC SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_GLCDC SYSTEM.MSTPCRC.BIT.MSTPC29 +#define MSTP_DRW2D SYSTEM.MSTPCRC.BIT.MSTPC28 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_ECCRAM SYSTEM.MSTPCRC.BIT.MSTPC6 +#define MSTP_RAM2 SYSTEM.MSTPCRC.BIT.MSTPC2 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_TSIP SYSTEM.MSTPCRD.BIT.MSTPD27 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSIE0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_SSIE1 SYSTEM.MSTPCRD.BIT.MSTPD14 + +#define IS_DPFPU_DPFPUEX IS0 +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_CAN2_ERS2 IS2 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRI IS26 +#define IS_CAC_MENDI IS27 +#define IS_CAC_OVFI IS28 +#define IS_DOC_DOPCI IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_SSIE0_SSIF0 IS17 +#define IS_SSIE1_SSIF1 IS18 +#define IS_S12AD_S12CMPAI IS20 +#define IS_S12AD_S12CMPBI IS21 +#define IS_S12AD1_S12CMPAI1 IS22 +#define IS_S12AD1_S12CMPBI1 IS23 +#define IS_RIIC1_TEI1 IS28 +#define IS_RIIC1_EEI1 IS29 +#define IS_POEG_POEGGAI IS7 +#define IS_POEG_POEGGBI IS8 +#define IS_POEG_POEGGCI IS9 +#define IS_POEG_POEGGDI IS10 +#define IS_SCI8_TEI8 IS0 +#define IS_SCI8_ERI8 IS1 +#define IS_SCI9_TEI9 IS4 +#define IS_SCI9_ERI9 IS5 +#define IS_SCI10_TEI10 IS8 +#define IS_SCI10_ERI10 IS9 +#define IS_SCI11_TEI11 IS12 +#define IS_SCI11_ERI11 IS13 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_RSPI2_SPII2 IS20 +#define IS_RSPI2_SPEI2 IS21 +#define IS_SCI7_TEI7 IS22 +#define IS_SCI7_ERI7 IS23 +#define IS_EPTPC_MINT IS0 +#define IS_PTPEDMAC_PINT IS1 +#define IS_EDMAC0_EINT0 IS4 +#define IS_EDMAC1_EINT1 IS5 +#define IS_GLCDC_VPOS IS8 +#define IS_GLCDC_GR1UF IS9 +#define IS_GLCDC_GR2UF IS10 +#define IS_DRW2D_DRWIRQ IS11 + +#define EN_DPFPU_DPFPUEX EN0 +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_CAN2_ERS2 EN2 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRI EN26 +#define EN_CAC_MENDI EN27 +#define EN_CAC_OVFI EN28 +#define EN_DOC_DOPCI EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_SSIE0_SSIF0 EN17 +#define EN_SSIE1_SSIF1 EN18 +#define EN_S12AD_S12CMPAI EN20 +#define EN_S12AD_S12CMPBI EN21 +#define EN_S12AD1_S12CMPAI1 EN22 +#define EN_S12AD1_S12CMPBI1 EN23 +#define EN_RIIC1_TEI1 EN28 +#define EN_RIIC1_EEI1 EN29 +#define EN_POEG_POEGGAI EN7 +#define EN_POEG_POEGGBI EN8 +#define EN_POEG_POEGGCI EN9 +#define EN_POEG_POEGGDI EN10 +#define EN_SCI8_TEI8 EN0 +#define EN_SCI8_ERI8 EN1 +#define EN_SCI9_TEI9 EN4 +#define EN_SCI9_ERI9 EN5 +#define EN_SCI10_TEI10 EN8 +#define EN_SCI10_ERI10 EN9 +#define EN_SCI11_TEI11 EN12 +#define EN_SCI11_ERI11 EN13 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_RSPI2_SPII2 EN20 +#define EN_RSPI2_SPEI2 EN21 +#define EN_SCI7_TEI7 EN22 +#define EN_SCI7_ERI7 EN23 +#define EN_EPTPC_MINT EN0 +#define EN_PTPEDMAC_PINT EN1 +#define EN_EDMAC0_EINT0 EN4 +#define EN_EDMAC1_EINT1 EN5 +#define EN_GLCDC_VPOS EN8 +#define EN_GLCDC_GR1UF EN9 +#define EN_GLCDC_GR2UF EN10 +#define EN_DRW2D_DRWIRQ EN11 + +#define CLR_DPFPU_DPFPUEX CLR0 +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 +#define CLR_CAN2_ERS2 CLR2 + +#define GEN_DPFPU_DPFPUEX GENIE0 +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_CAN2_ERS2 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRI GENBL0 +#define GEN_CAC_MENDI GENBL0 +#define GEN_CAC_OVFI GENBL0 +#define GEN_DOC_DOPCI GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_SSIE0_SSIF0 GENBL1 +#define GEN_SSIE1_SSIF1 GENBL1 +#define GEN_S12AD_S12CMPAI GENBL1 +#define GEN_S12AD_S12CMPBI GENBL1 +#define GEN_S12AD1_S12CMPAI1 GENBL1 +#define GEN_S12AD1_S12CMPBI1 GENBL1 +#define GEN_RIIC1_TEI1 GENBL1 +#define GEN_RIIC1_EEI1 GENBL1 +#define GEN_POEG_POEGGAI GENBL2 +#define GEN_POEG_POEGGBI GENBL2 +#define GEN_POEG_POEGGCI GENBL2 +#define GEN_POEG_POEGGDI GENBL2 +#define GEN_SCI8_TEI8 GENAL0 +#define GEN_SCI8_ERI8 GENAL0 +#define GEN_SCI9_TEI9 GENAL0 +#define GEN_SCI9_ERI9 GENAL0 +#define GEN_SCI10_TEI10 GENAL0 +#define GEN_SCI10_ERI10 GENAL0 +#define GEN_SCI11_TEI11 GENAL0 +#define GEN_SCI11_ERI11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_RSPI2_SPII2 GENAL0 +#define GEN_RSPI2_SPEI2 GENAL0 +#define GEN_SCI7_TEI7 GENAL0 +#define GEN_SCI7_ERI7 GENAL0 +#define GEN_EPTPC_MINT GENAL1 +#define GEN_PTPEDMAC_PINT GENAL1 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_EDMAC1_EINT1 GENAL1 +#define GEN_GLCDC_VPOS GENAL1 +#define GEN_GLCDC_GR1UF GENAL1 +#define GEN_GLCDC_GR2UF GENAL1 +#define GEN_DRW2D_DRWIRQ GENAL1 + +#define GRP_DPFPU_DPFPUEX GRPIE0 +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_CAN2_ERS2 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRI GRPBL0 +#define GRP_CAC_MENDI GRPBL0 +#define GRP_CAC_OVFI GRPBL0 +#define GRP_DOC_DOPCI GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_SSIE0_SSIF0 GRPBL1 +#define GRP_SSIE1_SSIF1 GRPBL1 +#define GRP_S12AD_S12CMPAI GRPBL1 +#define GRP_S12AD_S12CMPBI GRPBL1 +#define GRP_S12AD1_S12CMPAI1 GRPBL1 +#define GRP_S12AD1_S12CMPBI1 GRPBL1 +#define GRP_RIIC1_TEI1 GRPBL1 +#define GRP_RIIC1_EEI1 GRPBL1 +#define GRP_POEG_POEGGAI GRPBL2 +#define GRP_POEG_POEGGBI GRPBL2 +#define GRP_POEG_POEGGCI GRPBL2 +#define GRP_POEG_POEGGDI GRPBL2 +#define GRP_SCI8_TEI8 GRPAL0 +#define GRP_SCI8_ERI8 GRPAL0 +#define GRP_SCI9_TEI9 GRPAL0 +#define GRP_SCI9_ERI9 GRPAL0 +#define GRP_SCI10_TEI10 GRPAL0 +#define GRP_SCI10_ERI10 GRPAL0 +#define GRP_SCI11_TEI11 GRPAL0 +#define GRP_SCI11_ERI11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_RSPI2_SPII2 GRPAL0 +#define GRP_RSPI2_SPEI2 GRPAL0 +#define GRP_SCI7_TEI7 GRPAL0 +#define GRP_SCI7_ERI7 GRPAL0 +#define GRP_EPTPC_MINT GRPAL1 +#define GRP_PTPEDMAC_PINT GRPAL1 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_EDMAC1_EINT1 GRPAL1 +#define GRP_GLCDC_VPOS GRPAL1 +#define GRP_GLCDC_GR1UF GRPAL1 +#define GRP_GLCDC_GR2UF GRPAL1 +#define GRP_DRW2D_DRWIRQ GRPAL1 + +#define GCR_DPFPU_DPFPUEX GCRIE0 +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 +#define GCR_CAN2_ERS2 GCRBE0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CAN0 (*(volatile struct st_can *)0x90200) +#define CAN1 (*(volatile struct st_can *)0x91200) +#define CAN2 (*(volatile struct st_can *)0x92200) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw *)0x94280) +#define CRC (*(volatile struct st_crc *)0x88280) +#define DA (*(volatile struct st_da *)0x88040) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DMAC4 (*(volatile struct st_dmac1 *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 *)0x821C0) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DRW2D (*(volatile struct st_drw2d *)0xE3000) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ECCRAM (*(volatile struct st_eccram *)0x812C0) +#define EDMAC0 (*(volatile struct st_edmac *)0xC0000) +#define EDMAC1 (*(volatile struct st_edmac *)0xC0200) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define EPTPC (*(volatile struct st_eptpc *)0xC0500) +#define EPTPC0 (*(volatile struct st_eptpc0 *)0xC4800) +#define EPTPC1 (*(volatile struct st_eptpc0 *)0xC4C00) +#define ETHERC0 (*(volatile struct st_etherc *)0xC0100) +#define ETHERC1 (*(volatile struct st_etherc *)0xC0300) +#define EXDMAC (*(volatile struct st_exdmac *)0x82A00) +#define EXDMAC0 (*(volatile struct st_exdmac0 *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 *)0x82840) +#define FLASH (*(volatile struct st_flash *)0x81000) +#define GLCDC (*(volatile struct st_glcdc *)0xE0000) +#define GPTW0 (*(volatile struct st_gptw *)0xC2000) +#define GPTW1 (*(volatile struct st_gptw *)0xC2100) +#define GPTW2 (*(volatile struct st_gptw *)0xC2200) +#define GPTW3 (*(volatile struct st_gptw *)0xC2300) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define MMCIF (*(volatile struct st_mmcif *)0x88500) +#define MPC (*(volatile struct st_mpc *)0x8C100) +#define MPU (*(volatile struct st_mpu *)0x86400) +#define MTU (*(volatile struct st_mtu *)0xC120A) +#define MTU0 (*(volatile struct st_mtu0 *)0xC1290) +#define MTU1 (*(volatile struct st_mtu1 *)0xC1290) +#define MTU2 (*(volatile struct st_mtu2 *)0xC1292) +#define MTU3 (*(volatile struct st_mtu3 *)0xC1200) +#define MTU4 (*(volatile struct st_mtu4 *)0xC1200) +#define MTU5 (*(volatile struct st_mtu5 *)0xC1A94) +#define MTU6 (*(volatile struct st_mtu6 *)0xC1A00) +#define MTU7 (*(volatile struct st_mtu7 *)0xC1A00) +#define MTU8 (*(volatile struct st_mtu8 *)0xC1298) +#define OFSM (*(volatile struct st_ofsm *)0xFE7F5D00) +#define PDC (*(volatile struct st_pdc *)0xA0500) +#define PMGI0 (*(volatile struct st_pmgi *)0xC5880) +#define PMGI1 (*(volatile struct st_pmgi *)0xC5890) +#define POE3 (*(volatile struct st_poe *)0x8C4C0) +#define POEG (*(volatile struct st_poeg *)0x9E000) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT6 (*(volatile struct st_port6 *)0x8C006) +#define PORT7 (*(volatile struct st_port7 *)0x8C007) +#define PORT8 (*(volatile struct st_port8 *)0x8C008) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTF (*(volatile struct st_portf *)0x8C00F) +#define PORTG (*(volatile struct st_portg *)0x8C010) +#define PORTH (*(volatile struct st_porth *)0x8C011) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define PORTK (*(volatile struct st_portk *)0x8C013) +#define PORTL (*(volatile struct st_portl *)0x8C014) +#define PORTM (*(volatile struct st_portm *)0x8C015) +#define PORTN (*(volatile struct st_portn *)0x8C016) +#define PORTQ (*(volatile struct st_portq *)0x8C017) +#define PPG0 (*(volatile struct st_ppg0 *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 *)0x881F0) +#define PTPEDMAC (*(volatile struct st_ptpedmac *)0xC0400) +#define QSPI (*(volatile struct st_qspi *)0x89E00) +#define RAM (*(volatile struct st_ram *)0x81200) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RIIC1 (*(volatile struct st_riic *)0x88320) +#define RIIC2 (*(volatile struct st_riic *)0x88340) +#define RSPI0 (*(volatile struct st_rspi *)0xD0100) +#define RSPI1 (*(volatile struct st_rspi *)0xD0140) +#define RSPI2 (*(volatile struct st_rspi *)0xD0300) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 *)0x89100) +#define SCI0 (*(volatile struct st_sci0 *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 *)0x8A040) +#define SCI3 (*(volatile struct st_sci0 *)0x8A060) +#define SCI4 (*(volatile struct st_sci0 *)0x8A080) +#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0) +#define SCI7 (*(volatile struct st_sci7 *)0xD00E0) +#define SCI8 (*(volatile struct st_sci7 *)0xD0000) +#define SCI9 (*(volatile struct st_sci7 *)0xD0020) +#define SCI10 (*(volatile struct st_sci7 *)0xD0040) +#define SCI11 (*(volatile struct st_sci7 *)0xD0060) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SDHI (*(volatile struct st_sdhi *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci *)0x8A000) +#define SMCI1 (*(volatile struct st_smci *)0x8A020) +#define SMCI2 (*(volatile struct st_smci *)0x8A040) +#define SMCI3 (*(volatile struct st_smci *)0x8A060) +#define SMCI4 (*(volatile struct st_smci *)0x8A080) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci *)0xD00E0) +#define SMCI8 (*(volatile struct st_smci *)0xD0000) +#define SMCI9 (*(volatile struct st_smci *)0xD0020) +#define SMCI10 (*(volatile struct st_smci *)0xD0040) +#define SMCI11 (*(volatile struct st_smci *)0xD0060) +#define SMCI12 (*(volatile struct st_smci *)0x8B300) +#define SSIE0 (*(volatile struct st_ssie *)0x8A500) +#define SSIE1 (*(volatile struct st_ssie *)0x8A540) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x8C500) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 *)0x8810C) +#define TPUA (*(volatile struct st_tpua *)0x88100) +#define USB (*(volatile struct st_usb *)0xA0400) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define WDT (*(volatile struct st_wdt *)0x88020) +#define FLASHCONST (*(volatile struct st_flashconst *)0xFE7F7D90) +#define TEMPSCONST (*(volatile struct st_tempsconst *)0xFE7F7D7C) + +typedef enum enum_ir { +IR_BSC_BUSERR=16,IR_ICU_GROUPIE0=17, +IR_RAM_RAMERR, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT2=26,IR_ICU_SWINT, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMTW0_CMWI0, +IR_CMTW1_CMWI1, +IR_USB0_D0FIFO0=34,IR_USB0_D1FIFO0, +IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0, +IR_RSPI1_SPRI1,IR_RSPI1_SPTI1, +IR_QSPI_SPRI,IR_QSPI_SPTI, +IR_SDHI_SBFAI, +IR_MMCIF_MBFAI, +IR_SSIE0_SSITXI0,IR_SSIE0_SSIRXI0, +IR_SSIE1_SSIRTI1, +IR_RIIC1_RXI1=50,IR_RIIC1_TXI1, +IR_RIIC0_RXI0,IR_RIIC0_TXI0, +IR_RIIC2_RXI2,IR_RIIC2_TXI2, +IR_SCI0_RXI0=58,IR_SCI0_TXI0, +IR_SCI1_RXI1,IR_SCI1_TXI1, +IR_SCI2_RXI2,IR_SCI2_TXI2, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_SCI3_RXI3,IR_SCI3_TXI3, +IR_SCI4_RXI4,IR_SCI4_TXI4, +IR_SCI5_RXI5,IR_SCI5_TXI5, +IR_SCI6_RXI6,IR_SCI6_TXI6, +IR_LVD1_LVD1, +IR_LVD2_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_IWDT_IWUNI=95, +IR_WDT_WUNI, +IR_PDC_PCDFI, +IR_SCI7_RXI7,IR_SCI7_TXI7, +IR_SCI8_RXI8,IR_SCI8_TXI8, +IR_SCI9_RXI9,IR_SCI9_TXI9, +IR_SCI10_RXI10,IR_SCI10_TXI10, +IR_ICU_GROUPBE0,IR_ICU_GROUPBL2, +IR_RSPI2_SPRI2,IR_RSPI2_SPTI2, +IR_ICU_GROUPBL0,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1, +IR_SCI11_RXI11,IR_SCI11_TXI11, +IR_SCI12_RXI12,IR_SCI12_TXI12, +IR_DMAC_DMAC0I=120,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I, +IR_OST_OSTDI, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_PERIB_INTB128,IR_PERIB_INTB129,IR_PERIB_INTB130,IR_PERIB_INTB131,IR_PERIB_INTB132, +IR_PERIB_INTB133,IR_PERIB_INTB134,IR_PERIB_INTB135,IR_PERIB_INTB136,IR_PERIB_INTB137, +IR_PERIB_INTB138,IR_PERIB_INTB139,IR_PERIB_INTB140,IR_PERIB_INTB141,IR_PERIB_INTB142, +IR_PERIB_INTB143,IR_PERIB_INTB144,IR_PERIB_INTB145,IR_PERIB_INTB146,IR_PERIB_INTB147, +IR_PERIB_INTB148,IR_PERIB_INTB149,IR_PERIB_INTB150,IR_PERIB_INTB151,IR_PERIB_INTB152, +IR_PERIB_INTB153,IR_PERIB_INTB154,IR_PERIB_INTB155,IR_PERIB_INTB156,IR_PERIB_INTB157, +IR_PERIB_INTB158,IR_PERIB_INTB159,IR_PERIB_INTB160,IR_PERIB_INTB161,IR_PERIB_INTB162, +IR_PERIB_INTB163,IR_PERIB_INTB164,IR_PERIB_INTB165,IR_PERIB_INTB166,IR_PERIB_INTB167, +IR_PERIB_INTB168,IR_PERIB_INTB169,IR_PERIB_INTB170,IR_PERIB_INTB171,IR_PERIB_INTB172, +IR_PERIB_INTB173,IR_PERIB_INTB174,IR_PERIB_INTB175,IR_PERIB_INTB176,IR_PERIB_INTB177, +IR_PERIB_INTB178,IR_PERIB_INTB179,IR_PERIB_INTB180,IR_PERIB_INTB181,IR_PERIB_INTB182, +IR_PERIB_INTB183,IR_PERIB_INTB184,IR_PERIB_INTB185,IR_PERIB_INTB186,IR_PERIB_INTB187, +IR_PERIB_INTB188,IR_PERIB_INTB189,IR_PERIB_INTB190,IR_PERIB_INTB191,IR_PERIB_INTB192, +IR_PERIB_INTB193,IR_PERIB_INTB194,IR_PERIB_INTB195,IR_PERIB_INTB196,IR_PERIB_INTB197, +IR_PERIB_INTB198,IR_PERIB_INTB199,IR_PERIB_INTB200,IR_PERIB_INTB201,IR_PERIB_INTB202, +IR_PERIB_INTB203,IR_PERIB_INTB204,IR_PERIB_INTB205,IR_PERIB_INTB206,IR_PERIB_INTB207, +IR_PERIA_INTA208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212, +IR_PERIA_INTA213,IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217, +IR_PERIA_INTA218,IR_PERIA_INTA219,IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222, +IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225,IR_PERIA_INTA226,IR_PERIA_INTA227, +IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231,IR_PERIA_INTA232, +IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237, +IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242, +IR_PERIA_INTA243,IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247, +IR_PERIA_INTA248,IR_PERIA_INTA249,IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252, +IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255 +} enum_ir_t; + +typedef enum enum_dtce { +DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USB0_D0FIFO0=34,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSIE0_SSITXI0,DTCE_SSIE0_SSIRXI0, +DTCE_SSIE1_SSIRTI1, +DTCE_RIIC1_RXI1=50,DTCE_RIIC1_TXI1, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0=58,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI=97, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10,DTCE_SCI10_TXI10, +DTCE_RSPI2_SPRI2=108,DTCE_RSPI2_SPTI2, +DTCE_SCI11_RXI11=114,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I=120,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I=126,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +} enum_dtce_t; + +typedef enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_ICU_GROUPIE0=0x02, +IER_RAM_RAMERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMTW0_CMWI0=0x03, +IER_CMTW1_CMWI1=0x03, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04, +IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05, +IER_QSPI_SPRI=0x05,IER_QSPI_SPTI=0x05, +IER_SDHI_SBFAI=0x05, +IER_MMCIF_MBFAI=0x05, +IER_SSIE0_SSITXI0=0x05,IER_SSIE0_SSIRXI0=0x05, +IER_SSIE1_SSIRTI1=0x06, +IER_RIIC1_RXI1=0x06,IER_RIIC1_TXI1=0x06, +IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06, +IER_RIIC2_RXI2=0x06,IER_RIIC2_TXI2=0x06, +IER_SCI0_RXI0=0x07,IER_SCI0_TXI0=0x07, +IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07, +IER_SCI2_RXI2=0x07,IER_SCI2_TXI2=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_SCI3_RXI3=0x0A,IER_SCI3_TXI3=0x0A, +IER_SCI4_RXI4=0x0A,IER_SCI4_TXI4=0x0A, +IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A, +IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A, +IER_LVD1_LVD1=0x0B, +IER_LVD2_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_IWDT_IWUNI=0x0B, +IER_WDT_WUNI=0x0C, +IER_PDC_PCDFI=0x0C, +IER_SCI7_RXI7=0x0C,IER_SCI7_TXI7=0x0C, +IER_SCI8_RXI8=0x0C,IER_SCI8_TXI8=0x0C, +IER_SCI9_RXI9=0x0C,IER_SCI9_TXI9=0x0C, +IER_SCI10_RXI10=0x0D,IER_SCI10_TXI10=0x0D, +IER_ICU_GROUPBE0=0x0D,IER_ICU_GROUPBL2=0x0D, +IER_RSPI2_SPRI2=0x0D,IER_RSPI2_SPTI2=0x0D, +IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E, +IER_SCI11_RXI11=0x0E,IER_SCI11_TXI11=0x0E, +IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E, +IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F, +IER_OST_OSTDI=0x0F, +IER_EXDMAC_EXDMAC0I=0x0F,IER_EXDMAC_EXDMAC1I=0x0F, +IER_PERIB_INTB128=0x10,IER_PERIB_INTB129=0x10,IER_PERIB_INTB130=0x10,IER_PERIB_INTB131=0x10,IER_PERIB_INTB132=0x10, +IER_PERIB_INTB133=0x10,IER_PERIB_INTB134=0x10,IER_PERIB_INTB135=0x10,IER_PERIB_INTB136=0x11,IER_PERIB_INTB137=0x11, +IER_PERIB_INTB138=0x11,IER_PERIB_INTB139=0x11,IER_PERIB_INTB140=0x11,IER_PERIB_INTB141=0x11,IER_PERIB_INTB142=0x11, +IER_PERIB_INTB143=0x11,IER_PERIB_INTB144=0x12,IER_PERIB_INTB145=0x12,IER_PERIB_INTB146=0x12,IER_PERIB_INTB147=0x12, +IER_PERIB_INTB148=0x12,IER_PERIB_INTB149=0x12,IER_PERIB_INTB150=0x12,IER_PERIB_INTB151=0x12,IER_PERIB_INTB152=0x13, +IER_PERIB_INTB153=0x13,IER_PERIB_INTB154=0x13,IER_PERIB_INTB155=0x13,IER_PERIB_INTB156=0x13,IER_PERIB_INTB157=0x13, +IER_PERIB_INTB158=0x13,IER_PERIB_INTB159=0x13,IER_PERIB_INTB160=0x14,IER_PERIB_INTB161=0x14,IER_PERIB_INTB162=0x14, +IER_PERIB_INTB163=0x14,IER_PERIB_INTB164=0x14,IER_PERIB_INTB165=0x14,IER_PERIB_INTB166=0x14,IER_PERIB_INTB167=0x14, +IER_PERIB_INTB168=0x15,IER_PERIB_INTB169=0x15,IER_PERIB_INTB170=0x15,IER_PERIB_INTB171=0x15,IER_PERIB_INTB172=0x15, +IER_PERIB_INTB173=0x15,IER_PERIB_INTB174=0x15,IER_PERIB_INTB175=0x15,IER_PERIB_INTB176=0x16,IER_PERIB_INTB177=0x16, +IER_PERIB_INTB178=0x16,IER_PERIB_INTB179=0x16,IER_PERIB_INTB180=0x16,IER_PERIB_INTB181=0x16,IER_PERIB_INTB182=0x16, +IER_PERIB_INTB183=0x16,IER_PERIB_INTB184=0x17,IER_PERIB_INTB185=0x17,IER_PERIB_INTB186=0x17,IER_PERIB_INTB187=0x17, +IER_PERIB_INTB188=0x17,IER_PERIB_INTB189=0x17,IER_PERIB_INTB190=0x17,IER_PERIB_INTB191=0x17,IER_PERIB_INTB192=0x18, +IER_PERIB_INTB193=0x18,IER_PERIB_INTB194=0x18,IER_PERIB_INTB195=0x18,IER_PERIB_INTB196=0x18,IER_PERIB_INTB197=0x18, +IER_PERIB_INTB198=0x18,IER_PERIB_INTB199=0x18,IER_PERIB_INTB200=0x19,IER_PERIB_INTB201=0x19,IER_PERIB_INTB202=0x19, +IER_PERIB_INTB203=0x19,IER_PERIB_INTB204=0x19,IER_PERIB_INTB205=0x19,IER_PERIB_INTB206=0x19,IER_PERIB_INTB207=0x19, +IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A, +IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A,IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B, +IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B,IER_PERIA_INTA222=0x1B, +IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C, +IER_PERIA_INTA228=0x1C,IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D, +IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D,IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D, +IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E, +IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E, +IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F,IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F, +IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F +} enum_ier_t; + +typedef enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_ICU_GROUPIE0=0, +IPR_RAM_RAMERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMTW0_CMWI0=6, +IPR_CMTW1_CMWI1=7, +IPR_USB0_D0FIFO0=34,IPR_USB0_D1FIFO0=35, +IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39, +IPR_RSPI1_SPRI1=40,IPR_RSPI1_SPTI1=41, +IPR_QSPI_SPRI=42,IPR_QSPI_SPTI=43, +IPR_SDHI_SBFAI=44, +IPR_MMCIF_MBFAI=45, +IPR_SSIE0_SSITXI0=46,IPR_SSIE0_SSIRXI0=47, +IPR_SSIE1_SSIRTI1=48, +IPR_RIIC1_RXI1=50,IPR_RIIC1_TXI1=51, +IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53, +IPR_RIIC2_RXI2=54,IPR_RIIC2_TXI2=55, +IPR_SCI0_RXI0=58,IPR_SCI0_TXI0=59, +IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61, +IPR_SCI2_RXI2=62,IPR_SCI2_TXI2=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_SCI3_RXI3=80,IPR_SCI3_TXI3=81, +IPR_SCI4_RXI4=82,IPR_SCI4_TXI4=83, +IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85, +IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87, +IPR_LVD1_LVD1=88, +IPR_LVD2_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_IWDT_IWUNI=95, +IPR_WDT_WUNI=96, +IPR_PDC_PCDFI=97, +IPR_SCI7_RXI7=98,IPR_SCI7_TXI7=99, +IPR_SCI8_RXI8=100,IPR_SCI8_TXI8=101, +IPR_SCI9_RXI9=102,IPR_SCI9_TXI9=103, +IPR_SCI10_RXI10=104,IPR_SCI10_TXI10=105, +IPR_ICU_GROUPBE0=106,IPR_ICU_GROUPBL2=107, +IPR_RSPI2_SPRI2=108,IPR_RSPI2_SPTI2=109, +IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113, +IPR_SCI11_RXI11=114,IPR_SCI11_TXI11=115, +IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117, +IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124, +IPR_OST_OSTDI=125, +IPR_EXDMAC_EXDMAC0I=126,IPR_EXDMAC_EXDMAC1I=127, +IPR_PERIB_INTB128=128,IPR_PERIB_INTB129=129,IPR_PERIB_INTB130=130,IPR_PERIB_INTB131=131,IPR_PERIB_INTB132=132, +IPR_PERIB_INTB133=133,IPR_PERIB_INTB134=134,IPR_PERIB_INTB135=135,IPR_PERIB_INTB136=136,IPR_PERIB_INTB137=137, +IPR_PERIB_INTB138=138,IPR_PERIB_INTB139=139,IPR_PERIB_INTB140=140,IPR_PERIB_INTB141=141,IPR_PERIB_INTB142=142, +IPR_PERIB_INTB143=143,IPR_PERIB_INTB144=144,IPR_PERIB_INTB145=145,IPR_PERIB_INTB146=146,IPR_PERIB_INTB147=147, +IPR_PERIB_INTB148=148,IPR_PERIB_INTB149=149,IPR_PERIB_INTB150=150,IPR_PERIB_INTB151=151,IPR_PERIB_INTB152=152, +IPR_PERIB_INTB153=153,IPR_PERIB_INTB154=154,IPR_PERIB_INTB155=155,IPR_PERIB_INTB156=156,IPR_PERIB_INTB157=157, +IPR_PERIB_INTB158=158,IPR_PERIB_INTB159=159,IPR_PERIB_INTB160=160,IPR_PERIB_INTB161=161,IPR_PERIB_INTB162=162, +IPR_PERIB_INTB163=163,IPR_PERIB_INTB164=164,IPR_PERIB_INTB165=165,IPR_PERIB_INTB166=166,IPR_PERIB_INTB167=167, +IPR_PERIB_INTB168=168,IPR_PERIB_INTB169=169,IPR_PERIB_INTB170=170,IPR_PERIB_INTB171=171,IPR_PERIB_INTB172=172, +IPR_PERIB_INTB173=173,IPR_PERIB_INTB174=174,IPR_PERIB_INTB175=175,IPR_PERIB_INTB176=176,IPR_PERIB_INTB177=177, +IPR_PERIB_INTB178=178,IPR_PERIB_INTB179=179,IPR_PERIB_INTB180=180,IPR_PERIB_INTB181=181,IPR_PERIB_INTB182=182, +IPR_PERIB_INTB183=183,IPR_PERIB_INTB184=184,IPR_PERIB_INTB185=185,IPR_PERIB_INTB186=186,IPR_PERIB_INTB187=187, +IPR_PERIB_INTB188=188,IPR_PERIB_INTB189=189,IPR_PERIB_INTB190=190,IPR_PERIB_INTB191=191,IPR_PERIB_INTB192=192, +IPR_PERIB_INTB193=193,IPR_PERIB_INTB194=194,IPR_PERIB_INTB195=195,IPR_PERIB_INTB196=196,IPR_PERIB_INTB197=197, +IPR_PERIB_INTB198=198,IPR_PERIB_INTB199=199,IPR_PERIB_INTB200=200,IPR_PERIB_INTB201=201,IPR_PERIB_INTB202=202, +IPR_PERIB_INTB203=203,IPR_PERIB_INTB204=204,IPR_PERIB_INTB205=205,IPR_PERIB_INTB206=206,IPR_PERIB_INTB207=207, +IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212, +IPR_PERIA_INTA213=213,IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217, +IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219,IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222, +IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225,IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227, +IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231,IPR_PERIA_INTA232=232, +IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237, +IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242, +IPR_PERIA_INTA243=243,IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247, +IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249,IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252, +IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255, +IPR_ICU_SWI=3, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_CMTW0_=6, +IPR_CMTW1_=7, +IPR_SDHI_=44, +IPR_MMCIF_=45, +IPR_SSIE1_=48, +IPR_LVD1_=88, +IPR_LVD2_=89, +IPR_IWDT_=95, +IPR_WDT_=96, +IPR_PDC_=97, +IPR_OST_=125 +} enum_ipr_t; + + +#pragma pack(4) + + +typedef struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short BPEB : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short BPEB : 2; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS3WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS4WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS5WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS6WCR2; + char wk11[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS7WCR2; + char wk12[1926]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS0CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS0REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS1CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS1REC; + char wk16[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS2CR; + char wk17[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS2REC; + char wk18[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS3CR; + char wk19[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS3REC; + char wk20[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS4CR; + char wk21[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS4REC; + char wk22[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS5CR; + char wk23[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS5REC; + char wk24[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS6CR; + char wk25[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS6REC; + char wk26[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS7CR; + char wk27[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS7REC; + char wk28[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RCVEN0 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM7 : 1; +#else + unsigned short RCVENM7 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN0 : 1; +#endif + } BIT; + } CSRECEN; + char wk29[894]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXENB : 1; + unsigned char : 3; + unsigned char BSIZE : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BSIZE : 2; + unsigned char : 3; + unsigned char EXENB : 1; +#endif + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EMODE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EMODE : 1; +#endif + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BE : 1; +#endif + } BIT; + } SDAMOD; + char wk30[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SFEN : 1; +#endif + } BIT; + } SDSELF; + char wk31[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 12; + unsigned short REFW : 4; +#else + unsigned short REFW : 4; + unsigned short RFC : 12; +#endif + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RFEN : 1; +#endif + } BIT; + } SDRFEN; + char wk32[9]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char INIRQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char INIRQ : 1; +#endif + } BIT; + } SDICR; + char wk33[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ARFI : 4; + unsigned short ARFC : 4; + unsigned short PRC : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short PRC : 3; + unsigned short ARFC : 4; + unsigned short ARFI : 4; +#endif + } BIT; + } SDIR; + char wk34[26]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MXC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MXC : 2; +#endif + } BIT; + } SDADR; + char wk35[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CL : 3; + unsigned long : 5; + unsigned long WR : 1; + unsigned long RP : 3; + unsigned long RCD : 2; + unsigned long : 2; + unsigned long RAS : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RAS : 3; + unsigned long : 2; + unsigned long RCD : 2; + unsigned long RP : 3; + unsigned long WR : 1; + unsigned long : 5; + unsigned long CL : 3; +#endif + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MR : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short MR : 15; +#endif + } BIT; + } SDMOD; + char wk36[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MRSST : 1; + unsigned char : 2; + unsigned char INIST : 1; + unsigned char SRFST : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SRFST : 1; + unsigned char INIST : 1; + unsigned char : 2; + unsigned char MRSST : 1; +#endif + } BIT; + } SDSR; + char wk37[269231]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PR1SEL : 3; + unsigned long : 1; + unsigned long PR2SEL : 3; + unsigned long : 1; + unsigned long PR3SEL : 3; + unsigned long : 1; + unsigned long PR4SEL : 3; + unsigned long : 1; + unsigned long PR5SEL : 3; + unsigned long : 12; + unsigned long PRERR : 1; +#else + unsigned long PRERR : 1; + unsigned long : 12; + unsigned long PR5SEL : 3; + unsigned long : 1; + unsigned long PR4SEL : 3; + unsigned long : 1; + unsigned long PR3SEL : 3; + unsigned long : 1; + unsigned long PR2SEL : 3; + unsigned long : 1; + unsigned long PR1SEL : 3; +#endif + } BIT; + } EBMAPCR; +} st_bsc_t; + +typedef struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif + } BIT; + } FIDCR1; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MB0 : 1; + unsigned long MB1 : 1; + unsigned long MB2 : 1; + unsigned long MB3 : 1; + unsigned long MB4 : 1; + unsigned long MB5 : 1; + unsigned long MB6 : 1; + unsigned long MB7 : 1; + unsigned long MB8 : 1; + unsigned long MB9 : 1; + unsigned long MB10 : 1; + unsigned long MB11 : 1; + unsigned long MB12 : 1; + unsigned long MB13 : 1; + unsigned long MB14 : 1; + unsigned long MB15 : 1; + unsigned long MB16 : 1; + unsigned long MB17 : 1; + unsigned long MB18 : 1; + unsigned long MB19 : 1; + unsigned long MB20 : 1; + unsigned long MB21 : 1; + unsigned long MB22 : 1; + unsigned long MB23 : 1; + unsigned long MB24 : 1; + unsigned long MB25 : 1; + unsigned long MB26 : 1; + unsigned long MB27 : 1; + unsigned long MB28 : 1; + unsigned long MB29 : 1; + unsigned long MB30 : 1; + unsigned long MB31 : 1; +#else + unsigned long MB31 : 1; + unsigned long MB30 : 1; + unsigned long MB29 : 1; + unsigned long MB28 : 1; + unsigned long MB27 : 1; + unsigned long MB26 : 1; + unsigned long MB25 : 1; + unsigned long MB24 : 1; + unsigned long MB23 : 1; + unsigned long MB22 : 1; + unsigned long MB21 : 1; + unsigned long MB20 : 1; + unsigned long MB19 : 1; + unsigned long MB18 : 1; + unsigned long MB17 : 1; + unsigned long MB16 : 1; + unsigned long MB15 : 1; + unsigned long MB14 : 1; + unsigned long MB13 : 1; + unsigned long MB12 : 1; + unsigned long MB11 : 1; + unsigned long MB10 : 1; + unsigned long MB9 : 1; + unsigned long MB8 : 1; + unsigned long MB7 : 1; + unsigned long MB6 : 1; + unsigned long MB5 : 1; + unsigned long MB4 : 1; + unsigned long MB3 : 1; + unsigned long MB2 : 1; + unsigned long MB1 : 1; + unsigned long MB0 : 1; +#endif + } BIT; + } MKIVLR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MB0 : 1; + unsigned long MB1 : 1; + unsigned long MB2 : 1; + unsigned long MB3 : 1; + unsigned long MB4 : 1; + unsigned long MB5 : 1; + unsigned long MB6 : 1; + unsigned long MB7 : 1; + unsigned long MB8 : 1; + unsigned long MB9 : 1; + unsigned long MB10 : 1; + unsigned long MB11 : 1; + unsigned long MB12 : 1; + unsigned long MB13 : 1; + unsigned long MB14 : 1; + unsigned long MB15 : 1; + unsigned long MB16 : 1; + unsigned long MB17 : 1; + unsigned long MB18 : 1; + unsigned long MB19 : 1; + unsigned long MB20 : 1; + unsigned long MB21 : 1; + unsigned long MB22 : 1; + unsigned long MB23 : 1; + unsigned long MB24 : 1; + unsigned long MB25 : 1; + unsigned long MB26 : 1; + unsigned long MB27 : 1; + unsigned long MB28 : 1; + unsigned long MB29 : 1; + unsigned long MB30 : 1; + unsigned long MB31 : 1; +#else + unsigned long MB31 : 1; + unsigned long MB30 : 1; + unsigned long MB29 : 1; + unsigned long MB28 : 1; + unsigned long MB27 : 1; + unsigned long MB26 : 1; + unsigned long MB25 : 1; + unsigned long MB24 : 1; + unsigned long MB23 : 1; + unsigned long MB22 : 1; + unsigned long MB21 : 1; + unsigned long MB20 : 1; + unsigned long MB19 : 1; + unsigned long MB18 : 1; + unsigned long MB17 : 1; + unsigned long MB16 : 1; + unsigned long MB15 : 1; + unsigned long MB14 : 1; + unsigned long MB13 : 1; + unsigned long MB12 : 1; + unsigned long MB11 : 1; + unsigned long MB10 : 1; + unsigned long MB9 : 1; + unsigned long MB8 : 1; + unsigned long MB7 : 1; + unsigned long MB6 : 1; + unsigned long MB5 : 1; + unsigned long MB4 : 1; + unsigned long MB3 : 1; + unsigned long MB2 : 1; + unsigned long MB1 : 1; + unsigned long MB0 : 1; +#endif + } BIT; + } MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SENTDATA : 1; + unsigned char TRMACTIVE : 1; + unsigned char TRMABT : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char RECREQ : 1; + unsigned char TRMREQ : 1; +#else + unsigned char TRMREQ : 1; + unsigned char RECREQ : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char TRMABT : 1; + unsigned char TRMACTIVE : 1; + unsigned char SENTDATA : 1; +#endif + } TX; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NEWDATA : 1; + unsigned char INVALDATA : 1; + unsigned char MSGLOST : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char RECREQ : 1; + unsigned char TRMREQ : 1; +#else + unsigned char TRMREQ : 1; + unsigned char RECREQ : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char MSGLOST : 1; + unsigned char INVALDATA : 1; + unsigned char NEWDATA : 1; +#endif + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MBM : 1; + unsigned short IDFM : 2; + unsigned short MLM : 1; + unsigned short TPM : 1; + unsigned short TSRC : 1; + unsigned short TSPS : 2; + unsigned short CANM : 2; + unsigned short SLPM : 1; + unsigned short BOM : 2; + unsigned short RBOC : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RBOC : 1; + unsigned short BOM : 2; + unsigned short SLPM : 1; + unsigned short CANM : 2; + unsigned short TSPS : 2; + unsigned short TSRC : 1; + unsigned short TPM : 1; + unsigned short MLM : 1; + unsigned short IDFM : 2; + unsigned short MBM : 1; +#endif + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NDST : 1; + unsigned short SDST : 1; + unsigned short RFST : 1; + unsigned short TFST : 1; + unsigned short NMLST : 1; + unsigned short FMLST : 1; + unsigned short TABST : 1; + unsigned short EST : 1; + unsigned short RSTST : 1; + unsigned short HLTST : 1; + unsigned short SLPST : 1; + unsigned short EPST : 1; + unsigned short BOST : 1; + unsigned short TRMST : 1; + unsigned short RECST : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short RECST : 1; + unsigned short TRMST : 1; + unsigned short BOST : 1; + unsigned short EPST : 1; + unsigned short SLPST : 1; + unsigned short HLTST : 1; + unsigned short RSTST : 1; + unsigned short EST : 1; + unsigned short TABST : 1; + unsigned short FMLST : 1; + unsigned short NMLST : 1; + unsigned short TFST : 1; + unsigned short RFST : 1; + unsigned short SDST : 1; + unsigned short NDST : 1; +#endif + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCLKS : 1; + unsigned long : 7; + unsigned long TSEG2 : 3; + unsigned long : 1; + unsigned long SJW : 2; + unsigned long : 2; + unsigned long BRP : 10; + unsigned long : 2; + unsigned long TSEG1 : 4; +#else + unsigned long TSEG1 : 4; + unsigned long : 2; + unsigned long BRP : 10; + unsigned long : 2; + unsigned long SJW : 2; + unsigned long : 1; + unsigned long TSEG2 : 3; + unsigned long : 7; + unsigned long CCLKS : 1; +#endif + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFE : 1; + unsigned char RFUST : 3; + unsigned char RFMLF : 1; + unsigned char RFFST : 1; + unsigned char RFWST : 1; + unsigned char RFEST : 1; +#else + unsigned char RFEST : 1; + unsigned char RFWST : 1; + unsigned char RFFST : 1; + unsigned char RFMLF : 1; + unsigned char RFUST : 3; + unsigned char RFE : 1; +#endif + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TFE : 1; + unsigned char TFUST : 3; + unsigned char : 2; + unsigned char TFFST : 1; + unsigned char TFEST : 1; +#else + unsigned char TFEST : 1; + unsigned char TFFST : 1; + unsigned char : 2; + unsigned char TFUST : 3; + unsigned char TFE : 1; +#endif + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BEIE : 1; + unsigned char EWIE : 1; + unsigned char EPIE : 1; + unsigned char BOEIE : 1; + unsigned char BORIE : 1; + unsigned char ORIE : 1; + unsigned char OLIE : 1; + unsigned char BLIE : 1; +#else + unsigned char BLIE : 1; + unsigned char OLIE : 1; + unsigned char ORIE : 1; + unsigned char BORIE : 1; + unsigned char BOEIE : 1; + unsigned char EPIE : 1; + unsigned char EWIE : 1; + unsigned char BEIE : 1; +#endif + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BEIF : 1; + unsigned char EWIF : 1; + unsigned char EPIF : 1; + unsigned char BOEIF : 1; + unsigned char BORIF : 1; + unsigned char ORIF : 1; + unsigned char OLIF : 1; + unsigned char BLIF : 1; +#else + unsigned char BLIF : 1; + unsigned char OLIF : 1; + unsigned char ORIF : 1; + unsigned char BORIF : 1; + unsigned char BOEIF : 1; + unsigned char EPIF : 1; + unsigned char EWIF : 1; + unsigned char BEIF : 1; +#endif + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEF : 1; + unsigned char FEF : 1; + unsigned char AEF : 1; + unsigned char CEF : 1; + unsigned char BE1F : 1; + unsigned char BE0F : 1; + unsigned char ADEF : 1; + unsigned char EDPM : 1; +#else + unsigned char EDPM : 1; + unsigned char ADEF : 1; + unsigned char BE0F : 1; + unsigned char BE1F : 1; + unsigned char CEF : 1; + unsigned char AEF : 1; + unsigned char FEF : 1; + unsigned char SEF : 1; +#endif + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MBNST : 5; + unsigned char : 2; + unsigned char SEST : 1; +#else + unsigned char SEST : 1; + unsigned char : 2; + unsigned char MBNST : 5; +#endif + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MBSM : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MBSM : 2; +#endif + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSTE : 1; + unsigned char TSTM : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TSTM : 2; + unsigned char TSTE : 1; +#endif + } BIT; + } TCR; +} st_can_t; + +typedef struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif + } BIT; + } CMSTR1; +} st_cmt_t; + +typedef struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_cmtw { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short STR : 1; +#endif + } BIT; + } CMWSTR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 1; + unsigned short CMWIE : 1; + unsigned short IC0IE : 1; + unsigned short IC1IE : 1; + unsigned short OC0IE : 1; + unsigned short OC1IE : 1; + unsigned short : 1; + unsigned short CMS : 1; + unsigned short : 3; + unsigned short CCLR : 3; +#else + unsigned short CCLR : 3; + unsigned short : 3; + unsigned short CMS : 1; + unsigned short : 1; + unsigned short OC1IE : 1; + unsigned short OC0IE : 1; + unsigned short IC1IE : 1; + unsigned short IC0IE : 1; + unsigned short CMWIE : 1; + unsigned short : 1; + unsigned short CKS : 2; +#endif + } BIT; + } CMWCR; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IC0 : 2; + unsigned short IC1 : 2; + unsigned short IC0E : 1; + unsigned short IC1E : 1; + unsigned short : 2; + unsigned short OC0 : 2; + unsigned short OC1 : 2; + unsigned short OC0E : 1; + unsigned short OC1E : 1; + unsigned short : 1; + unsigned short CMWE : 1; +#else + unsigned short CMWE : 1; + unsigned short : 1; + unsigned short OC1E : 1; + unsigned short OC0E : 1; + unsigned short OC1 : 2; + unsigned short OC0 : 2; + unsigned short : 2; + unsigned short IC1E : 1; + unsigned short IC0E : 1; + unsigned short IC1 : 2; + unsigned short IC0 : 2; +#endif + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +} st_cmtw_t; + +typedef struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 3; + unsigned char : 3; + unsigned char LMS : 1; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char LMS : 1; + unsigned char : 3; + unsigned char GPS : 3; +#endif + } BIT; + } CRCCR; + char wk0[3]; + union { + unsigned long LONG; + unsigned char BYTE; + } CRCDIR; + union { + unsigned long LONG; + unsigned short WORD; + unsigned char BYTE; + } CRCDOR; +} st_crc_t; + +typedef struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char DAE : 1; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char DAE : 1; + unsigned char : 5; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAAMP0 : 1; + unsigned char DAAMP1 : 1; +#else + unsigned char DAAMP1 : 1; + unsigned char DAAMP0 : 1; + unsigned char : 6; +#endif + } BIT; + } DAAMPCR; + char wk1[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAASW0 : 1; + unsigned char DAASW1 : 1; +#else + unsigned char DAASW1 : 1; + unsigned char DAASW0 : 1; + unsigned char : 6; +#endif + } BIT; + } DAASWCR; + char wk2[17763]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char AMADSEL1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char AMADSEL1 : 1; + unsigned char : 1; +#endif + } BIT; + } DAADUSR; +} st_da_t; + +typedef struct st_dmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } DMAST; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char DMIS4 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS7 : 1; +#else + unsigned char DMIS7 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS4 : 1; + unsigned char : 4; +#endif + } BIT; + } DMIST; +} st_dmac_t; + +typedef struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +} st_dmac0_t; + +typedef struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +} st_dmac1_t; + +typedef struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +} st_doc_t; + +typedef struct st_drw2d { + union { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LIM1EN : 1; + unsigned long LIM2EN : 1; + unsigned long LIM3EN : 1; + unsigned long LIM4EN : 1; + unsigned long LIM5EN : 1; + unsigned long LIM6EN : 1; + unsigned long QUAD1EN : 1; + unsigned long QUAD2EN : 1; + unsigned long QUAD3EN : 1; + unsigned long LIM1TH : 1; + unsigned long LIM2TH : 1; + unsigned long LIM3TH : 1; + unsigned long LIM4TH : 1; + unsigned long LIM5TH : 1; + unsigned long LIM6TH : 1; + unsigned long BAND1EN : 1; + unsigned long BAND2EN : 1; + unsigned long UNION12 : 1; + unsigned long UNION34 : 1; + unsigned long UNION56 : 1; + unsigned long UNIONAB : 1; + unsigned long UNIONCD : 1; + unsigned long SPANABT : 1; + unsigned long SPANSTR : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long SPANSTR : 1; + unsigned long SPANABT : 1; + unsigned long UNIONCD : 1; + unsigned long UNIONAB : 1; + unsigned long UNION56 : 1; + unsigned long UNION34 : 1; + unsigned long UNION12 : 1; + unsigned long BAND2EN : 1; + unsigned long BAND1EN : 1; + unsigned long LIM6TH : 1; + unsigned long LIM5TH : 1; + unsigned long LIM4TH : 1; + unsigned long LIM3TH : 1; + unsigned long LIM2TH : 1; + unsigned long LIM1TH : 1; + unsigned long QUAD3EN : 1; + unsigned long QUAD2EN : 1; + unsigned long QUAD1EN : 1; + unsigned long LIM6EN : 1; + unsigned long LIM5EN : 1; + unsigned long LIM4EN : 1; + unsigned long LIM3EN : 1; + unsigned long LIM2EN : 1; + unsigned long LIM1EN : 1; +#endif + } BIT; + } CONTROL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BSYENUM : 1; + unsigned long BSYWR : 1; + unsigned long CACHEDTY : 1; + unsigned long DLSTACT : 1; + unsigned long ENUIR : 1; + unsigned long DLIR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long DLIR : 1; + unsigned long ENUIR : 1; + unsigned long DLSTACT : 1; + unsigned long CACHEDTY : 1; + unsigned long BSYWR : 1; + unsigned long BSYENUM : 1; +#endif + } BIT; + } STATUS; + }; + union { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PTNEN : 1; + unsigned long TEXENA : 1; + unsigned long PTNSRCL5 : 1; + unsigned long USEACB : 1; + unsigned long RDFMT2 : 2; + unsigned long BSFA : 1; + unsigned long BDFA : 1; + unsigned long WRFMT2 : 1; + unsigned long BSF : 1; + unsigned long BDF : 1; + unsigned long BSI : 1; + unsigned long BDI : 1; + unsigned long BC2 : 1; + unsigned long TEXCLPX : 1; + unsigned long TEXCLPY : 1; + unsigned long TEXFILTX : 1; + unsigned long TEXFILTY : 1; + unsigned long RDFMT : 2; + unsigned long WRFMT : 2; + unsigned long WRALPHA : 2; + unsigned long RLEEN : 1; + unsigned long CLUTEN : 1; + unsigned long COLKEYEN : 1; + unsigned long CLUTFORM : 1; + unsigned long BSIA : 1; + unsigned long BDIA : 1; + unsigned long RLEPIXW : 2; +#else + unsigned long RLEPIXW : 2; + unsigned long BDIA : 1; + unsigned long BSIA : 1; + unsigned long CLUTFORM : 1; + unsigned long COLKEYEN : 1; + unsigned long CLUTEN : 1; + unsigned long RLEEN : 1; + unsigned long WRALPHA : 2; + unsigned long WRFMT : 2; + unsigned long RDFMT : 2; + unsigned long TEXFILTY : 1; + unsigned long TEXFILTX : 1; + unsigned long TEXCLPY : 1; + unsigned long TEXCLPX : 1; + unsigned long BC2 : 1; + unsigned long BDI : 1; + unsigned long BSI : 1; + unsigned long BDF : 1; + unsigned long BSF : 1; + unsigned long WRFMT2 : 1; + unsigned long BDFA : 1; + unsigned long BSFA : 1; + unsigned long RDFMT2 : 2; + unsigned long USEACB : 1; + unsigned long PTNSRCL5 : 1; + unsigned long TEXENA : 1; + unsigned long PTNEN : 1; +#endif + } BIT; + } CONTROL2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REV : 12; + unsigned long : 5; + unsigned long DLR : 1; + unsigned long FBCACHE : 1; + unsigned long TXCACHE : 1; + unsigned long PERFCNT : 1; + unsigned long TEXCLUT : 1; + unsigned long : 1; + unsigned long RLEUNIT : 1; + unsigned long TEXCLUT256 : 1; + unsigned long COLKEY : 1; + unsigned long : 1; + unsigned long ACBLD : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long ACBLD : 1; + unsigned long : 1; + unsigned long COLKEY : 1; + unsigned long TEXCLUT256 : 1; + unsigned long RLEUNIT : 1; + unsigned long : 1; + unsigned long TEXCLUT : 1; + unsigned long PERFCNT : 1; + unsigned long TXCACHE : 1; + unsigned long FBCACHE : 1; + unsigned long DLR : 1; + unsigned long : 5; + unsigned long REV : 12; +#endif + } BIT; + } HWVER; + }; + char wk0[8]; + unsigned long L1START; + unsigned long L2START; + unsigned long L3START; + unsigned long L4START; + unsigned long L5START; + unsigned long L6START; + unsigned long L1XADD; + unsigned long L2XADD; + unsigned long L3XADD; + unsigned long L4XADD; + unsigned long L5XADD; + unsigned long L6XADD; + unsigned long L1YADD; + unsigned long L2YADD; + unsigned long L3YADD; + unsigned long L4YADD; + unsigned long L5YADD; + unsigned long L6YADD; + unsigned long L1BAND; + unsigned long L2BAND; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long COL1B : 8; + unsigned long COL1G : 8; + unsigned long COL1R : 8; + unsigned long COL1A : 8; +#else + unsigned long COL1A : 8; + unsigned long COL1R : 8; + unsigned long COL1G : 8; + unsigned long COL1B : 8; +#endif + } BIT; + } COLOR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long COL2B : 8; + unsigned long COL2G : 8; + unsigned long COL2R : 8; + unsigned long COL2A : 8; +#else + unsigned long COL2A : 8; + unsigned long COL2R : 8; + unsigned long COL2G : 8; + unsigned long COL2B : 8; +#endif + } BIT; + } COLOR2; + char wk2[8]; + unsigned long PATTERN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long X : 16; + unsigned long Y : 16; +#else + unsigned long Y : 16; + unsigned long X : 16; +#endif + } BIT; + } SIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PITCH : 16; + unsigned long SSD : 16; +#else + unsigned long SSD : 16; + unsigned long PITCH : 16; +#endif + } BIT; + } PITCH; + unsigned long ORIGIN; + char wk3[12]; + unsigned long LUST; + unsigned long LUXADD; + unsigned long LUYADD; + unsigned long LVSTI; + unsigned long LVSTF; + unsigned long LVXADDI; + unsigned long LVYADDI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LVXADDF : 16; + unsigned long LVYADDF : 16; +#else + unsigned long LVYADDF : 16; + unsigned long LVXADDF : 16; +#endif + } BIT; + } LVYXADDF; + char wk4[4]; + unsigned long TEXPITCH; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TEXUMSK : 11; + unsigned long TEXVMSK : 21; +#else + unsigned long TEXVMSK : 21; + unsigned long TEXUMSK : 11; +#endif + } BIT; + } TEXMSK; + unsigned long TEXORG; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ENUIREN : 1; + unsigned long DLIREN : 1; + unsigned long ENUIRCLR : 1; + unsigned long DLIRCLR : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long DLIRCLR : 1; + unsigned long ENUIRCLR : 1; + unsigned long DLIREN : 1; + unsigned long ENUIREN : 1; +#endif + } BIT; + } IRQCTL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CENFX : 1; + unsigned long CFLUFX : 1; + unsigned long CENTX : 1; + unsigned long CFLUTX : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CFLUTX : 1; + unsigned long CENTX : 1; + unsigned long CFLUFX : 1; + unsigned long CENFX : 1; +#endif + } BIT; + } CACHECTL; + unsigned long DLISTST; + unsigned long PERFCNT1; + unsigned long PERFCNT2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TRG1 : 16; + unsigned long TRG2 : 16; +#else + unsigned long TRG2 : 16; + unsigned long TRG1 : 16; +#endif + } BIT; + } PERFTRG; + char wk5[4]; + unsigned long TEXCLADDR; + unsigned long TEXCLDATA; + unsigned long TEXCLOFST; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif + } BIT; + } COLKEY; +} st_drw2d_t; + +typedef struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; + void *DTCIBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SQTFRL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SQTFRL : 1; +#endif + } BIT; + } DTCOR; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ESPSEL : 1; +#else + unsigned short ESPSEL : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSQE; + unsigned long DTCDISP; +} st_dtc_t; + +typedef struct st_eccram { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMMOD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RAMMOD : 2; +#endif + } BIT; + } ECCRAMMODE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECC2ERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ECC2ERR : 1; +#endif + } BIT; + } ECCRAM2STS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECC1STSEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ECC1STSEN : 1; +#endif + } BIT; + } ECCRAM1STSEN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ECC1ERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ECC1ERR : 1; +#endif + } BIT; + } ECCRAM1STS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PRCR : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char PRCR : 1; +#endif + } BIT; + } ECCRAMPRCR; + char wk0[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long ECC2EAD : 12; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long ECC2EAD : 12; + unsigned long : 3; +#endif + } BIT; + } ECCRAM2ECAD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long ECC1EAD : 12; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long ECC1EAD : 12; + unsigned long : 3; +#endif + } BIT; + } ECCRAM1ECAD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PRCR2 : 1; + unsigned char KW2 : 7; +#else + unsigned char KW2 : 7; + unsigned char PRCR2 : 1; +#endif + } BIT; + } ECCRAMPRCR2; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSTBYP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TSTBYP : 1; +#endif + } BIT; + } ECCRAMETST; +} st_eccram_t; + +typedef struct st_edmac { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SWR : 1; + unsigned long : 3; + unsigned long DL : 2; + unsigned long DE : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long DE : 1; + unsigned long DL : 2; + unsigned long : 3; + unsigned long SWR : 1; +#endif + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long TR : 1; +#endif + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RR : 1; +#endif + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CERF : 1; + unsigned long PRE : 1; + unsigned long RTSF : 1; + unsigned long RTLF : 1; + unsigned long RRF : 1; + unsigned long : 2; + unsigned long RMAF : 1; + unsigned long TRO : 1; + unsigned long CD : 1; + unsigned long DLC : 1; + unsigned long CND : 1; + unsigned long : 4; + unsigned long RFOF : 1; + unsigned long RDE : 1; + unsigned long FR : 1; + unsigned long TFUF : 1; + unsigned long TDE : 1; + unsigned long TC : 1; + unsigned long ECI : 1; + unsigned long : 1; + unsigned long RFCOF : 1; + unsigned long RABT : 1; + unsigned long TABT : 1; + unsigned long : 3; + unsigned long TWB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWB : 1; + unsigned long : 3; + unsigned long TABT : 1; + unsigned long RABT : 1; + unsigned long RFCOF : 1; + unsigned long : 1; + unsigned long ECI : 1; + unsigned long TC : 1; + unsigned long TDE : 1; + unsigned long TFUF : 1; + unsigned long FR : 1; + unsigned long RDE : 1; + unsigned long RFOF : 1; + unsigned long : 4; + unsigned long CND : 1; + unsigned long DLC : 1; + unsigned long CD : 1; + unsigned long TRO : 1; + unsigned long RMAF : 1; + unsigned long : 2; + unsigned long RRF : 1; + unsigned long RTLF : 1; + unsigned long RTSF : 1; + unsigned long PRE : 1; + unsigned long CERF : 1; +#endif + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CERFIP : 1; + unsigned long PREIP : 1; + unsigned long RTSFIP : 1; + unsigned long RTLFIP : 1; + unsigned long RRFIP : 1; + unsigned long : 2; + unsigned long RMAFIP : 1; + unsigned long TROIP : 1; + unsigned long CDIP : 1; + unsigned long DLCIP : 1; + unsigned long CNDIP : 1; + unsigned long : 4; + unsigned long RFOFIP : 1; + unsigned long RDEIP : 1; + unsigned long FRIP : 1; + unsigned long TFUFIP : 1; + unsigned long TDEIP : 1; + unsigned long TCIP : 1; + unsigned long ECIIP : 1; + unsigned long : 1; + unsigned long RFCOFIP : 1; + unsigned long RABTIP : 1; + unsigned long TABTIP : 1; + unsigned long : 3; + unsigned long TWBIP : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWBIP : 1; + unsigned long : 3; + unsigned long TABTIP : 1; + unsigned long RABTIP : 1; + unsigned long RFCOFIP : 1; + unsigned long : 1; + unsigned long ECIIP : 1; + unsigned long TCIP : 1; + unsigned long TDEIP : 1; + unsigned long TFUFIP : 1; + unsigned long FRIP : 1; + unsigned long RDEIP : 1; + unsigned long RFOFIP : 1; + unsigned long : 4; + unsigned long CNDIP : 1; + unsigned long DLCIP : 1; + unsigned long CDIP : 1; + unsigned long TROIP : 1; + unsigned long RMAFIP : 1; + unsigned long : 2; + unsigned long RRFIP : 1; + unsigned long RTLFIP : 1; + unsigned long RTSFIP : 1; + unsigned long PREIP : 1; + unsigned long CERFIP : 1; +#endif + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RRFCE : 1; + unsigned long : 2; + unsigned long RMAFCE : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RMAFCE : 1; + unsigned long : 2; + unsigned long RRFCE : 1; + unsigned long : 4; +#endif + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MFC : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MFC : 16; +#endif + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TFT : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long TFT : 11; +#endif + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFD : 5; + unsigned long : 3; + unsigned long TFD : 5; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long TFD : 5; + unsigned long : 3; + unsigned long RFD : 5; +#endif + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RNR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RNR : 1; +#endif + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UNDER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long UNDER : 16; +#endif + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long OVER : 16; +#endif + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ELB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long ELB : 1; +#endif + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDO : 3; + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; + unsigned long RFDO : 3; +#endif + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PADR : 6; + unsigned long : 10; + unsigned long PADS : 2; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long PADS : 2; + unsigned long : 10; + unsigned long PADR : 6; +#endif + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TIS : 1; + unsigned long : 3; + unsigned long TIM : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long TIM : 1; + unsigned long : 3; + unsigned long TIS : 1; +#endif + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_edmac_t; + +typedef struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR0; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR7; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR10; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR11; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR12; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR13; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR16; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR18; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR19; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR20; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR21; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR22; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR23; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR25; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR26; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR27; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR28; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0MD : 2; + unsigned char : 4; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char : 4; + unsigned char MTU0MD : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR3MD : 2; +#else + unsigned char TMR3MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL3; + union { + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; + } BIT; +#endif + } ELSEGR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR33; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR35; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR36; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR37; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR38; + char wk8[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR45; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPU0MD : 2; + unsigned char TPU1MD : 2; + unsigned char TPU2MD : 2; + unsigned char TPU3MD : 2; +#else + unsigned char TPU3MD : 2; + unsigned char TPU2MD : 2; + unsigned char TPU1MD : 2; + unsigned char TPU0MD : 2; +#endif + } BIT; + } ELOPF; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMTW0MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMTW0MD : 2; +#endif + } BIT; + } ELOPH; + char wk11[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR48; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR49; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR50; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR51; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR52; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR53; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR54; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR55; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR56; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR57; +} st_elc_t; + +typedef struct st_eptpc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RESET : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RESET : 1; +#endif + } BIT; + } PTRSTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SCLKDIV : 3; + unsigned long : 5; + unsigned long SCLKSEL : 3; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long SCLKSEL : 3; + unsigned long : 5; + unsigned long SCLKDIV : 3; +#endif + } BIT; + } STCSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BYPASS0 : 1; + unsigned long : 15; + unsigned long BYPASS1 : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long BYPASS1 : 1; + unsigned long : 15; + unsigned long BYPASS0 : 1; +#endif + } BIT; + } SYBYPSR; + char wk0[15092]; + unsigned long MIESR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ST : 1; + unsigned long SY0 : 1; + unsigned long SY1 : 1; + unsigned long PR : 1; + unsigned long : 12; + unsigned long CYC0 : 1; + unsigned long CYC1 : 1; + unsigned long CYC2 : 1; + unsigned long CYC3 : 1; + unsigned long CYC4 : 1; + unsigned long CYC5 : 1; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long CYC5 : 1; + unsigned long CYC4 : 1; + unsigned long CYC3 : 1; + unsigned long CYC2 : 1; + unsigned long CYC1 : 1; + unsigned long CYC0 : 1; + unsigned long : 12; + unsigned long PR : 1; + unsigned long SY1 : 1; + unsigned long SY0 : 1; + unsigned long ST : 1; +#endif + } BIT; + } MIEIPR; + char wk1[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYCP0 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP5 : 1; + unsigned long : 2; + unsigned long CYCN0 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN5 : 1; + unsigned long : 2; + unsigned long PLSP : 1; + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; + unsigned long PLSP : 1; + unsigned long : 2; + unsigned long CYCN5 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN0 : 1; + unsigned long : 2; + unsigned long CYCP5 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP0 : 1; +#endif + } BIT; + } ELIPPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYCP0 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP5 : 1; + unsigned long : 2; + unsigned long CYCN0 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN5 : 1; + unsigned long : 2; + unsigned long PLSP : 1; + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long PLSN : 1; + unsigned long : 7; + unsigned long PLSP : 1; + unsigned long : 2; + unsigned long CYCN5 : 1; + unsigned long CYCN4 : 1; + unsigned long CYCN3 : 1; + unsigned long CYCN2 : 1; + unsigned long CYCN1 : 1; + unsigned long CYCN0 : 1; + unsigned long : 2; + unsigned long CYCP5 : 1; + unsigned long CYCP4 : 1; + unsigned long CYCP3 : 1; + unsigned long CYCP2 : 1; + unsigned long CYCP1 : 1; + unsigned long CYCP0 : 1; +#endif + } BIT; + } ELIPACR; + char wk2[40]; + unsigned long STSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SYNC : 1; + unsigned long SYNCOUT : 1; + unsigned long : 1; + unsigned long SYNTOUT : 1; + unsigned long W10D : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long W10D : 1; + unsigned long SYNTOUT : 1; + unsigned long : 1; + unsigned long SYNCOUT : 1; + unsigned long SYNC : 1; +#endif + } BIT; + } STIPR; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STCF : 2; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long STCF : 2; +#endif + } BIT; + } STCFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WINT : 8; + unsigned long : 5; + unsigned long CMOD : 1; + unsigned long : 1; + unsigned long W10S : 1; + unsigned long SYTH : 4; + unsigned long DVTH : 4; + unsigned long : 4; + unsigned long ALEN0 : 1; + unsigned long ALEN1 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long ALEN1 : 1; + unsigned long ALEN0 : 1; + unsigned long : 4; + unsigned long DVTH : 4; + unsigned long SYTH : 4; + unsigned long W10S : 1; + unsigned long : 1; + unsigned long CMOD : 1; + unsigned long : 5; + unsigned long WINT : 8; +#endif + } BIT; + } STMR; + unsigned long SYNTOR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IPTSEL0 : 1; + unsigned long IPTSEL1 : 1; + unsigned long IPTSEL2 : 1; + unsigned long IPTSEL3 : 1; + unsigned long IPTSEL4 : 1; + unsigned long IPTSEL5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long IPTSEL5 : 1; + unsigned long IPTSEL4 : 1; + unsigned long IPTSEL3 : 1; + unsigned long IPTSEL2 : 1; + unsigned long IPTSEL1 : 1; + unsigned long IPTSEL0 : 1; +#endif + } BIT; + } IPTSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MINTEN0 : 1; + unsigned long MINTEN1 : 1; + unsigned long MINTEN2 : 1; + unsigned long MINTEN3 : 1; + unsigned long MINTEN4 : 1; + unsigned long MINTEN5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long MINTEN5 : 1; + unsigned long MINTEN4 : 1; + unsigned long MINTEN3 : 1; + unsigned long MINTEN2 : 1; + unsigned long MINTEN1 : 1; + unsigned long MINTEN0 : 1; +#endif + } BIT; + } MITSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ELTDIS0 : 1; + unsigned long ELTDIS1 : 1; + unsigned long ELTDIS2 : 1; + unsigned long ELTDIS3 : 1; + unsigned long ELTDIS4 : 1; + unsigned long ELTDIS5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long ELTDIS5 : 1; + unsigned long ELTDIS4 : 1; + unsigned long ELTDIS3 : 1; + unsigned long ELTDIS2 : 1; + unsigned long ELTDIS1 : 1; + unsigned long ELTDIS0 : 1; +#endif + } BIT; + } ELTSELR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SYSEL : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SYSEL : 1; +#endif + } BIT; + } STCHSELR; + char wk5[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long STR : 1; +#endif + } BIT; + } SYNSTARTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LOAD : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long LOAD : 1; +#endif + } BIT; + } LCIVLDR; + char wk6[8]; + unsigned long SYNTDARU; + unsigned long SYNTDARL; + unsigned long SYNTDBRU; + unsigned long SYNTDBRL; + char wk7[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VALU : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long VALU : 16; +#endif + } BIT; + } LCIVRU; + unsigned long LCIVRM; + unsigned long LCIVRL; + char wk8[104]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GW10 : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long GW10 : 1; +#endif + } BIT; + } GETW10R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMTU : 31; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long LMTU : 31; +#endif + } BIT; + } PLIMITRU; + unsigned long PLIMITRM; + unsigned long PLIMITRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMTU : 31; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long LMTU : 31; +#endif + } BIT; + } MLIMITRU; + unsigned long MLIMITRM; + unsigned long MLIMITRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INFO : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long INFO : 1; +#endif + } BIT; + } GETINFOR; + char wk9[44]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CNTU : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CNTU : 16; +#endif + } BIT; + } LCCVRU; + unsigned long LCCVRM; + unsigned long LCCVRL; + char wk10[148]; + unsigned long PW10VRU; + unsigned long PW10VRM; + unsigned long PW10VRL; + char wk11[180]; + unsigned long MW10RU; + unsigned long MW10RM; + unsigned long MW10RL; + char wk12[36]; + unsigned long TMSTTRU0; + unsigned long TMSTTRL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR0; + unsigned long TMSTTRU1; + unsigned long TMSTTRL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR1; + unsigned long TMSTTRU2; + unsigned long TMSTTRL2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR2; + unsigned long TMSTTRU3; + unsigned long TMSTTRL3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR3; + unsigned long TMSTTRU4; + unsigned long TMSTTRL4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR4; + unsigned long TMSTTRU5; + unsigned long TMSTTRL5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CYC : 30; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long CYC : 30; +#endif + } BIT; + } TMCYCR5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WTH : 29; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WTH : 29; +#endif + } BIT; + } TMPLSR5; + char wk13[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } TMSTARTR; + char wk14[128]; + unsigned long PRSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVRE0 : 1; + unsigned long OVRE1 : 1; + unsigned long OVRE2 : 1; + unsigned long OVRE3 : 1; + unsigned long : 4; + unsigned long MACE : 1; + unsigned long : 19; + unsigned long URE0 : 1; + unsigned long URE1 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long URE1 : 1; + unsigned long URE0 : 1; + unsigned long : 19; + unsigned long MACE : 1; + unsigned long : 4; + unsigned long OVRE3 : 1; + unsigned long OVRE2 : 1; + unsigned long OVRE1 : 1; + unsigned long OVRE0 : 1; +#endif + } BIT; + } PRIPR; + char wk15[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PRMACRU0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PRMACRL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PRMACRU1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PRMACRL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDIS : 2; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long TDIS : 2; +#endif + } BIT; + } TRNDISR; + char wk16[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MOD : 1; + unsigned long : 7; + unsigned long FWD0 : 1; + unsigned long FWD1 : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long FWD1 : 1; + unsigned long FWD0 : 1; + unsigned long : 7; + unsigned long MOD : 1; +#endif + } BIT; + } TRNMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long THVAL : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long THVAL : 11; +#endif + } BIT; + } TRNCTTDR; +} st_eptpc_t; + +typedef struct st_eptpc0 { + unsigned long SYSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OFMUD : 1; + unsigned long INTCHG : 1; + unsigned long MPDUD : 1; + unsigned long : 1; + unsigned long DRPTO : 1; + unsigned long INTDEV : 1; + unsigned long DRQOVR : 1; + unsigned long : 5; + unsigned long RECLP : 1; + unsigned long : 1; + unsigned long INFABT : 1; + unsigned long : 1; + unsigned long RESDN : 1; + unsigned long GENDN : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long GENDN : 1; + unsigned long RESDN : 1; + unsigned long : 1; + unsigned long INFABT : 1; + unsigned long : 1; + unsigned long RECLP : 1; + unsigned long : 5; + unsigned long DRQOVR : 1; + unsigned long INTDEV : 1; + unsigned long DRPTO : 1; + unsigned long : 1; + unsigned long MPDUD : 1; + unsigned long INTCHG : 1; + unsigned long OFMUD : 1; +#endif + } BIT; + } SYIPR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } SYMACRU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } SYMACRL; + unsigned long SYLLCCTLR; + unsigned long SYIPADDRR; + char wk1[32]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VER : 4; + unsigned long TRSP : 4; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TRSP : 4; + unsigned long VER : 4; +#endif + } BIT; + } SYSPVRR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DNUM : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long DNUM : 8; +#endif + } BIT; + } SYDOMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FLAG0 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG5 : 1; + unsigned long : 2; + unsigned long FLAG8 : 1; + unsigned long : 1; + unsigned long FLAG10 : 1; + unsigned long : 2; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long : 2; + unsigned long FLAG10 : 1; + unsigned long : 1; + unsigned long FLAG8 : 1; + unsigned long : 2; + unsigned long FLAG5 : 1; + unsigned long FLAG4 : 1; + unsigned long FLAG3 : 1; + unsigned long FLAG2 : 1; + unsigned long FLAG1 : 1; + unsigned long FLAG0 : 1; +#endif + } BIT; + } ANFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long FLAG8 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG10 : 1; + unsigned long : 2; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long : 2; + unsigned long FLAG10 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG8 : 1; + unsigned long : 8; +#endif + } BIT; + } SYNFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long FLAG10 : 1; + unsigned long : 2; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long : 2; + unsigned long FLAG10 : 1; + unsigned long : 10; +#endif + } BIT; + } DYRQFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long FLAG8 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG10 : 1; + unsigned long : 2; + unsigned long FLAG13 : 1; + unsigned long FLAG14 : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long FLAG14 : 1; + unsigned long FLAG13 : 1; + unsigned long : 2; + unsigned long FLAG10 : 1; + unsigned long FLAG9 : 1; + unsigned long FLAG8 : 1; + unsigned long : 8; +#endif + } BIT; + } DYRPFR; + unsigned long SYCIDRU; + unsigned long SYCIDRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PNUM : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PNUM : 16; +#endif + } BIT; + } SYPNUMR; + char wk3[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BMUP : 1; + unsigned long STUP : 1; + unsigned long ANUP : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long ANUP : 1; + unsigned long STUP : 1; + unsigned long BMUP : 1; +#endif + } BIT; + } SYRVLDR; + char wk4[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 2; + unsigned long : 2; + unsigned long SYNC : 3; + unsigned long : 1; + unsigned long FUP : 3; + unsigned long : 1; + unsigned long DRQ : 3; + unsigned long : 1; + unsigned long DRP : 3; + unsigned long : 1; + unsigned long PDRQ : 3; + unsigned long : 1; + unsigned long PDRP : 3; + unsigned long : 1; + unsigned long PDFUP : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long PDFUP : 3; + unsigned long : 1; + unsigned long PDRP : 3; + unsigned long : 1; + unsigned long PDRQ : 3; + unsigned long : 1; + unsigned long DRP : 3; + unsigned long : 1; + unsigned long DRQ : 3; + unsigned long : 1; + unsigned long FUP : 3; + unsigned long : 1; + unsigned long SYNC : 3; + unsigned long : 2; + unsigned long ANCE : 2; +#endif + } BIT; + } SYRFL1R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MAN : 2; + unsigned long : 2; + unsigned long SIG : 2; + unsigned long : 22; + unsigned long ILL : 2; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long ILL : 2; + unsigned long : 22; + unsigned long SIG : 2; + unsigned long : 2; + unsigned long MAN : 2; +#endif + } BIT; + } SYRFL2R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 1; + unsigned long : 3; + unsigned long SYNC : 1; + unsigned long : 3; + unsigned long DRQ : 1; + unsigned long : 3; + unsigned long PDRQ : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long PDRQ : 1; + unsigned long : 3; + unsigned long DRQ : 1; + unsigned long : 3; + unsigned long SYNC : 1; + unsigned long : 3; + unsigned long ANCE : 1; +#endif + } BIT; + } SYTRENR; + char wk5[4]; + unsigned long MTCIDU; + unsigned long MTCIDL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PNUM : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PNUM : 16; +#endif + } BIT; + } MTPID; + char wk6[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 8; + unsigned long SYNC : 8; + unsigned long DREQ : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DREQ : 8; + unsigned long SYNC : 8; + unsigned long ANCE : 8; +#endif + } BIT; + } SYTLIR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ANCE : 8; + unsigned long SYNC : 8; + unsigned long DRESP : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DRESP : 8; + unsigned long SYNC : 8; + unsigned long ANCE : 8; +#endif + } BIT; + } SYRLIR; + unsigned long OFMRU; + unsigned long OFMRL; + unsigned long MPDRU; + unsigned long MPDRL; + char wk7[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GMPR2 : 8; + unsigned long : 8; + unsigned long GMPR1 : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long GMPR1 : 8; + unsigned long : 8; + unsigned long GMPR2 : 8; +#endif + } BIT; + } GMPR; + unsigned long GMCQR; + unsigned long GMIDRU; + unsigned long GMIDRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TSRC : 8; + unsigned long : 8; + unsigned long CUTO : 16; +#else + unsigned long CUTO : 16; + unsigned long : 8; + unsigned long TSRC : 8; +#endif + } BIT; + } CUOTSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRMV : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long SRMV : 16; +#endif + } BIT; + } SRR; + char wk8[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PPMACRU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PPMACRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } PDMACRU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } PDMACRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TYPE : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long TYPE : 16; +#endif + } BIT; + } PETYPER; + char wk9[12]; + unsigned long PPIPR; + unsigned long PDIPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EVTO : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long EVTO : 8; +#endif + } BIT; + } PETOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GETO : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long GETO : 8; +#endif + } BIT; + } PGTOSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PRTL : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long PRTL : 8; +#endif + } BIT; + } PPTTLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PDTL : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long PDTL : 8; +#endif + } BIT; + } PDTTLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EVUPT : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EVUPT : 16; +#endif + } BIT; + } PEUDPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GEUPT : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long GEUPT : 16; +#endif + } BIT; + } PGUDPR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 1; + unsigned long PRT : 1; + unsigned long ENB : 1; + unsigned long : 13; + unsigned long EXTPRM : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long EXTPRM : 1; + unsigned long : 13; + unsigned long ENB : 1; + unsigned long PRT : 1; + unsigned long SEL : 1; +#endif + } BIT; + } FFLTR; + char wk10[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } FMAC0RU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } FMAC0RL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACU : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACU : 24; +#endif + } BIT; + } FMAC1RU; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MACL : 24; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long MACL : 24; +#endif + } BIT; + } FMAC1RL; + char wk11[80]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ASYMU : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ASYMU : 16; +#endif + } BIT; + } DASYMRU; + unsigned long DASYMRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EGP : 16; + unsigned long INGP : 16; +#else + unsigned long INGP : 16; + unsigned long EGP : 16; +#endif + } BIT; + } TSLATR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCYC : 8; + unsigned long : 4; + unsigned long SBDIS : 1; + unsigned long : 3; + unsigned long FILDIS : 1; + unsigned long : 3; + unsigned long TCMOD : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TCMOD : 1; + unsigned long : 3; + unsigned long FILDIS : 1; + unsigned long : 3; + unsigned long SBDIS : 1; + unsigned long : 4; + unsigned long TCYC : 8; +#endif + } BIT; + } SYCONFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FORM0 : 1; + unsigned long FORM1 : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long FORM1 : 1; + unsigned long FORM0 : 1; +#endif + } BIT; + } SYFORMR; + unsigned long RSTOUTR; +} st_eptpc0_t; + +typedef struct st_etherc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PRM : 1; + unsigned long DM : 1; + unsigned long RTM : 1; + unsigned long ILB : 1; + unsigned long : 1; + unsigned long TE : 1; + unsigned long RE : 1; + unsigned long : 2; + unsigned long MPDE : 1; + unsigned long : 2; + unsigned long PRCEF : 1; + unsigned long : 3; + unsigned long TXF : 1; + unsigned long RXF : 1; + unsigned long PFR : 1; + unsigned long ZPF : 1; + unsigned long TPC : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TPC : 1; + unsigned long ZPF : 1; + unsigned long PFR : 1; + unsigned long RXF : 1; + unsigned long TXF : 1; + unsigned long : 3; + unsigned long PRCEF : 1; + unsigned long : 2; + unsigned long MPDE : 1; + unsigned long : 2; + unsigned long RE : 1; + unsigned long TE : 1; + unsigned long : 1; + unsigned long ILB : 1; + unsigned long RTM : 1; + unsigned long DM : 1; + unsigned long PRM : 1; +#endif + } BIT; + } ECMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFL : 12; + unsigned long : 20; +#else + unsigned long : 20; + unsigned long RFL : 12; +#endif + } BIT; + } RFLR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICD : 1; + unsigned long MPD : 1; + unsigned long LCHNG : 1; + unsigned long : 1; + unsigned long PSRTO : 1; + unsigned long BFR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long BFR : 1; + unsigned long PSRTO : 1; + unsigned long : 1; + unsigned long LCHNG : 1; + unsigned long MPD : 1; + unsigned long ICD : 1; +#endif + } BIT; + } ECSR; + char wk2[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICDIP : 1; + unsigned long MPDIP : 1; + unsigned long LCHNGIP : 1; + unsigned long : 1; + unsigned long PSRTOIP : 1; + unsigned long BFSIPR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long BFSIPR : 1; + unsigned long PSRTOIP : 1; + unsigned long : 1; + unsigned long LCHNGIP : 1; + unsigned long MPDIP : 1; + unsigned long ICDIP : 1; +#endif + } BIT; + } ECSIPR; + char wk3[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDC : 1; + unsigned long MMD : 1; + unsigned long MDO : 1; + unsigned long MDI : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long MDI : 1; + unsigned long MDO : 1; + unsigned long MMD : 1; + unsigned long MDC : 1; +#endif + } BIT; + } PIR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMON : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long LMON : 1; +#endif + } BIT; + } PSR; + char wk5[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RMD : 20; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long RMD : 20; +#endif + } BIT; + } RDMLR; + char wk6[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IPG : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long IPG : 5; +#endif + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AP : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long AP : 16; +#endif + } BIT; + } APR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MP : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MP : 16; +#endif + } BIT; + } MPR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RPAUSE : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RPAUSE : 8; +#endif + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TPAUSE : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long TPAUSE : 16; +#endif + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TXP : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TXP : 8; +#endif + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BCF : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long BCF : 16; +#endif + } BIT; + } BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MA : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MA : 16; +#endif + } BIT; + } MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +} st_etherc_t; + +typedef struct st_exdmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +} st_exdmac_t; + +typedef struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DACKSEL : 1; + unsigned char DACKW : 1; + unsigned char DACKE : 1; + unsigned char DACKS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char DACKS : 1; + unsigned char DACKE : 1; + unsigned char DACKW : 1; + unsigned char DACKSEL : 1; +#endif + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DARA : 5; + unsigned long : 1; + unsigned long DM : 2; + unsigned long SARA : 5; + unsigned long : 1; + unsigned long SM : 2; + unsigned long DIR : 1; + unsigned long AMS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long AMS : 1; + unsigned long DIR : 1; + unsigned long SM : 2; + unsigned long : 1; + unsigned long SARA : 5; + unsigned long DM : 2; + unsigned long : 1; + unsigned long DARA : 5; +#endif + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } EDMSTS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DREQS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DREQS : 2; +#endif + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EREQ : 1; +#endif + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PREQ : 1; +#endif + } BIT; + } EDMPRF; +} st_exdmac0_t; + +typedef struct st_exdmac1 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DACKSEL : 1; + unsigned char DACKW : 1; + unsigned char DACKE : 1; + unsigned char DACKS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char DACKS : 1; + unsigned char DACKE : 1; + unsigned char DACKW : 1; + unsigned char DACKSEL : 1; +#endif + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DARA : 5; + unsigned long : 1; + unsigned long DM : 2; + unsigned long SARA : 5; + unsigned long : 1; + unsigned long SM : 2; + unsigned long DIR : 1; + unsigned long AMS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long AMS : 1; + unsigned long DIR : 1; + unsigned long SM : 2; + unsigned long : 1; + unsigned long SARA : 5; + unsigned long DM : 2; + unsigned long : 1; + unsigned long DARA : 5; +#endif + } BIT; + } EDMAMD; + char wk1[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } EDMSTS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DREQS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DREQS : 2; +#endif + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EREQ : 1; +#endif + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PREQ : 1; +#endif + } BIT; + } EDMPRF; +} st_exdmac1_t; + +typedef struct st_flash { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROMCEN : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ROMCEN : 1; +#endif + } BIT; + } ROMCE; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROMCIV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ROMCIV : 1; +#endif + } BIT; + } ROMCIV; + char wk1[58]; + unsigned long NCRG0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long NC1E : 1; + unsigned long NC2E : 1; + unsigned long NC3E : 1; + unsigned long NCSZ : 17; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long NCSZ : 17; + unsigned long NC3E : 1; + unsigned long NC2E : 1; + unsigned long NC1E : 1; + unsigned long : 1; +#endif + } BIT; + } NCRC0; + unsigned long NCRG1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long NC1E : 1; + unsigned long NC2E : 1; + unsigned long NC3E : 1; + unsigned long NCSZ : 17; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long NCSZ : 17; + unsigned long NC3E : 1; + unsigned long NC2E : 1; + unsigned long NC1E : 1; + unsigned long : 1; +#endif + } BIT; + } NCRC1; + char wk2[45638]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLWE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char FLWE : 2; +#endif + } BIT; + } FWEPROR; + char wk3[7798185]; + unsigned char EEPFCLK; + char wk4[8143]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char DFAE : 1; + unsigned char CMDLK : 1; + unsigned char : 2; + unsigned char CFAE : 1; +#else + unsigned char CFAE : 1; + unsigned char : 2; + unsigned char CMDLK : 1; + unsigned char DFAE : 1; + unsigned char : 3; +#endif + } BIT; + } FASTAT; + char wk5[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char DFAEIE : 1; + unsigned char CMDLKIE : 1; + unsigned char : 2; + unsigned char CFAEIE : 1; +#else + unsigned char CFAEIE : 1; + unsigned char : 2; + unsigned char CMDLKIE : 1; + unsigned char DFAEIE : 1; + unsigned char : 3; +#endif + } BIT; + } FAEINT; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRDYIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRDYIE : 1; +#endif + } BIT; + } FRDYIE; + char wk7[23]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FSADDR : 32; +#else + unsigned long FSADDR : 32; +#endif + } BIT; + } FSADDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FEADDR : 32; +#else + unsigned long FEADDR : 32; +#endif + } BIT; + } FEADDR; + char wk8[72]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long FLWEERR : 1; + unsigned long : 1; + unsigned long PRGSPD : 1; + unsigned long ERSSPD : 1; + unsigned long DBFULL : 1; + unsigned long SUSRDY : 1; + unsigned long PRGERR : 1; + unsigned long ERSERR : 1; + unsigned long ILGLERR : 1; + unsigned long FRDY : 1; + unsigned long : 4; + unsigned long OTERR : 1; + unsigned long SECERR : 1; + unsigned long FESETERR : 1; + unsigned long ILGCOMERR : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ILGCOMERR : 1; + unsigned long FESETERR : 1; + unsigned long SECERR : 1; + unsigned long OTERR : 1; + unsigned long : 4; + unsigned long FRDY : 1; + unsigned long ILGLERR : 1; + unsigned long ERSERR : 1; + unsigned long PRGERR : 1; + unsigned long SUSRDY : 1; + unsigned long DBFULL : 1; + unsigned long ERSSPD : 1; + unsigned long PRGSPD : 1; + unsigned long : 1; + unsigned long FLWEERR : 1; + unsigned long : 6; +#endif + } BIT; + } FSTATR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRYC : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRYC : 1; +#endif + } BIT; + } FENTRYR; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SUINIT : 1; + unsigned short : 7; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 7; + unsigned short SUINIT : 1; +#endif + } BIT; + } FSUINITR; + char wk10[18]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCMDR : 8; + unsigned short CMDR : 8; +#else + unsigned short CMDR : 8; + unsigned short PCMDR : 8; +#endif + } BIT; + } FCMDR; + char wk11[46]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCDIR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCDIR : 1; +#endif + } BIT; + } FBCCNT; + char wk12[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCST : 1; +#endif + } BIT; + } FBCSTAT; + char wk13[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSADR : 17; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long PSADR : 17; +#endif + } BIT; + } FPSADDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FAWS : 12; + unsigned long : 3; + unsigned long FSPR : 1; + unsigned long FAWE : 12; + unsigned long : 3; + unsigned long BTFLG : 1; +#else + unsigned long BTFLG : 1; + unsigned long : 3; + unsigned long FAWE : 12; + unsigned long FSPR : 1; + unsigned long : 3; + unsigned long FAWS : 12; +#endif + } BIT; + } FAWMON; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ESUSPMD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ESUSPMD : 1; +#endif + } BIT; + } FCPSR; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCKA : 8; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short PCKA : 8; +#endif + } BIT; + } FPCKAR; + char wk15[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SAS : 2; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short SAS : 2; +#endif + } BIT; + } FSUACR; +} st_flash_t; + +typedef struct st_glcdc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif + } BIT; + } GR1CLUT0[256]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif + } BIT; + } GR1CLUT1[256]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif + } BIT; + } GR2CLUT0[256]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif + } BIT; + } GR2CLUT1[256]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long SWRST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SWRST : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long EN : 1; +#endif + } BIT; + } BGEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FH : 11; + unsigned long : 5; + unsigned long FV : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long FV : 11; + unsigned long : 5; + unsigned long FH : 11; +#endif + } BIT; + } BGPERI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HP : 4; + unsigned long : 12; + unsigned long VP : 4; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long VP : 4; + unsigned long : 12; + unsigned long HP : 4; +#endif + } BIT; + } BGSYNC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VW : 11; + unsigned long : 5; + unsigned long VP : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long VP : 11; + unsigned long : 5; + unsigned long VW : 11; +#endif + } BIT; + } BGVSIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HW : 11; + unsigned long : 5; + unsigned long HP : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HP : 11; + unsigned long : 5; + unsigned long HW : 11; +#endif + } BIT; + } BGHSIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif + } BIT; + } BGCOLOR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long SWRST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SWRST : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long EN : 1; +#endif + } BIT; + } BGMON; + char wk0[228]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif + } BIT; + } GR1VEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RENB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RENB : 1; +#endif + } BIT; + } GR1FLMRD; + char wk1[4]; + unsigned long GR1FLM2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long LNOFF : 16; +#else + unsigned long LNOFF : 16; + unsigned long : 16; +#endif + } BIT; + } GR1FLM3; + char wk2[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DATANUM : 16; + unsigned long LNNUM : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long LNNUM : 11; + unsigned long DATANUM : 16; +#endif + } BIT; + } GR1FLM5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 28; + unsigned long FORMAT : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long FORMAT : 3; + unsigned long : 28; +#endif + } BIT; + } GR1FLM6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DISPSEL : 2; + unsigned long : 2; + unsigned long GRCDISPON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long ARCON : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long ARCON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long GRCDISPON : 1; + unsigned long : 2; + unsigned long DISPSEL : 2; +#endif + } BIT; + } GR1AB1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCVW : 11; + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; + unsigned long GRCVW : 11; +#endif + } BIT; + } GR1AB2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCHW : 11; + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; + unsigned long GRCHW : 11; +#endif + } BIT; + } GR1AB3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCVW : 11; + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; + unsigned long ARCVW : 11; +#endif + } BIT; + } GR1AB4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCHW : 11; + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; + unsigned long ARCHW : 11; +#endif + } BIT; + } GR1AB5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCRATE : 8; + unsigned long : 8; + unsigned long ARCCOEF : 9; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ARCCOEF : 9; + unsigned long : 8; + unsigned long ARCRATE : 8; +#endif + } BIT; + } GR1AB6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKON : 1; + unsigned long : 15; + unsigned long ARCDEF : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ARCDEF : 8; + unsigned long : 15; + unsigned long CKON : 1; +#endif + } BIT; + } GR1AB7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKKR : 8; + unsigned long CKKB : 8; + unsigned long CKKG : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long CKKG : 8; + unsigned long CKKB : 8; + unsigned long CKKR : 8; +#endif + } BIT; + } GR1AB8; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKR : 8; + unsigned long CKB : 8; + unsigned long CKG : 8; + unsigned long CKA : 8; +#else + unsigned long CKA : 8; + unsigned long CKG : 8; + unsigned long CKB : 8; + unsigned long CKR : 8; +#endif + } BIT; + } GR1AB9; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long R : 8; + unsigned long B : 8; + unsigned long G : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long G : 8; + unsigned long B : 8; + unsigned long R : 8; +#endif + } BIT; + } GR1BASE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LINE : 11; + unsigned long : 5; + unsigned long SEL : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SEL : 1; + unsigned long : 5; + unsigned long LINE : 11; +#endif + } BIT; + } GR1CLUTINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCST : 1; + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; + unsigned long ARCST : 1; +#endif + } BIT; + } GR1MON; + char wk4[168]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif + } BIT; + } GR2VEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RENB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RENB : 1; +#endif + } BIT; + } GR2FLMRD; + char wk5[4]; + unsigned long GR2FLM2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long LNOFF : 16; +#else + unsigned long LNOFF : 16; + unsigned long : 16; +#endif + } BIT; + } GR2FLM3; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DATANUM : 16; + unsigned long LNNUM : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long LNNUM : 11; + unsigned long DATANUM : 16; +#endif + } BIT; + } GR2FLM5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 28; + unsigned long FORMAT : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long FORMAT : 3; + unsigned long : 28; +#endif + } BIT; + } GR2FLM6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DISPSEL : 2; + unsigned long : 2; + unsigned long GRCDISPON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long ARCON : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long ARCON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long GRCDISPON : 1; + unsigned long : 2; + unsigned long DISPSEL : 2; +#endif + } BIT; + } GR2AB1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCVW : 11; + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; + unsigned long GRCVW : 11; +#endif + } BIT; + } GR2AB2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCHW : 11; + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; + unsigned long GRCHW : 11; +#endif + } BIT; + } GR2AB3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCVW : 11; + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; + unsigned long ARCVW : 11; +#endif + } BIT; + } GR2AB4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCHW : 11; + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; + unsigned long ARCHW : 11; +#endif + } BIT; + } GR2AB5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCRATE : 8; + unsigned long : 8; + unsigned long ARCCOEF : 9; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ARCCOEF : 9; + unsigned long : 8; + unsigned long ARCRATE : 8; +#endif + } BIT; + } GR2AB6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKON : 1; + unsigned long : 15; + unsigned long ARCDEF : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ARCDEF : 8; + unsigned long : 15; + unsigned long CKON : 1; +#endif + } BIT; + } GR2AB7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKKR : 8; + unsigned long CKKB : 8; + unsigned long CKKG : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long CKKG : 8; + unsigned long CKKB : 8; + unsigned long CKKR : 8; +#endif + } BIT; + } GR2AB8; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKR : 8; + unsigned long CKB : 8; + unsigned long CKG : 8; + unsigned long CKA : 8; +#else + unsigned long CKA : 8; + unsigned long CKG : 8; + unsigned long CKB : 8; + unsigned long CKR : 8; +#endif + } BIT; + } GR2AB9; + char wk7[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long R : 8; + unsigned long B : 8; + unsigned long G : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long G : 8; + unsigned long B : 8; + unsigned long R : 8; +#endif + } BIT; + } GR2BASE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LINE : 11; + unsigned long : 5; + unsigned long SEL : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SEL : 1; + unsigned long : 5; + unsigned long LINE : 11; +#endif + } BIT; + } GR2CLUTINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCST : 1; + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; + unsigned long ARCST : 1; +#endif + } BIT; + } GR2MON; + char wk8[168]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif + } BIT; + } GAMGVEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAMON : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long GAMON : 1; +#endif + } BIT; + } GAMSW; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN01 : 11; + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; + unsigned long GAIN01 : 11; +#endif + } BIT; + } GAMGLUT1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN03 : 11; + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; + unsigned long GAIN03 : 11; +#endif + } BIT; + } GAMGLUT2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN05 : 11; + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; + unsigned long GAIN05 : 11; +#endif + } BIT; + } GAMGLUT3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN07 : 11; + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; + unsigned long GAIN07 : 11; +#endif + } BIT; + } GAMGLUT4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN09 : 11; + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; + unsigned long GAIN09 : 11; +#endif + } BIT; + } GAMGLUT5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN11 : 11; + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; + unsigned long GAIN11 : 11; +#endif + } BIT; + } GAMGLUT6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN13 : 11; + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; + unsigned long GAIN13 : 11; +#endif + } BIT; + } GAMGLUT7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN15 : 11; + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; + unsigned long GAIN15 : 11; +#endif + } BIT; + } GAMGLUT8; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH03 : 10; + unsigned long TH02 : 10; + unsigned long TH01 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH01 : 10; + unsigned long TH02 : 10; + unsigned long TH03 : 10; +#endif + } BIT; + } GAMGAREA1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH06 : 10; + unsigned long TH05 : 10; + unsigned long TH04 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH04 : 10; + unsigned long TH05 : 10; + unsigned long TH06 : 10; +#endif + } BIT; + } GAMGAREA2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH09 : 10; + unsigned long TH08 : 10; + unsigned long TH07 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH07 : 10; + unsigned long TH08 : 10; + unsigned long TH09 : 10; +#endif + } BIT; + } GAMGAREA3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH12 : 10; + unsigned long TH11 : 10; + unsigned long TH10 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH10 : 10; + unsigned long TH11 : 10; + unsigned long TH12 : 10; +#endif + } BIT; + } GAMGAREA4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH15 : 10; + unsigned long TH14 : 10; + unsigned long TH13 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH13 : 10; + unsigned long TH14 : 10; + unsigned long TH15 : 10; +#endif + } BIT; + } GAMGAREA5; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif + } BIT; + } GAMBVEN; + char wk10[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN01 : 11; + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; + unsigned long GAIN01 : 11; +#endif + } BIT; + } GAMBLUT1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN03 : 11; + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; + unsigned long GAIN03 : 11; +#endif + } BIT; + } GAMBLUT2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN05 : 11; + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; + unsigned long GAIN05 : 11; +#endif + } BIT; + } GAMBLUT3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN07 : 11; + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; + unsigned long GAIN07 : 11; +#endif + } BIT; + } GAMBLUT4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN09 : 11; + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; + unsigned long GAIN09 : 11; +#endif + } BIT; + } GAMBLUT5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN11 : 11; + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; + unsigned long GAIN11 : 11; +#endif + } BIT; + } GAMBLUT6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN13 : 11; + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; + unsigned long GAIN13 : 11; +#endif + } BIT; + } GAMBLUT7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN15 : 11; + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; + unsigned long GAIN15 : 11; +#endif + } BIT; + } GAMBLUT8; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH03 : 10; + unsigned long TH02 : 10; + unsigned long TH01 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH01 : 10; + unsigned long TH02 : 10; + unsigned long TH03 : 10; +#endif + } BIT; + } GAMBAREA1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH06 : 10; + unsigned long TH05 : 10; + unsigned long TH04 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH04 : 10; + unsigned long TH05 : 10; + unsigned long TH06 : 10; +#endif + } BIT; + } GAMBAREA2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH09 : 10; + unsigned long TH08 : 10; + unsigned long TH07 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH07 : 10; + unsigned long TH08 : 10; + unsigned long TH09 : 10; +#endif + } BIT; + } GAMBAREA3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH12 : 10; + unsigned long TH11 : 10; + unsigned long TH10 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH10 : 10; + unsigned long TH11 : 10; + unsigned long TH12 : 10; +#endif + } BIT; + } GAMBAREA4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH15 : 10; + unsigned long TH14 : 10; + unsigned long TH13 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH13 : 10; + unsigned long TH14 : 10; + unsigned long TH15 : 10; +#endif + } BIT; + } GAMBAREA5; + char wk11[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif + } BIT; + } GAMRVEN; + char wk12[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN01 : 11; + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; + unsigned long GAIN01 : 11; +#endif + } BIT; + } GAMRLUT1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN03 : 11; + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; + unsigned long GAIN03 : 11; +#endif + } BIT; + } GAMRLUT2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN05 : 11; + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; + unsigned long GAIN05 : 11; +#endif + } BIT; + } GAMRLUT3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN07 : 11; + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; + unsigned long GAIN07 : 11; +#endif + } BIT; + } GAMRLUT4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN09 : 11; + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; + unsigned long GAIN09 : 11; +#endif + } BIT; + } GAMRLUT5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN11 : 11; + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; + unsigned long GAIN11 : 11; +#endif + } BIT; + } GAMRLUT6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN13 : 11; + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; + unsigned long GAIN13 : 11; +#endif + } BIT; + } GAMRLUT7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN15 : 11; + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; + unsigned long GAIN15 : 11; +#endif + } BIT; + } GAMRLUT8; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH03 : 10; + unsigned long TH02 : 10; + unsigned long TH01 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH01 : 10; + unsigned long TH02 : 10; + unsigned long TH03 : 10; +#endif + } BIT; + } GAMRAREA1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH06 : 10; + unsigned long TH05 : 10; + unsigned long TH04 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH04 : 10; + unsigned long TH05 : 10; + unsigned long TH06 : 10; +#endif + } BIT; + } GAMRAREA2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH09 : 10; + unsigned long TH08 : 10; + unsigned long TH07 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH07 : 10; + unsigned long TH08 : 10; + unsigned long TH09 : 10; +#endif + } BIT; + } GAMRAREA3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH12 : 10; + unsigned long TH11 : 10; + unsigned long TH10 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH10 : 10; + unsigned long TH11 : 10; + unsigned long TH12 : 10; +#endif + } BIT; + } GAMRAREA4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH15 : 10; + unsigned long TH14 : 10; + unsigned long TH13 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH13 : 10; + unsigned long TH14 : 10; + unsigned long TH15 : 10; +#endif + } BIT; + } GAMRAREA5; + char wk13[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif + } BIT; + } OUTVEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PHASE : 2; + unsigned long : 2; + unsigned long DIRSEL : 1; + unsigned long : 4; + unsigned long FRQSEL : 1; + unsigned long : 2; + unsigned long FORMAT : 2; + unsigned long : 10; + unsigned long SWAPON : 1; + unsigned long : 3; + unsigned long ENDIANON : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long ENDIANON : 1; + unsigned long : 3; + unsigned long SWAPON : 1; + unsigned long : 10; + unsigned long FORMAT : 2; + unsigned long : 2; + unsigned long FRQSEL : 1; + unsigned long : 4; + unsigned long DIRSEL : 1; + unsigned long : 2; + unsigned long PHASE : 2; +#endif + } BIT; + } OUTSET; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BRTG : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long BRTG : 10; +#endif + } BIT; + } BRIGHT1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BRTR : 10; + unsigned long : 6; + unsigned long BRTB : 10; + unsigned long : 6; +#else + unsigned long : 6; + unsigned long BRTB : 10; + unsigned long : 6; + unsigned long BRTR : 10; +#endif + } BIT; + } BRIGHT2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CONTR : 8; + unsigned long CONTB : 8; + unsigned long CONTG : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long CONTG : 8; + unsigned long CONTB : 8; + unsigned long CONTR : 8; +#endif + } BIT; + } CONTRAST; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PD : 2; + unsigned long : 2; + unsigned long PC : 2; + unsigned long : 2; + unsigned long PB : 2; + unsigned long : 2; + unsigned long PA : 2; + unsigned long : 2; + unsigned long FORM : 2; + unsigned long : 2; + unsigned long SEL : 2; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long SEL : 2; + unsigned long : 2; + unsigned long FORM : 2; + unsigned long : 2; + unsigned long PA : 2; + unsigned long : 2; + unsigned long PB : 2; + unsigned long : 2; + unsigned long PC : 2; + unsigned long : 2; + unsigned long PD : 2; +#endif + } BIT; + } PANELDTHA; + char wk14[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long TCON3EDG : 1; + unsigned long TCON2EDG : 1; + unsigned long TCON1EDG : 1; + unsigned long TCON0EDG : 1; + unsigned long : 1; + unsigned long LCDEDG : 1; + unsigned long : 3; + unsigned long FRONTGAM : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long FRONTGAM : 1; + unsigned long : 3; + unsigned long LCDEDG : 1; + unsigned long : 1; + unsigned long TCON0EDG : 1; + unsigned long TCON1EDG : 1; + unsigned long TCON2EDG : 1; + unsigned long TCON3EDG : 1; + unsigned long : 3; +#endif + } BIT; + } CLKPHASE; + char wk15[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OFFSET : 11; + unsigned long : 5; + unsigned long HALF : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HALF : 11; + unsigned long : 5; + unsigned long OFFSET : 11; +#endif + } BIT; + } TCONTIM; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VW : 11; + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; + unsigned long VW : 11; +#endif + } BIT; + } TCONSTVA1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif + } BIT; + } TCONSTVA2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VW : 11; + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; + unsigned long VW : 11; +#endif + } BIT; + } TCONSTVB1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif + } BIT; + } TCONSTVB2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HW : 11; + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; + unsigned long HW : 11; +#endif + } BIT; + } TCONSTHA1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 3; + unsigned long HSSEL : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long HSSEL : 1; + unsigned long : 3; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif + } BIT; + } TCONSTHA2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HW : 11; + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; + unsigned long HW : 11; +#endif + } BIT; + } TCONSTHB1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 3; + unsigned long HSSEL : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long HSSEL : 1; + unsigned long : 3; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif + } BIT; + } TCONSTHB2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INV : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long INV : 1; +#endif + } BIT; + } TCONDE; + char wk16[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOSDTC : 1; + unsigned long GR1UFDTC : 1; + unsigned long GR2UFDTC : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UFDTC : 1; + unsigned long GR1UFDTC : 1; + unsigned long VPOSDTC : 1; +#endif + } BIT; + } DTCTEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOSINTEN : 1; + unsigned long GR1UFINTEN : 1; + unsigned long GR2UFINTEN : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UFINTEN : 1; + unsigned long GR1UFINTEN : 1; + unsigned long VPOSINTEN : 1; +#endif + } BIT; + } INTEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOSCLR : 1; + unsigned long GR1UFCLR : 1; + unsigned long GR2UFCLR : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UFCLR : 1; + unsigned long GR1UFCLR : 1; + unsigned long VPOSCLR : 1; +#endif + } BIT; + } STCLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOS : 1; + unsigned long GR1UF : 1; + unsigned long GR2UF : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UF : 1; + unsigned long GR1UF : 1; + unsigned long VPOS : 1; +#endif + } BIT; + } STMON; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DCDR : 6; + unsigned long CLKEN : 1; + unsigned long : 1; + unsigned long CLKSEL : 1; + unsigned long : 3; + unsigned long PIXSEL : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long PIXSEL : 1; + unsigned long : 3; + unsigned long CLKSEL : 1; + unsigned long : 1; + unsigned long CLKEN : 1; + unsigned long DCDR : 6; +#endif + } BIT; + } PANELCLK; +} st_glcdc_t; + +typedef struct st_gptw { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WP : 1; + unsigned long STRWP : 1; + unsigned long STPWP : 1; + unsigned long CLRWP : 1; + unsigned long CMNWP : 1; + unsigned long : 3; + unsigned long PRKEY : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PRKEY : 8; + unsigned long : 3; + unsigned long CMNWP : 1; + unsigned long CLRWP : 1; + unsigned long STPWP : 1; + unsigned long STRWP : 1; + unsigned long WP : 1; +#endif + } BIT; + } GTWP; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSTRT0 : 1; + unsigned long CSTRT1 : 1; + unsigned long CSTRT2 : 1; + unsigned long CSTRT3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CSTRT3 : 1; + unsigned long CSTRT2 : 1; + unsigned long CSTRT1 : 1; + unsigned long CSTRT0 : 1; +#endif + } BIT; + } GTSTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSTOP0 : 1; + unsigned long CSTOP1 : 1; + unsigned long CSTOP2 : 1; + unsigned long CSTOP3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CSTOP3 : 1; + unsigned long CSTOP2 : 1; + unsigned long CSTOP1 : 1; + unsigned long CSTOP0 : 1; +#endif + } BIT; + } GTSTP; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCLR0 : 1; + unsigned long CCLR1 : 1; + unsigned long CCLR2 : 1; + unsigned long CCLR3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CCLR3 : 1; + unsigned long CCLR2 : 1; + unsigned long CCLR1 : 1; + unsigned long CCLR0 : 1; +#endif + } BIT; + } GTCLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SSGTRGAR : 1; + unsigned long SSGTRGAF : 1; + unsigned long SSGTRGBR : 1; + unsigned long SSGTRGBF : 1; + unsigned long SSGTRGCR : 1; + unsigned long SSGTRGCF : 1; + unsigned long SSGTRGDR : 1; + unsigned long SSGTRGDF : 1; + unsigned long SSCARBL : 1; + unsigned long SSCARBH : 1; + unsigned long SSCAFBL : 1; + unsigned long SSCAFBH : 1; + unsigned long SSCBRAL : 1; + unsigned long SSCBRAH : 1; + unsigned long SSCBFAL : 1; + unsigned long SSCBFAH : 1; + unsigned long SSELCA : 1; + unsigned long SSELCB : 1; + unsigned long SSELCC : 1; + unsigned long SSELCD : 1; + unsigned long SSELCE : 1; + unsigned long SSELCF : 1; + unsigned long SSELCG : 1; + unsigned long SSELCH : 1; + unsigned long : 7; + unsigned long CSTRT : 1; +#else + unsigned long CSTRT : 1; + unsigned long : 7; + unsigned long SSELCH : 1; + unsigned long SSELCG : 1; + unsigned long SSELCF : 1; + unsigned long SSELCE : 1; + unsigned long SSELCD : 1; + unsigned long SSELCC : 1; + unsigned long SSELCB : 1; + unsigned long SSELCA : 1; + unsigned long SSCBFAH : 1; + unsigned long SSCBFAL : 1; + unsigned long SSCBRAH : 1; + unsigned long SSCBRAL : 1; + unsigned long SSCAFBH : 1; + unsigned long SSCAFBL : 1; + unsigned long SSCARBH : 1; + unsigned long SSCARBL : 1; + unsigned long SSGTRGDF : 1; + unsigned long SSGTRGDR : 1; + unsigned long SSGTRGCF : 1; + unsigned long SSGTRGCR : 1; + unsigned long SSGTRGBF : 1; + unsigned long SSGTRGBR : 1; + unsigned long SSGTRGAF : 1; + unsigned long SSGTRGAR : 1; +#endif + } BIT; + } GTSSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSGTRGAR : 1; + unsigned long PSGTRGAF : 1; + unsigned long PSGTRGBR : 1; + unsigned long PSGTRGBF : 1; + unsigned long PSGTRGCR : 1; + unsigned long PSGTRGCF : 1; + unsigned long PSGTRGDR : 1; + unsigned long PSGTRGDF : 1; + unsigned long PSCARBL : 1; + unsigned long PSCARBH : 1; + unsigned long PSCAFBL : 1; + unsigned long PSCAFBH : 1; + unsigned long PSCBRAL : 1; + unsigned long PSCBRAH : 1; + unsigned long PSCBFAL : 1; + unsigned long PSCBFAH : 1; + unsigned long PSELCA : 1; + unsigned long PSELCB : 1; + unsigned long PSELCC : 1; + unsigned long PSELCD : 1; + unsigned long PSELCE : 1; + unsigned long PSELCF : 1; + unsigned long PSELCG : 1; + unsigned long PSELCH : 1; + unsigned long : 7; + unsigned long CSTOP : 1; +#else + unsigned long CSTOP : 1; + unsigned long : 7; + unsigned long PSELCH : 1; + unsigned long PSELCG : 1; + unsigned long PSELCF : 1; + unsigned long PSELCE : 1; + unsigned long PSELCD : 1; + unsigned long PSELCC : 1; + unsigned long PSELCB : 1; + unsigned long PSELCA : 1; + unsigned long PSCBFAH : 1; + unsigned long PSCBFAL : 1; + unsigned long PSCBRAH : 1; + unsigned long PSCBRAL : 1; + unsigned long PSCAFBH : 1; + unsigned long PSCAFBL : 1; + unsigned long PSCARBH : 1; + unsigned long PSCARBL : 1; + unsigned long PSGTRGDF : 1; + unsigned long PSGTRGDR : 1; + unsigned long PSGTRGCF : 1; + unsigned long PSGTRGCR : 1; + unsigned long PSGTRGBF : 1; + unsigned long PSGTRGBR : 1; + unsigned long PSGTRGAF : 1; + unsigned long PSGTRGAR : 1; +#endif + } BIT; + } GTPSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSGTRGAR : 1; + unsigned long CSGTRGAF : 1; + unsigned long CSGTRGBR : 1; + unsigned long CSGTRGBF : 1; + unsigned long CSGTRGCR : 1; + unsigned long CSGTRGCF : 1; + unsigned long CSGTRGDR : 1; + unsigned long CSGTRGDF : 1; + unsigned long CSCARBL : 1; + unsigned long CSCARBH : 1; + unsigned long CSCAFBL : 1; + unsigned long CSCAFBH : 1; + unsigned long CSCBRAL : 1; + unsigned long CSCBRAH : 1; + unsigned long CSCBFAL : 1; + unsigned long CSCBFAH : 1; + unsigned long CSELCA : 1; + unsigned long CSELCB : 1; + unsigned long CSELCC : 1; + unsigned long CSELCD : 1; + unsigned long CSELCE : 1; + unsigned long CSELCF : 1; + unsigned long CSELCG : 1; + unsigned long CSELCH : 1; + unsigned long : 7; + unsigned long CCLR : 1; +#else + unsigned long CCLR : 1; + unsigned long : 7; + unsigned long CSELCH : 1; + unsigned long CSELCG : 1; + unsigned long CSELCF : 1; + unsigned long CSELCE : 1; + unsigned long CSELCD : 1; + unsigned long CSELCC : 1; + unsigned long CSELCB : 1; + unsigned long CSELCA : 1; + unsigned long CSCBFAH : 1; + unsigned long CSCBFAL : 1; + unsigned long CSCBRAH : 1; + unsigned long CSCBRAL : 1; + unsigned long CSCAFBH : 1; + unsigned long CSCAFBL : 1; + unsigned long CSCARBH : 1; + unsigned long CSCARBL : 1; + unsigned long CSGTRGDF : 1; + unsigned long CSGTRGDR : 1; + unsigned long CSGTRGCF : 1; + unsigned long CSGTRGCR : 1; + unsigned long CSGTRGBF : 1; + unsigned long CSGTRGBR : 1; + unsigned long CSGTRGAF : 1; + unsigned long CSGTRGAR : 1; +#endif + } BIT; + } GTCSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long USGTRGAR : 1; + unsigned long USGTRGAF : 1; + unsigned long USGTRGBR : 1; + unsigned long USGTRGBF : 1; + unsigned long USGTRGCR : 1; + unsigned long USGTRGCF : 1; + unsigned long USGTRGDR : 1; + unsigned long USGTRGDF : 1; + unsigned long USCARBL : 1; + unsigned long USCARBH : 1; + unsigned long USCAFBL : 1; + unsigned long USCAFBH : 1; + unsigned long USCBRAL : 1; + unsigned long USCBRAH : 1; + unsigned long USCBFAL : 1; + unsigned long USCBFAH : 1; + unsigned long USELCA : 1; + unsigned long USELCB : 1; + unsigned long USELCC : 1; + unsigned long USELCD : 1; + unsigned long USELCE : 1; + unsigned long USELCF : 1; + unsigned long USELCG : 1; + unsigned long USELCH : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long USELCH : 1; + unsigned long USELCG : 1; + unsigned long USELCF : 1; + unsigned long USELCE : 1; + unsigned long USELCD : 1; + unsigned long USELCC : 1; + unsigned long USELCB : 1; + unsigned long USELCA : 1; + unsigned long USCBFAH : 1; + unsigned long USCBFAL : 1; + unsigned long USCBRAH : 1; + unsigned long USCBRAL : 1; + unsigned long USCAFBH : 1; + unsigned long USCAFBL : 1; + unsigned long USCARBH : 1; + unsigned long USCARBL : 1; + unsigned long USGTRGDF : 1; + unsigned long USGTRGDR : 1; + unsigned long USGTRGCF : 1; + unsigned long USGTRGCR : 1; + unsigned long USGTRGBF : 1; + unsigned long USGTRGBR : 1; + unsigned long USGTRGAF : 1; + unsigned long USGTRGAR : 1; +#endif + } BIT; + } GTUPSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DSGTRGAR : 1; + unsigned long DSGTRGAF : 1; + unsigned long DSGTRGBR : 1; + unsigned long DSGTRGBF : 1; + unsigned long DSGTRGCR : 1; + unsigned long DSGTRGCF : 1; + unsigned long DSGTRGDR : 1; + unsigned long DSGTRGDF : 1; + unsigned long DSCARBL : 1; + unsigned long DSCARBH : 1; + unsigned long DSCAFBL : 1; + unsigned long DSCAFBH : 1; + unsigned long DSCBRAL : 1; + unsigned long DSCBRAH : 1; + unsigned long DSCBFAL : 1; + unsigned long DSCBFAH : 1; + unsigned long DSELCA : 1; + unsigned long DSELCB : 1; + unsigned long DSELCC : 1; + unsigned long DSELCD : 1; + unsigned long DSELCE : 1; + unsigned long DSELCF : 1; + unsigned long DSELCG : 1; + unsigned long DSELCH : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DSELCH : 1; + unsigned long DSELCG : 1; + unsigned long DSELCF : 1; + unsigned long DSELCE : 1; + unsigned long DSELCD : 1; + unsigned long DSELCC : 1; + unsigned long DSELCB : 1; + unsigned long DSELCA : 1; + unsigned long DSCBFAH : 1; + unsigned long DSCBFAL : 1; + unsigned long DSCBRAH : 1; + unsigned long DSCBRAL : 1; + unsigned long DSCAFBH : 1; + unsigned long DSCAFBL : 1; + unsigned long DSCARBH : 1; + unsigned long DSCARBL : 1; + unsigned long DSGTRGDF : 1; + unsigned long DSGTRGDR : 1; + unsigned long DSGTRGCF : 1; + unsigned long DSGTRGCR : 1; + unsigned long DSGTRGBF : 1; + unsigned long DSGTRGBR : 1; + unsigned long DSGTRGAF : 1; + unsigned long DSGTRGAR : 1; +#endif + } BIT; + } GTDNSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ASGTRGAR : 1; + unsigned long ASGTRGAF : 1; + unsigned long ASGTRGBR : 1; + unsigned long ASGTRGBF : 1; + unsigned long ASGTRGCR : 1; + unsigned long ASGTRGCF : 1; + unsigned long ASGTRGDR : 1; + unsigned long ASGTRGDF : 1; + unsigned long ASCARBL : 1; + unsigned long ASCARBH : 1; + unsigned long ASCAFBL : 1; + unsigned long ASCAFBH : 1; + unsigned long ASCBRAL : 1; + unsigned long ASCBRAH : 1; + unsigned long ASCBFAL : 1; + unsigned long ASCBFAH : 1; + unsigned long ASELCA : 1; + unsigned long ASELCB : 1; + unsigned long ASELCC : 1; + unsigned long ASELCD : 1; + unsigned long ASELCE : 1; + unsigned long ASELCF : 1; + unsigned long ASELCG : 1; + unsigned long ASELCH : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ASELCH : 1; + unsigned long ASELCG : 1; + unsigned long ASELCF : 1; + unsigned long ASELCE : 1; + unsigned long ASELCD : 1; + unsigned long ASELCC : 1; + unsigned long ASELCB : 1; + unsigned long ASELCA : 1; + unsigned long ASCBFAH : 1; + unsigned long ASCBFAL : 1; + unsigned long ASCBRAH : 1; + unsigned long ASCBRAL : 1; + unsigned long ASCAFBH : 1; + unsigned long ASCAFBL : 1; + unsigned long ASCARBH : 1; + unsigned long ASCARBL : 1; + unsigned long ASGTRGDF : 1; + unsigned long ASGTRGDR : 1; + unsigned long ASGTRGCF : 1; + unsigned long ASGTRGCR : 1; + unsigned long ASGTRGBF : 1; + unsigned long ASGTRGBR : 1; + unsigned long ASGTRGAF : 1; + unsigned long ASGTRGAR : 1; +#endif + } BIT; + } GTICASR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BSGTRGAR : 1; + unsigned long BSGTRGAF : 1; + unsigned long BSGTRGBR : 1; + unsigned long BSGTRGBF : 1; + unsigned long BSGTRGCR : 1; + unsigned long BSGTRGCF : 1; + unsigned long BSGTRGDR : 1; + unsigned long BSGTRGDF : 1; + unsigned long BSCARBL : 1; + unsigned long BSCARBH : 1; + unsigned long BSCAFBL : 1; + unsigned long BSCAFBH : 1; + unsigned long BSCBRAL : 1; + unsigned long BSCBRAH : 1; + unsigned long BSCBFAL : 1; + unsigned long BSCBFAH : 1; + unsigned long BSELCA : 1; + unsigned long BSELCB : 1; + unsigned long BSELCC : 1; + unsigned long BSELCD : 1; + unsigned long BSELCE : 1; + unsigned long BSELCF : 1; + unsigned long BSELCG : 1; + unsigned long BSELCH : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long BSELCH : 1; + unsigned long BSELCG : 1; + unsigned long BSELCF : 1; + unsigned long BSELCE : 1; + unsigned long BSELCD : 1; + unsigned long BSELCC : 1; + unsigned long BSELCB : 1; + unsigned long BSELCA : 1; + unsigned long BSCBFAH : 1; + unsigned long BSCBFAL : 1; + unsigned long BSCBRAH : 1; + unsigned long BSCBRAL : 1; + unsigned long BSCAFBH : 1; + unsigned long BSCAFBL : 1; + unsigned long BSCARBH : 1; + unsigned long BSCARBL : 1; + unsigned long BSGTRGDF : 1; + unsigned long BSGTRGDR : 1; + unsigned long BSGTRGCF : 1; + unsigned long BSGTRGCR : 1; + unsigned long BSGTRGBF : 1; + unsigned long BSGTRGBR : 1; + unsigned long BSGTRGAF : 1; + unsigned long BSGTRGAR : 1; +#endif + } BIT; + } GTICBSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CST : 1; + unsigned long : 7; + unsigned long ICDS : 1; + unsigned long : 7; + unsigned long MD : 3; + unsigned long : 4; + unsigned long TPCS : 4; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long TPCS : 4; + unsigned long : 4; + unsigned long MD : 3; + unsigned long : 7; + unsigned long ICDS : 1; + unsigned long : 7; + unsigned long CST : 1; +#endif + } BIT; + } GTCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UD : 1; + unsigned long UDF : 1; + unsigned long : 14; + unsigned long OADTY : 2; + unsigned long OADTYF : 1; + unsigned long OADTYR : 1; + unsigned long : 4; + unsigned long OBDTY : 2; + unsigned long OBDTYF : 1; + unsigned long OBDTYR : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long OBDTYR : 1; + unsigned long OBDTYF : 1; + unsigned long OBDTY : 2; + unsigned long : 4; + unsigned long OADTYR : 1; + unsigned long OADTYF : 1; + unsigned long OADTY : 2; + unsigned long : 14; + unsigned long UDF : 1; + unsigned long UD : 1; +#endif + } BIT; + } GTUDDTYC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GTIOA : 5; + unsigned long : 1; + unsigned long OADFLT : 1; + unsigned long OAHLD : 1; + unsigned long OAE : 1; + unsigned long OADF : 2; + unsigned long : 2; + unsigned long NFAEN : 1; + unsigned long NFCSA : 2; + unsigned long GTIOB : 5; + unsigned long : 1; + unsigned long OBDFLT : 1; + unsigned long OBHLD : 1; + unsigned long OBE : 1; + unsigned long OBDF : 2; + unsigned long : 2; + unsigned long NFBEN : 1; + unsigned long NFCSB : 2; +#else + unsigned long NFCSB : 2; + unsigned long NFBEN : 1; + unsigned long : 2; + unsigned long OBDF : 2; + unsigned long OBE : 1; + unsigned long OBHLD : 1; + unsigned long OBDFLT : 1; + unsigned long : 1; + unsigned long GTIOB : 5; + unsigned long NFCSA : 2; + unsigned long NFAEN : 1; + unsigned long : 2; + unsigned long OADF : 2; + unsigned long OAE : 1; + unsigned long OAHLD : 1; + unsigned long OADFLT : 1; + unsigned long : 1; + unsigned long GTIOA : 5; +#endif + } BIT; + } GTIOR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GTINTA : 1; + unsigned long GTINTB : 1; + unsigned long GTINTC : 1; + unsigned long GTINTD : 1; + unsigned long GTINTE : 1; + unsigned long GTINTF : 1; + unsigned long GTINTPR : 2; + unsigned long : 8; + unsigned long ADTRAUEN : 1; + unsigned long ADTRADEN : 1; + unsigned long ADTRBUEN : 1; + unsigned long ADTRBDEN : 1; + unsigned long : 4; + unsigned long GRP : 2; + unsigned long : 2; + unsigned long GRPDTE : 1; + unsigned long GRPABH : 1; + unsigned long GRPABL : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long GRPABL : 1; + unsigned long GRPABH : 1; + unsigned long GRPDTE : 1; + unsigned long : 2; + unsigned long GRP : 2; + unsigned long : 4; + unsigned long ADTRBDEN : 1; + unsigned long ADTRBUEN : 1; + unsigned long ADTRADEN : 1; + unsigned long ADTRAUEN : 1; + unsigned long : 8; + unsigned long GTINTPR : 2; + unsigned long GTINTF : 1; + unsigned long GTINTE : 1; + unsigned long GTINTD : 1; + unsigned long GTINTC : 1; + unsigned long GTINTB : 1; + unsigned long GTINTA : 1; +#endif + } BIT; + } GTINTAD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long ITCNT : 3; + unsigned long : 4; + unsigned long TUCF : 1; + unsigned long ADTRAUF : 1; + unsigned long ADTRADF : 1; + unsigned long ADTRBUF : 1; + unsigned long ADTRBDF : 1; + unsigned long : 4; + unsigned long ODF : 1; + unsigned long : 3; + unsigned long DTEF : 1; + unsigned long OABHF : 1; + unsigned long OABLF : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long OABLF : 1; + unsigned long OABHF : 1; + unsigned long DTEF : 1; + unsigned long : 3; + unsigned long ODF : 1; + unsigned long : 4; + unsigned long ADTRBDF : 1; + unsigned long ADTRBUF : 1; + unsigned long ADTRADF : 1; + unsigned long ADTRAUF : 1; + unsigned long TUCF : 1; + unsigned long : 4; + unsigned long ITCNT : 3; + unsigned long : 8; +#endif + } BIT; + } GTST; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BD : 4; + unsigned long : 4; + unsigned long DBRTECA : 1; + unsigned long : 1; + unsigned long DBRTECB : 1; + unsigned long : 5; + unsigned long CCRA : 2; + unsigned long CCRB : 2; + unsigned long PR : 2; + unsigned long CCRSWT : 1; + unsigned long : 1; + unsigned long ADTTA : 2; + unsigned long ADTDA : 1; + unsigned long : 1; + unsigned long ADTTB : 2; + unsigned long ADTDB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long ADTDB : 1; + unsigned long ADTTB : 2; + unsigned long : 1; + unsigned long ADTDA : 1; + unsigned long ADTTA : 2; + unsigned long : 1; + unsigned long CCRSWT : 1; + unsigned long PR : 2; + unsigned long CCRB : 2; + unsigned long CCRA : 2; + unsigned long : 5; + unsigned long DBRTECB : 1; + unsigned long : 1; + unsigned long DBRTECA : 1; + unsigned long : 4; + unsigned long BD : 4; +#endif + } BIT; + } GTBER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ITLA : 1; + unsigned long ITLB : 1; + unsigned long ITLC : 1; + unsigned long ITLD : 1; + unsigned long ITLE : 1; + unsigned long ITLF : 1; + unsigned long IVTC : 2; + unsigned long IVTT : 3; + unsigned long : 1; + unsigned long ADTAL : 1; + unsigned long : 1; + unsigned long ADTBL : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long ADTBL : 1; + unsigned long : 1; + unsigned long ADTAL : 1; + unsigned long : 1; + unsigned long IVTT : 3; + unsigned long IVTC : 2; + unsigned long ITLF : 1; + unsigned long ITLE : 1; + unsigned long ITLD : 1; + unsigned long ITLC : 1; + unsigned long ITLB : 1; + unsigned long ITLA : 1; +#endif + } BIT; + } GTITC; + unsigned long GTCNT; + unsigned long GTCCRA; + unsigned long GTCCRB; + unsigned long GTCCRC; + unsigned long GTCCRE; + unsigned long GTCCRD; + unsigned long GTCCRF; + unsigned long GTPR; + unsigned long GTPBR; + unsigned long GTPDBR; + unsigned long GTADTRA; + unsigned long GTADTBRA; + unsigned long GTADTDBRA; + unsigned long GTADTRB; + unsigned long GTADTBRB; + unsigned long GTADTDBRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDE : 1; + unsigned long : 3; + unsigned long TDBUE : 1; + unsigned long TDBDE : 1; + unsigned long : 2; + unsigned long TDFER : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long TDFER : 1; + unsigned long : 2; + unsigned long TDBDE : 1; + unsigned long TDBUE : 1; + unsigned long : 3; + unsigned long TDE : 1; +#endif + } BIT; + } GTDTCR; + unsigned long GTDVU; + unsigned long GTDVD; + unsigned long GTDBU; + unsigned long GTDBD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SOS : 2; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long SOS : 2; +#endif + } BIT; + } GTSOS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SOTR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SOTR : 1; +#endif + } BIT; + } GTSOTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ADSMS0 : 2; + unsigned long : 6; + unsigned long ADSMEN0 : 1; + unsigned long : 7; + unsigned long ADSMS1 : 2; + unsigned long : 6; + unsigned long ADSMEN1 : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ADSMEN1 : 1; + unsigned long : 6; + unsigned long ADSMS1 : 2; + unsigned long : 7; + unsigned long ADSMEN0 : 1; + unsigned long : 6; + unsigned long ADSMS0 : 2; +#endif + } BIT; + } GTADSMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EIVTC1 : 2; + unsigned long : 2; + unsigned long EIVTT1 : 4; + unsigned long : 4; + unsigned long EITCNT1 : 4; + unsigned long EIVTC2 : 2; + unsigned long : 2; + unsigned long EIVTT2 : 4; + unsigned long EITCNT2IV : 4; + unsigned long EITCNT2 : 4; +#else + unsigned long EITCNT2 : 4; + unsigned long EITCNT2IV : 4; + unsigned long EIVTT2 : 4; + unsigned long : 2; + unsigned long EIVTC2 : 2; + unsigned long EITCNT1 : 4; + unsigned long : 4; + unsigned long EIVTT1 : 4; + unsigned long : 2; + unsigned long EIVTC1 : 2; +#endif + } BIT; + } GTEITC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EITLA : 3; + unsigned long : 1; + unsigned long EITLB : 3; + unsigned long : 1; + unsigned long EITLC : 3; + unsigned long : 1; + unsigned long EITLD : 3; + unsigned long : 1; + unsigned long EITLE : 3; + unsigned long : 1; + unsigned long EITLF : 3; + unsigned long : 1; + unsigned long EITLV : 3; + unsigned long : 1; + unsigned long EITLU : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long EITLU : 3; + unsigned long : 1; + unsigned long EITLV : 3; + unsigned long : 1; + unsigned long EITLF : 3; + unsigned long : 1; + unsigned long EITLE : 3; + unsigned long : 1; + unsigned long EITLD : 3; + unsigned long : 1; + unsigned long EITLC : 3; + unsigned long : 1; + unsigned long EITLB : 3; + unsigned long : 1; + unsigned long EITLA : 3; +#endif + } BIT; + } GTEITLI1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EADTAL : 3; + unsigned long : 1; + unsigned long EADTBL : 3; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long EADTBL : 3; + unsigned long : 1; + unsigned long EADTAL : 3; +#endif + } BIT; + } GTEITLI2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EBTLCA : 3; + unsigned long : 1; + unsigned long EBTLCB : 3; + unsigned long : 1; + unsigned long EBTLPR : 3; + unsigned long : 5; + unsigned long EBTLADA : 3; + unsigned long : 1; + unsigned long EBTLADB : 3; + unsigned long : 1; + unsigned long EBTLDVU : 3; + unsigned long : 1; + unsigned long EBTLDVD : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long EBTLDVD : 3; + unsigned long : 1; + unsigned long EBTLDVU : 3; + unsigned long : 1; + unsigned long EBTLADB : 3; + unsigned long : 1; + unsigned long EBTLADA : 3; + unsigned long : 5; + unsigned long EBTLPR : 3; + unsigned long : 1; + unsigned long EBTLCB : 3; + unsigned long : 1; + unsigned long EBTLCA : 3; +#endif + } BIT; + } GTEITLB; + char wk0[24]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SECSEL0 : 1; + unsigned long SECSEL1 : 1; + unsigned long SECSEL2 : 1; + unsigned long SECSEL3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long SECSEL3 : 1; + unsigned long SECSEL2 : 1; + unsigned long SECSEL1 : 1; + unsigned long SECSEL0 : 1; +#endif + } BIT; + } GTSECSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SBDCE : 1; + unsigned long SBDPE : 1; + unsigned long SBDAE : 1; + unsigned long SBDDE : 1; + unsigned long : 4; + unsigned long SBDCD : 1; + unsigned long SBDPD : 1; + unsigned long SBDAD : 1; + unsigned long SBDDD : 1; + unsigned long : 20; +#else + unsigned long : 20; + unsigned long SBDDD : 1; + unsigned long SBDAD : 1; + unsigned long SBDPD : 1; + unsigned long SBDCD : 1; + unsigned long : 4; + unsigned long SBDDE : 1; + unsigned long SBDAE : 1; + unsigned long SBDPE : 1; + unsigned long SBDCE : 1; +#endif + } BIT; + } GTSECR; +} st_gptw_t; + +typedef struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT2 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT2 : 1; +#endif + } BIT; + } SWINT2R; + char wk1[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[16]; + char wk11[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN8 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN15 : 1; +#else + unsigned char FLTEN15 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN8 : 1; +#endif + } BIT; + } IRQFLTE1; + char wk12[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL8 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL15 : 2; +#else + unsigned short FCLKSEL15 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL8 : 2; +#endif + } BIT; + } IRQFLTC1; + char wk13[84]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char EXNMIST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char EXNMIST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char EXNMIEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char EXNMIEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMST : 1; + unsigned char DPFPUST : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DPFPUST : 1; + unsigned char RAMST : 1; +#endif + } BIT; + } EXNMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMEN : 1; + unsigned char DPFPUEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DPFPUEN : 1; + unsigned char RAMEN : 1; +#endif + } BIT; + } EXNMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char DPFPUCLR : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DPFPUCLR : 1; + unsigned char : 1; +#endif + } BIT; + } EXNMICLR; + char wk14[9]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk15[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; + char wk16[27]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPIE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENIE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR0 : 1; + unsigned long CLR1 : 1; + unsigned long CLR2 : 1; + unsigned long CLR3 : 1; + unsigned long CLR4 : 1; + unsigned long CLR5 : 1; + unsigned long CLR6 : 1; + unsigned long CLR7 : 1; + unsigned long CLR8 : 1; + unsigned long CLR9 : 1; + unsigned long CLR10 : 1; + unsigned long CLR11 : 1; + unsigned long CLR12 : 1; + unsigned long CLR13 : 1; + unsigned long CLR14 : 1; + unsigned long CLR15 : 1; + unsigned long CLR16 : 1; + unsigned long CLR17 : 1; + unsigned long CLR18 : 1; + unsigned long CLR19 : 1; + unsigned long CLR20 : 1; + unsigned long CLR21 : 1; + unsigned long CLR22 : 1; + unsigned long CLR23 : 1; + unsigned long CLR24 : 1; + unsigned long CLR25 : 1; + unsigned long CLR26 : 1; + unsigned long CLR27 : 1; + unsigned long CLR28 : 1; + unsigned long CLR29 : 1; + unsigned long CLR30 : 1; + unsigned long CLR31 : 1; +#else + unsigned long CLR31 : 1; + unsigned long CLR30 : 1; + unsigned long CLR29 : 1; + unsigned long CLR28 : 1; + unsigned long CLR27 : 1; + unsigned long CLR26 : 1; + unsigned long CLR25 : 1; + unsigned long CLR24 : 1; + unsigned long CLR23 : 1; + unsigned long CLR22 : 1; + unsigned long CLR21 : 1; + unsigned long CLR20 : 1; + unsigned long CLR19 : 1; + unsigned long CLR18 : 1; + unsigned long CLR17 : 1; + unsigned long CLR16 : 1; + unsigned long CLR15 : 1; + unsigned long CLR14 : 1; + unsigned long CLR13 : 1; + unsigned long CLR12 : 1; + unsigned long CLR11 : 1; + unsigned long CLR10 : 1; + unsigned long CLR9 : 1; + unsigned long CLR8 : 1; + unsigned long CLR7 : 1; + unsigned long CLR6 : 1; + unsigned long CLR5 : 1; + unsigned long CLR4 : 1; + unsigned long CLR3 : 1; + unsigned long CLR2 : 1; + unsigned long CLR1 : 1; + unsigned long CLR0 : 1; +#endif + } BIT; + } GCRIE0; + char wk17[68]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBE0; + char wk18[44]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL2; + char wk19[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBE0; + char wk20[44]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL2; + char wk21[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR0 : 1; + unsigned long CLR1 : 1; + unsigned long CLR2 : 1; + unsigned long CLR3 : 1; + unsigned long CLR4 : 1; + unsigned long CLR5 : 1; + unsigned long CLR6 : 1; + unsigned long CLR7 : 1; + unsigned long CLR8 : 1; + unsigned long CLR9 : 1; + unsigned long CLR10 : 1; + unsigned long CLR11 : 1; + unsigned long CLR12 : 1; + unsigned long CLR13 : 1; + unsigned long CLR14 : 1; + unsigned long CLR15 : 1; + unsigned long CLR16 : 1; + unsigned long CLR17 : 1; + unsigned long CLR18 : 1; + unsigned long CLR19 : 1; + unsigned long CLR20 : 1; + unsigned long CLR21 : 1; + unsigned long CLR22 : 1; + unsigned long CLR23 : 1; + unsigned long CLR24 : 1; + unsigned long CLR25 : 1; + unsigned long CLR26 : 1; + unsigned long CLR27 : 1; + unsigned long CLR28 : 1; + unsigned long CLR29 : 1; + unsigned long CLR30 : 1; + unsigned long CLR31 : 1; +#else + unsigned long CLR31 : 1; + unsigned long CLR30 : 1; + unsigned long CLR29 : 1; + unsigned long CLR28 : 1; + unsigned long CLR27 : 1; + unsigned long CLR26 : 1; + unsigned long CLR25 : 1; + unsigned long CLR24 : 1; + unsigned long CLR23 : 1; + unsigned long CLR22 : 1; + unsigned long CLR21 : 1; + unsigned long CLR20 : 1; + unsigned long CLR19 : 1; + unsigned long CLR18 : 1; + unsigned long CLR17 : 1; + unsigned long CLR16 : 1; + unsigned long CLR15 : 1; + unsigned long CLR14 : 1; + unsigned long CLR13 : 1; + unsigned long CLR12 : 1; + unsigned long CLR11 : 1; + unsigned long CLR10 : 1; + unsigned long CLR9 : 1; + unsigned long CLR8 : 1; + unsigned long CLR7 : 1; + unsigned long CLR6 : 1; + unsigned long CLR5 : 1; + unsigned long CLR4 : 1; + unsigned long CLR3 : 1; + unsigned long CLR2 : 1; + unsigned long CLR1 : 1; + unsigned long CLR0 : 1; +#endif + } BIT; + } GCRBE0; + char wk22[124]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR5; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR6; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR8; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBR9; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIBRB; + char wk23[116]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR128; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR129; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR130; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR131; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR132; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR133; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR134; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR135; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR136; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR137; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR138; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR139; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR140; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR141; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR142; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBXR143; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR144; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR145; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR146; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR147; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR148; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR149; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR150; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR151; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR152; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR153; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR154; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR155; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR156; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR157; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR158; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR159; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR160; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR161; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR162; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR163; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR164; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR165; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR166; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR167; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR168; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR169; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR170; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR171; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR172; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR173; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR174; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR175; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR176; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR177; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR178; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR179; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR180; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR181; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR182; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR183; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR184; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR185; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR186; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR187; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR188; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR189; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR190; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR191; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR192; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR193; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR194; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR195; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR196; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR197; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR198; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR199; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR200; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR201; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR202; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR203; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR204; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR205; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR206; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIBR207; + char wk24[96]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPAL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPAL1; + char wk25[56]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENAL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENAL1; + char wk26[136]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR5; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR6; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR8; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR9; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARA; + char wk27[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARC; + char wk28[195]; + union { + unsigned char BYTE; + } SLIAR208; + union { + unsigned char BYTE; + } SLIAR209; + union { + unsigned char BYTE; + } SLIAR210; + union { + unsigned char BYTE; + } SLIAR211; + union { + unsigned char BYTE; + } SLIAR212; + union { + unsigned char BYTE; + } SLIAR213; + union { + unsigned char BYTE; + } SLIAR214; + union { + unsigned char BYTE; + } SLIAR215; + union { + unsigned char BYTE; + } SLIAR216; + union { + unsigned char BYTE; + } SLIAR217; + union { + unsigned char BYTE; + } SLIAR218; + union { + unsigned char BYTE; + } SLIAR219; + union { + unsigned char BYTE; + } SLIAR220; + union { + unsigned char BYTE; + } SLIAR221; + union { + unsigned char BYTE; + } SLIAR222; + union { + unsigned char BYTE; + } SLIAR223; + union { + unsigned char BYTE; + } SLIAR224; + union { + unsigned char BYTE; + } SLIAR225; + union { + unsigned char BYTE; + } SLIAR226; + union { + unsigned char BYTE; + } SLIAR227; + union { + unsigned char BYTE; + } SLIAR228; + union { + unsigned char BYTE; + } SLIAR229; + union { + unsigned char BYTE; + } SLIAR230; + union { + unsigned char BYTE; + } SLIAR231; + union { + unsigned char BYTE; + } SLIAR232; + union { + unsigned char BYTE; + } SLIAR233; + union { + unsigned char BYTE; + } SLIAR234; + union { + unsigned char BYTE; + } SLIAR235; + union { + unsigned char BYTE; + } SLIAR236; + union { + unsigned char BYTE; + } SLIAR237; + union { + unsigned char BYTE; + } SLIAR238; + union { + unsigned char BYTE; + } SLIAR239; + union { + unsigned char BYTE; + } SLIAR240; + union { + unsigned char BYTE; + } SLIAR241; + union { + unsigned char BYTE; + } SLIAR242; + union { + unsigned char BYTE; + } SLIAR243; + union { + unsigned char BYTE; + } SLIAR244; + union { + unsigned char BYTE; + } SLIAR245; + union { + unsigned char BYTE; + } SLIAR246; + union { + unsigned char BYTE; + } SLIAR247; + union { + unsigned char BYTE; + } SLIAR248; + union { + unsigned char BYTE; + } SLIAR249; + union { + unsigned char BYTE; + } SLIAR250; + union { + unsigned char BYTE; + } SLIAR251; + union { + unsigned char BYTE; + } SLIAR252; + union { + unsigned char BYTE; + } SLIAR253; + union { + unsigned char BYTE; + } SLIAR254; + union { + unsigned char BYTE; + } SLIAR255; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WPRC : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char WPRC : 1; +#endif + } BIT; + } SLIPRCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SELEXD0 : 1; + unsigned char SELEXD1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SELEXD1 : 1; + unsigned char SELEXD0 : 1; +#endif + } BIT; + } SELEXDR; +} st_icu_t; + +typedef struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +} st_iwdt_t; + +typedef struct st_mmcif { + union { + unsigned long LONG; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned long :1; + unsigned long BOOT:1; + unsigned long CMD:6; + unsigned long RTYP:2; + unsigned long RBSY:1; + unsigned long :1; + unsigned long WDAT:1; + unsigned long DWEN:1; + unsigned long CMLTE:1; + unsigned long CMD12EN:1; + unsigned long RIDXC:2; + unsigned long RCRC7C:2; + unsigned long :1; + unsigned long CRC16C:1; + unsigned long BOOTACK:1; + unsigned long CRCSTE:1; + unsigned long TBIT:1; + unsigned long OPDM:1; + unsigned long :2; + unsigned long SBIT:1; + unsigned long :1; + unsigned long DATW:2; + } BIT; +#endif + } CECMDSET; + char wk0[4]; + union { + unsigned long LONG; + } CEARG; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long C12ARG : 32; +#else + unsigned long C12ARG : 32; +#endif + } BIT; + } CEARGCMD12; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BREAK : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long BREAK : 1; +#endif + } BIT; + } CECMDCTRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BLKSIZ : 16; + unsigned long BLKCNT : 16; +#else + unsigned long BLKCNT : 16; + unsigned long BLKSIZ : 16; +#endif + } BIT; + } CEBLOCKSET; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long SRWDTO : 4; + unsigned long SRBSYTO : 4; + unsigned long SRSPTO : 2; + unsigned long : 2; + unsigned long CLKDIV : 4; + unsigned long : 4; + unsigned long CLKEN : 1; + unsigned long : 6; + unsigned long MMCBUSBSY : 1; +#else + unsigned long MMCBUSBSY : 1; + unsigned long : 6; + unsigned long CLKEN : 1; + unsigned long : 4; + unsigned long CLKDIV : 4; + unsigned long : 2; + unsigned long SRSPTO : 2; + unsigned long SRBSYTO : 4; + unsigned long SRWDTO : 4; + unsigned long : 4; +#endif + } BIT; + } CECLKCTRL; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long ATYP : 1; + unsigned long : 7; + unsigned long DMAREN : 1; + unsigned long DMAWEN : 1; + unsigned long DMATYP : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long DMATYP : 1; + unsigned long DMAWEN : 1; + unsigned long DMAREN : 1; + unsigned long : 7; + unsigned long ATYP : 1; + unsigned long : 16; +#endif + } BIT; + } CEBUFACC; + unsigned long CERESP3; + unsigned long CERESP2; + unsigned long CERESP1; + unsigned long CERESP0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSP12 : 32; +#else + unsigned long RSP12 : 32; +#endif + } BIT; + } CERESPCMD12; + unsigned long CEDATA; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long SBTDATTO : 4; + unsigned long SFSTBTDATTO : 4; + unsigned long SBTACKTO : 4; + unsigned long SBTCLKDIV : 4; +#else + unsigned long SBTCLKDIV : 4; + unsigned long SBTACKTO : 4; + unsigned long SFSTBTDATTO : 4; + unsigned long SBTDATTO : 4; + unsigned long : 16; +#endif + } BIT; + } CEBOOT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPTO : 1; + unsigned long RBSYTO : 1; + unsigned long RDATTO : 1; + unsigned long WDATTO : 1; + unsigned long CRCSTO : 1; + unsigned long : 3; + unsigned long RSPERR : 1; + unsigned long RIDXERR : 1; + unsigned long RDATERR : 1; + unsigned long WDATERR : 1; + unsigned long : 2; + unsigned long BUFVIO : 1; + unsigned long CMDVIO : 1; + unsigned long CRSPE : 1; + unsigned long RBSYE : 1; + unsigned long : 2; + unsigned long BUFREN : 1; + unsigned long BUFWEN : 1; + unsigned long BUFRE : 1; + unsigned long DTRANE : 1; + unsigned long CMD12CRE : 1; + unsigned long CMD12RBE : 1; + unsigned long CMD12DRE : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long CMD12DRE : 1; + unsigned long CMD12RBE : 1; + unsigned long CMD12CRE : 1; + unsigned long DTRANE : 1; + unsigned long BUFRE : 1; + unsigned long BUFWEN : 1; + unsigned long BUFREN : 1; + unsigned long : 2; + unsigned long RBSYE : 1; + unsigned long CRSPE : 1; + unsigned long CMDVIO : 1; + unsigned long BUFVIO : 1; + unsigned long : 2; + unsigned long WDATERR : 1; + unsigned long RDATERR : 1; + unsigned long RIDXERR : 1; + unsigned long RSPERR : 1; + unsigned long : 3; + unsigned long CRCSTO : 1; + unsigned long WDATTO : 1; + unsigned long RDATTO : 1; + unsigned long RBSYTO : 1; + unsigned long RSPTO : 1; +#endif + } BIT; + } CEINT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MRSPTO : 1; + unsigned long MRBSYTO : 1; + unsigned long MRDATTO : 1; + unsigned long MWDATTO : 1; + unsigned long MCRCSTO : 1; + unsigned long : 3; + unsigned long MRSPERR : 1; + unsigned long MRIDXERR : 1; + unsigned long MRDATERR : 1; + unsigned long MWDATERR : 1; + unsigned long : 2; + unsigned long MBUFVIO : 1; + unsigned long MCMDVIO : 1; + unsigned long MCRSPE : 1; + unsigned long MRBSYE : 1; + unsigned long : 2; + unsigned long MBUFREN : 1; + unsigned long MBUFWEN : 1; + unsigned long MBUFRE : 1; + unsigned long MDTRANE : 1; + unsigned long MCMD12CRE : 1; + unsigned long MCMD12RBE : 1; + unsigned long MCMD12DRE : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long MCMD12DRE : 1; + unsigned long MCMD12RBE : 1; + unsigned long MCMD12CRE : 1; + unsigned long MDTRANE : 1; + unsigned long MBUFRE : 1; + unsigned long MBUFWEN : 1; + unsigned long MBUFREN : 1; + unsigned long : 2; + unsigned long MRBSYE : 1; + unsigned long MCRSPE : 1; + unsigned long MCMDVIO : 1; + unsigned long MBUFVIO : 1; + unsigned long : 2; + unsigned long MWDATERR : 1; + unsigned long MRDATERR : 1; + unsigned long MRIDXERR : 1; + unsigned long MRSPERR : 1; + unsigned long : 3; + unsigned long MCRCSTO : 1; + unsigned long MWDATTO : 1; + unsigned long MRDATTO : 1; + unsigned long MRBSYTO : 1; + unsigned long MRSPTO : 1; +#endif + } BIT; + } CEINTEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RCVBLK : 16; + unsigned long DATSIG : 8; + unsigned long RSPIDX : 6; + unsigned long CMDSIG : 1; + unsigned long CMDSEQ : 1; +#else + unsigned long CMDSEQ : 1; + unsigned long CMDSIG : 1; + unsigned long RSPIDX : 6; + unsigned long DATSIG : 8; + unsigned long RCVBLK : 16; +#endif + } BIT; + } CEHOSTSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 5; + unsigned long BTDATTO : 1; + unsigned long FSTBTDATTO : 1; + unsigned long BTACKTO : 1; + unsigned long STRSPTO : 1; + unsigned long AC12RSPTO : 1; + unsigned long RSPBSYTO : 1; + unsigned long AC12BSYTO : 1; + unsigned long CRCSTTO : 1; + unsigned long DATBSYTO : 1; + unsigned long STRDATTO : 1; + unsigned long : 1; + unsigned long CRCST : 3; + unsigned long : 1; + unsigned long BTACKEBE : 1; + unsigned long BTACKPATE : 1; + unsigned long RSPIDXE : 1; + unsigned long AC12IDXE : 1; + unsigned long RSPEBE : 1; + unsigned long AC12REBE : 1; + unsigned long RDATEBE : 1; + unsigned long CRCSTEBE : 1; + unsigned long RSPCRC7E : 1; + unsigned long AC12CRCE : 1; + unsigned long CRC16E : 1; + unsigned long CRCSTE : 1; +#else + unsigned long CRCSTE : 1; + unsigned long CRC16E : 1; + unsigned long AC12CRCE : 1; + unsigned long RSPCRC7E : 1; + unsigned long CRCSTEBE : 1; + unsigned long RDATEBE : 1; + unsigned long AC12REBE : 1; + unsigned long RSPEBE : 1; + unsigned long AC12IDXE : 1; + unsigned long RSPIDXE : 1; + unsigned long BTACKPATE : 1; + unsigned long BTACKEBE : 1; + unsigned long : 1; + unsigned long CRCST : 3; + unsigned long : 1; + unsigned long STRDATTO : 1; + unsigned long DATBSYTO : 1; + unsigned long CRCSTTO : 1; + unsigned long AC12BSYTO : 1; + unsigned long RSPBSYTO : 1; + unsigned long AC12RSPTO : 1; + unsigned long STRSPTO : 1; + unsigned long BTACKTO : 1; + unsigned long FSTBTDATTO : 1; + unsigned long BTDATTO : 1; + unsigned long : 5; +#endif + } BIT; + } CEHOSTSTS2; + char wk2[32]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MCDFALL : 1; + unsigned long MCDRISE : 1; + unsigned long : 6; + unsigned long CDFALL : 1; + unsigned long CDRISE : 1; + unsigned long CDSIG : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long CDSIG : 1; + unsigned long CDRISE : 1; + unsigned long CDFALL : 1; + unsigned long : 6; + unsigned long MCDRISE : 1; + unsigned long MCDFALL : 1; + unsigned long : 4; +#endif + } BIT; + } CEDETECT; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 19; + unsigned long CLKMAIN : 1; + unsigned long : 1; + unsigned long RESNOUT : 1; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long RESNOUT : 1; + unsigned long : 1; + unsigned long CLKMAIN : 1; + unsigned long : 19; +#endif + } BIT; + } CEADDMODE; + char wk3[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VERSION : 16; + unsigned long : 15; + unsigned long SWRST : 1; +#else + unsigned long SWRST : 1; + unsigned long : 15; + unsigned long VERSION : 16; +#endif + } BIT; + } CEVERSION; +} st_mmcif_t; + +typedef struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0E : 1; + unsigned char CS1E : 1; + unsigned char CS2E : 1; + unsigned char CS3E : 1; + unsigned char CS4E : 1; + unsigned char CS5E : 1; + unsigned char CS6E : 1; + unsigned char CS7E : 1; +#else + unsigned char CS7E : 1; + unsigned char CS6E : 1; + unsigned char CS5E : 1; + unsigned char CS4E : 1; + unsigned char CS3E : 1; + unsigned char CS2E : 1; + unsigned char CS1E : 1; + unsigned char CS0E : 1; +#endif + } BIT; + } PFCSE; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0S : 1; + unsigned char : 1; + unsigned char CS1S : 2; + unsigned char CS2S : 2; + unsigned char CS3S : 2; +#else + unsigned char CS3S : 2; + unsigned char CS2S : 2; + unsigned char CS1S : 2; + unsigned char : 1; + unsigned char CS0S : 1; +#endif + } BIT; + } PFCSS0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS4S : 2; + unsigned char CS5S : 2; + unsigned char CS6S : 2; + unsigned char CS7S : 2; +#else + unsigned char CS7S : 2; + unsigned char CS6S : 2; + unsigned char CS5S : 2; + unsigned char CS4S : 2; +#endif + } BIT; + } PFCSS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A8E : 1; + unsigned char A9E : 1; + unsigned char A10E : 1; + unsigned char A11E : 1; + unsigned char A12E : 1; + unsigned char A13E : 1; + unsigned char A14E : 1; + unsigned char A15E : 1; +#else + unsigned char A15E : 1; + unsigned char A14E : 1; + unsigned char A13E : 1; + unsigned char A12E : 1; + unsigned char A11E : 1; + unsigned char A10E : 1; + unsigned char A9E : 1; + unsigned char A8E : 1; +#endif + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A16E : 1; + unsigned char A17E : 1; + unsigned char A18E : 1; + unsigned char A19E : 1; + unsigned char A20E : 1; + unsigned char A21E : 1; + unsigned char A22E : 1; + unsigned char A23E : 1; +#else + unsigned char A23E : 1; + unsigned char A22E : 1; + unsigned char A21E : 1; + unsigned char A20E : 1; + unsigned char A19E : 1; + unsigned char A18E : 1; + unsigned char A17E : 1; + unsigned char A16E : 1; +#endif + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADRLE : 1; + unsigned char ADRHMS : 1; + unsigned char ADRHMS2 : 1; + unsigned char BCLKO : 1; + unsigned char DHE : 1; + unsigned char DH32E : 1; + unsigned char WR1BC1E : 1; + unsigned char WR32BC32E : 1; +#else + unsigned char WR32BC32E : 1; + unsigned char WR1BC1E : 1; + unsigned char DH32E : 1; + unsigned char DHE : 1; + unsigned char BCLKO : 1; + unsigned char ADRHMS2 : 1; + unsigned char ADRHMS : 1; + unsigned char ADRLE : 1; +#endif + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAITS : 2; + unsigned char ALEOE : 1; + unsigned char ALES : 1; + unsigned char MDSDE : 1; + unsigned char : 1; + unsigned char DQM1E : 1; + unsigned char SDCLKE : 1; +#else + unsigned char SDCLKE : 1; + unsigned char DQM1E : 1; + unsigned char : 1; + unsigned char MDSDE : 1; + unsigned char ALES : 1; + unsigned char ALEOE : 1; + unsigned char WAITS : 2; +#endif + } BIT; + } PFBCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D0S : 2; + unsigned char D1S : 2; + unsigned char D2S : 2; + unsigned char D3S : 2; +#else + unsigned char D3S : 2; + unsigned char D2S : 2; + unsigned char D1S : 2; + unsigned char D0S : 2; +#endif + } BIT; + } PFBCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLHS : 1; + unsigned char : 5; + unsigned char SDCLKDRV : 1; + unsigned char WAITS2 : 1; +#else + unsigned char WAITS2 : 1; + unsigned char SDCLKDRV : 1; + unsigned char : 5; + unsigned char DLHS : 1; +#endif + } BIT; + } PFBCR3; + char wk1[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char PHYMODE0 : 1; + unsigned char PHYMODE1 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PHYMODE1 : 1; + unsigned char PHYMODE0 : 1; + unsigned char : 4; +#endif + } BIT; + } PFENET; + char wk2[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P01PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P02PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P03PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P05PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P52PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P56PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P57PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P60PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P61PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P62PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P63PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P64PFS; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P66PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P67PFS; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P71PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P72PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P76PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P77PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P82PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P83PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P84PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P85PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P86PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P87PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P93PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P94PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P95PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P96PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P97PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PF0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PF1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PF2PFS; + char wk10[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } PF5PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PG7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PH7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ3PFS; + char wk12[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PJ5PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PK7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PL7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PM7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PN0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PN1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PN2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PN3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PN4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PN5PFS; + char wk14[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PQ7PFS; +} st_mpc_t; + +typedef struct st_mpu { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MPEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MPEN : 1; +#endif + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UBAC : 3; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long UBAC : 3; + unsigned long : 1; +#endif + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CLR : 1; +#endif + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IMPER : 1; + unsigned long DMPER : 1; + unsigned long DRW : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DRW : 1; + unsigned long DMPER : 1; + unsigned long IMPER : 1; +#endif + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEA : 32; +#else + unsigned long DEA : 32; +#endif + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SA : 32; +#else + unsigned long SA : 32; +#endif + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short S : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short S : 1; +#endif + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short INV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short INV : 1; +#endif + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACI : 3; + unsigned long : 12; + unsigned long HITI : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITI : 8; + unsigned long : 12; + unsigned long UHACI : 3; + unsigned long : 1; +#endif + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACD : 3; + unsigned long : 12; + unsigned long HITD : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITD : 8; + unsigned long : 12; + unsigned long UHACD : 3; + unsigned long : 1; +#endif + } BIT; + } MHITD; +} st_mpu_t; + +typedef struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOERA; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTERA; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDERA; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBRA; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif + } BIT; + } TITMRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4COR : 3; +#endif + } BIT; + } TITCR2A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4CNT : 3; +#endif + } BIT; + } TITCNT2A; + char wk7[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif + } BIT; + } TWCRA; + char wk8[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif + } BIT; + } TMDR2A; + char wk9[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST8 : 1; + unsigned char : 2; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 2; + unsigned char CST8 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCH7 : 1; + unsigned char SCH6 : 1; + unsigned char : 1; + unsigned char SCH4 : 1; + unsigned char SCH3 : 1; + unsigned char SCH2 : 1; + unsigned char SCH1 : 1; + unsigned char SCH0 : 1; +#else + unsigned char SCH0 : 1; + unsigned char SCH1 : 1; + unsigned char SCH2 : 1; + unsigned char SCH3 : 1; + unsigned char SCH4 : 1; + unsigned char : 1; + unsigned char SCH6 : 1; + unsigned char SCH7 : 1; +#endif + } BIT; + } TCSYSTR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWERA; + char wk11[1925]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE6B : 1; + unsigned char OE7A : 1; + unsigned char OE7B : 1; + unsigned char OE6D : 1; + unsigned char OE7C : 1; + unsigned char OE7D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE7D : 1; + unsigned char OE7C : 1; + unsigned char OE6D : 1; + unsigned char OE7B : 1; + unsigned char OE7A : 1; + unsigned char OE6B : 1; +#endif + } BIT; + } TOERB; + char wk12[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCOR : 3; + unsigned char T7VEN : 1; + unsigned char T6ACOR : 3; + unsigned char T6AEN : 1; +#else + unsigned char T6AEN : 1; + unsigned char T6ACOR : 3; + unsigned char T7VEN : 1; + unsigned char T7VCOR : 3; +#endif + } BIT; + } TITCR1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCNT : 3; + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; + unsigned char T7VCNT : 3; +#endif + } BIT; + } TITCNT1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTERB; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDERB; + char wk17[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBRB; + char wk18[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif + } BIT; + } TITMRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7COR : 3; +#endif + } BIT; + } TITCR2B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7CNT : 3; +#endif + } BIT; + } TITCNT2B; + char wk19[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif + } BIT; + } TWCRB; + char wk20[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif + } BIT; + } TMDR2B; + char wk21[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char CST6 : 1; + unsigned char CST7 : 1; +#else + unsigned char CST7 : 1; + unsigned char CST6 : 1; + unsigned char : 6; +#endif + } BIT; + } TSTRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char SYNC6 : 1; + unsigned char SYNC7 : 1; +#else + unsigned char SYNC7 : 1; + unsigned char SYNC6 : 1; + unsigned char : 6; +#endif + } BIT; + } TSYRB; + char wk22[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWERB; +} st_mtu_t; + +typedef struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR0; + char wk0[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCRC; + char wk1[102]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 5; + unsigned char TTGE2 : 1; +#else + unsigned char TTGE2 : 1; + unsigned char : 5; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +} st_mtu0_t; + +typedef struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR1; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LWA : 1; + unsigned char PHCKSEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PHCKSEL : 1; + unsigned char LWA : 1; +#endif + } BIT; + } TMDR3; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +} st_mtu1_t; + +typedef struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR2; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +} st_mtu2_t; + +typedef struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR3; +} st_mtu3_t; + +typedef struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR4; +} st_mtu4_t; + +typedef struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2U; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2V; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2W; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk4[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +} st_mtu5_t; + +typedef struct st_mtu6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CE2B : 1; + unsigned char CE2A : 1; + unsigned char CE1B : 1; + unsigned char CE1A : 1; + unsigned char CE0D : 1; + unsigned char CE0C : 1; + unsigned char CE0B : 1; + unsigned char CE0A : 1; +#else + unsigned char CE0A : 1; + unsigned char CE0B : 1; + unsigned char CE0C : 1; + unsigned char CE0D : 1; + unsigned char CE1A : 1; + unsigned char CE1B : 1; + unsigned char CE2A : 1; + unsigned char CE2B : 1; +#endif + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR6; +} st_mtu6_t; + +typedef struct st_mtu7 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITA6AE : 1; + unsigned short DT7BE : 1; + unsigned short UT7BE : 1; + unsigned short DT7AE : 1; + unsigned short UT7AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT7AE : 1; + unsigned short DT7AE : 1; + unsigned short UT7BE : 1; + unsigned short DT7BE : 1; + unsigned short ITA6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITB7VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR7; +} st_mtu7_t; + +typedef struct st_mtu8 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR8; + char wk0[871]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +} st_mtu8_t; + +typedef struct st_ofsm { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDE : 3; + unsigned long : 1; + unsigned long BANKMD : 3; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long BANKMD : 3; + unsigned long : 1; + unsigned long MDE : 3; +#endif + } BIT; + } MDE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long IWDTSTRT : 1; + unsigned long IWDTTOPS : 2; + unsigned long IWDTCKS : 4; + unsigned long IWDTRPES : 2; + unsigned long IWDTRPSS : 2; + unsigned long IWDTRSTIRQS : 1; + unsigned long : 1; + unsigned long IWDTSLCSTP : 1; + unsigned long : 2; + unsigned long WDTSTRT : 1; + unsigned long WDTTOPS : 2; + unsigned long WDTCKS : 4; + unsigned long WDTRPES : 2; + unsigned long WDTRPSS : 2; + unsigned long WDTRSTIRQS : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WDTRSTIRQS : 1; + unsigned long WDTRPSS : 2; + unsigned long WDTRPES : 2; + unsigned long WDTCKS : 4; + unsigned long WDTTOPS : 2; + unsigned long WDTSTRT : 1; + unsigned long : 2; + unsigned long IWDTSLCSTP : 1; + unsigned long : 1; + unsigned long IWDTRSTIRQS : 1; + unsigned long IWDTRPSS : 2; + unsigned long IWDTRPES : 2; + unsigned long IWDTCKS : 4; + unsigned long IWDTTOPS : 2; + unsigned long IWDTSTRT : 1; + unsigned long : 1; +#endif + } BIT; + } OFS0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VDSEL : 2; + unsigned long LVDAS : 1; + unsigned long : 5; + unsigned long HOCOEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long HOCOEN : 1; + unsigned long : 5; + unsigned long LVDAS : 1; + unsigned long VDSEL : 2; +#endif + } BIT; + } OFS1; + char wk0[4]; + unsigned long TMINF; + char wk1[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BANKSWP : 3; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long BANKSWP : 3; +#endif + } BIT; + } BANKSEL; + char wk2[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 27; + unsigned long SPE : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long SPE : 1; + unsigned long : 27; +#endif + } BIT; + } SPCC; + char wk3[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 24; + unsigned long TMEF : 3; + unsigned long : 1; + unsigned long TMEFDB : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TMEFDB : 3; + unsigned long : 1; + unsigned long TMEF : 3; + unsigned long : 24; +#endif + } BIT; + } TMEF; + char wk4[4]; + union { + struct { + unsigned long ID4:8; + unsigned long ID3:8; + unsigned long ID2:8; + unsigned long ID1:8; + unsigned long ID8:8; + unsigned long ID7:8; + unsigned long ID6:8; + unsigned long ID5:8; + unsigned long ID12:8; + unsigned long ID11:8; + unsigned long ID10:8; + unsigned long ID9:8; + unsigned long ID16:8; + unsigned long ID15:8; + unsigned long ID14:8; + unsigned long ID13:8; + } BIT; + } OSIS; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FAWS : 12; + unsigned long : 3; + unsigned long FSPR : 1; + unsigned long FAWE : 12; + unsigned long : 3; + unsigned long BTFLG : 1; +#else + unsigned long BTFLG : 1; + unsigned long : 3; + unsigned long FAWE : 12; + unsigned long FSPR : 1; + unsigned long : 3; + unsigned long FAWS : 12; +#endif + } BIT; + } FAW; + char wk6[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CODE : 32; +#else + unsigned long CODE : 32; +#endif + } BIT; + } ROMCODE; +} st_ofsm_t; + +typedef struct st_pdc { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKE : 1; + unsigned long VPS : 1; + unsigned long HPS : 1; + unsigned long PRST : 1; + unsigned long DFIE : 1; + unsigned long FEIE : 1; + unsigned long OVIE : 1; + unsigned long UDRIE : 1; + unsigned long VERIE : 1; + unsigned long HERIE : 1; + unsigned long PCKOE : 1; + unsigned long PCKDIV : 3; + unsigned long EDS : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long EDS : 1; + unsigned long PCKDIV : 3; + unsigned long PCKOE : 1; + unsigned long HERIE : 1; + unsigned long VERIE : 1; + unsigned long UDRIE : 1; + unsigned long OVIE : 1; + unsigned long FEIE : 1; + unsigned long DFIE : 1; + unsigned long PRST : 1; + unsigned long HPS : 1; + unsigned long VPS : 1; + unsigned long PCKE : 1; +#endif + } BIT; + } PCCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCE : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long PCE : 1; +#endif + } BIT; + } PCCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBSY : 1; + unsigned long FEMPF : 1; + unsigned long FEF : 1; + unsigned long OVRF : 1; + unsigned long UDRF : 1; + unsigned long VERF : 1; + unsigned long HERF : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long HERF : 1; + unsigned long VERF : 1; + unsigned long UDRF : 1; + unsigned long OVRF : 1; + unsigned long FEF : 1; + unsigned long FEMPF : 1; + unsigned long FBSY : 1; +#endif + } BIT; + } PCSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VSYNC : 1; + unsigned long HSYNC : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long HSYNC : 1; + unsigned long VSYNC : 1; +#endif + } BIT; + } PCMONR; + union { + unsigned long LONG; + } PCDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VST : 12; + unsigned long : 4; + unsigned long VSZ : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long VSZ : 12; + unsigned long : 4; + unsigned long VST : 12; +#endif + } BIT; + } VCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HST : 12; + unsigned long : 4; + unsigned long HSZ : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long HSZ : 12; + unsigned long : 4; + unsigned long HST : 12; +#endif + } BIT; + } HCR; +} st_pdc_t; + +typedef struct st_pmgi { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long PSMCS : 6; + unsigned long : 1; + unsigned long PSMDP : 1; + unsigned long PSMHT : 3; + unsigned long : 1; + unsigned long PSMCT : 3; + unsigned long : 9; +#else + unsigned long : 9; + unsigned long PSMCT : 3; + unsigned long : 1; + unsigned long PSMHT : 3; + unsigned long PSMDP : 1; + unsigned long : 1; + unsigned long PSMCS : 6; + unsigned long : 8; +#endif + } BIT; + } PMGCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSME : 1; + unsigned long PSMAD : 1; + unsigned long : 1; + unsigned long PDA : 5; + unsigned long PRA : 5; + unsigned long : 3; + unsigned long PRD : 16; +#else + unsigned long PRD : 16; + unsigned long : 3; + unsigned long PRA : 5; + unsigned long PDA : 5; + unsigned long : 1; + unsigned long PSMAD : 1; + unsigned long PSME : 1; +#endif + } BIT; + } PSMR; +} st_pmgi_t; + +typedef struct st_poe { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short : 6; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short : 6; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE4M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 3; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE4M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE2 : 1; + unsigned short OCE2 : 1; + unsigned short : 5; + unsigned short OSF2 : 1; +#else + unsigned short OSF2 : 1; + unsigned short : 5; + unsigned short OCE2 : 1; + unsigned short OIE2 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE3 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE3 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTUCH34HIZ : 1; + unsigned char MTUCH67HIZ : 1; + unsigned char MTUCH0HIZ : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char MTUCH0HIZ : 1; + unsigned char MTUCH67HIZ : 1; + unsigned char MTUCH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0AZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0DZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MTU0DZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0AZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU7BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU6BDZE : 1; + unsigned short : 5; + unsigned short MTU4BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU3BDZE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short MTU3BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU4BDZE : 1; + unsigned short : 5; + unsigned short MTU6BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU7BDZE : 1; +#endif + } BIT; + } POECR2; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 2; + unsigned short IC2ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC5ADDMT34ZE : 1; + unsigned short : 3; + unsigned short IC1ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC5ADDMT67ZE : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short IC5ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC1ADDMT67ZE : 1; + unsigned short : 3; + unsigned short IC5ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC2ADDMT34ZE : 1; + unsigned short : 2; +#endif + } BIT; + } POECR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short IC5ADDMT0ZE : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short IC5ADDMT0ZE : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short : 1; +#endif + } BIT; + } POECR5; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE10M : 2; + unsigned short : 6; + unsigned short PIE4 : 1; + unsigned short POE10E : 1; + unsigned short : 2; + unsigned short POE10F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE10F : 1; + unsigned short : 2; + unsigned short POE10E : 1; + unsigned short PIE4 : 1; + unsigned short : 6; + unsigned short POE10M : 2; +#endif + } BIT; + } ICSR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE11M : 2; + unsigned short : 6; + unsigned short PIE5 : 1; + unsigned short POE11E : 1; + unsigned short : 2; + unsigned short POE11F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE11F : 1; + unsigned short : 2; + unsigned short POE11E : 1; + unsigned short PIE5 : 1; + unsigned short : 6; + unsigned short POE11M : 2; +#endif + } BIT; + } ICSR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG2B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG2B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif + } BIT; + } ALR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 9; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 9; +#endif + } BIT; + } ICSR6; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0ASEL : 4; + unsigned char M0BSEL : 4; +#else + unsigned char M0BSEL : 4; + unsigned char M0ASEL : 4; +#endif + } BIT; + } M0SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0CSEL : 4; + unsigned char M0DSEL : 4; +#else + unsigned char M0DSEL : 4; + unsigned char M0CSEL : 4; +#endif + } BIT; + } M0SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M3BSEL : 4; + unsigned char M3DSEL : 4; +#else + unsigned char M3DSEL : 4; + unsigned char M3BSEL : 4; +#endif + } BIT; + } M3SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4ASEL : 4; + unsigned char M4CSEL : 4; +#else + unsigned char M4CSEL : 4; + unsigned char M4ASEL : 4; +#endif + } BIT; + } M4SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4BSEL : 4; + unsigned char M4DSEL : 4; +#else + unsigned char M4DSEL : 4; + unsigned char M4BSEL : 4; +#endif + } BIT; + } M4SELR2; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M6BSEL : 4; + unsigned char M6DSEL : 4; +#else + unsigned char M6DSEL : 4; + unsigned char M6BSEL : 4; +#endif + } BIT; + } M6SELR; +} st_poe_t; + +typedef struct st_poeg { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 9; + unsigned long ST : 1; + unsigned long : 11; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long : 11; + unsigned long ST : 1; + unsigned long : 9; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGA; + char wk0[252]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 9; + unsigned long ST : 1; + unsigned long : 11; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long : 11; + unsigned long ST : 1; + unsigned long : 9; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGB; + char wk1[252]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 9; + unsigned long ST : 1; + unsigned long : 11; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long : 11; + unsigned long ST : 1; + unsigned long : 9; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGC; + char wk2[252]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 9; + unsigned long ST : 1; + unsigned long : 11; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long : 11; + unsigned long ST : 1; + unsigned long : 9; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGD; +} st_poeg_t; + +typedef struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 3; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 3; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port0_t; + +typedef struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } DSCR2; +} st_port1_t; + +typedef struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 3; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port2_t; + +typedef struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[103]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port3_t; + +typedef struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port4_t; + +typedef struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port5_t; + +typedef struct st_port6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[103]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port6_t; + +typedef struct st_port7 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port7_t; + +typedef struct st_port8 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[54]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port8_t; + +typedef struct st_port9 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port9_t; + +typedef struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_porta_t; + +typedef struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portb_t; + +typedef struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portc_t; + +typedef struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portd_t; + +typedef struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_porte_t; + +typedef struct st_portf { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[46]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[47]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_portf_t; + +typedef struct st_portg { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[47]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portg_t; + +typedef struct st_porth { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_porth_t; + +typedef struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } ODR1; + char wk4[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portj_t; + +typedef struct st_portk { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portk_t; + +typedef struct st_portl { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portl_t; + +typedef struct st_portm { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portm_t; + +typedef struct st_portn { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[53]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[40]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portn_t; + +typedef struct st_portq { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[54]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[39]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_portq_t; + +typedef struct st_ppg0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0CMS : 2; + unsigned char G1CMS : 2; + unsigned char G2CMS : 2; + unsigned char G3CMS : 2; +#else + unsigned char G3CMS : 2; + unsigned char G2CMS : 2; + unsigned char G1CMS : 2; + unsigned char G0CMS : 2; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0NOV : 1; + unsigned char G1NOV : 1; + unsigned char G2NOV : 1; + unsigned char G3NOV : 1; + unsigned char G0INV : 1; + unsigned char G1INV : 1; + unsigned char G2INV : 1; + unsigned char G3INV : 1; +#else + unsigned char G3INV : 1; + unsigned char G2INV : 1; + unsigned char G1INV : 1; + unsigned char G0INV : 1; + unsigned char G3NOV : 1; + unsigned char G2NOV : 1; + unsigned char G1NOV : 1; + unsigned char G0NOV : 1; +#endif + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER8 : 1; + unsigned char NDER9 : 1; + unsigned char NDER10 : 1; + unsigned char NDER11 : 1; + unsigned char NDER12 : 1; + unsigned char NDER13 : 1; + unsigned char NDER14 : 1; + unsigned char NDER15 : 1; +#else + unsigned char NDER15 : 1; + unsigned char NDER14 : 1; + unsigned char NDER13 : 1; + unsigned char NDER12 : 1; + unsigned char NDER11 : 1; + unsigned char NDER10 : 1; + unsigned char NDER9 : 1; + unsigned char NDER8 : 1; +#endif + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER0 : 1; + unsigned char NDER1 : 1; + unsigned char NDER2 : 1; + unsigned char NDER3 : 1; + unsigned char NDER4 : 1; + unsigned char NDER5 : 1; + unsigned char NDER6 : 1; + unsigned char NDER7 : 1; +#else + unsigned char NDER7 : 1; + unsigned char NDER6 : 1; + unsigned char NDER5 : 1; + unsigned char NDER4 : 1; + unsigned char NDER3 : 1; + unsigned char NDER2 : 1; + unsigned char NDER1 : 1; + unsigned char NDER0 : 1; +#endif + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD8 : 1; + unsigned char POD9 : 1; + unsigned char POD10 : 1; + unsigned char POD11 : 1; + unsigned char POD12 : 1; + unsigned char POD13 : 1; + unsigned char POD14 : 1; + unsigned char POD15 : 1; +#else + unsigned char POD15 : 1; + unsigned char POD14 : 1; + unsigned char POD13 : 1; + unsigned char POD12 : 1; + unsigned char POD11 : 1; + unsigned char POD10 : 1; + unsigned char POD9 : 1; + unsigned char POD8 : 1; +#endif + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD0 : 1; + unsigned char POD1 : 1; + unsigned char POD2 : 1; + unsigned char POD3 : 1; + unsigned char POD4 : 1; + unsigned char POD5 : 1; + unsigned char POD6 : 1; + unsigned char POD7 : 1; +#else + unsigned char POD7 : 1; + unsigned char POD6 : 1; + unsigned char POD5 : 1; + unsigned char POD4 : 1; + unsigned char POD3 : 1; + unsigned char POD2 : 1; + unsigned char POD1 : 1; + unsigned char POD0 : 1; +#endif + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR8 : 1; + unsigned char NDR9 : 1; + unsigned char NDR10 : 1; + unsigned char NDR11 : 1; + unsigned char NDR12 : 1; + unsigned char NDR13 : 1; + unsigned char NDR14 : 1; + unsigned char NDR15 : 1; +#else + unsigned char NDR15 : 1; + unsigned char NDR14 : 1; + unsigned char NDR13 : 1; + unsigned char NDR12 : 1; + unsigned char NDR11 : 1; + unsigned char NDR10 : 1; + unsigned char NDR9 : 1; + unsigned char NDR8 : 1; +#endif + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR0 : 1; + unsigned char NDR1 : 1; + unsigned char NDR2 : 1; + unsigned char NDR3 : 1; + unsigned char NDR4 : 1; + unsigned char NDR5 : 1; + unsigned char NDR6 : 1; + unsigned char NDR7 : 1; +#else + unsigned char NDR7 : 1; + unsigned char NDR6 : 1; + unsigned char NDR5 : 1; + unsigned char NDR4 : 1; + unsigned char NDR3 : 1; + unsigned char NDR2 : 1; + unsigned char NDR1 : 1; + unsigned char NDR0 : 1; +#endif + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR8 : 1; + unsigned char NDR9 : 1; + unsigned char NDR10 : 1; + unsigned char NDR11 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR11 : 1; + unsigned char NDR10 : 1; + unsigned char NDR9 : 1; + unsigned char NDR8 : 1; +#endif + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR0 : 1; + unsigned char NDR1 : 1; + unsigned char NDR2 : 1; + unsigned char NDR3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR3 : 1; + unsigned char NDR2 : 1; + unsigned char NDR1 : 1; + unsigned char NDR0 : 1; +#endif + } BIT; + } NDRL2; +} st_ppg0_t; + +typedef struct st_ppg1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PTRSL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PTRSL : 1; +#endif + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0CMS : 2; + unsigned char G1CMS : 2; + unsigned char G2CMS : 2; + unsigned char G3CMS : 2; +#else + unsigned char G3CMS : 2; + unsigned char G2CMS : 2; + unsigned char G1CMS : 2; + unsigned char G0CMS : 2; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0NOV : 1; + unsigned char G1NOV : 1; + unsigned char G2NOV : 1; + unsigned char G3NOV : 1; + unsigned char G0INV : 1; + unsigned char G1INV : 1; + unsigned char G2INV : 1; + unsigned char G3INV : 1; +#else + unsigned char G3INV : 1; + unsigned char G2INV : 1; + unsigned char G1INV : 1; + unsigned char G0INV : 1; + unsigned char G3NOV : 1; + unsigned char G2NOV : 1; + unsigned char G1NOV : 1; + unsigned char G0NOV : 1; +#endif + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER24 : 1; + unsigned char NDER25 : 1; + unsigned char NDER26 : 1; + unsigned char NDER27 : 1; + unsigned char NDER28 : 1; + unsigned char NDER29 : 1; + unsigned char NDER30 : 1; + unsigned char NDER31 : 1; +#else + unsigned char NDER31 : 1; + unsigned char NDER30 : 1; + unsigned char NDER29 : 1; + unsigned char NDER28 : 1; + unsigned char NDER27 : 1; + unsigned char NDER26 : 1; + unsigned char NDER25 : 1; + unsigned char NDER24 : 1; +#endif + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER16 : 1; + unsigned char NDER17 : 1; + unsigned char NDER18 : 1; + unsigned char NDER19 : 1; + unsigned char NDER20 : 1; + unsigned char NDER21 : 1; + unsigned char NDER22 : 1; + unsigned char NDER23 : 1; +#else + unsigned char NDER23 : 1; + unsigned char NDER22 : 1; + unsigned char NDER21 : 1; + unsigned char NDER20 : 1; + unsigned char NDER19 : 1; + unsigned char NDER18 : 1; + unsigned char NDER17 : 1; + unsigned char NDER16 : 1; +#endif + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD24 : 1; + unsigned char POD25 : 1; + unsigned char POD26 : 1; + unsigned char POD27 : 1; + unsigned char POD28 : 1; + unsigned char POD29 : 1; + unsigned char POD30 : 1; + unsigned char POD31 : 1; +#else + unsigned char POD31 : 1; + unsigned char POD30 : 1; + unsigned char POD29 : 1; + unsigned char POD28 : 1; + unsigned char POD27 : 1; + unsigned char POD26 : 1; + unsigned char POD25 : 1; + unsigned char POD24 : 1; +#endif + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD16 : 1; + unsigned char POD17 : 1; + unsigned char POD18 : 1; + unsigned char POD19 : 1; + unsigned char POD20 : 1; + unsigned char POD21 : 1; + unsigned char POD22 : 1; + unsigned char POD23 : 1; +#else + unsigned char POD23 : 1; + unsigned char POD22 : 1; + unsigned char POD21 : 1; + unsigned char POD20 : 1; + unsigned char POD19 : 1; + unsigned char POD18 : 1; + unsigned char POD17 : 1; + unsigned char POD16 : 1; +#endif + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR24 : 1; + unsigned char NDR25 : 1; + unsigned char NDR26 : 1; + unsigned char NDR27 : 1; + unsigned char NDR28 : 1; + unsigned char NDR29 : 1; + unsigned char NDR30 : 1; + unsigned char NDR31 : 1; +#else + unsigned char NDR31 : 1; + unsigned char NDR30 : 1; + unsigned char NDR29 : 1; + unsigned char NDR28 : 1; + unsigned char NDR27 : 1; + unsigned char NDR26 : 1; + unsigned char NDR25 : 1; + unsigned char NDR24 : 1; +#endif + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR16 : 1; + unsigned char NDR17 : 1; + unsigned char NDR18 : 1; + unsigned char NDR19 : 1; + unsigned char NDR20 : 1; + unsigned char NDR21 : 1; + unsigned char NDR22 : 1; + unsigned char NDR23 : 1; +#else + unsigned char NDR23 : 1; + unsigned char NDR22 : 1; + unsigned char NDR21 : 1; + unsigned char NDR20 : 1; + unsigned char NDR19 : 1; + unsigned char NDR18 : 1; + unsigned char NDR17 : 1; + unsigned char NDR16 : 1; +#endif + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR24 : 1; + unsigned char NDR25 : 1; + unsigned char NDR26 : 1; + unsigned char NDR27 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR27 : 1; + unsigned char NDR26 : 1; + unsigned char NDR25 : 1; + unsigned char NDR24 : 1; +#endif + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR16 : 1; + unsigned char NDR17 : 1; + unsigned char NDR18 : 1; + unsigned char NDR19 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR19 : 1; + unsigned char NDR18 : 1; + unsigned char NDR17 : 1; + unsigned char NDR16 : 1; +#endif + } BIT; + } NDRL2; +} st_ppg1_t; + +typedef struct st_ptpedmac { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SWR : 1; + unsigned long : 3; + unsigned long DL : 2; + unsigned long DE : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long DE : 1; + unsigned long DL : 2; + unsigned long : 3; + unsigned long SWR : 1; +#endif + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long TR : 1; +#endif + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RR : 1; +#endif + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TYPE : 4; + unsigned long PVER : 1; + unsigned long : 2; + unsigned long RPORT : 1; + unsigned long MACE : 1; + unsigned long : 7; + unsigned long RFOF : 1; + unsigned long RDE : 1; + unsigned long FR : 1; + unsigned long TFUF : 1; + unsigned long TDE : 1; + unsigned long TC : 1; + unsigned long : 2; + unsigned long RFCOF : 1; + unsigned long : 1; + unsigned long TABT : 1; + unsigned long : 3; + unsigned long TWB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWB : 1; + unsigned long : 3; + unsigned long TABT : 1; + unsigned long : 1; + unsigned long RFCOF : 1; + unsigned long : 2; + unsigned long TC : 1; + unsigned long TDE : 1; + unsigned long TFUF : 1; + unsigned long FR : 1; + unsigned long RDE : 1; + unsigned long RFOF : 1; + unsigned long : 7; + unsigned long MACE : 1; + unsigned long RPORT : 1; + unsigned long : 2; + unsigned long PVER : 1; + unsigned long TYPE : 4; +#endif + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long PVERIP : 1; + unsigned long : 2; + unsigned long RPORTIP : 1; + unsigned long MACEIP : 1; + unsigned long : 7; + unsigned long RFOFIP : 1; + unsigned long RDEIP : 1; + unsigned long FRIP : 1; + unsigned long TFUFIP : 1; + unsigned long TDEIP : 1; + unsigned long TCIP : 1; + unsigned long : 2; + unsigned long RFCOFIP : 1; + unsigned long : 1; + unsigned long TABTIP : 1; + unsigned long : 3; + unsigned long TWBIP : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWBIP : 1; + unsigned long : 3; + unsigned long TABTIP : 1; + unsigned long : 1; + unsigned long RFCOFIP : 1; + unsigned long : 2; + unsigned long TCIP : 1; + unsigned long TDEIP : 1; + unsigned long TFUFIP : 1; + unsigned long FRIP : 1; + unsigned long RDEIP : 1; + unsigned long RFOFIP : 1; + unsigned long : 7; + unsigned long MACEIP : 1; + unsigned long RPORTIP : 1; + unsigned long : 2; + unsigned long PVERIP : 1; + unsigned long : 4; +#endif + } BIT; + } EESIPR; + char wk6[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MFC : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MFC : 16; +#endif + } BIT; + } RMFCR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TFT : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long TFT : 11; +#endif + } BIT; + } TFTR; + char wk8[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFD : 5; + unsigned long : 3; + unsigned long TFD : 5; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long TFD : 5; + unsigned long : 3; + unsigned long RFD : 5; +#endif + } BIT; + } FDR; + char wk9[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RNR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RNR : 1; +#endif + } BIT; + } RMCR; + char wk10[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UNDER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long UNDER : 16; +#endif + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long OVER : 16; +#endif + } BIT; + } RFOCR; + char wk11[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDO : 3; + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; + unsigned long RFDO : 3; +#endif + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PADR : 6; + unsigned long : 10; + unsigned long PADS : 2; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long PADS : 2; + unsigned long : 10; + unsigned long PADR : 6; +#endif + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TIS : 1; + unsigned long : 3; + unsigned long TIM : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long TIM : 1; + unsigned long : 3; + unsigned long TIS : 1; +#endif + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_ptpedmac_t; + +typedef struct st_qspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SPSSLIE : 1; + unsigned char : 1; + unsigned char MSTR : 1; + unsigned char : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char : 1; + unsigned char MSTR : 1; + unsigned char : 1; + unsigned char SPSSLIE : 1; + unsigned char : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSLP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SSLP : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char IO2FV : 1; + unsigned char IO3FV : 1; + unsigned char : 1; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 1; + unsigned char IO3FV : 1; + unsigned char IO2FV : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char SPSSLF : 1; + unsigned char SPTEF : 1; + unsigned char TREND : 1; + unsigned char SPRFF : 1; +#else + unsigned char SPRFF : 1; + unsigned char TREND : 1; + unsigned char SPTEF : 1; + unsigned char SPSSLF : 1; + unsigned char : 4; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SPSC : 2; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SPSS : 2; +#endif + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPBR0 : 1; + unsigned char SPBR1 : 1; + unsigned char SPBR2 : 1; + unsigned char SPBR3 : 1; + unsigned char SPBR4 : 1; + unsigned char SPBR5 : 1; + unsigned char SPBR6 : 1; + unsigned char SPBR7 : 1; +#else + unsigned char SPBR7 : 1; + unsigned char SPBR6 : 1; + unsigned char SPBR5 : 1; + unsigned char SPBR4 : 1; + unsigned char SPBR3 : 1; + unsigned char SPBR2 : 1; + unsigned char SPBR1 : 1; + unsigned char SPBR0 : 1; +#endif + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TXDMY : 1; +#else + unsigned char TXDMY : 1; + unsigned char : 7; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXTRG : 3; + unsigned char TXTRGEX : 1; + unsigned char TXTRG : 2; + unsigned char RXRST : 1; + unsigned char TXRST : 1; +#else + unsigned char TXRST : 1; + unsigned char RXRST : 1; + unsigned char TXTRG : 2; + unsigned char TXTRGEX : 1; + unsigned char RXTRG : 3; +#endif + } BIT; + } SPBFCR; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RXBC : 6; + unsigned short : 2; + unsigned short TXBC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TXBC : 6; + unsigned short : 2; + unsigned short RXBC : 6; +#endif + } BIT; + } SPBDCR; + unsigned long SPBMUL0; + unsigned long SPBMUL1; + unsigned long SPBMUL2; + unsigned long SPBMUL3; +} st_qspi_t; + +typedef struct st_ram { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMMODE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RAMMODE : 2; +#endif + } BIT; + } RAMMODE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RAMERR : 1; +#endif + } BIT; + } RAMSTS; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMPRCR : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char RAMPRCR : 1; +#endif + } BIT; + } RAMPRCR; + char wk1[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long READ : 16; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long READ : 16; + unsigned long : 3; +#endif + } BIT; + } RAMECAD; + char wk2[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXRAMMODE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char EXRAMMODE : 2; +#endif + } BIT; + } EXRAMMODE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXRAMERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXRAMERR : 1; +#endif + } BIT; + } EXRAMSTS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXRAMPRCR : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char EXRAMPRCR : 1; +#endif + } BIT; + } EXRAMPRCR; + char wk4[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long READ : 16; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long READ : 16; + unsigned long : 3; +#endif + } BIT; + } EXRAMECAD; +} st_ram_t; + +typedef struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char FMPE : 1; +#else + unsigned char FMPE : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +} st_riic_t; + +typedef struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char UDRF : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char UDRF : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char SPBYT : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPBYT : 1; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BYSW : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BYSW : 1; +#endif + } BIT; + } SPDCR2; +} st_rspi_t; + +typedef struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT1; + }; + char wk2[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT2; + }; + char wk3[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT3; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT0AR; + }; + char wk7[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT1AR; + }; + char wk8[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT2AR; + }; + char wk9[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT3AR; + }; + char wk10[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT0AER; + }; + char wk11[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT1AER; + }; + char wk12[1]; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif + } BIT; + } BCNT2AER; + }; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT3AER; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif + } BIT; + } RCR3; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RCKSEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RCKSEL : 1; +#endif + } BIT; + } RCR4; + char wk17[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RFC : 1; +#endif + } BIT; + } RFRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 16; +#else + unsigned short RFC : 16; +#endif + } BIT; + } RFRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; + char wk18[17]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR2; + char wk21[13]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif + } BIT; + } BCNT0CP0; + }; + char wk22[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif + } BIT; + } BCNT1CP0; + }; + char wk23[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif + } BIT; + } BCNT2CP0; + }; + char wk24[3]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif + } BIT; + } BCNT3CP0; + }; + char wk25[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP0; + char wk26[5]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif + } BIT; + } BCNT0CP1; + }; + char wk27[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif + } BIT; + } BCNT1CP1; + }; + char wk28[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif + } BIT; + } BCNT2CP1; + }; + char wk29[3]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif + } BIT; + } BCNT3CP1; + }; + char wk30[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP1; + char wk31[5]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif + } BIT; + } BCNT0CP2; + }; + char wk32[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif + } BIT; + } BCNT1CP2; + }; + char wk33[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif + } BIT; + } BCNT2CP2; + }; + char wk34[3]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif + } BIT; + } BCNT3CP2; + }; + char wk35[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP2; +} st_rtc_t; + +typedef struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ADPRC : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short ADPRC : 2; + unsigned short : 1; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + char wk5[2]; + union { + unsigned short WORD; + } ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk7[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PRO : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PRO : 2; +#endif + } BIT; + } ADSAMPR; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SSTSH : 8; + unsigned short SHANS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SHANS : 3; + unsigned short SSTSH : 8; +#endif + } BIT; + } ADSHCR; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short SAM : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short SAM : 1; + unsigned short : 5; +#endif + } BIT; + } ADSAM; + char wk10[10]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHMD : 1; +#endif + } BIT; + } ADSHMSR; + char wk12[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk13[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk14[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk15[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + char wk16[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + char wk17[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + char wk18[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + char wk19[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk20[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk21[39]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSC007 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif + } BIT; + } ADANSC0; + char wk22[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif + } BIT; + } ADGCTRGR; + char wk23[6]; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +} st_s12ad_t; + +typedef struct st_s12ad1 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA008 : 1; + unsigned short ANSA009 : 1; + unsigned short ANSA010 : 1; + unsigned short ANSA011 : 1; + unsigned short ANSA012 : 1; + unsigned short ANSA013 : 1; + unsigned short ANSA014 : 1; + unsigned short ANSA015 : 1; +#else + unsigned short ANSA015 : 1; + unsigned short ANSA014 : 1; + unsigned short ANSA013 : 1; + unsigned short ANSA012 : 1; + unsigned short ANSA011 : 1; + unsigned short ANSA010 : 1; + unsigned short ANSA009 : 1; + unsigned short ANSA008 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSA104 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short ADS008 : 1; + unsigned short ADS009 : 1; + unsigned short ADS010 : 1; + unsigned short ADS011 : 1; + unsigned short ADS012 : 1; + unsigned short ADS013 : 1; + unsigned short ADS014 : 1; + unsigned short ADS015 : 1; +#else + unsigned short ADS015 : 1; + unsigned short ADS014 : 1; + unsigned short ADS013 : 1; + unsigned short ADS012 : 1; + unsigned short ADS011 : 1; + unsigned short ADS010 : 1; + unsigned short ADS009 : 1; + unsigned short ADS008 : 1; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short ADS102 : 1; + unsigned short ADS103 : 1; + unsigned short ADS104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ADS104 : 1; + unsigned short ADS103 : 1; + unsigned short ADS102 : 1; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ADPRC : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short ADPRC : 2; + unsigned short : 1; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short TSSB : 1; + unsigned short OCSB : 1; + unsigned short : 1; + unsigned short EXSEL : 2; + unsigned short EXOEN : 1; +#else + unsigned short EXOEN : 1; + unsigned short EXSEL : 2; + unsigned short : 1; + unsigned short OCSB : 1; + unsigned short TSSB : 1; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB008 : 1; + unsigned short ANSB009 : 1; + unsigned short ANSB010 : 1; + unsigned short ANSB011 : 1; + unsigned short ANSB012 : 1; + unsigned short ANSB013 : 1; + unsigned short ANSB014 : 1; + unsigned short ANSB015 : 1; +#else + unsigned short ANSB015 : 1; + unsigned short ANSB014 : 1; + unsigned short ANSB013 : 1; + unsigned short ANSB012 : 1; + unsigned short ANSB011 : 1; + unsigned short ANSB010 : 1; + unsigned short ANSB009 : 1; + unsigned short ANSB008 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSB104 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk2[25]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PRO : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PRO : 2; +#endif + } BIT; + } ADSAMPR; + char wk3[10]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short SAM : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short SAM : 1; + unsigned short : 5; +#endif + } BIT; + } ADSAM; + char wk4[10]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk5[5]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk8[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTS : 1; + unsigned char CMPSOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSOC : 1; + unsigned char CMPSTS : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTS : 1; + unsigned char CMPLOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOC : 1; + unsigned char CMPLTS : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA009 : 1; + unsigned short CMPCHA010 : 1; + unsigned short CMPCHA011 : 1; + unsigned short CMPCHA012 : 1; + unsigned short CMPCHA013 : 1; + unsigned short CMPCHA014 : 1; + unsigned short CMPCHA015 : 1; +#else + unsigned short CMPCHA015 : 1; + unsigned short CMPCHA014 : 1; + unsigned short CMPCHA013 : 1; + unsigned short CMPCHA012 : 1; + unsigned short CMPCHA011 : 1; + unsigned short CMPCHA010 : 1; + unsigned short CMPCHA009 : 1; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA009 : 1; + unsigned short CMPLCHA010 : 1; + unsigned short CMPLCHA011 : 1; + unsigned short CMPLCHA012 : 1; + unsigned short CMPLCHA013 : 1; + unsigned short CMPLCHA014 : 1; + unsigned short CMPLCHA015 : 1; +#else + unsigned short CMPLCHA015 : 1; + unsigned short CMPLCHA014 : 1; + unsigned short CMPLCHA013 : 1; + unsigned short CMPLCHA012 : 1; + unsigned short CMPLCHA011 : 1; + unsigned short CMPLCHA010 : 1; + unsigned short CMPLCHA009 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA009 : 1; + unsigned short CMPSTCHA010 : 1; + unsigned short CMPSTCHA011 : 1; + unsigned short CMPSTCHA012 : 1; + unsigned short CMPSTCHA013 : 1; + unsigned short CMPSTCHA014 : 1; + unsigned short CMPSTCHA015 : 1; +#else + unsigned short CMPSTCHA015 : 1; + unsigned short CMPSTCHA014 : 1; + unsigned short CMPSTCHA013 : 1; + unsigned short CMPSTCHA012 : 1; + unsigned short CMPSTCHA011 : 1; + unsigned short CMPSTCHA010 : 1; + unsigned short CMPSTCHA009 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPFTS : 1; + unsigned char CMPFOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPFOC : 1; + unsigned char CMPFTS : 1; +#endif + } BIT; + } ADCMPSER; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk10[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk11[39]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC007 : 1; + unsigned short ANSC008 : 1; + unsigned short ANSC009 : 1; + unsigned short ANSC010 : 1; + unsigned short ANSC011 : 1; + unsigned short ANSC012 : 1; + unsigned short ANSC013 : 1; + unsigned short ANSC014 : 1; + unsigned short ANSC015 : 1; +#else + unsigned short ANSC015 : 1; + unsigned short ANSC014 : 1; + unsigned short ANSC013 : 1; + unsigned short ANSC012 : 1; + unsigned short ANSC011 : 1; + unsigned short ANSC010 : 1; + unsigned short ANSC009 : 1; + unsigned short ANSC008 : 1; + unsigned short ANSC007 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif + } BIT; + } ADANSC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC100 : 1; + unsigned short ANSC101 : 1; + unsigned short ANSC102 : 1; + unsigned short ANSC103 : 1; + unsigned short ANSC104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSC104 : 1; + unsigned short ANSC103 : 1; + unsigned short ANSC102 : 1; + unsigned short ANSC101 : 1; + unsigned short ANSC100 : 1; +#endif + } BIT; + } ADANSC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSSC : 1; + unsigned char OCSC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char OCSC : 1; + unsigned char TSSC : 1; +#endif + } BIT; + } ADGCEXCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif + } BIT; + } ADGCTRGR; + char wk12[3]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + unsigned char ADSSTR8; + unsigned char ADSSTR9; + unsigned char ADSSTR10; + unsigned char ADSSTR11; + unsigned char ADSSTR12; + unsigned char ADSSTR13; + unsigned char ADSSTR14; + unsigned char ADSSTR15; +} st_s12ad1_t; + +typedef struct st_sci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char ABCSE : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char ABCSE : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCMF : 1; + unsigned char : 2; + unsigned char DPER : 1; + unsigned char DFER : 1; + unsigned char : 1; + unsigned char IDSEL : 1; + unsigned char DCME : 1; +#else + unsigned char DCME : 1; + unsigned char IDSEL : 1; + unsigned char : 1; + unsigned char DFER : 1; + unsigned char DPER : 1; + unsigned char : 2; + unsigned char DCMF : 1; +#endif + } BIT; + } DCCR; + char wk0[6]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPD : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPD : 9; +#endif + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXDMON : 1; + unsigned char SPB2DT : 1; + unsigned char SPB2IO : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPB2IO : 1; + unsigned char SPB2DT : 1; + unsigned char RXDMON : 1; +#endif + } BIT; + } SPTR; +} st_sci0_t; + +typedef struct st_sci7 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DR : 1; + unsigned char : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDF : 1; + unsigned char TDFE : 1; +#else + unsigned char TDFE : 1; + unsigned char RDF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char : 1; + unsigned char DR : 1; +#endif + } BIT; + } SSRFIFO; + }; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char ABCSE : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char ABCSE : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TDAT : 9; + unsigned short MPBT : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short MPBT : 1; + unsigned short TDAT : 9; +#endif + } BIT; + } FTDR; + }; + union { + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDAT : 9; + unsigned short MPB : 1; + unsigned short DR : 1; + unsigned short PER : 1; + unsigned short FER : 1; + unsigned short ORER : 1; + unsigned short RDF : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short RDF : 1; + unsigned short ORER : 1; + unsigned short FER : 1; + unsigned short PER : 1; + unsigned short DR : 1; + unsigned short MPB : 1; + unsigned short RDAT : 9; +#endif + } BIT; + } FRDR; + }; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCMF : 1; + unsigned char : 2; + unsigned char DPER : 1; + unsigned char DFER : 1; + unsigned char : 1; + unsigned char IDSEL : 1; + unsigned char DCME : 1; +#else + unsigned char DCME : 1; + unsigned char IDSEL : 1; + unsigned char : 1; + unsigned char DFER : 1; + unsigned char DPER : 1; + unsigned char : 2; + unsigned char DCMF : 1; +#endif + } BIT; + } DCCR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FM : 1; + unsigned short RFRST : 1; + unsigned short TFRST : 1; + unsigned short DRES : 1; + unsigned short TTRG : 4; + unsigned short RTRG : 4; + unsigned short RSTRG : 4; +#else + unsigned short RSTRG : 4; + unsigned short RTRG : 4; + unsigned short TTRG : 4; + unsigned short DRES : 1; + unsigned short TFRST : 1; + unsigned short RFRST : 1; + unsigned short FM : 1; +#endif + } BIT; + } FCR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short R : 5; + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; + unsigned short R : 5; +#endif + } BIT; + } FDR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ORER : 1; + unsigned short : 1; + unsigned short FNUM : 5; + unsigned short : 1; + unsigned short PNUM : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short PNUM : 5; + unsigned short : 1; + unsigned short FNUM : 5; + unsigned short : 1; + unsigned short ORER : 1; +#endif + } BIT; + } LSR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPD : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPD : 9; +#endif + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXDMON : 1; + unsigned char SPB2DT : 1; + unsigned char SPB2IO : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPB2IO : 1; + unsigned char SPB2DT : 1; + unsigned char RXDMON : 1; +#endif + } BIT; + } SPTR; +} st_sci7_t; + +typedef struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_sdhi { + union { + unsigned long LONG; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned long :16; + unsigned long CMD12AT:2; + unsigned long TRSTP:1; + unsigned long CMDRW:1; + unsigned long CMDTP:1; + unsigned long RSPTP:3; + unsigned long ACMD:2; + unsigned long CMDIDX:6; + } BIT; +#endif + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STP : 1; + unsigned long : 7; + unsigned long SDBLKCNTEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long SDBLKCNTEN : 1; + unsigned long : 7; + unsigned long STP : 1; +#endif + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPEND : 1; + unsigned long : 1; + unsigned long ACEND : 1; + unsigned long SDCDRM : 1; + unsigned long SDCDIN : 1; + unsigned long SDCDMON : 1; + unsigned long : 1; + unsigned long SDWPMON : 1; + unsigned long SDD3RM : 1; + unsigned long SDD3IN : 1; + unsigned long SDD3MON : 1; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long SDD3MON : 1; + unsigned long SDD3IN : 1; + unsigned long SDD3RM : 1; + unsigned long SDWPMON : 1; + unsigned long : 1; + unsigned long SDCDMON : 1; + unsigned long SDCDIN : 1; + unsigned long SDCDRM : 1; + unsigned long ACEND : 1; + unsigned long : 1; + unsigned long RSPEND : 1; +#endif + } BIT; + } SDSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDE : 1; + unsigned long CRCE : 1; + unsigned long ENDE : 1; + unsigned long DTO : 1; + unsigned long ILW : 1; + unsigned long ILR : 1; + unsigned long RSPTO : 1; + unsigned long SDD0MON : 1; + unsigned long BRE : 1; + unsigned long BWE : 1; + unsigned long : 3; + unsigned long SDCLKCREN : 1; + unsigned long CBSY : 1; + unsigned long ILA : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ILA : 1; + unsigned long CBSY : 1; + unsigned long SDCLKCREN : 1; + unsigned long : 3; + unsigned long BWE : 1; + unsigned long BRE : 1; + unsigned long SDD0MON : 1; + unsigned long RSPTO : 1; + unsigned long ILR : 1; + unsigned long ILW : 1; + unsigned long DTO : 1; + unsigned long ENDE : 1; + unsigned long CRCE : 1; + unsigned long CMDE : 1; +#endif + } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPENDM : 1; + unsigned long : 1; + unsigned long ACENDM : 1; + unsigned long SDCDRMM : 1; + unsigned long SDCDINM : 1; + unsigned long : 3; + unsigned long SDD3RMM : 1; + unsigned long SDD3INM : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long SDD3INM : 1; + unsigned long SDD3RMM : 1; + unsigned long : 3; + unsigned long SDCDINM : 1; + unsigned long SDCDRMM : 1; + unsigned long ACENDM : 1; + unsigned long : 1; + unsigned long RSPENDM : 1; +#endif + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDEM : 1; + unsigned long CRCEM : 1; + unsigned long ENDEM : 1; + unsigned long DTTOM : 1; + unsigned long ILWM : 1; + unsigned long ILRM : 1; + unsigned long RSPTOM : 1; + unsigned long : 1; + unsigned long BREM : 1; + unsigned long BWEM : 1; + unsigned long : 5; + unsigned long ILAM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ILAM : 1; + unsigned long : 5; + unsigned long BWEM : 1; + unsigned long BREM : 1; + unsigned long : 1; + unsigned long RSPTOM : 1; + unsigned long ILRM : 1; + unsigned long ILWM : 1; + unsigned long DTTOM : 1; + unsigned long ENDEM : 1; + unsigned long CRCEM : 1; + unsigned long CMDEM : 1; +#endif + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLKSEL : 8; + unsigned long CLKEN : 1; + unsigned long CLKCTRLEN : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long CLKCTRLEN : 1; + unsigned long CLKEN : 1; + unsigned long CLKSEL : 8; +#endif + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LEN : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long LEN : 10; +#endif + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTOP : 4; + unsigned long TOP : 4; + unsigned long : 7; + unsigned long WIDTH : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long WIDTH : 1; + unsigned long : 7; + unsigned long TOP : 4; + unsigned long CTOP : 4; +#endif + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDE0 : 1; + unsigned long CMDE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long RSPLENE1 : 1; + unsigned long RDLENE : 1; + unsigned long CRCLENE : 1; + unsigned long : 2; + unsigned long RSPCRCE0 : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RDCRCE : 1; + unsigned long CRCTKE : 1; + unsigned long CRCTK : 3; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long CRCTK : 3; + unsigned long CRCTKE : 1; + unsigned long RDCRCE : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RSPCRCE0 : 1; + unsigned long : 2; + unsigned long CRCLENE : 1; + unsigned long RDLENE : 1; + unsigned long RSPLENE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long CMDE1 : 1; + unsigned long CMDE0 : 1; +#endif + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long BSYTO1 : 1; + unsigned long RDTO : 1; + unsigned long CRCTO : 1; + unsigned long CRCBSYTO : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long CRCBSYTO : 1; + unsigned long CRCTO : 1; + unsigned long RDTO : 1; + unsigned long BSYTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long RSPTO0 : 1; +#endif + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INTEN : 1; + unsigned long : 1; + unsigned long RWREQ : 1; + unsigned long : 5; + unsigned long IOABT : 1; + unsigned long C52PUB : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long C52PUB : 1; + unsigned long IOABT : 1; + unsigned long : 5; + unsigned long RWREQ : 1; + unsigned long : 1; + unsigned long INTEN : 1; +#endif + } BIT; + } SDIOMD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IOIRQ : 1; + unsigned long : 13; + unsigned long EXPUB52 : 1; + unsigned long EXWT : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EXWT : 1; + unsigned long EXPUB52 : 1; + unsigned long : 13; + unsigned long IOIRQ : 1; +#endif + } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IOIRQM : 1; + unsigned long : 13; + unsigned long EXPUB52M : 1; + unsigned long EXWTM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EXWTM : 1; + unsigned long EXPUB52M : 1; + unsigned long : 13; + unsigned long IOIRQM : 1; +#endif + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long DMAEN : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long DMAEN : 1; + unsigned long : 1; +#endif + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SDRST : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SDRST : 1; +#endif + } BIT; + } SDRST; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IP1 : 8; + unsigned long IP2 : 4; + unsigned long : 2; + unsigned long CLKRAT : 1; + unsigned long CPRM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CPRM : 1; + unsigned long CLKRAT : 1; + unsigned long : 2; + unsigned long IP2 : 4; + unsigned long IP1 : 8; +#endif + } BIT; + } SDVER; + char wk10[24]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long BWSWP : 1; + unsigned long BRSWP : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long BRSWP : 1; + unsigned long BWSWP : 1; + unsigned long : 6; +#endif + } BIT; + } SDSWAP; +} st_sdhi_t; + +typedef struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; +} st_smci_t; + +typedef struct st_ssie { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REN : 1; + unsigned long TEN : 1; + unsigned long : 1; + unsigned long MUEN : 1; + unsigned long CKDV : 4; + unsigned long DEL : 1; + unsigned long PDTA : 1; + unsigned long SDTA : 1; + unsigned long SPDP : 1; + unsigned long LRCKP : 1; + unsigned long BCKP : 1; + unsigned long MST : 1; + unsigned long : 1; + unsigned long SWL : 3; + unsigned long DWL : 3; + unsigned long FRM : 2; + unsigned long : 1; + unsigned long IIEN : 1; + unsigned long ROIEN : 1; + unsigned long RUIEN : 1; + unsigned long TOIEN : 1; + unsigned long TUIEN : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TUIEN : 1; + unsigned long TOIEN : 1; + unsigned long RUIEN : 1; + unsigned long ROIEN : 1; + unsigned long IIEN : 1; + unsigned long : 1; + unsigned long FRM : 2; + unsigned long DWL : 3; + unsigned long SWL : 3; + unsigned long : 1; + unsigned long MST : 1; + unsigned long BCKP : 1; + unsigned long LRCKP : 1; + unsigned long SPDP : 1; + unsigned long SDTA : 1; + unsigned long PDTA : 1; + unsigned long DEL : 1; + unsigned long CKDV : 4; + unsigned long MUEN : 1; + unsigned long : 1; + unsigned long TEN : 1; + unsigned long REN : 1; +#endif + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 25; + unsigned long IIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long TUIRQ : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long IIRQ : 1; + unsigned long : 25; +#endif + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFRST : 1; + unsigned long TFRST : 1; + unsigned long RIE : 1; + unsigned long TIE : 1; + unsigned long : 7; + unsigned long BSW : 1; + unsigned long : 4; + unsigned long SSIRST : 1; + unsigned long : 14; + unsigned long AUCKE : 1; +#else + unsigned long AUCKE : 1; + unsigned long : 14; + unsigned long SSIRST : 1; + unsigned long : 4; + unsigned long BSW : 1; + unsigned long : 7; + unsigned long TIE : 1; + unsigned long RIE : 1; + unsigned long TFRST : 1; + unsigned long RFRST : 1; +#endif + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDF : 1; + unsigned long : 7; + unsigned long RDC : 6; + unsigned long : 2; + unsigned long TDE : 1; + unsigned long : 7; + unsigned long TDC : 6; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TDC : 6; + unsigned long : 7; + unsigned long TDE : 1; + unsigned long : 2; + unsigned long RDC : 6; + unsigned long : 7; + unsigned long RDF : 1; +#endif + } BIT; + } SSIFSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SSIFTDR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SSIFRDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OMOD : 2; + unsigned long : 6; + unsigned long LRCONT : 1; + unsigned long BCKASTP : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long BCKASTP : 1; + unsigned long LRCONT : 1; + unsigned long : 6; + unsigned long OMOD : 2; +#endif + } BIT; + } SSIOFR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDFS : 5; + unsigned long : 3; + unsigned long TDES : 5; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long TDES : 5; + unsigned long : 3; + unsigned long RDFS : 5; +#endif + } BIT; + } SSISCR; +} st_ssie_t; + +typedef struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROME : 1; + unsigned short EXBE : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short EXBE : 1; + unsigned short ROME : 1; +#endif + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 5; + unsigned short ECCRAME : 1; + unsigned short SBYRAME : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short SBYRAME : 1; + unsigned short ECCRAME : 1; + unsigned short : 5; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 14; + unsigned short OPE : 1; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short OPE : 1; + unsigned short : 14; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPA0 : 1; + unsigned long MSTPA1 : 1; + unsigned long : 2; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 1; + unsigned long MSTPA7 : 1; + unsigned long : 1; + unsigned long MSTPA9 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA11 : 1; + unsigned long : 1; + unsigned long MSTPA13 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 4; + unsigned long MSTPA24 : 1; + unsigned long : 2; + unsigned long MSTPA27 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA29 : 1; + unsigned long : 1; + unsigned long ACSE : 1; +#else + unsigned long ACSE : 1; + unsigned long : 1; + unsigned long MSTPA29 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA27 : 1; + unsigned long : 2; + unsigned long MSTPA24 : 1; + unsigned long : 4; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA13 : 1; + unsigned long : 1; + unsigned long MSTPA11 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA9 : 1; + unsigned long : 1; + unsigned long MSTPA7 : 1; + unsigned long : 1; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 2; + unsigned long MSTPA1 : 1; + unsigned long MSTPA0 : 1; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long MSTPB1 : 1; + unsigned long MSTPB2 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB8 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 3; + unsigned long MSTPB13 : 1; + unsigned long MSTPB14 : 1; + unsigned long MSTPB15 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long MSTPB20 : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB20 : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB15 : 1; + unsigned long MSTPB14 : 1; + unsigned long MSTPB13 : 1; + unsigned long : 3; + unsigned long MSTPB9 : 1; + unsigned long MSTPB8 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB2 : 1; + unsigned long MSTPB1 : 1; + unsigned long MSTPB0 : 1; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 1; + unsigned long MSTPC2 : 1; + unsigned long : 3; + unsigned long MSTPC6 : 1; + unsigned long MSTPC7 : 1; + unsigned long : 9; + unsigned long MSTPC17 : 1; + unsigned long : 1; + unsigned long MSTPC19 : 1; + unsigned long : 2; + unsigned long MSTPC22 : 1; + unsigned long MSTPC23 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC29 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long MSTPC29 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC23 : 1; + unsigned long MSTPC22 : 1; + unsigned long : 2; + unsigned long MSTPC19 : 1; + unsigned long : 1; + unsigned long MSTPC17 : 1; + unsigned long : 9; + unsigned long MSTPC7 : 1; + unsigned long MSTPC6 : 1; + unsigned long : 3; + unsigned long MSTPC2 : 1; + unsigned long : 1; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPD0 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD7 : 1; + unsigned long : 6; + unsigned long MSTPD14 : 1; + unsigned long MSTPD15 : 1; + unsigned long : 3; + unsigned long MSTPD19 : 1; + unsigned long : 1; + unsigned long MSTPD21 : 1; + unsigned long : 5; + unsigned long MSTPD27 : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long MSTPD27 : 1; + unsigned long : 5; + unsigned long MSTPD21 : 1; + unsigned long : 1; + unsigned long MSTPD19 : 1; + unsigned long : 3; + unsigned long MSTPD15 : 1; + unsigned long MSTPD14 : 1; + unsigned long : 6; + unsigned long MSTPD7 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD0 : 1; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long PCKC : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long BCK : 4; + unsigned long : 2; + unsigned long PSTOP0 : 1; + unsigned long PSTOP1 : 1; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long PSTOP1 : 1; + unsigned long PSTOP0 : 1; + unsigned long : 2; + unsigned long BCK : 4; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long PCKC : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short UCK : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short UCK : 4; + unsigned short : 4; +#endif + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 2; + unsigned short PLLSRCSEL : 1; + unsigned short : 3; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 3; + unsigned short PLLSRCSEL : 1; + unsigned short : 2; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk3[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCLKDIV : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCLKDIV : 1; +#endif + } BIT; + } BCKCR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif + } BIT; + } HOCOCR2; + char wk5[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char SOOVF : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char ILCOVF : 1; + unsigned char PPLOVF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PPLOVF : 1; + unsigned char ILCOVF : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char SOOVF : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKOSEL : 3; + unsigned short : 1; + unsigned short CKODIV : 3; + unsigned short CKOSTP : 1; +#else + unsigned short CKOSTP : 1; + unsigned short CKODIV : 3; + unsigned short : 1; + unsigned short CKOSEL : 3; + unsigned short : 8; +#endif + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short OUTCKSEL : 1; + unsigned short : 7; + unsigned short UPLLSEL : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short UPLLSEL : 1; + unsigned short : 7; + unsigned short OUTCKSEL : 1; + unsigned short : 4; +#endif + } BIT; + } PACKCR; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PPLIDIV : 2; + unsigned short : 6; + unsigned short PPLSTC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short PPLSTC : 6; + unsigned short : 6; + unsigned short PPLIDIV : 2; +#endif + } BIT; + } PPLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PPLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PPLLEN : 1; +#endif + } BIT; + } PPLLCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PPLCK : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PPLCK : 4; +#endif + } BIT; + } PPLLCR3; + char wk9[84]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 8; +#else + unsigned char MSTS : 8; +#endif + } BIT; + } MOSCWTCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSTS : 8; +#else + unsigned char SSTS : 8; +#endif + } BIT; + } SOSCWTCR; + char wk10[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk11[1]; + unsigned short SWRR; + char wk12[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk13[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk14[3100]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MEMWAIT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MEMWAIT : 1; +#endif + } BIT; + } MEMWAIT; + char wk15[45667]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEEPCUT : 2; + unsigned char : 4; + unsigned char IOKEEP : 1; + unsigned char DPSBY : 1; +#else + unsigned char DPSBY : 1; + unsigned char IOKEEP : 1; + unsigned char : 4; + unsigned char DEEPCUT : 2; +#endif + } BIT; + } DPSBYCR; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ7E : 1; +#else + unsigned char DIRQ7E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ0E : 1; +#endif + } BIT; + } DPSIER0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ15E : 1; +#else + unsigned char DIRQ15E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ8E : 1; +#endif + } BIT; + } DPSIER1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IE : 1; + unsigned char DLVD2IE : 1; + unsigned char DRTCIIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DNMIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DUSBIE : 1; +#else + unsigned char DUSBIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DNMIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DRTCIIE : 1; + unsigned char DLVD2IE : 1; + unsigned char DLVD1IE : 1; +#endif + } BIT; + } DPSIER2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIE : 1; +#endif + } BIT; + } DPSIER3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ7F : 1; +#else + unsigned char DIRQ7F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ0F : 1; +#endif + } BIT; + } DPSIFR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ15F : 1; +#else + unsigned char DIRQ15F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ8F : 1; +#endif + } BIT; + } DPSIFR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IF : 1; + unsigned char DLVD2IF : 1; + unsigned char DRTCIIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DNMIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DUSBIF : 1; +#else + unsigned char DUSBIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DNMIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DRTCIIF : 1; + unsigned char DLVD2IF : 1; + unsigned char DLVD1IF : 1; +#endif + } BIT; + } DPSIFR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIF : 1; +#endif + } BIT; + } DPSIFR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ7EG : 1; +#else + unsigned char DIRQ7EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ0EG : 1; +#endif + } BIT; + } DPSIEGR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ15EG : 1; +#else + unsigned char DIRQ15EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ8EG : 1; +#endif + } BIT; + } DPSIEGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1EG : 1; + unsigned char DLVD2EG : 1; + unsigned char : 2; + unsigned char DNMIEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DRIICCEG : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DRIICCEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DNMIEG : 1; + unsigned char : 2; + unsigned char DLVD2EG : 1; + unsigned char DLVD1EG : 1; +#endif + } BIT; + } DPSIEGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIEG : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIEG : 1; +#endif + } BIT; + } DPSIEGR3; + char wk17[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 3; + unsigned char DPSRSTF : 1; +#else + unsigned char DPSRSTF : 1; + unsigned char : 3; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk18[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOFXIN : 1; + unsigned char : 3; + unsigned char MODRV2 : 2; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV2 : 2; + unsigned char : 3; + unsigned char MOFXIN : 1; +#endif + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOPCNT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOCOPCNT : 1; +#endif + } BIT; + } HOCOPCR; + char wk19[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 5; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 4; +#else + unsigned char LVD2LVL : 4; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk20[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1FSAMP : 2; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char LVD1FSAMP : 2; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2FSAMP : 2; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char LVD2FSAMP : 2; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; + char wk21[4]; + unsigned char DPSBKR[32]; +} st_system_t; + +typedef struct st_temps { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char TSOE : 1; + unsigned char : 2; + unsigned char TSEN : 1; +#else + unsigned char TSEN : 1; + unsigned char : 2; + unsigned char TSOE : 1; + unsigned char : 4; +#endif + } BIT; + } TSCR; +} st_temps_t; + +typedef struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char ADTE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADTE : 1; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +} st_tmr0_t; + +typedef struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +} st_tmr1_t; + +typedef struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +} st_tmr01_t; + +typedef struct st_tpu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu0_t; + +typedef struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu1_t; + +typedef struct st_tpu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu2_t; + +typedef struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu3_t; + +typedef struct st_tpu4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu4_t; + +typedef struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu5_t; + +typedef struct st_tpua { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST3 : 1; + unsigned char CST4 : 1; + unsigned char CST5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CST5 : 1; + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SYNC5 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; +} st_tpua_t; + +typedef struct st_usb { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRPC0 : 1; + unsigned long RPUE0 : 1; + unsigned long : 1; + unsigned long DRPD0 : 1; + unsigned long FIXPHY0 : 1; + unsigned long : 11; + unsigned long DP0 : 1; + unsigned long DM0 : 1; + unsigned long : 2; + unsigned long DOVCA0 : 1; + unsigned long DOVCB0 : 1; + unsigned long : 1; + unsigned long DVBSTS0 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DVBSTS0 : 1; + unsigned long : 1; + unsigned long DOVCB0 : 1; + unsigned long DOVCA0 : 1; + unsigned long : 2; + unsigned long DM0 : 1; + unsigned long DP0 : 1; + unsigned long : 11; + unsigned long FIXPHY0 : 1; + unsigned long DRPD0 : 1; + unsigned long : 1; + unsigned long RPUE0 : 1; + unsigned long SRPC0 : 1; +#endif + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DPINTE0 : 1; + unsigned long DMINTE0 : 1; + unsigned long : 2; + unsigned long DOVRCRAE0 : 1; + unsigned long DOVRCRBE0 : 1; + unsigned long : 1; + unsigned long DVBSE0 : 1; + unsigned long : 8; + unsigned long DPINT0 : 1; + unsigned long DMINT0 : 1; + unsigned long : 2; + unsigned long DOVRCRA0 : 1; + unsigned long DOVRCRB0 : 1; + unsigned long : 1; + unsigned long DVBINT0 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DVBINT0 : 1; + unsigned long : 1; + unsigned long DOVRCRB0 : 1; + unsigned long DOVRCRA0 : 1; + unsigned long : 2; + unsigned long DMINT0 : 1; + unsigned long DPINT0 : 1; + unsigned long : 8; + unsigned long DVBSE0 : 1; + unsigned long : 1; + unsigned long DOVRCRBE0 : 1; + unsigned long DOVRCRAE0 : 1; + unsigned long : 2; + unsigned long DMINTE0 : 1; + unsigned long DPINTE0 : 1; +#endif + } BIT; + } DPUSR1R; +} st_usb_t; + +typedef struct st_usb0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short USBE : 1; + unsigned short : 3; + unsigned short DPRPU : 1; + unsigned short DRPD : 1; + unsigned short DCFM : 1; + unsigned short : 3; + unsigned short SCKE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SCKE : 1; + unsigned short : 3; + unsigned short DCFM : 1; + unsigned short DRPD : 1; + unsigned short DPRPU : 1; + unsigned short : 3; + unsigned short USBE : 1; +#endif + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 2; + unsigned short SOFEA : 1; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short SOFEA : 1; + unsigned short : 2; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RHST : 3; + unsigned short : 1; + unsigned short UACT : 1; + unsigned short RESUME : 1; + unsigned short USBRST : 1; + unsigned short RWUPE : 1; + unsigned short WKUP : 1; + unsigned short VBUSEN : 1; + unsigned short EXICEN : 1; + unsigned short HNPBTOA : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short HNPBTOA : 1; + unsigned short EXICEN : 1; + unsigned short VBUSEN : 1; + unsigned short WKUP : 1; + unsigned short RWUPE : 1; + unsigned short USBRST : 1; + unsigned short RESUME : 1; + unsigned short UACT : 1; + unsigned short : 1; + unsigned short RHST : 3; +#endif + } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CURPIPE : 4; + unsigned short : 1; + unsigned short ISEL : 1; + unsigned short : 2; + unsigned short BIGEND : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 3; + unsigned short REW : 1; + unsigned short RCNT : 1; +#else + unsigned short RCNT : 1; + unsigned short REW : 1; + unsigned short : 3; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short BIGEND : 1; + unsigned short : 2; + unsigned short ISEL : 1; + unsigned short : 1; + unsigned short CURPIPE : 4; +#endif + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DTLN : 9; + unsigned short : 4; + unsigned short FRDY : 1; + unsigned short BCLR : 1; + unsigned short BVAL : 1; +#else + unsigned short BVAL : 1; + unsigned short BCLR : 1; + unsigned short FRDY : 1; + unsigned short : 4; + unsigned short DTLN : 9; +#endif + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CURPIPE : 4; + unsigned short : 4; + unsigned short BIGEND : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short DREQE : 1; + unsigned short DCLRM : 1; + unsigned short REW : 1; + unsigned short RCNT : 1; +#else + unsigned short RCNT : 1; + unsigned short REW : 1; + unsigned short DCLRM : 1; + unsigned short DREQE : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short BIGEND : 1; + unsigned short : 4; + unsigned short CURPIPE : 4; +#endif + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DTLN : 9; + unsigned short : 4; + unsigned short FRDY : 1; + unsigned short BCLR : 1; + unsigned short BVAL : 1; +#else + unsigned short BVAL : 1; + unsigned short BCLR : 1; + unsigned short FRDY : 1; + unsigned short : 4; + unsigned short DTLN : 9; +#endif + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CURPIPE : 4; + unsigned short : 4; + unsigned short BIGEND : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short DREQE : 1; + unsigned short DCLRM : 1; + unsigned short REW : 1; + unsigned short RCNT : 1; +#else + unsigned short RCNT : 1; + unsigned short REW : 1; + unsigned short DCLRM : 1; + unsigned short DREQE : 1; + unsigned short : 1; + unsigned short MBW : 1; + unsigned short : 1; + unsigned short BIGEND : 1; + unsigned short : 4; + unsigned short CURPIPE : 4; +#endif + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DTLN : 9; + unsigned short : 4; + unsigned short FRDY : 1; + unsigned short BCLR : 1; + unsigned short BVAL : 1; +#else + unsigned short BVAL : 1; + unsigned short BCLR : 1; + unsigned short FRDY : 1; + unsigned short : 4; + unsigned short DTLN : 9; +#endif + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short BRDYE : 1; + unsigned short NRDYE : 1; + unsigned short BEMPE : 1; + unsigned short CTRE : 1; + unsigned short DVSE : 1; + unsigned short SOFE : 1; + unsigned short RSME : 1; + unsigned short VBSE : 1; +#else + unsigned short VBSE : 1; + unsigned short RSME : 1; + unsigned short SOFE : 1; + unsigned short DVSE : 1; + unsigned short CTRE : 1; + unsigned short BEMPE : 1; + unsigned short NRDYE : 1; + unsigned short BRDYE : 1; + unsigned short : 8; +#endif + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short SACKE : 1; + unsigned short SIGNE : 1; + unsigned short EOFERRE : 1; + unsigned short : 4; + unsigned short ATTCHE : 1; + unsigned short DTCHE : 1; + unsigned short : 1; + unsigned short BCHGE : 1; + unsigned short OVRCRE : 1; +#else + unsigned short OVRCRE : 1; + unsigned short BCHGE : 1; + unsigned short : 1; + unsigned short DTCHE : 1; + unsigned short ATTCHE : 1; + unsigned short : 4; + unsigned short EOFERRE : 1; + unsigned short SIGNE : 1; + unsigned short SACKE : 1; + unsigned short : 4; +#endif + } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short EDGESTS : 1; + unsigned short : 1; + unsigned short BRDYM : 1; + unsigned short : 1; + unsigned short TRNENSEL : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short TRNENSEL : 1; + unsigned short : 1; + unsigned short BRDYM : 1; + unsigned short : 1; + unsigned short EDGESTS : 1; + unsigned short : 4; +#endif + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSQ : 3; + unsigned short VALID : 1; + unsigned short DVSQ : 3; + unsigned short VBSTS : 1; + unsigned short BRDY : 1; + unsigned short NRDY : 1; + unsigned short BEMP : 1; + unsigned short CTRT : 1; + unsigned short DVST : 1; + unsigned short SOFR : 1; + unsigned short RESM : 1; + unsigned short VBINT : 1; +#else + unsigned short VBINT : 1; + unsigned short RESM : 1; + unsigned short SOFR : 1; + unsigned short DVST : 1; + unsigned short CTRT : 1; + unsigned short BEMP : 1; + unsigned short NRDY : 1; + unsigned short BRDY : 1; + unsigned short VBSTS : 1; + unsigned short DVSQ : 3; + unsigned short VALID : 1; + unsigned short CTSQ : 3; +#endif + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short SACK : 1; + unsigned short SIGN : 1; + unsigned short EOFERR : 1; + unsigned short : 4; + unsigned short ATTCH : 1; + unsigned short DTCH : 1; + unsigned short : 1; + unsigned short BCHG : 1; + unsigned short OVRCR : 1; +#else + unsigned short OVRCR : 1; + unsigned short BCHG : 1; + unsigned short : 1; + unsigned short DTCH : 1; + unsigned short ATTCH : 1; + unsigned short : 4; + unsigned short EOFERR : 1; + unsigned short SIGN : 1; + unsigned short SACK : 1; + unsigned short : 4; +#endif + } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDY : 1; + unsigned short PIPE1BRDY : 1; + unsigned short PIPE2BRDY : 1; + unsigned short PIPE3BRDY : 1; + unsigned short PIPE4BRDY : 1; + unsigned short PIPE5BRDY : 1; + unsigned short PIPE6BRDY : 1; + unsigned short PIPE7BRDY : 1; + unsigned short PIPE8BRDY : 1; + unsigned short PIPE9BRDY : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDY : 1; + unsigned short PIPE8BRDY : 1; + unsigned short PIPE7BRDY : 1; + unsigned short PIPE6BRDY : 1; + unsigned short PIPE5BRDY : 1; + unsigned short PIPE4BRDY : 1; + unsigned short PIPE3BRDY : 1; + unsigned short PIPE2BRDY : 1; + unsigned short PIPE1BRDY : 1; + unsigned short PIPE0BRDY : 1; +#endif + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDY : 1; + unsigned short PIPE1NRDY : 1; + unsigned short PIPE2NRDY : 1; + unsigned short PIPE3NRDY : 1; + unsigned short PIPE4NRDY : 1; + unsigned short PIPE5NRDY : 1; + unsigned short PIPE6NRDY : 1; + unsigned short PIPE7NRDY : 1; + unsigned short PIPE8NRDY : 1; + unsigned short PIPE9NRDY : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDY : 1; + unsigned short PIPE8NRDY : 1; + unsigned short PIPE7NRDY : 1; + unsigned short PIPE6NRDY : 1; + unsigned short PIPE5NRDY : 1; + unsigned short PIPE4NRDY : 1; + unsigned short PIPE3NRDY : 1; + unsigned short PIPE2NRDY : 1; + unsigned short PIPE1NRDY : 1; + unsigned short PIPE0NRDY : 1; +#endif + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMP : 1; + unsigned short PIPE1BEMP : 1; + unsigned short PIPE2BEMP : 1; + unsigned short PIPE3BEMP : 1; + unsigned short PIPE4BEMP : 1; + unsigned short PIPE5BEMP : 1; + unsigned short PIPE6BEMP : 1; + unsigned short PIPE7BEMP : 1; + unsigned short PIPE8BEMP : 1; + unsigned short PIPE9BEMP : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMP : 1; + unsigned short PIPE8BEMP : 1; + unsigned short PIPE7BEMP : 1; + unsigned short PIPE6BEMP : 1; + unsigned short PIPE5BEMP : 1; + unsigned short PIPE4BEMP : 1; + unsigned short PIPE3BEMP : 1; + unsigned short PIPE2BEMP : 1; + unsigned short PIPE1BEMP : 1; + unsigned short PIPE0BEMP : 1; +#endif + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FRNM : 11; + unsigned short : 3; + unsigned short CRCE : 1; + unsigned short OVRN : 1; +#else + unsigned short OVRN : 1; + unsigned short CRCE : 1; + unsigned short : 3; + unsigned short FRNM : 11; +#endif + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short DVCHG : 1; +#else + unsigned short DVCHG : 1; + unsigned short : 15; +#endif + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short USBADDR : 7; + unsigned short : 1; + unsigned short STSRECOV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short STSRECOV : 4; + unsigned short : 1; + unsigned short USBADDR : 7; +#endif + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short DIR : 1; + unsigned short : 2; + unsigned short SHTNAK : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short SHTNAK : 1; + unsigned short : 2; + unsigned short DIR : 1; + unsigned short : 4; +#endif + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MXPS : 7; + unsigned short : 5; + unsigned short DEVSEL : 4; +#else + unsigned short DEVSEL : 4; + unsigned short : 5; + unsigned short MXPS : 7; +#endif + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short CCPL : 1; + unsigned short : 2; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short : 2; + unsigned short SUREQCLR : 1; + unsigned short : 2; + unsigned short SUREQ : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short SUREQ : 1; + unsigned short : 2; + unsigned short SUREQCLR : 1; + unsigned short : 2; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 2; + unsigned short CCPL : 1; + unsigned short PID : 2; +#endif + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPESEL : 4; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short PIPESEL : 4; +#endif + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EPNUM : 4; + unsigned short DIR : 1; + unsigned short : 2; + unsigned short SHTNAK : 1; + unsigned short : 1; + unsigned short DBLB : 1; + unsigned short BFRE : 1; + unsigned short : 3; + unsigned short TYPE : 2; +#else + unsigned short TYPE : 2; + unsigned short : 3; + unsigned short BFRE : 1; + unsigned short DBLB : 1; + unsigned short : 1; + unsigned short SHTNAK : 1; + unsigned short : 2; + unsigned short DIR : 1; + unsigned short EPNUM : 4; +#endif + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MXPS : 9; + unsigned short : 3; + unsigned short DEVSEL : 4; +#else + unsigned short DEVSEL : 4; + unsigned short : 3; + unsigned short MXPS : 9; +#endif + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IITV : 3; + unsigned short : 9; + unsigned short IFIS : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short IFIS : 1; + unsigned short : 9; + unsigned short IITV : 3; +#endif + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short ATREPM : 1; + unsigned short : 3; + unsigned short INBUFM : 1; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short INBUFM : 1; + unsigned short : 3; + unsigned short ATREPM : 1; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PID : 2; + unsigned short : 3; + unsigned short PBUSY : 1; + unsigned short SQMON : 1; + unsigned short SQSET : 1; + unsigned short SQCLR : 1; + unsigned short ACLRM : 1; + unsigned short : 5; + unsigned short BSTS : 1; +#else + unsigned short BSTS : 1; + unsigned short : 5; + unsigned short ACLRM : 1; + unsigned short SQCLR : 1; + unsigned short SQSET : 1; + unsigned short SQMON : 1; + unsigned short PBUSY : 1; + unsigned short : 3; + unsigned short PID : 2; +#endif + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short TRCLR : 1; + unsigned short TRENB : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TRENB : 1; + unsigned short TRCLR : 1; + unsigned short : 8; +#endif + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 6; + unsigned short USBSPD : 2; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short USBSPD : 2; + unsigned short : 6; +#endif + } BIT; + } DEVADD5; + char wk16[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SLEWR00 : 1; + unsigned long SLEWR01 : 1; + unsigned long SLEWF00 : 1; + unsigned long SLEWF01 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long SLEWF01 : 1; + unsigned long SLEWF00 : 1; + unsigned long SLEWR01 : 1; + unsigned long SLEWR00 : 1; +#endif + } BIT; + } PHYSLEW; +} st_usb0_t; + +typedef struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } WDTRCR; +} st_wdt_t; + +typedef struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +} st_flashconst_t; + +typedef struct st_tempsconst { + unsigned long TSCDR; +} st_tempsconst_t; + + +#pragma pack() + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c new file mode 100644 index 000000000..b36242303 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c @@ -0,0 +1,202 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.c +* Device(s) : RX72N +* Description : Definition of the exception vector table, reset vector, and user boot options. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* BSP configuration. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION); +R_BSP_UB_POR_FUNCTION(R_BSP_UB_POWER_ON_RESET_FUNCTION); + +/*********************************************************************************************************************** +* The following array fills in the option function select registers, fixed vector table, and the ID code protection +* bytes. +***********************************************************************************************************************/ +#ifdef __BIG + #define BSP_PRV_MDE_VALUE (0xfffffff8) /* big */ +#else + #define BSP_PRV_MDE_VALUE (0xffffffff) /* little */ +#endif + +#if BSP_CFG_CODE_FLASH_BANK_MODE == 0 + #define BSP_PRV_BANK_MODE_VALUE (0xffffff8f) /* dual */ +#else + #define BSP_PRV_BANK_MODE_VALUE (0xffffffff) /* linear */ +#endif + +#if BSP_CFG_CODE_FLASH_START_BANK == 0 + /* The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xffffffff) +#else + /* The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xfffffff8) +#endif + +#if defined(__CCRX__) + +#pragma address __MDEreg = 0xFE7F5D00 +#pragma address __OFS0reg = 0xFE7F5D04 +#pragma address __OFS1reg = 0xFE7F5D08 +#pragma address __TMINFreg = 0xFE7F5D10 +#pragma address __BANKSELreg = 0xFE7F5D20 +#pragma address __SPCCreg = 0xFE7F5D40 +#pragma address __TMEFreg = 0xFE7F5D48 +#pragma address __OSIS1reg = 0xFE7F5D50 +#pragma address __OSIS2reg = 0xFE7F5D54 +#pragma address __OSIS3reg = 0xFE7F5D58 +#pragma address __OSIS4reg = 0xFE7F5D5C +#pragma address __FAWreg = 0xFE7F5D64 +#pragma address __ROMCODEreg = 0xFE7F5D70 + +const uint32_t __MDEreg = (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE); +const uint32_t __OFS0reg = BSP_CFG_OFS0_REG_VALUE; +const uint32_t __OFS1reg = BSP_CFG_OFS1_REG_VALUE; +const uint32_t __TMINFreg = 0xffffffff; +const uint32_t __BANKSELreg = BSP_PRV_START_BANK_VALUE; +const uint32_t __SPCCreg = 0xffffffff; +const uint32_t __TMEFreg = BSP_CFG_TRUSTED_MODE_FUNCTION; +const uint32_t __OSIS1reg = BSP_CFG_ID_CODE_LONG_1; +const uint32_t __OSIS2reg = BSP_CFG_ID_CODE_LONG_2; +const uint32_t __OSIS3reg = BSP_CFG_ID_CODE_LONG_3; +const uint32_t __OSIS4reg = BSP_CFG_ID_CODE_LONG_4; +const uint32_t __FAWreg = BSP_CFG_FAW_REG_VALUE; +const uint32_t __ROMCODEreg = BSP_CFG_ROMCODE_REG_VALUE; + +#elif defined(__GNUC__) + +const st_ofsm_sec_ofs1_t __ofsm_sec_ofs1 __attribute__ ((section(".ofs1"))) = { + (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE), /* __MDEreg */ + BSP_CFG_OFS0_REG_VALUE, /* __OFS0reg */ + BSP_CFG_OFS1_REG_VALUE /* __OFS1reg */ +}; +const uint32_t __TMINFreg __attribute__ ((section(".ofs2"))) = 0xffffffff; +const uint32_t __BANKSELreg __attribute__ ((section(".ofs3"))) = BSP_PRV_START_BANK_VALUE; +const uint32_t __SPCCreg __attribute__ ((section(".ofs4"))) = 0xffffffff; +const uint32_t __TMEFreg __attribute__ ((section(".ofs5"))) = BSP_CFG_TRUSTED_MODE_FUNCTION; +const st_ofsm_sec_ofs6_t __ofsm_sec_ofs6 __attribute__ ((section(".ofs6"))) = { + BSP_CFG_ID_CODE_LONG_1, /* __OSIS1reg */ + BSP_CFG_ID_CODE_LONG_2, /* __OSIS2reg */ + BSP_CFG_ID_CODE_LONG_3, /* __OSIS3reg */ + BSP_CFG_ID_CODE_LONG_4 /* __OSIS4reg */ +}; +const uint32_t __FAWreg __attribute__ ((section(".ofs7"))) = BSP_CFG_FAW_REG_VALUE; +const uint32_t __ROMCODEreg __attribute__ ((section(".ofs8"))) = BSP_CFG_ROMCODE_REG_VALUE; + +#elif defined(__ICCRX__) + +#pragma public_equ = "__MDE", (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE) +#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE +#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE +#pragma public_equ = "__TMINF", 0xffffffff +#pragma public_equ = "__BANKSEL", BSP_PRV_START_BANK_VALUE +#pragma public_equ = "__SPCC", 0xffffffff +#pragma public_equ = "__TMEF", BSP_CFG_TRUSTED_MODE_FUNCTION +#pragma public_equ = "__OSIS_1", BSP_CFG_ID_CODE_LONG_1 +#pragma public_equ = "__OSIS_2", BSP_CFG_ID_CODE_LONG_2 +#pragma public_equ = "__OSIS_3", BSP_CFG_ID_CODE_LONG_3 +#pragma public_equ = "__OSIS_4", BSP_CFG_ID_CODE_LONG_4 +#pragma public_equ = "__FAW", BSP_CFG_FAW_REG_VALUE +#pragma public_equ = "__ROM_CODE", BSP_CFG_ROMCODE_REG_VALUE + +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* The following array fills in the exception vector table. +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* System configurator generates the ritble.src as interrupt & exception vector tables. */ +#else /* BSP_CFG_RTOS_USED!=4 */ + +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT void (* const Except_Vectors[])(void) = +{ + /* Offset from EXTB: Reserved area - must be all 0xFF */ + (void (*)(void))0xFFFFFFFF, /* 0x00 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x04 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x08 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x0c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x10 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x14 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x18 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x1c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x20 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x24 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x28 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x2c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x30 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x34 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x38 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x3c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x40 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x44 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x48 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x4c - Reserved */ + + /* Exception vector table */ + excep_supervisor_inst_isr, /* 0x50 Exception(Supervisor Instruction) */ + excep_access_isr, /* 0x54 Exception(Access exception) */ + undefined_interrupt_source_isr, /* 0x58 Reserved */ + excep_undefined_inst_isr, /* 0x5c Exception(Undefined Instruction) */ + undefined_interrupt_source_isr, /* 0x60 Reserved */ + excep_floating_point_isr, /* 0x64 Exception(Floating Point) */ + undefined_interrupt_source_isr, /* 0x68 Reserved */ + undefined_interrupt_source_isr, /* 0x6c Reserved */ + undefined_interrupt_source_isr, /* 0x70 Reserved */ + undefined_interrupt_source_isr, /* 0x74 Reserved */ + non_maskable_isr, /* 0x78 NMI */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +* The following array fills in the reset vector. +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT void (* const Reset_Vector[])(void) = +{ + R_BSP_POWER_ON_RESET_FUNCTION /* 0xfffffffc RESET */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h new file mode 100644 index 000000000..802a4e950 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.h +* Description : Has function prototypes for exception callback functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef VECTTBL_HEADER_INC +#define VECTTBL_HEADER_INC + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if defined(__GNUC__) +typedef struct st_ofsm_sec_ofs1 +{ + uint32_t __MDEreg; + uint32_t __OFS0reg; + uint32_t __OFS1reg; +} st_ofsm_sec_ofs1_t; + +typedef struct st_ofsm_sec_ofs6 +{ + uint32_t __OSIS1reg; + uint32_t __OSIS2reg; + uint32_t __OSIS3reg; + uint32_t __OSIS4reg; +} st_ofsm_sec_ofs6_t; +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* VECTTBL_HEADER_INC */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/platform.h new file mode 100644 index 000000000..43921b899 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/platform.h @@ -0,0 +1,224 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : platform.h +* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using +* is not listed below, please add your own or use the default 'User Board'. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.11.2011 1.00 First Release +* : 13.01.2012 1.10 Moved from having platform defined using macro definition, to having platform defined +* by choosing an include path. This makes this file simpler and cleans up the issue +* where HEW shows all header files for all platforms under 'Dependencies'. +* : 14.02.2012 1.20 Added RX210 BSP. +* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding +* locking.c and locking.h in board folders. Also, r_bsp can now be configured through +* r_bsp_config.h. +* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using +* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort +* to remove any extra files that the user would need to touch. Removed the flash_options.c +* file and put its contents in vecttbl.c. +* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT +* macro options in r_bsp_config.h. Added some extra code to handle exceptions in +* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks. +* : 09.08.2012 1.60 Added IO_LIB_ENABLE macro to r_bsp_config_reference.h. +* : 14.11.2012 1.70 Added RSKRX62G, RSKRX63T, and RSKRX111 support. +* : 28.11.2012 2.00 Updated to be compliant with v1.00 r_bsp specification. +* : 21.01.2013 2.10 Added RSKRX63T_144PIN support. +* : 10.05.2013 2.20 Added new packages and memory variants to RX210. All iodefine.h files have been updated +* to latest revisions. On reset, all MCUs will now initialize non-bonded out pins to +* reduce current draw. r_bsp_common.c and .h files were added to support functionality +* common to all BSPs. cpu.c and cpu.h files were added to all MCU groups to support +* CPU functions such as enabling/disabling interrupts, setting the IPL, and controlling +* register protection. mcu_init.c and mcu_init.h were add to all MCU groups to support +* initialization functions that are common to a MCU group such as non-bonded pin init. +* Choosing MCU endian has been removed from r_bsp_config.h and is now automatically +* set based on compiler macros. RX-C, IAR, and GCC endian macros are supported. RX210 +* now has support for choosing HOCO frequency. All r_bsp_config.h files now have macro +* for defining Vcc which is needed by some FIT modules. IRQ locks were added for all +* MCU groups. BSP_PACKAGE_PINS macro was added to mcu_info.h which defines number of pins +* for the currently chosen package. RX111 and RX210 now have the option of using the +* r_cgc_rx module for clock management based on BSP_CFG_USE_CGC_MODULE macro in +* r_bsp_config.h. +* : 31.05.2013 2.21 Added latest iodefine.h files for RX111 (v0.9a), RX630 (v1,50a), and RX63N (v1.60). Also +* added 'doc' folder to root of r_bsp. Currently the only the document in there is the +* preliminary version of the r_bsp User's Manual. For RX210, the ability to choose chip +* version C was added to its r_bsp_config.h file. +* : 01.07.2013 2.30 Removed RSPI pin setup in RSKRX111 which caused excess current draw in low power +* modes. Changed FIT_NO_PTR and FIT_NO_FUNC macros to 0x10000000 which works for all +* RX MCUs. Added ability for user to use 1 or 2 stacks for RX MCUs. Added new interrupt +* handling features which allows for interrupt callback registration. This feature allows +* all interrupts that map to the NMI vector to be used and replaces the static callback +* definitions that were in r_bsp_config.h previously. RX111 information has been updated +* according to v1.00 HW manual. This includes support for 40-pin packages. All compiler +* messages and warnings for lowsrc.c have been cleaned up. Non-existent port init has +* been moved to end of hardware_setup() to ensure user does not overwrite the settings. +* Added blank lines between clock macros in r_bsp_config.h to aid in readability. Added +* '(void *)' cast to FIT_NO_PTR to remove compiler warnings. All r_bsp.h files now include +* r_bsp_common.h which has common includes (stdint.h, stddef.h, & stdbool.h) and uses +* r_typedefs.h when C99 is not available. RX111 and RX210 MCUs have the option of using +* the r_cgc_rx module for clock management. When this is used, the clock info macros in +* mcu_info.h (e.g. BSP_ICLK_HZ) will now make calls to the r_cgc_rx module instead of +* providing static info. For debug console output, lowlvl.src was replaced by lowlvl.c +* (assembly converted to C source). +* : 10.02.2014 2.40 Added support for the RSKRX110, RPBRX111, RSKRX220, and HSBRX21AP. Made sure +* in hwsetup.c files that the PMR registers are set after the MPC registers. Replaced +* use of stdint.h, stdbool.h, and stddef.h with platform.h to remove compiler warnings. +* Removed includes for machine.h since it is compiler specific and replaced with +* platform.h. Fixed bug in resetprg.c for many boards where LOCO was not being turned off +* when it was not being used. RX100 code now uses the oscillation stabilization flags +* instead of SW delay loop. Changed size_t to unsigned long. Defined PRC2 in register +* protection section for RX111. Fixed bug in non-existent pin setup for RX111. No +* platform is chosen by default (used to be the RSKRX111). This makes it easier to +* understand the problem when you build a new project and have not selected your platform. +* : 24.03.2014 2.50 Added support for the RSKRX64M. +* : 16.06.2014 2.60 Added version control for r_bsp_config.h Two user callback functions may now be +* configured allowing callbacks from PowerON_Reset_PC() for warm start detection. +* Stdio charget() and charput() functions may now be redirected to user defined functions. +* Added support for RSKRX631 and RDKRX631. +* : 05.08.2014 2.70 Added support for RSKRX113. +* : 29.09.2014 2.80 Added support for RSKRX71M. +* : 22.12.2014 2.90 Added support for RSKRX231. +* : 30.09.2015 3.00 Added support for RSSKRX23T and RSKRX23T. +* : 30.09.2015 3.01 Fix for RSKRX231 and RSKRX23T(RSSKRX23T). +* : 01.12.2015 3.10 Added support for RSKRX130. +* : 01.02.2016 3.20 Added support for RSKRX24T. +* : 29.02.2016 3.30 Added support for RSKRX230. +* : 01.10.2016 3.40 Added support for RSKRX65N. +* : 22.08.2016 3.50 Added support for RSKRX24U. +* : 15.05.2017 3.60 Added support for RSKRX65N-2MB. +* Added support for GENERIC_RX65N. +* Added support for RSKRX130-512KB. +* : 01.11.2017 3.70 Added support for GENERIC_RX130. +* Added support for GENERIC_RX110. +* Added support for GENERIC_RX111. +* Added support for GENERIC_RX113. +* Added support for GENERIC_RX230. +* Added support for GENERIC_RX231. +* Added support for GENERIC_RX23T. +* Added support for GENERIC_RX24T. +* Added support for GENERIC_RX24U. +* Added support for GENERIC_RX64M. +* Added support for GENERIC_RX71M. +* Added support for ENVISIONRX65N. +* : 01.11.2017 3.71 Corrected typo in Rev3.70 BSP. +* : 01.07.2018 3.80 Added support for TARGETBOARDRX65N. +* Added support for TARGETBOARDRX231. +* Added support for TARGETBOARDRX130. +* : 27.07.2018 3.90 Added support for GENERIC_RX66T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSKRX64M, RSKRX65N, RSKRX65N_2MB, TARGETBOARDRX65N, ENVISIONRX65N, RSKRX71M, +* RSKRX230, RSKRX231, TARGETBOARDRX231, RSKRX110, RSKRX111, RPBRX111, RSKRX113, +* RSKRX130, RSKRX130_512KB, and TARGETBOARDRX130 +* : 31.10.2018 4.00 Added support for GENERIC_RX72T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSSKRX23T, RSKRX23T, RSKRX24T, and RSKRX24U +* : 28.02.2019 5.00 Deleted the below board folders. +* - RSKRX610, RSKRX62N, RSKRX62T, RSKRX62G, RDKRX62N, RSKRX630, RSKRX631, RSKRX63T_64PIN, +* RSKRX63T_144PIN, RDKRX63N, RDKRX631, RSKRX210, HSBRX21AP and RSKRX220 +* : 29.03.2019 5.10 Added support for GENERIC_RX23W. +* : 08.04.2019 5.20 Added support for GENERIC_RX72M. +* : 26.07.2019 5.30 Added support for GENERIC_RX13T. +* : 31.07.2019 5.40 Added support for GENERIC_RX23E-A. +* : 08.10.2019 5.50 Added support for GENERIC_RX72N, and GENERIC_RX66N. +* Deleted the board folders of RSKRX63N. +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef PLATFORM_H +#define PLATFORM_H + +/*********************************************************************************************************************** +DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING. +***********************************************************************************************************************/ +/* GENERIC_RX64M */ +//#include "./board/generic_rx64m/r_bsp.h" + +/* GENERIC_RX65N */ +//#include "./board/generic_rx65n/r_bsp.h" + +/* GENERIC_RX66N */ +//#include "./board/generic_rx66n/r_bsp.h" + +/* GENERIC_RX66T */ +//#include "./board/generic_rx66t/r_bsp.h" + +/* GENERIC_RX71M */ +//#include "./board/generic_rx71m/r_bsp.h" + +/* GENERIC_RX72M */ +//#include "./board/generic_rx72m/r_bsp.h" + +/* GENERIC_RX72N */ +#include "./board/generic_rx72n/r_bsp.h" + +/* GENERIC_RX72T */ +//#include "./board/generic_rx72t/r_bsp.h" + +/* GENERIC_RX230 */ +//#include "./board/generic_rx230/r_bsp.h" + +/* GENERIC_RX231 */ +//#include "./board/generic_rx231/r_bsp.h" + +/* GENERIC_RX23E-A */ +//#include "./board/generic_rx23e-a/r_bsp.h" + +/* GENERIC_RX23T */ +//#include "./board/generic_rx23t/r_bsp.h" + +/* GENERIC_RX23W */ +//#include "./board/generic_rx23w/r_bsp.h" + +/* GENERIC_RX24T */ +//#include "./board/generic_rx24t/r_bsp.h" + +/* GENERIC_RX24U */ +//#include "./board/generic_rx24u/r_bsp.h" + +/* GENERIC_RX111 */ +//#include "./board/generic_rx111/r_bsp.h" + +/* GENERIC_RX110 */ +//#include "./board/generic_rx110/r_bsp.h" + +/* GENERIC_RX113 */ +//#include "./board/generic_rx113/r_bsp.h" + +/* GENERIC_RX130 */ +//#include "./board/generic_rx130/r_bsp.h" + +/* GENERIC_RX13T */ +//#include "./board/generic_rx13t/r_bsp.h" + +/* User Board - Define your own board here. */ +//#include "./board/user/r_bsp.h" + +/*********************************************************************************************************************** +MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT +***********************************************************************************************************************/ +#ifndef PLATFORM_DEFINED +#error "Error - No platform defined in platform.h!" +#endif + +#endif /* PLATFORM_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/readme.txt new file mode 100644 index 000000000..25aa74e4c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_bsp/readme.txt @@ -0,0 +1,57 @@ +r_bsp Package +============= + +Overview +-------- +The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU +information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder contains files +that are common to a MCU group. These files provide functionality such as easy register access, CPU functions, +and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board +and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help +configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each +supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which +board they are using by uncommenting the include path that applies to their board. For example, if you are using the +RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add +their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a +reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it +to r_bsp_config.h, and use the options inside the file to configure the BSP for their project. + + +Features +-------- +* Provides foundation to build code on top of. +* Provides MCU startup code. +* Provides SFR access through iodefine.h +* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware. +* Easily configure BSP through r_bsp_config.h. +* Choose MCU easily by inputting part number details in r_bsp_config.h. +* Provides callbacks for MCU exceptions and the bus error interrupt. +* Supports initializing non-bonded out pins to reduce power +* Provides API to control CPU functions such as setting the IPL, enabling/disabling interrupts, and controlling + register protection + + + +File Structure +-------------- +r_bsp +| platform.h +| readme.txt +| ++---board +| +---generic_rx111 +| | : +| : +| \---user +| ++---doc +| +---en +| r01an1685ej{VERSION_NUMBER}-rx-bsp.pdf +| +---ja +| r01an1685jj{VERSION_NUMBER}-rx-bsp.pdf +| +\---mcu + +---all + +---rx111 + | : + : \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/r_byteq_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/r_byteq_if.h new file mode 100644 index 000000000..1bd93830d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/r_byteq_if.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_if.h +* Description : Functions for using byte queues/circular buffers +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 01.22.2015 1.30 Updated version to 1.30 for RX71M release +* : 04.04.2015 1.40 Updated version to 1.40 for RX231 release +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Updated version to 1.60 for correspondence to RX Family +* : 01.06.2018 1.70 Updated version to 1.70 +* : 03.12.2018 1.71 Updated version to 1.71 for update of xml file. +* : 07.02.2019 1.80 Updated version to 1.80. +***********************************************************************************************************************/ + +#ifndef BYTEQ_IF_H +#define BYTEQ_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Version Number of API. */ +#define BYTEQ_VERSION_MAJOR (1) +#define BYTEQ_VERSION_MINOR (80) + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef enum e_byteq_err // BYTEQ API error codes +{ + BYTEQ_SUCCESS = 0, + BYTEQ_ERR_NULL_PTR, // received null ptr; missing required argument + BYTEQ_ERR_INVALID_ARG, // argument is not valid for parameter + BYTEQ_ERR_MALLOC_FAIL, // can't allocate memory for ctrl block; increase heap + BYTEQ_ERR_NO_MORE_CTRL_BLKS, // no more control blocks, increase BYTEQ_MAX_CTRL_BLKS + BYTEQ_ERR_QUEUE_FULL, // queue full; cannot add another byte + BYTEQ_ERR_QUEUE_EMPTY // queue empty; no byte to fetch +} byteq_err_t; + + +/* BYTE QUEUE HANDLE */ + +typedef struct st_byteq_ctrl * byteq_hdl_t; + + +/***************************************************************************** +Public Functions +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl); + +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte); + +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte); + +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +uint32_t R_BYTEQ_GetVersion(void); + + +#endif /* BYTEQ_IF_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/readme.txt new file mode 100644 index 000000000..1173711e1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/readme.txt @@ -0,0 +1,48 @@ + +r_byteq +======= + +Overview +-------------------------------------------------------------------------------- +The r_byteq module is a collection of circular buffer routines for byte data. +The application passes a buffer to be used as a circular buffer to the Open() +function which assigns a queue control block to it to handle indexing. The +Open() function returns a handle which is then used as a queue/buffer id for all +other API functions. These functions include routines for adding and removing +data from a queue, inspecting the amount of data in a queue, and the ability to +flush a queue. + +The queue control blocks can be allocated at compile time or dynamically at run +time. A configuration option for this exists in "r_config\r_byteq_config.h". +An original copy of the configuration file is stored in "r_byteq\ref\ +r_byteq_config_reference.h". + + +Features +-------- +* Statically or dynamically allocated queue control blocks. +* Number of queues limited only by the amount of RAM available on the mcu. + +File Structure +-------------- +r_byteq +| readme.txt +| r_byteq_if.h +| ++---doc +| +---en +| | r01an1683ej{VERSION_NUMBER}-rx.pdf +| | +| +---ja +| r01an1683jj{VERSION_NUMBER}-rx.pdf +| ++---ref +| r_byteq_config_reference.h +| ++---src + r_byteq.c + r_byteq_private.h + +r_config + r_byteq_config.h + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h new file mode 100644 index 000000000..40675c419 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + + +#endif /* BYTEQ_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/src/r_byteq.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/src/r_byteq.c new file mode 100644 index 000000000..816a88be8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/src/r_byteq.c @@ -0,0 +1,422 @@ +/***************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +******************************************************************************/ +/***************************************************************************** +* File Name : r_byteq.c +* Description : Functions for using byte queues/circular buffers. +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Fixed the initial setting process in the R_LONGQ_Open function. +* Fixed a program according to the Renesas coding rules. +* : 01.06.2018 1.70 Added the comment to while statement. +* : 07.02.2019 1.80 Deleted the inline expansion of the R_BYTEQ_GetVersion function. +******************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +/* Used functions of malloc() and the free() */ +#include + +/* Used the common type */ +#include "platform.h" + +/* Defines for BYTEQ support */ +#include "r_byteq_private.h" +#include "r_byteq_if.h" +#include "r_byteq_config.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK ALLOCATIONS */ + +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) +static byteq_ctrl_t g_qcb[BYTEQ_CFG_MAX_CTRL_BLKS]; +#endif + + +/***************************************************************************** +* Function Name: R_BYTEQ_Open +* Description : Allocates or assigns a queue control block for the buffer +* pointed to by p_buf (see BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS in +* config.h). Initializes the queue to an empty state and +* provides a Handle to its control structure in p_hdl which is +* then used as a queue ID for the other API functions. +* Arguments : p_buf - +* Pointer to byte buffer. +* size - +* Buffer size in bytes. +* p_hdl - +* Pointer to a handle for queue (value set here) +* Return Value : SCI_SUCCESS - +* queue initialized successfully +* BYTEQ_ERR_NULL_PTR +* received null ptr; missing required argument +* BYTEQ_ERR_INVALID_ARG +* argument is not valid for parameter +* BYTEQ_ERR_MALLOC_FAIL +* can't allocate memory for ctrl block; increase heap +* BYTEQ_ERR_NO_MORE_CTRL_BLKS +* no more control blocks, increase BYTEQ_CFG_MAX_CTRL_BLKS +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl) +{ + byteq_ctrl_t *p_qcb = 0; +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) + uint32_t i; + static bool qcb_init = false; +#endif + + /* CHECK ARGUMENTS */ + +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == p_hdl) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } + if (NULL == p_buf) + { + return BYTEQ_ERR_NULL_PTR; // return if no buffer pointer + } + if (size < 2) + { + return BYTEQ_ERR_INVALID_ARG; // return insufficient buffer size + } +#endif + + /* GET QUEUE CONTROL BLOCK */ + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + + /* allocate memory for a QCB */ + p_qcb = (byteq_ctrl_t *)malloc(sizeof(byteq_ctrl_t)); + if (NULL == p_qcb) + { + return BYTEQ_ERR_MALLOC_FAIL; + } +#else + /* if first Open call, mark all QCBs as being available */ + if (false == qcb_init) + { + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + g_qcb[i].buffer = NULL; + } + qcb_init = true; + } + + /* locate first available QCB */ + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + if (NULL == g_qcb[i].buffer) + { + p_qcb = &g_qcb[i]; + break; + } + } + + /* return error if none available */ + if (BYTEQ_CFG_MAX_CTRL_BLKS == i) + { + return BYTEQ_ERR_NO_MORE_CTRL_BLKS; + } +#endif + + + /* INITIALIZE QCB FIELDS */ + + p_qcb->buffer = p_buf; + p_qcb->size = size; + p_qcb->count = 0; + p_qcb->in_index = 0; + p_qcb->out_index = 0; + + + /* SET HANDLE */ + + *p_hdl = p_qcb; + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Put +* Description : This function adds a byte of data to the queue. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* byte - +* Byte to add to queue. +* Return Value : BYTEQ_SUCCESS - +* Successful; byte sent or queued for transmit +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_QUEUE_FULL - +* Queue full; cannot add byte to queue. +******************************************************************************/ +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } +#endif + + if (hdl->count >= hdl->size) + { + return BYTEQ_ERR_QUEUE_FULL; // return if queue is full + } + + /* load byte into queue */ + hdl->buffer[hdl->in_index++] = byte; // add byte + if (hdl->in_index >= hdl->size) // adjust index + { + hdl->in_index = 0; + } + hdl->count++; // adjust count + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Get +* Description : This function removes a byte of data from the queue. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* p_byte - +* Pointer to load byte to. +* Return Value : BYTEQ_SUCCESS - +* Successful; byte sent or queued for transmit +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_byte is NULL +* BYTEQ_ERR_QUEUE_EMPTY - +* Queue empty; no data available to fetch +******************************************************************************/ +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } + if (NULL == p_byte) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + if (0 == hdl->count) + { + return BYTEQ_ERR_QUEUE_EMPTY; // return if queue empty + } + + *p_byte = hdl->buffer[hdl->out_index++]; // get byte + if (hdl->out_index >= hdl->size) // adjust index + { + hdl->out_index = 0; + } + hdl->count--; // adjust count + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Flush +* Description : This function resets a queue to an empty state. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* Return Value : BYTEQ_SUCCESS - +* Successful; queue is reset to en ampty state +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + + /* RESET QUEUE */ + + hdl->in_index = 0; + hdl->out_index = 0; + hdl->count = 0; + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Used +* Description : This function provides the number of data bytes in the queue. +* Arguments : hdl - +* Handle for queue. +* p_cnt - +* Pointer to load queue data count to. +* Return Value : BYTEQ_SUCCESS - +* Successful; *p_cnt loaded with number of bytes in queue +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_cnt is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + *p_cnt = hdl->count; + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Unused +* Description : This function provides the number of data bytes available +* for storage in the queue. +* Arguments : hdl - +* Handle for queue. +* p_cnt - +* Pointer to load queue unused byte count to. +* Return Value : BYTEQ_SUCCESS - +* Successful; *p_cnt loaded with number of bytes available in +* queue +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_cnt is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + *p_cnt = (uint16_t) (hdl->size - hdl->count); + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Close +* Description : If the control block associated with this Handle was allocated +* dynamically at run time (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS set to 1 +* in config.h), then that memory is free()d by this function. If +* the control block was statically allocated at compile time +* (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS set to 0 in config.h), then this +* function marks the control block as available for use by another +* buffer. Nothing is done to the contents of the buffer referenced +* by this Handle. +* Arguments : hdl - +* handle for queue +* Return Value : BYTEQ_SUCCESS - +* Successful; control block freed +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL. +******************************************************************************/ +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + free(hdl); // free QCB memory +#else + hdl->buffer = NULL; // mark QCB as free +#endif + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_GetVersion +* Description : Returns the version of this module. The version number is +* encoded such that the top two bytes are the major version +* number and the bottom two bytes are the minor version number. +* Arguments : none +* Return Value : version number +******************************************************************************/ +uint32_t R_BYTEQ_GetVersion(void) +{ + + uint32_t const version = (BYTEQ_VERSION_MAJOR << 16) | BYTEQ_VERSION_MINOR; + return version; +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/src/r_byteq_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/src/r_byteq_private.h new file mode 100644 index 000000000..8f14acced --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_byteq/src/r_byteq_private.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_private.h +* Description : Definitions internal to byte queue module +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.0 Initial Release +* : 30.09.2015 1.50 Added dependency to BSP +***********************************************************************************************************************/ + +#ifndef BYTEQ_PRIVATE_H +#define BYTEQ_PRIVATE_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK */ + +typedef struct st_byteq_ctrl // Byte Queue Control Block (for handle) +{ + uint8_t *buffer; // pointer to buffer + uint16_t size; // buffer size + uint16_t count; // number data bytes in queue + uint16_t in_index; // index used by Put function to add data + uint16_t out_index; // index used by Get function to remove data +} byteq_ctrl_t; + + +#endif /* BYTEQ_PRIVATE_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_config.h new file mode 100644 index 000000000..5308bc5ae --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_config.h @@ -0,0 +1,774 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX72N +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release. +***********************************************************************************************************************/ +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/* Include for various workarounds. */ +#include "smc_workaround.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX72N. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 57 2N N D D BD + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FC = 0x0 = LFQFP/176/0.50 + BG = 0x1 = LFBGA/176/0.80 + BD = 0x2 = LFBGA/224/0.80 + FB = 0x3 = LFQFP/144/0.50 + LK = 0x4 = TFLGA/145/0.50 + FP = 0x5 = LFQFP/100/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x3) /* Generated value. Do not edit this manually */ + +/* Whether Encryption is included or not. + Character(s) = Value for macro = Description + D = 0xD = Encryption module not included + H = 0x11 = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0x11) /* Generated value. Do not edit this manually */ + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + D = 0xD = 2MB/1MB/32KB + N = 0x17 = 4MB/1MB/32KB +NOTE: The RAM areas are not contiguous.It is separated by 512 KB each. +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x17) /* Generated value. Do not edit this manually */ + +/* Group name. + Character(s) = Value for macro = Description + 2N = 0x0 = RX72N Group +*/ +#define BSP_CFG_MCU_PART_GROUP (0x0) /* Generated value. Do not edit this manually */ + +/* Series name. + Character(s) = Value for macro = Description + 57 = 0x0 = RX700 Series +*/ +#define BSP_CFG_MCU_PART_SERIES (0x0) /* Generated value. Do not edit this manually */ + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) /* Generated value. Do not edit this manually */ + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (0) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x0) +#endif + +/* Interrupt Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x0) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit (default) +*/ +#define BSP_CFG_CLOCK_SOURCE (4) /* Generated value. Do not edit this manually */ + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator (default) + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (0) /* Generated value. Do not edit this manually */ + +/* USB Clock source select (UPLLSEL). Choose which clock source to input to the USB circuit. + 0 = System Clock (PLL Circuit/No division) (This is not available.) + 1 = USB PLL Circuit (This is not available.) + 2 = PLL Circuit (UDIVCLK) (default) + 3 = PPLL Circuit (PPLLDIVCLK) +*/ +#define BSP_CFG_USB_CLOCK_SOURCE (2) /* Generated value. Do not edit this manually */ + +/* Ethernet-PHY clock source (OUTCKSEL). Choose which clock source to input to the Ethernet PHY LSI. + Available clock sources: + 0 = PLL circuit + 1 = PPLL circuit (default) + 2 = Ethernet-PHY not use +*/ +#define BSP_CFG_PHY_CLOCK_SOURCE (1) /* Generated value. Do not edit this manually */ + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 6 = PPLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE (1) /* Generated value. Do not edit this manually */ + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE (0) /* Generated value. Do not edit this manually */ + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP (0) /* Generated value. Do not edit this manually */ + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, BCLK is 80MHz, + USB Clock is 48MHz, ESC Clock is 100MHz, Ether-Phy Clock is 25MHz then the settings would be: + + BSP_CFG_XTAL_HZ = 24000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz) + BSP_CFG_PPLL_DIV = 3 (divide by 3) + BSP_CFG_PPLL_MUL = 25.0 (8MHz x 25.0 = 200MHz) + BSP_CFG_PPLCK_DIV = 2 (divide by 2) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 240MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_BCK_DIV = 3 : External Bus Clock (BCK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 80MHz + BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (16000000) /* Generated value. Do not edit this manually */ + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#define BSP_CFG_HOCO_FREQUENCY (2) /* Generated value. Do not edit this manually */ + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC (1) /* Generated value. Do not edit this manually */ + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (1) /* Generated value. Do not edit this manually */ + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL (12.0) /* Generated value. Do not edit this manually */ + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (1) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (2) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (4) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (4) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (4) /* Generated value. Do not edit this manually */ + +/* External Bus Clock Divider (BCLK). + Available divisors = /1 (no division), /2, /3, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_BCK_DIV (3) /* Generated value. Do not edit this manually */ + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (4) /* Generated value. Do not edit this manually */ + +/* USB Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_UCK_DIV (2) /* Generated value. Do not edit this manually */ + +/* PPLL Input Frequency Division Ratio Select (PPLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PPLL_DIV (1) /* Generated value. Do not edit this manually */ + +/* PPLL Frequency Multiplication Factor Select (PPLSTC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PPLL_MUL (10.0) /* Generated value. Do not edit this manually */ + +/* PPLL Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_PPLCK_DIV (2) /* Generated value. Do not edit this manually */ + +/* Configure BCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency +*/ +#define BSP_CFG_BCLK_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* Configure SDCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency + NOTE: The definition is invalid. +*/ +#define BSP_CFG_SDCLK_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV (0) /* Generated value. Do not edit this manually */ + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) /* Generated value. Do not edit this manually */ + +/* Sub-Clock Oscillator Wait Time (SOSCWTCR). + The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation + by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384 + (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h). +*/ +#define BSP_CFG_SOSC_WAIT_TIME (0x21) /* Generated value. Do not edit this manually */ + +/* ROM Cache Enable Register (ROMCE). + 0 = ROM cache operation disabled. + 1 = ROM cache operation enabled. +*/ +#define BSP_CFG_ROM_CACHE_ENABLE (1) + +/* Configure non-cacheable area 0 of the ROM cache function. + 0 = Non-cacheable area 0 settings disabled. + 1 = Non-cacheable area 0 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ENABLE (0) + +/* Specifies the start address of non-cacheable area 0. + Selects the start address of non-cacheable area 0. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 0. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of IF cache disabled. + 1 = Non-cacheable area 0 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of OA cache disabled. + 1 = Non-cacheable area 0 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of DM cache disabled. + 1 = Non-cacheable area 0 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE (1) + +/* Configure non-cacheable area 1 of the ROM cache function. + 0 = Non-cacheable area 1 settings disabled. + 1 = Non-cacheable area 1 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ENABLE (0) + +/* Specifies the start address of non-cacheable area 1. + Selects the start address of non-cacheable area 1. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 1. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of IF cache disabled. + 1 = Non-cacheable area 1 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of OA cache disabled. + 1 = Non-cacheable area 1 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of DM cache disabled. + 1 = Non-cacheable area 1 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE (1) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 78 and 79 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEFF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b26] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area + - 1: FFFF E000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory + when the flash programmer is used during off-board programming. + ROMCODE - ROM Code Protection Register + b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1). + 0000 0001h: ROM code protection enabled (ROM code protection 2). + Other than above: ROM code protection disabled. + Note: The ROMCODE register should be set in 32-bit units. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. +*/ +#if !defined(BSP_CFG_RTOS_USED) || (BSP_CFG_RTOS_USED == 0) +#if defined(BSP_CFG_RTOS_USED) +#undef BSP_CFG_RTOS_USED +#endif +#define BSP_CFG_RTOS_USED (1) /* Generated value. Do not edit this manually */ +#endif +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC + graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and + display list data read). + The default priority order in bsp is below + GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC. + Priority can be changed with this macro. + + Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */ +#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */ +#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */ +#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */ +#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */ + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) /* Generated value. Do not edit this manually */ + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (1) /* Generated value. Do not edit this manually */ + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (0) +#define BSP_CFG_SWINT_UNIT2_ENABLE (1) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt new file mode 100644 index 000000000..6a9002cf4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_config_readme.txt @@ -0,0 +1,12 @@ +FIT r_config folder +------------------- +The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration +files. Putting the files in one place makes them easy to find, backup, and put in a version control system. + +FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example, +the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are +provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the +user should copy this reference configuration file to this folder and remove '_reference' from the filename +(r_bsp_config_reference.h is renamed to r_bsp_config.h). For the r_bsp the reference configuration file can be found in +the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file +can be found in the 'ref' folder of the FIT Module. diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h new file mode 100644 index 000000000..189b6ef5d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_bsp_interrupt_config.h @@ -0,0 +1,222 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupt_config.h +* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 31.05.2019 1.00 First Release +***********************************************************************************************************************/ +#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE +#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you + * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you + * would do the following: + * + * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 + */ + +/* Interrupt B Sources. + * -Valid vector numbers are 128-207. + * -There are more vector slots for B sources than actual B sources. By default none of the CAN2 interrupts are + * mapped. + * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default. + * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be + * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0' + * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots. + */ +#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128 +#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175 +#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 192 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 193 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 194 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 195 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 196 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 197 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 198 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 199 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 200 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 201 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 202 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 203 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 204 + +/* Interrupt A Sources. + * -Valid vector numbers are 208-255. + * -There are more A sources than A vector slots. By default none of the GPTW interrupts and the ESC interrupts are + * mapped. + * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default. + */ +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3 +#define BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS 251 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I 252 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I 253 + +#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_byteq_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_byteq_config.h new file mode 100644 index 000000000..512a28eb2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_byteq_config.h @@ -0,0 +1,62 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + + +#endif /* BYTEQ_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_dtc_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_dtc_rx_config.h new file mode 100644 index 000000000..c0ac30518 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_dtc_rx_config.h @@ -0,0 +1,97 @@ +/* Generated configuration header file - do not edit */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_config.h +* Description : Configures the DTC drivers +******************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.01.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Added #define DTC_CFG_USE_SEQUENCE_TRANSFER. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +*******************************************************************************/ +#ifndef DTC_RX_CONFIG_H +#define DTC_RX_CONFIG_H + +#define DTC_DISABLE (0) +#define DTC_ENABLE (1) +/* + * SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + * 0 : Compiles out parameter checking. + * 1 : Includes parameter checking. + * Default value is set to BSP_CFG_PARAM_CHECKING_ENABLE to + * re-use the system default setting. +*/ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* + * SPECIFY WHETHER THE DTCER REGISTERS WILL BE CLEARED IN R_DTC_OPEN() + * DTC_DISABLE : Do nothing. + * DTC_ENABLE : Clear all DTCER registers in R_DTC_Open(). +*/ +#define DTC_CFG_DISABLE_ALL_ACT_SOURCE (DTC_ENABLE) + +/* + * SPECIFY WHICH ADDRESS MODE IS SUPPORTED BY DTC + * DTC_DISABLE : Select the Full address mode. + * DTC_ENABLE : Select the Short address mode. +*/ +#define DTC_CFG_SHORT_ADDRESS_MODE (DTC_DISABLE) + +/* + * SPECIFY WHETHER THE TRANSFER DATA READ SKIP IS ENABLED + * DTC_DISABLE : Disable Transfer Data Read Skip. + * DTC_ENABLE : Enable Transfer Data Read Skip. +*/ +#define DTC_CFG_TRANSFER_DATA_READ_SKIP_EN (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE DMAC FIT MODULE IS USED WITH DTC FIT MODULE + * DTC_DISABLE : DMAC FIT module is not used with DTC FIT module. + * DTC_ENABLE : DMAC FIT module is used with DTC FIT module. +*/ +#define DTC_CFG_USE_DMAC_FIT_MODULE (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE SEQUENCE TRANSFER IS USED + * Also, set DTC_DISABLE to DTC_CFG_SHORT_ADDRESS_MODE. + * DTC_DISABLE : Not use sequence transfer. + * DTC_ENABLE : Use sequence transfer. +*/ +#define DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_ENABLE) + + +#endif /* DTC_RX_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_gpio_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_gpio_rx_config.h new file mode 100644 index 000000000..6966431d9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_gpio_rx_config.h @@ -0,0 +1,47 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_sci_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_sci_rx_config.h new file mode 100644 index 000000000..dd172ccf9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_config/r_sci_rx_config.h @@ -0,0 +1,199 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (1) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * RX MCU supported channels + * + * CH# 110 111 113 130 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N RX23E-A + * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------- + * CH0 X Xa X X X X Xn X X X + * CH1 X X* X* Xu X X Xu Xu Xu X X Xs X X X X X X X Xu + * CH2 X X X Xu X X X + * CH3 X X Xs X X X + * CH4 X X Xn X X X + * CH5 X X X X X Xu X X X X X X X X X X X X X X + * CH6 X X X X X X X X Xn X X Xu X X X + * CH7 Xu Xu Xn X X X + * CH8 X Xa X X X X X X Xu X X X + * CH9 X Xa X X X Xs X X X X X + * CH10 X X X X + * CH11 X Xs X X X X X + * CH12 X X X X X X X X Xs X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (0) +#define SCI_CFG_CH1_INCLUDED (0) +#define SCI_CFG_CH2_INCLUDED (1) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (0) +#define SCI_CFG_CH6_INCLUDED (0) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (0) +#define SCI_CFG_CH9_INCLUDED (1) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (1) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY) 1 lowest, 15 highest */ + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj and SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +#endif /* SCI_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h new file mode 100644 index 000000000..5dee62a9f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h @@ -0,0 +1,297 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_if.h +* Description : Functions for DTC driver +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Moved struct dtc_transfer_data_cfg_t to r_dtc_rx_target_if.h +* : Added include pass of target mcu interface header file. +* : Added R_DTC_CreateSeq() function. +* : 31.01.2017 2.06 Modified r_dtc_rx.c. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 18.06.2019 3.01 Modified r_dtc_rx_private.h. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. + : 12.11.2019 3.21 Removed definitions for MTU5 in DTC activation interrupt source for RX23W. +* : 25.11.2019 3.30 Added support for RX13T. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +* : 31.03.2020 3.50 Added support for RX23E-A. +*******************************************************************************/ +#ifndef DTC_RX_IF_H +#define DTC_RX_IF_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Configuration for this package. */ +#include "r_dtc_rx_config.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define DTC_VERSION_MAJOR (3) +#define DTC_VERSION_MINOR (50) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +/* Configurable options for DTC Transfer mode */ +typedef enum e_dtc_transfer_mode +{ + DTC_TRANSFER_MODE_NORMAL = (0), /* = (0 << 6): Normal mode */ + DTC_TRANSFER_MODE_REPEAT = (1 << 6), /* Repeat mode */ + DTC_TRANSFER_MODE_BLOCK = (2 << 6) /* Block mode */ +} dtc_transfer_mode_t; + +/* Configurable options for DTC Data transfer size */ +typedef enum e_dtc_data_size +{ + DTC_DATA_SIZE_BYTE = (0), /* = (0 << 4): 8-bit (byte) data */ + DTC_DATA_SIZE_WORD = (1 << 4), /* 16-bit (word) data */ + DTC_DATA_SIZE_LWORD = (2 << 4) /* 32-bit (long word) data */ +} dtc_data_size_t; + +/* Configurable options for Source address addressing mode */ +typedef enum e_dtc_src_addr_mode +{ + DTC_SRC_ADDR_FIXED = (0), /* = (0 << 2): Source address is fixed. */ + DTC_SRC_ADDR_INCR = (2 << 2), /* Source address is incremented after each transfer. */ + DTC_SRC_ADDR_DECR = (3 << 2) /* Source address is decremented after each transfer. */ +} dtc_src_addr_mode_t; + +/* Configurable options for Chain transfer */ +typedef enum e_dtc_chain_transfer +{ + DTC_CHAIN_TRANSFER_DISABLE = (0), /* Disable Chain transfer. */ + DTC_CHAIN_TRANSFER_ENABLE = (1 << 7) /* Enable Chain transfer. */ +} dtc_chain_transfer_t; + +/* Configurable options for how chain transfer is performed. */ +typedef enum e_dtc_chain_transfer_mode +{ + DTC_CHAIN_TRANSFER_CONTINUOUSLY = (0), /* = (0 << 6): Chain transfer is performed continuously. */ + DTC_CHAIN_TRANSFER_NORMAL = (1 << 6) /* Chain transfer is performed only when the counter is changed to 0 or CRAH. */ +} dtc_chain_transfer_mode_t; + +/* Configurable options for Interrupt */ +typedef enum e_dtc_interrupt +{ + DTC_INTERRUPT_AFTER_ALL_COMPLETE = (0), /* Interrupt is generated when specified data transfer is completed. */ + DTC_INTERRUPT_PER_SINGLE_TRANSFER = (1 << 5) /* Interrupt is generated when each transfer time is completed. */ +} dtc_interrupt_t; + +/* Configurable options for Side to be repeat or block */ +typedef enum e_dtc_repeat_block_side +{ + DTC_REPEAT_BLOCK_DESTINATION = (0), /* = (0 << 4): Destination is repeat or block area. */ + DTC_REPEAT_BLOCK_SOURCE = (1 << 4) /* Source is repeat or block area. */ +} dtc_repeat_block_side_t; + +/* Configurable options for Destination address addressing mode */ +typedef enum e_dtc_dest_addr_mode +{ + DTC_DES_ADDR_FIXED = (1 << 2), /* Destination address is fixed. */ + DTC_DES_ADDR_INCR = (2 << 2), /* Destination address is incremented after each transfer. */ + DTC_DES_ADDR_DECR = (3 << 2) /* Destination address is decremented after each transfer. */ +} dtc_dest_addr_mode_t; + +/* Configurable options for Write-back Disable */ +typedef enum e_dtc_write_back +{ + DTC_WRITEBACK_ENABLE = (0), + DTC_WRITEBACK_DISABLE = (1) +} dtc_write_back_t; + +/* Configurable options for Sequence Transfer End */ +typedef enum e_dtc_sequence_end +{ + DTC_SEQUENCE_TRANSFER_CONTINUE = (0), + DTC_SEQUENCE_TRANSFER_END = (1) +} dtc_sequence_end_t; + +/* Configurable options for Index Table Reference */ +typedef enum e_dtc_refer_index_table +{ + DTC_REFER_INDEX_TABLE_DISABLE = (0), + DTC_REFER_INDEX_TABLE_ENABLE = (1 << 1) +} dtc_refer_index_table_t; + +/* Configurable options for Displacement Addition */ +typedef enum e_dtc_disp_add +{ + DTC_SRC_ADDR_DISP_ADD_DISABLE = (0), + DTC_SRC_ADDR_DISP_ADD_ENABLE = (1) +} dtc_disp_add_t; + +/* Enumerate list that can be selected as DTC activation source + * enum enum_dtce: is included from iodefine.h + */ +typedef enum enum_dtce dtc_activation_source_t; + +typedef enum e_dtc_command { + DTC_CMD_DTC_START, /* DTC will can accept activation requests. */ + DTC_CMD_DTC_STOP, /* DTC will not accept new activation request. */ + DTC_CMD_ACT_SRC_ENABLE, /* Enable an activation source specified by vector number. */ + DTC_CMD_ACT_SRC_DISABLE, /* Disable an activation source specified by vector number. */ + DTC_CMD_DATA_READ_SKIP_ENABLE, /* Enable Transfer Data Read Skip. */ + DTC_CMD_DATA_READ_SKIP_DISABLE, /* Disable Transfer Data Read Skip. */ + DTC_CMD_STATUS_GET, /* Get the current status of DTC. */ + DTC_CMD_CHAIN_TRANSFER_ABORT, /* Abort the current Chain transfer process. */ + DTC_CMD_SEQUENCE_TRANSFER_ENABLE, /* Sequence transfer is enabled. */ + DTC_CMD_SEQUENCE_TRANSFER_DISABLE, /* Sequence transfer is disabled. */ + DTC_CMD_SEQUENCE_TRANSFER_ABORT, /* Abort the sequence transfer. */ + DTC_CMD_CHANGING_DATA_FORCIBLY_SET /* Changing data forcibly set by R_DTC_Create(). */ +} dtc_command_t; + +typedef enum e_dtc_err /* DTC API error codes */ +{ + DTC_SUCCESS_DMAC_BUSY = 0, /* One or some DMAC resources are locked by another process. */ + DTC_SUCCESS, + DTC_ERR_OPENED, /* DTC was initialized already. */ + DTC_ERR_NOT_OPEN, /* DTC module is not initialized yet. */ + DTC_ERR_INVALID_ARG, /* Arguments are invalid. */ + DTC_ERR_INVALID_COMMAND, /* Command parameters are invalid. Or, forced data change failed. */ + DTC_ERR_NULL_PTR, /* Argument pointers are NULL. */ + DTC_ERR_BUSY, /* The DTC resources are locked by another process. */ + DTC_ERR_ACT /* Data transfer is in progress. */ +} dtc_err_t; + +/* Transfer data type */ +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ + +typedef struct st_transfer_data { /* 3 long-words */ + uint32_t lw1; + uint32_t lw2; + uint32_t lw3; +} dtc_transfer_data_t; + +#else /* Full-address mode */ +typedef struct st_transfer_data { /* 4 long-words */ + uint32_t lw1; + uint32_t lw2; + uint32_t lw3; + uint32_t lw4; +} dtc_transfer_data_t; +#endif + +/* Transfer data configuration */ +/* Moved struct dtc_transfer_data_cfg_t to r_dtc_rx_target_if.h */ +/* Include target mcu interface header file. */ +#if defined(BSP_MCU_RX23T) + #include ".\src\targets\rx23t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX24T) + #include ".\src\targets\rx24t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX24U) + #include ".\src\targets\rx24u\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX130) + #include ".\src\targets\rx130\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX113) + #include ".\src\targets\rx113\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX111) + #include ".\src\targets\rx111\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX110) + #include ".\src\targets\rx110\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX64M) + #include ".\src\targets\rx64m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX71M) + #include ".\src\targets\rx71m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72T) + #include ".\src\targets\rx72t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX231) + #include ".\src\targets\rx231\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX23E_A) + #include ".\src\targets\rx23e-a\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX230) + #include ".\src\targets\rx230\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX65N) + #include ".\src\targets\rx65n\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX66T) + #include ".\src\targets\rx66t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX66N) + #include ".\src\targets\rx66n\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX23W) + #include ".\src\targets\rx23w\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72M) + #include ".\src\targets\rx72m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX13T) + #include ".\src\targets\rx13t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72N) + #include ".\src\targets\rx72n\r_dtc_rx_target_if.h" +#else + #error "This MCU is not supported by the current r_dtc_rx module." +#endif + +typedef struct st_dtc_stat { + uint8_t vect_nr; /* the current vector number */ + bool in_progress; /* Active flag of DTC module */ +} dtc_stat_t; + +typedef struct st_dtc_cmd_arg { + dtc_activation_source_t act_src; /* The activation source will be controlled */ + uint32_t chain_transfer_nr; /* Number of chain transfer when command is DTC_CMD_CHAIN_TRANSFER_ABORT. */ + dtc_transfer_data_t *p_transfer_data; /* Pointer to start address of Transfer data area on RAM */ + dtc_transfer_data_cfg_t *p_data_cfg; /* Pointer to contains the settings for Transfer data */ +} dtc_cmd_arg_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +dtc_err_t R_DTC_Open(void); +dtc_err_t R_DTC_Create(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t chain_transfer_nr); +dtc_err_t R_DTC_CreateSeq(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t sequence_transfer_nr, + uint8_t sequence_no); +dtc_err_t R_DTC_Close(void); +dtc_err_t R_DTC_Control(dtc_command_t command, dtc_stat_t *p_stat, dtc_cmd_arg_t *p_args); +uint32_t R_DTC_GetVersion(void); + +#endif /* DTC_RX_IF_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/readme.txt new file mode 100644 index 000000000..f68a15cab --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/readme.txt @@ -0,0 +1,245 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION + +r_dtc_rx +========= + +Document Number +--------------- +R01AN1819EJ0350 +R01AN1819JJ0350 + +Version +------- +v3.50 + +Overview +-------- +The DTC driver provides a method to transmit the data using Data Transfer Controller (DTC). +The driver includes API functions to initialize DTC, create Transfer data, Control and get status of DTC. +The driver can be reduced in size by removing code used for parameter checking. +All configuration options can be found in "r_config\r_dtc_rx_config.h". +An original copy of the configuration file is stored in "r_dtc_rx\ref\r_dtc_rx_config_reference.h". + +Features +-------- +* Support Normal trasnsfer mode, Repeat trasnsfer mode and Block trasnsfer mode. +* Support chain transfer + +Supported MCUs +-------------- +* RX110 MCU +* RX111 MCU +* RX113 MCU +* RX130 MCU +* RX230 MCU +* RX231 MCU +* RX23E-A MCU +* RX64M MCU +* RX71M MCU +* RX23T MCU +* RX24T MCU +* RX24U MCU +* RX65N MCU +* RX651 MCU +* RX66T MCU +* RX66N MCU +* RX72T MCU +* RX23W MCU +* RX72M MCU +* RX13T MCU +* RX72N MCU + +Boards Tested On +---------------- +* RSKRX110 +* RSKRX111 +* RSKRX113 +* RSKRX130 +* RSKRX130_512KB +* RSKRX230 +* RSKRX231 +* RSKRX23E-A +* RSKRX64M +* RSKRX71M +* RSKRX23T +* RSKRX24T +* RSKRX24U +* RSKRX65N +* RSKRX65N_2MB +* RSKRX66T +* RSKRX66N +* RSKRX72T +* RSKRX23W +* RSKRX72M +* RSKRX13T +* RSKRX72N +Limitations +----------- +* None + +Peripherals Used Directly +------------------------- +* Data Transfer Controller (DTC) + +Required Packages +----------------- +* r_bsp + +How to add to your project +-------------------------- +This module must be added to each project in which it is used. +Renesas recommends using "Smart Configurator" described in (1) or (3). +However, "Smart Configurator" only supports some RX devices. +Please use the methods of (2) or (4) for unsupported RX devices. + +(1) Adding the FIT module to your project using "Smart Configurator" in e2 studio +By using the "Smart Configurator" in e2 studio, +the FIT module is automatically added to your project. +Refer to "Renesas e2 studio Smart Configurator User Guide (R20AN0451)" for details. + +(2) Adding the FIT module to your project using "FIT Configurator" in e2 studio +By using the "FIT Configurator" in e2 studio, +the FIT module is automatically added to your project. +Refer to "Adding Firmware Integration Technology Modules to Projects (R01AN1723)" for details. + +(3) Adding the FIT module to your project using "Smart Configurator" on CS+ +By using the "Smart Configurator Standalone version" in CS+, +the FIT module is automatically added to your project. +Refer to "Renesas e2 studio Smart Configurator User Guide (R20AN0451)" for details. + +(4) Adding the FIT module to your project in CS+ +In CS+, please manually add the FIT module to your project. +Refer to "Adding Firmware Integration Technology Modules to CS+ Projects (R01AN1826)" for details. + +Toolchain(s) Used +----------------- +* Renesas RX v3.02.00 +* GCC for Renesas RX 8.03.00.201904 +* IAR C/C++ Compiler for Renesas RX 4.12.1 + +File Structure +-------------- +r_dtc_rx +| r_dtc_rx_if.h +| readme.txt +| ++---doc +| | +| +---en +| | r01an1819ej{VERSION_NUMBER}-rx-dtc-dmac2.pdf +| +---ja +| r01an1819jj{VERSION_NUMBER}-rx-dtc-dmac2.pdf +| ++---ref +| r_dtc_rx_config_reference.h +| ++---src + | r_dtc_rx.c + | r_dtc_rx_private.h + | + +---targets + | + +---rx23t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx23w + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx24t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx24u + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx64m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx65n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx66t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx66n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx71m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx110 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx111 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx113 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx130 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx13t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx230 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx231 + r_dtc_rx_target.c + r_dtc_rx_target.h + r_dtc_rx_target_if.h + | + +---rx23E-A + r_dtc_rx_target.c + r_dtc_rx_target.h + r_dtc_rx_target_if.h + +r_config + r_dtc_rx_config.h + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h new file mode 100644 index 000000000..d0058ed06 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h @@ -0,0 +1,96 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_config.h +* Description : Configures the DTC drivers +******************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.01.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Added #define DTC_CFG_USE_SEQUENCE_TRANSFER. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +*******************************************************************************/ +#ifndef DTC_RX_CONFIG_H +#define DTC_RX_CONFIG_H + +#define DTC_DISABLE (0) +#define DTC_ENABLE (1) +/* + * SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + * 0 : Compiles out parameter checking. + * 1 : Includes parameter checking. + * Default value is set to BSP_CFG_PARAM_CHECKING_ENABLE to + * re-use the system default setting. +*/ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* + * SPECIFY WHETHER THE DTCER REGISTERS WILL BE CLEARED IN R_DTC_OPEN() + * DTC_DISABLE : Do nothing. + * DTC_ENABLE : Clear all DTCER registers in R_DTC_Open(). +*/ +#define DTC_CFG_DISABLE_ALL_ACT_SOURCE (DTC_ENABLE) + +/* + * SPECIFY WHICH ADDRESS MODE IS SUPPORTED BY DTC + * DTC_DISABLE : Select the Full address mode. + * DTC_ENABLE : Select the Short address mode. +*/ +#define DTC_CFG_SHORT_ADDRESS_MODE (DTC_DISABLE) + +/* + * SPECIFY WHETHER THE TRANSFER DATA READ SKIP IS ENABLED + * DTC_DISABLE : Disable Transfer Data Read Skip. + * DTC_ENABLE : Enable Transfer Data Read Skip. +*/ +#define DTC_CFG_TRANSFER_DATA_READ_SKIP_EN (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE DMAC FIT MODULE IS USED WITH DTC FIT MODULE + * DTC_DISABLE : DMAC FIT module is not used with DTC FIT module. + * DTC_ENABLE : DMAC FIT module is used with DTC FIT module. +*/ +#define DTC_CFG_USE_DMAC_FIT_MODULE (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE SEQUENCE TRANSFER IS USED + * Also, set DTC_DISABLE to DTC_CFG_SHORT_ADDRESS_MODE. + * DTC_DISABLE : Not use sequence transfer. + * DTC_ENABLE : Use sequence transfer. +*/ +#define DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) + + +#endif /* DTC_RX_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c new file mode 100644 index 000000000..1d46b93ee --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c @@ -0,0 +1,1127 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +/******************************************************************************* +* File Name : r_dtc_rx.c +* Description : Functions for using DTC on RX devices. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Changed Tool-Chain version. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : Added RX130, RX23T and RX24T. +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Supported sequence transfer. +* : Added R_DTC_CreateSeq() function. +* : Added DTC_CMD_SEQUENCE_TRANSFER_ENABLE, +* : DTC_CMD_SEQUENCE_TRANSFER_DISABLE and DTC_CMD_SEQUENCE_TRANSFER_ABORT +* : to R_DTC_Control(). +* : 31.01.2017 2.06 Added the default setting of "writeback_disable", "sequence_end", +* : "refer_index_table_enable" and "disp_add_enable" in R_DTC_Create() +* : if the DTC IP version is DTCb or later. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : Fixed to correspond to Renesas coding rule. +* : Added DTC_CMD_CHANGING_DATA_FORCIBLY_SET command to R_DTC_Control(). +* : 28.09.2018 2.10 Supported RX66T. +* : Fixed to correspond to Renesas coding rule. +* : Add WAIT_LOOP comments. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +* Fixed DTC setting procedure. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. + Fixed warnings in IAR. +* : 25.11.2019 3.30 Added support for RX13T. +* : Modified comment of API function to Doxygen style. +* : Fixed to comply with GSCE Coding Standards Rev.6.00. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Defines for DTC support */ +#include +#include "r_dtc_rx_if.h" +#include ".\src\r_dtc_rx_private.h" + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DTC_PRV_ACT_BIT_MASK (0x8000) /* DTC Active flag (DTCSTS.ACT) bit mask */ +#define DTC_PRV_VECT_NR_MASK (0x00FF) /* DTC-Activating Vector Number bits mask */ +#define DTC_PRV_MAX_16BITS_COUNT_VAL (65536) /* The maximum value of 16bit count value */ +#define DTC_PRV_MAX_8BITS_COUNT_VAL (256) /* The maximum value of 8bit count value */ +#define DTC_PRV_MIN_COUNT_VAL (1) /* The minimum of count value and block size */ +#define DTC_PRV_ESPSEL_BIT_MASK (0x8000) /* DTC Sequence transfer vector number setting bit mask */ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +extern const dtc_activation_source_t g_source_array[]; +uint32_t * gp_dtc_table_work[2]; + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ +static bool s_is_opened = false; /* Indicate whether DTC is opened. */ + +static dtc_err_t r_dtc_set_transfer_data(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_cfg); +static void r_dtc_clear_all_dtce_bits(void); +static bool r_dtc_abort_chain_transfer(uint32_t chain_transfer_nr); +static bool r_dtc_acquire_hw_lock(void); +static void r_dtc_release_hw_lock(void); +static bool r_dtc_check_dmac_locking_sw(void); +static dtc_err_t r_dtc_check_create_param(dtc_transfer_data_t *p_transfer_data, dtc_transfer_data_cfg_t *p_data_cfg); + + + +/*********************************************************************************************************************** +* Function Name: R_DTC_Open +********************************************************************************************************************//** +* @brief This function is run first when using the APIs of the DTC FIT module. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_OPENED DTC has been initialized already. +* @retval DTC_ERR_BUSY Resource has been locked by other process. +* @details Locks*1 the DTC and starts supplying clock to DTC, then initializes DTC vector table, address mode, +* Data Transfer Read Skip. When setting DTC_CFG_DISABLE_ALL_ACT_SOURCE to DTC_ENABLE in r_dtc_rx_config.h, all DTCER +* registers are cleared. When setting DTC_CFG_USE_SEQUENCE_TRANSFER to DTC_ENABLE, the area used in DTC index table is +* secured.\n\n +* Note: 1. The DTC FIT module uses the r_bsp default lock function. As a result, the DTC is in the locked state after a +* successful end. +* @note Set \#define BSP_CFG_HEAP_BYTES in r_bsp_config.h to the value greater than \#define DTC_VECTOR_TABLE_SIZE_BYTES +* in r_dtc_rx_target.h. This is to secure the DTC Vector table area using the malloc() function in the DTC FIT module. +*/ +dtc_err_t R_DTC_Open(void) +{ + uint8_t * p_dtc_table_work2 = 0; + + /* Check hw lock require */ + if (false == r_dtc_acquire_hw_lock()) + { + /* Lock has already been acquired by another task. Need to try again later. */ + return DTC_ERR_BUSY; + } + + if (true == s_is_opened) /* DTC is opened. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_OPENED; + } + + /* Allocate memory size */ + gp_dtc_table_work[0] = (uint32_t *)malloc(DTC_VECTOR_TABLE_SIZE_BYTES); + + if (0 == gp_dtc_table_work[0]) + { + r_dtc_release_hw_lock(); + return DTC_ERR_OPENED; + } + + gp_dtc_table_work[1] = gp_dtc_table_work[0]; + + /* Cast type of "gp_dtc_table_work" to match type of "p_dtc_table_work2" */ + p_dtc_table_work2 = (uint8_t *)gp_dtc_table_work[1]; + p_dtc_table_work2 = (p_dtc_table_work2 + 0x400); + + /* Cast type of "p_dtc_table_work2" to match type of "p_dtc_table_work2" */ + p_dtc_table_work2 = (uint8_t *)((uint32_t)p_dtc_table_work2 & 0xfffffc00); + +#if (DTC_ENABLE == DTC_CFG_DISABLE_ALL_ACT_SOURCE) /* Clear all DTCER registers. */ + + r_dtc_clear_all_dtce_bits(); + +#endif /* DTC_ENABLE == DTC_CFG_DISABLE_ALL_ACT_SOURCE */ + + /* Cancel module stop for DMAC and DTC. */ + r_dtc_module_enable(); + + /* Set DTC Vector Table Base Register. */ + DTC.DTCVBR = p_dtc_table_work2; + +#if (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) + p_dtc_table_work2 = (p_dtc_table_work2 + 0x400); + + /* Set address of the dtc index table. */ + DTC.DTCIBR = p_dtc_table_work2; +#endif /* (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ + + /* Set DTC address mode. */ +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + /*Turn on Short Address Mode*/ + DTC.DTCADMOD.BIT.SHORT = 1; +#else /* Full-address mode */ + DTC.DTCADMOD.BIT.SHORT = 0; +#endif /* DTC_CFG_SHORT_ADDRESS_MODE */ + + /* Set the Transfer Data Read Skip bit. */ +#if (DTC_ENABLE == DTC_CFG_TRANSFER_DATA_READ_SKIP_EN) /* Enable Data Read Skip. */ + DTC.DTCCR.BIT.RRS = 1; +#else /* Disable Data Read Skip. */ + DTC.DTCCR.BIT.RRS = 0; +#endif /* DTC_TRANSFER_DATA_READ_SKIP_EN */ + s_is_opened = true; /* DTC module is initialized successfully. */ + + return DTC_SUCCESS; +} +/* End of function R_DTC_Open */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Create +********************************************************************************************************************//** +* @brief This function is used to make DTC register settings and to specify the activation source. +* @param[in] act_source Activation source. +* @param[in] p_transfer_data Pointer to start address of Transfer data area on RAM. +* @param[in] p_data_cfg Pointer to settings for Transfer data. In the case of DTCb, the setting to the following +* structure members is invalid. This function sets the following values.\n +* p_data_cfg->writeback_disable = DTC_WRITEBACK_ENABLE;\n +* p_data_cfg->sequence_end = DTC_SEQUENCE_TRANSFER_CONTINUE;\n +* p_data_cfg->refer_index_table_enable = DTC_REFER_INDEX_TABLE_DISABLE;\n +* p_data_cfg->disp_add_enable = DTC_SRC_ADDR_DISP_ADD_DISABLE;\n +* @param[in] chain_transfer_nr Number of chain transfer.\n +* The number of Transfer data and corresponding configurations is (number of chain transfer + 1). +* Example: if chain_transfer_nr = 1, it means that there are 2 continuous Transfer data and 2 corresponding configurations +* and the first configuration enable the chain transfer.\n +* See Section 3 in application note for details. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_NOT_OPEN DTC is not initialized yet. +* @retval DTC_ERR_INVALID_ARG Parameters are invalid. +* @retval DTC_ERR_NULL_PTR Argument pointers are NULL. +* @details Writes the configuration to Transfer data. Writes the start address of Transfer data corresponding to interrupt +* number into DTC vector table. +* @note Before calling R_DTC_Create(), user must disable the current interrupt request (the interrupt source is passed to +* R_DTC_Create()) by clearing Interrupt Request Enable bit IERm.IENj:\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* Then, enable the interrupt request disabled after R_DTC_Create() is ended. The correspondence between IERm.IENj bit and +* interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of User's Manual: Hardware. +*/ +dtc_err_t R_DTC_Create(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t chain_transfer_nr) +{ + uint32_t count = chain_transfer_nr + 1; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_err_t ret = DTC_SUCCESS; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + + ret = r_dtc_check_create_param(p_transfer_data, p_data_cfg); + if (DTC_SUCCESS != ret) + { + return ret; + } + + if (false == s_is_opened) /* DTC is not initialized yet. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[act_source].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[act_source].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + +#if (DTC_IP_VER_DTCb <= DTC_IP) + /* Set the 0 value. */ + p_data_cfg->writeback_disable = DTC_WRITEBACK_ENABLE; + p_data_cfg->sequence_end = DTC_SEQUENCE_TRANSFER_CONTINUE; + p_data_cfg->refer_index_table_enable = DTC_REFER_INDEX_TABLE_DISABLE; + p_data_cfg->disp_add_enable = DTC_SRC_ADDR_DISP_ADD_DISABLE; +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + if (r_dtc_set_transfer_data(p_transfer_data, p_data_cfg) != DTC_SUCCESS) + { + /* Fail to apply configurations for Transfer data. */ + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_ARG; + } + else + { + p_data_cfg++; + p_transfer_data++; + } + count--; + } + + /* The row in Vector table corresponding to act_source */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCVBR + (4 * act_source)); + + /* Write start address of Transfer data to Vector table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + + /* Restore RRS bit. */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + + return DTC_SUCCESS; +} +/* End of function R_DTC_Create */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_CreateSeq +********************************************************************************************************************//** +* @brief This function performs the setting of the DTC register used in the sequence transfer and the activation source. +* @param[in] act_source Activation source +* @param[in] p_transfer_data Pointer to the start address in the transfer information area in RAM. +* @param[in] p_data_cfg Pointer to the transfer information setting\n +* Set the following structure members.\n +* p_data_cfg->writeback_disable\n +* p_data_cfg->sequence_end\n +* p_data_cfg->refer_index_table_enable\n +* p_data_cfg->disp_add_enable\n +* @param[in] sequence_transfer_nr Transfer information counts per sequence transfer (0 - 4294967295)\n +* See Section 3 in application note for details.\n\n +* @param[in] sequence_no Sequence number (0 - 255)\n +* The type definition of the transfer information and the data structure are the same as R_DTC_Create(). Total of 256 ways +* of the sequence information can be set. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_NOT_OPEN DTC is not initialized yet. +* @retval DTC_ERR_INVALID_ARG Arguments are invalid. +* @retval DTC_ERR_NULL_PTR Argument pointers are NULL. +* @details This function writes the setting information to the transfer information. Start address of the transfer +* information for the sequence number is written to DTC index table. +* @note Before calling R_DTC_CreateSeq(), user must disable the current interrupt request (the interrupt source is passed +* to R_DTC_CreateSeq()) by clearing Interrupt Request Enable bit (IERm.IENj):\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* Then, enable the interrupt request disabled after R_DTC_CreateSeq() is ended. The correspondence between IERm.IENj bit +* and interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of User's Manual: +* Hardware. +*/ +dtc_err_t R_DTC_CreateSeq(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t sequence_transfer_nr, + uint8_t sequence_no) +{ +#if (DTC_DISABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) + return DTC_ERR_INVALID_ARG; +#else + uint32_t count = sequence_transfer_nr; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_err_t ret = DTC_SUCCESS; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + + if (0 != count) + { + ret = r_dtc_check_create_param(p_transfer_data, p_data_cfg); + if (DTC_SUCCESS != ret) + { + return ret; + } + } + + if (false == s_is_opened) /* DTC is not initialized yet. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[act_source].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[act_source].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + /* The row in dtc index table corresponding to sequence_no. */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCIBR + (4 * sequence_no)); + + if (0 == count) + { + /* Set the cpu interrupt to the sequence number. */ + *p_ptr = DTC_INVALID_CMND; + } + else + { + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + /* Fail to apply configurations for Transfer data. */ + if (r_dtc_set_transfer_data(p_transfer_data, p_data_cfg) != DTC_SUCCESS) + { + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_ARG; + } + else + { + p_data_cfg++; + p_transfer_data++; + } + count--; + } + + /* Write start address of Transfer data to dtc index table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + } + + /* Restore RRS bit. */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + + return DTC_SUCCESS; +#endif /* (DTC_DISABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ +} +/* End of function R_DTC_CreateSeq */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Close +********************************************************************************************************************//** +* @brief This function is used to release the resources of the DTC. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_SUCCESS_DMAC_BUSY Successful operation.One or some DMAC resources are locked. +* @details Unlocks*1 the DTC and disable all DTC activation source by clearing the DTC Activation Enable Register DTCERn; +* stop supplying clock to DTC and put it to Module stop state. If in addition all DMAC channels have been unlocked, the +* function sets the DMAC and DTC to the module stop state.*2\n\n +* Note:\n 1. The DTC FIT module uses the r_bsp default lock function. As a result, the DTC is in the unlocked state after +* a successful end.\n 2. Because a shared bit is used as both the DMAC module stop setting bit and the DTC module stop +* setting bit, the function confirms that all DMAC channels are unlocked before making the module stop setting. (For +* details, see the "Low Power Consumption" section in the User's Manual: Hardware.)\n +* See Section 3 in application note for details. +* @note When controlling the DMAC without using the DMAC FIT module, make sure to monitor the usage of the DMAC and +* control locking and unlocking of the DMAC so that calling this function does not set the DMAC to the module stop state. +* Note that even if the DMAC has not been activated, it is necessary to keep it in the locked state when not making DMAC +* transfer settings. +*/ +dtc_err_t R_DTC_Close(void) +{ + /* Clear DTCE bits. */ + r_dtc_clear_all_dtce_bits(); + + /* Stop DTC module. */ + DTC.DTCST.BIT.DTCST = 0; + + /* DTC is closed. */ + s_is_opened = false; + + /* Cast type of "gp_dtc_table_work" to match type of parameter in "free" function */ + free((void *)gp_dtc_table_work[1]); + gp_dtc_table_work[1] = NULL; + + /* Check DMAC locking. */ + if (true == r_dtc_check_dmac_locking_sw()) + { + /* Disable the power for DTC and DMAC module. */ + r_dtc_module_disable(); + + /* Release hardware lock. */ + r_dtc_release_hw_lock(); + } + else + { + /* Release hardware lock. */ + r_dtc_release_hw_lock(); + return DTC_SUCCESS_DMAC_BUSY; + } + + return DTC_SUCCESS; +} +/* End of function R_DTC_Close */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Control +********************************************************************************************************************//** +* @brief This function controls the operation of the DTC. +* @param[in] command DTC control command +* @param[in] p_stat Pointer to the status when command is DTC_CMD_STATUS_GET.\n +* See Section 3 in application note for details. +* @param[in] p_args Pointer to the argument structure when command is DTC_CMD_ACT_SRC_ENABLE,DTC_CMD_ACT_SRC_DISABLE, +* DTC_CMD_CHAIN_TRANSFER_ABORT, DTC_CMD_SEQUENCE_TRANSFER_ENABLE, or DTC_CMD_CHANGING_DATA_FORCIBLY_SET.\n +* See Section 3 in application note for details. +* @retval [DTC_SUCCESS] Successful operation +* @retval [DTC_ERR_NOT_OPEN] DTC is not initialized yet. +* @retval [DTC_ERR_INVALID_COMMAND] Command parameters are invalid or DTC_CMD_CHANGING_DATA_FORCIBLY_SET command error. +* @retval [DTC_ERR_NULL_PTR] Argument pointers are NULL. +* @retval [DTC_ERR_ACT] Data transfer is in progress. +* @details Processing is performed depending on the command.\n +* See Section 3 in application note for details. +* @note When the command is DTC_CMD_GET_STATUS, the vector number is valid if only the DTC is in the progress +* (p_stat->in_progress is true). With command DTC_CMD_ENABLE_ACT_SRC, DTC_CMD_DISABLE_ACT_SRC or +* DTC_CMD_SEQUENCE_TRANSFER_ABORT, before calling R_DTC_Control(), user must disable the current interrupt request +* (the interrupt source is passed to R_DTC_Control()) by clearing Interrupt Request Enable bit (IERm.IENj);\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* After processing of R_DTC_Control() is ended, the interrupt request disabled is enabled. The correspondence between +* IERm.IENj bit and interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of +* User's Manual: Hardware. With abort processing, user must re-create the Chain transfer data after the transfer is +* aborted because the old Transfer data are destroyed. If an invalid value is attempted to set with +* DTC_CMD_CHANGING_DATA_FORCIBLY_SET, R_DTC_Control() returns DTC_ERR_INVALID_COMMAND R_DTC_Control() may already update +* some registers before the invalid value is detected. This occurs only when users try +* to change FORCIBLY DTC with Invalid Value. +*/ +dtc_err_t R_DTC_Control(dtc_command_t command, dtc_stat_t *p_stat, dtc_cmd_arg_t *p_args) +{ + uint32_t count = 0; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + +#if (1 == DTC_CFG_PARAM_CHECKING_ENABLE) + + if ((DTC_CMD_STATUS_GET == command) && (NULL == p_stat)) + { + return DTC_ERR_NULL_PTR; + } + else if ((((DTC_CMD_ACT_SRC_ENABLE == command) || (DTC_CMD_ACT_SRC_DISABLE == command)) || + (DTC_CMD_CHAIN_TRANSFER_ABORT == command)) || (DTC_CMD_SEQUENCE_TRANSFER_ENABLE == command)) + { + if (NULL == p_args) /* Require argument */ + { + return DTC_ERR_NULL_PTR; + } + } + else if (DTC_CMD_CHANGING_DATA_FORCIBLY_SET == command) + { + if (NULL == p_args) /* Require argument */ + { + return DTC_ERR_INVALID_COMMAND; + } + if (r_dtc_check_create_param(p_args->p_transfer_data, p_args->p_data_cfg) != DTC_SUCCESS) + { + return DTC_ERR_INVALID_COMMAND; + } + } + else + { + /* do nothing */ + } + +#endif /* DTC_CFG_PARAM_CHECKING_ENABLE */ + + if (false == s_is_opened) + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + switch (command) + { + case DTC_CMD_DTC_START: /* Start DTC module. */ + { + /* DTC Module start*/ + DTC.DTCST.BIT.DTCST = 1; + break; + } + + case DTC_CMD_DTC_STOP: /* Stop DTC module. */ + { + /* DTC Module stop*/ + DTC.DTCST.BIT.DTCST = 0; + break; + } + + case DTC_CMD_DATA_READ_SKIP_ENABLE: /* Enable Transfer Data Read Skip. */ + { + /* Set Read Skip Enable bit*/ + DTC.DTCCR.BIT.RRS = 1; + break; + } + + case DTC_CMD_DATA_READ_SKIP_DISABLE: /* Disable Transfer Data Read Skip. */ + { + /* Clear Read Skip Enable bit*/ + DTC.DTCCR.BIT.RRS = 0; + break; + } + + case DTC_CMD_ACT_SRC_ENABLE: /* Select one interrupt as a DTC activation source. */ + { + /* Set Activation source for DTC*/ + ICU.DTCER[p_args->act_src].BIT.DTCE = 1; + break; + } + + case DTC_CMD_ACT_SRC_DISABLE: /* Remove one interrupt as a DTC activation source. */ + { + /* Clear Activation source*/ + ICU.DTCER[p_args->act_src].BIT.DTCE = 0; + break; + } + + case DTC_CMD_STATUS_GET: + { + /* Check DTC Status*/ + if (0 == (DTC.DTCSTS.WORD & DTC_PRV_ACT_BIT_MASK)) /* DTC transfer operation is not in progress. */ + { + p_stat->in_progress = false; + + /* DTC is not in progress. -> vector number is invalid. */ + } + else /* DTC transfer operation is in progress. */ + { + p_stat->in_progress = true; + + /* Get the current vector number. */ + p_stat->vect_nr = (uint8_t)(DTC.DTCSTS.WORD & DTC_PRV_VECT_NR_MASK); /* get lower 8 bits: 0-7*/ + } + break; + } + + case DTC_CMD_CHAIN_TRANSFER_ABORT: + { + r_dtc_abort_chain_transfer(p_args->chain_transfer_nr); + break; + } + +#if (DTC_IP_VER_DTCb <= DTC_IP) + + case DTC_CMD_SEQUENCE_TRANSFER_ENABLE: + + /* Set the sequence transfer vector number and sequence transfer is enabled. */ + DTC.DTCSQE.WORD = (DTC_PRV_ESPSEL_BIT_MASK | (uint16_t)p_args->act_src); + break; + + case DTC_CMD_SEQUENCE_TRANSFER_DISABLE: + + /* Sequence transfer is disabled. */ + DTC.DTCSQE.WORD &= (~DTC_PRV_ESPSEL_BIT_MASK); + break; + + case DTC_CMD_SEQUENCE_TRANSFER_ABORT: + + /* DTC transfer operation is in progress. */ + if (DTC.DTCSTS.WORD & DTC_PRV_ACT_BIT_MASK) + { + /* Store value of VECN of DTCSQE Register to "tmp" variable */ + uint16_t tmp = DTC.DTCSQE.BIT.VECN; + + /* Compare value of VECN of DTCSTS Register with "tmp" variable */ + if (DTC.DTCSTS.BIT.VECN == tmp) + { + return DTC_ERR_ACT; + } + } + + /* Abort the sequence transfer. */ + DTC.DTCOR.BIT.SQTFRL = 1; + break; + +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + case DTC_CMD_CHANGING_DATA_FORCIBLY_SET: + { + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_args->p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[p_args->act_src].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[p_args->act_src].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + count = p_args->chain_transfer_nr + 1; + + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + if (r_dtc_set_transfer_data(p_args->p_transfer_data, p_args->p_data_cfg) != DTC_SUCCESS) + { + /* Fail to apply configurations for Transfer data. */ + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[p_args->act_src].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_COMMAND; + } + else + { + p_args->p_transfer_data++; + p_args->p_data_cfg++; + } + count--; + } + + /* The row in Vector table corresponding to act_source */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCVBR + (4 * p_args->act_src)); + + /* Write start address of Transfer data to Vector table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[p_args->act_src].BIT.DTCE = dtce_backup; + break; + } + default: + { + return DTC_ERR_INVALID_COMMAND; + break; + } + } + + return DTC_SUCCESS; +} +/* End of function R_DTC_Control */ + +/******************************************************************************* +* Function Name: R_DTC_GetVersion +****************************************************************************//** +* @brief This function is used to get the driver version information. +* @return Version_number Upper 2 bytes: major version, lower 2 bytes: minor version +* @details Returns the version information. +* @note None +*/ +uint32_t R_DTC_GetVersion(void) +{ + uint32_t version = 0; + + version = (DTC_VERSION_MAJOR << 16) | DTC_VERSION_MINOR; + + return version; +} +/* End of function R_DTC_GetVersion */ + +/******************************************************************************* +* Function Name: r_dtc_set_transfer_data +* Description : Applies configurations to a Transfer data area, it is an internal +* function called by R_DTC_Create(); and all arguments are validated +* in R_DTC_Create() +* Arguments : transfer_data - +* Start address of Transfer data +* data_cfg - +* Contains configurations for the Transfer data +* Return Value : DTC_SUCCESS - +* Apply configurations for Transfer data successfully. +* DTC_ERR_INVALID_ARG +* Fail to apply configurations for Transfer data. +*******************************************************************************/ +static dtc_err_t r_dtc_set_transfer_data(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_cfg) +{ + dtc_mra_t t_mra; + dtc_mrb_t t_mrb; + dtc_cra_t t_cra; + dtc_crb_t t_crb; + + /* Cast type of "p_transfer_data" to match type of "p_td_ptr" */ + volatile dtc_internal_registers_t *p_td_ptr = (volatile dtc_internal_registers_t *)p_transfer_data; + + /* Set for MRA - . */ +#if (DTC_IP_VER_DTCb <= DTC_IP) +#if (DTC_ENABLE != DTC_CFG_SHORT_ADDRESS_MODE) /* Full-address mode */ + dtc_mrc_t t_mrc; + + /* Casting to match type of "t_mrc.BYTE" */ + t_mrc.BYTE = (uint8_t)(p_cfg->disp_add_enable); +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ + /* Casting to match type of "t_mra.BYTE" */ + t_mra.BYTE = ((((uint8_t)p_cfg->writeback_disable | (uint8_t)p_cfg->src_addr_mode) | (uint8_t)p_cfg->data_size) | (uint8_t)p_cfg->transfer_mode); + + /* Casting to match type of "t_mrb.BYTE" */ + t_mrb.BYTE = (((((((uint8_t)p_cfg->sequence_end |(uint8_t)p_cfg->refer_index_table_enable) | (uint8_t)p_cfg->dest_addr_mode) | + (uint8_t)p_cfg->repeat_block_side) | (uint8_t)p_cfg->response_interrupt) | + (uint8_t)p_cfg->chain_transfer_enable) | (uint8_t)p_cfg->chain_transfer_mode); +#else + /* Casting to match type of "t_mra.BYTE" */ + t_mra.BYTE = (uint8_t)(p_cfg->src_addr_mode | p_cfg->data_size | p_cfg->transfer_mode); + + /* Casting to match type of "t_mrb.BYTE" */ + t_mrb.BYTE = (uint8_t)(p_cfg->dest_addr_mode | p_cfg->repeat_block_side | p_cfg->response_interrupt | + p_cfg->chain_transfer_enable | p_cfg->chain_transfer_mode); +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + switch (t_mra.BIT.MD) /* DTC transfer mode */ + { + case 0x0: /* Normal mode */ + { + if (DTC_PRV_MAX_16BITS_COUNT_VAL == p_cfg->transfer_count)/* Transfer count = 65536 */ + { + t_cra.WORD = 0x0000; + } + else /* 1 - 65535 */ + { + /* Cast type of "p_cfg->transfer_count" to uint16_t to match type of "t_cra.WORD" */ + t_cra.WORD = (uint16_t)p_cfg->transfer_count; + } + break; + } + + case 0x1: /* Repeat mode */ + { + /* Set counter. */ + if (p_cfg->transfer_count < DTC_PRV_MAX_8BITS_COUNT_VAL) /* count 1-255 */ + { + /* Cast type of "p_cfg->transfer_count" to match type of "t_cra.BYTE.CRA_H" */ + t_cra.BYTE.CRA_H = (uint8_t)p_cfg->transfer_count; + + /* Cast type of "p_cfg->transfer_count" to match type of "t_cra.BYTE.CRA_L" */ + t_cra.BYTE.CRA_L = (uint8_t)p_cfg->transfer_count; + } + else if (DTC_PRV_MAX_8BITS_COUNT_VAL == p_cfg->transfer_count) + { + t_cra.BYTE.CRA_H = 0x00; + t_cra.BYTE.CRA_L = 0x00; + } + else /* Transfer count > 256 */ + { + return DTC_ERR_INVALID_ARG; + } + break; + } + + case 0x2: /* DTC_TRANSFER_MODE_BLOCK - Block transfer mode */ + { + /* Set counter. */ + if (DTC_PRV_MAX_16BITS_COUNT_VAL == p_cfg->transfer_count)/* Transfer count = 65536 */ + { + t_crb.WORD = 0x0000; + } + else /* 1 - 65535 */ + { + /* Cast type of "p_cfg->transfer_count" to uint16_t to match type of "t_cra.WORD" */ + t_crb.WORD = (uint16_t)p_cfg->transfer_count; + } + + if (p_cfg->block_size < DTC_PRV_MAX_8BITS_COUNT_VAL) /* Block size 1-255 */ + { + /* Cast type of "p_cfg->block_size" to match type of "t_cra.BYTE.CRA_H" */ + t_cra.BYTE.CRA_H = (uint8_t)p_cfg->block_size; + + /* Cast type of "p_cfg->block_size" to match type of "t_cra.BYTE.CRA_L" */ + t_cra.BYTE.CRA_L = (uint8_t)p_cfg->block_size; + } + else if (DTC_PRV_MAX_8BITS_COUNT_VAL == p_cfg->block_size) /* Block size = 256 */ + { + t_cra.BYTE.CRA_H = 0; + t_cra.BYTE.CRA_L = 0; + } + else /* Invalid block size */ + { + return DTC_ERR_INVALID_ARG; + } + break; + } + + default: + { + return DTC_ERR_INVALID_ARG; + break; + } + } + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ + /* settings for fist long word: MRA & SAR */ + p_td_ptr->FIRST_LWORD.LWORD = 0; /* clear */ + p_td_ptr->FIRST_LWORD.REG.MRA = t_mra; /* 1 byte MRA */ + p_td_ptr->FIRST_LWORD.LWORD |= (p_cfg->source_addr & 0x00FFFFFF); /* 3 byte SAR */ + + /* settings for second long word: MRB & DAR */ + p_td_ptr->SECOND_LWORD.LWORD = 0; /* clear */ + p_td_ptr->SECOND_LWORD.REG.MRB = t_mrb; /* 1 byte MRB */ + p_td_ptr->SECOND_LWORD.LWORD |= (p_cfg->dest_addr & 0x00FFFFFF); /* 3 byte DAR */ + + /* settings for third long word: CRA & CRB */ + p_td_ptr->THIRD_LWORD.REG.CRA.WORD = t_cra.WORD; + p_td_ptr->THIRD_LWORD.REG.CRB.WORD = t_crb.WORD; + +#else /* Full-address mode */ + /* settings for fist long word: MRA & MRB */ + p_td_ptr->FIRST_LWORD.REG.MRA.BYTE = t_mra.BYTE; /* 1 byte MRA */ + p_td_ptr->FIRST_LWORD.REG.MRB.BYTE = t_mrb.BYTE; /* 1 byte MRB */ +#if (DTC_IP_VER_DTCb <= DTC_IP) + p_td_ptr->FIRST_LWORD.REG.MRC.BYTE = t_mrc.BYTE; /* 1 byte MRC */ +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + /* settings for second long word: SAR */ + p_td_ptr->SECOND_LWORD.SAR = p_cfg->source_addr; /* 4 byte SAR */ + + /* settings for third long word: DAR */ + p_td_ptr->THIRD_LWORD.DAR = p_cfg->dest_addr; /* 4 byte DAR */ + + /* settings for fourth long word: CRA & CRB */ + p_td_ptr->FOURTH_LWORD.REG.CRA.WORD = t_cra.WORD; + p_td_ptr->FOURTH_LWORD.REG.CRB.WORD = t_crb.WORD; +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ + return DTC_SUCCESS; +} +/* End of function r_dtc_set_transfer_data */ + +/******************************************************************************* +* Function Name: r_dtc_clear_all_dtce_bits +* Description : Clears all DTCERn.DTCE bit corresponding to the interrupt that +* can be selected as DTC activation sources. +* Arguments : addr - +* Address need to be validated +* Return Value : true - +* The address is valid. +* false - +* The address is invalid. +*******************************************************************************/ +static void r_dtc_clear_all_dtce_bits(void) +{ + volatile uint32_t dtce_cnt = 0; + + /* Clear all DTCER registers. + * Scan through all available DTCER registers in Array. + */ + /* WAIT_LOOP */ + while (dtce_cnt < DTC_NUM_INTERRUPT_SRC) + { + /* Clear Activation source*/ + ICU.DTCER[g_source_array[dtce_cnt]].BIT.DTCE = 0; + dtce_cnt++; + } + + return; +} +/* End of function r_dtc_clear_all_dtce_bits */ + +/******************************************************************************* +* Function Name: r_dtc_abort_chain_transfer +* Description : Aborts the current active chain transfer. +* Arguments : chain_transfer_nr - +* Number of chain transfer +* Return Value : true - +* Abort successfully. +* false +* Can not abort. +*******************************************************************************/ +static bool r_dtc_abort_chain_transfer(uint32_t chain_transfer_nr) +{ + volatile uint32_t cnt = 0; + uint16_t status_reg = 0; + + /* Set status register*/ + status_reg = DTC.DTCSTS.WORD; + + volatile dtc_internal_registers_t *p_td_ptr = NULL; + + if (0 == (status_reg & 0x8000)) /* DTC is not active. */ + { + return false; + } + + status_reg &= 0xFF; /* Get the vector number. */ + p_td_ptr = (((volatile dtc_internal_registers_t *)*((uint32_t *)DTC.DTCVBR + status_reg)) + chain_transfer_nr) - 1; + + /* Clear all CHNE bit */ + /* WAIT_LOOP */ + while (cnt < chain_transfer_nr) + { +#if (DTC_DISABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Full address mode */ + p_td_ptr->FIRST_LWORD.REG.MRB.BIT.CHNE = 0; +#else /* Short address mode */ + p_td_ptr->SECOND_LWORD.REG.MRB.BIT.CHNE = 0; +#endif + p_td_ptr--; + cnt++; + } + + return true; +} +/* End of function r_dtc_abort_chain_transfer */ + +/******************************************************************************* +* Function Name: r_dtc_acquire_hw_lock +* Description : Gets the hardware lock BSP_LOCK_DTC. +* Arguments : None. +* Return Value : true - +* The lock is acquired successfully +* false - +* Fails to get the lock +*******************************************************************************/ +static bool r_dtc_acquire_hw_lock(void) +{ + return R_BSP_HardwareLock(BSP_LOCK_DTC); +} +/* End of function r_dtc_acquire_hw_lock */ + +/******************************************************************************* +* Function Name: r_dtc_release_hw_lock +* Description : release hardware lock BSP_LOCK_DTC. +* Arguments : None. +* Return Value : None. +*******************************************************************************/ +static void r_dtc_release_hw_lock(void) +{ + R_BSP_HardwareUnlock(BSP_LOCK_DTC); + return; +} +/* End of function r_dtc_release_hw_lock */ + + +/******************************************************************************* +* Function Name: r_dtc_check_dmac_locking_sw +* Description : Checks all DMAC channel locking. +* Arguments : none - +* Return Value : true - +* All DMAC channels are unlocked. +* false - +* One or some DMAC channels are locked. +*******************************************************************************/ +static bool r_dtc_check_dmac_locking_sw(void) +{ + bool ret = true; + +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) + /* defined(0 != BSP_CFG_USER_LOCKING_ENABLED) */ + /* or defined(DTC_ENABLE !=DTC_CFG_USE_DMAC_FIT_MODULE) */ + /* or defined(bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) */ + /* User has to do the locking check of DMAC by themselves. */ + ret = r_dtc_check_DMAC_locking_byUSER(); +#else + uint32_t channel; + uint32_t dmac_lock_num = 0; + + /* Check locking status of all DMAC channels */ + /* WAIT_LOOP */ + for (channel = 0; channel < DMAC_NUM_CHANNELS; channel++) + { + /* Checks if DMAC channel is not locking */ + if (false == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_DMAC0 + channel))) + { + dmac_lock_num++; + } + else + { + /* Unlock DMAC channel */ + R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_DMAC0 + channel)); + } + } + + if (0 == dmac_lock_num) + { + ret = true; + } + else + { + ret = false; + } +#endif + + return ret; +} +/* End of function r_dtc_check_dmac_locking_sw */ + +/******************************************************************************* +* Function Name: r_dtc_check_create_param +* Description : Checks creating function parameter. +* Arguments : none - +* Return Value : DTC_SUCCESS - +* Successful operation +* DTC_ERR_INVALID_ARG - +* Parameters are invalid. +* DTC_ERR_NULL_PTR - +* The pointers are NULL. +*******************************************************************************/ +static dtc_err_t r_dtc_check_create_param(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg) +{ +#if (1 == DTC_CFG_PARAM_CHECKING_ENABLE) + + if ((NULL == p_data_cfg) || (NULL == p_transfer_data)) + { + return DTC_ERR_NULL_PTR; + } + + if ((p_data_cfg->transfer_count < DTC_PRV_MIN_COUNT_VAL) || + (p_data_cfg->transfer_count > DTC_PRV_MAX_16BITS_COUNT_VAL)) + { + return DTC_ERR_INVALID_ARG; + } + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ +/* Address must be in: 0x00000000h to 0x007FFFFF and 0xFF800000 to 0xFFFFFFFF */ + if ((p_data_cfg->source_addr > 0x007FFFFF) && (p_data_cfg->source_addr < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } + + if ((p_data_cfg->dest_addr > 0x007FFFFF) && (p_data_cfg->dest_addr < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } + /* Casting to match type of "uint32_t" */ + if (((uint32_t)p_transfer_data > 0x007FFFFF) && ((uint32_t)p_transfer_data < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ +#endif /* (1 == DTC_CFG_PARAM_CHECKING_ENABLE) */ + return DTC_SUCCESS; +} +/* End of function r_dtc_check_create_param */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h new file mode 100644 index 000000000..4995ce1cd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h @@ -0,0 +1,409 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_private.h +* Description : Functions for using DTC on RX devices. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : Added RX130, RX23T and RX24T. +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Supported sequence transfer. +* : Added DTC IP version definitions. +* : 13.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 18.06.2019 3.01 Removed "defined(__BIG_ENDIAN__)" from DTC_BIG_ENDIAN macro definition. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. +* : 25.11.2019 3.30 Added support for RX13T. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +* : 31.03.2020 3.50 Added support for RX23E-A. +*******************************************************************************/ +#ifndef DTC_RX_PRIVATE_H +#define DTC_RX_PRIVATE_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Fixed width integer support. */ +#include +/* Bool support */ +#include + +#if defined(BSP_MCU_RX23T) + #include ".\src\targets\rx23t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24T) + #include ".\src\targets\rx24t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24U) + #include ".\src\targets\rx24u\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX130) + #include ".\src\targets\rx130\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX13T) + #include ".\src\targets\rx13t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX113) + #include ".\src\targets\rx113\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX111) + #include ".\src\targets\rx111\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX110) + #include ".\src\targets\rx110\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX64M) + #include ".\src\targets\rx64m\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX71M) + #include ".\src\targets\rx71m\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX231) + #include ".\src\targets\rx231\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX23E_A) + #include ".\src\targets\rx23e-a\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX23W) + #include ".\src\targets\rx23w\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX230) + #include ".\src\targets\rx230\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX65N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx65n\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX66T) + #include ".\src\targets\rx66t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX66N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx66n\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX72T) + #include ".\src\targets\rx72t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX72M) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx72m\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX72N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx72n\r_dtc_rx_target.h" +#else + #error "This MCU is not supported by the current r_dtc_rx module." +#endif + +/***************************************************************************** +Macro definitions +******************************************************************************/ +#define DTC_BIG_ENDIAN (defined(__BIG) || defined(__RX_BIG_ENDIAN__)) +#define DTC_INVALID_CMND ((uint32_t)0x00000001) +/* DTC IP version */ +#define DTC_IP_VER_DTC (0) +#define DTC_IP_VER_DTCa (1) +#define DTC_IP_VER_DTCb (2) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +/* The DTC Mode Register A (MRA) structure */ + +R_BSP_PRAGMA_UNPACK; + +#if (DTC_IP_VER_DTCa == DTC_IP) +typedef union dtc_mra { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4 ( + uint8_t MD:2, /* b7,b6: DTC Transfer Mode Select */ + uint8_t SZ:2, /* DTC Data Transfer Size */ + uint8_t SM:2, /* Transfer Source Address Addressing Mode */ + uint8_t rs:2 /* reserved */ + ) BIT; + +} dtc_mra_t; + +/* The DTC Mode Register B (MRB) structure */ +typedef union dtc_mrb { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6 ( + uint8_t CHNE :1, /* b7: DTC Chain Transfer Enable */ + uint8_t CHNS :1, /* DTC Chain Transfer Select */ + uint8_t DISEL:1, /* DTC Interrupt Select */ + uint8_t DTS :1, /* DTC Transfer Mode Select */ + uint8_t DM :2, /* Transfer Destination Address Addressing Mode */ + uint8_t rs :2 /* reserved */ + ) BIT; + +} dtc_mrb_t; +#else +typedef union dtc_mra { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5 ( + uint8_t MD:2, /* b7,b6: DTC Transfer Mode Select */ + uint8_t SZ:2, /* DTC Data Transfer Size */ + uint8_t SM:2, /* Transfer Source Address Addressing Mode */ + uint8_t rs:1, /* reserved */ + uint8_t WBDIS:1 /* Write-back Disable */ + ) BIT; + +} dtc_mra_t; + +/* The DTC Mode Register B (MRB) structure */ +typedef union dtc_mrb { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7 ( + uint8_t CHNE :1, /* b7: DTC Chain Transfer Enable */ + uint8_t CHNS :1, /* DTC Chain Transfer Select */ + uint8_t DISEL:1, /* DTC Interrupt Select */ + uint8_t DTS :1, /* DTC Transfer Mode Select */ + uint8_t DM :2, /* Transfer Destination Address Addressing Mode */ + uint8_t INDX:1, /* Index Table Reference */ + uint8_t SQEND:1 /* Sequence Transfer End */ + ) BIT; + +} dtc_mrb_t; + +/* The DTC Mode Register C (MRC) structure */ +typedef union dtc_mrc { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2 ( + uint8_t rs :7, /* reserved */ + uint8_t DISPE :1 + ) BIT; + +} dtc_mrc_t; +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + +/* The DTC Transfer Count Register A (CRA) structure */ +typedef union dtc_cra { + uint16_t WORD; + struct { +#if (DTC_BIG_ENDIAN) + uint8_t CRA_H; + uint8_t CRA_L; +#else /* little endian */ + uint8_t CRA_L; + uint8_t CRA_H; +#endif /* (DTC_BIG_ENDIAN) */ + } BYTE; +} dtc_cra_t; + +/* The DTC Transfer Count Register B (CRB) structure */ +typedef union dtc_crb { + uint16_t WORD; +} dtc_crb_t; + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Transfer data in short-address mode */ +typedef struct st_dtc_short_transfer_data { + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mra_t MRA; + uint8_t SAR[3]; +#else /* Little-Endian */ + uint8_t SAR[3]; + dtc_mra_t MRA; +#endif /* (DTC_BIG_ENDIAN) */ + + } REG; + + } FIRST_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mrb_t MRB; + uint8_t DAR[3]; +#else /* Little-Endian */ + uint8_t SAR[3]; + dtc_mrb_t MRB; +#endif /* (DTC_BIG_ENDIAN) */ + + } REG; + } SECOND_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_cra_t CRA; + dtc_crb_t CRB; +#else /* Little-Endian */ + dtc_crb_t CRB; + dtc_cra_t CRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } THIRD_LWORD; +} dtc_internal_registers_t; + +#else /* Transfer data in full-address mode */ +typedef struct st_dtc_full_transfer_data { + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mra_t MRA; + dtc_mrb_t MRB; +#if (DTC_IP_VER_DTCa == DTC_IP) + uint16_t reserver; /* reserve area */ +#else + dtc_mrc_t MRC; + uint8_t reserver; /* reserve area */ +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + +#else /* Little-Endian */ +#if (DTC_IP_VER_DTCa == DTC_IP) + uint16_t reserver; /* reserve area */ +#else + uint8_t reserver; /* reserve area */ + dtc_mrc_t MRC; +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + dtc_mrb_t MRB; + dtc_mra_t MRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } FIRST_LWORD; + union { + uint32_t SAR; + } SECOND_LWORD; + union { + uint32_t DAR; + } THIRD_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_cra_t CRA; + dtc_crb_t CRB; +#else /* Little-Endian */ + dtc_crb_t CRB; + dtc_cra_t CRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } FOURTH_LWORD; +} dtc_internal_registers_t; + +#endif /* DTC_CFG_SHORT_ADDRESS_MODE */ + +R_BSP_PRAGMA_PACKOPTION; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void r_dtc_module_enable(void); +void r_dtc_module_disable(void); +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) +bool r_dtc_check_DMAC_locking_byUSER(void); +#endif + + +#endif /* DTC_RX_PRIVATE_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c new file mode 100644 index 000000000..ac86b0d7d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c @@ -0,0 +1,207 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target.c +* Device : RX72N +* Tool-Chain : Renesas RXC Toolchain v3.01.00 +* OS : not use +* H/W Platform : not use +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Defines for DTC support */ +#include "r_dtc_rx_if.h" +#include ".\src\r_dtc_rx_private.h" + +/* Check MCU Group */ +#if defined(BSP_MCU_RX72N) + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +/* The array of all interrupt source */ +const dtc_activation_source_t g_source_array[DTC_NUM_INTERRUPT_SRC] = +{ +DTCE_ICU_SWINT2,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USB0_D0FIFO0,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSIE0_SSITXI0,DTCE_SSIE0_SSIRXI0, +DTCE_SSIE1_SSIRTI1, +DTCE_RIIC1_RXI1,DTCE_RIIC1_TXI1, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10,DTCE_SCI10_TXI10, +DTCE_RSPI2_SPRI2,DTCE_RSPI2_SPTI2, +DTCE_SCI11_RXI11,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +}; + + +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) +/******************************************************************************* +* Function Name: r_dtc_check_DMAC_locking_byUSER +* Description : Checks all DMAC channel locking. +* Arguments : none - +* Return Value : true - +* All DMAC channels are unlocked. +* false - +* One or some DMAC channels are locked. +* +*******************************************************************************/ +bool r_dtc_check_DMAC_locking_byUSER(void) +{ + bool ret = true; + + /* User has to check the locking of DMAC by themselves. */ + /* do something */ + + return ret; +} +#endif + + +/******************************************************************************* +* Function Name: r_dtc_module_enable +* Description : Releases module stop state. +* Arguments : None +* Return Value : None +*******************************************************************************/ +void r_dtc_module_enable(void) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) +bsp_int_ctrl_t int_ctrl; +#endif + /* Enable writing to MSTP registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + /* Release from module stop state. */ + MSTP(DTC) = 0; + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + /* Disable writing to MSTP registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} +/****************************************************************************** + End of function r_dtc_module_enable + *****************************************************************************/ + +/******************************************************************************* +* Function Name: r_dtc_module_disable +* Description : Sets to module stop state. +* Arguments : None +* Return Value : None +*******************************************************************************/ +void r_dtc_module_disable(void) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) +bsp_int_ctrl_t int_ctrl; +#endif + /* Enable writing to MSTP registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + /* Set to module stop state. */ + MSTP(DTC) = 1; + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + /* Disable writing to MSTP registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} +/****************************************************************************** + End of function r_dtc_module_disable + *****************************************************************************/ + +#endif /* defined(BSP_MCU_RX72N) */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h new file mode 100644 index 000000000..918d5456f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target.h +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ +#ifndef DTC_RX_TARGET_H +#define DTC_RX_TARGET_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* The number of activation sources */ +#if defined(BSP_MCU_RX72N) +#define DTC_NUM_INTERRUPT_SRC (204) +#endif /* defined(BSP_MCU_RX72N) */ + +#if (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) +/* Size of DTC Vector table and DTC Index table (in byte units) */ +#define DTC_VECTOR_TABLE_SIZE_BYTES (0x400 + 0x400 + 0x400) +#else +/* Size of DTC Vector table (in byte units) */ +#define DTC_VECTOR_TABLE_SIZE_BYTES (0x400 + 0x400) +#endif /* (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ + +/* Definition of num of DMAC channel. */ +#define DMAC_NUM_CHANNELS (8) + +/* DTC IP Version */ +#define DTC_IP (DTC_IP_VER_DTCb) + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif /* DTC_RX_TARGET_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h new file mode 100644 index 000000000..d2234ccf5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target_if.h +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ +#ifndef DTC_RX_TARGET_IF_H +#define DTC_RX_TARGET_IF_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +/* Transfer data configuration */ +typedef struct st_dtc_transfer_data_cfg { + dtc_transfer_mode_t transfer_mode; /* DTC transfer mode */ + dtc_data_size_t data_size; /* Size of data */ + dtc_src_addr_mode_t src_addr_mode; /* Address mode of source */ + dtc_chain_transfer_t chain_transfer_enable; /* Chain transfer is enabled or not. */ + dtc_chain_transfer_mode_t chain_transfer_mode; /* How chain transfer is performed. */ + dtc_interrupt_t response_interrupt; /* How response interrupt is raised */ + dtc_repeat_block_side_t repeat_block_side; /* The side being repeat or block in repeat / block transfer mode. */ + dtc_dest_addr_mode_t dest_addr_mode; /* Address mode of destination */ + uint32_t source_addr; /* Start address of source */ + uint32_t dest_addr; /* Start address of destination */ + uint32_t transfer_count; /* Transfer count */ + uint16_t block_size; /* Size of a block in block transfer mode */ + uint16_t rsv; /* Reserved */ + dtc_write_back_t writeback_disable; /* Write-back disable or enable */ + dtc_sequence_end_t sequence_end; /* Sequence transfer end or continue */ + dtc_refer_index_table_t refer_index_table_enable; /* Index table refer or not refer */ + dtc_disp_add_t disp_add_enable; /* The displacement value is added or not added */ +} dtc_transfer_data_cfg_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif /* DTC_RX_TARGET_IF_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h new file mode 100644 index 000000000..67885fe4a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_if.h +* Description : General Purpose I/O driver for RX MCUs. This interface file has everything the user needs to use this +* module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 23.04.2014 1.20 Add support for RX63N, and RX110 +* : 28.05.2014 1.30 Add support for RX64M +* : 28.11.2014 1.40 Add support for RX113 +* : 02.09.2015 1.50 Add support for RX71M, increased the minor version number to 50. +* : Added GPIO_CMD_DSCR_DISABLE and GPIO_CMD_DSCR_ENABLE commands in gpio_cmd_t +* : 06.04.2015 1.60 Add support for RX231 +* : 30.09.2015 1.70 Add support for RX23T +* : 01.10.2015 1.80 Add support for RX130 +* : 01.12.2015 1.90 Add support for RX24T +* : 01.02.2016 2.00 Add support for RX230 +* : 15.06.2016 2.01 Added the demo of the RX64M group. +* : 01.10.2016 2.10 Add support for RX65N +* : 19.12.2016 2.20 Add support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Add support for RX65N-2M, RX130-512KB +* : 31.10.2017 2.31 Added the demo for RX65N, RX65N-2M +* : 28.09.2018 2.40 Add support for RX66T +* : 16.11.2018 2.41 Added XML document number +* : 01.02.2019 2.50 Add support for RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Removed support for Generation 1 devices. +* : 30.12.2019 3.40 Added support RX72N, RX66N +* : 31.03.2020 3.50 Added support for RX23E-A +***********************************************************************************************************************/ + +#ifndef GPIO_RX_INTERFACE_HEADER_FILE +#define GPIO_RX_INTERFACE_HEADER_FILE + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Module configuration. */ +#include "r_gpio_rx_config.h" + +/* Include specifics for chosen MCU. Go to the header file for your MCU to see available ports and pins. */ +#if defined(BSP_MCU_RX113) + #include "./src/targets/rx113/r_gpio_rx113.h" +#elif defined(BSP_MCU_RX110) + #include "./src/targets/rx110/r_gpio_rx110.h" +#elif defined(BSP_MCU_RX111) + #include "./src/targets/rx111/r_gpio_rx111.h" +#elif defined(BSP_MCU_RX130) + #include "./src/targets/rx130/r_gpio_rx130.h" +#elif defined(BSP_MCU_RX13T) + #include "./src/targets/rx13t/r_gpio_rx13t.h" +#elif defined(BSP_MCU_RX230) + #include "./src/targets/rx230/r_gpio_rx230.h" +#elif defined(BSP_MCU_RX231) + #include "./src/targets/rx231/r_gpio_rx231.h" +#elif defined(BSP_MCU_RX23T) + #include "./src/targets/rx23t/r_gpio_rx23t.h" +#elif defined(BSP_MCU_RX23W) + #include "./src/targets/rx23w/r_gpio_rx23w.h" +#elif defined(BSP_MCU_RX23E_A) + #include "./src/targets/rx23e-a/r_gpio_rx23e-a.h" +#elif defined(BSP_MCU_RX24T) + #include "./src/targets/rx24t/r_gpio_rx24t.h" +#elif defined(BSP_MCU_RX24U) + #include "./src/targets/rx24u/r_gpio_rx24u.h" +#elif defined(BSP_MCU_RX64M) + #include "./src/targets/rx64m/r_gpio_rx64m.h" +#elif defined(BSP_MCU_RX65N) + #include "./src/targets/rx65n/r_gpio_rx65n.h" +#elif defined(BSP_MCU_RX66T) + #include "./src/targets/rx66t/r_gpio_rx66t.h" +#elif defined(BSP_MCU_RX66N) + #include "./src/targets/rx66n/r_gpio_rx66n.h" +#elif defined(BSP_MCU_RX71M) + #include "./src/targets/rx71m/r_gpio_rx71m.h" +#elif defined(BSP_MCU_RX72T) + #include "./src/targets/rx72t/r_gpio_rx72t.h" +#elif defined(BSP_MCU_RX72M) + #include "./src/targets/rx72m/r_gpio_rx72m.h" +#elif defined(BSP_MCU_RX72N) + #include "./src/targets/rx72n/r_gpio_rx72n.h" +#else + #error "This MCU is not supported by the current r_gpio_rx module." +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define GPIO_RX_VERSION_MAJOR (3) +#define GPIO_RX_VERSION_MINOR (50) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The gpio_port_t and gpio_port_pin_t enums are located in the 'targets' folder for each MCU. For example, to see + * these enums for a RX111 look at the following file: r_gpio_rx/src/targets/rx111/r_gpio_rx111.h + */ + +/* Levels that can be set and read for individual pins. */ +typedef enum +{ + GPIO_LEVEL_LOW = 0, + GPIO_LEVEL_HIGH +} gpio_level_t; + +/* Options that can be used with the R_GPIO_PortDirectionSet() and R_GPIO_PinDirectionSet() functions. */ +typedef enum +{ + GPIO_DIRECTION_INPUT = 0, + GPIO_DIRECTION_OUTPUT +} gpio_dir_t; + +/* Commands that can be used with the R_GPIO_PinControl() function. This list will vary depending on the MCU chosen. */ +typedef enum +{ + GPIO_CMD_OUT_CMOS = 0, + GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN, + GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN, + GPIO_CMD_IN_PULL_UP_DISABLE, + GPIO_CMD_IN_PULL_UP_ENABLE, + GPIO_CMD_ASSIGN_TO_PERIPHERAL, + GPIO_CMD_ASSIGN_TO_GPIO, + GPIO_CMD_DSCR_DISABLE, + GPIO_CMD_DSCR_ENABLE, + GPIO_CMD_DSCR2_DISABLE, + GPIO_CMD_DSCR2_ENABLE +} gpio_cmd_t; + +/* Function return type. */ +typedef enum +{ + GPIO_SUCCESS = 0, + GPIO_ERR_INVALID_MODE, // The mode specified cannot be applied to this pin + GPIO_ERR_INVALID_CMD // The input command is not supported +} gpio_err_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_GPIO_PortWrite(gpio_port_t port, uint8_t value); +uint8_t R_GPIO_PortRead(gpio_port_t port); +void R_GPIO_PortDirectionSet(gpio_port_t port, gpio_dir_t dir, uint8_t mask); +void R_GPIO_PinWrite(gpio_port_pin_t pin, gpio_level_t level); +gpio_level_t R_GPIO_PinRead(gpio_port_pin_t pin); +void R_GPIO_PinDirectionSet(gpio_port_pin_t pin, gpio_dir_t dir); +gpio_err_t R_GPIO_PinControl(gpio_port_pin_t pin, gpio_cmd_t cmd); +uint32_t R_GPIO_GetVersion(void); + +#endif /* GPIO_RX_INTERFACE_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/readme.txt new file mode 100644 index 000000000..87c7b140f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/readme.txt @@ -0,0 +1,50 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS MODULE FOR MORE INFORMATION + +r_gpio_rx +========= + +Overview +-------- +This code implements a General Purpose Input/Output driver. Common features such as reading, writing, and setting the +direction of ports and pins are supported. Enabling features such as open-drain outputs and internal pull-ups are also +supported. + +Features +-------- +* Read ports and pins +* Write ports and pins +* Set ports and pins as inputs and outputs +* Enable features of pins such as internal pull-ups or open-drain outputs + +File Structure +-------------- +r_gpio_rx +| readme.txt +| r_gpio_rx_if.h +| ++---doc +| +---ja +| | r01an1721jj{VERSION_NUMBER}-rx-gpio.pdf +| +---en +| r01an1721ej{VERSION_NUMBER}-rx-gpio.pdf +| ++---ref +| r_gpio_rx_config_reference.h +| +\---src + | r_gpio_rx.c + | + \---targets + +---rx110 + | r_gpio_rx110.c + | r_gpio_rx110.h + | + +---rx111 + | r_gpio_rx111.c + | r_gpio_rx111.h + | + : + +r_config + r_gpio_rx_config.h + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h new file mode 100644 index 000000000..bfeb0766e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h @@ -0,0 +1,46 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c new file mode 100644 index 000000000..8ddb93940 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c @@ -0,0 +1,573 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx.c +* Description : General Purpose Input/Output driver for RX MCUs. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 21.11.2014 1.40 Added support for RX113 +* : 02.09.2015 1.50 Added support for RX71M +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR_ENABLE/_DISABLE commands. +* : 01.10.2016 2.10 Added support for RX65N +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR2_ENABLE/_DISABLE commands. +* : 19.12.2016 2.20 Added support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Added support for RX65N-2M, RX130-512KB. +* : 28.09.2018 2.40 Added support for RX66T. +* Update according to GSCE Code Checker +* : 01.02.2019 2.50 Added support for RX72T, RX65N-64pin +* Update according to GSCE Code Checker +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Modified comment of API function to Doxygen style. +* : 30.12.2019 3.40 Added support RX72N, RX66N. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +* Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Typedef definitions +***********************************************************************************************************************/ +/* Different pin output options. */ +typedef enum +{ + GPIO_PIN_OUT_CMOS = 0, + GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN = 1, + GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN = 2 +} gpio_pin_output_t; + +/*********************************************************************************************************************** +* Private global variables and functions +***********************************************************************************************************************/ +uint8_t volatile * gpio_port_addr_get(uint8_t volatile * base_addr, uint16_t index); +bool gpio_pin_function_check(uint8_t const * check_array, uint8_t port_number, uint8_t pin_number); +void gpio_set_output_type(gpio_port_pin_t pin, gpio_pin_output_t out_type); + +/*********************************************************************************************************************** +* Export global variables +***********************************************************************************************************************/ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + extern const uint8_t g_gpio_open_drain_n_support[]; + extern const uint8_t g_gpio_open_drain_p_support[]; + extern const uint8_t g_gpio_pull_up_support[]; + #if defined (GPIO_DSCR_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr_support[]; + #endif + #if defined (GPIO_DSCR2_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr2_support[]; + #endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortWrite +********************************************************************************************************************//** +* @brief This function writes the levels of all pins on a port. +* @param[in] port - Which port to write to. See Section 2.10.1, Ports. +* @param[in] value - The value to write to the port. Each bit corresponds to a pin on the port (e.g. bit 0 of value +* will be written to pin 0 on supplied port) +* @details The input value will be written to the specified port. Each bit in the value parameter corresponds to a pin +* on the port. For example, bit 7 of write value corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* @note In the interest of performance, this function does not automatically check for non-existent pins when the +* port-wide write function is called. It is up to the user’s application to insure that only valid pins are written to. +* +*/ +void R_GPIO_PortWrite (gpio_port_t port, uint8_t value) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)port); + + /* Write to the selected port. */ + *podr = value; +} /* End of function R_GPIO_PortWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortRead +********************************************************************************************************************//** +* @brief This function reads the levels of all pins on a port. +* @param[in] port - Which port to read. See Section 2.10.1, Ports. +* @return The value of the port. +* @details The specified port will be read, and the levels for all the pins will be returned. Each bit in the returned +* value corresponds to a pin on the port. For example, bit 7 of read value corresponds to pin 7, bit 6 corresponds to +* pin 6, and so forth. +*/ +uint8_t R_GPIO_PortRead (gpio_port_t port) +{ + /* PIDR register addresses are incremental in memory starting with PORT0.PIDR. Even if a port is not available + * on this MCU, the address is reserved. */ + + /* Read the selected port. */ + return *gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)port); +} /* End of function R_GPIO_PortRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortDirectionSet +********************************************************************************************************************//** +* @brief This function sets multiple pins on a port to inputs or outputs at once. +* @param[in] port - Which port to use. See Section 2.10.1, Ports. +* @param[in] dir - Which direction to use. See Section 2.10.5, Pin Direction. +* @param[in] mask - Mask of which pins to change. 1 = set direction, 0 = do not change. +* @details Multiple pins on a port can be set to inputs or outputs at once. Each bit in the mask parameter corresponds +* to a pin on the port. For example, bit 7 of mask corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* If a bit is set to 1 then the corresponding pin will be changed to an input or output as specified by the dir +* parameter. If a bit is set to 0 then the direction of the pin will not be changed. +* @note This function does not allow the user to specify the use of special modes such as input pull-up resistors or +* open-drain outputs. To enable these modes use the R_GPIO_PinControl() function. +*/ +void R_GPIO_PortDirectionSet (gpio_port_t port, gpio_dir_t dir, uint8_t mask) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)port); + + /* Write to the selected register. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) & (~mask)); + } + else + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) | mask); + } +} /* End of function R_GPIO_PortDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinWrite +********************************************************************************************************************//** +* @brief This function sets the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] level - What level to set the pin to. +* @details Pins can either be set as high (‘1’) or low (‘0’). +*/ +void R_GPIO_PinWrite (gpio_port_pin_t pin, gpio_level_t level) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_LEVEL_LOW == level) + { + /* Set value to port */ + *podr = (uint8_t)((*podr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Set value to port */ + *podr = (uint8_t)((*podr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinRead +********************************************************************************************************************//** +* @brief This function reads the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @return The level of the specified pin. +* @details The specified pin will be read and the level returned. +*/ +gpio_level_t R_GPIO_PinRead (gpio_port_pin_t pin) +{ + uint8_t volatile * pidr; + + /* PIDR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pidr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)pin); + + /* Mask to get the individual bit. */ + if (((*pidr) & (1 << (pin & 0x00FFu))) != 0) + { + return GPIO_LEVEL_HIGH; + } + else + { + return GPIO_LEVEL_LOW; + } +} /* End of function R_GPIO_PinRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinDirectionSet +********************************************************************************************************************//** +* @brief This function sets the direction (input/output) of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] dir - Which direction to use for this pin. See Section 2.10.5, Pin Direction. +* @details This function sets pins as inputs or outputs. For enabling other settings such as open-drain outputs or +* internal pull-ups see the R_GPIO_PinControl() function. +*/ +void R_GPIO_PinDirectionSet (gpio_port_pin_t pin, gpio_dir_t dir) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinControl +********************************************************************************************************************//** +* @brief This function allows the user to control various settings of a pin. +* @param[in] pin -Which pin to use. See Section 2.10.2, Pins +* @param[in] cmd - Which command to execute for this pin. See Section 2.10.6, Control Commands for available commands. +* @retval [GPIO_SUCCESS] Successful; pin modified as specified by command. +* @retval [GPIO_ERR_INVALID_MODE] Error; this pin does not support the specified option. +* @retval [GPIO_ERR_INVALID_CMD] Error; the input command is not supported. +* @details Depending on the MCU, pins have various settings that can be configured other than the direction and +* output level. Some examples include enabling open-drain outputs, internal pull-ups, and changing drive capacity +* levels. These features vary per chip which means that the options for this function will also vary. +*/ +gpio_err_t R_GPIO_PinControl (gpio_port_pin_t pin, gpio_cmd_t cmd) +{ + gpio_err_t err; + uint8_t volatile * addr; + uint8_t pin_number; + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + uint8_t port_number; + + /* Get port number */ + port_number = (uint8_t)(pin >> 8); +#endif + + err = GPIO_SUCCESS; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + switch (cmd) + { + +#if defined (GPIO_DSCR_IS_SUPPORTED) + case GPIO_CMD_DSCR_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + case GPIO_CMD_DSCR_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* GPIO_DSCR_IS_SUPPORTED */ +#if defined (GPIO_DSCR2_IS_SUPPORTED) + case GPIO_CMD_DSCR2_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_DSCR2_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* GPIO_DSCR2_IS_SUPPORTED */ + case GPIO_CMD_ASSIGN_TO_GPIO: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_ASSIGN_TO_PERIPHERAL: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_IN_PULL_UP_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_IN_PULL_UP_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_OUT_CMOS: + { + gpio_set_output_type(pin, GPIO_PIN_OUT_CMOS); + + break; + } + + case GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_n_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN); + + break; + } + case GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN: + { + #if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_p_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } + #endif + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN); + + break; + } + + default: + { + err = GPIO_ERR_INVALID_CMD; + break; + } + } + + return err; +} /* End of function R_GPIO_PinControl */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_GetVersion +********************************************************************************************************************//** +* @brief Returns the current version of this API. +* @return Version of this API. +* @details This function will return the version of the currently running API. The version number is encoded where +* the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example, +* Version 4.25 would be returned as 0x00040019. +*/ +uint32_t R_GPIO_GetVersion (void) +{ + /* These version macros are defined in r_gpio_rx_if.h. */ + return ((((uint32_t)GPIO_RX_VERSION_MAJOR) << 16) | (uint32_t)GPIO_RX_VERSION_MINOR); +} /* End of function R_GPIO_GetVersion */ + +/*********************************************************************************************************************** +* Function Name: gpio_port_addr_get +* Description : Get the address for a port register based on a base port register address. +* Arguments : base_addr - +* First port register of this type (e.g. &PORT0.PODR.BYTE) +* index - +* Index off the base. (e.g. for PORT4 it would be 0x0400) +* Return Value : Address of the register that was requested +***********************************************************************************************************************/ + +R_BSP_PRAGMA_INLINE (gpio_port_addr_get) +uint8_t volatile * gpio_port_addr_get (uint8_t volatile * base_addr, uint16_t index) +{ + /* Add port number to 'index' to correct register. */ + return (uint8_t volatile *)((((uint32_t)index >> 8) & 0x000000FFuL) + (uint32_t)base_addr); +} /* End of function gpio_port_addr_get */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +/*********************************************************************************************************************** +* Function Name: gpio_pin_function_check +* Description : Checks to see if a pin supports a certain function. +* Arguments : check_array - +* Which support array to use. +* port_number - +* Which port to use. +* pin_number - +* Which pin to use. +* Return Value : true - +* Functionality is supported on this pin. +* false - +* Functionality is not supported on this pin. +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE (gpio_pin_function_check) +bool gpio_pin_function_check (uint8_t const * check_array, uint8_t port_number, uint8_t pin_number) +{ + if ((check_array[port_number] & (1 << pin_number)) != 0) + { + return true; + } + else + { + return false; + } +} /* End of function gpio_pin_function_check */ +#endif + +/*********************************************************************************************************************** +* Function Name: gpio_set_output_type +* Description : Configures pin output type (e.g. CMOS, open-drain) +* Arguments : pin - +* Which pin to change output type for +* out_type - +* What output type to use for this pin +* Return Value : None +***********************************************************************************************************************/ +void gpio_set_output_type (gpio_port_pin_t pin, gpio_pin_output_t out_type) +{ + uint8_t volatile * addr; + uint8_t pin_number; + uint8_t bit_offset; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + /* 'pin' is multiplied by 2 because the ODR0 and ODR1 registers are staggered. This means that PORT0.ODR0 + * and PORT1.ODR0 are separated by 2 bytes instead of 1 as with the other port registers. */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUT_TYPE, (uint16_t)(((uint16_t)pin)*2)); + + /* ODR bit fields are 2-bits a piece. This means bits 0-3 are in the 1st byte (ODR0) and bits 4-7 are in + * the 2nd byte (ODR1). + */ + if (pin_number > 3) + { + /* Bit field is in ODR1. Increment address by 1 for ODR1 register for this port. */ + addr += 1; + + /* Subtract 4 from pin number since pins 4-7 are stored in ODR1 which is an 8-bit register. + * Multiple pin number by 2 since each pin is represented by 2 bits. + */ + bit_offset = (uint8_t)((pin_number - 4) * 2); + } + else + { + /* Multiple pin number by 2 since each pin is represented by 2 bits. */ + bit_offset = (uint8_t)(pin_number * 2); + } + + /* Clear the bits we intend to change. */ + *addr = (uint8_t)((*addr) & (~(3 << bit_offset))); + + /* Set the bits again if needed. */ + *addr = (uint8_t)((*addr) | (((uint8_t)out_type) << bit_offset)); +} /* End of function gpio_set_output_type */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c new file mode 100644 index 000000000..2d8a61f6f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c @@ -0,0 +1,206 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx72n.c +* Description : Data for r_gpio_rx driver specific to RX72N. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" + +#if defined(BSP_MCU_RX72N) + +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* These arrays hold which pins have extra functionality. For example, not all pins have the option of enabling + * open-drain N-channel output instead of the default CMOS output. Each entry in the array corresponds to a port. + * Each bit in each entry corresponds to a pin on that port. If bit 3 of array entry [4] was set to 1 then that would + * mean that PORT 4 PIN 3 supported the feature that array represented. + * + * These arrays are only used when GPIO_CFG_PARAM_CHECKING_ENABLE is set to 1 (checking enabled). If you know that + * your code does not need to check the pins then you can set this macro to 0 and save a little execution time + * and ROM space. + * + * Note: These arrays are defined for the largest package part. For smaller packages where some pins do not exist, + * pin checking is filtered by the enumerated port_pin list for that package as defined in r_gpio_rx72n.h. + */ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0xAF, // P0: P00 to P03, P05, P07 + 0xFF, // P1: P10 to P17 + 0xFF, // P2: P20 to P27 + 0xDF, // P3: P30 to P34, P36, P37 + 0xFF, // P4: P40 to P47 + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFF, // P7: P70 to P77 + 0xFF, // P8: P80 to P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x3F, // PF: PF0 to PF5 + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x2F, // PJ: PJ0 to PJ3, PJ5 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, // P0: - + 0x00, // P1: - + 0x00, // P2: - + 0x00, // P3: - + 0x00, // P4: - + 0x00, // P5: - + 0x00, // P6: - + 0x00, // P7: - + 0x00, // P8: - + 0x00, // P9: - + 0x00, // PA: - + 0x00, // PB: - + 0x00, // PC: - + 0x00, // PD: - + 0x02, // PE: PE1 + 0x00, // PF: - + 0x00, // PG: - + 0x00, // PH: - + 0x00, // PJ: - + 0x00, // PK: - + 0x00, // PL: - + 0x00, // PM: - + 0x00, // PN: - + 0x00, // PQ: - +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0xAF, // P0: P00 to P03, P05, P07 + 0xFF, // P1: P10 to P17 + 0xFF, // P2: P20 to P27 + 0xDF, // P3: P30 to P34, P36, P37 + 0xFF, // P4: P40 to P47 + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFF, // P7: P70 to P77 + 0xFF, // P8: P80 to P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x3F, // PF: PF0 to PF5 + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x2F, // PJ: PJ0 to PJ3, PJ5 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_dscr_support[GPIO_INFO_NUM_PORTS] = +{ + 0x07, // P0: P00 to P02 + 0x1E, // P1: P11 to P14 + 0x80, // P2: P27 + 0x00, // P3: - + 0x00, // P4: - + 0xF7, // P5: P50 to P52, P54 to P57 + 0x00, // P6: - + 0xF4, // P7: P72, P74 to P77 + 0x3F, // P8: P80 to P85 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x00, // PF: - + 0x03, // PG: PG0, PG1 + 0xFF, // PH: PH0 to PH7 + 0x07, // PJ: PJ0 to PJ2 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_dscr2_support[GPIO_INFO_NUM_PORTS] = +{ + 0x07, // P0: P00 to P02 + 0x9E, // P1: P11 to P14, P17 + 0x8F, // P2: P20 to P23, P27 + 0x03, // P3: P30, P31 + 0x00, // P4: - + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFD, // P7: P70, P72 to P77 + 0xBF, // P8: P80 to P85, P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x00, // PF: - + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x07, // PJ: PJ0 to PJ2 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +#endif /* GPIO_CFG_PARAM_CHECKING_ENABLE */ + +#endif /* BSP_MCU_RX72N */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h new file mode 100644 index 000000000..6734a9632 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h @@ -0,0 +1,810 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx72n.h +* Description : Specifics for the r_gpio_rx driver for the RX72N. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ +#ifndef GPIO_RX72N +#define GPIO_RX72N + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +#if defined(BSP_MCU_RX72N) /* Prevents the compiler from finding multiple definitions of constant in this file. */ + +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* General information about number of ports and pins on this device. */ +#define GPIO_INFO_NUM_PORTS (24) + +#if (BSP_PACKAGE_PINS == 224) + #define GPIO_INFO_NUM_PINS (183) +#elif (BSP_PACKAGE_PINS == 176) + #define GPIO_INFO_NUM_PINS (137) +#elif (BSP_PACKAGE_PINS == 145 || BSP_PACKAGE_PINS == 144) + #define GPIO_INFO_NUM_PINS (112) +#elif (BSP_PACKAGE_PINS == 100) + #define GPIO_INFO_NUM_PINS (79) +#else + #error "r_gpio_rx does not have information about this RX72N package. Please update r_gpio_rx72N.h" +#endif + +/* For testing we will allocate virtual IO ports. */ +#if !defined(GPIO_TESTING) +/* Base registers used for offsets on output data registers. */ +#define GPIO_PRV_BASE_ADDR_OUTPUT ((uint8_t volatile *)&PORT0.PODR.BYTE) +/* Base registers used for offsets on input data registers. */ +#define GPIO_PRV_BASE_ADDR_INPUT ((uint8_t volatile *)&PORT0.PIDR.BYTE) +/* Base registers used for offsets on direction registers. */ +#define GPIO_PRV_BASE_ADDR_DIRECTION ((uint8_t volatile *)&PORT0.PDR.BYTE) +/* Base registers used for offsets on mode registers. */ +#define GPIO_PRV_BASE_ADDR_MODE ((uint8_t volatile *)&PORT0.PMR.BYTE) +/* Base registers used for offsets on output type registers. */ +#define GPIO_PRV_BASE_ADDR_OUT_TYPE ((uint8_t volatile *)&PORT0.ODR0.BYTE) +/* Base registers used for offsets on pull-up registers. */ +#define GPIO_PRV_BASE_ADDR_PULL_UP ((uint8_t volatile *)&PORT0.PCR.BYTE) +/* Base registers used for offsets on drive capacity control registers. */ +#define GPIO_PRV_BASE_ADDR_DSCR ((uint8_t volatile *)&PORT0.DSCR.BYTE) +/* Base registers used for offsets on drive capacity control registers 2. (high-speed interface high-drive) */ +#define GPIO_PRV_BASE_ADDR_DSCR2 ((uint8_t volatile *)&PORT0.DSCR2.BYTE) + +#endif + +#define GPIO_DSCR_IS_SUPPORTED /* High-drive output is supported for the RX72N */ +#define GPIO_DSCR2_IS_SUPPORTED /* Large current output, high-drive output is supported for the RX72N */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (BSP_PACKAGE_PINS == 224) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200, + GPIO_PORT_K = 0x1300, + GPIO_PORT_L = 0x1400, + GPIO_PORT_M = 0x1500, + GPIO_PORT_N = 0x1600, + GPIO_PORT_Q = 0x1700, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFF, /* Available pins: P10 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0xFF, /* Available pins: P50 to P57 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xFF, /* Available pins: P80 to P87 */ + GPIO_PORT9_PIN_MASK = 0xFF, /* Available pins: P90 to P97 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x3F, /* Available pins: PF0 to PF5 */ + GPIO_PORTG_PIN_MASK = 0xFF, /* Available pins: PG0 to PG7 */ + GPIO_PORTH_PIN_MASK = 0xFF, /* Available pins: PH0 to PH7 */ + GPIO_PORTJ_PIN_MASK = 0x2F, /* Available pins: PJ0 to PJ3, PJ5 */ + GPIO_PORTK_PIN_MASK = 0xFF, /* Available pins: PK0 to PK7 */ + GPIO_PORTL_PIN_MASK = 0xFF, /* Available pins: PL0 to PL7 */ + GPIO_PORTM_PIN_MASK = 0xFF, /* Available pins: PM0 to PM7 */ + GPIO_PORTN_PIN_MASK = 0x3F, /* Available pins: PN0 to PN5 */ + GPIO_PORTQ_PIN_MASK = 0xFF, /* Available pins: PQ0 to PQ7 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_5_PIN_7 = 0x0507, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_4 = 0x0804, + GPIO_PORT_8_PIN_5 = 0x0805, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_9_PIN_7 = 0x0907, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_0 = 0x0F00, + GPIO_PORT_F_PIN_1 = 0x0F01, + GPIO_PORT_F_PIN_2 = 0x0F02, + GPIO_PORT_F_PIN_3 = 0x0F03, + GPIO_PORT_F_PIN_4 = 0x0F04, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_G_PIN_0 = 0x1000, + GPIO_PORT_G_PIN_1 = 0x1001, + GPIO_PORT_G_PIN_2 = 0x1002, + GPIO_PORT_G_PIN_3 = 0x1003, + GPIO_PORT_G_PIN_4 = 0x1004, + GPIO_PORT_G_PIN_5 = 0x1005, + GPIO_PORT_G_PIN_6 = 0x1006, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_H_PIN_4 = 0x1104, + GPIO_PORT_H_PIN_5 = 0x1105, + GPIO_PORT_H_PIN_6 = 0x1106, + GPIO_PORT_H_PIN_7 = 0x1107, + GPIO_PORT_J_PIN_0 = 0x1200, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_2 = 0x1202, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, + GPIO_PORT_K_PIN_0 = 0x1300, + GPIO_PORT_K_PIN_1 = 0x1301, + GPIO_PORT_K_PIN_2 = 0x1302, + GPIO_PORT_K_PIN_3 = 0x1303, + GPIO_PORT_K_PIN_4 = 0x1304, + GPIO_PORT_K_PIN_5 = 0x1305, + GPIO_PORT_K_PIN_6 = 0x1306, + GPIO_PORT_K_PIN_7 = 0x1307, + GPIO_PORT_L_PIN_0 = 0x1400, + GPIO_PORT_L_PIN_1 = 0x1401, + GPIO_PORT_L_PIN_2 = 0x1402, + GPIO_PORT_L_PIN_3 = 0x1403, + GPIO_PORT_L_PIN_4 = 0x1404, + GPIO_PORT_L_PIN_5 = 0x1405, + GPIO_PORT_L_PIN_6 = 0x1406, + GPIO_PORT_L_PIN_7 = 0x1407, + GPIO_PORT_M_PIN_0 = 0x1500, + GPIO_PORT_M_PIN_1 = 0x1501, + GPIO_PORT_M_PIN_2 = 0x1502, + GPIO_PORT_M_PIN_3 = 0x1503, + GPIO_PORT_M_PIN_4 = 0x1504, + GPIO_PORT_M_PIN_5 = 0x1505, + GPIO_PORT_M_PIN_6 = 0x1506, + GPIO_PORT_M_PIN_7 = 0x1507, + GPIO_PORT_N_PIN_0 = 0x1600, + GPIO_PORT_N_PIN_1 = 0x1601, + GPIO_PORT_N_PIN_2 = 0x1602, + GPIO_PORT_N_PIN_3 = 0x1603, + GPIO_PORT_N_PIN_4 = 0x1604, + GPIO_PORT_N_PIN_5 = 0x1605, + GPIO_PORT_Q_PIN_0 = 0x1700, + GPIO_PORT_Q_PIN_1 = 0x1701, + GPIO_PORT_Q_PIN_2 = 0x1702, + GPIO_PORT_Q_PIN_3 = 0x1703, + GPIO_PORT_Q_PIN_4 = 0x1704, + GPIO_PORT_Q_PIN_5 = 0x1705, + GPIO_PORT_Q_PIN_6 = 0x1706, + GPIO_PORT_Q_PIN_7 = 0x1707, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 176) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFF, /* Available pins: P10 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0xFF, /* Available pins: P50 to P57 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xFF, /* Available pins: P80 to P87 */ + GPIO_PORT9_PIN_MASK = 0xFF, /* Available pins: P90 to P97 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x3F, /* Available pins: PF0 to PF5 */ + GPIO_PORTG_PIN_MASK = 0xFF, /* Available pins: PG0 to PG7 */ + GPIO_PORTJ_PIN_MASK = 0x2F, /* Available pins: PJ0 to PJ3, PJ5 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_5_PIN_7 = 0x0507, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_4 = 0x0804, + GPIO_PORT_8_PIN_5 = 0x0805, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_9_PIN_7 = 0x0907, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_0 = 0x0F00, + GPIO_PORT_F_PIN_1 = 0x0F01, + GPIO_PORT_F_PIN_2 = 0x0F02, + GPIO_PORT_F_PIN_3 = 0x0F03, + GPIO_PORT_F_PIN_4 = 0x0F04, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_G_PIN_0 = 0x1000, + GPIO_PORT_G_PIN_1 = 0x1001, + GPIO_PORT_G_PIN_2 = 0x1002, + GPIO_PORT_G_PIN_3 = 0x1003, + GPIO_PORT_G_PIN_4 = 0x1004, + GPIO_PORT_G_PIN_5 = 0x1005, + GPIO_PORT_G_PIN_6 = 0x1006, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_J_PIN_0 = 0x1200, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_2 = 0x1202, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 145 || BSP_PACKAGE_PINS == 144) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x7F, /* Available pins: P50 to P56 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xCF, /* Available pins: P80 to P83, P86, P87 */ + GPIO_PORT9_PIN_MASK = 0x0F, /* Available pins: P90 to P93 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x32, /* Available pins: PF5 */ + GPIO_PORTJ_PIN_MASK = 0x40, /* Available pins: PJ3, PJ5 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 100) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xA0, /* Available pins: P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x3F, /* Available pins: P50 to P55 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTJ_PIN_MASK = 0x08, /* Available pins: PJ3 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_J_PIN_3 = 0x1203, +} gpio_port_pin_t; + +#endif /* BSP_PACKAGE_PINS */ + + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* BSP_MCU_RX72N */ +#endif /* GPIO_RX72N */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/Pin.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/Pin.c new file mode 100644 index 000000000..5dd8ec142 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/Pin.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.c +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Pins_Create +* Description : This function initializes Smart Configurator pins +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Pins_Create(void) +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set CLKOUT25M pin */ + MPC.P56PFS.BYTE = 0x2AU; + PORT5.PMR.BYTE |= 0x40U; + + /* Set RXD2 pin */ + MPC.P12PFS.BYTE = 0x0AU; + PORT1.PMR.BYTE |= 0x04U; + + /* Set RXD9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BYTE |= 0x40U; + + /* Set TXD2 pin */ + PORT1.PODR.BYTE |= 0x08U; + MPC.P13PFS.BYTE = 0x0AU; + PORT1.PDR.BYTE |= 0x08U; + // PORT1.PMR.BIT.B3 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD9 pin */ + PORTB.PODR.BYTE |= 0x80U; + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PDR.BYTE |= 0x80U; + // PORTB.PMR.BIT.B7 = 1U; // Please set the PMR bit after TE bit is set to 1. + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/Pin.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/Pin.h new file mode 100644 index 000000000..563b57a07 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/Pin.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.h +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +#ifndef PIN_H +#define PIN_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Pins_Create(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_pinset.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_pinset.h new file mode 100644 index 000000000..33cd297df --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_pinset.h @@ -0,0 +1,34 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_pinset.h.h +* Version : 1.0.1 +* Description : Declares all pin code headers into a single file +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +#ifndef R_PINSET_H +#define R_PINSET_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" + +#endif /* R_PINSET_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.c new file mode 100644 index 000000000..8b23ce348 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.c @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.c +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" +#include "platform.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI2 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI2() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD2/SMISO2 pin */ + MPC.P12PFS.BYTE = 0x0AU; + PORT1.PMR.BIT.B2 = 1U; + + /* Set TXD2/SMOSI2 pin */ + MPC.P13PFS.BYTE = 0x0AU; + PORT1.PMR.BIT.B3 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI9 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI9() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD9/SMISO9/SSCL9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B6 = 1U; + + /* Set TXD9/SMOSI9/SSDA9 pin */ + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B7 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.h new file mode 100644 index 000000000..2212975ba --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_pincfg/r_sci_rx_pinset.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.h +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +#ifndef R_SCI_RX_H +#define R_SCI_RX_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +void R_SCI_PinSet_SCI2(); +void R_SCI_PinSet_SCI9(); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/r_sci_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/r_sci_rx_if.h new file mode 100644 index 000000000..c85c67cc3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/r_sci_rx_if.h @@ -0,0 +1,313 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_if.h +* Description : Functions for using SCI on RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Bumped revision for RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added RX113 support +* 11.03.2015 1.40 Consolidated with r_sci_rx64m and added support for RX71M +* 11.05.2015 1.60 Added RX231 support +* 30.09.2015 1.70 Added RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added RX24U support +* SCI_CMD_EN_TEI was Changed to ineffective, because it is meaningless command. +* 07.03.2017 2.00 Fixed a bug that send/receive is incorrect when changed setting when FIFO enabled. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 31.10.2017 2.01 Added the demo for RX65N, RX65N-2M. +* 28.09.2018 2.10 Added support RX66T +* Added SCI_CMD_COMPARE_RECEIVED_DATA command +* Added SCI_EVT_RX_CHAR_MATCH for receiving data match event +* Fixed section layout follow GSCE 5.0 +* 16.11.2018 2.11 Added XML document number +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support RX23W +* 15.08.2019 3.20 Added support RX72M +* 16.09.2019 3.21 Fixed issue in RX631/RX63N sci_initialize_ints() +* 25.11.2019 3.30 Added support RX13T. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ + +#ifndef SCI_IF_H +#define SCI_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_config.h" /* SCI config definitions */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define SCI_VERSION_MAJOR (3) +#define SCI_VERSION_MINOR (50) + +#define SCI_CLK_INT (0x00U) /* use internal clock for baud generation */ +#define SCI_CLK_EXT8X (0x03U) /* use external clock 8x baud rate (ASYNC) */ +#define SCI_CLK_EXT16X (0x02U) /* use external clock 16x baud rate (ASYNC) */ +#define SCI_DATA_7BIT (0x40U) +#define SCI_DATA_8BIT (0x00U) +#define SCI_PARITY_ON (0x20U) +#define SCI_PARITY_OFF (0x00U) +#define SCI_ODD_PARITY (0x10U) +#define SCI_EVEN_PARITY (0x00U) +#define SCI_STOPBITS_2 (0x08U) +#define SCI_STOPBITS_1 (0x00U) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +typedef enum e_sci_ch // SCI channel numbers +{ + SCI_CH0=0, + SCI_CH1, + SCI_CH2, + SCI_CH3, + SCI_CH4, + SCI_CH5, + SCI_CH6, + SCI_CH7, + SCI_CH8, + SCI_CH9, + SCI_CH10, + SCI_CH11, + SCI_CH12, + SCI_NUM_CH +} sci_ch_t; + + +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_MAX, // End of modes currently supported +} sci_mode_t; + + +typedef enum e_sci_err /* SCI API error codes */ +{ + SCI_SUCCESS=0, + SCI_ERR_BAD_CHAN, // non-existent channel number + SCI_ERR_OMITTED_CHAN, // SCI_CHx_INCLUDED is 0 in config.h + SCI_ERR_CH_NOT_CLOSED, // chan still running in another mode + SCI_ERR_BAD_MODE, // unsupported or incorrect mode for channel + SCI_ERR_INVALID_ARG, // argument is not one of the predefined values + SCI_ERR_NULL_PTR, // received null ptr; missing required argument + SCI_ERR_XCVR_BUSY, // cannot start data transfer; transceiver busy + + /* Asynchronous mode only */ + SCI_ERR_QUEUE_UNAVAILABLE, // can't open tx or rx queue or both + SCI_ERR_INSUFFICIENT_SPACE, // not enough space in transmit queue + SCI_ERR_INSUFFICIENT_DATA, // not enough data in receive queue + + /* Synchronous/SSPI modes only */ + SCI_ERR_XFER_NOT_DONE // data transfer still in progress +} sci_err_t; + + +/* CHANNEL CONTROL BLOCK HANDLE */ + +typedef struct st_sci_ch_ctrl * sci_hdl_t; + + +/* SCI_OPEN() ARGUMENT DEFINITIONS (do NOT change values) */ + +typedef enum e_sci_spi_mode +{ + SCI_SPI_MODE_OFF = 1, /* channel is in synchronous mode */ + + SCI_SPI_MODE_0 = 0x80, /* SPMR Register CKPH=1, CKPOL=0 + Mode 0: 00 CPOL=0 resting lo, CPHA=0 leading edge/rising */ + SCI_SPI_MODE_1 = 0x40, /* SPMR Register CKPH=0, CKPOL=1 + Mode 1: 01 CPOL=0 resting lo, CPHA=1 trailing edge/falling */ + SCI_SPI_MODE_2 = 0xC0, /* SPMR Register CKPH=1, CKPOL=1 + Mode 2: 10 CPOL=1 resting hi, CPHA=0 leading edge/falling */ + SCI_SPI_MODE_3 = 0x00 /* SPMR Register CKPH=0, CKPOL=0 + Mode 3: 11 CPOL=1 resting hi, CPHA=1 trailing edge/rising */ +} sci_spi_mode_t; + + +/* Open() p_cfg structure when mode=SCI_MODE_ASYNC */ +typedef struct st_sci_uart +{ + uint32_t baud_rate; // ie 9600, 19200, 115200 + uint8_t clk_src; // use SCI_CLK_INT/EXT8X/EXT16X + uint8_t data_size; // use SCI_DATA_nBIT + uint8_t parity_en; // use SCI_PARITY_ON/OFF + uint8_t parity_type; // use SCI_ODD/EVEN_PARITY + uint8_t stop_bits; // use SCI_STOPBITS_1/2 + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_uart_t; + + +/* Open() p_cfg structure when mode = SCI_MODE_SYNC or SCI_MODE_SSPI */ +typedef struct st_sci_sync_sspi +{ + sci_spi_mode_t spi_mode; // clock polarity and phase; unused for sync + uint32_t bit_rate; // ie 1000000 for 1Mbps + bool msb_first; + bool invert_data; + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_sync_sspi_t; + +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; +} sci_cfg_t; + + +/* CALLBACK FUNCTION ARGUMENT DEFINITIONS */ + +typedef enum e_sci_cb_evt // callback function events +{ + /* Async Events */ + SCI_EVT_TEI, // TEI interrupt occurred; transmitter is idle + SCI_EVT_RX_CHAR, // received a character; already placed in queue + SCI_EVT_RX_CHAR_MATCH, // received a matched character; already placed in queue + SCI_EVT_RXBUF_OVFL, // rx queue is full; can't save anymore data + SCI_EVT_FRAMING_ERR, // receiver hardware framing error + SCI_EVT_PARITY_ERR, // receiver hardware parity error + + /* SSPI/Sync Events */ + SCI_EVT_XFER_DONE, // transfer completed + SCI_EVT_XFER_ABORTED, // transfer aborted + + /* Common Events */ + SCI_EVT_OVFL_ERR // receiver hardware overrun error +} sci_cb_evt_t; + +typedef struct st_sci_cb_args // callback arguments +{ + sci_hdl_t hdl; + sci_cb_evt_t event; + uint8_t byte; // byte read when error occurred (unused for TEI, XFER_DONE) + uint8_t num; // Number of bytes were stored to queue (used only async(FIFO)) +} sci_cb_args_t; + + +/* SCI_CONTROL() ARGUMENT DEFINITIONS */ + +/* commands */ +typedef enum e_sci_cmd +{ + /* All modes */ + SCI_CMD_CHANGE_BAUD, /* change baud/bit rate */ +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || (SCI_CFG_CH8_FIFO_INCLUDED) || (SCI_CFG_CH9_FIFO_INCLUDED) || (SCI_CFG_CH10_FIFO_INCLUDED) || (SCI_CFG_CH11_FIFO_INCLUDED)) + SCI_CMD_CHANGE_TX_FIFO_THRESH, /* change TX FIFO threshold */ + SCI_CMD_CHANGE_RX_FIFO_THRESH, /* change RX FIFO threshold */ +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + SCI_CMD_SET_RXI_PRIORITY, /* change RXI priority level */ + SCI_CMD_SET_TXI_PRIORITY, /* change TXI priority level */ +#endif + + /* Async commands */ + SCI_CMD_EN_NOISE_CANCEL, /* enable noise cancellation */ + SCI_CMD_EN_TEI, /* SCI_CMD_EN_TEI is obsolete command, + but it exists only for compatibility with older version. */ + SCI_CMD_OUTPUT_BAUD_CLK, /* output baud clock on the SCK pin */ + SCI_CMD_START_BIT_EDGE, /* detect start bit as falling edge of RXDn pin + (default detect as low level on RXDn pin) */ + SCI_CMD_GENERATE_BREAK, /* generate break condition */ + SCI_CMD_TX_Q_FLUSH, /* flush transmit queue */ + SCI_CMD_RX_Q_FLUSH, /* flush receive queue */ + SCI_CMD_TX_Q_BYTES_FREE, /* get count of unused transmit queue bytes */ + SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ, /* get num bytes ready for reading */ + SCI_CMD_COMPARE_RECEIVED_DATA, /* Compare received data with comparison data */ + + /* Async/Sync commands */ + SCI_CMD_EN_CTS_IN, /* enable CTS input (default RTS output) */ + + /* SSPI/Sync commands */ + SCI_CMD_CHECK_XFER_DONE, /* see if send, rcv, or both are done; SCI_SUCCESS if yes */ + SCI_CMD_ABORT_XFER, + SCI_CMD_XFER_LSB_FIRST, /* start from LSB bit when sending */ + SCI_CMD_XFER_MSB_FIRST, /* start from MSB bit when sending */ + SCI_CMD_INVERT_DATA, /* logic level of send/receive data is invert */ + + /* SSPI commands */ + SCI_CMD_CHANGE_SPI_MODE /* change clock polarity and phase in SSPI mode */ +} sci_cmd_t; + +/* SCI_CMD_CHANGE_BAUD/CHANGE_BITRATE take a ptr to this structure for *p_args */ +typedef struct st_sci_baud +{ + uint32_t pclk; // peripheral clock speed; e.g. 24000000 is 24MHz + uint32_t rate; // e.g. 9600, 19200, 115200 +} sci_baud_t; + +/* SCI_CMD_TX_Q_BYTES_FREE and SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ take a pointer + to a uint16_t for p_args */ + +/* SCI_CMD_SET_RXI_PRIORITY and SCI_CMD_SET_TXI_PRIORITY take a pointer to a + uint8_t for p_args */ + +/* SCI_CMD_CHANGE_SPI_MODE takes a pointer to an sci_spi_mode_t for p_args */ + +/***************************************************************************** +Public Functions +******************************************************************************/ +sci_err_t R_SCI_Open(uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl); + +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, // SSPI/SYNC only + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length); + +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); + +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); + +sci_err_t R_SCI_Close(sci_hdl_t const hdl); + +uint32_t R_SCI_GetVersion(void); + + +#endif /* SCI_IF_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/readme.txt new file mode 100644 index 000000000..8ff173dcb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/readme.txt @@ -0,0 +1,78 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS DRIVER FOR MORE INFORMATION + +r_sci_rx +======== + +Overview +-------------------------------------------------------------------------------- +The r_sci_rx module is a multi-channel, multi-mode, interrupt-driven driver which +supports Asynchronous, Master Synchronous, and Single Master Simple SPI (SSPI) +operation for the SCI peripherals. The API includes standard functions +to initialize a channel and to send and receive data, as well as a special control +function for taking actions such as issuing a break signal or enabling noise +cancellation. The driver supports all channels available on the mcu. The driver +can be reduced in size by removing code used for parameter checking, unused +channels, or unused modes. These configuration options can be found in +"r_config\r_sci_rx_config.h". An original copy of the configuration file +is stored in "r_sci_rx\ref\r_sci_rx_config_reference.h". + + +Features +-------- +* (RX110/111/113, RX65N/651) Simultaneous operation of up to 13 channels. +* (RX231/230) Simultaneous operation of up to 7 channels. +* (RX23T) Simultaneous operation of up to 2 channels. +* (RX23W) Simultaneous operation of up to 4 channels. +* (RX64M, RX71M) Simultaneous operation of up to 9 channels. +* (RX130) Simultaneous operation of up to 4 channels. +* (RX13T) Simultaneous operation of up to 3 channels. +* (RX24T) Simultaneous operation of up to 3 channels. +* (RX24U) Simultaneous operation of up to 6 channels. +* (RX66T) Simultaneous operation of up to 7 channels +* (RX72T) Simultaneous operation of up to 7 channels +* (RX72M) Simultaneous operation of up to 13 channels +* (RX72N) Simultaneous operation of up to 13 channels +* (RX66N) Simultaneous operation of up to 13 channels +* (RX23E-A) Simultaneous operation of up to 4 channels +* Simultaneous operation of Async, Sync, or SSPI modes on different channels. +* Queueing of incoming and outgoing data for Asynchronous channels. +* Interrupt driven. + + +File Structure +-------------- +r_sci_rx +| readme.txt +| r_sci_rx_if.h +| ++---doc +| +---ja +| | r01an1815jj{VERSION_NUMBER}-rx-serial.pdf +| +---en +| r01an1815ej{VERSION_NUMBER}-rx-serial.pdf +| ++---ref +| r_sci_rx_config_reference.h +| ++---src + | r_sci_rx.c + | r_sci_rx_platform.h + | r_sci_rx_private.h + | + +---targets + | + +---rx110 + | r_sci_rx110.c + | r_sci_rx110_data.c + | r_sci_rx110_private.h + +---rx111 + | r_sci_rx111.c + | r_sci_rx111_data.c + | r_sci_rx111_private.h + : + +r_config + r_sci_rx_config.h + +r_sci_rx.ftl + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h new file mode 100644 index 000000000..ea287d649 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h @@ -0,0 +1,198 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (1) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * RX MCU supported channels + * + * CH# 110 111 113 130 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N RX23E-A + * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------- + * CH0 X Xa X X X X Xn X X X + * CH1 X X* X* Xu X X Xu Xu Xu X X Xs X X X X X X X Xu + * CH2 X X X Xu X X X + * CH3 X X Xs X X X + * CH4 X X Xn X X X + * CH5 X X X X X Xu X X X X X X X X X X X X X X + * CH6 X X X X X X X X Xn X X Xu X X X + * CH7 Xu Xu Xn X X X + * CH8 X Xa X X X X X X Xu X X X + * CH9 X Xa X X X Xs X X X X X + * CH10 X X X X + * CH11 X Xs X X X X X + * CH12 X X X X X X X X Xs X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (0) +#define SCI_CFG_CH1_INCLUDED (1) +#define SCI_CFG_CH2_INCLUDED (0) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (0) +#define SCI_CFG_CH6_INCLUDED (0) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (0) +#define SCI_CFG_CH9_INCLUDED (0) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (0) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY) 1 lowest, 15 highest */ + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj and SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +#endif /* SCI_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx.c new file mode 100644 index 000000000..d103e1438 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx.c @@ -0,0 +1,2349 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016-2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx.c +* Description : Functions for using SCI on RX devices. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 FIT_NO_PTR check added to NULL check. +* Fixed a bug that may receive data more than the specified number of bytes +* on Clock Synchronous Mode. +* Fixed that R_SCI_Control function returns SCI_ERR_INVALID_ARG +* when using SCI_CMD_EN_CTS_IN on Simple SPI mode. +* Fix to clear error flag even if callback function is not set. +* Deleted unnecessary bit mask of SSR register from sci_error function. +* 07.03.2017 2.00 Fixed a bug that error condition not clear when FIFO enabled. +* Fixed a bug that where commands used only when FIFO mode is enable did not NULL check. +* Fixed a bug that sending data is overwrote by new R_SCI_Send() when FIFO(async) enabled. +* Fixed a bug that sending data is break up by new R_SCI_Send() when FIFO(sync) enabled. +* Fixed a bug that the new FIFO threshold was retained only on first receive. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 28.09.2018 2.10 Added support RX66T +* Add WAIT_LOOP comments. +* Fixed a bug that leaking memory in R_SCI_Open() when FIFO(async) enabled. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin. +* Fix GSCE Code Checker errors. +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support for RX72M +* 25.11.2019 3.30 Added support RX13T. +* Modified comment of API function to Doxygen style. +* Added support for atomic control. +* Fixed to comply with GSCE Coding Standards Rev.6.00. +* Fixed a bug that error when a reception interrupt occurs before incrementing "u_tx_data.buf" +* in "sci_send_sync_data" and "sci_receive" functions +* 30.12.2019 3.40 Added support RX66N, RX72N. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +/* Defines for SCI support */ +#include "r_sci_rx_private.h" + +/* Include specifics for chosen MCU. */ +#include "r_sci_rx_platform.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_init_queues(uint8_t const chan); + +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte); + +static void sci_transfer(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_transfer(sci_hdl_t const hdl); +#endif + +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static sci_err_t sci_init_sync(sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data); + +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +static void power_on(sci_hdl_t const hdl); +static void power_off(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static sci_err_t sci_init_fifo(sci_hdl_t const hdl); +#endif + +static void sci_receive(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static void sci_fifo_receive_sync(sci_hdl_t const hdl); +#endif + +static void sci_fifo_receive(sci_hdl_t const hdl); + +#endif + +#if SCI_CFG_DATA_MATCH_INCLUDED +static void sci_receive_data_match(sci_hdl_t const hdl); +#endif + +static void sci_error(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_error(sci_hdl_t const hdl); +#endif + +/* queue buffers */ +#if (SCI_CFG_ASYNC_INCLUDED) + +#if SCI_CFG_CH0_INCLUDED +static uint8_t ch0_tx_buf[SCI_CFG_CH0_TX_BUFSIZ]; +static uint8_t ch0_rx_buf[SCI_CFG_CH0_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH1_INCLUDED +static uint8_t ch1_tx_buf[SCI_CFG_CH1_TX_BUFSIZ]; +static uint8_t ch1_rx_buf[SCI_CFG_CH1_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH2_INCLUDED +static uint8_t ch2_tx_buf[SCI_CFG_CH2_TX_BUFSIZ]; +static uint8_t ch2_rx_buf[SCI_CFG_CH2_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH3_INCLUDED +static uint8_t ch3_tx_buf[SCI_CFG_CH3_TX_BUFSIZ]; +static uint8_t ch3_rx_buf[SCI_CFG_CH3_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH4_INCLUDED +static uint8_t ch4_tx_buf[SCI_CFG_CH4_TX_BUFSIZ]; +static uint8_t ch4_rx_buf[SCI_CFG_CH4_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH5_INCLUDED +static uint8_t ch5_tx_buf[SCI_CFG_CH5_TX_BUFSIZ]; +static uint8_t ch5_rx_buf[SCI_CFG_CH5_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH6_INCLUDED +static uint8_t ch6_tx_buf[SCI_CFG_CH6_TX_BUFSIZ]; +static uint8_t ch6_rx_buf[SCI_CFG_CH6_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH7_INCLUDED +static uint8_t ch7_tx_buf[SCI_CFG_CH7_TX_BUFSIZ]; +static uint8_t ch7_rx_buf[SCI_CFG_CH7_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH8_INCLUDED +static uint8_t ch8_tx_buf[SCI_CFG_CH8_TX_BUFSIZ]; +static uint8_t ch8_rx_buf[SCI_CFG_CH8_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH9_INCLUDED +static uint8_t ch9_tx_buf[SCI_CFG_CH9_TX_BUFSIZ]; +static uint8_t ch9_rx_buf[SCI_CFG_CH9_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH10_INCLUDED +static uint8_t ch10_tx_buf[SCI_CFG_CH10_TX_BUFSIZ]; +static uint8_t ch10_rx_buf[SCI_CFG_CH10_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH11_INCLUDED +static uint8_t ch11_tx_buf[SCI_CFG_CH11_TX_BUFSIZ]; +static uint8_t ch11_rx_buf[SCI_CFG_CH11_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH12_INCLUDED +static uint8_t ch12_tx_buf[SCI_CFG_CH12_TX_BUFSIZ]; +static uint8_t ch12_rx_buf[SCI_CFG_CH12_RX_BUFSIZ]; +#endif + +#endif /* #if (SCI_CFG_ASYNC_INCLUDED) */ + +extern const sci_hdl_t g_handles[SCI_NUM_CH]; + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Open +********************************************************************************************************************//** +* @brief This function applies power to the SCI channel, initializes the associated registers, enables interrupts, and +* provides the channel handle for use with other API functions. This function must be called before calling any +* other API functions +* @param[in] chan Channel to initialize. +* +* @param[in] mode Operational mode (see enumeration below) +* @code +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_MAX // End of modes currently supported +} sci_mode_t; +* @endcode +* @param[in] p_cfg Pointer to configuration union, structure elements (see below) are specific to mode +* @code +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; +} sci_cfg_t; +* @endcode +* +* @param[in] p_callback Pointer to function called from interrupt when an RXI or receiver error is detected or +* for transmit end (TEI) condition. See Section 2.11 Callback Function in application note for details. +* +* @param[in] p_hdl Pointer to a handle for channel (value set here) +* Confirm the return value from R_SCI_Open is “SCI_SUCCESS” and then set the first parameter for the +* other APIs except R_SCI_GetVersion(). See Section 2.9 Parameters in the application note for details. +* +* +* @retval SCI_SUCCESS Successful; channel initialized +* +* @retval SCI_ERR_BAD_CHAN Channel number is invalid for part +* +* @retval SCI_ERR_OMITTED_CHAN Corresponding SCI_CHx_INCLUDED is invalid (0) +* +* @retval SCI_ERR_CH_NOT_CLOSED Channel currently in operation; Perform R_SCI_Close() first +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_NULL_PTR p_cfg pointer is NULL +* +* @retval SCI_ERR_INVALID_ARG An element of the p_cfg structure contains an invalid value. +* +* @retval SCI_ERR_QUEUE_UNAVAILABLE Cannot open transmit or receive queue or both (Asynchronous mode). +* @details Initializes an SCI channel for a particular mode and provides a Handle in *p_hdl for use with other API +* functions. RXI and ERI interrupts are enabled in all modes. TXI is enabled in Asynchronous mode +* @note The driver calculates the optimum values for BRR, SEMR.ABCS, and SMR.CKS using BSP_PCLKA_HZ and +* BSP_PCLKB_HZ as defined in mcu_info.h of the board support package. This however does not guarantee +* a low bit error rate for all peripheral clock/baud rate combinations. +* If an external clock is used in Asynchronous mode, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Open() in the application note for details. +*/ +sci_err_t R_SCI_Open(uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl) +{ + sci_err_t err = SCI_SUCCESS; + uint8_t priority = 1; + + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + err = sci_mcu_param_check(chan); + if (SCI_SUCCESS != err) + { + return err; + } + + /* Check argument g_handles */ + if ((NULL == g_handles[chan]) || (FIT_NO_PTR == g_handles[chan])) + { + return SCI_ERR_OMITTED_CHAN; + } + if (SCI_MODE_OFF != g_handles[chan]->mode) + { + return SCI_ERR_CH_NOT_CLOSED; + } + if ((SCI_MODE_OFF == mode) || (SCI_MODE_MAX <= mode)) + { + return SCI_ERR_BAD_MODE; + } + + /* Check argument p_cfg, p_hdl */ + if (((NULL == p_cfg) || (NULL == p_hdl)) || ((FIT_NO_PTR == p_cfg) || (FIT_NO_PTR == p_hdl))) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* APPLY POWER TO CHANNEL */ + power_on(g_handles[chan]); + + /* INITIALIZE REGISTER */ + sci_init_register(g_handles[chan]); + + /* INITIALIZE MODE SPECIFIC FEATURES */ + g_handles[chan]->mode = mode; + if (SCI_MODE_ASYNC == mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_uart_t type is valid */ + err = sci_init_async(g_handles[chan], (sci_uart_t *)p_cfg, &priority); +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_sync_sspi_t type is valid */ + err = sci_init_sync(g_handles[chan], (sci_sync_sspi_t *)p_cfg, &priority); +#endif + } + + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + g_handles[chan]->callback = p_callback; + + /* INITIALIZE TX AND RX QUEUES */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == mode) + { + err = sci_init_queues(chan); + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + +#if SCI_CFG_FIFO_INCLUDED + if (true == g_handles[chan]->fifo_ctrl) + { + /* INITIALIZE TX AND RX FIFO */ + err = sci_init_fifo(g_handles[chan]); + if (SCI_SUCCESS != err) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* DE-INITIALIZE TX AND RX QUEUES */ + if (SCI_MODE_ASYNC == mode) + { + R_BYTEQ_Close(g_handles[chan]->u_tx_data.que); + R_BYTEQ_Close(g_handles[chan]->u_rx_data.que); + } +#endif + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + + /* ENABLE INTERRUPTS */ + sci_initialize_ints(g_handles[chan], priority); + + /* FINISH */ + *p_hdl = g_handles[chan]; + + return SCI_SUCCESS; +} /* End of function R_SCI_Open() */ + +/***************************************************************************** +* Function Name: power_on +* Description : This function provides power to the channel referenced by +* the handle by taking it out of the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_on(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) &= (~hdl->rom->stop_mask); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_on() */ + +/***************************************************************************** +* Function Name: power_off +* Description : This function removes power to the channel referenced by +* handle by putting it into the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_off(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) |= (hdl->rom->stop_mask); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_off() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_queues +* Description : This function attaches transmit and receive queues to the +* channel. +* +* Arguments : chan - +* channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_QUEUE_UNAVAILABLE - +* no queue control blocks available +******************************************************************************/ +static sci_err_t sci_init_queues(uint8_t const chan) +{ + byteq_err_t q_err1 = BYTEQ_ERR_INVALID_ARG; + byteq_err_t q_err2 = BYTEQ_ERR_INVALID_ARG; + sci_err_t err = SCI_SUCCESS; + + /* channel number verified as legal prior to calling this function */ + switch (chan) + { +#if SCI_CFG_CH0_INCLUDED + case (SCI_CH0): + { + q_err1 = R_BYTEQ_Open(ch0_tx_buf, SCI_CFG_CH0_TX_BUFSIZ, &g_handles[SCI_CH0]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch0_rx_buf, SCI_CFG_CH0_RX_BUFSIZ, &g_handles[SCI_CH0]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH1_INCLUDED + case (SCI_CH1): + { + q_err1 = R_BYTEQ_Open(ch1_tx_buf, SCI_CFG_CH1_TX_BUFSIZ, &g_handles[SCI_CH1]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch1_rx_buf, SCI_CFG_CH1_RX_BUFSIZ, &g_handles[SCI_CH1]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH2_INCLUDED + case (SCI_CH2): + { + q_err1 = R_BYTEQ_Open(ch2_tx_buf, SCI_CFG_CH2_TX_BUFSIZ, &g_handles[SCI_CH2]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch2_rx_buf, SCI_CFG_CH2_RX_BUFSIZ, &g_handles[SCI_CH2]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH3_INCLUDED + case (SCI_CH3): + { + q_err1 = R_BYTEQ_Open(ch3_tx_buf, SCI_CFG_CH3_TX_BUFSIZ, &g_handles[SCI_CH3]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch3_rx_buf, SCI_CFG_CH3_RX_BUFSIZ, &g_handles[SCI_CH3]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH4_INCLUDED + case (SCI_CH4): + { + q_err1 = R_BYTEQ_Open(ch4_tx_buf, SCI_CFG_CH4_TX_BUFSIZ, &g_handles[SCI_CH4]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch4_rx_buf, SCI_CFG_CH4_RX_BUFSIZ, &g_handles[SCI_CH4]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH5_INCLUDED + case (SCI_CH5): + { + q_err1 = R_BYTEQ_Open(ch5_tx_buf, SCI_CFG_CH5_TX_BUFSIZ, &g_handles[SCI_CH5]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch5_rx_buf, SCI_CFG_CH5_RX_BUFSIZ, &g_handles[SCI_CH5]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH6_INCLUDED + case (SCI_CH6): + { + q_err1 = R_BYTEQ_Open(ch6_tx_buf, SCI_CFG_CH6_TX_BUFSIZ, &g_handles[SCI_CH6]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch6_rx_buf, SCI_CFG_CH6_RX_BUFSIZ, &g_handles[SCI_CH6]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH7_INCLUDED + case (SCI_CH7): + { + q_err1 = R_BYTEQ_Open(ch7_tx_buf, SCI_CFG_CH7_TX_BUFSIZ, &g_handles[SCI_CH7]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch7_rx_buf, SCI_CFG_CH7_RX_BUFSIZ, &g_handles[SCI_CH7]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH8_INCLUDED + case (SCI_CH8): + { + q_err1 = R_BYTEQ_Open(ch8_tx_buf, SCI_CFG_CH8_TX_BUFSIZ, &g_handles[SCI_CH8]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch8_rx_buf, SCI_CFG_CH8_RX_BUFSIZ, &g_handles[SCI_CH8]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH9_INCLUDED + case (SCI_CH9): + { + q_err1 = R_BYTEQ_Open(ch9_tx_buf, SCI_CFG_CH9_TX_BUFSIZ, &g_handles[SCI_CH9]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch9_rx_buf, SCI_CFG_CH9_RX_BUFSIZ, &g_handles[SCI_CH9]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH10_INCLUDED + case (SCI_CH10): + { + q_err1 = R_BYTEQ_Open(ch10_tx_buf, SCI_CFG_CH10_TX_BUFSIZ, &g_handles[SCI_CH10]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch10_rx_buf, SCI_CFG_CH10_RX_BUFSIZ, &g_handles[SCI_CH10]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH11_INCLUDED + case (SCI_CH11): + { + q_err1 = R_BYTEQ_Open(ch11_tx_buf, SCI_CFG_CH11_TX_BUFSIZ, &g_handles[SCI_CH11]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch11_rx_buf, SCI_CFG_CH11_RX_BUFSIZ, &g_handles[SCI_CH11]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH12_INCLUDED + case (SCI_CH12): + { + q_err1 = R_BYTEQ_Open(ch12_tx_buf, SCI_CFG_CH12_TX_BUFSIZ, &g_handles[SCI_CH12]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch12_rx_buf, SCI_CFG_CH12_RX_BUFSIZ, &g_handles[SCI_CH12]->u_rx_data.que); + break; + } +#endif + default: + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + break; + } + } + + if ((BYTEQ_SUCCESS != q_err1) || (BYTEQ_SUCCESS != q_err2)) + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + } + return err; +} /* End of function sci_init_queues() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_init_fifo +* Description : This function the setting of the FIFO mode, reset of the +* TX/RX FIFO, and the threshold setting of the TX/RX FIFO. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* fifo initialized successfully +* SCI_ERR_INVALID_ARG - +* element of hdl contains illegal value +******************************************************************************/ +static sci_err_t sci_init_fifo(sci_hdl_t const hdl) +{ + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (hdl->tx_dflt_thresh > 15) + { + return SCI_ERR_INVALID_ARG; + } + if ((hdl->rx_dflt_thresh < 1) || (hdl->rx_dflt_thresh > 15)) + { + return SCI_ERR_INVALID_ARG; + } +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if (hdl->tx_dflt_thresh != hdl->rx_dflt_thresh) + { + return SCI_ERR_INVALID_ARG; + } +#endif +#endif + + /* FIFO Mode Select (1:FIFO mode) */ + hdl->rom->regs->FCR.BIT.FM = 0x01; + + /* reset TX/RX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* set TX/RX FIFO threshold initial value */ + hdl->rom->regs->FCR.BIT.TTRG = hdl->tx_dflt_thresh; + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_dflt_thresh; + + return SCI_SUCCESS; +} /* End of function sci_init_fifo() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_async +* Description : This function initializes the control block and UART +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to Uart configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (((SCI_DATA_8BIT != p_cfg->data_size) && (SCI_DATA_7BIT != p_cfg->data_size)) + || ((SCI_STOPBITS_1 != p_cfg->stop_bits) && (SCI_STOPBITS_2 != p_cfg->stop_bits)) + || ((p_cfg->int_priority < (BSP_MCU_IPL_MIN+1)) || (p_cfg->int_priority > BSP_MCU_IPL_MAX))) + { + return SCI_ERR_INVALID_ARG; + } + + if (SCI_PARITY_ON == p_cfg->parity_en) + { + if ((SCI_EVEN_PARITY != p_cfg->parity_type) && (SCI_ODD_PARITY != p_cfg->parity_type)) + { + return SCI_ERR_INVALID_ARG; + } + } + else if (SCI_PARITY_OFF != p_cfg->parity_en) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + if (SCI_CLK_INT == p_cfg->clk_src) + { + if (0 == p_cfg->baud_rate) + { + return SCI_ERR_INVALID_ARG; + } + } + else if ((SCI_CLK_EXT8X != p_cfg->clk_src) && (SCI_CLK_EXT16X != p_cfg->clk_src)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + + + /* Configure SMR for asynchronous mode, single processor, and user settings */ + if (SCI_PARITY_OFF == p_cfg->parity_en) + { + p_cfg->parity_type = 0; // ensure random value is not ORed into SMR + } + + /* Configure SMR */ + hdl->rom->regs->SMR.BYTE = (uint8_t)((p_cfg->data_size | p_cfg->stop_bits) | (p_cfg->parity_en | p_cfg->parity_type)); + + /* SETUP CLOCK FOR BAUD RATE */ + + if (SCI_CLK_INT == p_cfg->clk_src) + { + /* Use internal clock for baud rate */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->baud_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = p_cfg->baud_rate; // save baud rate for break generation + } + } + else + { + /* Use external clock for baud rate */ + hdl->rom->regs->SCR.BIT.CKE = 0x02; + hdl->rom->regs->SEMR.BIT.ABCS = (SCI_CLK_EXT8X == p_cfg->clk_src) ? 1 : 0; + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_async() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_sync +* Description : This function initializes the control block and SYNC/SSPI +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to SSPI configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_sync(sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err = SCI_SUCCESS; + int32_t bit_err; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((SCI_MODE_SSPI == hdl->mode) + && (SCI_SPI_MODE_0 != p_cfg->spi_mode) && (SCI_SPI_MODE_1 != p_cfg->spi_mode) + && (SCI_SPI_MODE_2 != p_cfg->spi_mode) && (SCI_SPI_MODE_3 != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else if ((SCI_MODE_SYNC == hdl->mode) && (SCI_SPI_MODE_OFF != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + + if (0 == p_cfg->bit_rate) + { + return SCI_ERR_INVALID_ARG; + } + + if ((0 == p_cfg->int_priority) || (p_cfg->int_priority > BSP_MCU_IPL_MAX)) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + hdl->tx_dummy = false; + + /* Configure SMR for SSPI/SYNC mode */ + hdl->rom->regs->SMR.BYTE = 0x80; + hdl->rom->regs->SCMR.BIT.SMIF = 0; /* default */ + hdl->rom->regs->SIMR1.BIT.IICM = 0; /* default */ + + /* Configure SPI register for clock polarity/phase and single master */ + if (SCI_MODE_SSPI == hdl->mode) + { + hdl->rom->regs->SPMR.BYTE = p_cfg->spi_mode; + } + else /* synchronous operation */ + { + hdl->rom->regs->SPMR.BYTE = 0; + } + + /* Configure data inversion */ + hdl->rom->regs->SCMR.BIT.SINV = (uint8_t)((true == p_cfg->invert_data) ? 1 : 0); + + /* Configure bit order */ + hdl->rom->regs->SCMR.BIT.SDIR = (uint8_t)((true == p_cfg->msb_first) ? 1 : 0); + + + /* SETUP CLOCK FOR BIT RATE */ + + /* Use internal clock for bit rate (master) */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->bit_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; /* impossible bit rate; 100% error */ + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_sync() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Send +********************************************************************************************************************//** +* @brief Initiates transmit if transmitter is not in use. Queues data for later transmit when in Asynchronous mode. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_src Pointer to data to transmit +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Transmit initiated or loaded into queue (Asynchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_SPACE Insufficient space in queue to load all data (Asynchronous) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous) +* +* +* @details In asynchronous mode, this function places data into a transmit queue if the transmitter for the SCI channel +* referenced by the handle is not in use. In SSPI and Synchronous modes, no data is queued and transmission begins immediately +* if the transceiver is not already in use. All transmissions are handled at the interrupt level.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave Select line +* for the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* @note None +*/ +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err=SCI_SUCCESS; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_src */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl)) || ((NULL == p_src) || (FIT_NO_PTR == p_src))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_send_async_data(hdl, p_src, length); +#endif + } + else + { + /* SSPI or SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_send_sync_data(hdl, p_src, NULL, length, false); +#endif + } + + return err; +} /* End of function R_SCI_Send() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_async_data +* Description : This function determines if the tx byte queue of the channel +* referenced by the handle is not full, and call the byte +* transmission function. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* length - +* number of bytes to send and possibly receive +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_ERR_QUEUE_FULL; + + if (true != hdl->tx_idle ) + { + return SCI_ERR_XCVR_BUSY; + } + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* TX FIFO use check */ + if (0x00 < hdl->rom->regs->FDR.BIT.T) + { + return SCI_ERR_XCVR_BUSY; + } + + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + } +#endif + + /* Determine amount of space left in tx queue */ + R_BYTEQ_Unused(hdl->u_tx_data.que, &cnt); + + if (cnt < length) + { + /* If can't fit, return */ + return SCI_ERR_INSUFFICIENT_SPACE; + } + + /* Else load bytes into tx queue for transmission */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { + byteq_err = sci_put_byte(hdl, *p_src++); + if (BYTEQ_SUCCESS != byteq_err) + { + /* If the return value is not BYTEQ_SUCCESS. */ + err = SCI_ERR_INSUFFICIENT_SPACE; + break; + } + } + + if (SCI_SUCCESS == err) + { + hdl->tx_idle = false; + ENABLE_TXI_INT; + } + + return err; +} /* End of function sci_send_async_data() */ + +/***************************************************************************** +* Function Name: sci_put_byte +* Description : Transmits byte if channel is not busy. Otherwise, byte is +* stored in tx queue until can transmit. If buffer is full +* and cannot store it, an error code is returned. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* byte - +* byte to transmit +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte) +{ + byteq_err_t err = BYTEQ_ERR_QUEUE_FULL; + + /* else load next byte into tx queue (space checked in calling func) */ + err = R_BYTEQ_Put(hdl->u_tx_data.que, byte); + + return err; +} /* End of function sci_put_byte() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and begins the data transfer process +* (both sending and receiving data). +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* p_dst - +* ptr to buffer to store receive data (optional) +* length - +* number of bytes to send and possibly receive +* save_rx_data - +* true if data clocked in should be saved to p_dst. +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + if (true == hdl->tx_idle) + { + if (true == save_rx_data) + { + hdl->u_rx_data.buf = p_dst; + } + hdl->save_rx_data = save_rx_data; + + hdl->u_tx_data.buf = p_src; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_idle = false; + hdl->tx_dummy = false; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + + thresh_cnt = hdl->rom->regs->FCR.BIT.RTRG; + + hdl->tx_cnt -= thresh_cnt; + + /* Repeated FIFO RX threshold count */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + if(0 != cnt) + { + hdl->u_tx_data.buf++; + } + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + } + else +#endif + { + hdl->tx_cnt--; + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_send_sync_data() */ +#endif /* SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/*********************************************************************************************************************** +* Function Name: R_SCI_SendReceive +********************************************************************************************************************//** +* @brief For Synchronous and SSPI modes only. Transmits and receives data simultaneously if the transceiver is not +* in use. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* @param[in] p_src Pointer to data to transmit +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Data transfer initiated +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Channel mode not SSPI or Synchronous +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy +* @details If the transceiver is not in use, this function clocks out data from the p_src buffer while simultaneously +* clocking in data and placing it in the p_dst buffer. +* Note that the toggling of Slave Select lines for SSPI is not handled by this driver. The Slave Select line for +* the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +*/ +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check arguments */ + if ((((NULL == hdl) || (FIT_NO_PTR == hdl)) /* Check if hdl is available or not */ + || ((NULL == p_src) || (FIT_NO_PTR == p_src))) /* Check if p_src is available or not */ + || ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) /* Check if p_dst is available or not */ + { + return SCI_ERR_NULL_PTR; + } + + if ((SCI_MODE_SSPI != hdl->mode) && (SCI_MODE_SYNC != hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + err = sci_send_sync_data(hdl, p_src, p_dst, length, true); + + return err; +} /* End of function R_SCI_SendReceive() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_transfer +* Description : Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_transfer(sci_hdl_t const hdl) +{ + uint16_t num; + uint8_t byte; + + /* Get bytes from tx queue */ + (void)R_BYTEQ_Get(hdl->u_tx_data.que, (uint8_t *)&byte); + + /* TDR/FTDR register write access */ + SCI_TDR(byte); + + /* Get data byte number from que and if the number of data bytes is 0, to disable the transfer */ + R_BYTEQ_Used(hdl->u_tx_data.que, &num); + if (0 >= num) + { + /* Disable transmit interrupt */ + DISABLE_TXI_INT; +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + hdl->tx_idle = true; // set flag if queue empty + } +} /* End of function sci_transfer() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_transfer +* Description : FIFO Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_transfer(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num; + + /* Repeated empty FIFO buffer count */ + fifo_num = SCI_FIFO_FRAME_SIZE - hdl->rom->regs->FDR.BIT.T; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* SCI Transfer */ + sci_transfer(hdl); + + /* If the queue is empty(true == hdl->tx_idle), exit from FIFO transfer loop */ + if (true == hdl->tx_idle) + { + break; + } + } + + /* When the settings of transmit data are completed, set the SSRFIFO.TDFE flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + /* Casting register 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } +} /* End of function sci_fifo_transfer() */ +#endif /*End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: txi_handler +* Description : TXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void txi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Transfer */ + sci_fifo_transfer(hdl); + } + else +#endif + { + /* SCI Transfer */ + sci_transfer(hdl); + } +} /* End of function txi_handler() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* Function Name: tei_handler +* Description : TEI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void tei_handler(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + + /* Disable transmit end interrupt */ + DISABLE_TEI_INT; + hdl->rom->regs->SCR.BIT.TEIE = 0; + + /* Activate callback function if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_TEI; + + /* Activate callback function */ + hdl->callback((void *)&args); + } +} /* End of function tei_handler() */ +#endif + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Receive +********************************************************************************************************************//** +* @brief In Asynchronous mode, fetches data from a queue which is filled by RXI interrupts. In other modes, initiates +* reception if transceiver is not in use. +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to read +* +* @retval SCI_SUCCESS Requested number of bytes were loaded into p_dst (Asynchronous) Clocking in of data initiated +* (SSPI/Synchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_DATA Insufficient data in receive queue to fetch all data (Asynchronous) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous) +* +* @details In Asynchronous mode, this function gets data received on an SCI channel referenced by the handle from its +* receive queue. This function will not block if the requested number of bytes is not available. In +* SSPI/Synchronous modes, the clocking in of data begins immediately if the transceiver is not already in use. +* The value assigned to SCI_CFG_DUMMY_TX_BYTE in r_sci_config.h is clocked out while the receive data is being clocked in.\n +* If any errors occurred during reception, the callback function specified in R_SCI_Open() is executed. Check +* an event passed with the argument of the callback function to see if the reception has been successfully +* completed. See Section 2.11 Callback Function in application note for details.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave +* Select line for the target device must be enabled prior to calling this function. +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +* In Asynchronous mode, when data match detected, received data stored in a queue and notify to user by callback function +* with event SCI_EVT_RX_CHAR_MATCH. +*/ +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +sci_err_t err = SCI_SUCCESS; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_dst */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl))|| ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_receive_async_data(hdl, p_dst, length); +#endif + } + + else + { + /* mode is SSPI/SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_receive_sync_data(hdl, p_dst, length); +#endif + } + + return err; +} /* End of function R_SCI_Receive() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_async_data +* Description : This function determines if the rx byte queue of the channel +* referenced by the handle, the requested number of bytes +* is available, and get the data from the rx byte queue. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_INSUFFICIENT_DATA - +* rx queue does not contain requested amount of data +******************************************************************************/ +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_SUCCESS; + + /* CHECK FOR SUFFICIENT DATA IN QUEUE, AND FETCH IF AVAILABLE */ + R_BYTEQ_Used(hdl->u_rx_data.que, &cnt); + + if (cnt < length) + { + return SCI_ERR_INSUFFICIENT_DATA; + } + + /* Get bytes from rx queue */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { + /* Disable RXI Interrupt */ + DISABLE_RXI_INT; + byteq_err = R_BYTEQ_Get(hdl->u_rx_data.que, p_dst++); + ENABLE_RXI_INT; + if (BYTEQ_SUCCESS != byteq_err) + { + err = SCI_ERR_INSUFFICIENT_DATA; + break; + } + } + + return err; +} /* End of function sci_receive_async_data() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and dummy data send. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + /* IF TRANCEIVER NOT IN USE, START DUMMY TRANSMIT TO CLOCK IN DATA */ + if (true == hdl->tx_idle) + { + hdl->u_rx_data.buf = p_dst; + hdl->save_rx_data = true; /* save the data clocked in */ + hdl->tx_idle = false; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_dummy = true; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + if (length > SCI_FIFO_FRAME_SIZE) + { + thresh_cnt = SCI_FIFO_FRAME_SIZE; + } + else + { + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + thresh_cnt = length; + } + + hdl->tx_cnt -= thresh_cnt; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transmit */ + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transfer */ + } + + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_receive_sync_data() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +* Function Name: sci_receive +* Description : Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + /* Read byte */ + SCI_RDR(byte); + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + hdl->rx_cnt--; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + *hdl->u_rx_data.buf++ = byte; + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (0 < hdl->tx_cnt) + { + /* send another byte */ + if (true == hdl->tx_dummy) + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + else + { + hdl->tx_cnt--; + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + else + { + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } + } +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + } +} /* End of function sci_receive() */ + +#if SCI_CFG_FIFO_INCLUDED +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_fifo_receive_sync +* Description : FIFO Receive for SCI mode is SYNC and SSPI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive_sync(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num_rx; + uint8_t fifo_num_tx; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; + + fifo_num_rx = hdl->rom->regs->FDR.BIT.R; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + SCI_RDR(byte_rx[cnt]); + } + + hdl->rx_cnt -= fifo_num_rx; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + /* SCI Receive */ + *hdl->u_rx_data.buf++ = byte_rx[cnt]; + } + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (hdl->rom->regs->FCR.BIT.RTRG > hdl->rx_cnt) + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_cnt; + } + + if (0 < hdl->tx_cnt) + { + if (hdl->tx_cnt > fifo_num_rx) + { + fifo_num_tx = fifo_num_rx; + hdl->tx_cnt -= fifo_num_rx; + } + else + { + fifo_num_tx = hdl->tx_cnt; + hdl->tx_cnt = 0; + } + + /* send another byte */ + if (true == hdl->tx_dummy) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + } + else + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + } + else + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_curr_thresh; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + } +} /* End of function sci_fifo_receive_sync() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_receive +* Description : FIFO Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive(sci_hdl_t const hdl) +{ +#if (SCI_CFG_ASYNC_INCLUDED) + uint16_t cnt; + uint16_t fifo_num; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting unsigned char type to uint16_t type is valid */ + fifo_num = (uint16_t)hdl->rom->regs->FDR.BIT.R; + + /* RX FIFO flush */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* Read byte */ + SCI_RDR(byte_rx[cnt]); + } + + /* Determine amount of space left in rx queue */ + (void)R_BYTEQ_Unused(hdl->u_rx_data.que, &cnt); + if (cnt >= fifo_num) + { + /* free space is enough */ + args.event = SCI_EVT_RX_CHAR; + } + else + { + /* insufficient free space, store as much as possible */ + fifo_num = cnt; + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* store bytes to rx queue for R_SCI_Receive */ + (void)R_BYTEQ_Put(hdl->u_rx_data.que, byte_rx[cnt]); + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + + /* Number of bytes were stored to queue */ + args.num = (uint8_t)fifo_num; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED*/ + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* SCI Receive */ + sci_fifo_receive_sync(hdl); +#endif + } + + /* When the readings of receive data are completed, set the SSRFIFO.RDF flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.RDF) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_RDF_MASK; + } + + if (SCI_MODE_ASYNC == hdl->mode) + { + if (1 == hdl->rom->regs->SSRFIFO.BIT.DR) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_DR_MASK; + } + } +} /* End of function sci_fifo_receive() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED +/***************************************************************************** +* Function Name: sci_receive_data_match +* Description : SCI receive data match +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive_data_match(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (0 == hdl->rom->regs->DCCR.BIT.DCME) /* DCME automatically set 0 when data matched */ + { + hdl->rom->regs->DCCR.BIT.DCMF = 0; /* Clear Data Match Flag */ + + if ((0 == hdl->rom->regs->DCCR.BIT.DFER ) && (0 == hdl->rom->regs->DCCR.BIT.DPER )) /* Check framing error and parity error */ + { + /* Casting unsigned char type to unin8_t type is valid */ + byte = (uint8_t)(hdl->rom->regs->CDR.BYTE.L); /* Read data from comparison data register */ + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR_MATCH; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + } +} /* End of function sci_receive_data_match() */ +#endif /* End of SCI_CFG_DATA_MATCH_INCLUDED */ + +/***************************************************************************** +* Function Name: rxi_handler +* Description : RXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void rxi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_DATA_MATCH_INCLUDED + if (1 == hdl->rom->regs->DCCR.BIT.DCMF) /* Check Data match flag */ + { + sci_receive_data_match(hdl); + } + else +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Receive */ + sci_fifo_receive(hdl); + } + else +#endif + { + /* SCI Receive */ + sci_receive(hdl); + } +} /* End of function rxi_handler() */ + + +/***************************************************************************** +* Function Name: sci_error +* Description : Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + uint8_t reg; + + reg = SCI_SSR; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Flush register */ + SCI_RDR(byte); + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + SCI_RDR(byte); + + reg = SCI_SSR; + reg &= (~SCI_RCVR_ERR_MASK); + reg |= SCI_SSR_CLR_MASK; + SCI_SSR = reg; + + if (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + +} /* End of function sci_error() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_error +* Description : FIFO Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t reg; + volatile uint8_t ssrfifo_data; + volatile uint16_t dummy; + + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = 0; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + + /* if error condition don't clear in callback when it clear at here */ + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + /* Flush register */ + /* WAIT_LOOP */ + while (0 != hdl->rom->regs->FDR.BIT.R) + { + dummy = hdl->rom->regs->FRDR.WORD; /* FRDR dummy read */ + } + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) /* Check PER, FER, ORER flags */ + { + ssrfifo_data = SCI_SSRFIFO; /* SSRFIFO dummy read */ + SCI_SSRFIFO = (uint8_t)~SCI_RCVR_ERR_MASK; /* PER, FER, ORER clear */ + if (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + } + } + + return; +} /* End of function sci_fifo_error() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: eri_handler +* Description : ERI interrupt handler for SCI UART mode +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void eri_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Error */ + sci_fifo_error(hdl); + } + else +#endif + { + /* SCI error */ + sci_error(hdl); + } +} /* End of function eri_handler() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Control +********************************************************************************************************************//** +* @brief This function configures and controls the operating mode for the SCI channel. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] cmd Command to run (see Section 3. R_SCI_Control() in application note for details) +* +* @param[in] p_args Pointer to arguments (see Section 3. R_SCI_Control() in application note for details) specific to +* command, casted to void * +* +* @retval SCI_SUCCESS Successful; channel initialized. +* +* @retval SCI_ERR_NULL_PTR hdl or p_args pointer is NULL (when required) +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INVALID_ARG +* The cmd value or an element of p_args contains an invalid value. +* @details This function is used for configuring special hardware features such as changing driver configuration and +* obtaining driver status. +* The CTS/ RTS pin functions as RTS by default hardware control. By issuing an SCI_CMD_EN_CTS_IN, the pin functions as CTS. +* @note When SCI_CMD_CHANGE_BAUD is used, the optimum values for BRR, SEMR.ABCS, and SMR.CKS is calculated based on +* the bit rate specified. This however does not guarantee a low bit error rate for all peripheral clock/baud rate +* combinations.\n +* If the command SCI_CMD_EN_CTS_IN is to be used, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Control() for details. +*/ +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err = SCI_SUCCESS; + sci_baud_t *baud; + int32_t bit_err; + + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } + + /* Check argument p_args*/ + if ((NULL == p_args) || (FIT_NO_PTR == p_args)) + { + if (SCI_CMD_CHANGE_BAUD == cmd) + { + return SCI_ERR_NULL_PTR; + } +#if SCI_CFG_FIFO_INCLUDED + if ((SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) || (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } +#if SCI_CFG_FIFO_INCLUDED + if (SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if (15 < (*(uint8_t *)p_args)) + { + return SCI_ERR_INVALID_ARG; + } + } + if (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (15 < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd)) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (BSP_MCU_IPL_MAX < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + /* COMMANDS COMMON TO ALL MODES */ + + switch (cmd) + { + case (SCI_CMD_CHANGE_BAUD): + { + /* Casting void* type is valid */ + baud = (sci_baud_t *)p_args; +#if (SCI_CFG_ASYNC_INCLUDED) + hdl->pclk_speed = baud->pclk; // save for break generation +#endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, baud->pclk, baud->rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = baud->rate; // save for break generation + } + break; + } + + case (SCI_CMD_EN_CTS_IN): + { + if (SCI_MODE_SSPI != hdl->mode) + { + /* PFS & port pins must be configured for CTS prior to calling this */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BIT.CTSE = 1; // enable CTS input + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + /* Can not use CTS in smart card interface mode, simple SPI mode, and simple I2C mode */ + err = SCI_ERR_INVALID_ARG; + } + break; + } + +#if SCI_CFG_FIFO_INCLUDED + case (SCI_CMD_CHANGE_TX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + /* save current TX FIFO threshold */ + hdl->tx_curr_thresh = *((uint8_t *)p_args); + + /* change TX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.TTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } + + case (SCI_CMD_CHANGE_RX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + /* save current RX FIFO threshold */ + hdl->rx_curr_thresh = *((uint8_t *)p_args); + + /* change RX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.RTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + case (SCI_CMD_SET_TXI_PRIORITY): + { + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_txi = *((uint8_t *)p_args); + break; + } + + case (SCI_CMD_SET_RXI_PRIORITY): + { + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_rxi = *((uint8_t *)p_args); + break; + } +#endif + + default: + { + /* ASYNC-SPECIFIC COMMANDS */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_async_cmds(hdl, cmd, p_args); +#endif + } + + /* SSPI/SYNC-SPECIFIC COMMANDS */ + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_sync_cmds(hdl, cmd, p_args); +#endif + } + break; + } + } + + return err; +} /* End of function R_SCI_Control() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Close +********************************************************************************************************************//** +* @brief This function removes power from the SCI channel and disables the associated interrupts. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @retval SCI_SUCCESS Successful; channel closed +* +* @retval SCI_ERR_NULL_PTR hdl is NULL +* +* @details Disables the SCI channel designated by the handle and enters module-stop state. +* @note This function will abort any transmission or reception that may be in progress. +*/ +sci_err_t R_SCI_Close(sci_hdl_t const hdl) +{ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* disable ICU interrupts */ + sci_disable_ints(hdl); + + /* free tx and rx queues */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + R_BYTEQ_Close(hdl->u_tx_data.que); + R_BYTEQ_Close(hdl->u_rx_data.que); + } +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset FIFO threshold */ + hdl->rx_curr_thresh = hdl->rx_dflt_thresh; + hdl->tx_curr_thresh = hdl->tx_dflt_thresh; + } +#endif + + /* mark the channel as not in use and power down */ + hdl->mode = SCI_MODE_OFF; + power_off(hdl); + + return SCI_SUCCESS; +} /* End of function R_SCI_Close() */ + + +/*********************************************************************************************************************** +* Function Name: R_SCI_GetVersion +********************************************************************************************************************//** +* @brief This function returns the driver version number at runtime. +* @return Version number. +* @details Returns the version of this module. The version number is encoded such that the top 2 bytes are the major +* version number and the bottom 2 bytes are the minor version number. +* @note None +*/ +uint32_t R_SCI_GetVersion(void) +{ + uint32_t const version = (SCI_VERSION_MAJOR << 16) | SCI_VERSION_MINOR; + + return version; +} /* End of function R_SCI_GetVersion() */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h new file mode 100644 index 000000000..892f8820c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_platform.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 Added RX24U support +* 28.09.2018 2.10 Added RX66T support +* 01.02.2019 2.20 Added RX72T, RX65N-64pin support +* 28.06.2019 3.10 Added RX23W support +* 15.08.2019 3.20 Added RX72M support +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +************************************************************************************************************************/ + +#ifndef SCI_RX_PLATFORM_H +#define SCI_RX_PLATFORM_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sci_rx_if.h" + +#if defined(BSP_MCU_RX110) +#include "./targets/rx110/r_sci_rx110_private.h" /* RX110 */ +#elif defined(BSP_MCU_RX111) +#include "./targets/rx111/r_sci_rx111_private.h" /* RX111 */ +#elif defined(BSP_MCU_RX113) +#include "./targets/rx113/r_sci_rx113_private.h" /* RX113 */ +#elif defined(BSP_MCU_RX130) +#include "./targets/rx130/r_sci_rx130_private.h" /* RX130 */ +#elif defined(BSP_MCU_RX13T) +#include "./targets/rx13t/r_sci_rx13t_private.h" /* RX13T */ +#elif defined(BSP_MCU_RX230) +#include "./targets/rx230/r_sci_rx230_private.h" /* RX230 */ +#elif defined(BSP_MCU_RX231) +#include "./targets/rx231/r_sci_rx231_private.h" /* RX231 */ +#elif defined(BSP_MCU_RX23E_A) +#include "./targets/rx23e-a/r_sci_rx23e-a_private.h" /* RX23E-A */ +#elif defined(BSP_MCU_RX23T) +#include "./targets/rx23t/r_sci_rx23t_private.h" /* RX23T */ +#elif defined(BSP_MCU_RX23W) +#include "./targets/rx23w/r_sci_rx23w_private.h" /* RX23W */ +#elif defined(BSP_MCU_RX24T) +#include "./targets/rx24t/r_sci_rx24t_private.h" /* RX24T */ +#elif defined(BSP_MCU_RX24U) +#include "./targets/rx24u/r_sci_rx24u_private.h" /* RX24U */ +#elif defined(BSP_MCU_RX64M) +#include "./targets/rx64m/r_sci_rx64m_private.h" /* RX64M */ +#elif defined(BSP_MCU_RX65N) +#include "./targets/rx65n/r_sci_rx65n_private.h" /* RX65N */ +#elif defined(BSP_MCU_RX66T) +#include "./targets/rx66t/r_sci_rx66t_private.h" /* RX66T */ +#elif defined(BSP_MCU_RX66N) +#include "./targets/rx66n/r_sci_rx66n_private.h" /* RX66N */ +#elif defined(BSP_MCU_RX71M) +#include "./targets/rx71m/r_sci_rx71m_private.h" /* RX71M */ +#elif defined(BSP_MCU_RX72T) +#include "./targets/rx72t/r_sci_rx72t_private.h" /* RX72T */ +#elif defined(BSP_MCU_RX72M) +#include "./targets/rx72m/r_sci_rx72m_private.h" /* RX72M */ +#elif defined(BSP_MCU_RX72N) +#include "./targets/rx72n/r_sci_rx72n_private.h" /* RX72N */ +#else +#error "ERROR - r_sci_rxXXX_private.h not included." +#endif + +#endif /* SCI_RX_PLATFORM_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h new file mode 100644 index 000000000..72ed5f11f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h @@ -0,0 +1,184 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_private.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 28.09.2018 2.10 Added SCI_CFG_DATA_MATCH_INCLUDED for configuration data match function. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support received data match function for RX65N (SCI10 and SCI11). +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0 to SCI11). +* Added support FIFO mode for RX72M (SCI7 to SCI11). +***********************************************************************************************************************/ + +#ifndef SCI_RX_H +#define SCI_RX_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../r_sci_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Bit position masks */ +#define BIT0_MASK (0x00000001U) +#define BIT1_MASK (0x00000002U) +#define BIT2_MASK (0x00000004U) +#define BIT3_MASK (0x00000008U) +#define BIT4_MASK (0x00000010U) +#define BIT5_MASK (0x00000020U) +#define BIT6_MASK (0x00000040U) +#define BIT7_MASK (0x00000080U) +#define BIT8_MASK (0x00000100U) +#define BIT9_MASK (0x00000200U) +#define BIT10_MASK (0x00000400U) +#define BIT11_MASK (0x00000800U) +#define BIT12_MASK (0x00001000U) +#define BIT13_MASK (0x00002000U) +#define BIT14_MASK (0x00004000U) +#define BIT15_MASK (0x00008000U) +#define BIT16_MASK (0x00010000U) +#define BIT17_MASK (0x00020000U) +#define BIT18_MASK (0x00040000U) +#define BIT19_MASK (0x00080000U) +#define BIT20_MASK (0x00100000U) +#define BIT21_MASK (0x00200000U) +#define BIT22_MASK (0x00400000U) +#define BIT23_MASK (0x00800000U) +#define BIT24_MASK (0x01000000U) +#define BIT25_MASK (0x02000000U) +#define BIT26_MASK (0x04000000U) +#define BIT27_MASK (0x08000000U) +#define BIT28_MASK (0x10000000U) +#define BIT29_MASK (0x20000000U) +#define BIT30_MASK (0x40000000U) +#define BIT31_MASK (0x80000000U) + +#ifndef NULL /* Resolves e2studio code analyzer false error message. */ + #define NULL (0) +#endif + +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || \ + (SCI_CFG_CH8_FIFO_INCLUDED) || \ + (SCI_CFG_CH9_FIFO_INCLUDED) || \ + (SCI_CFG_CH10_FIFO_INCLUDED) || \ + (SCI_CFG_CH11_FIFO_INCLUDED)) + #define SCI_CFG_FIFO_INCLUDED (1) +#endif + +#if ((SCI_CFG_CH0_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH1_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH2_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH3_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH4_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH5_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH6_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH7_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH8_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH9_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH10_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH11_DATA_MATCH_INCLUDED)) + #define SCI_CFG_DATA_MATCH_INCLUDED (1) +#endif + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_ORER (hdl->rom->regs->SSRFIFO.BIT.ORER) +#define SCI_SSRFIFO_PER (hdl->rom->regs->SSRFIFO.BIT.PER) +#define SCI_SSRFIFO_FER (hdl->rom->regs->SSRFIFO.BIT.FER) +#define SCI_SSRFIFO_RDF (hdl->rom->regs->SSRFIFO.BIT.RDF) +#define SCI_SSRFIFO (hdl->rom->regs->SSRFIFO.BYTE) +#endif +#define SCI_SSR_ORER (hdl->rom->regs->SSR.BIT.ORER) +#define SCI_SSR_PER (hdl->rom->regs->SSR.BIT.PER) +#define SCI_SSR_FER (hdl->rom->regs->SSR.BIT.FER) +#define SCI_SSR (hdl->rom->regs->SSR.BYTE) + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_FIFO_FRAME_SIZE (16) +#endif + +/* SCR register dummy read */ +#define SCI_SCR_DUMMY_READ \ + if (0x00 == hdl->rom->regs->SCR.BYTE) \ + { \ + R_BSP_NOP(); \ + } + +/* Interrupt Request register flag clear */ +#define SCI_IR_TXI_CLEAR (*hdl->rom->ir_txi = 0) + +/* TDR/FTDR register write access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_TDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + hdl->rom->regs->FTDR.BYTE.L = (byte); \ + } \ + else \ + { \ + hdl->rom->regs->TDR = (byte); \ + } +#else +#define SCI_TDR(byte) \ + hdl->rom->regs->TDR = (byte); +#endif + +/* RDR/FRDR register read access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_RDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + (byte) = hdl->rom->regs->FRDR.BYTE.L; \ + } \ + else \ + { \ + (byte) = hdl->rom->regs->RDR; \ + } +#else +#define SCI_RDR(byte) \ + (byte) = hdl->rom->regs->RDR; +#endif + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +extern void txi_handler(sci_hdl_t const hdl); +#endif + +#if SCI_CFG_TEI_INCLUDED +extern void tei_handler(sci_hdl_t const hdl); +#endif + +extern void rxi_handler(sci_hdl_t const hdl); + +extern void eri_handler(sci_hdl_t const hdl); + +#endif /* SCI_RX_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c new file mode 100644 index 000000000..10c9f9974 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c @@ -0,0 +1,1448 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx72n.c +* Description : Functions for using SCI on the RX72N device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx72n_private.h" + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/***************************************************************************** +* Function Name: sci_mcu_param_check +* Description : This function parameters check on MCU. +* (channel range, interrupt priority, etc...) +* Arguments : chan - +* channel to check +* Return Value : SCI_SUCCESS - +* parameter check all successfully +* SCI_ERR_BAD_CHAN - +* channel number invalid for part +* SCI_ERR_INVALID_ARG - +* interrupt priority out of range +******************************************************************************/ +sci_err_t sci_mcu_param_check(uint8_t const chan) +{ + /* channel range parameter check */ + if (SCI_NUM_CH <= chan) + { + return SCI_ERR_BAD_CHAN; + } + + /* interrupt priority configuration parameter check */ + if ((1 > SCI_CFG_ERI_TEI_PRIORITY) || (15 < SCI_CFG_ERI_TEI_PRIORITY)) + { + return SCI_ERR_INVALID_ARG; + } + + return SCI_SUCCESS; +} /* End of function sci_mcu_param_check() */ + +/***************************************************************************** +* Function Name: sci_init_register +* Description : This function initializes the register for SCI. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_init_register(sci_hdl_t const hdl) +{ + /* SCI transmit enable bit and receive enable bit check & disable */ + /* WAIT_LOOP */ + while ((0 != hdl->rom->regs->SCR.BIT.TE) || (0 != hdl->rom->regs->SCR.BIT.RE)) + { + if (0 != hdl->rom->regs->SCR.BIT.TE) + { + hdl->rom->regs->SCR.BIT.TE = 0; // transmit disable + } + + if (0 != hdl->rom->regs->SCR.BIT.RE) + { + hdl->rom->regs->SCR.BIT.RE = 0; // receive disable + } + } + + /* SMR register initialize */ + hdl->rom->regs->SMR.BYTE = 0x00; + + /* SCR register initialize */ + hdl->rom->regs->SCR.BYTE = 0x00; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SSRFIFO register initialize */ + if (1 == SCI_SSRFIFO_ORER) + { + SCI_SSRFIFO_ORER = 0; + } + + if (1 == SCI_SSRFIFO_PER) + { + SCI_SSRFIFO_PER = 0; + } + + if (1 == SCI_SSRFIFO_FER) + { + SCI_SSRFIFO_FER = 0; + } + + if (1 == SCI_SSRFIFO_RDF) + { + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + SCI_SSRFIFO_RDF = 0; + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { + /* SSR register initialize */ + if (1 == SCI_SSR_ORER) + { + SCI_SSR_ORER = 0; + } + + if (1 == SCI_SSR_PER) + { + SCI_SSR_PER = 0; + } + + if (1 == SCI_SSR_FER) + { + SCI_SSR_FER = 0; + } + } + + /* SCMR register initialize */ + hdl->rom->regs->SCMR.BIT.SMIF = 0; + hdl->rom->regs->SCMR.BIT.SINV = 0; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + + /* BRR register initialize */ + hdl->rom->regs->BRR = 0xFF; + + /* SEMR register initialize */ + hdl->rom->regs->SEMR.BIT.BRME = 0; + hdl->rom->regs->SEMR.BIT.ABCS = 0; + hdl->rom->regs->SEMR.BIT.NFEN = 0; + hdl->rom->regs->SEMR.BIT.BGDM = 0; + hdl->rom->regs->SEMR.BIT.RXDESEL = 0; + + /* SNFR register initialize */ + hdl->rom->regs->SNFR.BYTE = 0; + + /* SPMR register initialize */ + hdl->rom->regs->SPMR.BIT.CTSE = 0; + hdl->rom->regs->SPMR.BIT.CKPOL = 0; + hdl->rom->regs->SPMR.BIT.CKPH = 0; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* FCR register initialize */ + hdl->rom->regs->FCR.BIT.FM = 0; + hdl->rom->regs->FCR.BIT.TFRST = 0; + hdl->rom->regs->FCR.BIT.RFRST = 0; + hdl->rom->regs->FCR.BIT.TTRG = 0; + hdl->rom->regs->FCR.BIT.RTRG = 8; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED + /* DCCR register initialize */ + hdl->rom->regs->DCCR.BIT.DCME = 0; + hdl->rom->regs->DCCR.BIT.DCMF = 0; + hdl->rom->regs->DCCR.BIT.DFER = 0; + hdl->rom->regs->DCCR.BIT.DPER = 0; + hdl->rom->regs->DCCR.BIT.IDSEL = 0; + + /* CDR register initialize */ + hdl->rom->regs->CDR.BYTE.L = 0; + + /* Set initial value of receive in 8-bit data length */ + hdl->rom->regs->SMR.BIT.CHR = 0; + hdl->rom->regs->SCMR.BIT.CHR1 = 1; +#endif + + return; +} /* End of function sci_init_register() */ + +/***************************************************************************** +* Function Name: sci_init_bit_rate +* Description : This function determines the best possible settings for the +* baud rate registers for the specified peripheral clock speed +* and baud rate. Note that this does not guarantee a low bit +* error rate, just the best possible one. The bit rate error is +* returned in .1% increments. If the hardware cannot support +* the specified combination, a value of 1000 (100% error) is +* returned. +* +* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled +* prior to calling this function. +* +* The application must pause for 1 bit time after the BRR register +* is loaded before transmitting/receiving to allow time for the clock +* to settle. +* +* Arguments : hdl - +* Handle for channel (ptr to chan control block) +* NOTE: mode element must be already set +* pclk - +* Peripheral clock speed; e.g. 24000000 for 24MHz +* baud - +* Baud rate; 19200, 57600, 115200, etc. +* Return Value : bit error in .1% increments; e.g. 16 = 1.6% bit rate error +* a value of 1000 denotes 100% error; no registers set +******************************************************************************/ +int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud) +{ + uint32_t i; + uint32_t num_divisors = 0; + uint32_t ratio; + uint32_t tmp; + baud_divisor_t const *p_baud_info = NULL; + + uint32_t divisor; + uint32_t int_M; + float float_M; + float error; + float abs_error; + +#if SCI_CFG_FIFO_INCLUDED + uint8_t brr; +#endif + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((0 == pclk) || (0 == baud)) + { + return 1000; + } +#endif + + /* SELECT PROPER TABLE BASED UPON MODE */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + p_baud_info = async_baud; + num_divisors = NUM_DIVISORS_ASYNC; +#endif + } + else + { + /* SYNC or SSPI */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + p_baud_info = sync_baud; + num_divisors = NUM_DIVISORS_SYNC; +#endif + } + + /* FIND DIVISOR; table has associated ABCS, BGDM and CKS values */ + /* BRR must be 255 or less */ + /* the "- 1" is ignored in some steps for approximations */ + /* BRR = (PCLK/(divisor * baud)) - 1 */ + /* BRR = (ratio / divisor) - 1 */ + ratio = pclk/baud; + + /* WAIT_LOOP */ + for(i = 0; i < num_divisors; i++) + { + /* Casting int16_t to uint32_t is valid. Because clock divisor is positive integer */ + if (ratio < (uint32_t)(p_baud_info[i].divisor * 256)) + { + break; + } + } + + /* RETURN IF BRR WILL BE >255 OR LESS THAN 0 */ + if (i == num_divisors) + { + return(1000); // impossible baud rate requested; return 100% error + } + + /* Casting int16_t to uint32_t is valid. Because clock divisor is a positive integer */ + divisor = (uint32_t)p_baud_info[i].divisor; + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + if(0 == tmp) + { + return(1000); // illegal value; return 100% error + } + + /* SET BRR, ABCS, BDGM, and CKS */ + tmp = ratio / (divisor/2); // divide by half the divisor + +#if SCI_CFG_FIFO_INCLUDED + /* Casting is valid. Because result of calculation is in range uint8_t type */ + brr = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + if (0 == brr) + { + if (true == hdl->fifo_ctrl) + { + if (1 == hdl->rom->regs->SMR.BIT.CM) + { + if (0 == hdl->rom->regs->SMR.BIT.CKS) + { + return(1000); + } + } + } + } +#endif + + /* if odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */ + hdl->rom->regs->BRR = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + hdl->rom->regs->SEMR.BIT.ABCS = p_baud_info[i].abcs; + hdl->rom->regs->SEMR.BIT.BGDM = p_baud_info[i].bgdm; + hdl->rom->regs->SMR.BIT.CKS = p_baud_info[i].cks; + + /* CALCULATE BIT RATE ERROR. + * RETURN IF ERROR LESS THAN 1% OR IF IN SYNCHRONOUS/SSPI MODE. + */ + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + + /* Casting uint32_t to float is valid */ + error = ( ((float)pclk / ((baud * divisor) * tmp)) - 1) * 100; + abs_error = (error < 0) ? (-error) : error; + + if ((abs_error <= 1.0) || (SCI_MODE_ASYNC != hdl->mode)) + { + hdl->rom->regs->SEMR.BIT.BRME = 0; // disable MDDR + + /* Casting float to uint32_t */ + return (uint32_t)(error*10); + } + + /* CALCULATE M ASSUMING A 0% ERROR then WRITE REGISTER */ + hdl->rom->regs->BRR = (uint8_t)(tmp-1); + + /* Casting uint32_t to float is valid */ + float_M = ((float)((baud * divisor) * 256) * tmp) / pclk; + float_M *= 2; + + /* Casting float to uint32_t */ + int_M = (uint32_t)float_M; + int_M = (int_M & 0x01) ? ((int_M/2) + 1) : (int_M/2); + + /* Casting uint32_t type to uint8_t type in this case is valid. Range value of m is not exceed uint8_t */ + hdl->rom->regs->MDDR = (uint8_t)int_M; // write M + hdl->rom->regs->SEMR.BIT.BRME = 1; // enable MDDR + + /* Casting uint32_t to float is valid*/ + error = (( (float)(pclk) / (((divisor * tmp) * baud) * ((float)(256)/int_M)) ) - 1) * 100; + + /* Casting float to int32_t */ + return (int32_t)(error*10); +} /* End of function sci_init_bit_rate() */ + +/***************************************************************************** +* Function Name: sci_initialize_ints +* Description : This function sets priority, clears flags, and sets +* interrupts in both the ICU and SCI peripheral. These include +* RXI, TXI, TEI, and ERI/GROUP12 interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* priority - +* priority for interrupts +* Return Value : none +******************************************************************************/ +void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority) +{ + volatile bsp_int_ctrl_t group_priority; + + /* SET PRIORITY FOR INTERRUPTS */ + *hdl->rom->ipr_rxi = priority; // can set separately using Control() + *hdl->rom->ipr_txi = priority; + + group_priority.ipl = 0x00000000; +#if ((SCI_CFG_CH0_INCLUDED == 1) || (SCI_CFG_CH1_INCLUDED == 1) || (SCI_CFG_CH2_INCLUDED == 1) || \ + (SCI_CFG_CH3_INCLUDED == 1) || (SCI_CFG_CH4_INCLUDED == 1) || (SCI_CFG_CH5_INCLUDED == 1) || \ + (SCI_CFG_CH6_INCLUDED == 1) || (SCI_CFG_CH12_INCLUDED == 1)) + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPBL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } +#endif + + +#if ((SCI_CFG_CH7_INCLUDED == 1) || (SCI_CFG_CH8_INCLUDED == 1) || (SCI_CFG_CH9_INCLUDED == 1) || \ + (SCI_CFG_CH10_INCLUDED == 1) || (SCI_CFG_CH11_INCLUDED == 1)) + + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPAL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } +#endif + + /* DISABLE ERI INTERRUPT */ + DISABLE_ERI_INT; + + /* DISABLE RXI INTERRUPT */ + DISABLE_RXI_INT; + + /* DISABLE TXI INTERRUPT */ + DISABLE_TXI_INT; + + /* DISABLE TEI INTERRUPT */ + DISABLE_TEI_INT; + + /* CLEAR INTERRUPT FLAGS */ + *hdl->rom->ir_rxi = 0; + *hdl->rom->ir_txi = 0; + (*hdl->rom->icu_grp) &= (~hdl->rom->tei_ch_mask); + (*hdl->rom->icu_grp) &= (~hdl->rom->eri_ch_mask); + + /* REGISTER GROUP INTERRUPTS WITH BSP */ + #if SCI_CFG_TEI_INCLUDED + R_BSP_InterruptWrite(hdl->rom->tei_vector, hdl->rom->tei_isr); + #endif + R_BSP_InterruptWrite(hdl->rom->eri_vector, hdl->rom->eri_isr); + + /* ENABLE GROUP INTERRUPTS */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, (void *)&group_priority); + + /* ENABLE ERI AND RXI INTERRUPTS REQUESTS */ + ENABLE_ERI_INT; + ENABLE_RXI_INT; + + /* ENABLE INTERRUPTS IN SCI PERIPHERAL */ + /* Note: Enable interrupts after xcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; // enable TE, RE, TXI, and RXI/ERI + + return; +} /* End of function sci_initialize_ints() */ + +/***************************************************************************** +* Function Name: sci_disable_ints +* Description : This function disable interrupts in both the ICU and SCI +* peripheral. These include RXI, TXI, TEI, ERI, and group +* interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_disable_ints(sci_hdl_t const hdl) +{ + volatile bsp_int_ctrl_t group_priority; + + /* Disable ICU RXI interrupt */ + DISABLE_RXI_INT; + + /* Disable ICU TXI interrupt */ + DISABLE_TXI_INT; + + /* Disable ICU ERI interrupt */ + DISABLE_ERI_INT; + + /* Disable ICU TEI interrupt */ + DISABLE_TEI_INT; + + /* disable peripheral interrupts and xcvr (TE and RE) */ + hdl->rom->regs->SCR.BYTE = 0; + + /* disable group interrupts */ + group_priority.ipl = 0x00000000; + + /* Casting pointer to void* is valid */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, (void *)&group_priority); + + return; +} /* End of function sci_disable_ints() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_async_cmds +* Description : This function configures non-standard UART hardware and +* performs special software operations. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +******************************************************************************/ +sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + uint32_t slow_baud; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + + /* Check parameters */ + if (((NULL == p_args) || (FIT_NO_PTR == p_args)) + && ((SCI_CMD_TX_Q_BYTES_FREE == cmd) || (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ == cmd)|| (SCI_CMD_COMPARE_RECEIVED_DATA == cmd))) + { + return SCI_ERR_NULL_PTR; + } + +#endif + + switch(cmd) + { + case (SCI_CMD_EN_NOISE_CANCEL): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.NFEN = 1; /* enable noise filter */ + hdl->rom->regs->SNFR.BYTE = 0; /* clock divided by 1 (default) */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_OUTPUT_BAUD_CLK): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCR.BIT.CKE = 0x01; /* output baud clock on SCK pin */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_START_BIT_EDGE): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.RXDESEL = 1; /* detect start bit on falling edge */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + #if SCI_CFG_TEI_INCLUDED + case (SCI_CMD_EN_TEI): /* SCI_CMD_EN_TEI is obsolete command, but it exists only for compatibility with older version. */ + { + break; + } + #endif + + case (SCI_CMD_TX_Q_FLUSH): + { + /* Disable TXI interrupt */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + break; + } + + case (SCI_CMD_RX_Q_FLUSH): + { + /* Disable RXI interrupt */ + DISABLE_RXI_INT; + R_BYTEQ_Flush(hdl->u_rx_data.que); + ENABLE_RXI_INT; + break; + } + + case (SCI_CMD_TX_Q_BYTES_FREE): + { + /* Casting pointer void* to uint16_t* type is valid */ + R_BYTEQ_Unused(hdl->u_tx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ): + { + /* Casting pointer void* type to uint16_t* type is valid */ + R_BYTEQ_Used(hdl->u_rx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_GENERATE_BREAK): + { + /* flush transmit queue */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + + /* NOTE: the following steps will abort anything being sent */ + + /* set baud rate 1.5x slower */ + slow_baud = (hdl->baud_rate << 1) / 3; + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, slow_baud); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; + } + else + { + /* transmit "0" and wait for completion */ + SCI_TDR(0); + + /* WAIT_LOOP */ + while (0 == hdl->rom->regs->SSR.BIT.TEND) + { + R_BSP_NOP(); + } + + /* restore original baud rate */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + sci_init_bit_rate(hdl, hdl->pclk_speed, hdl->baud_rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + break; + } + + #if SCI_CFG_DATA_MATCH_INCLUDED + case SCI_CMD_COMPARE_RECEIVED_DATA: + { + hdl->rom->regs->DCCR.BIT.DFER = 0; /* Clear Match Data Framing Error Flag */ + hdl->rom->regs->DCCR.BIT.DPER = 0; /* Clear Match Data Parity Error Flag */ + hdl->rom->regs->DCCR.BIT.DCME = 1; /* Enable Data match function */ + hdl->rom->regs->CDR.BYTE.L = *((unsigned char *)p_args); /* Comparison data */ + break; + } + #endif + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_async_cmds() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_sync_cmds +* Description : This function performs special software operations specific +* to the SSPI and SYNC protocols. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +* May be due to mode channel is operating in. +******************************************************************************/ +sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_spi_mode_t spi_mode; + sci_cb_args_t args; + sci_err_t err = SCI_SUCCESS; + + switch (cmd) + { + case (SCI_CMD_CHECK_XFER_DONE): + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XFER_NOT_DONE; + } + break; + } + + case (SCI_CMD_XFER_LSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_XFER_MSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_INVERT_DATA): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SINV ^= 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_ABORT_XFER): + { + /* Disable receive interrupts in ICU and peripheral */ + DISABLE_RXI_INT; + DISABLE_ERI_INT; + + hdl->rom->regs->SCR.BYTE &= (~(SCI_SCR_REI_MASK | SCI_SCR_RE_MASK | SCI_SCR_TE_MASK)); + + hdl->tx_cnt = 0; + hdl->tx_dummy = false; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_ABORTED; + + /* Casting pointer to void* is valid */ + hdl->callback((void *)&args); + } + + *hdl->rom->ir_rxi = 0; /* clear rxi interrupt flag */ + (*hdl->rom->icu_grp) &= (~hdl->rom->eri_ch_mask); /* clear eri interrupt flag */ + + ENABLE_ERI_INT; /* enable rx err interrupts in ICU */ + ENABLE_RXI_INT; /* enable receive interrupts in ICU */ + + /* Enable receive interrupt in peripheral after rcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK); + hdl->rom->regs->SCR.BYTE |= SCI_SCR_REI_MASK; + break; + } + + case (SCI_CMD_CHANGE_SPI_MODE): + { + #if SCI_CFG_PARAM_CHECKING_ENABLE + + if (SCI_MODE_SSPI != hdl->mode) + { + return SCI_ERR_INVALID_ARG; + } + + /* Check parameters */ + if ((NULL == p_args ) || (FIT_NO_PTR == p_args)) + { + return SCI_ERR_NULL_PTR; + } + + /* Casting pointer void* type is valid */ + spi_mode = *((sci_spi_mode_t *)p_args); + + if ((SCI_SPI_MODE_0 != spi_mode) && (SCI_SPI_MODE_1 != spi_mode) + && (SCI_SPI_MODE_2 != spi_mode) && (SCI_SPI_MODE_3 != spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + #endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BYTE &= 0x3F; /* clear previous mode */ + hdl->rom->regs->SPMR.BYTE |= (*((uint8_t *)p_args)); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_sync_cmds() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +ISRs +******************************************************************************/ + + +#if (SCI_CFG_ASYNC_INCLUDED) + +/***************************************************************************** +* sciN_txiN_isr +* Description : TXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_txi0_isr + * Description : TXI interrupt routines for SCI0 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_txi0_isr, VECT(SCI0,TXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_txi0_isr(void) +{ + txi_handler(&ch0_ctrl); +} /* End of function sci0_txi0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED  */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_txi1_isr + * Description : TXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_txi1_isr, VECT(SCI1,TXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void) +{ + txi_handler(&ch1_ctrl); +} /* End of function sci1_txi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED  */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_txi2_isr + * Description : TXI interrupt routines for SCI2 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci2_txi2_isr, VECT(SCI2,TXI2)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci2_txi2_isr(void) +{ + txi_handler(&ch2_ctrl); +} /* End of function sci2_txi2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED  */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_txi3_isr + * Description : TXI interrupt routines for SCI3 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci3_txi3_isr, VECT(SCI3,TXI3)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci3_txi3_isr(void) +{ + txi_handler(&ch3_ctrl); +} /* End of function sci3_txi3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED  */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_txi4_isr + * Description : TXI interrupt routines for SCI4 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci4_txi4_isr, VECT(SCI4,TXI4)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci4_txi4_isr(void) +{ + txi_handler(&ch4_ctrl); +} /* End of function sci4_txi4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED  */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_txi5_isr + * Description : TXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_txi5_isr, VECT(SCI5,TXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void) +{ + txi_handler(&ch5_ctrl); +} /* End of function sci5_txi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED  */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_txi6_isr + * Description : TXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_txi6_isr, VECT(SCI6,TXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void) +{ + txi_handler(&ch6_ctrl); +} /* End of function sci6_txi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED  */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_txi7_isr + * Description : TXI interrupt routines for SCI7 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci7_txi7_isr, VECT(SCI7,TXI7)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci7_txi7_isr(void) +{ + txi_handler(&ch7_ctrl); +} /* End of function sci7_txi7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED  */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_txi8_isr + * Description : TXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_txi8_isr, VECT(SCI8,TXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void) +{ + txi_handler(&ch8_ctrl); +} /* End of function sci8_txi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED  */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_txi9_isr + * Description : TXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_txi9_isr, VECT(SCI9,TXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void) +{ + txi_handler(&ch9_ctrl); +} /* End of function sci9_txi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED  */ + +#if SCI_CFG_CH10_INCLUDED +/******************************************************************************* + * Function Name: sci10_txi10_isr + * Description : TXI interrupt routines for SCI10 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci10_txi10_isr, VECT(SCI10,TXI10)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci10_txi10_isr(void) +{ + txi_handler(&ch10_ctrl); +} /* End of function sci10_txi10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED  */ + +#if SCI_CFG_CH11_INCLUDED +/******************************************************************************* + * Function Name: sci11_txi11_isr + * Description : TXI interrupt routines for SCI11 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci11_txi11_isr, VECT(SCI11,TXI11)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci11_txi11_isr(void) +{ + txi_handler(&ch11_ctrl); +} /* End of function sci11_txi11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED  */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_txi12_isr + * Description : TXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_txi12_isr, VECT(SCI12,TXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void) +{ + txi_handler(&ch12_ctrl); +} /* End of function sci12_txi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED  */ + +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* sciN_teiN_isr +* +* Description : TEI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_tei0_isr + * Description : TEI interrupt routines for SCI0 channel. + ******************************************************************************/ +void sci0_tei0_isr(void *cb_args) +{ + tei_handler(&ch0_ctrl); +} /* End of function sci0_tei0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_tei1_isr + * Description : TEI interrupt routines for SCI1 channel. + ******************************************************************************/ +void sci1_tei1_isr(void *cb_args) +{ + tei_handler(&ch1_ctrl); +} /* End of function sci1_tei1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_tei2_isr + * Description : TEI interrupt routines for SCI2 channel. + ******************************************************************************/ +void sci2_tei2_isr(void *cb_args) +{ + tei_handler(&ch2_ctrl); +} /* End of function sci2_tei2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_tei3_isr + * Description : TEI interrupt routines for SCI3 channel. + ******************************************************************************/ +void sci3_tei3_isr(void *cb_args) +{ + tei_handler(&ch3_ctrl); +} /* End of function sci3_tei3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_tei4_isr + * Description : TEI interrupt routines for SCI4 channel. + ******************************************************************************/ +void sci4_tei4_isr(void *cb_args) +{ + tei_handler(&ch4_ctrl); +} /* End of function sci4_tei4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_tei5_isr + * Description : TEI interrupt routines for SCI5 channel. + ******************************************************************************/ +void sci5_tei5_isr(void *cb_args) +{ + tei_handler(&ch5_ctrl); +} /* End of function sci5_tei5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_tei6_isr + * Description : TEI interrupt routines for SCI6 channel. + ******************************************************************************/ +void sci6_tei6_isr(void *cb_args) +{ + tei_handler(&ch6_ctrl); +} /* End of function sci6_tei6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_tei7_isr + * Description : TEI interrupt routines for SCI7 channel. + ******************************************************************************/ +void sci7_tei7_isr(void *cb_args) +{ + tei_handler(&ch7_ctrl); +} /* End of function sci7_tei7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function Name: sci8_tei8_isr +* Description : TEI interrupt routines for SCI8 channel. +******************************************************************************/ +void sci8_tei8_isr(void *cb_args) +{ + tei_handler(&ch8_ctrl); +} /* End of function sci8_tei8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_tei9_isr +* Description : TEI interrupt routines for SCI9 channel. +******************************************************************************/ +void sci9_tei9_isr(void *cb_args) +{ + tei_handler(&ch9_ctrl); +} /* End of function sci9_tei9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/***************************************************************************** +* Function Name: sci10_tei10_isr +* Description : TEI interrupt routines for SCI10 channel. +******************************************************************************/ +void sci10_tei10_isr(void *cb_args) +{ + tei_handler(&ch10_ctrl); +} /* End of function sci10_tei10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/***************************************************************************** +* Function name: sci11_tei11_isr +* Description : TEI interrupt routines for SCI11 channel. +******************************************************************************/ +void sci11_tei11_isr(void *cb_args) +{ + tei_handler(&ch11_ctrl); +} /* End of function sci11_tei11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function Name: sci12_tei12_isr +* Description : TEI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_tei12_isr(void *cb_args) +{ + tei_handler(&ch12_ctrl); +} /* End of function sci12_tei12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +#endif /* SCI_CFG_TEI_INCLUDED */ + +/***************************************************************************** +* sciN_rxiN_isr +* Description : RXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_rxi0_isr + * Description : RXI interrupt routines for SCI0 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_rxi0_isr, VECT(SCI0,RXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_rxi0_isr(void) +{ + rxi_handler(&ch0_ctrl); +} /* End of function sci0_rxi0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_rxi1_isr + * Description : RXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_rxi1_isr, VECT(SCI1,RXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void) +{ + rxi_handler(&ch1_ctrl); +} /* End of function sci1_rxi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_rxi2_isr + * Description : RXI interrupt routines for SCI2 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci2_rxi2_isr, VECT(SCI2,RXI2)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci2_rxi2_isr(void) +{ + rxi_handler(&ch2_ctrl); +} /* End of function sci2_rxi2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_rxi3_isr + * Description : RXI interrupt routines for SCI3 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci3_rxi3_isr, VECT(SCI3,RXI3)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci3_rxi3_isr(void) +{ + rxi_handler(&ch3_ctrl); +} /* End of function sci3_rxi3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_rxi4_isr + * Description : RXI interrupt routines for SCI4 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci4_rxi4_isr, VECT(SCI4,RXI4)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci4_rxi4_isr(void) +{ + rxi_handler(&ch4_ctrl); +} /* End of function sci4_rxi4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_rxi5_isr + * Description : RXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_rxi5_isr, VECT(SCI5,RXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void) +{ + rxi_handler(&ch5_ctrl); +} /* End of function sci5_rxi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_rxi6_isr + * Description : RXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_rxi6_isr, VECT(SCI6,RXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void) +{ + rxi_handler(&ch6_ctrl); +} /* End of function sci6_rxi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_rxi7_isr + * Description : RXI interrupt routines for SCI7 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci7_rxi7_isr, VECT(SCI7,RXI7)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci7_rxi7_isr(void) +{ + rxi_handler(&ch7_ctrl); +} /* End of function sci7_rxi7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_rxi8_isr + * Description : RXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_rxi8_isr, VECT(SCI8,RXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void) +{ + rxi_handler(&ch8_ctrl); +} /* End of function sci8_rxi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_rxi9_isr + * Description : RXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_rxi9_isr, VECT(SCI9,RXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void) +{ + rxi_handler(&ch9_ctrl); +} /* End of function sci9_rxi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/******************************************************************************* + * Function Name: sci10_rxi10_isr + * Description : RXI interrupt routines for SCI10 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci10_rxi10_isr, VECT(SCI10,RXI10)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci10_rxi10_isr(void) +{ + rxi_handler(&ch10_ctrl); +} /* End of function sci10_rxi10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/******************************************************************************* + * Function Name: sci11_rxi11_isr + * Description : RXI interrupt routines for SCI11 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci11_rxi11_isr, VECT(SCI11,RXI11)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci11_rxi11_isr(void) +{ + rxi_handler(&ch11_ctrl); +} /* End of function sci11_rxi11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_rxi12_isr + * Description : RXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_rxi12_isr, VECT(SCI12,RXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void) +{ + rxi_handler(&ch12_ctrl); +} /* End of function sci12_rxi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +/***************************************************************************** +* sciN_eriN_isr +* +* Description : ERI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/***************************************************************************** +* Function name: sci0_eri0_isr +* Description : ERI interrupt routines for SCI0 channel. +******************************************************************************/ +void sci0_eri0_isr(void *cb_args) +{ + eri_handler(&ch0_ctrl); +} /* End of function sci0_eri0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/***************************************************************************** +* Function name: sci1_eri1_isr +* Description : ERI interrupt routines for SCI1 channel. +******************************************************************************/ +void sci1_eri1_isr(void *cb_args) +{ + eri_handler(&ch1_ctrl); +} /* End of function sci1_eri1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/***************************************************************************** +* Function name: sci2_eri2_isr +* Description : ERI interrupt routines for SCI2 channel. +******************************************************************************/ +void sci2_eri2_isr(void *cb_args) +{ + eri_handler(&ch2_ctrl); +} /* End of function sci2_eri2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/***************************************************************************** +* Function name: sci3_eri3_isr +* Description : ERI interrupt routines for SCI3 channel. +******************************************************************************/ +void sci3_eri3_isr(void *cb_args) +{ + eri_handler(&ch3_ctrl); +} /* End of function sci3_eri3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/***************************************************************************** +* Function name: sci4_eri4_isr +* Description : ERI interrupt routines for SCI4 channel. +******************************************************************************/ +void sci4_eri4_isr(void *cb_args) +{ + eri_handler(&ch4_ctrl); +} /* End of function sci4_eri4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/***************************************************************************** +* Function name: sci5_eri5_isr +* Description : ERI interrupt routines for SCI5 channel. +******************************************************************************/ +void sci5_eri5_isr(void *cb_args) +{ + eri_handler(&ch5_ctrl); +} /* End of function sci5_eri5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/***************************************************************************** +* Function name: sci6_eri6_isr +* Description : ERI interrupt routines for SCI6 channel. +******************************************************************************/ +void sci6_eri6_isr(void *cb_args) +{ + eri_handler(&ch6_ctrl); +} /* End of function sci6_eri6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/***************************************************************************** +* Function name: sci7_eri7_isr +* Description : ERI interrupt routines for SCI7 channel. +******************************************************************************/ +void sci7_eri7_isr(void *cb_args) +{ + eri_handler(&ch7_ctrl); +} /* End of function sci7_eri7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function name: sci8_eri8_isr +* Description : ERI interrupt routines for SCI8 channel. +******************************************************************************/ +void sci8_eri8_isr(void *cb_args) +{ + eri_handler(&ch8_ctrl); +} /* End of function sci8_eri8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_eri9_isr +* Description : ERI interrupt routines for SCI9 channel. +******************************************************************************/ +void sci9_eri9_isr(void *cb_args) +{ + eri_handler(&ch9_ctrl); +} /* End of function sci9_eri9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/***************************************************************************** +* Function name: sci10_eri10_isr +* Description : ERI interrupt routines for SCI10 channel. +******************************************************************************/ +void sci10_eri10_isr(void *cb_args) +{ + eri_handler(&ch10_ctrl); +} /* End of function sci10_eri10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/***************************************************************************** +* Function name: sci11_eri11_isr +* Description : ERI interrupt routines for SCI11 channel. +******************************************************************************/ +void sci11_eri11_isr(void *cb_args) +{ + eri_handler(&ch11_ctrl); +} /* End of function sci11_eri11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function name: sci12_eri12_isr +* Description : ERI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_eri12_isr(void *cb_args) +{ + eri_handler(&ch12_ctrl); +} /* End of function sci12_eri12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c new file mode 100644 index 000000000..734b852dd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c @@ -0,0 +1,641 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx72n_data.c +* Description : Functions for using SCI on the RX72N device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx72n_private.h" + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* BAUD DIVISOR INFO */ + +/* Asynchronous */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=0 & bgdm=0, divisor = 64*pow(2,2n-1) */ +/* when abcs=1 & bgdm=0 OR abcs=0 & bgdm=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=1 & bgdm=1, divisor = 16*pow(2,2n-1) */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/* NOTE: diff than SCI async baud table, but should provide same results */ +const baud_divisor_t async_baud[NUM_DIVISORS_ASYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {8, 1, 1, 0}, + {16, 0, 1, 0}, + {32, 0, 0, 0}, + {64, 0, 1, 1}, + {128, 0, 0, 1}, + {256, 0, 1, 2}, + {512, 0, 0, 2}, + {1024, 0, 1, 3}, + {2048, 0, 0, 3} +}; +#endif + +/* Synchronous and Simple SPI */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* abcs=0, bdgm=0, divisor = 8*pow(2,2n-1) */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/* NOTE: Identical to SCI sync baud table */ +const baud_divisor_t sync_baud[NUM_DIVISORS_SYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {4, 0, 0, 0}, + {16, 0, 0, 1}, + {64, 0, 0, 2}, + {256, 0, 0, 3} +}; +#endif + + +/* CHANNEL MEMORY ALLOCATIONS */ + +#if SCI_CFG_CH0_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch0_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI0, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT31_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI0_TEI0, sci0_tei0_isr, + #endif + BSP_INT_SRC_BL0_SCI0_ERI0, sci0_eri0_isr, + BIT0_MASK, BIT1_MASK, + &ICU.IPR[IPR_SCI0_RXI0].BYTE, + &ICU.IPR[IPR_SCI0_TXI0].BYTE, + &ICU.IR[IR_SCI0_RXI0].BYTE, + &ICU.IR[IR_SCI0_TXI0].BYTE, + &ICU.IER[IER_SCI0_RXI0].BYTE, + &ICU.IER[IER_SCI0_TXI0].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch0_ctrl = {&ch0_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH0_INCLUDED */ + + +#if SCI_CFG_CH1_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch1_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI1, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT30_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI1_TEI1, sci1_tei1_isr, + #endif + BSP_INT_SRC_BL0_SCI1_ERI1, sci1_eri1_isr, + BIT2_MASK, BIT3_MASK, + &ICU.IPR[IPR_SCI1_RXI1].BYTE, + &ICU.IPR[IPR_SCI1_TXI1].BYTE, + &ICU.IR[IR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_TXI1].BYTE, + &ICU.IER[IER_SCI1_RXI1].BYTE, + &ICU.IER[IER_SCI1_TXI1].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch1_ctrl = {&ch1_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH1_INCLUDED */ + + +#if SCI_CFG_CH2_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch2_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI2, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT29_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI2_TEI2, sci2_tei2_isr, + #endif + BSP_INT_SRC_BL0_SCI2_ERI2, sci2_eri2_isr, + BIT4_MASK, BIT5_MASK, + &ICU.IPR[IPR_SCI2_RXI2].BYTE, + &ICU.IPR[IPR_SCI2_TXI2].BYTE, + &ICU.IR[IR_SCI2_RXI2].BYTE, + &ICU.IR[IR_SCI2_TXI2].BYTE, + &ICU.IER[IER_SCI2_RXI2].BYTE, + &ICU.IER[IER_SCI2_TXI2].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch2_ctrl = {&ch2_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH2_INCLUDED */ + + +#if SCI_CFG_CH3_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch3_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI3, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT28_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI3_TEI3, sci3_tei3_isr, + #endif + BSP_INT_SRC_BL0_SCI3_ERI3, sci3_eri3_isr, + BIT6_MASK, BIT7_MASK, + &ICU.IPR[IPR_SCI3_RXI3].BYTE, + &ICU.IPR[IPR_SCI3_TXI3].BYTE, + &ICU.IR[IR_SCI3_RXI3].BYTE, + &ICU.IR[IR_SCI3_TXI3].BYTE, + &ICU.IER[IER_SCI3_RXI3].BYTE, + &ICU.IER[IER_SCI3_TXI3].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT0_MASK, BIT1_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch3_ctrl = {&ch3_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH3_INCLUDED */ + + +#if SCI_CFG_CH4_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch4_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI4, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT27_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI4_TEI4, sci4_tei4_isr, + #endif + BSP_INT_SRC_BL0_SCI4_ERI4, sci4_eri4_isr, + BIT8_MASK, BIT9_MASK, + &ICU.IPR[IPR_SCI4_RXI4].BYTE, + &ICU.IPR[IPR_SCI4_TXI4].BYTE, + &ICU.IR[IR_SCI4_RXI4].BYTE, + &ICU.IR[IR_SCI4_TXI4].BYTE, + &ICU.IER[IER_SCI4_RXI4].BYTE, + &ICU.IER[IER_SCI4_TXI4].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch4_ctrl = {&ch4_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH4_INCLUDED */ + + +#if SCI_CFG_CH5_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch5_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI5, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI5_TEI5, sci5_tei5_isr, + #endif + BSP_INT_SRC_BL0_SCI5_ERI5, sci5_eri5_isr, + BIT10_MASK, BIT11_MASK, + &ICU.IPR[IPR_SCI5_RXI5].BYTE, + &ICU.IPR[IPR_SCI5_TXI5].BYTE, + &ICU.IR[IR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_TXI5].BYTE, + &ICU.IER[IER_SCI5_RXI5].BYTE, + &ICU.IER[IER_SCI5_TXI5].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch5_ctrl = {&ch5_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH5_INCLUDED */ + + +#if SCI_CFG_CH6_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch6_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI6, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI6_TEI6, sci6_tei6_isr, + #endif + BSP_INT_SRC_BL0_SCI6_ERI6, sci6_eri6_isr, + BIT12_MASK, BIT13_MASK, + &ICU.IPR[IPR_SCI6_RXI6].BYTE, + &ICU.IPR[IPR_SCI6_TXI6].BYTE, + &ICU.IR[IR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_TXI6].BYTE, + &ICU.IER[IER_SCI6_RXI6].BYTE, + &ICU.IER[IER_SCI6_TXI6].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch6_ctrl = {&ch6_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH6_INCLUDED */ + + +#if SCI_CFG_CH7_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch7_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI7, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT24_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI7_TEI7, sci7_tei7_isr, + #endif + BSP_INT_SRC_AL0_SCI7_ERI7, sci7_eri7_isr, + BIT22_MASK, BIT23_MASK, + &ICU.IPR[IPR_SCI7_RXI7].BYTE, + &ICU.IPR[IPR_SCI7_TXI7].BYTE, + &ICU.IR[IR_SCI7_RXI7].BYTE, + &ICU.IR[IR_SCI7_TXI7].BYTE, + &ICU.IER[IER_SCI7_RXI7].BYTE, + &ICU.IER[IER_SCI7_TXI7].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch7_ctrl = {&ch7_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH7_FIFO_INCLUDED + , SCI_CFG_CH7_RX_FIFO_THRESH + , SCI_CFG_CH7_RX_FIFO_THRESH + , SCI_CFG_CH7_TX_FIFO_THRESH + , SCI_CFG_CH7_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH7_INCLUDED */ + + +#if SCI_CFG_CH8_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch8_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI8, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT27_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI8_TEI8, sci8_tei8_isr, + #endif + BSP_INT_SRC_AL0_SCI8_ERI8, sci8_eri8_isr, + BIT0_MASK, BIT1_MASK, + &ICU.IPR[IPR_SCI8_RXI8].BYTE, + &ICU.IPR[IPR_SCI8_TXI8].BYTE, + &ICU.IR[IR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_TXI8].BYTE, + &ICU.IER[IER_SCI8_RXI8].BYTE, + &ICU.IER[IER_SCI8_TXI8].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch8_ctrl = {&ch8_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH8_FIFO_INCLUDED + , SCI_CFG_CH8_RX_FIFO_THRESH + , SCI_CFG_CH8_RX_FIFO_THRESH + , SCI_CFG_CH8_TX_FIFO_THRESH + , SCI_CFG_CH8_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch9_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI9, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI9_TEI9, sci9_tei9_isr, + #endif + BSP_INT_SRC_AL0_SCI9_ERI9, sci9_eri9_isr, + BIT4_MASK, BIT5_MASK, + &ICU.IPR[IPR_SCI9_RXI9].BYTE, + &ICU.IPR[IPR_SCI9_TXI9].BYTE, + &ICU.IR[IR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_TXI9].BYTE, + &ICU.IER[IER_SCI9_RXI9].BYTE, + &ICU.IER[IER_SCI9_TXI9].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch9_ctrl = {&ch9_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH9_FIFO_INCLUDED + , SCI_CFG_CH9_RX_FIFO_THRESH + , SCI_CFG_CH9_RX_FIFO_THRESH + , SCI_CFG_CH9_TX_FIFO_THRESH + , SCI_CFG_CH9_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH9_INCLUDED */ + + +#if SCI_CFG_CH10_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch10_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI10, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI10_TEI10, sci10_tei10_isr, + #endif + BSP_INT_SRC_AL0_SCI10_ERI10, sci10_eri10_isr, + BIT8_MASK, BIT9_MASK, + &ICU.IPR[IPR_SCI10_RXI10].BYTE, + &ICU.IPR[IPR_SCI10_TXI10].BYTE, + &ICU.IR[IR_SCI10_RXI10].BYTE, + &ICU.IR[IR_SCI10_TXI10].BYTE, + &ICU.IER[IER_SCI10_RXI10].BYTE, + &ICU.IER[IER_SCI10_TXI10].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT0_MASK, BIT1_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch10_ctrl = {&ch10_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH10_FIFO_INCLUDED + , SCI_CFG_CH10_RX_FIFO_THRESH + , SCI_CFG_CH10_RX_FIFO_THRESH + , SCI_CFG_CH10_TX_FIFO_THRESH + , SCI_CFG_CH10_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH10_INCLUDED */ + + +#if SCI_CFG_CH11_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch11_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI11, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT24_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI11_TEI11, sci11_tei11_isr, + #endif + BSP_INT_SRC_AL0_SCI11_ERI11, sci11_eri11_isr, + BIT12_MASK, BIT13_MASK, + &ICU.IPR[IPR_SCI11_RXI11].BYTE, + &ICU.IPR[IPR_SCI11_TXI11].BYTE, + &ICU.IR[IR_SCI11_RXI11].BYTE, + &ICU.IR[IR_SCI11_TXI11].BYTE, + &ICU.IER[IER_SCI11_RXI11].BYTE, + &ICU.IER[IER_SCI11_TXI11].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch11_ctrl = {&ch11_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH11_FIFO_INCLUDED + , SCI_CFG_CH11_RX_FIFO_THRESH + , SCI_CFG_CH11_RX_FIFO_THRESH + , SCI_CFG_CH11_TX_FIFO_THRESH + , SCI_CFG_CH11_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH11_INCLUDED */ + + +#if SCI_CFG_CH12_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch12_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI12, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT4_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI12_TEI12, sci12_tei12_isr, + #endif + BSP_INT_SRC_BL0_SCI12_ERI12, sci12_eri12_isr, + BIT16_MASK, BIT17_MASK, + &ICU.IPR[IPR_SCI12_RXI12].BYTE, + &ICU.IPR[IPR_SCI12_TXI12].BYTE, + &ICU.IR[IR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_TXI12].BYTE, + &ICU.IER[IER_SCI12_RXI12].BYTE, + &ICU.IER[IER_SCI12_TXI12].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch12_ctrl = {&ch12_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH12_INCLUDED */ + + +/* SCI HANDLE-ARRAY DECLARATION */ + +const sci_hdl_t g_handles[SCI_NUM_CH] = +{ +#if SCI_CFG_CH0_INCLUDED + &ch0_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH1_INCLUDED + &ch1_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH2_INCLUDED + &ch2_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH3_INCLUDED + &ch3_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH4_INCLUDED + &ch4_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH5_INCLUDED + &ch5_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH6_INCLUDED + &ch6_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH7_INCLUDED + &ch7_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH8_INCLUDED + &ch8_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH9_INCLUDED + &ch9_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH10_INCLUDED + &ch10_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH11_INCLUDED + &ch11_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH12_INCLUDED + &ch12_ctrl +#else + NULL +#endif +}; + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h new file mode 100644 index 000000000..6760bf730 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h @@ -0,0 +1,320 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx72n_private.h +* Description : Functions for using SCI on the RX72N device. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +#ifndef SCI_RX72N_H +#define SCI_RX72N_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../../r_sci_rx_private.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* Mask of all active channels */ +#define SCI_CFG_CH_INCLUDED_MASK ((SCI_CFG_CH0_INCLUDED << 0) | \ + (SCI_CFG_CH1_INCLUDED << 1) | \ + (SCI_CFG_CH2_INCLUDED << 2) | \ + (SCI_CFG_CH3_INCLUDED << 3) | \ + (SCI_CFG_CH4_INCLUDED << 4) | \ + (SCI_CFG_CH5_INCLUDED << 5) | \ + (SCI_CFG_CH6_INCLUDED << 6) | \ + (SCI_CFG_CH7_INCLUDED << 7) | \ + (SCI_CFG_CH8_INCLUDED << 8) | \ + (SCI_CFG_CH9_INCLUDED << 9) | \ + (SCI_CFG_CH10_INCLUDED << 10) | \ + (SCI_CFG_CH11_INCLUDED << 11) | \ + (SCI_CFG_CH12_INCLUDED << 12)) + +/* SCI SCR register masks */ +#define SCI_SCR_TEI_MASK (0x80U) /* transmit interrupt enable */ +#define SCI_SCR_REI_MASK (0x40U) /* receive interrupt enable */ +#define SCI_SCR_TE_MASK (0x20U) /* transmitter enable */ +#define SCI_SCR_RE_MASK (0x10U) /* receiver enable */ +#define SCI_EN_XCVR_MASK (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK | SCI_SCR_REI_MASK | SCI_SCR_TEI_MASK) + +/* SCI SSR register receiver error masks */ +#define SCI_SSR_ORER_MASK (0x20U) /* overflow error */ +#define SCI_SSR_FER_MASK (0x10U) /* framing error */ +#define SCI_SSR_PER_MASK (0x08U) /* parity err */ +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) +#define SCI_SSR_CLR_MASK (0xC0U) /* SSR register cleare mask (11000000b) */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_CLR_MASK (0xC6U) /* SSR register cleare mask (11000110b) */ +#define SCI_SSRFIFO_TDFE_MASK (0x80U) /* SSR register transmit data empty flag mask (10000000b) */ +#define SCI_SSRFIFO_RDF_MASK (0x40U) /* SSR register receive FIFO full flag mask (01000000b) */ +#define SCI_SSRFIFO_DR_MASK (0x01U) /* SSR register receive DR flag mask (00000001b) */ +#endif + +/* Macros to enable and disable ICU interrupts */ +#define ENABLE_RXI_INT (*hdl->rom->icu_rxi |= hdl->rom->rxi_en_mask) +#define DISABLE_RXI_INT (*hdl->rom->icu_rxi &= (uint8_t)~hdl->rom->rxi_en_mask) +#define ENABLE_TXI_INT (*hdl->rom->icu_txi |= hdl->rom->txi_en_mask) +#define DISABLE_TXI_INT (*hdl->rom->icu_txi &= (uint8_t)~hdl->rom->txi_en_mask) + +#define ENABLE_ERI_INT (*hdl->rom->icu_grp |= hdl->rom->eri_ch_mask) +#define DISABLE_ERI_INT (*hdl->rom->icu_grp &= ~hdl->rom->eri_ch_mask) +#define ENABLE_TEI_INT (*hdl->rom->icu_grp |= hdl->rom->tei_ch_mask) +#define DISABLE_TEI_INT (*hdl->rom->icu_grp &= ~hdl->rom->tei_ch_mask) + +#define NUM_DIVISORS_ASYNC (9) +#define NUM_DIVISORS_SYNC (4) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* ROM INFO */ + +typedef struct st_sci_ch_rom /* SCI ROM info for channel control block */ +{ + volatile struct st_sci7 R_BSP_EVENACCESS_SFR *regs; /* base ptr to ch registers */ + volatile uint32_t R_BSP_EVENACCESS_SFR *mstp; /* ptr to mstp register */ + uint32_t stop_mask; /* mstp mask to disable ch */ +#if SCI_CFG_TEI_INCLUDED + bsp_int_src_t tei_vector; + bsp_int_cb_t tei_isr; +#endif + bsp_int_src_t eri_vector; + bsp_int_cb_t eri_isr; + uint32_t tei_ch_mask; /* ICU IR and IEN mask */ + uint32_t eri_ch_mask; /* ICU IR and IEN mask */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_rxi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_txi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_rxi; /* ptr to RXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_txi; /* ptr to TXI IR register */ + + /* + * DO NOT use the enable/disable interrupt bits in the SCR + * register. Pending interrupts can be lost that way. + */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_rxi; /* ptr to ICU register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_txi; + volatile uint32_t R_BSP_EVENACCESS_SFR *icu_grp; + uint8_t rxi_en_mask; /* ICU enable/disable rxi mask */ + uint8_t txi_en_mask; /* ICU enable/disable txi mask */ +} sci_ch_rom_t; + + +/* CHANNEL CONTROL BLOCK */ + +typedef struct st_sci_ch_ctrl /* SCI channel control (for handle) */ +{ + sci_ch_rom_t const *rom; /* pointer to rom info */ + sci_mode_t mode; /* operational mode */ + uint32_t baud_rate; /* baud rate */ + void (*callback)(void *p_args); /* function ptr for rcvr errs */ + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async transmit queue handle */ +#endif + uint8_t *buf; /* sspi/sync tx buffer ptr */ + } u_tx_data; + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async receive queue handle */ +#endif + uint8_t *buf; /* sspi/sync rx buffer ptr */ + } u_rx_data; + bool tx_idle; /* TDR is empty (async); TSR is empty (sync/sspi) */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + bool save_rx_data; /* save the data that is clocked in */ + uint16_t tx_cnt; /* number of bytes to transmit */ + uint16_t rx_cnt; /* number of bytes to receive */ + bool tx_dummy; /* transmit dummy byte, not buffer */ +#endif + uint32_t pclk_speed; /* saved peripheral clock speed for break generation */ +#if SCI_CFG_FIFO_INCLUDED + uint8_t fifo_ctrl; /* fifo ctrl (enable/disable) flag */ + uint8_t rx_dflt_thresh; /* RX FIFO threshold(default) */ + uint8_t rx_curr_thresh; /* RX FIFO threshold(current) */ + uint8_t tx_dflt_thresh; /* TX FIFO threshold(default) */ + uint8_t tx_curr_thresh; /* TX FIFO threshold(current) */ +#endif +} sci_ch_ctrl_t; + + +/* BAUD DIVISOR INFO */ + +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=0, divisor = 64*pow(2,2n-1) */ + +typedef struct st_baud_divisor +{ + int16_t divisor; // clock divisor + uint8_t abcs; // abcs value to get divisor + uint8_t bgdm; // bdgm value to get divisor + uint8_t cks; // cks value to get divisor (cks = n) +} baud_divisor_t; + + + +/***************************************************************************** +Exported global variables and functions +******************************************************************************/ +extern const sci_hdl_t g_sci_handles[]; + +#if (SCI_CFG_ASYNC_INCLUDED) +extern const baud_divisor_t async_baud[]; +#endif +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern const baud_divisor_t sync_baud[]; +#endif + +#if (SCI_CFG_CH0_INCLUDED) +extern const sci_ch_rom_t ch0_rom; +extern sci_ch_ctrl_t ch0_ctrl; +#endif + +#if (SCI_CFG_CH1_INCLUDED) +extern const sci_ch_rom_t ch1_rom; +extern sci_ch_ctrl_t ch1_ctrl; +#endif + +#if (SCI_CFG_CH2_INCLUDED) +extern const sci_ch_rom_t ch2_rom; +extern sci_ch_ctrl_t ch2_ctrl; +#endif + +#if (SCI_CFG_CH3_INCLUDED) +extern const sci_ch_rom_t ch3_rom; +extern sci_ch_ctrl_t ch3_ctrl; +#endif + +#if (SCI_CFG_CH4_INCLUDED) +extern const sci_ch_rom_t ch4_rom; +extern sci_ch_ctrl_t ch4_ctrl; +#endif + +#if (SCI_CFG_CH5_INCLUDED) +extern const sci_ch_rom_t ch5_rom; +extern sci_ch_ctrl_t ch5_ctrl; +#endif + +#if (SCI_CFG_CH6_INCLUDED) +extern const sci_ch_rom_t ch6_rom; +extern sci_ch_ctrl_t ch6_ctrl; +#endif + +#if (SCI_CFG_CH7_INCLUDED) +extern const sci_ch_rom_t ch7_rom; +extern sci_ch_ctrl_t ch7_ctrl; +#endif + +#if (SCI_CFG_CH8_INCLUDED) +extern const sci_ch_rom_t ch8_rom; +extern sci_ch_ctrl_t ch8_ctrl; +#endif + +#if (SCI_CFG_CH9_INCLUDED) +extern const sci_ch_rom_t ch9_rom; +extern sci_ch_ctrl_t ch9_ctrl; +#endif + +#if (SCI_CFG_CH10_INCLUDED) +extern const sci_ch_rom_t ch10_rom; +extern sci_ch_ctrl_t ch10_ctrl; +#endif + +#if (SCI_CFG_CH11_INCLUDED) +extern const sci_ch_rom_t ch11_rom; +extern sci_ch_ctrl_t ch11_ctrl; +#endif + +#if (SCI_CFG_CH12_INCLUDED) +extern const sci_ch_rom_t ch12_rom; +extern sci_ch_ctrl_t ch12_ctrl; +#endif + +/***************************************************************************** +Exported global functions +******************************************************************************/ +#if SCI_CFG_TEI_INCLUDED +extern void sci0_tei0_isr(void *cb_args); +extern void sci1_tei1_isr(void *cb_args); +extern void sci2_tei2_isr(void *cb_args); +extern void sci3_tei3_isr(void *cb_args); +extern void sci4_tei4_isr(void *cb_args); +extern void sci5_tei5_isr(void *cb_args); +extern void sci6_tei6_isr(void *cb_args); +extern void sci7_tei7_isr(void *cb_args); +extern void sci8_tei8_isr(void *cb_args); +extern void sci9_tei9_isr(void *cb_args); +extern void sci10_tei10_isr(void *cb_args); +extern void sci11_tei11_isr(void *cb_args); +extern void sci12_tei12_isr(void *cb_args); +#endif /* End of SCI_CFG_TEI_INCLUDED */ + +extern void sci0_eri0_isr(void *cb_args); +extern void sci1_eri1_isr(void *cb_args); +extern void sci2_eri2_isr(void *cb_args); +extern void sci3_eri3_isr(void *cb_args); +extern void sci4_eri4_isr(void *cb_args); +extern void sci5_eri5_isr(void *cb_args); +extern void sci6_eri6_isr(void *cb_args); +extern void sci7_eri7_isr(void *cb_args); +extern void sci8_eri8_isr(void *cb_args); +extern void sci9_eri9_isr(void *cb_args); +extern void sci10_eri10_isr(void *cb_args); +extern void sci11_eri11_isr(void *cb_args); +extern void sci12_eri12_isr(void *cb_args); + +extern void sci_init_register(sci_hdl_t const hdl); + +#if (SCI_CFG_ASYNC_INCLUDED) +extern sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +extern sci_err_t sci_mcu_param_check(uint8_t const chan); + +extern int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud); + +extern void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority); + +extern void sci_disable_ints(sci_hdl_t const hdl); + +#endif /* SCI_RX72N_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/CC_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/CC_patch.h new file mode 100644 index 000000000..5f604deb9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/CC_patch.h @@ -0,0 +1,22 @@ +#ifndef CC_PATCH_H +#define CC_PATCH_H + +#if defined(__CCRX__) + +/* This file has to be included by using CC-RX's -preinclude option. */ + +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#ifndef _FEVAL +#define _FEVAL 0 +#endif +#ifndef _FEVVAL +#define _FEVVAL 0 +#endif +#ifndef _HAS_C9X_FAST_FMA +#define _HAS_C9X_FAST_FMA 0 +#endif + +#endif /* defined(__CCRX__) */ + +#endif /* CC_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/CG_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/CG_patch.h new file mode 100644 index 000000000..d390aeb5b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/CG_patch.h @@ -0,0 +1,9 @@ +#ifndef CG_PATCH_H +#define CG_PATCH_H + +/* Workaround for warning messages caused by missing function declaration. + */ +void R_CGC_Create_UserInit(void); +void r_undefined_exception(void); + +#endif /* CG_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch.c new file mode 100644 index 000000000..4f6af1b8e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch.c @@ -0,0 +1,63 @@ +#include "platform.h" +#include + +#if BSP_CFG_RTOS_USED != 0 + +/* Replacement to be thread-safe (in case of other than using heap_3.c). */ +void *malloc( size_t xWantedSize ) +{ +#if BSP_CFG_RTOS_USED == 1 + /* FreeRTOS */ + + return pvPortMalloc( xWantedSize ); +#else + /* SEGGER embOS */ + /* Micrium MicroC/OS */ + /* Renesas RI600V4 & RI600PX */ + + #error "Unsupported RTOS is selected." +#endif +} + +/* Replacement to be thread-safe (in case of other than using heap_3.c). */ +void free( void *pv ) +{ +#if BSP_CFG_RTOS_USED == 1 + /* FreeRTOS */ + + vPortFree( pv ); +#else + /* SEGGER embOS */ + /* Micrium MicroC/OS */ + /* Renesas RI600V4 & RI600PX */ + + #error "Unsupported RTOS is selected." +#endif +} + +#if defined(__GNUC__) + +int8_t *sbrk( size_t size ); + +/* Maybe not called but necessary for linking without an undefined error. */ +int8_t *sbrk( size_t size ) +{ + ( void ) size; + return (int8_t *)-1; +} + +#endif /* defined(__GNUC__) */ + +#if defined(__ICCRX__) + +void main( void ); + +/* Never called but necessary for linking without an undefined error. */ +void main( void ) +{ + /* Nothing to do. */ +} + +#endif /* defined(__ICCRX__) */ + +#endif /* BSP_CFG_RTOS_USED != 0 */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch.h new file mode 100644 index 000000000..cfc555838 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch.h @@ -0,0 +1,32 @@ +#ifndef FIT_PATCH_H +#define FIT_PATCH_H + +/* Workaround for the stand alone RX SmartConfigurator's missing support of FreeRTOS project. + */ +#define BSP_CFG_RTOS_USED (1) + +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#define SCI_CFG_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_FIFO_INCLUDED (0) + +/* Workaround for warning messages caused by missing 'void' argument prototype. + */ +void R_SCI_PinSet_SCI2(void); +void R_SCI_PinSet_SCI9(void); + +#if defined(__ICCRX__) + +/* Workaround to reduce the following remark messages caused in the r_rx_compiler.h. + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * Turn off the remark messages temporarily. + */ +#pragma diag_suppress = Pe007 + +#endif /* defined(__ICCRX__) */ + +#endif /* FIT_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch2.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch2.h new file mode 100644 index 000000000..010be9edb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/FIT_patch2.h @@ -0,0 +1,60 @@ +#ifndef FIT_PATCH2_H +#define FIT_PATCH2_H + +#if defined(__ICCRX__) + +/* Workaround to reduce the following remark messages caused in the r_rx_compiler.h. + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * Turn on the remark messages here. + */ +#pragma diag_default = Pe007 + +/* Workaround to reduce the following remark messages. (The following is example.) + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * R_BSP_ASM( SUB #01H, R1 ) + * ^ + * "XXX\r_bsp_common.c",NNN Remark[Pe010]: "#" not expected here + * + * R_BSP_ASM_BEGIN + * ^ + * "XXX\r_bsp_common.c",NNN Remark[Pa174]: inline assembler statement has no declared + * side-effect. All optimizations around it will be disabled. Either add side-effect + * declarations or add volatile. + * + * Now redefine the following macros. + */ +#if !defined(__CDT_PARSER__) + +#undef _R_BSP_ASM +#undef R_BSP_ASM +/* #undef R_BSP_ASM_LAB_NEXT */ /* no change */ +/* #undef R_BSP_ASM_LAB_PREV */ /* no change */ +/* #undef R_BSP_ASM_LAB */ /* no change */ +#undef R_BSP_ASM_BEGIN +#undef R_BSP_ASM_END + +#define _R_BSP_ASM(...) #__VA_ARGS__ "\n" +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__) +/* #define R_BSP_ASM_LAB_NEXT(n) _lab##n */ /* no change */ +/* #define R_BSP_ASM_LAB_PREV(n) _lab##n */ /* no change */ +/* #define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) */ /* no change */ +#define R_BSP_ASM_BEGIN R_BSP_PRAGMA(diag_suppress = Pa174)\ + R_BSP_PRAGMA(diag_suppress = Pe010)\ + __asm volatile( +#define R_BSP_ASM_END );\ + R_BSP_PRAGMA(diag_default = Pe010)\ + R_BSP_PRAGMA(diag_default = Pa174) + +#endif /* !defined(__CDT_PARSER__) */ + +#endif /* defined(__ICCRX__) */ + +#endif /* FIT_PATCH2_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/IDE_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/IDE_patch.h new file mode 100644 index 000000000..0c5dcdbb1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/IDE_patch.h @@ -0,0 +1,42 @@ +#ifndef IDE_PATCH_H +#define IDE_PATCH_H + +#if defined(__CDT_PARSER__) + +#if defined(__CCRX__) + +/* Workaround for missing pre-defined macro in the Renesas Toolchain Builtin + * Language Settings. + */ +#ifndef __TFU +#define __TFU 1 +#endif + +/* Workaround for wrong pre-defined macro in the Renesas Toolchain Builtin + * Language Settings. + */ +#ifdef __DBL4 +#undef __DBL4 +#endif +#ifndef __DBL8 +#define __DBL8 1 +#endif + +#endif /* defined(__CCRX__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. + */ +#ifndef __asm +#define __asm asm +#endif +#ifndef __attribute__ +#define __attribute__(...) +#endif + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +#endif /* defined(__CDT_PARSER__) */ + +#endif /* IDE_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_bsp_patch/platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_bsp_patch/platform.h new file mode 100644 index 000000000..d7cec9d35 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_bsp_patch/platform.h @@ -0,0 +1,17 @@ +#ifndef PLATFORM_PATCH_H +#define PLATFORM_PATCH_H + +#include "../smc_gen/r_bsp/platform.h" + +/* In case of stand alone Smart Configurator and CS+, generating source code places + * the /src/smc_gen/r_bsp folder prior to the /src/smc_workaround/r_bsp_patch folder + * in the include folder list so that including patch files here is not recommended + * when CC-RX is used. + */ +#if defined(__GNUC__) || defined(__ICCRX__) + +#include "FIT_patch2.h" + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +#endif /* PLATFORM_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c new file mode 100644 index 000000000..ee873a979 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c @@ -0,0 +1,5 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#include "../../smc_gen/r_dtc_rx/r_dtc_rx_if.h" +#include "../../smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h" +#include "../../smc_gen/r_dtc_rx/src/r_dtc_rx.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h new file mode 100644 index 000000000..8b78568b8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h @@ -0,0 +1,4 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#define bsp_lock_t 0 +#include "../smc_gen/r_dtc_rx/src/r_dtc_rx_private.h" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c new file mode 100644 index 000000000..aa7a135b1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c @@ -0,0 +1,5 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#include "../../smc_gen/r_dtc_rx/r_dtc_rx_if.h" +#include "../../smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h" +#include "../../smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/smc_workaround.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/smc_workaround.h new file mode 100644 index 000000000..13abedd52 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_GCC_e2studio/src/smc_workaround/smc_workaround.h @@ -0,0 +1,33 @@ +#ifndef SMC_WORKAROUND_H +#define SMC_WORKAROUND_H + +#include "CC_patch.h" +#include "IDE_patch.h" +#include "CG_patch.h" +#include "FIT_patch.h" + +#if defined(__GNUC__) + +/* Just for convenience. + */ +#define brk() R_BSP_BRK() +#define int_exception(x) R_BSP_INT(x) +#define wait() R_BSP_WAIT() +#define nop() R_BSP_NOP() + +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) + +/* Just for convenience. + */ +#define setpsw_i() R_BSP_SETPSW_I() +#define clrpsw_i() R_BSP_CLRPSW_I() + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/* Just for convenience. For example, memcmp(), memcpy(), memset(), and so on. + */ +#include + +#endif /* SMC_WORKAROUND_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.cproject b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.cproject new file mode 100644 index 000000000..ea4ec32cd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.cproject @@ -0,0 +1,314 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.project b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.project new file mode 100644 index 000000000..6247a011d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.project @@ -0,0 +1,260 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS + 2 + virtual:/virtual + + + src/FreeRTOS/Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/FreeRTOS_Demo/Full_Demo/FreeRTOS-Plus-CLI + 2 + FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI + + + src/FreeRTOS_Demo/Full_Demo/Sample-CLI-commands.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c + + + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/FreeRTOS_Demo/Full_Demo/UARTCommandConsole.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c + + + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1593736401112 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RTOSDemo_ICCRX.scfg + + + + 1593736401170 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RTOSDemo_ICCRX.ipcf + + + + 0 + src/FreeRTOS/Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 0 + src/FreeRTOS/Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 0 + src/FreeRTOS/Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IAR + + + + 1442773470090 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442773470090 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442773470100 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442773470100 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442773470110 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442773470110 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442773470120 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442773470120 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442773470130 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442773470130 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442773470140 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442773470140 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442773470150 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442773470150 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442773470160 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 0 + src/FreeRTOS/Source/portable/IAR + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX700v3_DPFPU + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.settings/fittemp/r_sci_rx.ftl b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.settings/fittemp/r_sci_rx.ftl new file mode 100644 index 000000000..a505f3edd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.settings/fittemp/r_sci_rx.ftl @@ -0,0 +1,85 @@ +<#-- + Copyright(C) 2015 Renesas Electronics Corporation + RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + This program must be used solely for the purpose for which it was furnished + by Renesas Electronics Corporation. No part of this program may be reproduced + or disclosed to others, in any form, without the prior written permission of + Renesas Electronics Corporation. +--> +<#-- = DECLARE FUNCTION INFORMATION HERE =================== --> +<#-- + (Step 1) Explanation: These variables are necessary information for the function header. + Please fill up or leave blank, but do not delete +--> +<#assign Function_Base_Name = "R_SCI_PinSet"> +<#assign Function_Description = "This function initializes pins for r_sci_rx module"> +<#assign Function_Arg = "none"> +<#assign Function_Ret = "none"> +<#assign Version = 1.00> + +<#-- = DECLARE FUNCTION CONTENT HERE ======================= --> +<#-- + (Step 2) Explanation: Function content. + - Macro [initialsection] : + Any text that goes into this section will be printed out 1 time per function + input [postfix] :Use this variable to add the channel number to the function base name. +--> +<#macro initialsection postfix> +<#assign Function_Name = "${Function_Base_Name}${postfix}"> +<#include "lib/functionheader.ftl"> +void ${Function_Name}() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + +<#-- + (Step 3) Explanation: Function content. + - Macro [peripheralpincode] : Any text that goes into this section will be printed out 1 time per peripheral + - input [pin] : Available info includes: + pin.pinName :The name of pin, eg “SSLA0” + pin.assignedPinName :The pin assigned to, eg “P32” + pin.pinMPC :The port number of assigned pin, eg “P32” has portNume = “3” + pin.portNum :The bit number of the assigned pin, eg “P32” has pinBitNum = “2” + pin.pinBitNum :The value of MPC +--> +<#macro peripheralpincode pin> + + +<#-- + (Step 4) Explanation: Function content. + - Macro [channelpincode] : Any text that goes into this section will be printed out 1 time per channel + - input [pin] : Same as above +--> +<#macro channelpincode pin> + + /* Set ${pin.pinName} pin */ + MPC.${pin.assignedPinName}PFS.BYTE = 0x${pin.pinMPC}U; + PORT${pin.portNum}.PMR.BIT.B${pin.pinBitNum} = 1U; + + +<#macro channelpincodeextra pin postfix> + + +<#-- + (Step 5) Explanation: Function content. + - Macro [endsection] : Any text that goes into this section will be printed out 1 time last +--> +<#macro endsection> + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + + +<#-- + (Step 6) Explanation: Header file content + - Macro [headerfilesection] : Any text that goes into this section will be printed out 1 time in the header file + - input [postfix] :Use this variable to add the channel number to the function base name. +--> +<#macro headerfilesection postfix> +void ${Function_Base_Name}${postfix}(); + + +<#macro headerfilesectionExtra postfix> + + +<#-- = END OF FILE ========================================= --> \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.settings/org.eclipse.cdt.core.prefs b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 000000000..0b8fbc2fb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,14 @@ +eclipse.preferences.version=1 +indexer/indexAllFiles=false +indexer/indexAllHeaderVersions=true +indexer/indexAllVersionsSpecificHeaders= +indexer/indexOnOpen=false +indexer/indexUnusedHeadersWithDefaultLang=false +indexer/indexerId=org.eclipse.cdt.core.fastIndexer +indexer/skipFilesLargerThanMB=8 +indexer/skipImplicitReferences=false +indexer/skipIncludedFilesLargerThanMB=16 +indexer/skipMacroReferences=false +indexer/skipReferences=false +indexer/skipTypeReferences=false +indexer/useHeuristicIncludeResolution=false diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..744a48b31 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo HardwareDebug.launch @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.custom_argvars b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.custom_argvars new file mode 100644 index 000000000..976d19e95 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.custom_argvars @@ -0,0 +1,2 @@ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.ewd b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.ewd new file mode 100644 index 000000000..467c83c5e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.ewd @@ -0,0 +1,794 @@ + + + 3 + + Debug + + RX + + 1 + + C-SPY + 5 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 5 + + 6 + 1 + 1 + + + + + + + + + + + + + RXE2 + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + RXE2LITE + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + RXJLINK + 4 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + SIMRX + 1 + + 3 + 1 + 1 + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + RX + + 0 + + C-SPY + 5 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 5 + + 6 + 1 + 0 + + + + + + + + + + + + + RXE2 + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + RXE2LITE + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + RXJLINK + 4 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + SIMRX + 1 + + 3 + 1 + 0 + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.ewp b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.ewp new file mode 100644 index 000000000..e963ac438 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.ewp @@ -0,0 +1,2823 @@ + + + 3 + + Debug + + RX + + 1 + + General + 7 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 10 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 6 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + RX + + 0 + + General + 7 + + 7 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 10 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\Source\include\queue.h + + + $PROJ_DIR$\..\..\Source\include\semphr.h + + + $PROJ_DIR$\..\..\Source\include\stack_macros.h + + + $PROJ_DIR$\..\..\Source\include\StackMacros.h + + + $PROJ_DIR$\..\..\Source\include\stdint.readme + + + $PROJ_DIR$\..\..\Source\include\stream_buffer.h + + + $PROJ_DIR$\..\..\Source\include\task.h + + + $PROJ_DIR$\..\..\Source\include\timers.h + + + + portable + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + $PROJ_DIR$\..\..\Source\portable\IAR\RX700v3_DPFPU\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\RX700v3_DPFPU\portmacro.h + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + FreeRTOS_Demo + + Blinky_Demo + + $PROJ_DIR$\src\FreeRTOS_Demo\Blinky_Demo\main_blinky.c + + + + Full_Demo + + FreeRTOS+CLI + + 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$PROJ_DIR$\src\smc_workaround\FIT_patch2.h + + + $PROJ_DIR$\src\smc_workaround\IDE_patch.h + + + $PROJ_DIR$\src\smc_workaround\smc_workaround.h + + + + + $PROJ_DIR$\RTOSDemo_ICCRX.ipcf + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.eww b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.eww new file mode 100644 index 000000000..43a672e84 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo_ICCRX.ipcf b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo_ICCRX.ipcf new file mode 100644 index 000000000..1cd12c28e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo_ICCRX.ipcf @@ -0,0 +1,811 @@ + + + + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\general + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_bsp + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_byteq + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_config + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_dtc_rx + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_gpio_rx + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_pincfg + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_sci_rx + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_byteq\src + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_gpio_rx\src + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_sci_rx\src + C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\src\smc_gen\r_dtc_rx\src + + + + + + .\src\smc_gen\general\r_cg_hardware_setup.c + + + + + .\src\smc_gen\general\r_cg_macrodriver.h + + + + + .\src\smc_gen\general\r_cg_userdefine.h + + + + + .\src\smc_gen\general\r_smc_cgc.c + + + + + .\src\smc_gen\general\r_smc_cgc.h + + + + + .\src\smc_gen\general\r_smc_cgc_user.c + + + + + .\src\smc_gen\general\r_smc_entry.h + + + + + .\src\smc_gen\general\r_smc_interrupt.c + + + + + .\src\smc_gen\general\r_smc_interrupt.h + + + + + + + .\src\smc_gen\r_bsp\board\generic_rx72n\hwsetup.c + + + + + + + + + .\src\smc_gen\r_bsp\board\generic_rx72n\hwsetup.h + + + + + + + + + .\src\smc_gen\r_bsp\board\generic_rx72n\r_bsp.h + + + + + + + + + .\src\smc_gen\r_bsp\board\generic_rx72n\r_bsp_config_reference.h + + + + + + + + + .\src\smc_gen\r_bsp\board\generic_rx72n\r_bsp_interrupt_config_reference.h + + + + + + + + + .\src\smc_gen\r_bsp\board\user\r_bsp.h + + + + + + + + + .\src\smc_gen\r_bsp\doc\en\r01an1685ej0552-rx-bsp.pdf + + + + + + + + + .\src\smc_gen\r_bsp\doc\ja\r01an1685jj0552-rx-bsp.pdf + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\lowlvl.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\lowsrc.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\mcu_locks.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\resetprg.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_common.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_common.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_cpu.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_interrupts.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_interrupts.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_locking.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_mcu_startup.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_mcu_startup.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_software_interrupt.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_bsp_software_interrupt.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_rtos.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_rx_compiler.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_rx_intrinsic_functions.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_rx_intrinsic_functions.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\all\r_typedefs.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_clocks.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_clocks.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_info.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_init.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_init.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_interrupts.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_interrupts.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_locks.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_mapped_interrupts.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_mapped_interrupts.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\mcu_mapped_interrupts_private.h + + + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\register_access\iccrx\iodefine.h + + + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\r_bsp_cpu.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\r_bsp_locking.h + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\vecttbl.c + + + + + + + + + .\src\smc_gen\r_bsp\mcu\rx72n\vecttbl.h + + + + + + + .\src\smc_gen\r_bsp\platform.h + + + + + .\src\smc_gen\r_bsp\readme.txt + + + + + + + .\src\smc_gen\r_byteq\doc\en\r01an1683ej0180-rx-apl.pdf + + + + + + + + + .\src\smc_gen\r_byteq\doc\ja\r01an1683jj0180-rx-apl.pdf + + + + + + + .\src\smc_gen\r_byteq\readme.txt + + + + + + .\src\smc_gen\r_byteq\ref\r_byteq_config_reference.h + + + + + + .\src\smc_gen\r_byteq\r_byteq_if.h + + + + + + .\src\smc_gen\r_byteq\src\r_byteq.c + + + + + + + .\src\smc_gen\r_byteq\src\r_byteq_private.h + + + + + + .\src\smc_gen\r_config\r_bsp_config.h + + + + + .\src\smc_gen\r_config\r_bsp_config_readme.txt + + + + + .\src\smc_gen\r_config\r_bsp_interrupt_config.h + + + + + .\src\smc_gen\r_config\r_byteq_config.h + + + + + .\src\smc_gen\r_config\r_dtc_rx_config.h + + + + + .\src\smc_gen\r_config\r_gpio_rx_config.h + + + + + .\src\smc_gen\r_config\r_sci_rx_config.h + + + + + + + .\src\smc_gen\r_dtc_rx\doc\en\r01an1819ej0350-rx-dtc-dmac2.pdf + + + + + + + + + .\src\smc_gen\r_dtc_rx\doc\ja\r01an1819jj0350-rx-dtc-dmac2.pdf + + + + + + + .\src\smc_gen\r_dtc_rx\readme.txt + + + + + + .\src\smc_gen\r_dtc_rx\ref\r_dtc_rx_config_reference.h + + + + + + .\src\smc_gen\r_dtc_rx\r_dtc_rx_if.h + + + + + + .\src\smc_gen\r_dtc_rx\src\r_dtc_rx.c + + + + + + + .\src\smc_gen\r_dtc_rx\src\r_dtc_rx_private.h + + + + + + + + + .\src\smc_gen\r_dtc_rx\src\targets\rx72n\r_dtc_rx_target.c + + + + + + + + + + + .\src\smc_gen\r_dtc_rx\src\targets\rx72n\r_dtc_rx_target.h + + + + + + + + + + + .\src\smc_gen\r_dtc_rx\src\targets\rx72n\r_dtc_rx_target_if.h + + + + + + + + + + .\src\smc_gen\r_gpio_rx\doc\en\r01an1721ej0350-rx-gpio.pdf + + + + + + + + + .\src\smc_gen\r_gpio_rx\doc\ja\r01an1721jj0350-rx-gpio.pdf + + + + + + + .\src\smc_gen\r_gpio_rx\readme.txt + + + + + + .\src\smc_gen\r_gpio_rx\ref\r_gpio_rx_config_reference.h + + + + + + .\src\smc_gen\r_gpio_rx\r_gpio_rx_if.h + + + + + + .\src\smc_gen\r_gpio_rx\src\r_gpio_rx.c + + + + + + + + + .\src\smc_gen\r_gpio_rx\src\targets\rx72n\r_gpio_rx72n.c + + + + + + + + + + + .\src\smc_gen\r_gpio_rx\src\targets\rx72n\r_gpio_rx72n.h + + + + + + + + .\src\smc_gen\r_pincfg\Pin.c + + + + + .\src\smc_gen\r_pincfg\Pin.h + + + + + .\src\smc_gen\r_pincfg\r_pinset.h + + + + + .\src\smc_gen\r_pincfg\r_sci_rx_pinset.c + + + + + .\src\smc_gen\r_pincfg\r_sci_rx_pinset.h + + + + + + + .\src\smc_gen\r_sci_rx\doc\en\r01an1815ej0350-rx-serial.pdf + + + + + + + + + .\src\smc_gen\r_sci_rx\doc\ja\r01an1815jj0350-rx-serial.pdf + + + + + + + .\src\smc_gen\r_sci_rx\readme.txt + + + + + + .\src\smc_gen\r_sci_rx\ref\r_sci_rx_config_reference.h + + + + + + .\src\smc_gen\r_sci_rx\r_sci_rx_if.h + + + + + + .\src\smc_gen\r_sci_rx\src\r_sci_rx.c + + + + + + + .\src\smc_gen\r_sci_rx\src\r_sci_rx_platform.h + + + + + + + .\src\smc_gen\r_sci_rx\src\r_sci_rx_private.h + + + + + + + + + .\src\smc_gen\r_sci_rx\src\targets\rx72n\r_sci_rx72n.c + + + + + + + + + + + .\src\smc_gen\r_sci_rx\src\targets\rx72n\r_sci_rx72n_data.c + + + + + + + + + + + .\src\smc_gen\r_sci_rx\src\targets\rx72n\r_sci_rx72n_private.h + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo_ICCRX.scfg b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo_ICCRX.scfg new file mode 100644 index 000000000..8d81edd9d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/RTOSDemo_ICCRX.scfg @@ -0,0 +1,865 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/SmartConfigurator.launch b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/SmartConfigurator.launch new file mode 100644 index 000000000..3e906fac2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/SmartConfigurator.launch @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..dfc9cb078 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Renesas\EWB\8.4\common\bin\cspybat" -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Renesas\EWB\8.4\common\bin\cspybat" -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.cspy.ps1 b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.cspy.ps1 new file mode 100644 index 000000000..f1a8cd021 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Renesas\EWB\8.4\common\bin\cspybat" -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.driver.xcl" +} +else +{ +& "C:\Renesas\EWB\8.4\common\bin\cspybat" -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\settings\RTOSDemo.Debug.driver.xcl" +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..1d65ffdfd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,35 @@ +"-p" + +"C:\Renesas\EWB\8.4\rx\config\debugger\ior5f572nn.ddf" + +"--endian" + +"l" + +"--double" + +"64" + +"--core" + +"rxv3" + +"--int" + +"32" + +"--fpu" + +"64" + +"-d" + +"e2lite" + +"--drv_mode" + +"debugging" + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..86336ce8a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Renesas\EWB\8.4\rx\bin\rxproc.dll" + +"C:\Renesas\EWB\8.4\rx\bin\rxe2e2l.dll" + +"C:\Renesas\GitHubDesktop\work\FreeRTOS\FreeRTOS\Demo\RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX\Debug\Exe\RTOSDemo.out" + +--plugin="C:\Renesas\EWB\8.4\rx\bin\rxbat.dll" + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.crun b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.crun new file mode 100644 index 000000000..d71ea555a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.dni b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.dni new file mode 100644 index 000000000..e27b37590 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.dni @@ -0,0 +1,250 @@ +[DebugChecksum] +Checksum=-1340739960 +[CodeCoverage] +Enabled=_ 0 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[E1/E20] +BlockBits=15 +B0=1,0 +B1=1,1024 +B2=1,2048 +B3=1,3072 +StartEnabled=0 +StartSymbol= +StopEnabled=0 +StopSymbol= +RecordingCondition=0 +TraceMode=0 +TraceOutput=0 +TraceType=0 +TraceCapacity=0 +TraceRestart=0 +TraceTimeStamp=0 +TraceTimestampDivision=0 +TraceDataTransfer=1 +TraceStackOperation=1 +TraceStringOperation=1 +TraceArithmeticalOperation=1 +TraceLogicalOperation=1 +TraceBitOperation=1 +TraceFPU=1 +TraceException=1 +OperatingFrequency=0.000000 +PerfEnabled=0 +PerfCondition=0,0 +PerfDisplayTime=0,0 +PerfOnlyOnce=0,0 +PerfUse64Bit=0 +ChipName=R5F571ML +PinMode=0 +RegMode=0 +Endian=0 +ExtMemBlockNum=55 +ExtMemEndian_000=0 +ExtMemCondAccess_000=0 +ExtMemEndian_001=0 +ExtMemCondAccess_001=0 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+ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Breakpoints2] +Count=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[Simulator] +Freq=98000000 +[DataSample] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +[DriverProfiling] +Enabled=0 +Mode=1 +Graph=0 +Symbiont=0 +Exclusions= +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[Monitor Execution] +Leave target running=0 +Release target=0 +[Trace1] +Enabled=0 +ShowSource=1 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.dnx b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.dnx new file mode 100644 index 000000000..b9c329911 --- /dev/null +++ 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0 + + + 0 + 1 + + + 0 + 0 + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.wspos b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.wspos new file mode 100644 index 000000000..5275c93f4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 250 0 1350 872 3 diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..4f08d0f62 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It sends the value 100 to the queue every 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. It blocks on the queue to wait for data to arrive from the + * queue send task - toggling the LED each time it receives the value 100. The + * queue send task writes to the queue every 200ms, so the LED should toggle + * every 200ms. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "platform.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200UL ) ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..0d900caa8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c @@ -0,0 +1,130 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This file contains the non-portable and therefore RX specific parts of the + * IntQueue standard demo task - namely the configuration of the timers that + * generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Renesas includes. */ +#include "platform.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2000UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_2_3_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set priority and enable interrupt. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IEN( PERIB, INTB128 ) = 1; + + /* Ensure that the flag is set to 0, otherwise the interrupt will not be + accepted. */ + IR( PERIB, INTB128 ) = 0; + + /* Do the same for TMR2, but to vector 129. */ + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IEN( PERIB, INTB129 ) = 1; + IR( PERIB, INTB129 ) = 0; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +R_BSP_PRAGMA_STATIC_INTERRUPT( prvIntQTimer_0_1_ISR, VECT( PERIB, INTB128) ) +R_BSP_ATTRIB_STATIC_INTERRUPT void prvIntQTimer_0_1_ISR( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + setpsw_i(); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +R_BSP_PRAGMA_STATIC_INTERRUPT( prvIntQTimer_2_3_ISR, VECT( PERIB, INTB129) ) +R_BSP_ATTRIB_STATIC_INTERRUPT void prvIntQTimer_2_3_ISR( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + setpsw_i(); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..49c2351d8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c new file mode 100644 index 000000000..05eda5290 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/main_full.c @@ -0,0 +1,847 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates a set of demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "FreeRTOS+CLI command console" - The command console uses SCI1 for its + * input and output. The baud rate is set to 19200. Type "help" to see a list + * of registered commands. The FreeRTOS+CLI license is different to the + * FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage + * details. + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks are not only still executing, + * but are executing without reporting any errors. If the check task discovers + * that a task has either stalled, or reported an error, then it changes its own + * execution period from the initial three seconds, to just 200ms. The check + * task also toggles an LED on each iteration of its loop. This provides a + * visual indication of the system status: If the LED toggles every three + * seconds, then no issues have been discovered. If the LED toggles every + * 200ms, then an issue has been discovered with at least one task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include "platform.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The period of the check task, in ms, provided no errors have been reported by +any of the standard demo tasks. ms are converted to the equivalent in ticks +using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) + +/* The period of the check task, in ms, if an error has been reported in one of +the standard demo tasks. ms are converted to the equivalent in ticks using the +portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL ); + + /* Start the tasks that implements the command console on the UART, as + described above. */ + vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); + + /* Register the standard CLI commands. */ + vRegisterSampleCLICommands(); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = pdMS_TO_TICKS( 35 ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + +#if defined(__DPFPU) + + /* Tell the kernel that this task require a DPFPU context before any DPFPU + instructions are executed. */ + portTASK_USES_DPFPU(); + +#endif /* defined(__DPFPU) */ + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + +#if defined(__DPFPU) + + /* Tell the kernel that this task require a DPFPU context before any DPFPU + instructions are executed. */ + portTASK_USES_DPFPU(); + +#endif /* defined(__DPFPU) */ + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +R_BSP_PRAGMA_STATIC_INLINE_ASM( prvRegTest1Implementation ) +void prvRegTest1Implementation( void ) +{ +R_BSP_ASM_BEGIN + + /* Put a known value in each register. */ + R_BSP_ASM( MOV.L #1, R1 ) + R_BSP_ASM( MOV.L #2, R2 ) + R_BSP_ASM( MOV.L #3, R3 ) + R_BSP_ASM( MOV.L #4, R4 ) + R_BSP_ASM( MOV.L #5, R5 ) + R_BSP_ASM( MOV.L #6, R6 ) + R_BSP_ASM( MOV.L #7, R7 ) + R_BSP_ASM( MOV.L #8, R8 ) + R_BSP_ASM( MOV.L #9, R9 ) + R_BSP_ASM( MOV.L #10, R10 ) + R_BSP_ASM( MOV.L #11, R11 ) + R_BSP_ASM( MOV.L #12, R12 ) + R_BSP_ASM( MOV.L #13, R13 ) + R_BSP_ASM( MOV.L #14, R14 ) + R_BSP_ASM( MOV.L #15, R15 ) + +#if defined(__DPFPU) + /* Put a known value in each DPFPU register. (DR0 is the same value as DR15.) */ + R_BSP_ASM( ITOD R1, DR1 ) + R_BSP_ASM( ITOD R2, DR2 ) + R_BSP_ASM( ITOD R3, DR3 ) + R_BSP_ASM( ITOD R4, DR4 ) + R_BSP_ASM( ITOD R5, DR5 ) + R_BSP_ASM( ITOD R6, DR6 ) + R_BSP_ASM( ITOD R7, DR7 ) + R_BSP_ASM( ITOD R8, DR8 ) + R_BSP_ASM( ITOD R9, DR9 ) + R_BSP_ASM( ITOD R10, DR10 ) + R_BSP_ASM( ITOD R11, DR11 ) + R_BSP_ASM( ITOD R12, DR12 ) + R_BSP_ASM( ITOD R13, DR13 ) + R_BSP_ASM( ITOD R14, DR14 ) + R_BSP_ASM( ITOD R15, DR15 ) + R_BSP_ASM( ITOD R15, DR0 ) +#endif /* defined(__DPFPU) */ + + /* Loop, checking each iteration that each register still contains the + expected value. */ +R_BSP_ASM_LAB(1:) /* TestLoop1: */ + + /* Push the registers that are going to get clobbered. */ + R_BSP_ASM( PUSHM R14-R15 ) + + /* Increment the loop counter to show this task is still getting CPU time. */ + R_BSP_ASM( MOV.L #_ulRegTest1LoopCounter, R14 ) + R_BSP_ASM( MOV.L [ R14 ], R15 ) + R_BSP_ASM( ADD #1, R15 ) + R_BSP_ASM( MOV.L R15, [ R14 ] ) + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + R_BSP_ASM( MOV.L #1, R14 ) + R_BSP_ASM( MOV.L #0872E0H, R15 ) + R_BSP_ASM( MOV.B R14, [R15] ) + R_BSP_ASM( NOP ) + R_BSP_ASM( NOP ) + + /* Restore the clobbered registers. */ + R_BSP_ASM( POPM R14-R15 ) + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + R_BSP_ASM( CMP #1, R1 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #2, R2 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #3, R3 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #4, R4 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #5, R5 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #6, R6 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #7, R7 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #8, R8 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #9, R9 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #10, R10 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #11, R11 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #12, R12 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #13, R13 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #14, R14 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #15, R15 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + +#if defined(__DPFPU) + /* Now compare each DPFPU register to ensure it still contains the value that was + set before this loop was entered. (DR0 is the same value as DR15.) */ + R_BSP_ASM( DCMPEQ DR0, DR15 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R1, DR0 ) + R_BSP_ASM( DCMPEQ DR1, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R2, DR0 ) + R_BSP_ASM( DCMPEQ DR2, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R3, DR0 ) + R_BSP_ASM( DCMPEQ DR3, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R4, DR0 ) + R_BSP_ASM( DCMPEQ DR4, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R5, DR0 ) + R_BSP_ASM( DCMPEQ DR5, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R6, DR0 ) + R_BSP_ASM( DCMPEQ DR6, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R7, DR0 ) + R_BSP_ASM( DCMPEQ DR7, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R8, DR0 ) + R_BSP_ASM( DCMPEQ DR8, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R9, DR0 ) + R_BSP_ASM( DCMPEQ DR9, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R10, DR0 ) + R_BSP_ASM( DCMPEQ DR10, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R11, DR0 ) + R_BSP_ASM( DCMPEQ DR11, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R12, DR0 ) + R_BSP_ASM( DCMPEQ DR12, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R13, DR0 ) + R_BSP_ASM( DCMPEQ DR13, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R14, DR0 ) + R_BSP_ASM( DCMPEQ DR14, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R15, DR0 ) + R_BSP_ASM( DCMPEQ DR15, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ +#endif /* defined(__DPFPU) */ + + /* All comparisons passed, start a new itteratio of this loop. */ + R_BSP_ASM( BRA.W R_BSP_ASM_LAB_PREV(1) ) /* BRA TestLoop1 */ + +R_BSP_ASM_LAB(11:) /* RegTest1Error: */ + /* A compare failed, just loop here so the loop counter stops incrementing + causing the check task to indicate the error. */ + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_PREV(11) ) /* BRA RegTest1Error */ + +R_BSP_ASM_END +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +R_BSP_PRAGMA_STATIC_INLINE_ASM( prvRegTest2Implementation ) +void prvRegTest2Implementation( void ) +{ +R_BSP_ASM_BEGIN + + /* Put a known value in each register. */ + R_BSP_ASM( MOV.L #10, R1 ) + R_BSP_ASM( MOV.L #20, R2 ) + R_BSP_ASM( MOV.L #30, R3 ) + R_BSP_ASM( MOV.L #40, R4 ) + R_BSP_ASM( MOV.L #50, R5 ) + R_BSP_ASM( MOV.L #60, R6 ) + R_BSP_ASM( MOV.L #70, R7 ) + R_BSP_ASM( MOV.L #80, R8 ) + R_BSP_ASM( MOV.L #90, R9 ) + R_BSP_ASM( MOV.L #100, R10 ) + R_BSP_ASM( MOV.L #110, R11 ) + R_BSP_ASM( MOV.L #120, R12 ) + R_BSP_ASM( MOV.L #130, R13 ) + R_BSP_ASM( MOV.L #140, R14 ) + R_BSP_ASM( MOV.L #150, R15 ) + +#if defined(__DPFPU) + /* Put a known value in each DPFPU register. (DR0 is the same value as DR15.) */ + R_BSP_ASM( ITOD R1, DR1 ) + R_BSP_ASM( ITOD R2, DR2 ) + R_BSP_ASM( ITOD R3, DR3 ) + R_BSP_ASM( ITOD R4, DR4 ) + R_BSP_ASM( ITOD R5, DR5 ) + R_BSP_ASM( ITOD R6, DR6 ) + R_BSP_ASM( ITOD R7, DR7 ) + R_BSP_ASM( ITOD R8, DR8 ) + R_BSP_ASM( ITOD R9, DR9 ) + R_BSP_ASM( ITOD R10, DR10 ) + R_BSP_ASM( ITOD R11, DR11 ) + R_BSP_ASM( ITOD R12, DR12 ) + R_BSP_ASM( ITOD R13, DR13 ) + R_BSP_ASM( ITOD R14, DR14 ) + R_BSP_ASM( ITOD R15, DR15 ) + R_BSP_ASM( ITOD R15, DR0 ) +#endif /* defined(__DPFPU) */ + + /* Loop, checking on each iteration that each register still contains the + expected value. */ +R_BSP_ASM_LAB(2:) /* TestLoop2: */ + + /* Push the registers that are going to get clobbered. */ + R_BSP_ASM( PUSHM R14-R15 ) + + /* Increment the loop counter to show this task is still getting CPU time. */ + R_BSP_ASM( MOV.L #_ulRegTest2LoopCounter, R14 ) + R_BSP_ASM( MOV.L [ R14 ], R15 ) + R_BSP_ASM( ADD #1, R15 ) + R_BSP_ASM( MOV.L R15, [ R14 ] ) + + /* Restore the clobbered registers. */ + R_BSP_ASM( POPM R14-R15 ) + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + R_BSP_ASM( CMP #10, R1 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #20, R2 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #30, R3 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #40, R4 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #50, R5 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #60, R6 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #70, R7 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #80, R8 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #90, R9 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #100, R10 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #110, R11 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #120, R12 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #130, R13 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #140, R14 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #150, R15 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + +#if defined(__DPFPU) + /* Now compare each DPFPU register to ensure it still contains the value that was + set before this loop was entered. (DR0 is the same value as DR15.) */ + R_BSP_ASM( DCMPEQ DR0, DR15 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R1, DR0 ) + R_BSP_ASM( DCMPEQ DR1, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R2, DR0 ) + R_BSP_ASM( DCMPEQ DR2, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R3, DR0 ) + R_BSP_ASM( DCMPEQ DR3, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R4, DR0 ) + R_BSP_ASM( DCMPEQ DR4, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R5, DR0 ) + R_BSP_ASM( DCMPEQ DR5, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R6, DR0 ) + R_BSP_ASM( DCMPEQ DR6, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R7, DR0 ) + R_BSP_ASM( DCMPEQ DR7, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R8, DR0 ) + R_BSP_ASM( DCMPEQ DR8, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R9, DR0 ) + R_BSP_ASM( DCMPEQ DR9, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R10, DR0 ) + R_BSP_ASM( DCMPEQ DR10, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R11, DR0 ) + R_BSP_ASM( DCMPEQ DR11, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R12, DR0 ) + R_BSP_ASM( DCMPEQ DR12, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R13, DR0 ) + R_BSP_ASM( DCMPEQ DR13, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R14, DR0 ) + R_BSP_ASM( DCMPEQ DR14, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R15, DR0 ) + R_BSP_ASM( DCMPEQ DR15, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ +#endif /* defined(__DPFPU) */ + + /* All comparisons passed, start a new itteratio of this loop. */ + R_BSP_ASM( BRA.W R_BSP_ASM_LAB_PREV(2) ) /* BRA TestLoop2 */ + +R_BSP_ASM_LAB(22:) /* RegTest2Error: */ + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_PREV(22) ) /* BRA RegTest2Error */ + +R_BSP_ASM_END +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c new file mode 100644 index 000000000..330530546 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/Full_Demo/serial.c @@ -0,0 +1,208 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program includes. */ +#include "serial.h" + +/* Renesas includes. */ +#include "platform.h" +#include "r_dtc_rx_if.h" +#include "r_sci_rx_if.h" +#include "r_byteq_if.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Characters received from the UART are stored in this queue, ready to be +received by the application. ***NOTE*** Using a queue in this way is very +convenient, but also very inefficient. It can be used here because characters +will only arrive slowly. In a higher bandwidth system a circular RAM buffer or +DMA should be used in place of this queue. */ +static QueueHandle_t xRxQueue = NULL; + +/* When a task calls vSerialPutString() its handle is stored in xSendingTask, +before being placed into the Blocked state (so does not use any CPU time) to +wait for the transmission to end. The task handle is then used from the UART +transmit end interrupt to remove the task from the Blocked state. */ +static TaskHandle_t xSendingTask = NULL; + +/* Callback function which is called from Renesas API's interrupt service routine. */ +void vSerialSciCallback( void *pvArgs ) +{ +sci_cb_args_t *pxArgs = (sci_cb_args_t *)pvArgs; + + /* Renesas API has a built-in queue but we will ignore it. If the queue is not + full, a received character is passed with SCI_EVT_RX_CHAR event. If the queue + is full, a received character is passed with SCI_EVT_RXBUF_OVFL event. */ + if( SCI_EVT_RX_CHAR == pxArgs->event || SCI_EVT_RXBUF_OVFL == pxArgs->event ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + configASSERT( xRxQueue ); + + /* Characters received from the UART are stored in this queue, ready to be + received by the application. ***NOTE*** Using a queue in this way is very + convenient, but also very inefficient. It can be used here because + characters will only arrive slowly. In a higher bandwidth system a circular + RAM buffer or DMA should be used in place of this queue. */ + xQueueSendFromISR( xRxQueue, &pxArgs->byte, &xHigherPriorityTaskWoken ); + + /* See http://www.freertos.org/xQueueOverwriteFromISR.html for information + on the semantics of this ISR. */ + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + /* Renesas API notifies the completion of transmission by SCI_EVT_TEI event. */ + else if( SCI_EVT_TEI == pxArgs->event ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + if( xSendingTask != NULL ) + { + /* A task is waiting for the end of the Tx, unblock it now. + http://www.freertos.org/vTaskNotifyGiveFromISR.html */ + vTaskNotifyGiveFromISR( xSendingTask, &xHigherPriorityTaskWoken ); + xSendingTask = NULL; + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + } +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + ( void ) ulWantedBaud; + ( void ) uxQueueLength; + + /* Characters received from the UART are stored in this queue, ready to be + received by the application. ***NOTE*** Using a queue in this way is very + convenient, but also very inefficient. It can be used here because + characters will only arrive slowly. In a higher bandwidth system a circular + RAM buffer or DMA should be used in place of this queue. */ + xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) ); + configASSERT( xRxQueue ); + + /* Set interrupt priority. (Other UART settings had been initialized in the + src/smc_gen/general/r_cg_hardware_setup.c.) */ + uint8_t ucInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + R_SCI_Control( xSerialSciHandle, SCI_CMD_SET_RXI_PRIORITY, ( void * ) &ucInterruptPriority ); + R_SCI_Control( xSerialSciHandle, SCI_CMD_SET_TXI_PRIORITY, ( void * ) &ucInterruptPriority ); + + /* Only one UART is supported, so it doesn't matter what is returned + here. */ + return 0; +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength ) +{ +const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 5000 ); + + /* Only one port is supported. */ + ( void ) pxPort; + + /* Don't send the string unless the previous string has been sent. */ + if( ( xSendingTask == NULL ) && ( usStringLength > 0 ) ) + { + /* Ensure the calling task's notification state is not already + pending. */ + xTaskNotifyStateClear( NULL ); + + /* Store the handle of the transmitting task. This is used to unblock + the task when the transmission has completed. */ + xSendingTask = xTaskGetCurrentTaskHandle(); + + /* Send the string using the Renesas API with a workaround. */ + if( usStringLength > 1 ) + { + /* Set up Data Transfer Control. */ + dtc_cmd_arg_t xSerialTxDtcArg; + dtc_transfer_data_cfg_t xSerialTxDtcConfig; + + xSerialTxDtcArg.act_src = U_DTC_UART_CLI_TX_ACT; + xSerialTxDtcConfig.transfer_mode = DTC_TRANSFER_MODE_NORMAL; + xSerialTxDtcConfig.data_size = DTC_DATA_SIZE_BYTE; + xSerialTxDtcConfig.src_addr_mode = DTC_SRC_ADDR_INCR; + xSerialTxDtcConfig.dest_addr_mode = DTC_DES_ADDR_FIXED; + xSerialTxDtcConfig.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + xSerialTxDtcConfig.repeat_block_side = DTC_REPEAT_BLOCK_SOURCE; + xSerialTxDtcConfig.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + xSerialTxDtcConfig.chain_transfer_mode = (dtc_chain_transfer_mode_t)0; + xSerialTxDtcConfig.source_addr = ( uint32_t ) pcString; + xSerialTxDtcConfig.dest_addr = ( uint32_t ) &U_DTC_UART_CLI_TX_DR; + xSerialTxDtcConfig.transfer_count = ( uint32_t ) usStringLength - 1; + xSerialTxDtcArg.chain_transfer_nr = 0; + xSerialTxDtcArg.p_transfer_data = &xSerialTxDtcInfo; + xSerialTxDtcArg.p_data_cfg = &xSerialTxDtcConfig; + + R_DTC_Create( xSerialTxDtcArg.act_src, &xSerialTxDtcInfo, &xSerialTxDtcConfig, 0 ); + R_DTC_Control( DTC_CMD_ACT_SRC_ENABLE, NULL, &xSerialTxDtcArg ); + R_SCI_Send( xSerialSciHandle, ( uint8_t * ) (pcString + usStringLength - 1), 1 ); + } + else + { + R_SCI_Send( xSerialSciHandle, ( uint8_t * ) pcString, 1 ); + } + + /* Wait in the Blocked state (so not using any CPU time) until the + transmission has completed. */ + ulTaskNotifyTake( pdTRUE, xMaxBlockTime ); + + /* A breakpoint can be set here for debugging. */ + nop(); + } +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime ) +{ + /* Only one UART is supported. */ + ( void ) pxPort; + + /* Return a received character, if any are available. Otherwise block to + wait for a character. */ + return xQueueReceive( xRxQueue, pcRxedChar, xBlockTime ); +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime ) +{ + /* Just mapped to vSerialPutString() so the block time is not used. */ + ( void ) xBlockTime; + + vSerialPutString( pxPort, &cOutChar, sizeof( cOutChar ) ); + return pdPASS; +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_main.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_main.h new file mode 100644 index 000000000..caa38e9d4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_main.h @@ -0,0 +1,13 @@ +#ifndef DEMO_MAIN_H +#define DEMO_MAIN_H + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/* demo_main() is placed in the src/frtos_startup/freertos_start.c and it calls +main_blinky() or main_full() according to the mainCREATE_SIMPLE_BLINKY_DEMO_ONLY +setting. */ +extern void demo_main( void ); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h new file mode 100644 index 000000000..f3a19fa11 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/FreeRTOS_Demo/demo_specific_io.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef LED_IO_H +#define LED_IO_H + + #define EnvisionRX72N + +/* Board support settings. */ + + #ifdef EnvisionRX72N + + /* R5F572NDHDFB 144pin LQFP */ + + /* General Values */ + #define LED_ON (0) + #define LED_OFF (1) + #define SW_PUSH (0) + #define SW_RELEASE (1) + + /* Switches (and its notation in the User's Manual) */ + #define SW1/*(SW2)*/ (PORT0.PIDR.BIT.B7) + #define U_GPIO_PIN_SW1/*(SW2)*/ (GPIO_PORT_0_PIN_7) + + /* LED port settings (and its notation in the User's Manual) */ + #define LED0/*(LED2)*/ (PORT4.PODR.BIT.B0) + #define U_GPIO_PIN_LED0/*(LED2)*/ (GPIO_PORT_4_PIN_0) + + /* FreeRTOS CLI Command Console */ + #define U_SCI_UART_CLI_PINSET() R_SCI_PinSet_SCI2() + #define U_SCI_UART_CLI_SCI_CH (SCI_CH2) + #define U_DTC_UART_CLI_TX_ACT ((dtc_activation_source_t)VECT(SCI2,TXI2)) + #define U_DTC_UART_CLI_TX_DR (SCI2.TDR) + + #endif /* EnvisionRX72N */ + + #ifndef LED0 + #error The hardware platform is not defined + #endif + +/* Board Support Data Structures. */ + +#include "r_sci_rx_if.h" +#include "r_dtc_rx_if.h" + +extern sci_hdl_t xSerialSciHandle; +extern dtc_transfer_data_t xSerialTxDtcInfo; + +/* Board Support Callback Functions. */ + +extern void vSerialSciCallback( void *pvArgs ); + +#endif /* LED_IO_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h new file mode 100644 index 000000000..0b8a0ea27 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_config/FreeRTOSConfig.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ (BSP_ICLK_HZ) +#define configPERIPHERAL_CLOCK_HZ (BSP_PCLKB_HZ) +#define configTICK_RATE_HZ (( TickType_t ) 1000) +#define configMINIMAL_STACK_SIZE (( unsigned short ) 170) +#define configTOTAL_HEAP_SIZE_N (60) +#define configTOTAL_HEAP_SIZE (( size_t ) ( configTOTAL_HEAP_SIZE_N * 1024 )) +#define configMAX_TASK_NAME_LEN (12) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES (7) +#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_TASK_NOTIFICATIONS 1 +#define configRECORD_STACK_HIGH_ADDRESS 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + +/* Dynamic allocation and static allocation. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 0 + +/* Run time stats gathering definitions. */ +unsigned long ulGetRunTimeCounterValue( void ); +void vConfigureTimerForRunTimeStats( void ); +#define configGENERATE_RUN_TIME_STATS 0 +//#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() +//#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (6) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will +be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before +making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then +tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has +no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care +of any DPFPU context (even if DPFPU registers are used). */ +#define configUSE_TASK_DPFPU_SUPPORT 1 + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() + +/* The buffer into which output generated by FreeRTOS+CLI is placed. This must +be at least big enough to contain the output of the task-stats command, as the +example implementation does not include buffer overlow checking. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 3500 +#define configINCLUDE_QUERY_HEAP_COMMAND 1 + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY (( configMAX_PRIORITIES - 3 )) +#define bktSECONDARY_PRIORITY (( configMAX_PRIORITIES - 4 )) +#define intqHIGHER_PRIORITY (( configMAX_PRIORITIES - 3 )) + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be used. */ +#define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_skeleton/task_function.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_skeleton/task_function.h new file mode 100644 index 000000000..c25944146 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_skeleton/task_function.h @@ -0,0 +1,23 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef TASK_FUNCTION_H_ +#define TASK_FUNCTION_H_ + +#endif /* TASK_FUNCTION_H_ */ \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_object_init.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_object_init.c new file mode 100644 index 000000000..829831d0f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_object_init.c @@ -0,0 +1,80 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name : freertos_object_init.c + * Version : 1.0 + * Description : + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 07.12.2018 1.00 First Release + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "FreeRTOS.h" +#include "freertos_start.h" +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Kernel_Object_init (void); +void Object_init_manual (void); +/*********************************************************************************************************************** + * Function Name: Kernel_Object_init + * Description : This function initializes FreeRTOS objects. + * Arguments : None. + * Return Value : None. + **********************************************************************************************************************/ +void Kernel_Object_init (void) +{ + /************** task creation ****************************/ + + /************** semaphore creation ***********************/ + + /************** queue creation ***************************/ + + /************** software time creation **************************/ + + /************** event groups creation ********************/ + + /************** stream buffer creation *************************/ + + /************** message buffer creation *********************/ + +} /* End of function Kernel_Object_init()*/ + +/*********************************************************************************************************************** + * Function Name : Object_init_manual + * Description : This function re-initializes FreeRTOS objects and should be called at runtime. + * Arguments : None. + * Return value : None. + **********************************************************************************************************************/ +void Object_init_manual (void) +{ + /************** task creation ****************************/ +} /* End of function Object_init_manual()*/ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_start.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_start.c new file mode 100644 index 000000000..25a9af682 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_start.c @@ -0,0 +1,483 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : freertos_start.c +* Version : 1.0 +* Description : Contains FreeRTOS user-defined functions. +******************************************************************************/ +/***************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2016 1.00 First Release +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" +#include "freertos_start.h" +#include "demo_main.h" +#include "demo_specific_io.h" + +#if (BSP_CFG_RTOS_USED == 1) + +#if (RTOS_USB_SUPPORT == 1) +#include "r_usb_basic_if.h" +#include "r_usb_cstd_rtos.h" +#endif + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/************* semaphore initialization *****************/ + +/****************************************************************************** +Exported global variables (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ + +/* FreeRTOS's system timer. */ +void vApplicationSetupTimerInterrupt(void); + +/* Hook functions used by FreeRTOS. */ +void vAssertCalled(void); +void vApplicationIdleHook(void); +void vApplicationTickHook(void); +void vApplicationMallocFailedHook(void); +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName); + +/* FreeRTOS's processing before start the kernel. */ +void Processing_Before_Start_Kernel(void); + +/* Main task. */ +extern void main_task(void *pvParameters); + + +/****************************************************************************** +* Function Name: vApplicationSetupTimerInterrupt +* Description : Initialize system timer for FreeRTOS with tick interrupt 1ms. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationSetupTimerInterrupt(void) +{ + /* CMT channel 0 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 0) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Stop counter. */ + CMT.CMSTR0.BIT.STR0 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT0.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT0, CMI0) = 0; + + /* Enable the interrupt. */ + IEN(CMT0, CMI0) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 0. */ + CMT.CMSTR0.BIT.STR0 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 0) */ + + /* CMT channel 1 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 1) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 1. */ + MSTP( CMT1 ) = 0; + + /* Stop counter. */ + CMT.CMSTR0.BIT.STR1 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT1.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT1.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT1.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT1, CMI1) = 0; + + /* Enable the interrupt. */ + IEN(CMT1, CMI1) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT1, CMI1) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 1. */ + CMT.CMSTR0.BIT.STR1 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 1) */ + + /* CMT channel 2 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 2) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 2. */ + MSTP( CMT2 ) = 0; + + /* Stop counter. */ + CMT.CMSTR1.BIT.STR2 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT2.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT2.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT2, CMI2) = 0; + + /* Enable the interrupt. */ + IEN(CMT2, CMI2) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT2, CMI2) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 2. */ + CMT.CMSTR1.BIT.STR2 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 2) */ + + /* CMT channel 3 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 3) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 3. */ + MSTP( CMT3 ) = 0; + + /* Stop counter. */ + CMT.CMSTR1.BIT.STR3 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT3.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT3.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT3.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT3, CMI3) = 0; + + /* Enable the interrupt. */ + IEN(CMT3, CMI3) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT3, CMI3) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 3. */ + CMT.CMSTR1.BIT.STR3 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 3) */ + +} /* End of function vApplicationSetupTimerInterrupt() */ + +/****************************************************************************** +* Function Name: vAssertCalled +* Description : This function is used to validate the input parameters. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vAssertCalled(void) +{ + volatile unsigned long ul = 0; + + taskENTER_CRITICAL(); + { + /* Use the debugger to set ul to a non-zero value in order to step out + of this function to determine why it was called. */ + while( 0 == ul ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); + +} /* End of function vAssertCalled() */ + +/****************************************************************************** +* Function Name: vApplicationIdleHook +* Description : This function will be called on each cycle of the idle task. +* NOTE: vApplicationIdleHook() MUST NOT CALL A FUNCTION +* THAT MIGHT BLOCK UNDER ANY CIRCUMSTANCES. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationIdleHook(void) +{ + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; + +} /* End of function vApplicationIdleHook() */ + +/****************************************************************************** +* Function Name: vApplicationTickHook +* Description : This function will be called every tick interrupt. +* NOTE: vApplicationTickHook() EXECUTES FROM WITHIN AN ISR, +* SO MUST BE VERY SHORT AND NOT USE MUCH STACK. +* IN ADDITION, NOT CALL ANY APIs WITHOUT "FromISR" OR +* "FROM_ISR" AT THE END. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationTickHook(void) +{ + /* The tick hook is not used by the blinky demo, but is by the full demo. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif + +} /* End of function vApplicationTickHook() */ + +/****************************************************************************** +* Function Name: vApplicationMallocFailedHook +* Description : This function is to capture the failure while +* memory allocation. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationMallocFailedHook(void) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); + + taskDISABLE_INTERRUPTS(); + for( ; ; ) + { + /* Loop here */ + }; + +} /* End of function vApplicationMallocFailedHook() */ + +/****************************************************************************** +* Function Name: vApplicationStackOverflowHook +* Description : Hook function is to capture the failure when the stack size +* is insufficient for processing. +* Arguments : pxTask - +* Task handler +* pcTaskName - +* Pointer of where to store the task's name +* Return Value : None. +******************************************************************************/ +void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); + + taskDISABLE_INTERRUPTS(); + for( ; ; ) + { + /* Loop here */ + }; + +} /* End of function vApplicationStackOverflowHook() */ + +/****************************************************************************** +* Function Name : Processing_Before_Start_Kernel +* Description : Create a main task, FreeRTOS's objects (e.g. mailbox, task, +* semaphore, mutex...) if required. +* Arguments : None. +* Return value : None. +******************************************************************************/ +void Processing_Before_Start_Kernel(void) +{ +#if 0 /* Generated Renesas Code */ + + BaseType_t ret; + + /************** semaphore creation ***********************/ + + + + /************** mutex creation ***************************/ + + + /************** queues creation **************************/ + + + /************** event groups creation ********************/ + + + /************** mailbox creation *************************/ + + + /************** memory pool creation *********************/ + + /** USB RTOS Configuration **/ +#if (RTOS_USB_SUPPORT == 1) + usb_rtos_err_t err = usb_rtos_configuration(); + if (UsbRtos_Success != err) + { + while(1) + { + /** Failure of UsbRtos Configuration **/ + } + } +#endif + + Kernel_Object_init(); + + /************** task creation ****************************/ + /* Main task. */ + ret = xTaskCreate(main_task, "MAIN_TASK", 512, NULL, 3, NULL); + if (pdPASS != ret) + { + while(1) + { + /* Failed! Task can not be created. */ + } + } + +#else /* Run FreeRTOS Demo */ + + demo_main(); + +#endif + +} /* End of function Processing_Before_Start_Kernel() */ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +void demo_main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + /* Should never get reached. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Turn on LED0 at start. (The system initialization had been done in the + src/smc_gen/general/r_cg_hardware_setup.c.) */ + LED0 = LED_ON; +} +/*-----------------------------------------------------------*/ + +#endif /* (BSP_CFG_RTOS_USED == 1) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_start.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_start.h new file mode 100644 index 000000000..f91a1efb7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/frtos_startup/freertos_start.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : freertos_start.h +* Version : 1.0 +* Description : FreeRTOS's user-defined functions header file. +******************************************************************************/ +/***************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2016 1.00 First Release +******************************************************************************/ + +#ifndef FREERTOS_START_H_ +#define FREERTOS_START_H_ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* USB FIT module support macro */ +#define RTOS_USB_SUPPORT 0 + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global variables +******************************************************************************/ +/************* semaphore handler *****************/ + + + +/************* mutex handler *********************/ + + +/************** queues handler *******************/ + + +/************** event groups handler *************/ + + +/************** mailbox handler ******************/ + + +/************** memory pool handler **************/ + + +/************** task handler *********************/ + + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +extern void Processing_Before_Start_Kernel(void); +extern void Kernel_Object_init(void); + +#endif /* FREERTOS_START_H_ */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_hardware_setup.c new file mode 100644 index 000000000..094ae6dd4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_hardware_setup.c @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : Initialization file for code generation configurations. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_cgc.h" +#include "r_smc_interrupt.h" +/* Start user code for include. Do not edit comment generated here */ +#include "r_gpio_rx_if.h" +#include "r_sci_rx_pinset.h" +#include "r_sci_rx_if.h" +#include "r_dtc_rx_if.h" +#include "demo_specific_io.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +/* Board Support Data Structures. */ +sci_hdl_t xSerialSciHandle; +dtc_transfer_data_t xSerialTxDtcInfo; + +/* Workaround to execute FIT Board Support Settings */ +void R_CG_Config_Create(void); +void R_FIT_Board_Support_Settings(void); +void R_Systeminit(void) +{ + R_CG_Config_Create(); + R_FIT_Board_Support_Settings(); +} +#define R_Systeminit R_CG_Config_Create + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_undefined_exception +* Description : This function is undefined interrupt service routine +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void r_undefined_exception(void) +{ + /* Start user code for r_undefined_exception. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every configuration +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50BU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Write 0 to the target bits in the POECR2 registers */ + POE3.POECR2.WORD = 0x0000U; + + /* Initialize clocks settings */ + R_CGC_Create(); + + /* Register undefined interrupt */ + R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} + +/* Start user code for adding. Do not edit comment generated here */ + +void R_FIT_Board_Support_Settings(void) +{ + /* Do not call any functions which enables generating any interrupt requests. */ + + /* GPIO for LED */ + R_GPIO_PinWrite(U_GPIO_PIN_LED0, (gpio_level_t)LED_OFF); // for the initial level after input --> output + R_GPIO_PinDirectionSet(U_GPIO_PIN_LED0, GPIO_DIRECTION_OUTPUT); + + /* GPIO for SW */ + R_GPIO_PinDirectionSet(U_GPIO_PIN_SW1, GPIO_DIRECTION_INPUT ); + + /* FreeRTOS CLI Command Console */ + U_SCI_UART_CLI_PINSET(); + sci_cfg_t xSerialSciConfig; + xSerialSciConfig.async.baud_rate = 115200; + xSerialSciConfig.async.clk_src = SCI_CLK_INT; + xSerialSciConfig.async.data_size = SCI_DATA_8BIT; + xSerialSciConfig.async.parity_en = SCI_PARITY_OFF; + xSerialSciConfig.async.parity_type = SCI_EVEN_PARITY; + xSerialSciConfig.async.stop_bits = SCI_STOPBITS_1; + xSerialSciConfig.async.int_priority = 1; /* lowest at first. */ + R_SCI_Open(U_SCI_UART_CLI_SCI_CH, SCI_MODE_ASYNC, &xSerialSciConfig, vSerialSciCallback, &xSerialSciHandle); + R_DTC_Open(); + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); +} + +/* End user code. Do not edit comment generated here */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_macrodriver.h new file mode 100644 index 000000000..723c73e67 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_macrodriver.h @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : Macro header file for code generation. +***********************************************************************************************************************/ + +#ifndef MACRODRIVER_H +#define MACRODRIVER_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "platform.h" +#include "r_smc_interrupt.h" +#include "intrinsics.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Systeminit(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_userdefine.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_userdefine.h new file mode 100644 index 000000000..660ad8706 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_cg_userdefine.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : User header file for code generation. +***********************************************************************************************************************/ + +#ifndef CG_USER_DEF_H +#define CG_USER_DEF_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* Start user code for register. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Start user code for macro define. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Start user code for type define. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc.c new file mode 100644 index 000000000..9b97e088f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc.c @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc.c +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : This file implements CGC setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_CGC_Create(void) +{ + /* Set CLKOUT25M pin */ + MPC.P56PFS.BYTE = 0x2AU; + PORT5.DSCR2.BYTE |= 0x40U; + PORT5.PMR.BYTE |= 0x40U; + + R_CGC_Create_UserInit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc.h new file mode 100644 index 000000000..0a594c2a8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc.h @@ -0,0 +1,174 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc.h +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : CGC setting header file. +***********************************************************************************************************************/ + +#ifndef SMC_CGC_H +#define SMC_CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PLL Clock Source Select (PLLSRCSEL) */ +#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */ +#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */ +#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */ +#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Clock Oscillator Forced Oscillation (MOFXIN) */ +#define _00_CGC_MAINOSC_NOT_CONTROLLED (0x00U) /* Oscillator is not controlled by this bit */ +#define _01_CGC_MAINOSC_FORCE_OSCILLATED (0x01U) /* The main clock oscillator is forcedly oscillated */ +/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */ +#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */ +#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */ +#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */ +#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + PPLL Control Register (PPLLCR) +*/ +/* PPLL Input Pulse Frequency Division Ratio Select (PPLIDIV[1:0]) */ +#define _0000_CGC_PPLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PPLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PPLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PPLL Frequency Multiplier Setting (PPLSTC[5:0]) */ +#define _1300_CGC_PPLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PPLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PPLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PPLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PPLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PPLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PPLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PPLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PPLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PPLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PPLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PPLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PPLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PPLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PPLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PPLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PPLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PPLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PPLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PPLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PPLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PPLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PPLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PPLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PPLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PPLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PPLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PPLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PPLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PPLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PPLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PPLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PPLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PPLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PPLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PPLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PPLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PPLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PPLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PPLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PPLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); +void R_CGC_Create_UserInit(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc_user.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc_user.c new file mode 100644 index 000000000..378321ff7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_cgc_user.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc_user.c +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : This file implements CGC setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create_UserInit +* Description : This function adds user code after initializing CGC +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_CGC_Create_UserInit(void) +{ + /* Start user code for user init. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_entry.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_entry.h new file mode 100644 index 000000000..e91c0784e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_entry.h @@ -0,0 +1,53 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_entry.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : SMC platform header file. +***********************************************************************************************************************/ + +#ifndef SMC_ENTRY_H +#define SMC_ENTRY_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_interrupt.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_interrupt.c new file mode 100644 index 000000000..59f2a4533 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_interrupt.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_interrupt.c +* Version : 1.1.0 +* Device(s) : R5F572NNHxFB +* Description : This file implements interrupt setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_interrupt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Interrupt_Create +* Description : This function Used to set the fast interrupt or group interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Interrupt_Create(void) +{ + /* No fast interrupt and group settings have been configured in the Interrupts tab. */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_interrupt.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_interrupt.h new file mode 100644 index 000000000..07913ebcc --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/general/r_smc_interrupt.h @@ -0,0 +1,295 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_interrupt.h +* Version : 1.1.0 +* Device(s) : R5F572NNHxFB +* Description : This file implements interrupt setting. +***********************************************************************************************************************/ + +#ifndef SMC_INTERRUPT_H +#define SMC_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* Priority level of interrupt source. + * These macro definitions are used to set the IPR register directly + */ +#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (disabled) */ +#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR (0) + +/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab + * Please do not modify this file manually + */ +#define ICU_BSC_BUSERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPIE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RAM_RAMERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_FCU_FIFERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_FCU_FRDYI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_SWINT2_PRIORITY (_01_ICU_PRIORITY_LEVEL1) +#define ICU_ICU_SWINT_PRIORITY (_01_ICU_PRIORITY_LEVEL1) +#define ICU_CMT0_CMI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT1_CMI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_CMWI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_CMWI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_D0FIFO0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_D1FIFO0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI0_SPRI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI0_SPTI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI1_SPRI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI1_SPTI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_QSPI_SPRI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_QSPI_SPTI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SDHI_SBFAI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MMCIF_MBFAI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE0_SSITXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE0_SSIRXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE1_SSIRTI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC1_RXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC1_TXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC0_RXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC0_TXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC2_RXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC2_TXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI0_RXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI0_TXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI1_RXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI1_TXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI2_RXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI2_TXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ13_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ14_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ15_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI3_RXI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI3_TXI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI4_RXI4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI4_TXI4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI5_RXI5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI5_TXI5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI6_RXI6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI6_TXI6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_LVD1_LVD1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_LVD2_LVD2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_USBR0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_ALM_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_PRD_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_IWDT_IWUNI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_WDT_WUNI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PDC_PCDFI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI7_RXI7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI7_TXI7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI8_RXI8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI8_TXI8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI9_RXI9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI9_TXI9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI10_RXI10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI10_TXI10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI2_SPRI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI2_SPTI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPAL0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPAL1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI11_RXI11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI11_TXI11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI12_RXI12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI12_TXI12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC2I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC3I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC74I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_OST_OSTDI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EXDMAC_EXDMAC0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EXDMAC_EXDMAC1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT2_CMI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT3_CMI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0C_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0D_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TCI0V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TGI1B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TCI1V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TCI1U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TGI2A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TGI2B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TCI2V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TCI2U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TGI1A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3C_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_CMIA0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_CMIB0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_OVI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_CMIA1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_CMIB1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_OVI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_CMIA2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_CMIB2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_OVI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_CMIA3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_CMIB3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_OVI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3D_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TCI3V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TGI4A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TGI4B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TCI4V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TCI4U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TGI5A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TGI5B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TCI5V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TCI5U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_IC0I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_IC1I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_OC0I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_OC1I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_IC0I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_IC1I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_OC0I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_OC1I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_CUP_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_RXF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_TXF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_RXM0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_TXM0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_RXF1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_TXF1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_RXM1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_TXM1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_USBI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12ADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12GBADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12GCADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12ADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12GBADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12GCADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ELC_ELSR18I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ELC_ELSR19I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_PROC_BUSY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_ROMOK_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_LONG_PLG_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_TEST_BUSY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_RDRDY0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_RDRDY1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB205_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB206_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB207_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TGIA1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIA0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIB0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIC0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGID0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TCIV0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TGIB1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TCIV1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TCIU1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TGIA2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TGIB2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TCIV2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TCIU2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIA3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIB3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIC3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGID3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TCIV3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIA4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIB4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIC4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGID4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TCIV4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIU5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIV5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIW5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIA6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIB6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIC6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGID6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TCIV6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIA7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIB7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIC7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGID7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TCIV7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIA8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIB8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIC8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGID8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TCIV8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EPTPC_IPLS_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PMGI0_PMGI0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PMGI1_PMGI1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIA_INTA254_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIA_INTA255_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Interrupt_Create(void); +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c new file mode 100644 index 000000000..0620d7fe2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c @@ -0,0 +1,414 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.c +* Device(s) : RX +* H/W Platform : GENERIC_RX72N +* Description : Defines the initialization routines used each time the MCU is restarted. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* I/O Register and board definitions */ +#include "platform.h" +#if BSP_CFG_CONFIGURATOR_SELECT == 1 +#include "r_cg_macrodriver.h" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +R_BSP_PRAGMA_UNPACK +typedef struct bsp_bsc { + union { + uint32_t u_long; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13( + uint32_t prerr:1, + uint32_t :1, + uint32_t rpstop:1, + uint32_t :10, + uint32_t pr5sel:3, + uint32_t :1, + uint32_t pr4sel:3, + uint32_t :1, + uint32_t pr3sel:3, + uint32_t :1, + uint32_t pr2sel:3, + uint32_t :1, + uint32_t pr1sel:3 + ) bit; + } ebmapcr; +} st_bsp_bsc_t; +R_BSP_PRAGMA_PACKOPTION + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +/* ROM cache configuration function declaration */ +#if BSP_CFG_ROM_CACHE_ENABLE == 1 +static void rom_cache_function_set(void); +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 +static void rom_cache_noncacheable_area0_set(void); +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 +static void rom_cache_noncacheable_area1_set(void); +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/* MCU I/O port configuration function declaration */ +static void output_ports_configure(void); + +/* Interrupt configuration function declaration */ +static void interrupts_configure(void); + +/* MCU peripheral module configuration function declaration */ +static void peripheral_modules_enable(void); + +/* ADC initial configuration function declaration */ +static void bsp_adc_initial_configure(void); + +/* BUS initial configuration function declaration */ +static void bsp_bsc_initial_configure(void); + +/*********************************************************************************************************************** +* Function name: hardware_setup +* Description : Contains setup functions called at device restart +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void hardware_setup(void) +{ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +#if BSP_CFG_ROM_CACHE_ENABLE == 1 + /* Initialize ROM cache function */ + rom_cache_function_set(); +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + + output_ports_configure(); + interrupts_configure(); + peripheral_modules_enable(); + bsp_non_existent_port_init(); + bsp_adc_initial_configure(); + bsp_bsc_initial_configure(); +} /* End of function hardware_setup() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +#if BSP_CFG_ROM_CACHE_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_function_set +* Description : Configures the rom cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_function_set (void) +{ +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 + rom_cache_noncacheable_area0_set(); +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ + +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 + rom_cache_noncacheable_area1_set(); +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ + + /* Invalidates the contents of the ROM cache. */ + FLASH.ROMCIV.WORD = 0x0001; + + /* Enables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0001; +} /* End of function rom_cache_function_set() */ + +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_noncacheable_area0_set +* Description : Configures non-cacheable area 0 of the ROM cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_noncacheable_area0_set (void) +{ + /* Used to specify the value written to the NCRC0 register. */ + uint32_t tmp_ncrc = 0; + + /* Disables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0000; + + /* Makes settings to the NCRG0 register. */ +#if (BSP_CFG_NONCACHEABLE_AREA0_ADDR >= 0xFFC00000) \ + && ((BSP_CFG_NONCACHEABLE_AREA0_ADDR & 0x0000000F) == 0x00000000) + FLASH.NCRG0 = BSP_CFG_NONCACHEABLE_AREA0_ADDR; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA0_ADDR in r_bsp_config.h" +#endif + + /* Sets the value of the NCSZ bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x0 + /* Do nothing since NCRC0 bits should be 0. */ +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x1 + tmp_ncrc |= 0x00000010; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x2 + tmp_ncrc |= 0x00000030; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x3 + tmp_ncrc |= 0x00000070; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x4 + tmp_ncrc |= 0x000000F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x5 + tmp_ncrc |= 0x000001F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x6 + tmp_ncrc |= 0x000003F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x7 + tmp_ncrc |= 0x000007F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x8 + tmp_ncrc |= 0x00000FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x9 + tmp_ncrc |= 0x00001FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xA + tmp_ncrc |= 0x00003FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xB + tmp_ncrc |= 0x00007FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xC + tmp_ncrc |= 0x0000FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xD + tmp_ncrc |= 0x0001FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xE + tmp_ncrc |= 0x0003FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xF + tmp_ncrc |= 0x0007FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x10 + tmp_ncrc |= 0x000FFFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x11 + tmp_ncrc |= 0x001FFFF0; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA0_SIZE in r_bsp_config.h" +#endif + + /* Sets the value of the NC1E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE == 1 + tmp_ncrc |= 0x00000002; +#endif + + /* Sets the value of the NC2E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE == 1 + tmp_ncrc |= 0x00000004; +#endif + + /* Sets the value of the NC3E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE == 1 + tmp_ncrc |= 0x00000008; +#endif + + /* Makes settings to the NCRC0 register. */ + FLASH.NCRC0.LONG = tmp_ncrc; +} /* End of function rom_cache_noncacheable_area0_set() */ +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ + +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_noncacheable_area1_set +* Description : Configures non-cacheable area 1 of the ROM cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_noncacheable_area1_set (void) +{ + /* Used to specify the value written to the NCRC1 register. */ + uint32_t tmp_ncrc = 0; + + /* Disables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0000; + + /* Makes settings to the NCRG1 register. */ +#if (BSP_CFG_NONCACHEABLE_AREA1_ADDR >= 0xFFC00000) \ + && ((BSP_CFG_NONCACHEABLE_AREA1_ADDR & 0x0000000F) == 0x00000000) + FLASH.NCRG1 = BSP_CFG_NONCACHEABLE_AREA1_ADDR; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA1_ADDR in r_bsp_config.h" +#endif + + /* Sets the value of the NCSZ bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x0 + /* Do nothing since NCRC1 bits should be 0. */ +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x1 + tmp_ncrc |= 0x00000010; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x2 + tmp_ncrc |= 0x00000030; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x3 + tmp_ncrc |= 0x00000070; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x4 + tmp_ncrc |= 0x000000F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x5 + tmp_ncrc |= 0x000001F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x6 + tmp_ncrc |= 0x000003F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x7 + tmp_ncrc |= 0x000007F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x8 + tmp_ncrc |= 0x00000FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x9 + tmp_ncrc |= 0x00001FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xA + tmp_ncrc |= 0x00003FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xB + tmp_ncrc |= 0x00007FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xC + tmp_ncrc |= 0x0000FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xD + tmp_ncrc |= 0x0001FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xE + tmp_ncrc |= 0x0003FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xF + tmp_ncrc |= 0x0007FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x10 + tmp_ncrc |= 0x000FFFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x11 + tmp_ncrc |= 0x001FFFF0; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA1_SIZE in r_bsp_config.h" +#endif + + /* Sets the value of the NC1E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE == 1 + tmp_ncrc |= 0x00000002; +#endif + + /* Sets the value of the NC2E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE == 1 + tmp_ncrc |= 0x00000004; +#endif + + /* Sets the value of the NC3E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE == 1 + tmp_ncrc |= 0x00000008; +#endif + + /* Makes settings to the NCRC1 register. */ + FLASH.NCRC1.LONG = tmp_ncrc; +} /* End of function rom_cache_noncacheable_area1_set() */ +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function name: output_ports_configure +* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void output_ports_configure(void) +{ + /* Add code here to setup additional output ports */ + R_BSP_NOP(); +} /* End of function output_ports_configure() */ + +/*********************************************************************************************************************** +* Function name: interrupts_configure +* Description : Configures interrupts used +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void interrupts_configure(void) +{ + /* Add code here to setup additional interrupts */ + R_BSP_NOP(); +} /* End of function interrupts_configure() */ + +/*********************************************************************************************************************** +* Function name: peripheral_modules_enable +* Description : Enables and configures peripheral devices on the MCU +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void peripheral_modules_enable(void) +{ + /* Add code here to enable peripherals used by the application */ +#if BSP_CFG_CONFIGURATOR_SELECT == 1 + /* Smart Configurator initialization function */ + R_Systeminit(); +#endif +} /* End of function peripheral_modules_enable() */ + +/*********************************************************************************************************************** +* Function name: bsp_adc_initial_configure +* Description : Configures the ADC initial settings +* Arguments : none +* Return value : none +* Note : This function should be called when the PSW.I bit is 0 (interrupt disabled). +* This function should be called when the ADCSR.ADST bit is 0. +***********************************************************************************************************************/ +static void bsp_adc_initial_configure(void) +{ + uint32_t tmp_mstp; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Store the value of the MSTPCR. */ + tmp_mstp = MSTP(S12AD1); + + /* Release from the module-stop state */ + MSTP(S12AD1) = 0; + + /* Writing to the A/D conversion time setting register is enabled. */ + S12AD1.ADSAMPR.BYTE = 0x03; + + /* Sets conversion time for middle-speed for S12AD unit 1. */ + S12AD1.ADSAM.WORD = 0x0020; + + /* Writing to the A/D conversion time setting register is disabled. */ + S12AD1.ADSAMPR.BYTE = 0x02; + + /* Restore the value of the MSTPCR. */ + MSTP(S12AD1) = tmp_mstp; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_adc_initial_configure() */ + +/*********************************************************************************************************************** +* Function name: bsp_bsc_initial_configure +* Description : Configures the BUS initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_bsc_initial_configure(void) +{ + st_bsp_bsc_t bsp_bsc; + + /* Setting priority when bus right request contention occurs. */ + bsp_bsc.ebmapcr.u_long = BSC.EBMAPCR.LONG; + bsp_bsc.ebmapcr.bit.pr1sel = BSP_CFG_EBMAPCR_1ST_PRIORITY; + bsp_bsc.ebmapcr.bit.pr2sel = BSP_CFG_EBMAPCR_2ND_PRIORITY; + bsp_bsc.ebmapcr.bit.pr3sel = BSP_CFG_EBMAPCR_3RD_PRIORITY; + bsp_bsc.ebmapcr.bit.pr4sel = BSP_CFG_EBMAPCR_4TH_PRIORITY; + bsp_bsc.ebmapcr.bit.pr5sel = BSP_CFG_EBMAPCR_5TH_PRIORITY; + + /* Set to EBMAPCR register */ + BSC.EBMAPCR.LONG = bsp_bsc.ebmapcr.u_long; +} /* End of function bsp_bsc_initial_configure() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h new file mode 100644 index 000000000..6c25e0f30 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.h +* Description : Hardware setup header file. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef HWSETUP_H +#define HWSETUP_H + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void hardware_setup(void); //r_bsp internal function. DO NOT CALL. + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h new file mode 100644 index 000000000..28180a97e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* H/W Platform : GENERIC_RX72N +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +#include "mcu/all/r_bsp_common.h" +#include "r_bsp_config.h" +#include "mcu/all/r_rx_compiler.h" + +#include "r_bsp_interrupt_config.h" + +#include "mcu/all/lowlvl.h" +#include "mcu/all/lowsrc.h" +#include "mcu/all/r_bsp_mcu_startup.h" + +#if defined(__CCRX__) +#include "mcu/rx72n/register_access/ccrx/iodefine.h" +#elif defined(__GNUC__) +#include "mcu/rx72n/register_access/gnuc/iodefine.h" +#elif defined(__ICCRX__) +#include "mcu/rx72n/register_access/iccrx/iodefine.h" +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "mcu/rx72n/r_bsp_cpu.h" +#include "mcu/rx72n/r_bsp_locking.h" +#include "mcu/rx72n/mcu_clocks.h" +#include "mcu/rx72n/mcu_info.h" +#include "mcu/rx72n/mcu_init.h" +#include "mcu/rx72n/mcu_interrupts.h" +#include "mcu/rx72n/mcu_locks.h" +#include "mcu/rx72n/mcu_mapped_interrupts_private.h" +#include "mcu/rx72n/mcu_mapped_interrupts.h" +#include "mcu/rx72n/vecttbl.h" + +#include "board/generic_rx72n/hwsetup.h" + +#include "mcu/all/r_bsp_interrupts.h" +#include "mcu/all/r_bsp_software_interrupt.h" +#include "mcu/all/r_rx_intrinsic_functions.h" +#include "mcu/all/r_rtos.h" + +#ifdef __cplusplus +} +#endif + +#ifndef BSP_BOARD_GENERIC_RX72N +#define BSP_BOARD_GENERIC_RX72N + +#endif /* BSP_BOARD_GENERIC_RX72N */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h new file mode 100644 index 000000000..be9268128 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h @@ -0,0 +1,766 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX72N +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release. +***********************************************************************************************************************/ +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX72N. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 57 2N N D D BD + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FC = 0x0 = LFQFP/176/0.50 + BG = 0x1 = LFBGA/176/0.80 + BD = 0x2 = LFBGA/224/0.80 + FB = 0x3 = LFQFP/144/0.50 + LK = 0x4 = TFLGA/145/0.50 + FP = 0x5 = LFQFP/100/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x2) + +/* Whether Encryption is included or not. + Character(s) = Value for macro = Description + D = 0xD = Encryption module not included + H = 0x11 = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0xD) + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + D = 0xD = 2MB/1MB/32KB + N = 0x17 = 4MB/1MB/32KB +NOTE: The RAM areas are not contiguous.It is separated by 512 KB each. +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x17) + +/* Group name. + Character(s) = Value for macro = Description + 2N = 0x0 = RX72N Group +*/ +#define BSP_CFG_MCU_PART_GROUP (0x0) + +/* Series name. + Character(s) = Value for macro = Description + 57 = 0x0 = RX700 Series +*/ +#define BSP_CFG_MCU_PART_SERIES (0x0) + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (1) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x1000) +#endif + +/* Interrupt Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x400) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit (default) +*/ +#define BSP_CFG_CLOCK_SOURCE (4) + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator (default) + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (0) + +/* USB Clock source select (UPLLSEL). Choose which clock source to input to the USB circuit. + 0 = System Clock (PLL Circuit/No division) (This is not available.) + 1 = USB PLL Circuit (This is not available.) + 2 = PLL Circuit (UDIVCLK) (default) + 3 = PPLL Circuit (PPLLDIVCLK) +*/ +#define BSP_CFG_USB_CLOCK_SOURCE (2) + +/* Ethernet-PHY clock source (OUTCKSEL). Choose which clock source to input to the Ethernet PHY LSI. + Available clock sources: + 0 = PLL circuit + 1 = PPLL circuit (default) + 2 = Ethernet-PHY not use +*/ +#define BSP_CFG_PHY_CLOCK_SOURCE (1) + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 6 = PPLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE (2) + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE (0) + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP (0) + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, BCLK is 80MHz, + USB Clock is 48MHz, ESC Clock is 100MHz, Ether-Phy Clock is 25MHz then the settings would be: + + BSP_CFG_XTAL_HZ = 24000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz) + BSP_CFG_PPLL_DIV = 3 (divide by 3) + BSP_CFG_PPLL_MUL = 25.0 (8MHz x 25.0 = 200MHz) + BSP_CFG_PPLCK_DIV = 2 (divide by 2) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 240MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_BCK_DIV = 3 : External Bus Clock (BCK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 80MHz + BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (24000000) + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#define BSP_CFG_HOCO_FREQUENCY (0) + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC (0) + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (1) + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL (10.0) + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (1) + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (2) + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (4) + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (4) + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (4) + +/* External Bus Clock Divider (BCLK). + Available divisors = /1 (no division), /2, /3, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_BCK_DIV (3) + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (4) + +/* USB Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_UCK_DIV (5) + +/* PPLL Input Frequency Division Ratio Select (PPLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PPLL_DIV (3) + +/* PPLL Frequency Multiplication Factor Select (PPLSTC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PPLL_MUL (25.0) + +/* PPLL Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_PPLCK_DIV (2) + +/* Configure BCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency +*/ +#define BSP_CFG_BCLK_OUTPUT (0) + +/* Configure SDCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency + NOTE: The definition is invalid. +*/ +#define BSP_CFG_SDCLK_OUTPUT (0) + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV (0) + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT (0) + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) + +/* Sub-Clock Oscillator Wait Time (SOSCWTCR). + The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation + by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384 + (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h). +*/ +#define BSP_CFG_SOSC_WAIT_TIME (0x21) + +/* ROM Cache Enable Register (ROMCE). + 0 = ROM cache operation disabled. + 1 = ROM cache operation enabled. +*/ +#define BSP_CFG_ROM_CACHE_ENABLE (1) + +/* Configure non-cacheable area 0 of the ROM cache function. + 0 = Non-cacheable area 0 settings disabled. + 1 = Non-cacheable area 0 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ENABLE (0) + +/* Specifies the start address of non-cacheable area 0. + Selects the start address of non-cacheable area 0. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 0. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of IF cache disabled. + 1 = Non-cacheable area 0 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of OA cache disabled. + 1 = Non-cacheable area 0 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of DM cache disabled. + 1 = Non-cacheable area 0 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE (1) + +/* Configure non-cacheable area 1 of the ROM cache function. + 0 = Non-cacheable area 1 settings disabled. + 1 = Non-cacheable area 1 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ENABLE (0) + +/* Specifies the start address of non-cacheable area 1. + Selects the start address of non-cacheable area 1. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 1. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of IF cache disabled. + 1 = Non-cacheable area 1 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of OA cache disabled. + 1 = Non-cacheable area 1 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of DM cache disabled. + 1 = Non-cacheable area 1 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE (1) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 78 and 79 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEFF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b26] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area + - 1: FFFF E000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory + when the flash programmer is used during off-board programming. + ROMCODE - ROM Code Protection Register + b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1). + 0000 0001h: ROM code protection enabled (ROM code protection 2). + Other than above: ROM code protection disabled. + Note: The ROMCODE register should be set in 32-bit units. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. +*/ +#define BSP_CFG_RTOS_USED (0) + +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC + graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and + display list data read). + The default priority order in bsp is below + GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC. + Priority can be changed with this macro. + + Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */ +#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */ +#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */ +#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */ +#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */ + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (0) + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (1) +#define BSP_CFG_SWINT_UNIT2_ENABLE (1) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h new file mode 100644 index 000000000..697280fd6 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h @@ -0,0 +1,222 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupt_config.h +* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ +#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE +#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you + * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you + * would do the following: + * + * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 + */ + +/* Interrupt B Sources. + * -Valid vector numbers are 128-207. + * -There are more vector slots for B sources than actual B sources. By default none of the CAN2 interrupts are + * mapped. + * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default. + * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be + * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0' + * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots. + */ +#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128 +#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175 +#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 192 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 193 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 194 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 195 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 196 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 197 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 198 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 199 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 200 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 201 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 202 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 203 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 204 + +/* Interrupt A Sources. + * -Valid vector numbers are 208-255. + * -There are more A sources than A vector slots. By default none of the GPTW interrupts and the ESC interrupts are + * mapped. + * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default. + */ +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3 +#define BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS 251 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I 252 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I 253 + +#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/user/r_bsp.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/user/r_bsp.h new file mode 100644 index 000000000..94ecab164 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/board/user/r_bsp.h @@ -0,0 +1,54 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 13.01.2012 1.00 First Release +* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure. +***********************************************************************************************************************/ + +#ifndef BSP_BOARD_USER +#define BSP_BOARD_USER + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +/* This is a user defined board. Start off by: + 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group). + 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h. + 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier. + 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h. + 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h. + You can also add your own include files here as well. */ +#include "r_bsp_config.h" +#include "mcu/*MCU Group*/mcu_info.h" + +#endif /* BSP_BOARD_USER */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/lowlvl.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/lowlvl.h new file mode 100644 index 000000000..9ca8db79d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/lowlvl.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowlvl.h +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef LOWLVL_H +#define LOWLVL_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/* Output one character to standard output (the E1 Virtual Console or a serial port via user own charput function) */ +void charput (char output_char); + +/* Input one character from standard input (the E1 Virtual Console or a serial port via user own charget function) */ +char charget (void); + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/lowsrc.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/lowsrc.h new file mode 100644 index 000000000..15b2426fd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/lowsrc.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowsrc.h +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOWSRC_H +#define LOWSRC_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__CCRX__) +void init_iolib(void); +void close_all(void); +long open(const char *name, long mode, long flg); +long close(long fileno); +long write(long fileno, const unsigned char *buf, long count); +long read(long fileno, unsigned char *buf, long count); +long lseek(long fileno, long offset, long base); +#ifdef _REENTRANT +long *errno_addr(void) +long wait_sem(long semnum) +long signal_sem(long semnum) +#endif +#endif /* defined(__CCRX__) */ + +#if defined(__GNUC__) +int write(int fileno, char *buf, int count); +int read(int fileno, char *buf, int count); +int _write(int fileno, char *buf, int count); +int _read(int fileno, char *buf, int count); +void close(void); +void fstat(void); +void isatty(void); +void lseek(void); +#endif /* defined(__GNUC__) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/mcu_locks.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/mcu_locks.c new file mode 100644 index 000000000..4fb5c24b3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/mcu_locks.c @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.c +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Used for getting MCU information to accurately reflect available MCU resources. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +/* Below are locks for controlling access to MCU resources. */ +BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[BSP_NUM_LOCKS]; + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c new file mode 100644 index 000000000..ab902b064 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c @@ -0,0 +1,225 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.c +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 26.03.2014 1.10 Added R_BSP_SoftwareDelay() function +* : 03.09.2014 1.20 Corrected R_BSP_SoftwareDelay() timing when using an RX64M +* : 30.09.2015 1.30 Added RX23T +* : 01.02.2016 1.40 Added RX24T +* Changed the value of the following macro definition. +* - OVERHEAD_CYCLES +* - OVERHEAD_CYCLES_64 +* : 29.02.2016 1.50 Added RX230 +* : 01.10.2016 1.60 Added RX65N +* : 22.08.2016 1.70 Added RX24U +* : 15.05.2017 1.80 Changed method of selecting the number of CPU cycles required to execute +* the delayWait() loop. +* : 27.07.2018 1.90 Changed the value of the following macro definition, because added RX66T. +* - CPU_CYCLES_PER_LOOP +* : 28.02.2019 2.00 Deleted the following definition. +* (The following definition moved to the common file (mcu_info.h).) +* - CPU_CYCLES_PER_LOOP +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_OVERHEAD_CYCLES +* - BSP_PRV_OVERHEAD_CYCLES_64 +* - BSP_PRV_CKSEL_LOCO +* Renamed following function. +* - delay_wait +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get information about current board and MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_OVERHEAD_CYCLES (2) /* R_BSP_SoftwareDelay() overhead per call */ +#define BSP_PRV_OVERHEAD_CYCLES_64 (2) /* R_BSP_SoftwareDelay() overhead per call using 64-bit ints */ + +#define BSP_PRV_CKSEL_LOCO (0x0) /* SCKCR3 register setting for LOCO */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_GetVersion + ******************************************************************************************************************//** + * @brief Returns the current version of the r_bsp. + * @return Version of the r_bsp. + * @details This function will return the version of the currently installed r_bsp. The version number is encoded + * where the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For + * example, Version 4.25 would be returned as 0x00040019. + */ +uint32_t R_BSP_GetVersion (void) +{ + /* These version macros are defined in platform.h. */ + return ((((uint32_t)R_BSP_VERSION_MAJOR) << 16) | (uint32_t)R_BSP_VERSION_MINOR); +} /* End of function R_BSP_GetVersion() */ + + +/*********************************************************************************************************************** +* Function Name: delay_wait +* Description : This asm loop executes a known number (5) of CPU cycles. If a value of '4' is passed +* in as an argument, then this function would consume 20 CPU cycles before returning. +* Arguments : loop_cnt - A single 32-bit value is provided as the number of loops to execute. +* Return Value : None +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(delay_wait) +void delay_wait (unsigned long loop_cnt) +{ + R_BSP_ASM_INTERNAL_USED(loop_cnt) + R_BSP_ASM_BEGIN + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_NEXT(0) ) + R_BSP_ASM( NOP ) + R_BSP_ASM_LAB(0: ) + R_BSP_ASM( NOP ) + R_BSP_ASM( SUB #01H, R1 ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_PREV(0) ) + R_BSP_ASM_END +} /* End of function delay_wait() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_GetIClkFreqHz + ******************************************************************************************************************//** + * @brief Returns the system clock frequency. + * @return System clock frequency specified by the r_bsp. + * @details This function returns the system clock frequency. For example, when the system clock is set to 120 MHz in + * r_bsp_config_h and the r_bsp has completed to specify the clock setting, then even if the user changed the system + * clock frequency to 60 MHz, the return value is '60000000'. + */ +uint32_t R_BSP_GetIClkFreqHz(void) +{ + return get_iclk_freq_hz(); // Get the MCU specific ICLK frequency +} /* End of function R_BSP_GetIClkFreqHz() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareDelay + ******************************************************************************************************************//** + * @brief Delay the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' for the units specified. + * @retval true True if delay executed. + * @retval false False if delay/units combination resulted in overflow/underflow. + * @details This is function that may be called for all MCU targets to implement a specific wait time. + * The actual delay time is plus the overhead at a specified duration. The overhead changes under the influence of + * the compiler, operating frequency and ROM cache. When the operating frequency is low, or the specified duration in + * units of microsecond level, please note that the error becomes large. + */ +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units) +{ + volatile uint32_t iclk_rate; + volatile uint32_t delay_cycles; + volatile uint32_t loop_cnt; + volatile uint64_t delay_cycles_64; + volatile uint64_t loop_cnt_64; + +#ifdef BSP_CFG_PARAM_CHECKING_ENABLE + if ((BSP_DELAY_MICROSECS != units) && (BSP_DELAY_MILLISECS != units) && (BSP_DELAY_SECS != units)) + { + return(false); + } +#endif + + iclk_rate = R_BSP_GetIClkFreqHz(); /* Get the current ICLK frequency */ + + /* + * In order to handle all possible combinations of delay/ICLK it is necessary to use 64-bit + * integers (not all MCUs have floating point support). However, there is no native hw support + * for 64 bit integers so it requires many more clock cycles. This is not an issue if the + * requested delay is long enough and the ICLK is fast, but for delays in the low microseconds + * and/or a slow ICLK we use 32 bit integers to reduce the overhead cycles of this function + * by approximately a third and stand the best chance of achieving the requested delay. + */ + if ( (BSP_DELAY_MICROSECS == units) && + (delay <= (0xFFFFFFFFUL / iclk_rate)) ) /* Ensure (iclk_rate * delay) will not exceed 32 bits */ + { + delay_cycles = ((iclk_rate * delay) / units); + + if (delay_cycles > BSP_PRV_OVERHEAD_CYCLES) + { + delay_cycles -= BSP_PRV_OVERHEAD_CYCLES; + } + else + { + delay_cycles = 0; + } + + loop_cnt = delay_cycles / CPU_CYCLES_PER_LOOP; + + if (0 == loop_cnt) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + } + else + { + /* Casting is valid because it matches the type to the right side or argument. */ + delay_cycles_64 = (((uint64_t)iclk_rate * (uint64_t)delay) / units); + + if (delay_cycles_64 > BSP_PRV_OVERHEAD_CYCLES_64) + { + delay_cycles_64 -= BSP_PRV_OVERHEAD_CYCLES_64; + } + else + { + delay_cycles = 0; + } + + loop_cnt_64 = delay_cycles_64 / CPU_CYCLES_PER_LOOP; + + if ((loop_cnt_64 > 0xFFFFFFFFUL) || (0 == loop_cnt_64)) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + + /* Casting is valid because it matches the type to the right side or argument. */ + loop_cnt = (uint32_t)loop_cnt_64; + } + + delay_wait(loop_cnt); + + return(true); +} /* End of function R_BSP_SoftwareDelay() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h new file mode 100644 index 000000000..f5146b7ce --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.h +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 25.06.2013 1.10 Now contains standard includes (stdint.h, stdbool.h, etc) as well as include for +* r_typedefs.h when needed. +* : 02.07.2013 1.11 Added #include for machine.h. +* : 10.02.2014 1.12 Changed minor version to '40'. +* : 24.03.2014 1.12 Changed minor version to '60'. +* : 14.04.2014 1.12 Added typedef for fit_callback_t. +* : 30.09.2015 1.13 Changed Major/Minor version to 3.00 +* : 30.09.2015 1.14 Changed Minor version to 3.01 +* : 01.12.2015 1.15 Changed Minor version to 3.10 +* : 01.02.2016 1.16 Changed Minor version to 3.20 +* : 29.02.2016 1.17 Changed Minor version to 3.30 +* : 13.04.2016 1.18 Changed Minor version to 3.31 +* : 01.10.2016 1.19 Changed Minor version to 3.40 +* : 04.11.2016 1.20 Changed Minor version to 3.50 +* : 15.05.2017 1.21 Changed Minor version to 3.60 +* : 01.11.2017 1.22 Changed Minor version to 3.70 +* : 01.12.2017 1.23 Changed Minor version to 3.71 +* : 01.07.2018 1.24 Changed Minor version to 3.80 +* : 27.07.2018 1.25 Changed Minor version to 3.90. +* : 31.08.2018 1.26 Changed Minor version to 3.91. +* : 31.10.2018 1.27 Changed Major/Minor version to 4.00. +* : 11.01.2019 1.28 Changed Minor version to 4.01. +* : 28.02.2019 1.29 Changed Major version to 5.00. +* Added the following macro definition. +* - INTERNAL_NOT_USED(p) +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 29.03.2019 1.30 Changed Minor version to 5.10. +* : 08.04.2019 1.31 Changed Minor version to 5.20. +* : 23.07.2019 1.32 Changed Minor version to 5.21. +* : 26.07.2019 1.33 Changed Minor version to 5.30. +* : 31.07.2019 1.34 Changed Minor version to 5.40. +* : 08.10.2019 1.35 Changed Minor version to 5.50. +* : 10.12.2019 1.36 Changed Minor version to 5.51. +* : 14.02.2020 1.37 Changed Minor version to 5.52. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* C99 (or later) is necessary because r_rx_compiler.h uses Pragma operator and variadic macros. + * This means that r_typedefs.h is not used in any case. */ +#if !defined(__cplusplus) && !defined(CPPAPP) +/* All implementation is C99 (or later) */ +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#include +#include +#include +#include +#else +#error "This version of FIT needs C99 (or later)." +#endif +#else /* defined(__cplusplus) || defined(CPPAPP) */ +/* Interface might be referred from C++ */ +#include +#include +#include +#include +#endif /* !defined(__cplusplus) && !defined(CPPAPP) */ + +#if defined(__CCRX__) || defined(__ICCRX__) +/* Intrinsic functions provided by compiler. */ +#include +#elif defined(__GNUC__) +/* No header file for intrinsic functions. */ +#else +/* PORT: Use header file for other compiler and port r_rx_compiler.h. */ +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_BSP_COMMON_H +#define R_BSP_COMMON_H + +/* Version Number of r_bsp. */ +#define R_BSP_VERSION_MAJOR (5) +#define R_BSP_VERSION_MINOR (52) + +/* This macro is used to suppress compiler messages about not only a parameter but also a auto variable not being used + * in a function. The nice thing about using this implementation is that it does not take any extra RAM or ROM. + * This macro is available for the followings: + * CC-RX's 'M0520826:Parameter "XXXX" was never referenced' + * CC-RX's 'W0520550:Variable "XXXX" was set but never used' + * GNURX's 'unused parameter 'XXXX' [-Wunused-parameter]' + * GNURX's 'variable 'XXXX' set but not used [-Wunused-but-set-variable]' + * When the variable is declared as volatile, the '&' can be applied like 'R_INTERNAL_NOT_USED(&volatile_variable);'. + */ +#define INTERNAL_NOT_USED(p) ((void)(p)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available delay units. */ +typedef enum +{ + BSP_DELAY_MICROSECS = 1000000, // Requested delay amount is in microseconds + BSP_DELAY_MILLISECS = 1000, // Requested delay amount is in milliseconds + BSP_DELAY_SECS = 1 // Requested delay amount is in seconds +} bsp_delay_units_t; + +/* Easy to use typedef for FIT module callback functions. */ +typedef void (*fit_callback_t)(void *p_args); + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t R_BSP_GetVersion(void); +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +uint32_t R_BSP_GetIClkFreqHz(void); + +/* End of multiple inclusion prevention macro */ +#endif /* R_BSP_COMMON_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c new file mode 100644 index 000000000..b575b5736 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c @@ -0,0 +1,672 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.c +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 3.10 Added the API function(R_BSP_SoftwareReset). +* Modified comment of API function to Doxygen style. +* Added the vbatt_voltage_stability_wait function. +* Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +* : 31.07.2019 3.11 Deleted the compile condition for R_BSP_SoftwareReset. +* : 08.10.2019 3.12 Changed the following functions. +* - R_BSP_InterruptsDisable +* - R_BSP_InterruptsEnable +* - R_BSP_CpuInterruptLevelWrite +* : 10.12.2019 3.13 Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500) +#endif + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/* The macro definition for combinations where settings of USBVON bit conflict. */ +#define BSP_PRV_USBVON_CONFLICT (BSP_VOL_USB_POWEROFF | BSP_VOL_USB_POWERON) +/* The macro definition for combinations where settings of PGAVLS bit conflict. */ +#define BSP_PRV_PGAVLS_CONFLICT (BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT | BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT) +/* The macro definition for combinations where settings of RICVLS bit conflict. */ +#define BSP_PRV_RICVLS_CONFLICT (BSP_VOL_RIIC_4_5V_OROVER | BSP_VOL_RIIC_UNDER_4_5V) +/* Bit number of VOLSR register. */ +#define BSP_PRV_VOLSR_RICVLS_BIT_NUM (7) +#define BSP_PRV_VOLSR_PGAVLS_BIT_NUM (6) +#define BSP_PRV_VOLSR_USBVON_BIT_NUM (2) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Used for holding reference counters for protection bits. */ +static volatile uint16_t s_protect_counters[BSP_REG_PROTECT_TOTAL_ITEMS]; + +/* Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t s_prcr_masks[BSP_REG_PROTECT_TOTAL_ITEMS-1] = +{ +#ifdef BSP_MCU_RCPC_PRC0 + 0x0001, /* PRC0. */ +#endif +#ifdef BSP_MCU_RCPC_PRC1 + 0x0002, /* PRC1. */ +#endif +#ifdef BSP_MCU_RCPC_PRC2 + 0x0004, /* PRC2. */ +#endif +#ifdef BSP_MCU_RCPC_PRC3 + 0x0008, /* PRC3. */ +#endif +}; +#endif + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsDisable + ******************************************************************************************************************//** + * @brief Globally disables interrupts. + * @details This function globally disables interrupts. This is performed by clearing the 'I' bit in the CPU's + * Processor Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsDisable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to clear the I flag. */ + R_BSP_CLRPSW_I(); + } + +} /* End of function R_BSP_InterruptsDisable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsEnable + ******************************************************************************************************************//** + * @brief Globally enable interrupts. + * @details This function globally enables interrupts. This is performed by setting the 'I' bit in the CPU's Processor + * Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsEnable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to set the I flag. */ + R_BSP_SETPSW_I(); + } + +} /* End of function R_BSP_InterruptsEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelRead + ******************************************************************************************************************//** + * @brief Reads the CPU's Interrupt Priority Level. + * @return The CPU's Interrupt Priority Level. + * @details This function reads the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. + */ +uint32_t R_BSP_CpuInterruptLevelRead (void) +{ + /* Use the compiler intrinsic function to read the CPU IPL. */ + uint32_t psw_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + psw_value = (uint32_t)R_BSP_GET_PSW(); + psw_value = psw_value & 0x0f000000; + psw_value = psw_value >> 24; + + return psw_value; +} /* End of function R_BSP_CpuInterruptLevelRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelWrite + ******************************************************************************************************************//** + * @brief Writes the CPU's Interrupt Priority Level. + * @param[in] level The level to write to the CPU's IPL. + * @retval true Successful, CPU's IPL has been written. + * @retval false Failure, provided 'level' has invalid IPL value or called when the CPU is in User Mode. + * @details This function writes the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. This function does check to make sure that the IPL being written is valid. + * The maximum and minimum valid settings for the CPU IPL are defined in mcu_info.h using the BSP_MCU_IPL_MAX and + * BSP_MCU_IPL_MIN macros. + * @note The CPU's IPL can only be modified by the user when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does not control IPL and return false. + */ +bool R_BSP_CpuInterruptLevelWrite (uint32_t level) +{ + bool ret; + uint32_t pmode; + + /* The R_BSP_SET_IPL() function use the MVTIPL instruction. + The MVTIPL instruction needs to set an immediate value to src. */ + + ret = false; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + ret = true; + + /* Use the compiler intrinsic function to set the CPU IPL. */ + switch (level) + { + case (0): + + /* IPL = 0 */ + R_BSP_SET_IPL(0); + break; + + case (1): + + /* IPL = 1 */ + R_BSP_SET_IPL(1); + break; + + case (2): + + /* IPL = 2 */ + R_BSP_SET_IPL(2); + break; + + case (3): + + /* IPL = 3 */ + R_BSP_SET_IPL(3); + break; + + case (4): + + /* IPL = 4 */ + R_BSP_SET_IPL(4); + break; + + case (5): + + /* IPL = 5 */ + R_BSP_SET_IPL(5); + break; + + case (6): + + /* IPL = 6 */ + R_BSP_SET_IPL(6); + break; + + case (7): + + /* IPL = 7 */ + R_BSP_SET_IPL(7); + break; + + #if 7 < BSP_MCU_IPL_MAX + case (8): + + /* IPL = 8 */ + R_BSP_SET_IPL(8); + break; + + case (9): + + /* IPL = 9 */ + R_BSP_SET_IPL(9); + break; + + case (10): + + /* IPL = 10 */ + R_BSP_SET_IPL(10); + break; + + case (11): + + /* IPL = 11 */ + R_BSP_SET_IPL(11); + break; + + case (12): + + /* IPL = 12 */ + R_BSP_SET_IPL(12); + break; + + case (13): + + /* IPL = 13 */ + R_BSP_SET_IPL(13); + break; + + case (14): + + /* IPL = 14 */ + R_BSP_SET_IPL(14); + break; + + case (15): + + /* IPL = 15 */ + R_BSP_SET_IPL(15); + break; + #endif /* BSP_MCU_IPL_MAX */ + + default: + ret = false; + break; + } + } + + return ret; +} /* End of function R_BSP_CpuInterruptLevelWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectEnable + ******************************************************************************************************************//** + * @brief Enables write protection for selected registers. + * @param[in] regs_to_protect Which registers to enable write protection for. + * @details This function enables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectDisable(), use counters for each entry in the bsp_reg_protect_t enum so + * that users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. An + * example of why this is needed is shown below in the Special Notes section below. + * @note + * (1) About why counters are needed. \n + * See Section 5.7 in the application note for details.\n + * (2) Notes on user mode \n + * The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control with + * this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* Is it safe to disable write access? */ + if (0 != s_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + s_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0 == s_protect_counters[regs_to_protect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_protect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + disable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) & (~s_prcr_masks[regs_to_protect])); + } + else + { + /* Enable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. It could be assumed that the B0WI bit is still cleared from a call to + protection disable function, but it is written here to make sure that the PFSWE bit always gets + cleared. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Disable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 0; + + /* Disable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 1; + } + } + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_protect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectDisable + ******************************************************************************************************************//** + * @brief Disables write protection for selected registers. + * @param[in] regs_to_unprotect Which registers to disable write protection for. + * @details This function disables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectEnable(), use counters for each entry in the bsp_reg_protect_t enum so that + * users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. + * @note The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control + * with this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* If this is first entry then disable protection. */ + if (0 == s_protect_counters[regs_to_unprotect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_unprotect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. + Set lower bits to 1 to enable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) | s_prcr_masks[regs_to_unprotect]); + } + else + { + /* Disable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Enable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 1; + } + } + + /* Increment the protect counter */ + s_protect_counters[regs_to_unprotect]++; + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_unprotect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectDisable() */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/********************************************************************************************************************** + * Function Name: R_BSP_VoltageLevelSetting + ******************************************************************************************************************//** + * @brief This API function is used excessively with the RX66T and RX72T. It makes settings to the voltage level + * setting register (VOLSR) that are necessary in order to use the USB, AD, and RIIC peripheral modules. Call this + * function only when it is necessary to change the register settings. + * @param[in] ctrl_ptn Register Setting Patterns + * The following setting patterns cannot be selected at the same time. + * When specifying more than one pattern at the same time, use the "|" (OR) operator. + * - BSP_VOL_USB_POWEROFF and BSP_VOL_USB_POWERON + * - BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT and BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT + * - BSP_VOL_RIIC_4_5V_OROVER and BSP_VOL_RIIC_UNDER_4_5V + * + * BSP_VOL_USB_POWEROFF: Updates the USBVON bit to 0. + * + * BSP_VOL_USB_POWERON: Updates the USBVON bit to 1. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT: Updates the PGAVLS bit to 0. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT: Updates the PGAVLS bit to 1. + * + * BSP_VOL_RIIC_4_5V_OROVER: Updates the RICVLS bit to 0. + * + * BSP_VOL_RIIC_UNDER_4_5V: Updates the RICVLS bit to 1. + * @retval true Processing completed, register successfully updated. + * @retval false The function was called under the following conditions, so the register setting was not updated. + * - Setting patterns that cannot be selected at the same time were selected. + * - A setting pattern related to the USB was selected when the USB was not in the module stop state. + * - A setting pattern related to the AD was selected when the AD was not in the module stop state. + * - A setting pattern related to the RIIC was selected when the RIIC was not in the module stop state. + * @details This function initializes the voltage level setting register (VOLSR), which is necessary in order to use + * the USB, AD and RIIC peripheral modules. When specifying a setting pattern related to the USB, call this function + * before the USB is released from the module stop state. When specifying a setting pattern related to the AD, call + * this function before the AD (unit 0 and unit 1) is released from the module stop state. When specifying a setting + * pattern related to the RIIC, call this function before the RIIC is released from the module stop state. If the + * function is called with a setting pattern related to the USB specified after the USB is released from the module + * stop state, the function returns "false" as the return value and does not update the register settings. If the + * function is called with a setting pattern related to the AD specified after the AD (unit 0 and unit 1) is released + * from the module stop state, the function returns "false" as the return value and does not update the register + * settings. Finally, if the function is called with a setting pattern related to the RIIC specified after the RIIC is + * released from the module stop state, the function returns "false" as the return value and does not update the + * register settings. + */ +bool R_BSP_VoltageLevelSetting (uint8_t ctrl_ptn) +{ + uint8_t *p_volsr_addr; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* ---- CHECK ARGUMENTS ---- */ + if (BSP_PRV_USBVON_CONFLICT == (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + return false; + } + + if (BSP_PRV_PGAVLS_CONFLICT == (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + return false; + } + + if (BSP_PRV_RICVLS_CONFLICT == (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + return false; + } +#endif + + /* Check USB module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(USB0)) + { + return false; + } + } + + /* Check AD module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if((0 == MSTP(S12AD)) || (0 == MSTP(S12AD1))) + { + return false; + } + } + + /* Check RIIC module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(RIIC0)) + { + return false; + } + } + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_volsr_addr = (uint8_t *)&SYSTEM.VOLSR.BYTE; + + /* Updated the RICVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_RIIC_UNDER_4_5V)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_RIIC_4_5V_OROVER)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + /* Updated the PGAVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + /* Updated the USBVON bit. */ + if(0 != (ctrl_ptn & BSP_VOL_USB_POWERON)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_USB_POWEROFF)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + return true; +} /* End of function R_BSP_VoltageLevelSetting() */ +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareReset + ******************************************************************************************************************//** + * @details Reset the MCU by Software Reset. + */ +void R_BSP_SoftwareReset(void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + /* Protect off. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); +#endif + + /* Resets the MCU. */ + SYSTEM.SWRR = 0xA501; + + /* WAIT_LOOP */ + while(1) + { + R_BSP_NOP(); + } +} /* End of function R_BSP_SoftwareReset() */ + +/*********************************************************************************************************************** +* Function Name: bsp_register_protect_open +* Description : Initializes variables needed for register protection functionality. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_register_protect_open (void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + uint32_t i; + + /* Initialize reference counters to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_REG_PROTECT_TOTAL_ITEMS; i++) + { + s_protect_counters[i] = 0; + } +#else + /* No registers to protect. */ +#endif +} /* End of function bsp_register_protect_open() */ + +/*********************************************************************************************************************** +* Function Name: bsp_ram_initialize +* Description : Initialize ram variable. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_ram_initialize (void) +{ + uint32_t i; + + /* Initialize g_bsp_Locks to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_NUM_LOCKS; i++) + { + g_bsp_Locks[i].lock = 0; + } +} /* End of function bsp_ram_initialize() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c new file mode 100644 index 000000000..a72ade038 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c @@ -0,0 +1,1085 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.c +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.04.2019 1.01 Added process for Group IE0 interrupts. +* Added process for EXNMI interrupts. +* : 26.07.2019 1.10 Modified comment of API function to Doxygen style. +* Modified the following function for added function. +* - R_BSP_InterruptControl +* Added the following functions. +* - bsp_fit_interrupts_control +* - bsp_fit_interrupt_enable +* - bsp_fit_interrupt_disable +* Fixed coding style. +* : 08.10.2019 1.11 Added process for software interrupt. +* : 10.12.2019 1.12 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_FLOATING_POINT +/* Defines CV, CO, CZ, CU, CX, and CE bits. */ +#define BSP_PRV_FPU_CAUSE_FLAGS (0x000000FC) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* This array holds callback functions. */ +static void (* g_bsp_vectors[BSP_INT_SRC_TOTAL_ITEMS])(void * pdata); + +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata); + +#ifdef BSP_MCU_GROUP_INTERRUPT +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl); +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestEnable + ******************************************************************************************************************//** + * @brief Enable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Enable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector number + * of the argument, and set "1" to that bit. The macro defined in iodefine.h can be used to the setting of the + * argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestEnable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_SET(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestDisable + ******************************************************************************************************************//** + * @brief Disable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Disable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector + * number of the argument, and clear "0" to that bit. The macro defined in iodefine.h can be used to the setting of + * the argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestDisable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_CLEAR(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestDisable() */ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_open +* Description : Initialize callback function array. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_interrupt_open (void) +{ + uint32_t i; + + /* WAIT_LOOP */ + for (i = 0; i < BSP_INT_SRC_TOTAL_ITEMS; i++) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[i] = FIT_NO_FUNC; + } + +#ifdef BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT + /* Initialize mapped interrupts. */ + bsp_mapped_interrupt_open(); +#endif + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT1); +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT2); +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ +} /* End of function bsp_interrupt_open() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptWrite + ******************************************************************************************************************//** + * @brief Registers a callback function for an interrupt. + * @param[in] vector Which interrupt to register a callback for. + * @param[in] callback Pointer to function to call when interrupt occurs. + * @retval BSP_INT_SUCCESS Successful, callback has been registered. + * @retval BSP_INT_ERR_INVALID_ARG Invalid function address input, any previous function has been unregistered. + * @details This function registers a callback function for an interrupt. If FIT_NO_FUNC, NULL, or any other invalid + * function address is passed for the callback argument then any previously registered callbacks are unregistered. + * If one of the interrupts that is handled by this code is triggered then the interrupt handler will query this code + * to see if a valid callback function is registered. If one is found then the callback function will be called. + * If one is not found then the interrupt handler will clear the appropriate flag(s) and exit. If the user has a + * callback function registered and wishes to no longer handle the interrupt then the user should call this function + * again with FIT_NO_FUNC as the vector parameter. + * @note Use of FIT_NO_FUNC is preferred over NULL since access to the address defined by FIT_NO_FUNC will cause a + * bus error which is easy for the user to catch. NULL typically resolves to 0 which is a valid address on RX MCUs. + */ +bsp_int_err_t R_BSP_InterruptWrite (bsp_int_src_t vector, bsp_int_cb_t callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)callback == (uint32_t)NULL) || ((uint32_t)callback == (uint32_t)FIT_NO_FUNC)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[vector] = FIT_NO_FUNC; + } + else + { + g_bsp_vectors[vector] = callback; + } + + return err; +} /* End of function R_BSP_InterruptWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRead + ******************************************************************************************************************//** + * @brief Gets the callback for an interrupt if one is registered. + * @param[in] vector Which interrupt to read the callback for. + * @param[out] callback Pointer to where to store callback address. + * @retval BSP_INT_SUCCESS Successful, callback address has been returned. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @details This function returns the callback function address for an interrupt if one has been registered. If a + * callback function has not been registered then an error is returned and nothing is stored to the callback address. + */ +bsp_int_err_t R_BSP_InterruptRead (bsp_int_src_t vector, bsp_int_cb_t * callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)g_bsp_vectors[vector] == (uint32_t)NULL) || ((uint32_t)g_bsp_vectors[vector] == (uint32_t)FIT_NO_FUNC)) + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + else + { + *callback = g_bsp_vectors[vector]; + } + + return err; +} /* End of function R_BSP_InterruptRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptControl + ******************************************************************************************************************//** + * @brief Controls various interrupt operations. + * @param[in] vector Which interrupt to control for.\n + * If the interrupt control commands is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE or the BSP_INT_CMD_FIT_INTERRUPT_DISABLE + * commands, set BSP_INT_SRC_EMPTY to "vector" because no arguments are used. + * @param[in] cmd Interrupt control command. + * @param[in,out] pdata Pointer to the argument for each interrupt control command. Typecasted to void*. See typedef + * defines of bsp_int_ctrl_t. \n + * Most of the interrupt control commands do not need the argument and take FIT_NO_PTR for + * this parameter. If the interrupt control command is the BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command, set the + * interrupt priority level for group interrupts as the argument. If the interrupt control command is the + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE command, set the address of a variable for saving the current processor interrupt + * priority level in the argument. If the interrupt control command is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE command, + * set the address of a variable used in the BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + * @retval BSP_INT_SUCCESS Successful. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @retval BSP_INT_ERR_INVALID_ARG The command passed is invalid. + * @retval BSP_INT_ERR_UNSUPPORTED This processing is not supported. + * @retval BSP_INT_ERR_GROUP_STILL_ENABLED Group interrupt request remains enabled. + * @retval BSP_INT_ERR_INVALID_IPL Illegal IPL value input. + * @details This function controls the interrupt callback function call and enabling/disabling interrupts such as bus + * error interrupt, floating-point exception, NMI pin interrupt, and group interrupts, and enabling/disabling + * interrupts by controlling the Processor Interrupt Priority Level. When BSP_INT_CMD_GROUP_INTERRUPT_ENABLE is set as + * the interrupt control command, the interrupt request (IER) for group interrupts is enabled and also the interrupt + * priority level is set. The interrupt priority level set must be higher than the current level. When + * BSP_INT_CMD_GROUP_INTERRUPT_DISABLE is set as the interrupt control command, the interrupt request (IER) for group + * interrupts is disabled. Note that the interrupt request (IER) for group interrupts cannot be disabled as long as + * all interrupt requests (GEN) caused by grouped interrupt sources are disabled. When + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE is set as the interrupt control command, the current processor interrupt priority + * level (IPL) is saved to the address specified by pdata as an argument, and disables interrupts by controlling the + * IPL. The value of IPL to be set is the value of BSP_CFG_FIT_IPL_MAX. When BSP_INT_CMD_FIT_INTERRUPT_ENABLE is set + * as the interrupt control command, the interrupt is enabled by setting the value stored in the address specified by + * pdata to IPL. These two commands are valid only in supervisor mode. When BSP_INT_CMD_FIT_INTERRUPT_DISABLE and + * BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands are executed in user mode, Controlling IPL is not executed and an error + * code BSP_INT_ERR_UNSUPPORTED is returned. + * @note BSP_INT_CMD_FIT_INTERRUPT_DISABLE and BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands can be used to secure + * atomicity of critical sections. However, these commands are valid only in supervisor mode. When these commands are + * executed in user mode, atomicity is not to secure.\n + * See Section 5.15 in the application note for more information. + */ +bsp_int_err_t R_BSP_InterruptControl (bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata) +{ + bsp_int_err_t err; + bsp_int_cb_args_t cb_args; + + err = BSP_INT_SUCCESS; + +#ifdef BSP_MCU_GROUP_INTERRUPT + /* nothing */ +#else + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(pdata); +#endif + + switch (cmd) + { + case (BSP_INT_CMD_CALL_CALLBACK): + + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)g_bsp_vectors[vector] != (uint32_t)NULL) && ((uint32_t)g_bsp_vectors[vector] != (uint32_t)FIT_NO_FUNC)) + { + /* Fill in callback info. */ + cb_args.vector = vector; + + g_bsp_vectors[vector](&cb_args); + } + else + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + break; + + case (BSP_INT_CMD_INTERRUPT_ENABLE): + err = bsp_interrupt_enable_disable(vector, true); + break; + + case (BSP_INT_CMD_INTERRUPT_DISABLE): + err = bsp_interrupt_enable_disable(vector, false); + break; + +#ifdef BSP_MCU_GROUP_INTERRUPT + case (BSP_INT_CMD_GROUP_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_gr_int_enable_disable(vector, true, ((bsp_int_ctrl_t *)pdata)->ipl); + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + break; + + case (BSP_INT_CMD_GROUP_INTERRUPT_DISABLE): + err = bsp_gr_int_enable_disable(vector, false, 0); + break; +#endif + + case (BSP_INT_CMD_FIT_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(true, (bsp_int_ctrl_t *)pdata); + break; + + case (BSP_INT_CMD_FIT_INTERRUPT_DISABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(false, (bsp_int_ctrl_t *)pdata); + break; + + default: + err = BSP_INT_ERR_INVALID_ARG; + break; + } + + return err; +} /* End of function R_BSP_InterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_fit_interrupts_control +* Description : +* Arguments : enable - +* Whether to enable or disable the interrupt. +* pdata - +* Pointer to variable for saves ipl or restore ipl. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid argument input. +* BSP_INT_ERR_INVALID_IPL - +* Invalid IPL input. +* BSP_INT_ERR_UNSUPPORTED - +* This processing is not supported. (Executed in user mode.) +***********************************************************************************************************************/ +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata) +{ + bsp_int_err_t err; + uint32_t pmode; + bool ret; + uint32_t ipl_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + err = BSP_INT_SUCCESS; + + if (true == enable) + { + ipl_value = pdata->ipl; + } + else + { + /* Get the current Processor Interrupt Priority Level (IPL) and save IPL value. */ + pdata->ipl = R_BSP_CpuInterruptLevelRead(); + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + ipl_value = BSP_CFG_FIT_IPL_MAX; + } + + if (pdata->ipl < BSP_CFG_FIT_IPL_MAX) + { + ret = R_BSP_CpuInterruptLevelWrite(ipl_value); + if (false == ret) + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_UNSUPPORTED; + } + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_fit_interrupts_control() */ + +#ifdef BSP_MCU_GROUP_INTERRUPT +/*********************************************************************************************************************** +* Function Name: bsp_gr_int_enable_disable +* Description : Either enables or disables a group interrupt. If a group interrupt is called multiple times to be +* enabled then it will use the highest given IPL. A group interrupt will only be disabled when all +* interrupt sources for that group are already disabled. +* Arguments : vector - +* An interrupt source inside the group that is to be enabled/disabled. +* enable - +* Whether to enable or disable the interrupt. +* ipl - +* If enabling a group interrupt, what IPL to use. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid IPL or vector +* BSP_INT_ERR_GROUP_STILL_ENABLED - +* Not all group interrupts were disabled so group interrupt was not disabled. +***********************************************************************************************************************/ +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl) +{ + bsp_int_err_t err = BSP_INT_SUCCESS; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* If interrupt is going to be enabled, verify that IPL is valid. */ + if ((true == enable) && ((BSP_MCU_IPL_MIN == ipl) || (ipl > BSP_MCU_IPL_MAX))) + { + return BSP_INT_ERR_INVALID_ARG; + } +#endif + + if ((vector > BSP_INT_SRC_GR_INT_IE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BE0_TOP)) + { + /* Group IE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_IE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPIE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = (uint8_t)((ipl > IPR(ICU, GROUPIE0)) ? ipl : IPR(ICU, GROUPIE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPIE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENIE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL0_TOP)) + { + /* Group BE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = (uint8_t)((ipl > IPR(ICU, GROUPBE0)) ? ipl : IPR(ICU, GROUPBE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL1_TOP)) + { + /* Group BL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = (uint8_t)((ipl > IPR(ICU, GROUPBL0)) ? ipl : IPR(ICU, GROUPBL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL1_TOP) && (vector < BSP_INT_SRC_GR_INT_BL2_TOP)) + { + /* Group BL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = (uint8_t)((ipl > IPR(ICU, GROUPBL1)) ? ipl : IPR(ICU, GROUPBL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL2_TOP) && (vector < BSP_INT_SRC_GR_INT_AL0_TOP)) + { + /* Group BL2. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL2 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL2) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = (uint8_t)((ipl > IPR(ICU, GROUPBL2)) ? ipl : IPR(ICU, GROUPBL2)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL2)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL2.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL0_TOP) && (vector < BSP_INT_SRC_GR_INT_AL1_TOP)) + { + /* Group AL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = (uint8_t)((ipl > IPR(ICU, GROUPAL0)) ? ipl : IPR(ICU, GROUPAL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL1_TOP) && (vector < BSP_INT_SRC_GR_INT_END)) + { + /* Group AL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = (uint8_t)((ipl > IPR(ICU, GROUPAL1)) ? ipl : IPR(ICU, GROUPAL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + } + else + { + /* Vector given was not part of a group. */ + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_gr_int_enable_disable() */ +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_supervisor_inst_isr +* Description : Supervisor Instruction Violation ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_supervisor_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_SUPERVISOR_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_supervisor_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +/*********************************************************************************************************************** +* Function name: excep_access_isr +* Description : Access exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_access_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_ACCESS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_access_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_undefined_inst_isr +* Description : Undefined instruction exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_undefined_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_UNDEFINED_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_undefined_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +/*********************************************************************************************************************** +* Function name: excep_floating_point_isr +* Description : Floating point exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_floating_point_isr(void) +{ +#ifdef __FPU + /* Used for reading FPSW register. */ + uint32_t tmp_fpsw; +#endif + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_FPU, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + +#ifdef __FPU + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW(tmp_fpsw & ((uint32_t)~BSP_PRV_FPU_CAUSE_FLAGS)); +#endif +} /* End of function excep_floating_point_isr() */ +#endif + +#ifdef BSP_MCU_NON_MASKABLE_ISR +/*********************************************************************************************************************** +* Function name: non_maskable_isr +* Description : Non-maskable interrupt ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void non_maskable_isr(void) +{ + /* Determine what is the cause of this interrupt. */ + +#ifdef BSP_MCU_NMI_EXC_NMI_PIN + /* EXC_NMI_PIN */ + if ((1 == ICU.NMISR.BIT.NMIST) && (1 == ICU.NMIER.BIT.NMIEN)) + { + /* NMI pin interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_NMI_PIN, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear NMI pin interrupt flag. */ + ICU.NMICLR.BIT.NMICLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_OSC_STOP_DETECT + /* OSC_STOP_DETECT */ + if ((1 == ICU.NMISR.BIT.OSTST) && (1 == ICU.NMIER.BIT.OSTEN)) + { + /* Oscillation stop detection interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_OSC_STOP_DETECT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear oscillation stop detect flag. */ + ICU.NMICLR.BIT.OSTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_WDT_ERROR + /* WDT_ERROR */ + if ((1 == ICU.NMISR.BIT.WDTST) && (1 == ICU.NMIER.BIT.WDTEN)) + { + /* WDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_WDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear WDT flag. */ + ICU.NMICLR.BIT.WDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD + /* LVD */ + if ((1 == ICU.NMISR.BIT.LVDST) && (1 == ICU.NMIER.BIT.LVDEN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +#endif + +#ifdef BSP_MCU_NMI_IWDT_ERROR + /* IWDT_ERROR */ + if ((1 == ICU.NMISR.BIT.IWDTST) && (1 == ICU.NMIER.BIT.IWDTEN)) + { + /* IWDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_IWDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear IWDT flag. */ + ICU.NMICLR.BIT.IWDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD1 + /* LVD1 */ + if ((1 == ICU.NMISR.BIT.LVD1ST) && (1 == ICU.NMIER.BIT.LVD1EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD1 flag. */ + ICU.NMICLR.BIT.LVD1CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD2 + /* LVD2 */ + if ((1 == ICU.NMISR.BIT.LVD2ST) && (1 == ICU.NMIER.BIT.LVD2EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.LVD2CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_VBATT + /* VBATT */ + if ((1 == ICU.NMISR.BIT.VBATST) && (1 == ICU.NMIER.BIT.VBATEN)) + { + /* VBATT monitoring interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_VBATT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.VBATCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_ECCRAM + /* ECCRAM */ + if ((1 == ICU.NMISR.BIT.ECCRAMST) && (1 == ICU.NMIER.BIT.ECCRAMEN)) + { + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + } +#endif + +#ifdef BSP_MCU_NMI_RAM + /* RAM */ + if ((1 == ICU.NMISR.BIT.RAMST) && (1 == ICU.NMIER.BIT.RAMEN)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_ECCRAM */ + } +#endif /* BSP_MCU_NMI_RAM */ + +#ifdef BSP_MCU_NMI_EXNMI + /* EXNMI */ + if ((1 == ICU.NMISR.BIT.EXNMIST) && (1 == ICU.NMIER.BIT.EXNMIEN)) + { + #ifdef BSP_MCU_NMI_EXNMI_RAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.RAMST) && (1 == ICU.EXNMIER.BIT.RAMEN)) + { + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_EXNMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_EXNMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_ECCRAM */ + } + #endif /* BSP_MCU_NMI_EXNMI_RAM */ + + #ifdef BSP_MCU_NMI_EXNMI_DPFPUEX + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.DPFPUST) && (1 == ICU.EXNMIER.BIT.DPFPUEN)) + { + /* Double-Precision Floating-Point Exception interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear DPFPUST flag. */ + ICU.EXNMICLR.BIT.DPFPUCLR = 1; + } + #endif /* BSP_MCU_NMI_EXNMI_DPFPUEX */ + } +#endif /* BSP_MCU_NMI_EXNMI */ + + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Return from Non-maskable interrupt handlling routine is prohibited. + Never use the non-maskable interrupt with an attempt to return to the program that was being executed at + the time of interrupt generation after the exception handling routine is ended. + */ + R_BSP_NOP(); + } +} /* End of function non_maskable_isr() */ +#endif /* BSP_MCU_NON_MASKABLE_ISR */ + +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +/*********************************************************************************************************************** +* Function name: undefined_interrupt_source_isr +* Description : All undefined interrupt vectors point to this function. +* Set a breakpoint in this function to determine which source is creating unwanted interrupts. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void undefined_interrupt_source_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_UNDEFINED_INTERRUPT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function undefined_interrupt_source_isr() */ +#endif + +#ifdef BSP_MCU_BUS_ERROR_ISR +/*********************************************************************************************************************** +* Function name: bus_error_isr +* Description : By default, this demo code enables the Bus Error Interrupt. This interrupt will fire if the user tries +* to access code or data from one of the reserved areas in the memory map, including the areas covered +* by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint +* during debugging and development, and further handling should be added by the user for their +* application. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void bus_error_isr (void) +{ + /* Clear the bus error */ + BSC.BERCLR.BIT.STSCLR = 1; + + /* + To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD. + The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units) + */ + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function bus_error_isr() */ +#endif + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h new file mode 100644 index 000000000..d6de101be --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.h +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptRequestEnable(uint32_t vector); +void R_BSP_InterruptRequestDisable(uint32_t vector); +bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector, bsp_int_cb_t callback); +bsp_int_err_t R_BSP_InterruptRead(bsp_int_src_t vector, bsp_int_cb_t * callback); +bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata); + +void bsp_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_supervisor_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_access_isr) +#endif +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_undefined_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_floating_point_isr) +#endif +#ifdef BSP_MCU_NON_MASKABLE_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(non_maskable_isr) +#endif +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +R_BSP_PRAGMA_INTERRUPT_DEFAULT(undefined_interrupt_source_isr) +#endif +#ifdef BSP_MCU_BUS_ERROR_ISR +R_BSP_PRAGMA_INTERRUPT(bus_error_isr, VECT(BSC,BUSERR)) +#endif + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c new file mode 100644 index 000000000..6170397d7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c @@ -0,0 +1,187 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.c +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* : 10.12.2019 2.02 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform configuration. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareLock + ******************************************************************************************************************//** + * @brief Attempts to reserve a lock. + * @param[out] plock Pointer to lock structure with lock to try and acquire. + * @retval true Successful, lock was available and acquired. + * @retval false Failure, lock was already acquired and is not available. + * @details This function implements an atomic locking mechanism. Locks can be used in numerous ways. Two common uses + * of locks are to protect critical sections of code and to protect against duplicate resource allocation. + * For protecting critical sections of code the user would require that the code first obtain the critical section's + * lock before executing. An example of protecting against duplicate resource allocation would be if the user had two + * FIT modules that used the same peripheral. For example, the user may have one FIT module that uses the SCI + * peripheral in UART mode and another FIT module that uses the SCI peripheral in I2C mode. To make sure that both + * modules cannot use the same SCI channel, locks can be used. + * Care should be taken when using locks as they do not provide advanced features one might expect from an RTOS + * semaphore or mutex. If used improperly locks can lead to deadlock in the user's system. + * Users can override the default locking mechanisms. + */ +bool R_BSP_SoftwareLock (BSP_CFG_USER_LOCKING_TYPE * const plock) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + bool ret = false; + + /* Variable used in trying to acquire lock. Using the xchg instruction makes this atomic */ + int32_t is_locked = true; + + /* This example uses the RX MCU's atomic xchg() instruction. plock->lock is the lock we are trying to reserve. + The way this works is that 'is_locked' gets the value of the plock->lock and plock->lock gets the value of + 'is_locked' which we just set to 'true'. Basically this is an atomic 'swap' command. If the lock had not yet been + reserved then its value would be 'false' and after the xchg() instruction finished 'is_locked' would have + 'false'. If it had already been reserved then 'is_locked' would have 'true' after the xchg() instruction. Since + plock->lock was already 'true' and we just set it back to 'true' everything is ok. To see if we reserved the lock + we just need to check the value of 'is_locked' after this instruction finishes. */ + + /* Try to acquire semaphore to obtain lock */ + R_BSP_EXCHANGE(&is_locked, &plock->lock); + + /* Check to see if semaphore was successfully taken */ + if (false == is_locked) + { + /* Lock obtained, return success. */ + ret = true; + } + else + { + /* Lock was not obtained, another task already has it. */ + R_BSP_NOP(); + } + + return ret; +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(plock); +#endif +} /* End of function R_BSP_SoftwareLock() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareUnlock + ******************************************************************************************************************//** + * @brief Releases a lock. + * @param[out] plock Pointer to lock structure with lock to release. + * @retval true Successful, lock was released. Or the lock has been already released. + * @retval false Failure, lock could not be released. + * @details This function releases a lock that was previously acquired using the R_BSP_SoftwareLock() function. + */ +bool R_BSP_SoftwareUnlock (BSP_CFG_USER_LOCKING_TYPE * const plock) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Set lock back to unlocked. */ + plock->lock = false; + + return true; +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(plock); +#endif +} /* End of function R_BSP_SoftwareUnlock() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_HardwareLock + ******************************************************************************************************************//** + * @brief Attempts to reserve a hardware peripheral lock. + * @param[in] hw_index Index of lock to acquire from the hardware lock array. + * @retval true Successful, lock was available and acquired. + * @retval false Failure, lock was already acquired and is not available. + * @details This function attempts to acquire the lock for a hardware resource of the MCU. Instead of sending in a + * pointer to a lock as with the R_BSP_SoftwareLock() function, the user sends in an index to an array that holds 1 + * lock per MCU hardware resource. This array is shared amongst all FIT modules and user code therefore allowing + * multiple FIT modules (and user code) to use the same locks. The user can see the available hardware resources by + * looking at the mcu_lock_t enum in mcu_locks.h. These enum values are also the index into the hardware lock array. + * The same atomic locking mechanisms from the R_BSP_SoftwareLock() function are used with this function as well. + * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required + * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum they are not + * using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. The + * user will save 4-bytes per deleted entry. + */ +bool R_BSP_HardwareLock (mcu_lock_t const hw_index) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Pass actual lock to software lock function. */ + return R_BSP_SoftwareLock(&g_bsp_Locks[hw_index]); +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(hw_index); +#endif +} /* End of function R_BSP_HardwareLock() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_HardwareUnlock + ******************************************************************************************************************//** + * @brief Releases a hardware peripheral lock. + * @param[in] hw_index Index of lock to release from the hardware lock array. + * @retval true Successful, lock was released. + * @retval false Failure, lock could not be released. + * @details This function attempts to release the lock for a hardware resource of the MCU that was previously acquired + * using the R_BSP_HardwareLock() function. + * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required + * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum that they are + * not using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. + * The user will save 4-bytes per deleted entry. + */ +bool R_BSP_HardwareUnlock (mcu_lock_t const hw_index) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Pass actual lock to software unlock function. */ + return R_BSP_SoftwareUnlock(&g_bsp_Locks[hw_index]); +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(hw_index); +#endif +} /* End of function R_BSP_HardwareUnlock() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c new file mode 100644 index 000000000..69a22da8f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c @@ -0,0 +1,93 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_mcu_startup.c +* Description : This module implements user startup specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* Added Initialization the trigonometric function unit in R_BSP_StartupOpen function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE != 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_StartupOpen + ******************************************************************************************************************//** + * @brief Specifies settings to use the BSP and peripheral FIT modules. Call this function only when the BSP startup + * is disabled. + * @details This function performs initialization for the interrupt callback, register protection, and the hardware + * and pins. These processing are needed for using the BSP and peripheral FIT modules. Thus, this function must be + * called in the beginning of the main function. Call this function only when the BSP startup is disabled. + * @note The R_BSP_StartupOpen function performs a part of processing in the startup function. + * See Section 5.18 in the application note for more information. + */ +void R_BSP_StartupOpen (void) +{ + /* Initializes the trigonometric function unit. */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU + R_BSP_INIT_TFU(); +#endif +#endif + /* Initialize RAM. */ + bsp_ram_initialize(); + + /* Initialize MCU interrupt callbacks. */ + bsp_interrupt_open(); + + /* Initialize register protection functionality. */ + bsp_register_protect_open(); + + /* Configure the MCU and board hardware */ + hardware_setup(); +} /* End of function R_BSP_StartupOpen() */ + +#endif /* BSP_CFG_STARTUP_DISABLE != 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h new file mode 100644 index 000000000..50a8304da --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_mcu_startup.h +* Description : This module implements user startup specific functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_STARTUP_H +#define MCU_STARTUP_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_StartupOpen(void); + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c new file mode 100644 index 000000000..203210da9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c @@ -0,0 +1,1053 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.c +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_SWINT_TASK_BUFFER_MAX (BSP_CFG_SWINT_TASK_BUFFER_NUMBER + 1) +#define BSP_PRV_SWINT_ACCESS_ACCEPTATION (1) +#define BSP_PRV_SWINT_ACCESS_REJECTION (0) +#define BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT (1) +#define BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +st_bsp_swint_access_control_t g_bsp_swint_access_ctrl[BSP_SWINT_UNIT_MAX]; + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Interrupt functions */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint_isr, VECT(ICU, SWINT)) +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint2_isr, VECT(ICU, SWINT2)) +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + +/* Functions */ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args); +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit); +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args); +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit); +static void bsp_swint_dummy_task(void * p_dummy_context); + +/* Variables */ +static st_bsp_swint_task_t s_bsp_swint_task[BSP_SWINT_UNIT_MAX][BSP_PRV_SWINT_TASK_BUFFER_MAX]; +static uint8_t s_bsp_swint_buf_used[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_top[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_bottom[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_nested_int_status[BSP_SWINT_UNIT_MAX]; + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptOpen + ******************************************************************************************************************//** + * @brief This function initializes software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function locks the hardware, resets the access control status, clears the interrupt request (IR), + * initializes the interrupt priority level (IPR), enables nested-interrupt status, initializes the task buffer, and + * enables interrupts (IEN). + * @note This function is available only when use of software interrupts is enabled in a configuration macro. + * This function is called automatically at BSP startup when the value of BSP_CFG_SWINT_UNITn_ENABLE in r_bsp_config.h + * is 1. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + uint8_t swint_ipr; + + swint_ret = BSP_SWINT_SUCCESS; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + break; + } + + if (BSP_SWINT_SUCCESS == swint_ret) + { + if (true == lock_ret) + { + /* Reset Access Control Status */ + g_bsp_swint_access_ctrl[unit].status = BSP_PRV_SWINT_ACCESS_ACCEPTATION; + + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Set Interrupt Priority(IPR) */ + swint_ipr = BSP_CFG_SWINT_IPR_INITIAL_VALUE; + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, &swint_ipr); + + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Enable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_ENABLE_INTERRUPT, FIT_NO_PTR); + } + else + { + swint_ret = BSP_SWINT_ERR_ALREADY_OPEN; + } + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptOpen() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptClose + ******************************************************************************************************************//** + * @brief This function terminates software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function unlocks the hardware, disables interrupts (IEN), clears the interrupt request (IR), + * initializes the task buffer, and disables nested-interrupt status. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the R_BSP_SoftwareInterruptSetTask function or software interrupt function (bsp_swint_execute_task) is acquiring + * acces control rights and an interrupt is generated and this function is called within the interrupt, the task + * buffer may not be controlled correctly. If this function is used in an interrupt, clear the all task by the + * R_BSP_SoftwareInterruptControl function with the BSP_SWINT_CMD_CLEAR_ALL_TASK command before call this function. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + if (true == lock_ret) + { + swint_ret = BSP_SWINT_SUCCESS; + } + else + { + swint_ret = BSP_SWINT_ERR_NOT_CLOSED; + } + } + else + { + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptClose() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptSetTask + ******************************************************************************************************************//** + * @brief This function sets a task in the software interrupt task buffer. + * @param[in] unit Software interrupt unit + * @param[in] set_task Software interrupt task + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_TASK Invalid task pointer specified. + * @retval BSP_SWINT_ERR_FULL_BUFFER Task buffer full. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function sets the task specified by an argument in the software interrupt task buffer. After setting + * the task, the software interrupt occurs. If the task buffer is full, the task is not set. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_access_control_t access_control; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)FIT_NO_FUNC == (uint32_t)set_task.p_taskAddr) || ((uint32_t)NULL == (uint32_t)set_task.p_taskAddr)) + { + ret = BSP_SWINT_ERR_INVALID_TASK; + } + else if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_used[unit]) + { + ret = BSP_SWINT_ERR_FULL_BUFFER; + } + else + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_top[unit]) + { + s_bsp_swint_buf_top[unit] = 0; + } + else + { + s_bsp_swint_buf_top[unit]++; + } + + s_bsp_swint_buf_used[unit]++; + + /* Set Task Buffer */ + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].status = BSP_SWINT_TASK_STATUS_REQUESTED; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_taskAddr = set_task.p_taskAddr; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_context = set_task.p_context; + + ret = BSP_SWINT_SUCCESS; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptSetTask() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_interrupt_information +* Description : Get the software interrupt information. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args) +{ + st_bsp_swint_int_info_t *p_swint_int_info; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_int_info = (st_bsp_swint_int_info_t *)p_args; + + switch (unit) + { + /* Get Interrupt Information */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + p_swint_int_info->ipr = IPR(ICU, SWINT); + p_swint_int_info->ien = IEN(ICU, SWINT); + p_swint_int_info->ir = IR(ICU, SWINT); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + p_swint_int_info->ipr = IPR(ICU, SWINT2); + p_swint_int_info->ien = IEN(ICU, SWINT2); + p_swint_int_info->ir = IR(ICU, SWINT2); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_get_interrupt_information() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_interrupt +* Description : Enable interrupt. (Set the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Enable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_enable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_interrupt +* Description : Disable interrupt. (Clear the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Disable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_disable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_priority +* Description : Set interrupt priority. (Set the IPR register.) +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_INVALID_IPR - Overflow interrupt priority. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_ipr; + uint8_t ien; + bsp_int_ctrl_t int_ctrl; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_ipr = (uint8_t *)p_args; + + /* Check Interrupt Priority */ + if (BSP_MCU_IPL_MAX < (*p_swint_ipr)) + { + ret = BSP_SWINT_ERR_INVALID_IPR; + } + else + { + /* Set IPL to the maximum value to disable all interrupts*/ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + switch (unit) + { + /* Set Interrupt Priority */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ien = IEN(ICU, SWINT); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ien = IEN(ICU, SWINT2); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT2) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + /* Restore the IPL */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + + ret = BSP_SWINT_SUCCESS; + } + + return ret; +} /* End of function bsp_swint_set_interrupt_priority() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_request +* Description : Set interrupt request. (Set the SWINTR register.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Set Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ICU.SWINTR.BIT.SWINT = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ICU.SWINT2R.BIT.SWINT2 = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_set_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_interrupt_request +* Description : Clear interrupt request. (Clear the IR bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Clear Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + IR(ICU, SWINT) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + IR(ICU, SWINT2) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_clear_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_nested_interrupt +* Description : Set nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_enable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_nested_interrupt +* Description : Clear nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_disable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_task +* Description : Clear the task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +* BSP_SWINT_ERR_INVALID_BUFFER_NUMBER - Set invalid buffer number. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_task_buffer_t *p_swint_task_buffer; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task_buffer = (st_bsp_swint_task_buffer_t *)p_args; + + if (BSP_PRV_SWINT_TASK_BUFFER_MAX > p_swint_task_buffer->number) + { + /* Clear Task Buffer */ + if (BSP_SWINT_TASK_STATUS_EXECUTING != s_bsp_swint_task[unit][p_swint_task_buffer->number].status) + { + s_bsp_swint_task[unit][p_swint_task_buffer->number].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_context = FIT_NO_PTR; + ret = BSP_SWINT_SUCCESS; + } + else + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_BUFFER_NUMBER; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_all_task +* Description : Clear the all task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit) +{ + e_bsp_swint_err_t ret; + uint8_t buf_num; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + ret = BSP_SWINT_SUCCESS; + + /* Check Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][buf_num].status) + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + break; + } + } + + if (BSP_SWINT_SUCCESS == ret) + { + /* Clear ALL Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } + else + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_all_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_all_task_status +* Description : Get the task status of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args) +{ + uint8_t buf_num; + st_bsp_swint_task_t *p_swint_task; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task = (st_bsp_swint_task_t *)p_args; + + /* Clear Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + p_swint_task->status = s_bsp_swint_task[unit][buf_num].status; + p_swint_task->p_taskAddr = s_bsp_swint_task[unit][buf_num].p_taskAddr; + p_swint_task->p_context = s_bsp_swint_task[unit][buf_num].p_context; + p_swint_task++; + } +} /* End of function bsp_swint_get_all_task_status() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptControl + ******************************************************************************************************************//** + * @brief This function controls software interrupts. + * @param[in] unit Software interrupt unit + * @param[in] cmd Software interrupt control command + * @param[in, out] p_args Pointer to arguments for software interrupt control commands. Set the argument type to match + * each software interrupt control command. For commands that do not require arguments, use the setting FIT_NO_PTR. + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_IPR Invalid interrupt priority level specified. + * @retval BSP_SWINT_ERR_INVALID_CMD Invalid command specified. + * @retval BSP_SWINT_ERR_INVALID_BUFFER_NUMBER Invalid task buffer number specified. + * @retval BSP_SWINT_ERR_TASK_EXECUTING Attempt to manipulate a task that is running. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function performs software interrupt control in response to commands. Refer the application note for + * the operation of each command. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * Do not change the interrupt priority level (IPR) while a software interrupt is being processed.\n + * When the BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY command is run, interrupts are disabled temporarily in order to set + * the interrupt priority level (IPR).\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right.\n + * If a software interrupt is generated while this function has the access control right, the software interrupt + * cannot obtain the access control right and interrupt processing ends with the task remaining unexecuted. For this + * reason, after returning from a software interrupt the interrupt request is cleared regardless of whether a task has + * been set in the task buffer. To avoid this, setting of the interrupt request occurs at the end of the processing of + * the BSP_SWINT_CMD_CLEAR_TASK and BSP_SWINT_CMD_CLEAR_ALL_TASK commands. Nevertheless, since all task buffers are + * cleared when processing of the BSP_SWINT_CMD_CLEAR_ALL_TASK command completes successfully, the interrupt request + * is not set. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + ret = BSP_SWINT_SUCCESS; + + /* Execute Command */ + switch (cmd) + { + case BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION: + bsp_swint_get_interrupt_information(unit, p_args); + break; + + case BSP_SWINT_CMD_ENABLE_INTERRUPT: + bsp_swint_enable_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_INTERRUPT: + bsp_swint_disable_interrupt(unit); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY: + ret = bsp_swint_set_interrupt_priority(unit, p_args); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_REQUEST: + bsp_swint_set_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST: + bsp_swint_clear_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT: + bsp_swint_enable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT: + bsp_swint_disable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_CLEAR_TASK: + ret = bsp_swint_clear_task(unit, p_args); + break; + + case BSP_SWINT_CMD_CLEAR_ALL_TASK: + ret = bsp_swint_clear_all_task(unit); + break; + + case BSP_SWINT_CMD_GET_ALL_TASK_STATUS: + bsp_swint_get_all_task_status(unit, p_args); + break; + + case BSP_SWINT_CMD_GET_USED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)s_bsp_swint_buf_used[unit]; + break; + + case BSP_SWINT_CMD_GET_UNUSED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)(BSP_CFG_SWINT_TASK_BUFFER_NUMBER - s_bsp_swint_buf_used[unit]); + break; + + default: + ret = BSP_SWINT_ERR_INVALID_CMD; + break; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_access_control +* Description : Get access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Get access. +* false - Failed to get access. +***********************************************************************************************************************/ +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Get Access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == p_args->status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_get_access_control() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_release_access_control +* Description : Release access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Release access. +* false - Failed to release access. +***********************************************************************************************************************/ +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Release access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == g_bsp_swint_access_ctrl[unit].status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_release_access_control() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_dummy_task +* Description : Dummy task. +* Arguments : p_dummy_context - Dummy arguments. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_dummy_task(void * p_dummy_context) +{ + R_BSP_NOP(); +} /* End of function bsp_swint_dummy_task() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_execute_task +* Description : Execute task of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit) +{ + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Enable Multiple Interrupt */ + if (BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT == s_bsp_swint_nested_int_status[unit]) + { + R_BSP_InterruptsEnable(); + } + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + /* WAIT_LOOP */ + while (0 != s_bsp_swint_buf_used[unit]) + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_bottom[unit]) + { + s_bsp_swint_buf_bottom[unit] = 0; + } + else + { + s_bsp_swint_buf_bottom[unit]++; + } + + if (BSP_SWINT_TASK_STATUS_REQUESTED == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "EXECUTING" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_EXECUTING; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Execute Task */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_taskAddr(s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_context); + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "COMPLETED" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_COMPLETED; + } + } + + if (0 != s_bsp_swint_buf_used[unit]) + { + s_bsp_swint_buf_used[unit]--; + } + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } +} /* End of function bsp_swint_execute_task() */ + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint_isr +* Description : Software interrupt function. (Unit1) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT1); +} /* End of function bsp_swint_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint2_isr +* Description : Software interrupt function. (Unit2) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint2_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT2); +} /* End of function bsp_swint2_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h new file mode 100644 index 000000000..0ce9ba056 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h @@ -0,0 +1,138 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.h +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* Multiple inclusion prevention macro */ +#ifndef SOFTWARE_INTERRUPT_H +#define SOFTWARE_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +typedef enum e_bsp_swint_unit +{ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + BSP_SWINT_UNIT1, +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + BSP_SWINT_UNIT2, +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + BSP_SWINT_UNIT_MAX +} e_bsp_swint_unit_t; + +typedef enum e_bsp_swint_err +{ + BSP_SWINT_SUCCESS = 0, + BSP_SWINT_ERR_ALREADY_OPEN, + BSP_SWINT_ERR_NOT_CLOSED, + BSP_SWINT_ERR_INVALID_UNIT, + BSP_SWINT_ERR_INVALID_IPR, + BSP_SWINT_ERR_INVALID_CMD, + BSP_SWINT_ERR_INVALID_TASK, + BSP_SWINT_ERR_INVALID_BUFFER_NUMBER, + BSP_SWINT_ERR_TASK_EXECUTING, + BSP_SWINT_ERR_FULL_BUFFER, + BSP_SWINT_ERR_ACCESS_REJECTION +} e_bsp_swint_err_t; + +typedef enum e_bsp_swint_cmd +{ + BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION = 0, + BSP_SWINT_CMD_ENABLE_INTERRUPT, + BSP_SWINT_CMD_DISABLE_INTERRUPT, + BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, + BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, + BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, + BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_CLEAR_TASK, + BSP_SWINT_CMD_CLEAR_ALL_TASK, + BSP_SWINT_CMD_GET_ALL_TASK_STATUS, + BSP_SWINT_CMD_GET_USED_BUFFER, + BSP_SWINT_CMD_GET_UNUSED_BUFFER +} e_bsp_swint_cmd_t; + +typedef struct st_bsp_swint_int_info +{ + uint8_t ipr; + uint8_t ien; + uint8_t ir; + uint8_t nested_int; +} st_bsp_swint_int_info_t; + +typedef enum e_bsp_swint_task_status +{ + BSP_SWINT_TASK_STATUS_NO_REQUEST = 0, + BSP_SWINT_TASK_STATUS_REQUESTED, + BSP_SWINT_TASK_STATUS_EXECUTING, + BSP_SWINT_TASK_STATUS_COMPLETED +} e_bsp_swint_task_status_t; + +typedef struct st_bsp_swint_task +{ + e_bsp_swint_task_status_t status; + void (*p_taskAddr)(void *p_task_args); + void *p_context; +} st_bsp_swint_task_t; + +typedef struct st_bsp_swint_task_buffer +{ + uint8_t number; +} st_bsp_swint_task_buffer_t; + +typedef struct st_bsp_swint_access_control +{ + int32_t status; +} st_bsp_swint_access_control_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task); +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args); + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rtos.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rtos.h new file mode 100644 index 000000000..6d4d8268d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rtos.h @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rtos.h +* Description : This module implements functions of rtos. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.10 Added include file and macro definitions for Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_config.h" + +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ +#elif BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "queue.h" +#include "croutine.h" +#include "timers.h" +#include "event_groups.h" +#include "freertos_start.h" +#elif BSP_CFG_RTOS_USED == 2 /* SEGGER embOS */ +#elif BSP_CFG_RTOS_USED == 3 /* Micrium MicroC/OS */ +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#include "kernel.h" +#include "kernel_id.h" + +#define RENESAS_RI600V4 0 +#define RENESAS_RI600PX 1 + +#undef BSP_CFG_RTOS_SYSTEM_TIMER +#define BSP_CFG_RTOS_SYSTEM_TIMER _RI_CLOCK_TIMER +#else +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RTOS_H +#define R_RTOS_H + +#endif /* R_RTOS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h new file mode 100644 index 000000000..d03359072 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h @@ -0,0 +1,1638 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_compiler.h +* Description : This is a file for integrating the definitions of different functions for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.01 Modified definition of __RX_DPFPU_INSNS__ to __RX_DFPU_INSNS__ for GNUC. +* Modified definition of TFU for GNUC. +* Modified comment of TFU for ICCRX. +* Added include of r_bsp_config.h. +* Changed the following definitions for added support of Renesas RTOS(RI600V4 or RI600PX). +* - R_BSP_SECNAME_INTVECTTBL +* - R_BSP_SECNAME_EXCEPTVECTTBL +* - R_BSP_SECNAME_FIXEDVECTTBL +* - R_BSP_PRAGMA_INTERRUPT +* - R_BSP_PRAGMA_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_FUNCTION +* - R_BSP_ATTRIB_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_DEFAULT +* - R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT +* Changed the following definitions to definition without __no_init for ICCRX so that +* there is no warning when the initial value is specified. +* - _R_BSP_ATTRIB_SECTION_CHANGE_C1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C8 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D8 +* : 17.12.2019 1.02 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_common.h" +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_COMPILER_H +#define R_RX_COMPILER_H + +/* ========== Check Compiler ========== */ +#if defined(__CCRX__) + /* supported */ +#elif defined(__GNUC__) + /* supported */ +#elif defined(__ICCRX__) + /* supported */ +#else + #error "Unrecognized compiler" +#endif + + +/* ========== Macros ========== */ +#if defined(__CCRX__) + +/* #define __RX 1 */ /* This is automatically defined by CCRX. */ +/* #define __LIT 1 */ /* This is automatically defined by CCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by CCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by CCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by CCRX. */ +/* #define __DPFPU 1 */ /* This is automatically defined by CCRX. */ + +#elif defined(__GNUC__) + +#if !defined(__RX) +#define __RX 1 +#endif + +#if defined(__RX_LITTLE_ENDIAN__) +#if !defined(__LIT) +#define __LIT 1 +#endif +#elif defined(__RX_BIG_ENDIAN__) +#if !defined(__BIG) +#define __BIG 1 +#endif +#endif + +#if defined(__RX_FPU_INSNS__) +#if !defined(__FPU) +#define __FPU 1 +#endif +#endif + +#if defined(__RXv1__) +#if !defined(__RXV1) +#define __RXV1 1 +#endif +#endif + +#if defined(__RXv2__) +#if !defined(__RXV2) +#define __RXV2 1 +#endif +#endif + +#if defined(__RXv3__) +#if !defined(__RXV3) +#define __RXV3 1 +#endif +#endif + +/* #define __TFU 1 */ /* This is automatically defined by GNUC. */ + +#if defined(__RX_DFPU_INSNS__) +#if !defined(__DPFPU) +#define __DPFPU 1 +#endif +#endif + +#elif defined(__ICCRX__) + +#if !defined(__RX) +#define __RX 1 +#endif + +/* #define __LIT 1 */ /* This is automatically defined by ICCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by ICCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by ICCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __DPFPU 1 */ /* Not yet supported. */ + +#endif + + +/* ========== Keywords ========== */ +#if !(defined(__CCRX__) && defined(__cplusplus)) +#define R_BSP_PRAGMA(...) _Pragma(#__VA_ARGS__) +#else +/* CC-RX' C++ mode does not support Pragma operator and variadic macros */ +#define R_BSP_PRAGMA(x) +#endif + +#if defined(__CCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile __evenaccess +#define R_BSP_EVENACCESS __evenaccess +#define R_BSP_EVENACCESS_SFR __evenaccess +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS /* none */ +#define R_BSP_EVENACCESS_SFR /* none */ +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__ICCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS volatile +#define R_BSP_EVENACCESS_SFR __sfr +#define R_BSP_VOLATILE_SFR volatile __sfr +#define R_BSP_SFR __sfr + +#endif + + +/* ========== Sections ========== */ + +/* ---------- Operators ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP(name) __sectop(#name) +#define R_BSP_SECEND(name) __secend(#name) +#define R_BSP_SECSIZE(name) __secsize(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP(name) ((void *)name##_start) +#define R_BSP_SECEND(name) ((void *)name##_end) +#define R_BSP_SECSIZE(name) ((size_t)((uint8_t *)R_BSP_SECEND(name) - (uint8_t *)R_BSP_SECTOP(name))) + +#define R_BSP_SECTION_OPERATORS_INIT(name) extern uint8_t name##_start[], name##_end[]; + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP(name) __section_begin(#name) +#define R_BSP_SECEND(name) __section_end(#name) +#define R_BSP_SECSIZE(name) __section_size(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) R_BSP_PRAGMA(section = #name); + +#endif + +/* ---------- Names ---------- */ +#if defined(__CCRX__) + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_INTVECTTBL "INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_INTVECTTBL "C$VECT" +#endif /* BSP_CFG_RTOS_USED */ + +#if defined(__RXV2) || defined(__RXV3) +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "EXCEPTVECT" +#endif /* BSP_CFG_RTOS_USED */ +#define R_BSP_SECNAME_RESETVECT "RESETVECT" +#else /* __RXV1 */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIXEDVECT" +#endif /* BSP_CFG_RTOS_USED */ +#endif /* defined(__RXV2) || defined(__RXV3) */ +#define R_BSP_SECNAME_UBSETTINGS "UBSETTINGS" + +#elif defined(__GNUC__) + +#define R_BSP_SECNAME_INTVECTTBL ".rvectors" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exvectors" +#define R_BSP_SECNAME_RESETVECT ".fvectors" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".fvectors" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#elif defined(__ICCRX__) + +#define R_BSP_SECNAME_INTVECTTBL ".inttable" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exceptvect" +#define R_BSP_SECNAME_RESETVECT ".resetvect" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".exceptvect" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#endif + +/* ---------- Addresses ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP_INTVECTTBL __sectop(R_BSP_SECNAME_INTVECTTBL) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL __sectop(R_BSP_SECNAME_EXCEPTVECTTBL) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP_INTVECTTBL ((void *)rvectors_start) +extern void * const rvectors_start[]; +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL ((void *)exvectors_start) +extern void * const exvectors_start[]; +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP_INTVECTTBL /* none */ +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL /* none */ +#endif + +#endif + + +/* ========== #pragma Directive ========== */ + +/* ---------- Stack Size ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(_size) _R_BSP_PRAGMA_STACKSIZE_SI(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SI(_size) __R_BSP_PRAGMA_STACKSIZE_SI##_size +#define __R_BSP_PRAGMA_STACKSIZE_SI(size) R_BSP_PRAGMA(stacksize si=size) +#define R_BSP_PRAGMA_STACKSIZE_SU(_size) _R_BSP_PRAGMA_STACKSIZE_SU(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SU(_size) __R_BSP_PRAGMA_STACKSIZE_SU##_size +#define __R_BSP_PRAGMA_STACKSIZE_SU(size) R_BSP_PRAGMA(stacksize su=size) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) static uint8_t istack_area[size] __attribute__((section(".r_bsp_istack"), used)); +#define R_BSP_PRAGMA_STACKSIZE_SU(size) static uint8_t ustack_area[size] __attribute__((section(".r_bsp_ustack"), used)); + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) /* none */ +#define R_BSP_PRAGMA_STACKSIZE_SU(size) /* none */ + +#endif + +/* ---------- Section Switch (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(section C UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT R_BSP_PRAGMA(section C EXCEPTVECT) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT R_BSP_PRAGMA(section C RESETVECT) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT R_BSP_PRAGMA(section C FIXEDVECT) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS __attribute__((section(R_BSP_SECNAME_UBSETTINGS))) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT __attribute__((section(R_BSP_SECNAME_EXCEPTVECTTBL))) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT __attribute__((section(R_BSP_SECNAME_RESETVECT))) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT __attribute__((section(R_BSP_SECNAME_FIXEDVECTTBL))) +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(location=R_BSP_SECNAME_UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT /* none */ +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT /* none */ +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT /* none */ +#endif +#endif + +/* ---------- Section Switch (part2) ---------- */ +#if defined(__CCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(type, section_name) R_BSP_PRAGMA(section type section_name) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(type, section_name) R_BSP_PRAGMA(section type section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P, P##section_tag) + +#if !defined(__cplusplus) +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#else +/* CC-RX' C++ mode does not support variadic macros */ +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, align) _R_BSP_ATTRIB_SECTION_CHANGE_##type##align(section_tag) +#endif + +#define R_BSP_ATTRIB_SECTION_CHANGE_END R_BSP_PRAGMA(section) + +#elif defined(__GNUC__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) __attribute__((section(#section_name))) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) __attribute__((section(#section_name))) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#elif defined(__ICCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) R_BSP_PRAGMA(location=#section_name)\ + __no_init +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) R_BSP_PRAGMA(location=#section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#endif + +/* ---------- Interrupt Function Creation ---------- */ +#if defined(__CCRX__) + +/* Standard */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void); + +#else /* BSP_CFG_RTOS_USED != 4*/ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + static void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because of no corresponding keyword */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT +#else /* BSP_CFG_RTOS_USED !=4 */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because of no corresponding keyword */ +#endif /* BSP_CFG_RTOS_USED */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + static void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + static void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* only this one because of no corresponding keyword */ + +/* Default */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) void function_name(void); +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#elif defined(__GNUC__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((interrupt)); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((interrupt, used)); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because __attribute__((interrupt)) prevents GNURX from generating vector */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because __attribute__((interrupt, used)) prevents GNURX from generating vector */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))) \ + __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)) \ + __attribute__((fast_interrupt, used)); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((fast_interrupt, used)); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* __attribute__((interrupt(fast))) Not necessary, + but Don't forget a R_BSP_PRAGMA_FAST_INTERRUPT() declaration */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* __attribute__((interrupt(fast)), used) Not necessary, + but Don't forget a R_BSP_PRAGMA_STATIC_FAST_INTERRUPT() declaration */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"), used)); + +#elif defined(__ICCRX__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __interrupt void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static __interrupt void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __fast_interrupt void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static __fast_interrupt void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static __interrupt void function_name(void); + +#endif + +/* ---------- Inline Expansion of Function ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + static + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_INLINE(function_name) inline extern __attribute__((always_inline)) +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) inline static __attribute__((always_inline)) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + static + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__GNUC__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) extern __attribute__((naked, noinline)) +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) static __attribute__((naked, noinline)) + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__ICCRX__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* ICCRX requires __task not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* ICCRX requires __task not only at a function declaration but also at a function definition */ + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part2) ---------- */ +#if defined(__CDT_PARSER__) + +#define R_BSP_ASM(...) /* none */ +#define R_BSP_ASM_LAB_NEXT(n) /* none */ +#define R_BSP_ASM_LAB_PREV(n) /* none */ +#define R_BSP_ASM_LAB(n_colon) /* none */ +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#else + +#if defined(__CCRX__) + +#if !defined(__cplusplus) +#define R_BSP_ASM(...) __VA_ARGS__ +#else +/* CC-RX' C++ mode does not support variadic macros */ +#endif +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#elif defined(__GNUC__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN __asm__ volatile ( +#define R_BSP_ASM_END R_BSP_ASM(rts)); + +#elif defined(__ICCRX__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) _lab##n +#define R_BSP_ASM_LAB_PREV(n) _lab##n +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) +#define R_BSP_ASM_BEGIN asm( +#define R_BSP_ASM_END ); + +#endif + +#endif /* defined(__CDT_PARSER__) */ + +/* ---------- Inline Expansion of Assembly-Language Function (part3) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) /* no way */ +#define R_BSP_ASM_INTERNAL_NOT_USED(p) /* no way */ + +#elif defined(__GNUC__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#elif defined(__ICCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#endif + +/* ---------- Bit Field Order Specification ---------- */ + +/* ---------- bit_order=left ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order left)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=reversed_disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- bit_order=right ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order right)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- Alignment Value Specification for Structure Members and Class Members ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(unpack) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(packoption) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#endif + +/* ========== Rename Functions ========== */ + +#if defined(__CCRX__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ + +#elif defined(__GNUC__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC_Prg + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ + +#elif defined(__ICCRX__) + +#define R_BSP_POR_FUNCTION(name) extern int name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION _iar_program_start +#define R_BSP_STARTUP_FUNCTION __low_level_init + +#define R_BSP_UB_POR_FUNCTION(name) extern int name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION _iar_program_start + +#define R_BSP_MAIN_FUNCTION _iar_main_call + +#define _INITSCT __iar_data_init2 +#define excep_supervisor_inst_isr __privileged_handler +#define excep_access_isr __excep_access_inst +#define excep_undefined_inst_isr __undefined_handler +#define excep_floating_point_isr _float_placeholder +#define non_maskable_isr __NMI_handler +#define undefined_interrupt_source_isr __undefined_interrupt_source_handler + +#endif + +#endif /* R_RX_COMPILER_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c new file mode 100644 index 000000000..d344aed03 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c @@ -0,0 +1,994 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.c +* Description : Defines built-in functions that are in CCRX but not in the GCC and IAR compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.01 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* Added the below functions. +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.02 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 10.12.2019 1.03 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* : 17.12.2019 1.04 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_rx_compiler.h" +#include "r_rx_intrinsic_functions.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpc(uint32_t *data); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_extb(uint32_t *data); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_hi_long(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_mi_long(uint32_t *data); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_dpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_decnt(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_depc(uint32_t *ret); +#endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_BSP_Max +* Description : Selects the greater of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The greater value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2) +{ + return (data1 > data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_Min +* Description : Selects the smaller of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The smaller value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Min(signed long data1, signed long data2) +{ + return (data1 < data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_B +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_W +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_L +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeftWithCarry +* Description : Rotates data including the C flag to left by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* Return Value : data - Result of 1-bit left rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) +{ + __asm("rolc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRightWithCarry +* Description : Rotates data including the C flag to right by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* Return Value : data - Result of 1-bit right rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRightWithCarry(unsigned long data) +{ + __asm("rorc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeft +* Description : Rotates data to left by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* num - Number of bits to be rotated. +* Return Value : data - Result of num-bit left rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) +{ + __asm("rotl %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRight +* Description : Rotates data to right by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* num - Number of bits to be rotated. +* Return Value : result - Result of num-bit right rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num) +{ + __asm("rotr %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SignedMultiplication +* Description : Performs signed multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of signed multiplication. (signed 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) +{ + return ((signed long long)data1) * ((signed long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_UnsignedMultiplication +* Description : Performs unsigned multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of unsigned multiplication. (unsigned 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) +{ + return ((unsigned long long)data1) * ((unsigned long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function name: R_BSP_ChangeToUserMode +* Description : Switches to user mode. The PSW will be changed as following. +* Before Execution After Execution +* PSW.PM PSW.U PSW.PM PSW.U +* 0 (supervisor mode) 0 (interrupt stack) --> 1 (user mode) 1 (user stack) +* 0 (supervisor mode) 1 (user stack) --> 1 (user mode) 1 (user stack) +* 1 (user mode) 1 (user stack) --> NO CHANGE +* 1 (user mode) 0 (interrupt stack)) <== N/A +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_ChangeToUserMode) +void R_BSP_ChangeToUserMode(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM(;_R_BSP_Change_PSW_PM_to_UserMode: ) + R_BSP_ASM( PUSH.L R1 ; push the R1 value ) + R_BSP_ASM( MVFC PSW, R1 ; get the current PSW value ) + R_BSP_ASM( BTST #20, R1 ; check PSW.PM ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_NEXT(0);_psw_pm_is_user_mode ) + R_BSP_ASM(;_psw_pm_is_supervisor_mode: ) + R_BSP_ASM( BSET #20, R1 ; change PM = 0(Supervisor Mode) --> 1(User Mode) ) + R_BSP_ASM( PUSH.L R2 ; push the R2 value ) + R_BSP_ASM( MOV.L R0, R2 ; move the current SP value to the R2 value ) + R_BSP_ASM( XCHG 8[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the return address value of caller and the PSW value) ) + R_BSP_ASM( XCHG 4[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the R1 value of stack and the return address value of caller) ) + R_BSP_ASM( POP R2 ; pop the R2 value of stack ) + R_BSP_ASM( RTE ) + R_BSP_ASM_LAB(0:;_psw_pm_is_user_mode: ) + R_BSP_ASM( POP R1 ; pop the R1 value of stack ) + R_BSP_ASM( ;RTS ) + R_BSP_ASM_END +} /* End of function R_BSP_ChangeToUserMode() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetACC +* Description : Sets a value to ACC. +* Arguments : data - Value to be set to ACC. +* Return Value : none +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +void R_BSP_SetACC(signed long long data) +{ +#if defined(__GNUC__) + __builtin_rx_mvtachi(data >> 32); + __builtin_rx_mvtaclo(data & 0xFFFFFFFF); +#elif defined(__ICCRX__) + int32_t data_hi; + int32_t data_lo; + + data_hi = (int32_t)(data >> 32); + data_lo = (int32_t)(data & 0x00000000FFFFFFFF); + + R_BSP_MoveToAccHiLong(data_hi); + R_BSP_MoveToAccLoLong(data_lo); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetACC +* Description : Refers to the ACC value. +* Arguments : none +* Return Value : result - ACC value. +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_GetACC(void) +{ +#if defined(__GNUC__) + signed long long result = ((signed long long)__builtin_rx_mvfachi()) << 32; + result |= (((signed long long)__builtin_rx_mvfacmi()) << 16) & 0xFFFF0000; + return result; +#elif defined(__ICCRX__) + int64_t result; + + result = ((int64_t)R_BSP_MoveFromAccHiLong()) << 32; + result |= (((int64_t)R_BSP_MoveFromAccMiLong()) << 16) & 0xFFFF0000; + + return result; +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_2byte +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* four bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, the contents of ACC are +* fetched by the MVFACMI instruction and used as the return value of the intrinsic function. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : S(data1[n] * data2[n]) result. +***********************************************************************************************************************/ +#if defined(__GNUC__) +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + return __builtin_rx_mvfacmi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint1 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* The macw1 function performs rounding with the "RACW #1" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(1); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint2 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* the macw2 function performs rounding with the "RACW #2" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(2); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPSW +* Description : Sets a value to BPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPSW) +void R_BSP_SetBPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpsw +* Description : Refers to the BPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpsw) +void bsp_get_bpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPSW +* Description : Refers to the BPSW value. +* Arguments : none +* Return Value : BPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetBPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPC +* Description : Sets a value to BPC. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPC) +void R_BSP_SetBPC(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPC ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPC() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpc +* Description : Refers to the BPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpc) +void bsp_get_bpc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpc() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPC +* Description : Refers to the BPC value. +* Arguments : none +* Return Value : BPC value +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetBPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpc((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetBPC() */ + +#ifdef BSP_MCU_EXCEPTION_TABLE +/*********************************************************************************************************************** +* Function Name: R_BSP_SetEXTB +* Description : Sets a value for EXTB. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetEXTB) +void R_BSP_SetEXTB(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, EXTB ) + R_BSP_ASM_END +} /* End of function R_BSP_SetEXTB() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_extb +* Description : Refers to the EXTB value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_extb) +void bsp_get_extb(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC EXTB, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_extb() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetEXTB +* Description : Refers to the EXTB value. +* Arguments : none +* Return Value : EXTB value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetEXTB(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_extb((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetEXTB() */ +#endif /* BSP_MCU_EXCEPTION_TABLE */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccHiLong +* Description : This function moves the contents of src to the higher-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccHiLong) +void R_BSP_MoveToAccHiLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACHI R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccLoLong +* Description : This function moves the contents of src to the lower-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccLoLong) +void R_BSP_MoveToAccLoLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACLO R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccLoLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_hi_long +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_hi_long) +void bsp_move_from_acc_hi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACHI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_hi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccHiLong +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : none +* Return Value : The higher-order 32 bits of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccHiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_hi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_mi_long +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_mi_long) +void bsp_move_from_acc_mi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACMI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_mi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccMiLong +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : none +* Return Value : The contents of bits 47 to 16 of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccMiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_mi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccMiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitSet +* Description : Sets the specified one bit in the specified 1-byte area to 1. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitSet) +void R_BSP_BitSet(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BSET R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitSet() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitClear +* Description : Sets the specified one bit in the specified 1-byte area to 0. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitClear) +void R_BSP_BitClear(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BCLR R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitClear() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitReverse +* Description : Reverses the value of the specified one bit in the specified 1-byte area. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitReverse) +void R_BSP_BitReverse(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BNOT R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitReverse() */ + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDPSW +* Description : Sets a value to DPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDPSW) +void R_BSP_SetDPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_dpsw +* Description : Refers to the DPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_dpsw) +void bsp_get_dpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_dpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDPSW +* Description : Refers to the DPSW value. +* Arguments : none +* Return Value : DPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_dpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDECNT +* Description : Sets a value to DECNT. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDECNT) +void R_BSP_SetDECNT(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DECNT ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_decnt +* Description : Refers to the DECNT value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_decnt) +void bsp_get_decnt(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DECNT, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDECNT +* Description : Refers to the DECNT value. +* Arguments : none +* Return Value : DECNT value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDECNT(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_decnt((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_depc +* Description : Refers to the DEPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_depc) +void bsp_get_depc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DEPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDEPC +* Description : Refers to the DEPC value. +* Arguments : none +* Return Value : DEPC value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetDEPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_depc((uint32_t *)&ret); + return (void *)ret; +} /* End of function R_BSP_GetDECNT() */ +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +/*********************************************************************************************************************** +* Function Name: R_BSP_InitTFU +* Description : Initialize arithmetic unit for trigonometric functions. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_InitTFU) +void R_BSP_InitTFU(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R1 ) + R_BSP_ASM( MOV.L #81400H, R1 ) + R_BSP_ASM( MOV.B #7, [R1] ) + R_BSP_ASM( MOV.B #7, 1[R1] ) + R_BSP_ASM( POP R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_InitTFU() */ + +#ifdef __FPU +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSine_Cosine +* Description : Uses the trigonometric function unit to calculate the sine and cosine of an angle at the same time +* (single precision). +* Arguments : f - Value in radians from which to calculate the sine and cosine +* : sin - Address for storing the result of the sine operation +* : cos - Address for storing the result of the cosine operation +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcSine_Cosine) +void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R4 ) + R_BSP_ASM( MOV.L #81410H, R4 ) + R_BSP_ASM( MOV.L R1, 4[R4] ) + R_BSP_ASM( MOV.L 4[R4], [R2] ) + R_BSP_ASM( MOV.L [R4], [R3] ) + R_BSP_ASM( POP R4 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcSine_Cosine() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcAtan_SquareRoot +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of +* the sum of squares of these values at the same time (single precision). +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* atan2 - Address for storing the result of the arc tangent operation for y/x +* hypot - Address for storing the result of the square root of the sum of squares of x and y +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcAtan_SquareRoot) +void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSHM R5-R6 ) + R_BSP_ASM( MOV.L #81418H, R5 ) + R_BSP_ASM( MOV.L R2, [R5] ) + R_BSP_ASM( MOV.L R1, 4[R5] ) + R_BSP_ASM( MOV.L 4[R5], [R3] ) + R_BSP_ASM( MOV.L [R5], R6 ) + R_BSP_ASM( FMUL #3F1B74EEH, R6 ) + R_BSP_ASM( MOV.L R6, [R4] ) + R_BSP_ASM( POPM R5-R6 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcAtan_SquareRoot() */ +#endif /* __FPU */ +#endif /* __TFU */ +#endif /* BSP_MCU_TRIGONOMETRIC */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h new file mode 100644 index 000000000..1f418eaa4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.h +* Description : This is a file for integrating the definitions of built-in functions that differ for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.10 Added the following function. +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.11 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 08.10.2019 1.12 Modified the followind definition of intrinsic function of TFU for ICCRX. +* - R_BSP_INIT_TFU +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* : 17.12.2019 1.13 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_INTRINSIC_FUNCTIONS_H +#define R_RX_INTRINSIC_FUNCTIONS_H + +/* ---------- Maximum value and minimum value ---------- */ +#if defined(__CCRX__) + +/* signed long max(signed long data1, signed long data2) */ +#define R_BSP_MAX(x, y) max((signed long)(x), (signed long)(y)) +/* signed long min(signed long data1, signed long data2) */ +#define R_BSP_MIN(x, y) min((signed long)(x), (signed long)(y)) + +#elif defined(__GNUC__) + +/* signed long R_BSP_Max(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MAX(x, y) R_BSP_Max((signed long)(x), (signed long)(y)) +/* signed long R_BSP_Min(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MIN(x, y) R_BSP_Min((signed long)(x), (signed long)(y)) + +#elif defined(__ICCRX__) + +/* signed long __MAX(signed long, signed long) */ +#define R_BSP_MAX(x, y) __MAX((signed long)(x), (signed long)(y)) +/* signed long __MIN(signed long, signed long) */ +#define R_BSP_MIN(x, y) __MIN((signed long)(x), (signed long)(y)) + +#endif + +/* ---------- Byte switch ---------- */ +#if defined(__CCRX__) + +/* unsigned long revl(unsigned long data) */ +#define R_BSP_REVL(x) revl((unsigned long)(x)) +/* unsigned long revw(unsigned long data) */ +#define R_BSP_REVW(x) revw((unsigned long)(x)) + +#elif defined(__GNUC__) + +/* uint32_t __builtin_bswap32(uint32_t x) */ +#define R_BSP_REVL(x) __builtin_bswap32((uint32_t)(x)) +/* int __builtin_rx_revw(int) */ +#define R_BSP_REVW(x) (unsigned long)__builtin_rx_revw((int)(x)) + +#elif defined(__ICCRX__) + +/* unsigned long __REVL(unsigned long) */ +#define R_BSP_REVL(x) __REVL((unsigned long)(x)) +/* unsigned long __REVW(unsigned long) */ +#define R_BSP_REVW(x) __REVW((unsigned long)(x)) + +#endif + +/* ---------- Data Exchange ---------- */ +#if defined(__CCRX__) + +/* void xchg(signed long *data1, signed long *data2) */ +#define R_BSP_EXCHANGE(x, y) xchg((signed long *)(x), (signed long *)(y)) + +#elif defined(__GNUC__) + +/* void __builtin_rx_xchg (int *, int *) */ +#define R_BSP_EXCHANGE(x, y) __builtin_rx_xchg((int *)(x), (int *)(y)) + +#elif defined(__ICCRX__) + +/* void _builtin_xchg(signed long *, signed long *) */ +#define R_BSP_EXCHANGE(x, y) _builtin_xchg((signed long *)(x), (signed long *)(y)) + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__GNUC__) + +/* long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAB(w, x, y, z) R_BSP_MulAndAccOperation_B((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAW(w, x, y, z) R_BSP_MulAndAccOperation_W((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAL(w, x, y, z) R_BSP_MulAndAccOperation_L((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__ICCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#endif + +/* ---------- Rotation ---------- */ +#if defined(__CCRX__) + +/* unsigned long rolc(unsigned long data) */ +#define R_BSP_ROLC(x) rolc((unsigned long)(x)) +/* unsigned long rorc(unsigned long data) */ +#define R_BSP_RORC(x) rorc((unsigned long)(x)) +/* unsigned long rotl(unsigned long data, unsigned long num) */ +#define R_BSP_ROTL(x, y) rotl((unsigned long)(x), (unsigned long)(y)) +/* unsigned long rotr (unsigned long data, unsigned long num) */ +#define R_BSP_ROTR(x, y) rotr((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_ROLC(x) R_BSP_RotateLeftWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateRightWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_RORC(x) R_BSP_RotateRightWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTL(x, y) R_BSP_RotateLeft((unsigned long)(x), (unsigned long)(y)) +/* unsigned long R_BSP_RotateRight (unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTR(x, y) R_BSP_RotateRight((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* unsigned long __ROLC(unsigned long) */ +#define R_BSP_ROLC(x) __ROLC((unsigned long)(x)) +/* unsigned long __RORC(unsigned long) */ +#define R_BSP_RORC(x) __RORC((unsigned long)(x)) +/* unsigned long __ROTL(unsigned long, unsigned long) */ +#define R_BSP_ROTL(x, y) __ROTL((unsigned long)(y), (unsigned long)(x)) +/* unsigned long __ROTR(unsigned long, unsigned long) */ +#define R_BSP_ROTR(x, y) __ROTR((unsigned long)(y), (unsigned long)(x)) + +#endif + +/* ---------- Special Instructions ---------- */ +#if defined(__CCRX__) + +/* void brk(void) */ +#define R_BSP_BRK() brk() +/* void int_exception(signed long num) */ +#define R_BSP_INT(x) int_exception((signed long)(x)) +/* void wait(void) */ +#define R_BSP_WAIT() wait() +/* void nop(void) */ +#define R_BSP_NOP() nop() + +#elif defined(__GNUC__) + +/* void __builtin_rx_brk (void) */ +#define R_BSP_BRK() __builtin_rx_brk() +/* void __builtin_rx_int (int) */ +#define R_BSP_INT(x) __builtin_rx_int((int)(x)) +/* void __builtin_rx_wait (void) */ +#define R_BSP_WAIT() __builtin_rx_wait() +/* __asm("nop") */ +#define R_BSP_NOP() __asm("nop") + +#elif defined(__ICCRX__) + +/* void __break(void) */ +#define R_BSP_BRK() __break() +/* void __software_interrupt(unsigned char) */ +#define R_BSP_INT(x) __software_interrupt((unsigned char)(x)) +/* void __wait_for_interrupt(void) */ +#define R_BSP_WAIT() __wait_for_interrupt() +/* void __no_operation(void) */ +#define R_BSP_NOP() __no_operation() + +#endif + +/* ---------- Processor interrupt priority level (IPL) ---------- */ +#if defined(__CCRX__) + +/* void set_ipl(signed long level) */ +#define R_BSP_SET_IPL(x) set_ipl((signed long)(x)) +/* unsigned char get_ipl(void) */ +#define R_BSP_GET_IPL() get_ipl() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtipl (int) */ +#define R_BSP_SET_IPL(x) __builtin_rx_mvtipl((int)(x)) +/* uint32_t R_BSP_CpuInterruptLevelRead (void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_IPL() (unsigned char)R_BSP_CpuInterruptLevelRead() + +#elif defined(__ICCRX__) + +/* void __set_interrupt_level(__ilevel_t) */ +#define R_BSP_SET_IPL(x) __set_interrupt_level((__ilevel_t)(x)) +/* __ilevel_t __get_interrupt_level(void) */ +#define R_BSP_GET_IPL() (unsigned char)__get_interrupt_level() + +#endif + +/* ---------- Processor status word (PSW) ---------- */ +#if defined(__CCRX__) + +/* void set_psw(unsigned long data) */ +#define R_BSP_SET_PSW(x) set_psw((unsigned long)(x)) +/* unsigned long get_psw(void) */ +#define R_BSP_GET_PSW() get_psw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_PSW(x) __builtin_rx_mvtc(0x0, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_PSW() (unsigned long)__builtin_rx_mvfc(0x0) + +#elif defined(__ICCRX__) + +/* void __set_PSW_register(unsigned long) */ +#define R_BSP_SET_PSW(x) __set_PSW_register((unsigned long)(x)) +/* unsigned long __get_PSW_register(void) */ +#define R_BSP_GET_PSW() __get_PSW_register() + +#endif + +/* ---------- Floating-point status word (FPSW) ---------- */ +#ifdef __FPU +#if defined(__CCRX__) + +/* void set_fpsw(unsigned long data) */ +#define R_BSP_SET_FPSW(x) set_fpsw((unsigned long)(x)) +/* unsigned long get_fpsw(void) */ +#define R_BSP_GET_FPSW() get_fpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FPSW(x) __builtin_rx_mvtc(0x3, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FPSW() (unsigned long)__builtin_rx_mvfc(0x3) + +#elif defined(__ICCRX__) + +/* void __set_FPSW_register(unsigned long) */ +#define R_BSP_SET_FPSW(x) __set_FPSW_register((unsigned long)(x)) +/* unsigned long __get_FPSW_register(void) */ +#define R_BSP_GET_FPSW() __get_FPSW_register() + +#endif +#endif + +/* ---------- User Stack Pointer (USP) ---------- */ +#if defined(__CCRX__) + +/* void set_usp(void *data) */ +#define R_BSP_SET_USP(x) set_usp((void *)(x)) +/* void *get_usp(void) */ +#define R_BSP_GET_USP() get_usp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_USP(x) __builtin_rx_mvtc(0x2, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_USP() (void *)__builtin_rx_mvfc(0x2) + +#elif defined(__ICCRX__) + +/* void __set_USP_register(unsigned long) */ +#define R_BSP_SET_USP(x) __set_USP_register((unsigned long)(x)) +/* unsigned long __get_USP_register(void) */ +#define R_BSP_GET_USP() (void *)__get_USP_register() + +#endif + +/* ---------- Interrupt Stack Pointer (ISP) ---------- */ +#if defined(__CCRX__) + +/* void set_isp(void *data) */ +#define R_BSP_SET_ISP(x) set_isp((void *)(x)) +/* void *get_isp(void) */ +#define R_BSP_GET_ISP() get_isp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_ISP(x) __builtin_rx_mvtc(0xA, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_ISP() (void *)__builtin_rx_mvfc(0xA) + +#elif defined(__ICCRX__) + +/* void __set_ISP_register(unsigned long) */ +#define R_BSP_SET_ISP(x) __set_ISP_register((unsigned long)(x)) +/* unsigned long __get_ISP_register(void) */ +#define R_BSP_GET_ISP() (void *)__get_ISP_register() + +#endif + +/* ---------- Interrupt Table Register (INTB) ---------- */ +#if defined(__CCRX__) + +/* void set_intb(void *data) */ +#define R_BSP_SET_INTB(x) set_intb((void *)(x)) +/* void *get_intb(void) */ +#define R_BSP_GET_INTB() get_intb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_INTB(x) __builtin_rx_mvtc(0xC, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_INTB() (void *)__builtin_rx_mvfc(0xC) + +#elif defined(__ICCRX__) + +/* void __set_interrupt_table(unsigned long address) */ +#define R_BSP_SET_INTB(x) __set_interrupt_table((unsigned long)(x)) +/* unsigned long __get_interrupt_table(void); */ +#define R_BSP_GET_INTB() (void *)__get_interrupt_table() + +#endif + +/* ---------- Backup PSW (BPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_bpsw(unsigned long data) */ +#define R_BSP_SET_BPSW(x) set_bpsw((unsigned long)(x)) +/* unsigned long get_bpsw(void) */ +#define R_BSP_GET_BPSW() get_bpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPSW(x) __builtin_rx_mvtc(0x8, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPSW() (unsigned long)__builtin_rx_mvfc(0x8) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPSW(x) R_BSP_SetBPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetBPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPSW() R_BSP_GetBPSW() + +#endif + +/* ---------- Backup PC (BPC) ---------- */ +#if defined(__CCRX__) + +/* void set_bpc(void *data) */ +#define R_BSP_SET_BPC(x) set_bpc((void *)(x)) +/* void *get_bpc(void) */ +#define R_BSP_GET_BPC() get_bpc() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPC(x) __builtin_rx_mvtc(0x9, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPC() (void *)__builtin_rx_mvfc(0x9) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPC(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPC(x) R_BSP_SetBPC((void *)(x)) +/* void *R_BSP_GetBPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPC() R_BSP_GetBPC() + +#endif + +/* ---------- Fast Interrupt Vector Register (FINTV) ---------- */ +#if defined(__CCRX__) + +/* void set_fintv(void *data) */ +#define R_BSP_SET_FINTV(x) set_fintv((void *)(x)) +/* void *get_fintv(void) */ +#define R_BSP_GET_FINTV() get_fintv() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FINTV(x) __builtin_rx_mvtc(0xB, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FINTV() (void *)__builtin_rx_mvfc(0xB) + +#elif defined(__ICCRX__) + +/* void __set_FINTV_register(__fast_int_f) */ +#define R_BSP_SET_FINTV(x) __set_FINTV_register((__fast_int_f)(x)) +/* __fast_int_f __get_FINTV_register(void) */ +#define R_BSP_GET_FINTV() (void *)__get_FINTV_register() + +#endif + +/* ---------- Significant 64-bit multiplication ---------- */ +#if defined(__CCRX__) + +/* signed long long emul(signed long data1, signed long data2) */ +#define R_BSP_EMUL(x, y) emul((signed long)(x), (signed long)(y)) +/* unsigned long long emulu(unsigned long data1, unsigned long data2) */ +#define R_BSP_EMULU(x, y) emulu((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#endif + +/* ---------- Processor mode (PM) ---------- */ +#if defined(__CCRX__) + +/* void chg_pmusr(void) */ +#define R_BSP_CHG_PMUSR() chg_pmusr() + +#elif defined(__GNUC__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#elif defined(__ICCRX__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#endif + +/* ---------- Accumulator (ACC) ---------- */ +#if defined(__CCRX__) + +/* void set_acc(signed long long data) */ +#define R_BSP_SET_ACC(x) set_acc((signed long long)(x)) +/* signed long long get_acc(void) */ +#define R_BSP_GET_ACC() get_acc() + +#elif defined(__GNUC__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#endif + +/* ---------- Control of the interrupt enable bits ---------- */ +#if defined(__CCRX__) + +/* void setpsw_i(void) */ +#define R_BSP_SETPSW_I() setpsw_i() +/* void clrpsw_i(void) */ +#define R_BSP_CLRPSW_I() clrpsw_i() + +#elif defined(__GNUC__) + +/* void __builtin_rx_setpsw (int) */ +#define R_BSP_SETPSW_I() __builtin_rx_setpsw('I') +/* void __builtin_rx_clrpsw (int) */ +#define R_BSP_CLRPSW_I() __builtin_rx_clrpsw('I') + +#elif defined(__ICCRX__) + +/* void __enable_interrupt(void) */ +#define R_BSP_SETPSW_I() __enable_interrupt() +/* void __disable_interrupt(void) */ +#define R_BSP_CLRPSW_I() __disable_interrupt() + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long macl(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw1(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw2(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__GNUC__) + +/* long R_BSP_MulAndAccOperation_2byte(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACL(x, y, z) R_BSP_MulAndAccOperation_2byte((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint1(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW1(x, y, z) R_BSP_MulAndAccOperation_FixedPoint1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint2(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW2(x, y, z) R_BSP_MulAndAccOperation_FixedPoint2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__ICCRX__) + +/* long __macl(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) __macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw1(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) __macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw2(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) __macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#endif + +/* ---------- Exception Table Register (EXTB) ---------- */ +#ifdef BSP_MCU_EXCEPTION_TABLE +#if defined(__CCRX__) + +/* void set_extb(void *data) */ +#define R_BSP_SET_EXTB(x) set_extb((void *)(x)) +/* void *get_extb(void) */ +#define R_BSP_GET_EXTB() get_extb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_EXTB(x) __builtin_rx_mvtc(0xD, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_EXTB() (void *)__builtin_rx_mvfc(0xD) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetEXTB(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_EXTB(x) R_BSP_SetEXTB((void *)(x)) +/* void *R_BSP_GetEXTB(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_EXTB() R_BSP_GetEXTB() + +#endif +#endif + +/* ---------- Bit Manipulation ---------- */ +#if defined(__CCRX__) + +/* void __bclr(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_CLEAR(x, y) __bclr((unsigned char *)(x), (unsigned long)(y)) +/* void __bset(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_SET(x, y) __bset((unsigned char *)(x), (unsigned long)(y)) +/* void __bnot(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_REVERSE(x, y) __bnot((unsigned char *)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#elif defined(__ICCRX__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/* ---------- Double-Precision Floating-Point Status Word (DPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_dpsw(unsigned long data) */ +#define R_BSP_SET_DPSW(x) __set_dpsw((unsigned long)(x)) +/* unsigned long get_dpsw(void) */ +#define R_BSP_GET_DPSW() __get_dpsw() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#endif + +/* ---------- Double-precision floating-point exception handling operation control register (DECNT) ---------- */ +#if defined(__CCRX__) + +/* void __set_decnt(unsigned long data) */ +#define R_BSP_SET_DECNT(x) __set_decnt((unsigned long)(x)) +/* unsigned long __get_decnt(void) */ +#define R_BSP_GET_DECNT() __get_decnt() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#endif + +/* ---------- Double-precision floating-point exception program counter (DEPC) ---------- */ +#if defined(__CCRX__) + +/* void *__get_depc(void) */ +#define R_BSP_GET_DEPC() __get_depc() + +#elif defined(__GNUC__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#elif defined(__ICCRX__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#endif +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */ +#ifdef BSP_MCU_TRIGONOMETRIC +#if defined(__CCRX__) + +/* void __init_tfu(void) */ +#define R_BSP_INIT_TFU() __init_tfu() + +#elif defined(__GNUC__) + +/* void R_BSP_InitTFU(void) (This macro uses API function of BSP.) */ +#define R_BSP_INIT_TFU() R_BSP_InitTFU() + +#elif defined(__ICCRX__) + +/* Invalid for ICCRX. + Because the initilaze function of TFU is called automatically when the TFU function is called. */ +#define R_BSP_INIT_TFU() + +#endif + +/* ---------- Calculating the Sine and Cosine of an angle at the same time(single precision) ---------- */ +#if defined(__CCRX__) + +/* void __sincosf(float f, float *sin, float *cos) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) R_BSP_CalcSine_Cosine((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#endif + +/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */ +#if defined(__CCRX__) + +/* void __atan2hypotf(float y, float x, float *atan2, float *hypot) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) R_BSP_CalcAtan_SquareRoot((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#endif +#endif /* BSP_MCU_TRIGONOMETRIC */ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2); +signed long R_BSP_Min(signed long data1, signed long data2); +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2); +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2); +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2); +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data); +unsigned long R_BSP_RotateRightWithCarry(unsigned long data); +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num); +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num); +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count); +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2); +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2); +void R_BSP_SetACC(signed long long data); +signed long long R_BSP_GetACC(void); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +R_BSP_ATTRIB_INLINE_ASM void R_BSP_ChangeToUserMode(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPSW(uint32_t data); +uint32_t R_BSP_GetBPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPC(void * data); +void *R_BSP_GetBPC(void); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetEXTB(void * data); +void *R_BSP_GetEXTB(void); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitSet(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitClear(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitReverse(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccHiLong(int32_t data); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccLoLong(int32_t data); +int32_t R_BSP_MoveFromAccHiLong(void); +int32_t R_BSP_MoveFromAccMiLong(void); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDPSW(uint32_t data); +uint32_t R_BSP_GetDPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDECNT(uint32_t data); +uint32_t R_BSP_GetDECNT(void); +void *R_BSP_GetDEPC(void); +#endif +#endif +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_InitTFU(void); +#ifdef __FPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot); +#endif /* __FPU */ +#endif /* __TFU */ +#endif + +/* End of multiple inclusion prevention macro */ +#endif /* R_RX_INTRINSIC_FUNCTIONS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_typedefs.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_typedefs.h new file mode 100644 index 000000000..34f975d0b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/r_typedefs.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_typedefs.h +* Description : This has fixed-width integer and bool support for compilers that are not C99 compliant and do not have +* the header files stdint.h, stdbool.h, and stddef.h. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 18.09.2012 1.00 First Release +* : 21.06.2013 1.10 Added NULL and size_t support. +* : 22.11.2013 1.11 Changed size_t to 'unsigned long' from 'unsigned int'. +* : 28.02.2019 1.12 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +#define bool (_Bool) +#define false (0) +#define true (1) +#define NULL (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef signed long long int64_t; +typedef unsigned long long uint64_t; +typedef unsigned int _Bool; +typedef unsigned long size_t; + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/resetprg.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/resetprg.c new file mode 100644 index 000000000..d6fa1bfcd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/all/resetprg.c @@ -0,0 +1,365 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : resetprg.c +* Description : Defines post-reset routines that are used to configure the MCU prior to the main program starting. +* This is where the program counter starts on power-up or reset. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_PSW_INIT +* - BSP_PRV_FPSW_INIT +* - BSP_PRV_FPU_ROUND +* - BSP_PRV_FPU_DENOM +* Added following macro definitions. +* - BSP_PRV_DPSW_INIT +* : 26.07.2019 3.01 Added vbatt_voltage_stability_wait function. +* : 08.10.2019 3.10 Changed for added support of Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) +/* Defines MCU configuration functions used in this file */ +#include <_h_c_lib.h> +#endif /* defined(__CCRX__) */ + +/* Define the target platform */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + +#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX +#pragma section P PS +#pragma section B BS +#pragma section C CS +#pragma section D DS +#else +#include "ri_cmt.h" /* Generated by cfg600 */ +#endif /* BSP_CFG_RENESAS_RTOS_USED */ + +#else /* BSP_CFG_RTOS_USED!=4 */ + +/* Declaration of stack size. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +R_BSP_PRAGMA_STACKSIZE_SU(BSP_CFG_USTACK_BYTES) +#endif +R_BSP_PRAGMA_STACKSIZE_SI(BSP_CFG_ISTACK_BYTES) + +#endif/* BSP_CFG_RTOS_USED */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + #define BSP_PRV_PSW_INIT (0x00000000) /* Supervisor mode & Disable Interrupt */ +#else /* BSP_CFG_RTOS_USED!=4 */ +/* If the user chooses only 1 stack then the 'U' bit will not be set and the CPU will always use the interrupt stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 + #define BSP_PRV_PSW_INIT (0x00030000) +#else + #define BSP_PRV_PSW_INIT (0x00010000) +#endif +#endif/* BSP_CFG_RTOS_USED */ + +#if defined(__CCRX__) || defined(__GNUC__) + +#ifdef BSP_MCU_FLOATING_POINT + /* Initialize FPSW for floating-point operations */ +#define BSP_PRV_FPSW_INIT (0x00000000) /* Currently nothing set by default. */ +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + /* Initialize DPSW for double-precision floating-point operations */ +#define BSP_PRV_DPSW_INIT (0x00000000) /* Currently nothing set by default. */ +#endif + +#ifdef __ROZ +#define BSP_PRV_FPU_ROUND (0x00000001) /* Let FPSW RMbits=01 (round to zero) */ +#else +#define BSP_PRV_FPU_ROUND (0x00000000) /* Let FPSW RMbits=00 (round to nearest) */ +#endif +#ifdef __DOFF +#define BSP_PRV_FPU_DENOM (0x00000100) /* Let FPSW DNbit=1 (denormal as zero) */ +#else +#define BSP_PRV_FPU_DENOM (0x00000000) /* Let FPSW DNbit=0 (denormal as is) */ +#endif +#endif + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +Pre-processor Directives +***********************************************************************************************************************/ +/* Set this as the entry point from a power-on reset */ +#if defined(__CCRX__) +#pragma entry PowerON_Reset_PC +#endif /* defined(__CCRX__) */ + +/*********************************************************************************************************************** +External function Prototypes +***********************************************************************************************************************/ +/* Initialize C runtime environment */ +extern void _INITSCT(void); + +#if defined(CPPAPP) +/* Initialize C++ global class object */ +extern void _CALL_INIT(void); +#endif + +#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED != 0 +/* If user is requesting warm start callback functions then these are the prototypes. */ +void BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(void); +#endif + +#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED != 0 +/* If user is requesting warm start callback functions then these are the prototypes. */ +void BSP_CFG_USER_WARM_START_POST_C_FUNCTION(void); +#endif + +#if BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ +/* A function is used to create a main task, rtos's objects required to be available in advance. */ +extern void Processing_Before_Start_Kernel(void); +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +/* kernel initialization routine */ +extern void vsta_knl(void); +#endif/* BSP_CFG_RTOS_USED */ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Power-on reset function declaration */ +R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION); + +/* Main program function declaration */ +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ +extern void R_BSP_MAIN_FUNCTION(void); +#endif + +/*********************************************************************************************************************** +* Function name: PowerON_Reset_PC +* Description : This function is the MCU's entry point from a power-on reset. +* The following steps are taken in the startup code: +* 1. The User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) are both set immediately after entry +* to this function. The USP and ISP stack sizes are set in the file bsp_config.h. +* 2. The interrupt vector base register is set to point to the beginning of the relocatable interrupt +* vector table. +* 3. The MCU is setup for floating point operations by setting the initial value of the Floating Point +* Status Word (FPSW). +* 4. The MCU operating frequency is set by configuring the Clock Generation Circuit (CGC) in +* operating_frequency_set. +* 5. Calls are made to functions to setup the C runtime environment which involves initializing all +* initialed data, zeroing all uninitialized variables, and configuring STDIO if used +* (calls to _INITSCT and init_iolib). +* 6. Board-specific hardware setup, including configuring I/O pins on the MCU, in hardware_setup. +* 7. Global interrupts are enabled by setting the I bit in the Program Status Word (PSW), and the stack +* is switched from the ISP to the USP. The initial Interrupt Priority Level is set to zero, enabling +* any interrupts with a priority greater than zero to be serviced. +* 8. The processor is optionally switched to user mode. To run in user mode, set the macro +* BSP_CFG_RUN_IN_USER_MODE above to a 1. +* 9. The bus error interrupt is enabled to catch any accesses to invalid or reserved areas of memory. +* +* Once this initialization is complete, the user's main() function is called. It should not return. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION) +{ + /* Stack pointers are setup prior to calling this function - see comments above */ + + /* You can use auto variables in this function but such variables other than register variables + * will be unavailable after you change the stack from the I stack to the U stack (if change). */ + + /* The bss sections have not been cleared and the data sections have not been initialized + * and constructors of C++ objects have not been executed until the _INITSCT() is executed. */ +#if defined(__GNUC__) +#if BSP_CFG_USER_STACK_ENABLE == 1 + INTERNAL_NOT_USED(ustack_area); +#endif + INTERNAL_NOT_USED(istack_area); +#endif + +#if defined(__CCRX__) || defined(__GNUC__) + + /* Initialize the Interrupt Table Register */ + R_BSP_SET_INTB(R_BSP_SECTOP_INTVECTTBL); + +#ifdef BSP_MCU_EXCEPTION_TABLE + /* Initialize the Exception Table Register */ + R_BSP_SET_EXTB(R_BSP_SECTOP_EXCEPTVECTTBL); +#endif + +#ifdef BSP_MCU_FLOATING_POINT +#ifdef __FPU + /* Initialize the Floating-Point Status Word Register. */ + R_BSP_SET_FPSW(BSP_PRV_FPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM); +#endif +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU + /* Initialize the Double-Precision Floating-Point Status Word Register. */ + R_BSP_SET_DPSW(BSP_PRV_DPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM); +#endif +#endif + + /* Initializes the trigonometric function unit. */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU + R_BSP_INIT_TFU(); +#endif +#endif + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + + /* Wait for power voltage stabilization of VBATT function. */ +#if (defined(BSP_CFG_VBATT_ENABLE) && (BSP_CFG_VBATT_ENABLE == 0)) + vbatt_voltage_stability_wait(); +#endif + + /* Switch to high-speed operation */ + mcu_clock_setup(); + + /* If the warm start Pre C runtime callback is enabled, then call it. */ +#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED == 1 + BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(); +#endif + + /* Initialize C runtime environment */ + _INITSCT(); + +#if defined(CPPAPP) + /* Initialize C++ global class object */ + _CALL_INIT(); +#endif + + /* Initialize RAM */ + bsp_ram_initialize(); + + /* If the warm start Post C runtime callback is enabled, then call it. */ +#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED == 1 + BSP_CFG_USER_WARM_START_POST_C_FUNCTION(); +#endif + +#if BSP_CFG_IO_LIB_ENABLE == 1 + /* Comment this out if not using I/O lib */ +#if defined(__CCRX__) + init_iolib(); +#endif /* defined(__CCRX__) */ +#endif + + /* Initialize MCU interrupt callbacks. */ + bsp_interrupt_open(); + + /* Initialize register protection functionality. */ + bsp_register_protect_open(); + + /* Configure the MCU and board hardware */ + hardware_setup(); + + /* Enable interrupt and select the I stack or the U stack */ + R_BSP_SET_PSW(BSP_PRV_PSW_INIT); + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* Does not change the MCU's user mode to user in Renesas RTOS. */ +#else /* BSP_CFG_RTOS_USED != 4 */ +#if BSP_CFG_RUN_IN_USER_MODE == 1 + /* Change the MCU's user mode from supervisor to user */ + #if BSP_CFG_USER_STACK_ENABLE == 1 + R_BSP_CHG_PMUSR(); + #else + #error "Settings of BSP_CFG_RUN_IN_USER_MODE and BSP_CFG_USER_STACK_ENABLE are inconsistent with each other." + #endif +#endif /* BSP_CFG_RUN_IN_USER_MODE */ +#endif /* BSP_CFG_RTOS_USED */ + + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR); + +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ + /* Call the main program function (should not return) */ + R_BSP_MAIN_FUNCTION(); +#elif BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ + /* Lock the channel that system timer of RTOS is using. */ + #if (((BSP_CFG_RTOS_SYSTEM_TIMER) >=0) && ((BSP_CFG_RTOS_SYSTEM_TIMER) <= 3)) + if (R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + BSP_CFG_RTOS_SYSTEM_TIMER)) == false) + { + /* WAIT_LOOP */ + while(1); + } + #else + #error "Setting BSP_CFG_RTOS_SYSTEM_TIMER is invalid." + #endif + + /* Prepare the necessary tasks, FreeRTOS's resources... required to be executed at the beginning + * after vTaskStarScheduler() is called. Other tasks can also be created after starting scheduler at any time */ + Processing_Before_Start_Kernel(); + + /* Call the kernel startup (should not return) */ + vTaskStartScheduler(); +#elif BSP_CFG_RTOS_USED == 2 /* SEGGER embOS */ +#elif BSP_CFG_RTOS_USED == 3 /* Micrium MicroC/OS */ +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4 + /* Lock a timer resource by r_bsp, if using time function on RTOS. */ + if(R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + _RI_CLOCK_TIMER)) == false) + { + /* WAIT_LOOP */ + while(1); + } + /* Initialize CMT for RI600V4 */ + _RI_init_cmt(); +#else + /* When RI600PX, the above are in _RI_init_cmt_knl called from the kernel. */ +#endif + /* Make sure to disable interrupt. */ + R_BSP_CLRPSW_I();/* clrpsw_i() */ + vsta_knl(); +#endif/* BSP_CFG_RTOS_USED */ + +#if BSP_CFG_IO_LIB_ENABLE == 1 + /* Comment this out if not using I/O lib - cleans up open files */ +#if defined(__CCRX__) + close_all(); +#endif /* defined(__CCRX__) */ +#endif + + /* Infinite loop is intended here. */ + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Put a breakpoint here if you want to catch an exit of main(). */ + R_BSP_NOP(); + } +} /* End of function PowerON_Reset_PC() */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +/* Definition of Kernel data section */ +#include "kernel_ram.h" /* generated by cfg600 */ +#include "kernel_rom.h" /* generated by cfg600 */ +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c new file mode 100644 index 000000000..f8c4a0f3c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c @@ -0,0 +1,1082 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.c +* Description : Contains clock specific routines +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Removed unnecessary processing from the clock_source_select fucntion. +* : 17.12.2019 1.02 Fixed warning of clock_source_select function with IAR compiler. +* : 14.02.2020 1.03 Fixed warning of clock_source_select function with CCRX and IAR compiler. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_CKSEL_LOCO (0x0) +#define BSP_PRV_CKSEL_HOCO (0x1) +#define BSP_PRV_CKSEL_MAIN_OSC (0x2) +#define BSP_PRV_CKSEL_SUBCLOCK (0x3) +#define BSP_PRV_CKSEL_PLL (0x4) + +#define BSP_PRV_NORMALIZE_X10 (10) /* used to avoid floating point arithmetic */ + +/* This macro runs or stops the low-speed on-chip oscillator(LOCO). + If the following conditions are satisfied, LOCO will operate. + 1. System clock source is LOCO. + 2. Clock output enable and CLKOUT source is LOCO. + */ +#if (BSP_CFG_CLOCK_SOURCE == 0) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 0)) + #define BSP_PRV_LOCO_CLK_OPERATING (1) /* LOCO is operating. */ +#else + #define BSP_PRV_LOCO_CLK_OPERATING (0) /* LOCO is stopped. */ +#endif + +/* This macro runs or stops the high-speed on-chip oscillator(HOCO). + If the following conditions are satisfied, HOCO will operate. + 1. System clock source is HOCO. + 2. System clock source is PLL circuit. PLL source is HOCO. + 3. PHY clock source is PLL circuit. PLL source is HOCO. + 4. PHY clock source is PPLL circuit. PPLL source is HOCO. + 5. Clock output enable and clock output source is HOCO. + 6. Clock output enable and clock output source is PLL circuit. PLL source is HOCO. + 7. Clock output enable and clock output source is PPLL circuit. PPLL source is HOCO. + */ +#if (BSP_CFG_CLOCK_SOURCE == 1) \ + || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 0) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 1) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6) && (BSP_CFG_PLL_SRC == 1)) + #define BSP_PRV_HOCO_CLK_OPERATING (1) /* HOCO is operating. */ +#else + #define BSP_PRV_HOCO_CLK_OPERATING (0) /* HOCO is stopped. */ +#endif + +/* This macro runs or stops the Main-clock oscillator. + If the following conditions are satisfied, Main-clock oscillator will operate. + 1. System clock source is Main-clock oscillator. + 2. System clock source is PLL circuit. PLL source is Main-clock oscillator. + 3. USB clock source is PPLL circuit. PPLL source is Main-clock oscillator. + 4. PHY clock source is PLL circuit. PLL source is Main-clock oscillator. + 5. PHY clock source is PPLL circuit. PPLL source is Main-clock oscillator. + 6. Clock output enable and clock output source is Main-clock oscillator. + 7. Clock output enable and clock output source is PLL circuit. PLL source is Main-clock oscillator. + 8. Clock output enable and clock output source is PPLL circuit. PPLL source is Main-clock oscillator. + */ +#if (BSP_CFG_CLOCK_SOURCE == 2) \ + || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_USB_CLOCK_SOURCE == 3) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 0) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 1) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 2)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6) && (BSP_CFG_PLL_SRC == 0)) + #define BSP_PRV_MAIN_CLK_OPERATING (1) /* Main-clock oscillator is operating. */ +#else + #define BSP_PRV_MAIN_CLK_OPERATING (0) /* Main-clock oscillator is stopped. */ +#endif + +/* This macro runs or stops the Sub-clock oscillator. + If the following conditions are satisfied, Sub-clock oscillator will operate. + 1. System clock source is Sub-clock oscillator. + 2. Clock output enable and clock output source is Sub-clock oscillator. + */ +#if (BSP_CFG_CLOCK_SOURCE == 3) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 3)) + #define BSP_PRV_SUB_CLK_OPERATING (1) /* Sub-clock oscillator is operating. */ +#else /* Clock source is not Sub-clock oscillator. */ + #define BSP_PRV_SUB_CLK_OPERATING (0) /* Sub-clock oscillator is stopped. */ +#endif + +/* This macro runs or stops the PLL circuit. + If the following conditions are satisfied, PLL circuit will operate. + 1. System clock source is PLL circuit. + 2. PHY clock source is PLL circuit. + 3. Clock output enable and clock output source is PLL circuit. + */ +#if (BSP_CFG_CLOCK_SOURCE == 4) \ + || (BSP_CFG_PHY_CLOCK_SOURCE == 0) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4)) + #define BSP_PRV_PLL_CLK_OPERATING (1) /* PLL circuit is operating. */ +#else /* PLL is not used as clock source. */ + #define BSP_PRV_PLL_CLK_OPERATING (0) /* PLL circuit is stopped. */ +#endif + +/* This macro runs or stops the PPLL circuit. + If the following conditions are satisfied, PPLL circuit will operate. + 1. USB clock source is PPLL circuit. + 2. PHY clock source is PPLL circuit. + 3. Clock output enable and clock output source is PPLL circuit. + */ +#if (BSP_CFG_USB_CLOCK_SOURCE == 3) \ + || (BSP_CFG_PHY_CLOCK_SOURCE == 1) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6)) + #define BSP_PRV_PPLL_CLK_OPERATING (1) /* PPLL circuit is operating. */ +#else /* PPLL is not used for USB clock. */ + #define BSP_PRV_PPLL_CLK_OPERATING (0) /* PPLL circuit is stopped. */ +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +static void operating_frequency_set(void); +static void clock_source_select(void); +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/* CLKOUT initial configuration function declaration */ +static void bsp_clkout_initial_configure(void); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function Name: get_iclk_freq_hz +* Description : Return the current ICLK frequency in Hz. Called by R_BSP_GetIClkFreqHz(). +* The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to +* determine the ICLK frequency we need to first find the current system clock source and then, +* in some cases where the clock source can be configured for multiple frequencies, calculate the +* frequency at which it is currently running. +* Arguments : None +* Return Value : uint32_t - the iclk frequency in Hz +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void) +{ + uint32_t sys_clock_src_freq; + uint32_t pll_multiplier; + uint32_t pll_source_freq; + uint32_t hoco_frequency[3] = {16000000, 18000000, 20000000}; + + /* Casting is valid because it matches the type to the retern value. */ + uint8_t cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL; + + switch (cksel) + { + case BSP_PRV_CKSEL_LOCO: + sys_clock_src_freq = BSP_LOCO_HZ; + break; + + case BSP_PRV_CKSEL_HOCO: + + /* Set HOCO frequency. */ + sys_clock_src_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + break; + + case BSP_PRV_CKSEL_MAIN_OSC: + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + + case BSP_PRV_CKSEL_SUBCLOCK: + sys_clock_src_freq = BSP_SUB_CLOCK_HZ; + break; + + case BSP_PRV_CKSEL_PLL: + + /* The RX72N have two possible sources for the PLL */ + + /* Casting is valid because it matches the type to the retern value. */ + pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2); + + /* Default to the MAIN OSC as the PLL source */ + pll_source_freq = BSP_CFG_XTAL_HZ; + + /* If 1 then the HOCO is the PLL source */ + if (0x1 == SYSTEM.PLLCR.BIT.PLLSRCSEL) + { + /* Set HOCO frequency. */ + pll_source_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + } + + /* Casting is valid because it matches the type to the retern value. */ + sys_clock_src_freq = ((pll_source_freq / (((uint32_t)(SYSTEM.PLLCR.BIT.PLIDIV + 1)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier); + break; + + default: + + /* Should never arrive here. Use the Main OSC freq as a default... */ + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + } + + /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */ + return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK)); +} /* End of function get_iclk_freq_hz() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +* Function name: mcu_clock_setup +* Description : Contains clock functions called at device restart. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void mcu_clock_setup(void) +{ + /* Switch to high-speed operation */ + operating_frequency_set(); + +#if BSP_CFG_CLKOUT_OUTPUT != 0 + bsp_clkout_initial_configure(); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +} /* End of function mcu_clock_setup() */ + +/*********************************************************************************************************************** +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void operating_frequency_set (void) +{ + /* Used for constructing value to write to SCKCR, SCKCR2, and SCKCR3 registers. */ + uint32_t tmp_clock = 0; + uint32_t tmp_restore_clock = 0; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Select the clock based upon user's choice. */ + clock_source_select(); + + /* Figure out setting for FCK bits. */ +#if BSP_CFG_FCK_DIV == 1 + /* Do nothing since FCK bits should be 0. */ +#elif BSP_CFG_FCK_DIV == 2 + tmp_clock |= 0x10000000; +#elif BSP_CFG_FCK_DIV == 4 + tmp_clock |= 0x20000000; +#elif BSP_CFG_FCK_DIV == 8 + tmp_clock |= 0x30000000; +#elif BSP_CFG_FCK_DIV == 16 + tmp_clock |= 0x40000000; +#elif BSP_CFG_FCK_DIV == 32 + tmp_clock |= 0x50000000; +#elif BSP_CFG_FCK_DIV == 64 + tmp_clock |= 0x60000000; +#else + #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for ICK bits. */ +#if BSP_CFG_ICK_DIV == 1 + /* Do nothing since ICK bits should be 0. */ +#elif BSP_CFG_ICK_DIV == 2 + tmp_clock |= 0x01000000; +#elif BSP_CFG_ICK_DIV == 4 + tmp_clock |= 0x02000000; +#elif BSP_CFG_ICK_DIV == 8 + tmp_clock |= 0x03000000; +#elif BSP_CFG_ICK_DIV == 16 + tmp_clock |= 0x04000000; +#elif BSP_CFG_ICK_DIV == 32 + tmp_clock |= 0x05000000; +#elif BSP_CFG_ICK_DIV == 64 + tmp_clock |= 0x06000000; +#else + #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for BCK bits. */ +#if BSP_CFG_BCK_DIV == 1 + /* Do nothing since BCK bits should be 0. */ +#elif BSP_CFG_BCK_DIV == 2 + tmp_clock |= 0x00010000; +#elif BSP_CFG_BCK_DIV == 3 + tmp_clock |= 0x00090000; +#elif BSP_CFG_BCK_DIV == 4 + tmp_clock |= 0x00020000; +#elif BSP_CFG_BCK_DIV == 8 + tmp_clock |= 0x00030000; +#elif BSP_CFG_BCK_DIV == 16 + tmp_clock |= 0x00040000; +#elif BSP_CFG_BCK_DIV == 32 + tmp_clock |= 0x00050000; +#elif BSP_CFG_BCK_DIV == 64 + tmp_clock |= 0x00060000; +#else + #error "Error! Invalid setting for BSP_CFG_BCK_DIV in r_bsp_config.h" +#endif + + /* Configure PSTOP1 bit for BCLK output. */ +#if BSP_CFG_BCLK_OUTPUT == 0 + /* Set PSTOP1 bit */ + tmp_clock |= 0x00800000; +#elif BSP_CFG_BCLK_OUTPUT == 1 + /* Clear PSTOP1 bit */ + tmp_clock &= ~0x00800000; +#elif BSP_CFG_BCLK_OUTPUT == 2 + /* Clear PSTOP1 bit */ + tmp_clock &= ~0x00800000; + /* Set BCLK divider bit */ + SYSTEM.BCKCR.BIT.BCLKDIV = 1; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(1 == SYSTEM.BCKCR.BIT.BCLKDIV) + { + R_BSP_NOP(); + } +#else + #error "Error! Invalid setting for BSP_CFG_BCLK_OUTPUT in r_bsp_config.h" +#endif + + /* Figure out setting for PCKA bits. */ +#if BSP_CFG_PCKA_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKA_DIV == 2 + tmp_clock |= 0x00001000; +#elif BSP_CFG_PCKA_DIV == 4 + tmp_clock |= 0x00002000; +#elif BSP_CFG_PCKA_DIV == 8 + tmp_clock |= 0x00003000; +#elif BSP_CFG_PCKA_DIV == 16 + tmp_clock |= 0x00004000; +#elif BSP_CFG_PCKA_DIV == 32 + tmp_clock |= 0x00005000; +#elif BSP_CFG_PCKA_DIV == 64 + tmp_clock |= 0x00006000; +#else + #error "Error! Invalid setting for BSP_CFG_PCKA_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKB bits. */ +#if BSP_CFG_PCKB_DIV == 1 + /* Do nothing since PCKB bits should be 0. */ +#elif BSP_CFG_PCKB_DIV == 2 + tmp_clock |= 0x00000100; +#elif BSP_CFG_PCKB_DIV == 4 + tmp_clock |= 0x00000200; +#elif BSP_CFG_PCKB_DIV == 8 + tmp_clock |= 0x00000300; +#elif BSP_CFG_PCKB_DIV == 16 + tmp_clock |= 0x00000400; +#elif BSP_CFG_PCKB_DIV == 32 + tmp_clock |= 0x00000500; +#elif BSP_CFG_PCKB_DIV == 64 + tmp_clock |= 0x00000600; +#else + #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKC bits. */ +#if BSP_CFG_PCKC_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKC_DIV == 2 + tmp_clock |= 0x00000010; +#elif BSP_CFG_PCKC_DIV == 4 + tmp_clock |= 0x00000020; +#elif BSP_CFG_PCKC_DIV == 8 + tmp_clock |= 0x00000030; +#elif BSP_CFG_PCKC_DIV == 16 + tmp_clock |= 0x00000040; +#elif BSP_CFG_PCKC_DIV == 32 + tmp_clock |= 0x00000050; +#elif BSP_CFG_PCKC_DIV == 64 + tmp_clock |= 0x00000060; +#else + #error "Error! Invalid setting for BSP_CFG_PCKC_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKD bits. */ +#if BSP_CFG_PCKD_DIV == 1 + /* Do nothing since PCKD bits should be 0. */ +#elif BSP_CFG_PCKD_DIV == 2 + tmp_clock |= 0x00000001; +#elif BSP_CFG_PCKD_DIV == 4 + tmp_clock |= 0x00000002; +#elif BSP_CFG_PCKD_DIV == 8 + tmp_clock |= 0x00000003; +#elif BSP_CFG_PCKD_DIV == 16 + tmp_clock |= 0x00000004; +#elif BSP_CFG_PCKD_DIV == 32 + tmp_clock |= 0x00000005; +#elif BSP_CFG_PCKD_DIV == 64 + tmp_clock |= 0x00000006; +#else + #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h" +#endif + + /* To change the ICLK frequency from less than 70 MHz to 70 MHz or higher such that the ratio of the frequency + after the change to that before the change is greater than four, start by setting the frequency to one quarter + of the intended frequency, wait for 3 us, and then change it to the intended frequency. + (Refer User's Manual: 9.10.7 Notes on Changing the ICLK Frequency.) */ + /* Confirm whether to change ICLK frequency from less than 70 MHz to 70 MHz or higher. */ + if(BSP_ICLK_HZ >= BSP_MCU_ICLK_FREQ_THRESHOLD) + { + /* The clock source after reset is LOCO. The frequency of LOCO is 240 kHz. + When the target clock frequency is 70 MHz or higher, it always exceeds 4 times the current clock frequency. + Therefore, this process does not check whether the target clock frequency exceeds 4 times the current + clock frequency. */ + + /* Backup of tmp_clock */ + tmp_restore_clock = tmp_clock; + + /* Clear the setting for ICK and BCK bits. */ + tmp_clock &= 0xF0F0FFFF; +#if BSP_CFG_ICK_DIV == 1 + /* Set ICK and BCK bits to divide by 4. */ + tmp_clock |= 0x02020000; +#elif BSP_CFG_ICK_DIV == 2 + /* Set ICK and BCK bits to divide by 8. */ + tmp_clock |= 0x03030000; +#endif + } + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + + /* Re-init tmp_clock to use to set SCKCR2. */ + tmp_clock = 0; + + /* Figure out setting for UCK bits. */ +#if BSP_CFG_UCK_DIV == 2 + tmp_clock |= 0x00000011; +#elif BSP_CFG_UCK_DIV == 3 + tmp_clock |= 0x00000021; +#elif BSP_CFG_UCK_DIV == 4 + tmp_clock |= 0x00000031; +#elif BSP_CFG_UCK_DIV == 5 + tmp_clock |= 0x00000041; +#else + #error "Error! Invalid setting for BSP_CFG_UCK_DIV in r_bsp_config.h" +#endif + + /* Set SCKCR2 register. */ + SYSTEM.SCKCR2.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR2.WORD) + { + R_BSP_NOP(); + } + + /* Choose clock source. Default for r_bsp_config.h is PLL. */ + tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8; + + /* Casting is valid because it matches the type to the retern value. */ + SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + + /* Set ICLK frequency to target ICLK. */ + if(BSP_ICLK_HZ >= BSP_MCU_ICLK_FREQ_THRESHOLD) + { + /* Wait for 3 us. */ + R_BSP_SoftwareDelay((uint32_t)3, BSP_DELAY_MICROSECS); + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_restore_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_restore_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + } + +#if BSP_PRV_LOCO_CLK_OPERATING == 0 + /* We can now turn LOCO off since it is not going to be used. */ + SYSTEM.LOCOCR.BYTE = 0x01; + + /* Wait for five the LOCO cycles */ + /* 5 count of LOCO : (1000000/216000)*5 = 23.148148148us + 23 + 2 = 25us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)25, BSP_DELAY_MICROSECS); +#endif + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function operating_frequency_set() */ + +/*********************************************************************************************************************** +* Function name: clock_source_select +* Description : Enables and disables clocks as chosen by the user. This function also implements the delays +* needed for the clocks to stabilize. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void clock_source_select (void) +{ + volatile uint8_t i; + volatile uint8_t dummy; +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + uint8_t tmp; +#endif + volatile uint16_t tmp_packcr; + + /* Main clock will be not oscillate in software standby or deep software standby modes. */ + SYSTEM.MOFCR.BIT.MOFXIN = 0; + + /* Set the oscillation source of the main clock oscillator. */ + SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE; + +#if BSP_PRV_HOCO_CLK_OPERATING == 1 + /* HOCO is chosen. Start it operating if it is not already operating. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn on power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x00; + + /* Stop HOCO. */ + SYSTEM.HOCOCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stopped. */ + R_BSP_NOP(); + } + + /* Set HOCO frequency. */ + #if (BSP_CFG_HOCO_FREQUENCY == 0) + SYSTEM.HOCOCR2.BYTE = 0x00; //16MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 1) + SYSTEM.HOCOCR2.BYTE = 0x01; //18MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 2) + SYSTEM.HOCOCR2.BYTE = 0x02; //20MHz + #else + #error "Error! Invalid setting for BSP_CFG_HOCO_FREQUENCY in r_bsp_config.h" + #endif + + /* HOCO is chosen. Start it operating. */ + SYSTEM.HOCOCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.HOCOCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. */ + R_BSP_NOP(); + } +#else /* (BSP_PRV_HOCO_CLK_OPERATING == 0) */ + /* If HOCO is already operating, it doesn't stop. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn off power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x01; + } + else + { + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. */ + R_BSP_NOP(); + } + } +#endif /* BSP_PRV_HOCO_CLK_OPERATING == 1 */ + +#if BSP_PRV_MAIN_CLK_OPERATING == 1 + /* Main clock oscillator is chosen. Start it operating. */ + + /* If the main oscillator is >10MHz then the main clock oscillator forced oscillation control register (MOFCR) must + be changed. */ + if (BSP_CFG_XTAL_HZ > 20000000) + { + /* 20 - 24MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 0; + } + else if (BSP_CFG_XTAL_HZ > 16000000) + { + /* 16 - 20MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 1; + } + else if (BSP_CFG_XTAL_HZ > 8000000) + { + /* 8 - 16MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 2; + } + else + { + /* 8MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 3; + } + + /* Set the oscillation stabilization wait time of the main clock oscillator. */ +#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */ + SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME; +#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */ + SYSTEM.MOSCWTCR.BYTE = 0x00; +#else + #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h" +#endif + + /* Set the main clock to operating. */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. */ + R_BSP_NOP(); + } +#else /* (BSP_PRV_MAIN_CLK_OPERATING == 0) */ + /* Main clock is stopped after reset. */ +#endif /* BSP_PRV_MAIN_CLK_OPERATING == 1 */ + + /* Sub-clock setting. */ + + /* Cold start setting */ + if (0 == SYSTEM.RSTSR1.BIT.CWSF) + { + /* Stop the sub-clock oscillator */ + /* RCR4 - RTC Control Register 4 + b7:b1 Reserved - The write value should be 0. + b0 RCKSEL - Count Source Select - Sub-clock oscillator is selected. */ + RTC.RCR4.BIT.RCKSEL = 0; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR4.BYTE; + } + + /* Confirm that the written */ + if (0 != RTC.RCR4.BIT.RCKSEL) + { + R_BSP_NOP(); + } + + /* RCR3 - RTC Control Register 3 + b7:b4 Reserved - The write value should be 0. + b3:b1 RTCDV - Sub-clock oscillator Drive Ability Control. + b0 RTCEN - Sub-clock oscillator is stopped. */ + RTC.RCR3.BIT.RTCEN = 0; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BYTE; + } + + /* Confirm that the written */ + if (0 != RTC.RCR3.BIT.RTCEN) + { + R_BSP_NOP(); + } + + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stopped. */ + R_BSP_NOP(); + } + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Set the drive capacity of the sub-clock oscillator */ + #if (BSP_CFG_SOSC_DRV_CAP == 0) /* Standard CL */ + tmp = 0x06; + #elif (BSP_CFG_SOSC_DRV_CAP == 1) /* Low CL */ + tmp = 0x01; + #else + #error "Error! Invalid setting for BSP_CFG_SOSC_DRV_CAP in r_bsp_config.h" + #endif + + /* Set the Sub-Clock Oscillator Drive Capacity Control. */ + RTC.RCR3.BIT.RTCDV = tmp; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BYTE; + } + + /* Confirm that the written */ + if (tmp != RTC.RCR3.BIT.RTCDV) + { + R_BSP_NOP(); + } + + /* Set wait time until the sub-clock oscillator stabilizes */ + /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register + b7:b5 Reserved - The write value should be 0. + b4:b0 SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */ + SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME; + + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x00 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stabilized. */ + R_BSP_NOP(); + } +#endif /* (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) */ + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */ + SYSTEM.SOSCWTCR.BYTE = 0x00; + + /* ---- Operate the sub-clock oscillator ---- */ + RTC.RCR3.BIT.RTCEN = 1; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BIT.RTCEN; + } + + /* Confirm that the written value can be read correctly. */ + if (1 != RTC.RCR3.BIT.RTCEN) + { + R_BSP_NOP(); + } +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for six the sub-clock cycles */ + /* 6 count of sub-clock : (1000000/32768)*6=183.10546875us + In the case of LOCO frequency is 264kHz : 183.10546875/(1000000/264000)=48.33984375cycle + (48.33984375+2)*(1000000/240000)=209.7493489583333us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)210, BSP_DELAY_MICROSECS); +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) && (BSP_CFG_RTC_ENABLE == 0) + /* Stop prescaler and counter */ + /* RCR2 - RTC Control Register 2 + b7 CNTMD - Count Mode Select - The calendar count mode. + b6 HR24 - Hours Mode - The RTC operates in 24-hour mode. + b5 AADJP - Automatic Adjustment Period Select - The RADJ.ADJ[5:0] setting value is adjusted from + the count value of the prescaler every 10 seconds. + b4 AADJE - Automatic Adjustment Enable - Automatic adjustment is enabled. + b3 RTCOE - RTCOUT Output Enable - RTCOUT output enabled. + b2 ADJ30 - 30-Second Adjustment - 30-second adjustment is executed. + b1 RESET - RTC Software Reset - The prescaler and the target registers for RTC software reset are initialized. + b0 START - start - Prescaler is stopped. */ + RTC.RCR2.BYTE &= 0x7E; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.START) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* RTC Software Reset */ + RTC.RCR2.BIT.RESET = 1; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.RESET) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* An alarm interrupt request is disabled */ + /* RCR1 - RTC Control Register 1 + b7:b4 PES - Periodic Interrupt Select - These bits specify the period for the periodic interrupt. + b3 RTCOS - RTCOUT Output Select - RTCOUT outputs 1 Hz. + b2 PIE - Periodic Interrupt Enable - A periodic interrupt request is disabled. + b1 CIE - Carry Interrupt Enable - A carry interrupt request is disabled. + b0 AIE - Alarm Interrupt Enable - An alarm interrupt request is disabled. */ + RTC.RCR1.BYTE &= 0xF8; + + /* Wait for one the sub-clock cycles */ + /* 1 count of sub-clock : (1000000/32768)=30.517578125us + In the case of LOCO frequency is 264kHz : 30.517578125/(1000000/264000)=8.056640625cycle + (8.056640625+2)*(1000000/240000)=41.902669270833us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)42, BSP_DELAY_MICROSECS); + + /* Confirm that the written value can be read correctly. */ + if (0x00 != (RTC.RCR1.BYTE & 0x07)) + { + R_BSP_NOP(); + } +#endif /* (BSP_PRV_SUB_CLK_OPERATING == 1) && (BSP_CFG_RTC_ENABLE == 0) */ + } + /* Warm start setting */ + else + { +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || ((BSP_PRV_SUB_CLK_OPERATING == 0) && (BSP_CFG_RTC_ENABLE == 0)) + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* Confirm that the Sub clock stopped. */ + R_BSP_NOP(); + } +#endif + +#if BSP_PRV_SUB_CLK_OPERATING == 1 + /* Set wait time until the sub-clock oscillator stabilizes */ + /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register + b7:b5 Reserved - The write value should be 0. + b4:b0 SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */ + SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME; + + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x00 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stabilized. */ + R_BSP_NOP(); + } +#endif + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */ + SYSTEM.SOSCWTCR.BYTE = 0x00; +#endif + } + +#if (BSP_CFG_PHY_CLOCK_SOURCE == 1) || (BSP_CFG_USB_CLOCK_SOURCE == 3) + /* initialize */ + tmp_packcr = SYSTEM.PACKCR.WORD; + +#if BSP_CFG_PHY_CLOCK_SOURCE == 1 + /* Set value of OUTCKSEL bit. */ + tmp_packcr |= 0x0010; +#endif + +#if BSP_CFG_USB_CLOCK_SOURCE == 3 + /* Set value of UPLLSEL bit. */ + tmp_packcr |= 0x1000; +#endif + + /* Set value to PACLCR register. */ + SYSTEM.PACKCR.WORD = tmp_packcr; +#endif + +#if (BSP_PRV_PLL_CLK_OPERATING == 1) || (BSP_PRV_PPLL_CLK_OPERATING == 1) + /* Set PLL clock source. */ + #if BSP_CFG_PLL_SRC == 0 + /* Clear PLL clock source if PLL clock source is Main clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 0; + #else + /* Set PLL clock source if PLL clock source is HOCO clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 1; + #endif +#endif + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + + /* Set PLL Input Divisor. */ + SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV - 1; + + /* Set PLL Multiplier. */ + SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0)) - 1; + + /* Set the PLL to operating. */ + SYSTEM.PLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. */ + R_BSP_NOP(); + } +#else + /* PLL is stopped after reset. */ +#endif + +#if BSP_PRV_PPLL_CLK_OPERATING == 1 + /* Set PPLL Input Divisor. */ + SYSTEM.PPLLCR.BIT.PPLIDIV = BSP_CFG_PPLL_DIV - 1; + + /* Set PPLL Multiplier. */ + SYSTEM.PPLLCR.BIT.PPLSTC = ((uint8_t)((float)BSP_CFG_PPLL_MUL * 2.0)) - 1; + + /* Set the PPLL to operating. */ + SYSTEM.PPLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PPLOVF) + { + /* The delay period needed is to make sure that the PPLL has stabilized. */ + R_BSP_NOP(); + } + + /* Set PPLCK Input Divisor. */ + SYSTEM.PPLLCR3.BIT.PPLCK = BSP_CFG_PPLCK_DIV - 1; +#endif + + /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn + it off until another clock has been enabled and is ready to use. */ +#if BSP_PRV_LOCO_CLK_OPERATING == 1 + /* LOCO is chosen. This is the default out of reset. */ +#else + /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */ +#endif + + /* RX72N has a MEMWAIT register which controls the cycle waiting for access to code flash memory. + It is set as zero coming out of reset. We only want to set this if we are > 120 MHz. + */ + if (BSP_ICLK_HZ > BSP_MCU_MEMWAIT_FREQ_THRESHOLD) + { + /* Set MEMWAIT */ + SYSTEM.MEMWAIT.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x01 == SYSTEM.MEMWAIT.BYTE) + { + R_BSP_NOP(); + } + } +} /* End of function clock_source_select() */ + +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/*********************************************************************************************************************** +* Function name: bsp_clkout_initial_configure +* Description : Configures the CLKOUT initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_clkout_initial_configure(void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Set the CLKOUT Output Divisor Select. */ + SYSTEM.CKOCR.BIT.CKODIV = BSP_CFG_CLKOUT_DIV; + + /* Set the CLKOUT Output Source Select. */ + SYSTEM.CKOCR.BIT.CKOSEL = BSP_CFG_CLKOUT_SOURCE; +#if BSP_CFG_CLKOUT_OUTPUT == 1 + + /* Set the CLKOUT Output Stop Control. */ + SYSTEM.CKOCR.BIT.CKOSTP = 0; +#elif BSP_CFG_CLKOUT_OUTPUT == 0 + /* do nothing */ +#else + #error "Error! Invalid setting for BSP_CFG_CLKOUT_OUTPUT in r_bsp_config.h" +#endif + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_clkout_initial_configure() */ +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h new file mode 100644 index 000000000..61c2ab378 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.h +* Description : Contains clock specific routines. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_CLOCKS_H +#define MCU_CLOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void); +void mcu_clock_setup(void); + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h new file mode 100644 index 000000000..075b2d313 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h @@ -0,0 +1,269 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_info.h +* Device(s) : RX72N +* Description : Information about the MCU. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INFO +#define MCU_INFO + +/* MCU CPU Version */ +#define BSP_MCU_CPU_VERSION (3) + +/* CPU cycles. Known number of RXv3 CPU cycles required to execute the delay_wait() loop */ +#define CPU_CYCLES_PER_LOOP (3) + +/* MCU Series. */ +#if BSP_CFG_MCU_PART_SERIES == 0x0 + #define BSP_MCU_SERIES_RX700 (1) +#else + #error "ERROR - BSP_CFG_MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h" +#endif + +/* This macro means that this MCU is part of the RX72x collection of MCUs (i.e. RX72N). */ +#define BSP_MCU_RX72_ALL (1) + +/* MCU Group name. */ +#if BSP_CFG_MCU_PART_GROUP == 0x0 + #define BSP_MCU_RX72N (1) +#else + #error "ERROR - BSP_CFG_MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h" +#endif + +/* Package. */ +#if BSP_CFG_MCU_PART_PACKAGE == 0x0 + #define BSP_PACKAGE_LFQFP176 (1) + #define BSP_PACKAGE_PINS (176) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x1 + #define BSP_PACKAGE_LFBGA176 (1) + #define BSP_PACKAGE_PINS (176) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x2 + #define BSP_PACKAGE_LFBGA224 (1) + #define BSP_PACKAGE_PINS (224) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x3 + #define BSP_PACKAGE_LFQFP144 (1) + #define BSP_PACKAGE_PINS (144) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x4 + #define BSP_PACKAGE_TFLGA145 (1) + #define BSP_PACKAGE_PINS (145) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x5 + #define BSP_PACKAGE_LFQFP100 (1) + #define BSP_PACKAGE_PINS (100) +#else + #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h" +#endif + +/* Memory size of your MCU. */ +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xD + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (1048576) + #define BSP_DATA_FLASH_SIZE_BYTES (32768) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x17 + #define BSP_ROM_SIZE_BYTES (4194304) + #define BSP_RAM_SIZE_BYTES (1048576) + #define BSP_DATA_FLASH_SIZE_BYTES (32768) +#else + #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h" +#endif + +/* These macros define clock speeds for fixed speed clocks. */ +#define BSP_LOCO_HZ (240000) +#define BSP_SUB_CLOCK_HZ (32768) + +/* Define frequency of HOCO. */ +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "ERROR - Invalid HOCO frequency chosen in r_bsp_config.h! Set valid value for BSP_CFG_HOCO_FREQUENCY." +#endif + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#if BSP_CFG_CLOCK_SOURCE == 0 + #define BSP_SELECTED_CLOCK_HZ (BSP_LOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 1 + #define BSP_SELECTED_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 2 + #define BSP_SELECTED_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 3 + #define BSP_SELECTED_CLOCK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 4 + #if BSP_CFG_PLL_SRC == 0 + #define BSP_SELECTED_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #elif BSP_CFG_PLL_SRC == 1 + #define BSP_SELECTED_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." + #endif +#else + #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h" +#endif + +/* Define frequency of PPLL clock. */ +#if BSP_CFG_PLL_SRC == 0 + #define BSP_PPLL_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PPLL_DIV) * BSP_CFG_PPLL_MUL) +#elif BSP_CFG_PLL_SRC == 1 + #define BSP_PPLL_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PPLL_DIV) * BSP_CFG_PPLL_MUL) +#else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." +#endif + +/* Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#if (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_4TH_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) + #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY" +#endif +#if (5 <= BSP_CFG_EBMAPCR_1ST_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_5TH_PRIORITY) + #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY" +#endif + +/* System clock speed in Hz. */ +#define BSP_ICLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) +/* Peripheral Module Clock A speed in Hz. Used for ETHERC and EDMAC. */ +#define BSP_PCLKA_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKA_DIV) +/* Peripheral Module Clock B speed in Hz. */ +#define BSP_PCLKB_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) +/* Peripheral Module Clock C speed in Hz. */ +#define BSP_PCLKC_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKC_DIV) +/* Peripheral Module Clock D speed in Hz. */ +#define BSP_PCLKD_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) +/* External bus clock speed in Hz. */ +#define BSP_BCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_BCK_DIV) +/* FlashIF clock speed in Hz. */ +#define BSP_FCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) +/* USB clock speed in Hz. */ +#if BSP_CFG_USB_CLOCK_SOURCE == 2 + #define BSP_UCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_UCK_DIV) +#elif BSP_CFG_USB_CLOCK_SOURCE == 3 + #define BSP_UCLK_HZ (BSP_PPLL_CLOCK_HZ / BSP_CFG_PPLCK_DIV) +#else + #error "ERROR - BSP_CFG_USB_CLOCK_SOURCE - Unknown usb clock source chosen in r_bsp_config.h" +#endif + +/* CLKOUT25M clock speed in Hz. */ +#if BSP_CFG_PHY_CLOCK_SOURCE == 0 + #define BSP_CLKOUT25M_HZ (BSP_SELECTED_CLOCK_HZ/8) +#elif BSP_CFG_PHY_CLOCK_SOURCE == 1 + #define BSP_CLKOUT25M_HZ (BSP_PPLL_CLOCK_HZ / 8) +#elif BSP_CFG_PHY_CLOCK_SOURCE == 2 + /* Ethernet-PHY not use */ +#else + #error "ERROR - BSP_CFG_PHY_CLOCK_SOURCE - Unknown Ethernet-PHY clock source chosen in r_bsp_config.h" +#endif + +/* Null argument definitions. */ +#define FIT_NO_FUNC ((void (*)(void *))0x10000000) /* Reserved space on RX */ +#define FIT_NO_PTR ((void *)0x10000000) /* Reserved space on RX */ + +/* Mininum and maximum IPL levels available for this MCU. */ +#define BSP_MCU_IPL_MAX (0xF) +#define BSP_MCU_IPL_MIN (0) + +/* Frequency threshold of memory wait cycle setting. */ +#define BSP_MCU_MEMWAIT_FREQ_THRESHOLD (120000000) /* ICLK > 120MHz requires MEMWAIT register update */ + +/* Frequency threshold of iclk. */ +#define BSP_MCU_ICLK_FREQ_THRESHOLD (70000000) + +/* MCU functions */ +#define BSP_MCU_REGISTER_WRITE_PROTECTION +#define BSP_MCU_RCPC_PRC0 +#define BSP_MCU_RCPC_PRC1 +#define BSP_MCU_RCPC_PRC3 +#define BSP_MCU_FLOATING_POINT +#define BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#define BSP_MCU_EXCEPTION_TABLE +#define BSP_MCU_GROUP_INTERRUPT +#define BSP_MCU_GROUP_INTERRUPT_IE0 +#define BSP_MCU_GROUP_INTERRUPT_BE0 +#define BSP_MCU_GROUP_INTERRUPT_BL0 +#define BSP_MCU_GROUP_INTERRUPT_BL1 +#define BSP_MCU_GROUP_INTERRUPT_BL2 +#define BSP_MCU_GROUP_INTERRUPT_AL0 +#define BSP_MCU_GROUP_INTERRUPT_AL1 +#define BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT +#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +#define BSP_MCU_EXCEP_ACCESS_ISR +#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR +#define BSP_MCU_EXCEP_FLOATING_POINT_ISR +#define BSP_MCU_NON_MASKABLE_ISR +#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +#define BSP_MCU_BUS_ERROR_ISR +#define BSP_MCU_TRIGONOMETRIC + +#define BSP_MCU_NMI_EXC_NMI_PIN +#define BSP_MCU_NMI_OSC_STOP_DETECT +#define BSP_MCU_NMI_WDT_ERROR +#define BSP_MCU_NMI_IWDT_ERROR +#define BSP_MCU_NMI_LVD1 +#define BSP_MCU_NMI_LVD2 +#define BSP_MCU_NMI_EXNMI +#define BSP_MCU_NMI_EXNMI_RAM +#define BSP_MCU_NMI_EXNMI_RAM_EXRAM +#define BSP_MCU_NMI_EXNMI_RAM_ECCRAM +#define BSP_MCU_NMI_EXNMI_DPFPUEX + +#endif /* MCU_INFO */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c new file mode 100644 index 000000000..d9b0c1025 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.c +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get specifics on this MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* RX MCUs come in different packages and different pin counts. + Each bit of PORTm.PDR corresponds to each pin of port m; I/O direction can be specified in 1-bit units. + Each bit of PDR corresponding to port m that does not exist is reserved. + Also, each bit of PDR corresponding to P35 pins is reserved, because such pins are input only. + Make settings of the reserved bit according to the description in section 22.4, Initialization of the Port Direction + Register (PDR). These values are then ORed into the direction registers to set non-existent pins as outputs or + inputs, which can help save power. + */ +#if BSP_PACKAGE_PINS == 224 + /* Refer User's Manual: Hardware Table 22.4. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTH_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD0) + #define BSP_PRV_PORTK_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTL_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTM_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0x00) +#elif BSP_PACKAGE_PINS == 176 + /* Refer User's Manual: Hardware Table 22.5. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD0) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#elif (BSP_PACKAGE_PINS == 145) || (BSP_PACKAGE_PINS == 144) + /* Refer User's Manual: Hardware Table 22.6. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x80) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x30) + #define BSP_PRV_PORT9_NE_PIN_MASK (0xF0) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xDF) + #define BSP_PRV_PORTG_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD7) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#elif BSP_PACKAGE_PINS == 100 + /* Refer User's Manual: Hardware Table 22.7. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x5F) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORT6_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT7_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT8_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT9_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTG_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xF7) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#else + #error "ERROR - This package is not defined in mcu_init.c" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_non_existent_port_init +* Description : For MCUs that do not have the maximum number of pins for their group (e.g. MCU with 176 pins when +* maximum is 224 pins) these 'non-existent' pins that are not bonded out need to be initialized to save +* power. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_non_existent_port_init (void) +{ + /* OR in missing pin masks from above. */ + + /* Set PORT0.PDR */ + PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK; + + /* Set PORT1.PDR */ + PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK; + + /* Set PORT2.PDR */ + PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK; + + /* Set PORT3.PDR */ + PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK; + + /* Set PORT4.PDR */ + PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK; + + /* Set PORT5.PDR */ + PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK; + + /* Set PORT6.PDR */ + PORT6.PDR.BYTE |= BSP_PRV_PORT6_NE_PIN_MASK; + + /* Set PORT7.PDR */ + PORT7.PDR.BYTE |= BSP_PRV_PORT7_NE_PIN_MASK; + + /* Set PORT8.PDR */ + PORT8.PDR.BYTE |= BSP_PRV_PORT8_NE_PIN_MASK; + + /* Set PORT9.PDR */ + PORT9.PDR.BYTE |= BSP_PRV_PORT9_NE_PIN_MASK; + + /* Set PORTA.PDR */ + PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK; + + /* Set PORTB.PDR */ + PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK; + + /* Set PORTC.PDR */ + PORTC.PDR.BYTE |= BSP_PRV_PORTC_NE_PIN_MASK; + + /* Set PORTD.PDR */ + PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK; + + /* Set PORTE.PDR */ + PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK; + + /* Set PORTF.PDR */ + PORTF.PDR.BYTE |= BSP_PRV_PORTF_NE_PIN_MASK; + + /* Set PORTG.PDR */ + PORTG.PDR.BYTE |= BSP_PRV_PORTG_NE_PIN_MASK; + + /* Set PORTH.PDR */ + PORTH.PDR.BYTE |= BSP_PRV_PORTH_NE_PIN_MASK; + + /* Set PORTJ.PDR */ + PORTJ.PDR.BYTE |= BSP_PRV_PORTJ_NE_PIN_MASK; + + /* Set PORTK.PDR */ + PORTK.PDR.BYTE |= BSP_PRV_PORTK_NE_PIN_MASK; + + /* Set PORTL.PDR */ + PORTL.PDR.BYTE |= BSP_PRV_PORTL_NE_PIN_MASK; + + /* Set PORTM.PDR */ + PORTM.PDR.BYTE |= BSP_PRV_PORTM_NE_PIN_MASK; + + /* Set PORTN.PDR */ + PORTN.PDR.BYTE |= BSP_PRV_PORTN_NE_PIN_MASK; + + /* Set PORTQ.PDR */ + PORTQ.PDR.BYTE |= BSP_PRV_PORTQ_NE_PIN_MASK; +} /* End of function bsp_non_existent_port_init() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h new file mode 100644 index 000000000..115c6b869 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.h +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INIT_H +#define MCU_INIT_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_non_existent_port_init(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_INIT_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c new file mode 100644 index 000000000..faba267c7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ +#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl2_handler_isr, VECT(ICU,GROUPBL2)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al1_handler_isr, VECT(ICU,GROUPAL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_ie0_handler_isr, VECT(ICU,GROUPIE0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_be0_handler_isr, VECT(ICU,GROUPBE0)) + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ +#ifdef __FPU + uint32_t tmp_fpsw; +#endif + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + +#ifdef __FPU + case (BSP_INT_SRC_EXC_FPU): + + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + if (true == enable) + { + /* Set the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + else + { + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + break; +#endif + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + +/*********************************************************************************************************************** +* Function Name: group_bl0_handler_isr +* Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void) +{ + /* BL0 IS1 */ + if (1 == ICU.GRPBL0.BIT.IS1) + { + /* BSP_INT_SRC_BL0_SCI0_ERI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_ERI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS0 */ + if (1 == ICU.GRPBL0.BIT.IS0) + { + /* BSP_INT_SRC_BL0_SCI0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS3 */ + if (1 == ICU.GRPBL0.BIT.IS3) + { + /* BSP_INT_SRC_BL0_SCI1_ERI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS2 */ + if (1 == ICU.GRPBL0.BIT.IS2) + { + /* BSP_INT_SRC_BL0_SCI1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS5 */ + if (1 == ICU.GRPBL0.BIT.IS5) + { + /* BSP_INT_SRC_BL0_SCI2_ERI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_ERI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS4 */ + if (1 == ICU.GRPBL0.BIT.IS4) + { + /* BSP_INT_SRC_BL0_SCI2_TEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS7 */ + if (1 == ICU.GRPBL0.BIT.IS7) + { + /* BSP_INT_SRC_BL0_SCI3_ERI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_ERI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS6 */ + if (1 == ICU.GRPBL0.BIT.IS6) + { + /* BSP_INT_SRC_BL0_SCI3_TEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_TEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS9 */ + if (1 == ICU.GRPBL0.BIT.IS9) + { + /* BSP_INT_SRC_BL0_SCI4_ERI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_ERI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS8 */ + if (1 == ICU.GRPBL0.BIT.IS8) + { + /* BSP_INT_SRC_BL0_SCI4_TEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_TEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS11 */ + if (1 == ICU.GRPBL0.BIT.IS11) + { + /* BSP_INT_SRC_BL0_SCI5_ERI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS10 */ + if (1 == ICU.GRPBL0.BIT.IS10) + { + /* BSP_INT_SRC_BL0_SCI5_TEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS13 */ + if (1 == ICU.GRPBL0.BIT.IS13) + { + /* BSP_INT_SRC_BL0_SCI6_ERI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS12 */ + if (1 == ICU.GRPBL0.BIT.IS12) + { + /* BSP_INT_SRC_BL0_SCI6_TEI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS17 */ + if (1 == ICU.GRPBL0.BIT.IS17) + { + /* BSP_INT_SRC_BL0_SCI12_ERI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS16 */ + if (1 == ICU.GRPBL0.BIT.IS16) + { + /* BSP_INT_SRC_BL0_SCI12_TEI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS18 */ + if (1 == ICU.GRPBL0.BIT.IS18) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS19 */ + if (1 == ICU.GRPBL0.BIT.IS19) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS20 */ + if (1 == ICU.GRPBL0.BIT.IS20) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS21 */ + if (1 == ICU.GRPBL0.BIT.IS21) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS24 */ + if (1 == ICU.GRPBL0.BIT.IS24) + { + /* BSP_INT_SRC_BL0_QSPI_QSPSSLI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_QSPI_QSPSSLI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS26 */ + if (1 == ICU.GRPBL0.BIT.IS26) + { + /* BSP_INT_SRC_BL0_CAC_FERRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS27 */ + if (1 == ICU.GRPBL0.BIT.IS27) + { + /* BSP_INT_SRC_BL0_CAC_MENDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS28 */ + if (1 == ICU.GRPBL0.BIT.IS28) + { + /* BSP_INT_SRC_BL0_CAC_OVFI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS29 */ + if (1 == ICU.GRPBL0.BIT.IS29) + { + /* BSP_INT_SRC_BL0_DOC_DOPCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS31 */ + if (1 == ICU.GRPBL0.BIT.IS31) + { + /* BSP_INT_SRC_BL0_PDC_PCERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS30 */ + if (1 == ICU.GRPBL0.BIT.IS30) + { + /* BSP_INT_SRC_BL0_PDC_PCFEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCFEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl1_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void) +{ + /* BL1 IS3 */ + if (1 == ICU.GRPBL1.BIT.IS3) + { + /* BSP_INT_SRC_BL1_SDHI_CDETI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CDETI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS4 */ + if (1 == ICU.GRPBL1.BIT.IS4) + { + /* BSP_INT_SRC_BL1_SDHI_CACI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS5 */ + if (1 == ICU.GRPBL1.BIT.IS5) + { + /* BSP_INT_SRC_BL1_SDHI_SDACI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_SDACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS6 */ + if (1 == ICU.GRPBL1.BIT.IS6) + { + /* BSP_INT_SRC_BL1_MMCIF_CDETIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_CDETIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS7 */ + if (1 == ICU.GRPBL1.BIT.IS7) + { + /* BSP_INT_SRC_BL1_MMCIF_ERRIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ERRIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS8 */ + if (1 == ICU.GRPBL1.BIT.IS8) + { + /* BSP_INT_SRC_BL1_MMCIF_ACCIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ACCIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS9 */ + if (1 == ICU.GRPBL1.BIT.IS9) + { + /* BSP_INT_SRC_BL1_POE3_OEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS10 */ + if (1 == ICU.GRPBL1.BIT.IS10) + { + /* BSP_INT_SRC_BL1_POE3_OEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS11 */ + if (1 == ICU.GRPBL1.BIT.IS11) + { + /* BSP_INT_SRC_BL1_POE3_OEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS12 */ + if (1 == ICU.GRPBL1.BIT.IS12) + { + /* BSP_INT_SRC_BL1_POE3_OEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS14 */ + if (1 == ICU.GRPBL1.BIT.IS14) + { + /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS13 */ + if (1 == ICU.GRPBL1.BIT.IS13) + { + /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS16 */ + if (1 == ICU.GRPBL1.BIT.IS16) + { + /* BSP_INT_SRC_BL1_RIIC2_EEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_EEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS15 */ + if (1 == ICU.GRPBL1.BIT.IS15) + { + /* BSP_INT_SRC_BL1_RIIC2_TEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS17 */ + if (1 == ICU.GRPBL1.BIT.IS17) + { + /* BSP_INT_SRC_BL1_SSIE0_SSIF0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SSIE0_SSIF0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS18 */ + if (1 == ICU.GRPBL1.BIT.IS18) + { + /* BSP_INT_SRC_BL1_SSIE1_SSIF1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SSIE1_SSIF1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS20 */ + if (1 == ICU.GRPBL1.BIT.IS20) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS21 */ + if (1 == ICU.GRPBL1.BIT.IS21) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS22 */ + if (1 == ICU.GRPBL1.BIT.IS22) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS23 */ + if (1 == ICU.GRPBL1.BIT.IS23) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS29 */ + if (1 == ICU.GRPBL1.BIT.IS29) + { + /* BSP_INT_SRC_BL1_RIIC1_EEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_EEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS28 */ + if (1 == ICU.GRPBL1.BIT.IS28) + { + /* BSP_INT_SRC_BL1_RIIC1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl2_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl2_handler_isr (void) +{ + /* BL2 IS7 */ + if (1 == ICU.GRPBL2.BIT.IS7) + { + /* BSP_INT_SRC_BL2_POEG_POEGGAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS8 */ + if (1 == ICU.GRPBL2.BIT.IS8) + { + /* BSP_INT_SRC_BL2_POEG_POEGGBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS9 */ + if (1 == ICU.GRPBL2.BIT.IS9) + { + /* BSP_INT_SRC_BL2_POEG_POEGGCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS10 */ + if (1 == ICU.GRPBL2.BIT.IS10) + { + /* BSP_INT_SRC_BL2_POEG_POEGGDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl2_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al0_handler_isr +* Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void) +{ + /* AL0 IS1 */ + if (1 == ICU.GRPAL0.BIT.IS1) + { + /* BSP_INT_SRC_AL0_SCI8_ERI8 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI8_ERI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS0 */ + if (1 == ICU.GRPAL0.BIT.IS0) + { + /* BSP_INT_SRC_AL0_SCI8_TEI8 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI8_TEI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS5 */ + if (1 == ICU.GRPAL0.BIT.IS5) + { + /* BSP_INT_SRC_AL0_SCI9_ERI9 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI9_ERI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS4 */ + if (1 == ICU.GRPAL0.BIT.IS4) + { + /* BSP_INT_SRC_AL0_SCI9_TEI9 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI9_TEI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS9 */ + if (1 == ICU.GRPAL0.BIT.IS9) + { + /* BSP_INT_SRC_AL0_SCI10_ERI10 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_ERI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS8 */ + if (1 == ICU.GRPAL0.BIT.IS8) + { + /* BSP_INT_SRC_AL0_SCI10_TEI10 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_TEI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS13 */ + if (1 == ICU.GRPAL0.BIT.IS13) + { + /* BSP_INT_SRC_AL0_SCI11_ERI11 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_ERI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS12 */ + if (1 == ICU.GRPAL0.BIT.IS12) + { + /* BSP_INT_SRC_AL0_SCI11_TEI11 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_TEI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS17 */ + if (1 == ICU.GRPAL0.BIT.IS17) + { + /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS16 */ + if (1 == ICU.GRPAL0.BIT.IS16) + { + /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS19 */ + if (1 == ICU.GRPAL0.BIT.IS19) + { + /* BSP_INT_SRC_AL0_RSPI1_SPEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS18 */ + if (1 == ICU.GRPAL0.BIT.IS18) + { + /* BSP_INT_SRC_AL0_RSPI1_SPII1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPII1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS21 */ + if (1 == ICU.GRPAL0.BIT.IS21) + { + /* BSP_INT_SRC_AL0_RSPI2_SPEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS20 */ + if (1 == ICU.GRPAL0.BIT.IS20) + { + /* BSP_INT_SRC_AL0_RSPI2_SPII2 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPII2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS23 */ + if (1 == ICU.GRPAL0.BIT.IS23) + { + /* BSP_INT_SRC_AL0_SCI7_ERI7 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI7_ERI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS22 */ + if (1 == ICU.GRPAL0.BIT.IS22) + { + /* BSP_INT_SRC_AL0_SCI7_TEI7 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI7_TEI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al1_handler_isr +* Description : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al1_handler_isr (void) +{ + /* AL1 IS0 */ + if (1 == ICU.GRPAL1.BIT.IS0) + { + /* BSP_INT_SRC_AL1_EPTPC_MINT */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EPTPC_MINT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS1 */ + if (1 == ICU.GRPAL1.BIT.IS1) + { + /* BSP_INT_SRC_AL1_PTPEDMAC_PINT */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_PTPEDMAC_PINT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS4 */ + if (1 == ICU.GRPAL1.BIT.IS4) + { + /* BSP_INT_SRC_AL1_EDMAC0_EINT0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC0_EINT0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS5 */ + if (1 == ICU.GRPAL1.BIT.IS5) + { + /* BSP_INT_SRC_AL1_EDMAC1_EINT1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC1_EINT1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS9 */ + if (1 == ICU.GRPAL1.BIT.IS9) + { + /* BSP_INT_SRC_AL1_GLCDC_GR1UF */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR1UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS10 */ + if (1 == ICU.GRPAL1.BIT.IS10) + { + /* BSP_INT_SRC_AL1_GLCDC_GR2UF */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR2UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS8 */ + if (1 == ICU.GRPAL1.BIT.IS8) + { + /* BSP_INT_SRC_AL1_GLCDC_VPOS */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_VPOS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS11 */ + if (1 == ICU.GRPAL1.BIT.IS11) + { + /* BSP_INT_SRC_AL1_DRW2D_DRW_IRQ */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_ie0_handler_isr +* Description : Interrupt handler for Group IE0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_ie0_handler_isr (void) +{ + /* IE0 IS0 */ + if (1 == ICU.GRPIE0.BIT.IS0) + { + /* Clear the interrupt status flag. */ + ICU.GCRIE0.BIT.CLR0 = 1; + + /* BSP_INT_SRC_IE0_DPFPU_DPFPUEX */ + R_BSP_InterruptControl(BSP_INT_SRC_IE0_DPFPU_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_ie0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_be0_handler_isr +* Description : Interrupt handler for Group BE0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_be0_handler_isr (void) +{ + /* BE0 IS0 */ + if (1 == ICU.GRPBE0.BIT.IS0) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR0 = 1; + + /* BSP_INT_SRC_BE0_CAN0_ERS0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN0_ERS0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BE0 IS1 */ + if (1 == ICU.GRPBE0.BIT.IS1) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR1 = 1; + + /* BSP_INT_SRC_BE0_CAN1_ERS1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN1_ERS1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BE0 IS2 */ + if (1 == ICU.GRPBE0.BIT.IS2) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR2 = 1; + + /* BSP_INT_SRC_BE0_CAN2_ERS2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN2_ERS2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_be0_handler_isr() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h new file mode 100644 index 000000000..14c6960d4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h @@ -0,0 +1,230 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_GROUP_STILL_ENABLED, /* Not all group interrupts were disabled so group interrupt was not + disabled */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_EXC_FPU, /* FPU exception */ + BSP_INT_SRC_EXC_ACCESS, /* Access exception */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_WDT_ERROR, /* WDT underflow/refresh error has occurred */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_RAM, /* RAM error interrupt */ + BSP_INT_SRC_EXRAM, /* EXRAM error interrupt */ + BSP_INT_SRC_ECCRAM_1BIT, /* ECCRAM 1-bit error interrupt */ + BSP_INT_SRC_ECCRAM_2BIT, /* ECCRAM 2-bit error interrupt */ + BSP_INT_SRC_DPFPUEX, /* Double-Precision Floating-Point Exception interrupt */ + + BSP_INT_SRC_GR_INT_TOP, + + /* IE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_IE0_TOP, + BSP_INT_SRC_IE0_DPFPU_DPFPUEX, + + /* BE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_BE0_TOP, + BSP_INT_SRC_BE0_CAN0_ERS0, + BSP_INT_SRC_BE0_CAN1_ERS1, + BSP_INT_SRC_BE0_CAN2_ERS2, + + /* BL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL0_TOP, + BSP_INT_SRC_BL0_SCI0_TEI0, + BSP_INT_SRC_BL0_SCI0_ERI0, + BSP_INT_SRC_BL0_SCI1_TEI1, + BSP_INT_SRC_BL0_SCI1_ERI1, + BSP_INT_SRC_BL0_SCI2_TEI2, + BSP_INT_SRC_BL0_SCI2_ERI2, + BSP_INT_SRC_BL0_SCI3_TEI3, + BSP_INT_SRC_BL0_SCI3_ERI3, + BSP_INT_SRC_BL0_SCI4_TEI4, + BSP_INT_SRC_BL0_SCI4_ERI4, + BSP_INT_SRC_BL0_SCI5_TEI5, + BSP_INT_SRC_BL0_SCI5_ERI5, + BSP_INT_SRC_BL0_SCI6_TEI6, + BSP_INT_SRC_BL0_SCI6_ERI6, + BSP_INT_SRC_BL0_SCI12_TEI12, + BSP_INT_SRC_BL0_SCI12_ERI12, + BSP_INT_SRC_BL0_SCI12_SCIX0, + BSP_INT_SRC_BL0_SCI12_SCIX1, + BSP_INT_SRC_BL0_SCI12_SCIX2, + BSP_INT_SRC_BL0_SCI12_SCIX3, + BSP_INT_SRC_BL0_QSPI_QSPSSLI, + BSP_INT_SRC_BL0_CAC_FERRI, + BSP_INT_SRC_BL0_CAC_MENDI, + BSP_INT_SRC_BL0_CAC_OVFI, + BSP_INT_SRC_BL0_DOC_DOPCI, + BSP_INT_SRC_BL0_PDC_PCFEI, + BSP_INT_SRC_BL0_PDC_PCERI, + + /* BL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL1_TOP, + BSP_INT_SRC_BL1_SDHI_CDETI, + BSP_INT_SRC_BL1_SDHI_CACI, + BSP_INT_SRC_BL1_SDHI_SDACI, + BSP_INT_SRC_BL1_MMCIF_CDETIO, + BSP_INT_SRC_BL1_MMCIF_ERRIO, + BSP_INT_SRC_BL1_MMCIF_ACCIO, + BSP_INT_SRC_BL1_POE3_OEI1, + BSP_INT_SRC_BL1_POE3_OEI2, + BSP_INT_SRC_BL1_POE3_OEI3, + BSP_INT_SRC_BL1_POE3_OEI4, + BSP_INT_SRC_BL1_RIIC0_TEI0, + BSP_INT_SRC_BL1_RIIC0_EEI0, + BSP_INT_SRC_BL1_RIIC2_TEI2, + BSP_INT_SRC_BL1_RIIC2_EEI2, + BSP_INT_SRC_BL1_SSIE0_SSIF0, + BSP_INT_SRC_BL1_SSIE1_SSIF1, + BSP_INT_SRC_BL1_S12AD0_S12CMPAI, + BSP_INT_SRC_BL1_S12AD0_S12CMPBI, + BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, + BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, + BSP_INT_SRC_BL1_RIIC1_TEI1, + BSP_INT_SRC_BL1_RIIC1_EEI1, + + /* BL2 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL2_TOP, + BSP_INT_SRC_BL2_POEG_POEGGAI, + BSP_INT_SRC_BL2_POEG_POEGGBI, + BSP_INT_SRC_BL2_POEG_POEGGCI, + BSP_INT_SRC_BL2_POEG_POEGGDI, + + /* AL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL0_TOP, + BSP_INT_SRC_AL0_SCI8_TEI8, + BSP_INT_SRC_AL0_SCI8_ERI8, + BSP_INT_SRC_AL0_SCI9_TEI9, + BSP_INT_SRC_AL0_SCI9_ERI9, + BSP_INT_SRC_AL0_SCI10_TEI10, + BSP_INT_SRC_AL0_SCI10_ERI10, + BSP_INT_SRC_AL0_SCI11_TEI11, + BSP_INT_SRC_AL0_SCI11_ERI11, + BSP_INT_SRC_AL0_RSPI0_SPII0, + BSP_INT_SRC_AL0_RSPI0_SPEI0, + BSP_INT_SRC_AL0_RSPI1_SPII1, + BSP_INT_SRC_AL0_RSPI1_SPEI1, + BSP_INT_SRC_AL0_RSPI2_SPII2, + BSP_INT_SRC_AL0_RSPI2_SPEI2, + BSP_INT_SRC_AL0_SCI7_TEI7, + BSP_INT_SRC_AL0_SCI7_ERI7, + + /* AL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL1_TOP, + BSP_INT_SRC_AL1_EPTPC_MINT, + BSP_INT_SRC_AL1_PTPEDMAC_PINT, + BSP_INT_SRC_AL1_EDMAC0_EINT0, + BSP_INT_SRC_AL1_EDMAC1_EINT1, + BSP_INT_SRC_AL1_GLCDC_VPOS, + BSP_INT_SRC_AL1_GLCDC_GR1UF, + BSP_INT_SRC_AL1_GLCDC_GR2UF, + BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, + + BSP_INT_SRC_GR_INT_END, + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for FPU, and Bus Error) */ + BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, /* Enables a group interrupt when a group interrupt source is given. The + pdata argument should give the IPL to be used using the bsp_int_ctrl_t + type. If a group interrupt is enabled multiple times with different IPL + levels it will use the highest given IPL. */ + BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, /* Disables a group interrupt when a group interrupt source is given. + This will only disable a group interrupt when all interrupt + sources for that group are already disabled. */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h new file mode 100644 index 000000000..c3fadfc4a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h @@ -0,0 +1,211 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.h +* Device(s) : RX72N +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_LOCKS_H +#define MCU_LOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you + will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not + using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */ +typedef enum +{ + BSP_LOCK_BSC = 0, + BSP_LOCK_CAC, + BSP_LOCK_CAN0, + BSP_LOCK_CAN1, + BSP_LOCK_CAN2, + BSP_LOCK_CMT, + BSP_LOCK_CMT0, + BSP_LOCK_CMT1, + BSP_LOCK_CMT2, + BSP_LOCK_CMT3, + BSP_LOCK_CMTW0, + BSP_LOCK_CMTW1, + BSP_LOCK_CRC, + BSP_LOCK_DA, + BSP_LOCK_DMAC, + BSP_LOCK_DMAC0, + BSP_LOCK_DMAC1, + BSP_LOCK_DMAC2, + BSP_LOCK_DMAC3, + BSP_LOCK_DMAC4, + BSP_LOCK_DMAC5, + BSP_LOCK_DMAC6, + BSP_LOCK_DMAC7, + BSP_LOCK_DOC, + BSP_LOCK_DRW2D, + BSP_LOCK_DTC, + BSP_LOCK_ECCRAM, + BSP_LOCK_EDMAC0, + BSP_LOCK_EDMAC1, + BSP_LOCK_ELC, + BSP_LOCK_EPTPC, + BSP_LOCK_EPTPC0, + BSP_LOCK_EPTPC1, + BSP_LOCK_ETHERC0, + BSP_LOCK_ETHERC1, + BSP_LOCK_EXDMAC, + BSP_LOCK_EXDMAC0, + BSP_LOCK_EXDMAC1, + BSP_LOCK_FLASH, + BSP_LOCK_GLCDC, + BSP_LOCK_GPTW0, + BSP_LOCK_GPTW1, + BSP_LOCK_GPTW2, + BSP_LOCK_GPTW3, + BSP_LOCK_IRQ0, + BSP_LOCK_IRQ1, + BSP_LOCK_IRQ2, + BSP_LOCK_IRQ3, + BSP_LOCK_IRQ4, + BSP_LOCK_IRQ5, + BSP_LOCK_IRQ6, + BSP_LOCK_IRQ7, + BSP_LOCK_IRQ8, + BSP_LOCK_IRQ9, + BSP_LOCK_IRQ10, + BSP_LOCK_IRQ11, + BSP_LOCK_IRQ12, + BSP_LOCK_IRQ13, + BSP_LOCK_IRQ14, + BSP_LOCK_IRQ15, + BSP_LOCK_ICU, + BSP_LOCK_IWDT, + BSP_LOCK_MMC, + BSP_LOCK_MPC, + BSP_LOCK_MPU, + BSP_LOCK_MTU, + BSP_LOCK_MTU0, + BSP_LOCK_MTU1, + BSP_LOCK_MTU2, + BSP_LOCK_MTU3, + BSP_LOCK_MTU4, + BSP_LOCK_MTU5, + BSP_LOCK_MTU6, + BSP_LOCK_MTU7, + BSP_LOCK_MTU8, + BSP_LOCK_PDC, + BSP_LOCK_PMGI0, + BSP_LOCK_PMGI1, + BSP_LOCK_POE, + BSP_LOCK_POEG, + BSP_LOCK_PPG0, + BSP_LOCK_PPG1, + BSP_LOCK_PTPEDMAC, + BSP_LOCK_QSPI, + BSP_LOCK_RAM, + BSP_LOCK_RIIC0, + BSP_LOCK_RIIC1, + BSP_LOCK_RIIC2, + BSP_LOCK_RSPI0, + BSP_LOCK_RSPI1, + BSP_LOCK_RSPI2, + BSP_LOCK_RTC, + BSP_LOCK_S12AD, + BSP_LOCK_S12AD1, + BSP_LOCK_SCI0, + BSP_LOCK_SCI1, + BSP_LOCK_SCI2, + BSP_LOCK_SCI3, + BSP_LOCK_SCI4, + BSP_LOCK_SCI5, + BSP_LOCK_SCI6, + BSP_LOCK_SCI7, + BSP_LOCK_SCI8, + BSP_LOCK_SCI9, + BSP_LOCK_SCI10, + BSP_LOCK_SCI11, + BSP_LOCK_SCI12, + BSP_LOCK_SDHI, + BSP_LOCK_SSIE0, + BSP_LOCK_SSIE1, + BSP_LOCK_SYSTEM, + BSP_LOCK_TEMPS, + BSP_LOCK_TMR0, + BSP_LOCK_TMR1, + BSP_LOCK_TMR2, + BSP_LOCK_TMR3, + BSP_LOCK_TMR01, + BSP_LOCK_TMR23, + BSP_LOCK_TPU0, + BSP_LOCK_TPU1, + BSP_LOCK_TPU2, + BSP_LOCK_TPU3, + BSP_LOCK_TPU4, + BSP_LOCK_TPU5, + BSP_LOCK_TPUA, + BSP_LOCK_USB, + BSP_LOCK_USB0, + BSP_LOCK_WDT, + BSP_LOCK_FLASHCONST, + BSP_LOCK_TEMPSCONST, + BSP_LOCK_SWINT, + BSP_LOCK_SWINT2, + BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch! +} mcu_lock_t; + +typedef struct +{ + /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */ + int32_t lock; + + /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */ +} bsp_lock_t; + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 +#undef BSP_CFG_USER_LOCKING_TYPE +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t +#else + #if !defined(BSP_CFG_USER_LOCKING_TYPE) + #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h." + #endif +#endif + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[]; + +#endif /* MCU_LOCKS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c new file mode 100644 index 000000000..5d26263b2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c @@ -0,0 +1,877 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_mapped_interrupt_open +* Description : Initializes mapped interrupts. This code does the following for each possible mapped interrupt: +* 1) PREPROCCESOR - Test to see if this interrupt is chosen to be used +* 2) PREPROCESSOR - Figure out which interrupt select register needs to be written to +* 3) RUNTIME C - Set the appropriate select register with the number of this mapped interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open (void) +{ +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) = BSP_PRV_INT_B_NUM_CMT2_CMI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) = BSP_PRV_INT_B_NUM_CMT3_CMI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) = BSP_PRV_INT_B_NUM_TMR0_CMIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) = BSP_PRV_INT_B_NUM_TMR0_CMIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) = BSP_PRV_INT_B_NUM_TMR0_OVI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) = BSP_PRV_INT_B_NUM_TMR1_CMIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) = BSP_PRV_INT_B_NUM_TMR1_CMIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) = BSP_PRV_INT_B_NUM_TMR1_OVI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) = BSP_PRV_INT_B_NUM_TMR2_CMIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) = BSP_PRV_INT_B_NUM_TMR2_CMIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) = BSP_PRV_INT_B_NUM_TMR2_OVI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) = BSP_PRV_INT_B_NUM_TMR3_CMIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) = BSP_PRV_INT_B_NUM_TMR3_CMIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) = BSP_PRV_INT_B_NUM_TMR3_OVI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) = BSP_PRV_INT_B_NUM_TPU0_TGI0A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) = BSP_PRV_INT_B_NUM_TPU0_TGI0B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) = BSP_PRV_INT_B_NUM_TPU0_TGI0C; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) = BSP_PRV_INT_B_NUM_TPU0_TGI0D; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) = BSP_PRV_INT_B_NUM_TPU0_TCI0V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) = BSP_PRV_INT_B_NUM_TPU1_TGI1A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) = BSP_PRV_INT_B_NUM_TPU1_TGI1B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) = BSP_PRV_INT_B_NUM_TPU1_TCI1V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) = BSP_PRV_INT_B_NUM_TPU1_TCI1U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) = BSP_PRV_INT_B_NUM_TPU2_TGI2A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) = BSP_PRV_INT_B_NUM_TPU2_TGI2B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) = BSP_PRV_INT_B_NUM_TPU2_TCI2V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) = BSP_PRV_INT_B_NUM_TPU2_TCI2U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) = BSP_PRV_INT_B_NUM_TPU3_TGI3A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) = BSP_PRV_INT_B_NUM_TPU3_TGI3B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) = BSP_PRV_INT_B_NUM_TPU3_TGI3C; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) = BSP_PRV_INT_B_NUM_TPU3_TGI3D; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) = BSP_PRV_INT_B_NUM_TPU3_TCI3V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) = BSP_PRV_INT_B_NUM_TPU4_TGI4A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) = BSP_PRV_INT_B_NUM_TPU4_TGI4B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) = BSP_PRV_INT_B_NUM_TPU4_TCI4V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) = BSP_PRV_INT_B_NUM_TPU4_TCI4U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) = BSP_PRV_INT_B_NUM_TPU5_TGI5A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) = BSP_PRV_INT_B_NUM_TPU5_TGI5B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) = BSP_PRV_INT_B_NUM_TPU5_TCI5V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) = BSP_PRV_INT_B_NUM_TPU5_TCI5U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) = BSP_PRV_INT_B_NUM_CMTW0_IC0I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) = BSP_PRV_INT_B_NUM_CMTW0_IC1I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) = BSP_PRV_INT_B_NUM_CMTW0_OC0I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) = BSP_PRV_INT_B_NUM_CMTW0_OC1I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) = BSP_PRV_INT_B_NUM_CMTW1_IC0I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) = BSP_PRV_INT_B_NUM_CMTW1_IC1I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) = BSP_PRV_INT_B_NUM_CMTW1_OC0I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) = BSP_PRV_INT_B_NUM_CMTW1_OC1I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) = BSP_PRV_INT_B_NUM_RTC_CUP; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) = BSP_PRV_INT_B_NUM_CAN0_RXF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) = BSP_PRV_INT_B_NUM_CAN0_TXF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) = BSP_PRV_INT_B_NUM_CAN0_RXM0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) = BSP_PRV_INT_B_NUM_CAN0_TXM0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) = BSP_PRV_INT_B_NUM_CAN1_RXF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) = BSP_PRV_INT_B_NUM_CAN1_TXF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) = BSP_PRV_INT_B_NUM_CAN1_RXM1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) = BSP_PRV_INT_B_NUM_CAN1_TXM1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) = BSP_PRV_INT_B_NUM_CAN2_RXF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) = BSP_PRV_INT_B_NUM_CAN2_TXF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) = BSP_PRV_INT_B_NUM_CAN2_RXM2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) = BSP_PRV_INT_B_NUM_CAN2_TXM2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) = BSP_PRV_INT_B_NUM_USB0_USBI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) = BSP_PRV_INT_B_NUM_ELC_ELSR18I; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) = BSP_PRV_INT_B_NUM_ELC_ELSR19I; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) = BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) = BSP_PRV_INT_B_NUM_TSIP_ROMOK; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) = BSP_PRV_INT_B_NUM_TSIP_LONG_PLG; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) = BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) = BSP_PRV_INT_B_NUM_TSIP_WRRDY0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) = BSP_PRV_INT_B_NUM_TSIP_WRRDY1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) = BSP_PRV_INT_B_NUM_TSIP_WRRDY4; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) = BSP_PRV_INT_B_NUM_TSIP_RDRDY0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) = BSP_PRV_INT_B_NUM_TSIP_RDRDY1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) = BSP_PRV_INT_A_NUM_MTU0_TGIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) = BSP_PRV_INT_A_NUM_MTU0_TGIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) = BSP_PRV_INT_A_NUM_MTU0_TGIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) = BSP_PRV_INT_A_NUM_MTU0_TGID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) = BSP_PRV_INT_A_NUM_MTU0_TCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) = BSP_PRV_INT_A_NUM_MTU0_TGIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) = BSP_PRV_INT_A_NUM_MTU0_TGIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) = BSP_PRV_INT_A_NUM_MTU1_TGIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) = BSP_PRV_INT_A_NUM_MTU1_TGIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) = BSP_PRV_INT_A_NUM_MTU1_TCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) = BSP_PRV_INT_A_NUM_MTU1_TCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) = BSP_PRV_INT_A_NUM_MTU2_TGIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) = BSP_PRV_INT_A_NUM_MTU2_TGIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) = BSP_PRV_INT_A_NUM_MTU2_TCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) = BSP_PRV_INT_A_NUM_MTU2_TCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) = BSP_PRV_INT_A_NUM_MTU3_TGIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) = BSP_PRV_INT_A_NUM_MTU3_TGIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) = BSP_PRV_INT_A_NUM_MTU3_TGIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) = BSP_PRV_INT_A_NUM_MTU3_TGID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) = BSP_PRV_INT_A_NUM_MTU3_TCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) = BSP_PRV_INT_A_NUM_MTU4_TGIA4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) = BSP_PRV_INT_A_NUM_MTU4_TGIB4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) = BSP_PRV_INT_A_NUM_MTU4_TGIC4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) = BSP_PRV_INT_A_NUM_MTU4_TGID4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) = BSP_PRV_INT_A_NUM_MTU4_TCIV4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) = BSP_PRV_INT_A_NUM_MTU5_TGIU5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) = BSP_PRV_INT_A_NUM_MTU5_TGIV5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) = BSP_PRV_INT_A_NUM_MTU5_TGIW5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) = BSP_PRV_INT_A_NUM_MTU6_TGIA6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) = BSP_PRV_INT_A_NUM_MTU6_TGIB6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) = BSP_PRV_INT_A_NUM_MTU6_TGIC6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) = BSP_PRV_INT_A_NUM_MTU6_TGID6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) = BSP_PRV_INT_A_NUM_MTU6_TCIV6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) = BSP_PRV_INT_A_NUM_MTU7_TGIA7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) = BSP_PRV_INT_A_NUM_MTU7_TGIB7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) = BSP_PRV_INT_A_NUM_MTU7_TGIC7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) = BSP_PRV_INT_A_NUM_MTU7_TGID7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) = BSP_PRV_INT_A_NUM_MTU7_TCIV7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) = BSP_PRV_INT_A_NUM_MTU8_TGIA8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) = BSP_PRV_INT_A_NUM_MTU8_TGIB8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) = BSP_PRV_INT_A_NUM_MTU8_TGIC8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) = BSP_PRV_INT_A_NUM_MTU8_TGID8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) = BSP_PRV_INT_A_NUM_MTU8_TCIV8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) = BSP_PRV_INT_A_NUM_GPTW0_GTCID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) = BSP_PRV_INT_A_NUM_GPTW0_GDTE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIU0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIC1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) = BSP_PRV_INT_A_NUM_GPTW1_GTCID1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) = BSP_PRV_INT_A_NUM_GPTW1_GDTE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIC2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) = BSP_PRV_INT_A_NUM_GPTW2_GTCID2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) = BSP_PRV_INT_A_NUM_GPTW2_GDTE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) = BSP_PRV_INT_A_NUM_GPTW3_GTCID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) = BSP_PRV_INT_A_NUM_GPTW3_GDTE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIF3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIU3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) = BSP_PRV_INT_A_NUM_EPTPC_IPLS; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) = BSP_PRV_INT_A_NUM_PMGI0_PMGI0I; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) = BSP_PRV_INT_A_NUM_PMGI1_PMGI1I; +#endif +} /* End of function bsp_mapped_interrupt_open() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h new file mode 100644 index 000000000..aed97bbcd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h @@ -0,0 +1,1692 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_H +#define MCU_MAPPED_INTERRUPTS_H + +/* The following macros define the number for each interrupt request source as it pertains to being an Interrupt B or + * Interrupt A interrupt. These values are used when setting the interrupt select registers (i.e. SLIBXRn, SLIBrn, and + * SLIARn). + */ +/* Available Interrupt B Sources. */ +#define BSP_PRV_INT_B_NUM_CMT2_CMI2 1 +#define BSP_PRV_INT_B_NUM_CMT3_CMI3 2 +#define BSP_PRV_INT_B_NUM_TMR0_CMIA0 3 +#define BSP_PRV_INT_B_NUM_TMR0_CMIB0 4 +#define BSP_PRV_INT_B_NUM_TMR0_OVI0 5 +#define BSP_PRV_INT_B_NUM_TMR1_CMIA1 6 +#define BSP_PRV_INT_B_NUM_TMR1_CMIB1 7 +#define BSP_PRV_INT_B_NUM_TMR1_OVI1 8 +#define BSP_PRV_INT_B_NUM_TMR2_CMIA2 9 +#define BSP_PRV_INT_B_NUM_TMR2_CMIB2 10 +#define BSP_PRV_INT_B_NUM_TMR2_OVI2 11 +#define BSP_PRV_INT_B_NUM_TMR3_CMIA3 12 +#define BSP_PRV_INT_B_NUM_TMR3_CMIB3 13 +#define BSP_PRV_INT_B_NUM_TMR3_OVI3 14 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0A 15 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0B 16 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0C 17 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0D 18 +#define BSP_PRV_INT_B_NUM_TPU0_TCI0V 19 +#define BSP_PRV_INT_B_NUM_TPU1_TGI1A 20 +#define BSP_PRV_INT_B_NUM_TPU1_TGI1B 21 +#define BSP_PRV_INT_B_NUM_TPU1_TCI1V 22 +#define BSP_PRV_INT_B_NUM_TPU1_TCI1U 23 +#define BSP_PRV_INT_B_NUM_TPU2_TGI2A 24 +#define BSP_PRV_INT_B_NUM_TPU2_TGI2B 25 +#define BSP_PRV_INT_B_NUM_TPU2_TCI2V 26 +#define BSP_PRV_INT_B_NUM_TPU2_TCI2U 27 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3A 28 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3B 29 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3C 30 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3D 31 +#define BSP_PRV_INT_B_NUM_TPU3_TCI3V 32 +#define BSP_PRV_INT_B_NUM_TPU4_TGI4A 33 +#define BSP_PRV_INT_B_NUM_TPU4_TGI4B 34 +#define BSP_PRV_INT_B_NUM_TPU4_TCI4V 35 +#define BSP_PRV_INT_B_NUM_TPU4_TCI4U 36 +#define BSP_PRV_INT_B_NUM_TPU5_TGI5A 37 +#define BSP_PRV_INT_B_NUM_TPU5_TGI5B 38 +#define BSP_PRV_INT_B_NUM_TPU5_TCI5V 39 +#define BSP_PRV_INT_B_NUM_TPU5_TCI5U 40 +#define BSP_PRV_INT_B_NUM_CMTW0_IC0I0 41 +#define BSP_PRV_INT_B_NUM_CMTW0_IC1I0 42 +#define BSP_PRV_INT_B_NUM_CMTW0_OC0I0 43 +#define BSP_PRV_INT_B_NUM_CMTW0_OC1I0 44 +#define BSP_PRV_INT_B_NUM_CMTW1_IC0I1 45 +#define BSP_PRV_INT_B_NUM_CMTW1_IC1I1 46 +#define BSP_PRV_INT_B_NUM_CMTW1_OC0I1 47 +#define BSP_PRV_INT_B_NUM_CMTW1_OC1I1 48 +#define BSP_PRV_INT_B_NUM_RTC_CUP 49 +#define BSP_PRV_INT_B_NUM_CAN0_RXF0 50 +#define BSP_PRV_INT_B_NUM_CAN0_TXF0 51 +#define BSP_PRV_INT_B_NUM_CAN0_RXM0 52 +#define BSP_PRV_INT_B_NUM_CAN0_TXM0 53 +#define BSP_PRV_INT_B_NUM_CAN1_RXF1 54 +#define BSP_PRV_INT_B_NUM_CAN1_TXF1 55 +#define BSP_PRV_INT_B_NUM_CAN1_RXM1 56 +#define BSP_PRV_INT_B_NUM_CAN1_TXM1 57 +#define BSP_PRV_INT_B_NUM_CAN2_RXF2 58 +#define BSP_PRV_INT_B_NUM_CAN2_TXF2 59 +#define BSP_PRV_INT_B_NUM_CAN2_RXM2 60 +#define BSP_PRV_INT_B_NUM_CAN2_TXM2 61 +#define BSP_PRV_INT_B_NUM_USB0_USBI0 62 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0 64 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0 65 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0 66 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1 68 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1 69 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1 70 +#define BSP_PRV_INT_B_NUM_ELC_ELSR18I 79 +#define BSP_PRV_INT_B_NUM_ELC_ELSR19I 80 +#define BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY 85 +#define BSP_PRV_INT_B_NUM_TSIP_ROMOK 86 +#define BSP_PRV_INT_B_NUM_TSIP_LONG_PLG 87 +#define BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY 88 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY0 89 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY1 90 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY4 91 +#define BSP_PRV_INT_B_NUM_TSIP_RDRDY0 92 +#define BSP_PRV_INT_B_NUM_TSIP_RDRDY1 93 +#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY 94 +#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY 95 + +/* Available Interrupt A Sources. */ +#define BSP_PRV_INT_A_NUM_MTU0_TGIA0 1 +#define BSP_PRV_INT_A_NUM_MTU0_TGIB0 2 +#define BSP_PRV_INT_A_NUM_MTU0_TGIC0 3 +#define BSP_PRV_INT_A_NUM_MTU0_TGID0 4 +#define BSP_PRV_INT_A_NUM_MTU0_TCIV0 5 +#define BSP_PRV_INT_A_NUM_MTU0_TGIE0 6 +#define BSP_PRV_INT_A_NUM_MTU0_TGIF0 7 +#define BSP_PRV_INT_A_NUM_MTU1_TGIA1 8 +#define BSP_PRV_INT_A_NUM_MTU1_TGIB1 9 +#define BSP_PRV_INT_A_NUM_MTU1_TCIV1 10 +#define BSP_PRV_INT_A_NUM_MTU1_TCIU1 11 +#define BSP_PRV_INT_A_NUM_MTU2_TGIA2 12 +#define BSP_PRV_INT_A_NUM_MTU2_TGIB2 13 +#define BSP_PRV_INT_A_NUM_MTU2_TCIV2 14 +#define BSP_PRV_INT_A_NUM_MTU2_TCIU2 15 +#define BSP_PRV_INT_A_NUM_MTU3_TGIA3 16 +#define BSP_PRV_INT_A_NUM_MTU3_TGIB3 17 +#define BSP_PRV_INT_A_NUM_MTU3_TGIC3 18 +#define BSP_PRV_INT_A_NUM_MTU3_TGID3 19 +#define BSP_PRV_INT_A_NUM_MTU3_TCIV3 20 +#define BSP_PRV_INT_A_NUM_MTU4_TGIA4 21 +#define BSP_PRV_INT_A_NUM_MTU4_TGIB4 22 +#define BSP_PRV_INT_A_NUM_MTU4_TGIC4 23 +#define BSP_PRV_INT_A_NUM_MTU4_TGID4 24 +#define BSP_PRV_INT_A_NUM_MTU4_TCIV4 25 +#define BSP_PRV_INT_A_NUM_MTU5_TGIU5 27 +#define BSP_PRV_INT_A_NUM_MTU5_TGIV5 28 +#define BSP_PRV_INT_A_NUM_MTU5_TGIW5 29 +#define BSP_PRV_INT_A_NUM_MTU6_TGIA6 30 +#define BSP_PRV_INT_A_NUM_MTU6_TGIB6 31 +#define BSP_PRV_INT_A_NUM_MTU6_TGIC6 32 +#define BSP_PRV_INT_A_NUM_MTU6_TGID6 33 +#define BSP_PRV_INT_A_NUM_MTU6_TCIV6 34 +#define BSP_PRV_INT_A_NUM_MTU7_TGIA7 35 +#define BSP_PRV_INT_A_NUM_MTU7_TGIB7 36 +#define BSP_PRV_INT_A_NUM_MTU7_TGIC7 37 +#define BSP_PRV_INT_A_NUM_MTU7_TGID7 38 +#define BSP_PRV_INT_A_NUM_MTU7_TCIV7 39 +#define BSP_PRV_INT_A_NUM_MTU8_TGIA8 41 +#define BSP_PRV_INT_A_NUM_MTU8_TGIB8 42 +#define BSP_PRV_INT_A_NUM_MTU8_TGIC8 43 +#define BSP_PRV_INT_A_NUM_MTU8_TGID8 44 +#define BSP_PRV_INT_A_NUM_MTU8_TCIV8 45 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIA0 47 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIB0 48 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIC0 49 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCID0 50 +#define BSP_PRV_INT_A_NUM_GPTW0_GDTE0 51 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIE0 52 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIF0 53 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIV0 54 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIU0 55 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIA1 58 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIB1 59 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIC1 60 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCID1 61 +#define BSP_PRV_INT_A_NUM_GPTW1_GDTE1 62 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIE1 63 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIF1 64 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIV1 65 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIU1 66 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIA2 67 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIB2 68 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIC2 69 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCID2 70 +#define BSP_PRV_INT_A_NUM_GPTW2_GDTE2 71 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIE2 72 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIF2 73 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIV2 74 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIU2 75 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIA3 76 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIB3 77 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIC3 78 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCID3 79 +#define BSP_PRV_INT_A_NUM_GPTW3_GDTE3 80 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIE3 81 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIF3 82 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIV3 83 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIU3 84 +#define BSP_PRV_INT_A_NUM_EPTPC_IPLS 86 +#define BSP_PRV_INT_A_NUM_PMGI0_PMGI0I 98 +#define BSP_PRV_INT_A_NUM_PMGI1_PMGI1I 99 + +/* The appropriate macros will now be defined based on the vector selections made by the user. + * These are the same macros that are defined for constant-mapped interrupts (vectors 0-127). This means that the + * code can define, setup, and use mapped interrupts the same as would be done for constant-mapped interrupts. + */ +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IR_CMT2_CMI2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define DTCE_CMT2_CMI2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IER_CMT2_CMI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IPR_CMT2_CMI2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IEN_CMT2_CMI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define VECT_CMT2_CMI2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IR_CMT3_CMI3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define DTCE_CMT3_CMI3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IER_CMT3_CMI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IPR_CMT3_CMI3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IEN_CMT3_CMI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define VECT_CMT3_CMI3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IR_TPU0_TGI0A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define DTCE_TPU0_TGI0A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IER_TPU0_TGI0A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IPR_TPU0_TGI0A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IEN_TPU0_TGI0A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define VECT_TPU0_TGI0A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IR_TPU0_TGI0B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define DTCE_TPU0_TGI0B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IER_TPU0_TGI0B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IPR_TPU0_TGI0B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IEN_TPU0_TGI0B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define VECT_TPU0_TGI0B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IR_TPU0_TGI0C BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define DTCE_TPU0_TGI0C BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IER_TPU0_TGI0C BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IPR_TPU0_TGI0C BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IEN_TPU0_TGI0C BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define VECT_TPU0_TGI0C BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IR_TPU0_TGI0D BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define DTCE_TPU0_TGI0D BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IER_TPU0_TGI0D BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IPR_TPU0_TGI0D BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IEN_TPU0_TGI0D BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define VECT_TPU0_TGI0D BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IR_TPU0_TCI0V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define DTCE_TPU0_TCI0V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IER_TPU0_TCI0V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IPR_TPU0_TCI0V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IEN_TPU0_TCI0V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define VECT_TPU0_TCI0V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IR_TPU1_TGI1B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define DTCE_TPU1_TGI1B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IER_TPU1_TGI1B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IPR_TPU1_TGI1B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IEN_TPU1_TGI1B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define VECT_TPU1_TGI1B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IR_TPU1_TCI1V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define DTCE_TPU1_TCI1V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IER_TPU1_TCI1V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IPR_TPU1_TCI1V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IEN_TPU1_TCI1V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define VECT_TPU1_TCI1V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IR_TPU1_TCI1U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define DTCE_TPU1_TCI1U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IER_TPU1_TCI1U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IPR_TPU1_TCI1U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IEN_TPU1_TCI1U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define VECT_TPU1_TCI1U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IR_TPU2_TGI2A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define DTCE_TPU2_TGI2A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IER_TPU2_TGI2A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IPR_TPU2_TGI2A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IEN_TPU2_TGI2A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define VECT_TPU2_TGI2A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IR_TPU2_TGI2B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define DTCE_TPU2_TGI2B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IER_TPU2_TGI2B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IPR_TPU2_TGI2B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IEN_TPU2_TGI2B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define VECT_TPU2_TGI2B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IR_TPU2_TCI2V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define DTCE_TPU2_TCI2V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IER_TPU2_TCI2V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IPR_TPU2_TCI2V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IEN_TPU2_TCI2V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define VECT_TPU2_TCI2V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IR_TPU2_TCI2U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define DTCE_TPU2_TCI2U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IER_TPU2_TCI2U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IPR_TPU2_TCI2U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IEN_TPU2_TCI2U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define VECT_TPU2_TCI2U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IR_TPU3_TGI3A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define DTCE_TPU3_TGI3A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IER_TPU3_TGI3A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IPR_TPU3_TGI3A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IEN_TPU3_TGI3A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define VECT_TPU3_TGI3A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IR_TPU3_TGI3B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define DTCE_TPU3_TGI3B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IER_TPU3_TGI3B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IPR_TPU3_TGI3B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IEN_TPU3_TGI3B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define VECT_TPU3_TGI3B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IR_TPU1_TGI1A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define DTCE_TPU1_TGI1A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IER_TPU1_TGI1A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IPR_TPU1_TGI1A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IEN_TPU1_TGI1A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define VECT_TPU1_TGI1A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IR_TPU3_TGI3C BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define DTCE_TPU3_TGI3C BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IER_TPU3_TGI3C BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IPR_TPU3_TGI3C BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IEN_TPU3_TGI3C BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define VECT_TPU3_TGI3C BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IR_TMR0_CMIA0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define DTCE_TMR0_CMIA0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IER_TMR0_CMIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IPR_TMR0_CMIA0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IEN_TMR0_CMIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define VECT_TMR0_CMIA0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IR_TMR0_CMIB0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define DTCE_TMR0_CMIB0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IER_TMR0_CMIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IPR_TMR0_CMIB0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IEN_TMR0_CMIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define VECT_TMR0_CMIB0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IR_TMR0_OVI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define DTCE_TMR0_OVI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IER_TMR0_OVI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IPR_TMR0_OVI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IEN_TMR0_OVI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define VECT_TMR0_OVI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IR_TMR1_CMIA1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define DTCE_TMR1_CMIA1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IER_TMR1_CMIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IPR_TMR1_CMIA1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IEN_TMR1_CMIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define VECT_TMR1_CMIA1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IR_TMR1_CMIB1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define DTCE_TMR1_CMIB1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IER_TMR1_CMIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IPR_TMR1_CMIB1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IEN_TMR1_CMIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define VECT_TMR1_CMIB1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IR_TMR1_OVI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define DTCE_TMR1_OVI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IER_TMR1_OVI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IPR_TMR1_OVI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IEN_TMR1_OVI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define VECT_TMR1_OVI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IR_TMR2_CMIA2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define DTCE_TMR2_CMIA2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IER_TMR2_CMIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IPR_TMR2_CMIA2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IEN_TMR2_CMIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define VECT_TMR2_CMIA2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IR_TMR2_CMIB2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define DTCE_TMR2_CMIB2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IER_TMR2_CMIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IPR_TMR2_CMIB2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IEN_TMR2_CMIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define VECT_TMR2_CMIB2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IR_TMR2_OVI2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define DTCE_TMR2_OVI2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IER_TMR2_OVI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IPR_TMR2_OVI2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IEN_TMR2_OVI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define VECT_TMR2_OVI2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IR_TMR3_CMIA3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define DTCE_TMR3_CMIA3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IER_TMR3_CMIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IPR_TMR3_CMIA3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IEN_TMR3_CMIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define VECT_TMR3_CMIA3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IR_TMR3_CMIB3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define DTCE_TMR3_CMIB3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IER_TMR3_CMIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IPR_TMR3_CMIB3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IEN_TMR3_CMIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define VECT_TMR3_CMIB3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IR_TMR3_OVI3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define DTCE_TMR3_OVI3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IER_TMR3_OVI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IPR_TMR3_OVI3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IEN_TMR3_OVI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define VECT_TMR3_OVI3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IR_TPU3_TGI3D BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define DTCE_TPU3_TGI3D BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IER_TPU3_TGI3D BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IPR_TPU3_TGI3D BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IEN_TPU3_TGI3D BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define VECT_TPU3_TGI3D BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IR_TPU3_TCI3V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define DTCE_TPU3_TCI3V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IER_TPU3_TCI3V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IPR_TPU3_TCI3V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IEN_TPU3_TCI3V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define VECT_TPU3_TCI3V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IR_TPU4_TGI4A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define DTCE_TPU4_TGI4A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IER_TPU4_TGI4A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IPR_TPU4_TGI4A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IEN_TPU4_TGI4A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define VECT_TPU4_TGI4A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IR_TPU4_TGI4B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define DTCE_TPU4_TGI4B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IER_TPU4_TGI4B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IPR_TPU4_TGI4B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IEN_TPU4_TGI4B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define VECT_TPU4_TGI4B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IR_TPU4_TCI4V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define DTCE_TPU4_TCI4V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IER_TPU4_TCI4V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IPR_TPU4_TCI4V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IEN_TPU4_TCI4V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define VECT_TPU4_TCI4V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IR_TPU4_TCI4U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define DTCE_TPU4_TCI4U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IER_TPU4_TCI4U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IPR_TPU4_TCI4U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IEN_TPU4_TCI4U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define VECT_TPU4_TCI4U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IR_TPU5_TGI5A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define DTCE_TPU5_TGI5A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IER_TPU5_TGI5A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IPR_TPU5_TGI5A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IEN_TPU5_TGI5A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define VECT_TPU5_TGI5A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IR_TPU5_TGI5B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define DTCE_TPU5_TGI5B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IER_TPU5_TGI5B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IPR_TPU5_TGI5B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IEN_TPU5_TGI5B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define VECT_TPU5_TGI5B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IR_TPU5_TCI5V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define DTCE_TPU5_TCI5V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IER_TPU5_TCI5V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IPR_TPU5_TCI5V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IEN_TPU5_TCI5V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define VECT_TPU5_TCI5V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IR_TPU5_TCI5U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define DTCE_TPU5_TCI5U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IER_TPU5_TCI5U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IPR_TPU5_TCI5U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IEN_TPU5_TCI5U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define VECT_TPU5_TCI5U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IR_CMTW0_IC0I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define DTCE_CMTW0_IC0I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IER_CMTW0_IC0I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IPR_CMTW0_IC0I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IEN_CMTW0_IC0I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define VECT_CMTW0_IC0I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IR_CMTW0_IC1I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define DTCE_CMTW0_IC1I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IER_CMTW0_IC1I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IPR_CMTW0_IC1I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IEN_CMTW0_IC1I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define VECT_CMTW0_IC1I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IR_CMTW0_OC0I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define DTCE_CMTW0_OC0I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IER_CMTW0_OC0I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IPR_CMTW0_OC0I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IEN_CMTW0_OC0I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define VECT_CMTW0_OC0I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IR_CMTW0_OC1I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define DTCE_CMTW0_OC1I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IER_CMTW0_OC1I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IPR_CMTW0_OC1I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IEN_CMTW0_OC1I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define VECT_CMTW0_OC1I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IR_CMTW1_IC0I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define DTCE_CMTW1_IC0I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IER_CMTW1_IC0I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IPR_CMTW1_IC0I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IEN_CMTW1_IC0I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define VECT_CMTW1_IC0I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IR_CMTW1_IC1I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define DTCE_CMTW1_IC1I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IER_CMTW1_IC1I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IPR_CMTW1_IC1I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IEN_CMTW1_IC1I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define VECT_CMTW1_IC1I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IR_CMTW1_OC0I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define DTCE_CMTW1_OC0I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IER_CMTW1_OC0I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IPR_CMTW1_OC0I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IEN_CMTW1_OC0I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define VECT_CMTW1_OC0I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IR_CMTW1_OC1I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define DTCE_CMTW1_OC1I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IER_CMTW1_OC1I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IPR_CMTW1_OC1I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IEN_CMTW1_OC1I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define VECT_CMTW1_OC1I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IR_RTC_CUP BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define DTCE_RTC_CUP BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IER_RTC_CUP BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IPR_RTC_CUP BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IEN_RTC_CUP BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define VECT_RTC_CUP BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IR_CAN0_RXF0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define DTCE_CAN0_RXF0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IER_CAN0_RXF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IPR_CAN0_RXF0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IEN_CAN0_RXF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define VECT_CAN0_RXF0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IR_CAN0_TXF0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define DTCE_CAN0_TXF0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IER_CAN0_TXF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IPR_CAN0_TXF0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IEN_CAN0_TXF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define VECT_CAN0_TXF0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IR_CAN0_RXM0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define DTCE_CAN0_RXM0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IER_CAN0_RXM0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IPR_CAN0_RXM0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IEN_CAN0_RXM0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define VECT_CAN0_RXM0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IR_CAN0_TXM0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define DTCE_CAN0_TXM0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IER_CAN0_TXM0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IPR_CAN0_TXM0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IEN_CAN0_TXM0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define VECT_CAN0_TXM0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IR_CAN1_RXF1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define DTCE_CAN1_RXF1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IER_CAN1_RXF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IPR_CAN1_RXF1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IEN_CAN1_RXF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define VECT_CAN1_RXF1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IR_CAN1_TXF1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define DTCE_CAN1_TXF1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IER_CAN1_TXF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IPR_CAN1_TXF1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IEN_CAN1_TXF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define VECT_CAN1_TXF1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IR_CAN1_RXM1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define DTCE_CAN1_RXM1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IER_CAN1_RXM1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IPR_CAN1_RXM1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IEN_CAN1_RXM1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define VECT_CAN1_RXM1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IR_CAN1_TXM1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define DTCE_CAN1_TXM1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IER_CAN1_TXM1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IPR_CAN1_TXM1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IEN_CAN1_TXM1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define VECT_CAN1_TXM1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IR_CAN2_RXF2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define DTCE_CAN2_RXF2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IER_CAN2_RXF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IPR_CAN2_RXF2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IEN_CAN2_RXF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define VECT_CAN2_RXF2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IR_CAN2_TXF2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define DTCE_CAN2_TXF2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IER_CAN2_TXF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IPR_CAN2_TXF2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IEN_CAN2_TXF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define VECT_CAN2_TXF2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IR_CAN2_RXM2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define DTCE_CAN2_RXM2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IER_CAN2_RXM2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IPR_CAN2_RXM2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IEN_CAN2_RXM2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define VECT_CAN2_RXM2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IR_CAN2_TXM2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define DTCE_CAN2_TXM2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IER_CAN2_TXM2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IPR_CAN2_TXM2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IEN_CAN2_TXM2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define VECT_CAN2_TXM2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IR_USB0_USBI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define DTCE_USB0_USBI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IER_USB0_USBI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IPR_USB0_USBI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IEN_USB0_USBI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define VECT_USB0_USBI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IR_S12ADC0_S12ADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define DTCE_S12ADC0_S12ADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IER_S12ADC0_S12ADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IPR_S12ADC0_S12ADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IEN_S12ADC0_S12ADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define VECT_S12ADC0_S12ADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IR_S12ADC0_S12GBADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define DTCE_S12ADC0_S12GBADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IER_S12ADC0_S12GBADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IPR_S12ADC0_S12GBADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IEN_S12ADC0_S12GBADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define VECT_S12ADC0_S12GBADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IR_S12ADC0_S12GCADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define DTCE_S12ADC0_S12GCADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IER_S12ADC0_S12GCADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IPR_S12ADC0_S12GCADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IEN_S12ADC0_S12GCADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define VECT_S12ADC0_S12GCADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IR_S12ADC1_S12ADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define DTCE_S12ADC1_S12ADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IER_S12ADC1_S12ADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IPR_S12ADC1_S12ADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IEN_S12ADC1_S12ADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define VECT_S12ADC1_S12ADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IR_S12ADC1_S12GBADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define DTCE_S12ADC1_S12GBADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IER_S12ADC1_S12GBADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IPR_S12ADC1_S12GBADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IEN_S12ADC1_S12GBADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define VECT_S12ADC1_S12GBADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IR_S12ADC1_S12GCADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define DTCE_S12ADC1_S12GCADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IER_S12ADC1_S12GCADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IPR_S12ADC1_S12GCADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IEN_S12ADC1_S12GCADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define VECT_S12ADC1_S12GCADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IR_ELC_ELSR18I BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define DTCE_ELC_ELSR18I BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IER_ELC_ELSR18I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IPR_ELC_ELSR18I BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IEN_ELC_ELSR18I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define VECT_ELC_ELSR18I BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IR_ELC_ELSR19I BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define DTCE_ELC_ELSR19I BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IER_ELC_ELSR19I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IPR_ELC_ELSR19I BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IEN_ELC_ELSR19I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define VECT_ELC_ELSR19I BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IR_TSIP_PROC_BUSY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define DTCE_TSIP_PROC_BUSY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IER_TSIP_PROC_BUSY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IPR_TSIP_PROC_BUSY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IEN_TSIP_PROC_BUSY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define VECT_TSIP_PROC_BUSY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IR_TSIP_ROMOK BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define DTCE_TSIP_ROMOK BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IER_TSIP_ROMOK BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IPR_TSIP_ROMOK BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IEN_TSIP_ROMOK BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define VECT_TSIP_ROMOK BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IR_TSIP_LONG_PLG BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define DTCE_TSIP_LONG_PLG BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IER_TSIP_LONG_PLG BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IPR_TSIP_LONG_PLG BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IEN_TSIP_LONG_PLG BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define VECT_TSIP_LONG_PLG BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IR_TSIP_TEST_BUSY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define DTCE_TSIP_TEST_BUSY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IER_TSIP_TEST_BUSY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IPR_TSIP_TEST_BUSY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IEN_TSIP_TEST_BUSY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define VECT_TSIP_TEST_BUSY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IR_TSIP_WRRDY0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define DTCE_TSIP_WRRDY0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IER_TSIP_WRRDY0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IPR_TSIP_WRRDY0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IEN_TSIP_WRRDY0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define VECT_TSIP_WRRDY0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IR_TSIP_WRRDY1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define DTCE_TSIP_WRRDY1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IER_TSIP_WRRDY1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IPR_TSIP_WRRDY1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IEN_TSIP_WRRDY1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define VECT_TSIP_WRRDY1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IR_TSIP_WRRDY4 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define DTCE_TSIP_WRRDY4 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IER_TSIP_WRRDY4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IPR_TSIP_WRRDY4 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IEN_TSIP_WRRDY4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define VECT_TSIP_WRRDY4 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IR_TSIP_RDRDY0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define DTCE_TSIP_RDRDY0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IER_TSIP_RDRDY0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IPR_TSIP_RDRDY0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IEN_TSIP_RDRDY0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define VECT_TSIP_RDRDY0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IR_TSIP_RDRDY1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define DTCE_TSIP_RDRDY1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IER_TSIP_RDRDY1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IPR_TSIP_RDRDY1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IEN_TSIP_RDRDY1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define VECT_TSIP_RDRDY1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IR_TSIP_INTEGRATE_WRRDY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define DTCE_TSIP_INTEGRATE_WRRDY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IER_TSIP_INTEGRATE_WRRDY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IPR_TSIP_INTEGRATE_WRRDY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IEN_TSIP_INTEGRATE_WRRDY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define VECT_TSIP_INTEGRATE_WRRDY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IR_TSIP_INTEGRATE_RDRDY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define DTCE_TSIP_INTEGRATE_RDRDY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IER_TSIP_INTEGRATE_RDRDY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IPR_TSIP_INTEGRATE_RDRDY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IEN_TSIP_INTEGRATE_RDRDY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define VECT_TSIP_INTEGRATE_RDRDY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IR_MTU1_TGIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define DTCE_MTU1_TGIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IER_MTU1_TGIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IPR_MTU1_TGIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IEN_MTU1_TGIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define VECT_MTU1_TGIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IR_MTU0_TGIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define DTCE_MTU0_TGIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IER_MTU0_TGIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IPR_MTU0_TGIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IEN_MTU0_TGIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define VECT_MTU0_TGIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IR_MTU0_TGIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define DTCE_MTU0_TGIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IER_MTU0_TGIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IPR_MTU0_TGIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IEN_MTU0_TGIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define VECT_MTU0_TGIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IR_MTU0_TGIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define DTCE_MTU0_TGIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IER_MTU0_TGIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IPR_MTU0_TGIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IEN_MTU0_TGIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define VECT_MTU0_TGIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IR_MTU0_TGID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define DTCE_MTU0_TGID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IER_MTU0_TGID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IPR_MTU0_TGID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IEN_MTU0_TGID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define VECT_MTU0_TGID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IR_MTU0_TCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define DTCE_MTU0_TCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IER_MTU0_TCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IPR_MTU0_TCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IEN_MTU0_TCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define VECT_MTU0_TCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IR_MTU0_TGIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define DTCE_MTU0_TGIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IER_MTU0_TGIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IPR_MTU0_TGIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IEN_MTU0_TGIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define VECT_MTU0_TGIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IR_MTU0_TGIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define DTCE_MTU0_TGIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IER_MTU0_TGIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IPR_MTU0_TGIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IEN_MTU0_TGIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define VECT_MTU0_TGIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IR_MTU1_TGIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define DTCE_MTU1_TGIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IER_MTU1_TGIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IPR_MTU1_TGIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IEN_MTU1_TGIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define VECT_MTU1_TGIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IR_MTU1_TCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define DTCE_MTU1_TCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IER_MTU1_TCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IPR_MTU1_TCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IEN_MTU1_TCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define VECT_MTU1_TCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IR_MTU1_TCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define DTCE_MTU1_TCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IER_MTU1_TCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IPR_MTU1_TCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IEN_MTU1_TCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define VECT_MTU1_TCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IR_MTU2_TGIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define DTCE_MTU2_TGIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IER_MTU2_TGIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IPR_MTU2_TGIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IEN_MTU2_TGIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define VECT_MTU2_TGIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IR_MTU2_TGIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define DTCE_MTU2_TGIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IER_MTU2_TGIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IPR_MTU2_TGIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IEN_MTU2_TGIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define VECT_MTU2_TGIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IR_MTU2_TCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define DTCE_MTU2_TCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IER_MTU2_TCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IPR_MTU2_TCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IEN_MTU2_TCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define VECT_MTU2_TCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IR_MTU2_TCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define DTCE_MTU2_TCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IER_MTU2_TCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IPR_MTU2_TCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IEN_MTU2_TCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define VECT_MTU2_TCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IR_MTU3_TGIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define DTCE_MTU3_TGIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IER_MTU3_TGIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IPR_MTU3_TGIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IEN_MTU3_TGIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define VECT_MTU3_TGIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IR_MTU3_TGIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define DTCE_MTU3_TGIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IER_MTU3_TGIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IPR_MTU3_TGIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IEN_MTU3_TGIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define VECT_MTU3_TGIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IR_MTU3_TGIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define DTCE_MTU3_TGIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IER_MTU3_TGIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IPR_MTU3_TGIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IEN_MTU3_TGIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define VECT_MTU3_TGIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IR_MTU3_TGID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define DTCE_MTU3_TGID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IER_MTU3_TGID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IPR_MTU3_TGID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IEN_MTU3_TGID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define VECT_MTU3_TGID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IR_MTU3_TCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define DTCE_MTU3_TCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IER_MTU3_TCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IPR_MTU3_TCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IEN_MTU3_TCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define VECT_MTU3_TCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IR_MTU4_TGIA4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define DTCE_MTU4_TGIA4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IER_MTU4_TGIA4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IPR_MTU4_TGIA4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IEN_MTU4_TGIA4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define VECT_MTU4_TGIA4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IR_MTU4_TGIB4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define DTCE_MTU4_TGIB4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IER_MTU4_TGIB4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IPR_MTU4_TGIB4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IEN_MTU4_TGIB4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define VECT_MTU4_TGIB4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IR_MTU4_TGIC4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define DTCE_MTU4_TGIC4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IER_MTU4_TGIC4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IPR_MTU4_TGIC4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IEN_MTU4_TGIC4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define VECT_MTU4_TGIC4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IR_MTU4_TGID4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define DTCE_MTU4_TGID4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IER_MTU4_TGID4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IPR_MTU4_TGID4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IEN_MTU4_TGID4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define VECT_MTU4_TGID4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IR_MTU4_TCIV4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define DTCE_MTU4_TCIV4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IER_MTU4_TCIV4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IPR_MTU4_TCIV4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IEN_MTU4_TCIV4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define VECT_MTU4_TCIV4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IR_MTU5_TGIU5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define DTCE_MTU5_TGIU5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IER_MTU5_TGIU5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IPR_MTU5_TGIU5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IEN_MTU5_TGIU5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define VECT_MTU5_TGIU5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IR_MTU5_TGIV5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define DTCE_MTU5_TGIV5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IER_MTU5_TGIV5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IPR_MTU5_TGIV5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IEN_MTU5_TGIV5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define VECT_MTU5_TGIV5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IR_MTU5_TGIW5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define DTCE_MTU5_TGIW5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IER_MTU5_TGIW5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IPR_MTU5_TGIW5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IEN_MTU5_TGIW5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define VECT_MTU5_TGIW5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IR_MTU6_TGIA6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define DTCE_MTU6_TGIA6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IER_MTU6_TGIA6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IPR_MTU6_TGIA6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IEN_MTU6_TGIA6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define VECT_MTU6_TGIA6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IR_MTU6_TGIB6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define DTCE_MTU6_TGIB6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IER_MTU6_TGIB6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IPR_MTU6_TGIB6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IEN_MTU6_TGIB6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define VECT_MTU6_TGIB6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IR_MTU6_TGIC6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define DTCE_MTU6_TGIC6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IER_MTU6_TGIC6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IPR_MTU6_TGIC6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IEN_MTU6_TGIC6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define VECT_MTU6_TGIC6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IR_MTU6_TGID6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define DTCE_MTU6_TGID6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IER_MTU6_TGID6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IPR_MTU6_TGID6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IEN_MTU6_TGID6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define VECT_MTU6_TGID6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IR_MTU6_TCIV6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define DTCE_MTU6_TCIV6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IER_MTU6_TCIV6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IPR_MTU6_TCIV6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IEN_MTU6_TCIV6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define VECT_MTU6_TCIV6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IR_MTU7_TGIA7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define DTCE_MTU7_TGIA7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IER_MTU7_TGIA7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IPR_MTU7_TGIA7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IEN_MTU7_TGIA7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define VECT_MTU7_TGIA7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IR_MTU7_TGIB7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define DTCE_MTU7_TGIB7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IER_MTU7_TGIB7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IPR_MTU7_TGIB7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IEN_MTU7_TGIB7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define VECT_MTU7_TGIB7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IR_MTU7_TGIC7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define DTCE_MTU7_TGIC7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IER_MTU7_TGIC7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IPR_MTU7_TGIC7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IEN_MTU7_TGIC7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define VECT_MTU7_TGIC7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IR_MTU7_TGID7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define DTCE_MTU7_TGID7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IER_MTU7_TGID7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IPR_MTU7_TGID7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IEN_MTU7_TGID7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define VECT_MTU7_TGID7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IR_MTU7_TCIV7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define DTCE_MTU7_TCIV7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IER_MTU7_TCIV7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IPR_MTU7_TCIV7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IEN_MTU7_TCIV7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define VECT_MTU7_TCIV7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IR_MTU8_TGIA8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define DTCE_MTU8_TGIA8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IER_MTU8_TGIA8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IPR_MTU8_TGIA8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IEN_MTU8_TGIA8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define VECT_MTU8_TGIA8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IR_MTU8_TGIB8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define DTCE_MTU8_TGIB8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IER_MTU8_TGIB8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IPR_MTU8_TGIB8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IEN_MTU8_TGIB8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define VECT_MTU8_TGIB8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IR_MTU8_TGIC8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define DTCE_MTU8_TGIC8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IER_MTU8_TGIC8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IPR_MTU8_TGIC8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IEN_MTU8_TGIC8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define VECT_MTU8_TGIC8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IR_MTU8_TGID8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define DTCE_MTU8_TGID8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IER_MTU8_TGID8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IPR_MTU8_TGID8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IEN_MTU8_TGID8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define VECT_MTU8_TGID8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IR_MTU8_TCIV8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define DTCE_MTU8_TCIV8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IER_MTU8_TCIV8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IPR_MTU8_TCIV8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IEN_MTU8_TCIV8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define VECT_MTU8_TCIV8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IR_GPTW0_GTCIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define DTCE_GPTW0_GTCIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IER_GPTW0_GTCIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IPR_GPTW0_GTCIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IEN_GPTW0_GTCIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define VECT_GPTW0_GTCIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IR_GPTW0_GTCIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define DTCE_GPTW0_GTCIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IER_GPTW0_GTCIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IPR_GPTW0_GTCIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IEN_GPTW0_GTCIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define VECT_GPTW0_GTCIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IR_GPTW0_GTCIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define DTCE_GPTW0_GTCIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IER_GPTW0_GTCIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IPR_GPTW0_GTCIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IEN_GPTW0_GTCIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define VECT_GPTW0_GTCIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IR_GPTW0_GTCID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define DTCE_GPTW0_GTCID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IER_GPTW0_GTCID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IPR_GPTW0_GTCID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IEN_GPTW0_GTCID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define VECT_GPTW0_GTCID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IR_GPTW0_GDTE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define DTCE_GPTW0_GDTE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IER_GPTW0_GDTE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IPR_GPTW0_GDTE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IEN_GPTW0_GDTE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define VECT_GPTW0_GDTE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IR_GPTW0_GTCIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define DTCE_GPTW0_GTCIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IER_GPTW0_GTCIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IPR_GPTW0_GTCIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IEN_GPTW0_GTCIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define VECT_GPTW0_GTCIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IR_GPTW0_GTCIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define DTCE_GPTW0_GTCIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IER_GPTW0_GTCIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IPR_GPTW0_GTCIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IEN_GPTW0_GTCIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define VECT_GPTW0_GTCIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IR_GPTW0_GTCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define DTCE_GPTW0_GTCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IER_GPTW0_GTCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IPR_GPTW0_GTCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IEN_GPTW0_GTCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define VECT_GPTW0_GTCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IR_GPTW0_GTCIU0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define DTCE_GPTW0_GTCIU0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IER_GPTW0_GTCIU0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IPR_GPTW0_GTCIU0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IEN_GPTW0_GTCIU0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define VECT_GPTW0_GTCIU0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IR_GPTW1_GTCIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define DTCE_GPTW1_GTCIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IER_GPTW1_GTCIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IPR_GPTW1_GTCIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IEN_GPTW1_GTCIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define VECT_GPTW1_GTCIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IR_GPTW1_GTCIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define DTCE_GPTW1_GTCIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IER_GPTW1_GTCIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IPR_GPTW1_GTCIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IEN_GPTW1_GTCIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define VECT_GPTW1_GTCIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IR_GPTW1_GTCIC1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define DTCE_GPTW1_GTCIC1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IER_GPTW1_GTCIC1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IPR_GPTW1_GTCIC1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IEN_GPTW1_GTCIC1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define VECT_GPTW1_GTCIC1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IR_GPTW1_GTCID1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define DTCE_GPTW1_GTCID1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IER_GPTW1_GTCID1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IPR_GPTW1_GTCID1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IEN_GPTW1_GTCID1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define VECT_GPTW1_GTCID1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IR_GPTW1_GDTE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define DTCE_GPTW1_GDTE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IER_GPTW1_GDTE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IPR_GPTW1_GDTE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IEN_GPTW1_GDTE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define VECT_GPTW1_GDTE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IR_GPTW1_GTCIE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define DTCE_GPTW1_GTCIE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IER_GPTW1_GTCIE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IPR_GPTW1_GTCIE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IEN_GPTW1_GTCIE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define VECT_GPTW1_GTCIE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IR_GPTW1_GTCIF1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define DTCE_GPTW1_GTCIF1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IER_GPTW1_GTCIF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IPR_GPTW1_GTCIF1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IEN_GPTW1_GTCIF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define VECT_GPTW1_GTCIF1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IR_GPTW1_GTCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define DTCE_GPTW1_GTCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IER_GPTW1_GTCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IPR_GPTW1_GTCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IEN_GPTW1_GTCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define VECT_GPTW1_GTCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IR_GPTW1_GTCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define DTCE_GPTW1_GTCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IER_GPTW1_GTCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IPR_GPTW1_GTCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IEN_GPTW1_GTCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define VECT_GPTW1_GTCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IR_GPTW2_GTCIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define DTCE_GPTW2_GTCIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IER_GPTW2_GTCIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IPR_GPTW2_GTCIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IEN_GPTW2_GTCIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define VECT_GPTW2_GTCIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IR_GPTW2_GTCIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define DTCE_GPTW2_GTCIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IER_GPTW2_GTCIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IPR_GPTW2_GTCIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IEN_GPTW2_GTCIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define VECT_GPTW2_GTCIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IR_GPTW2_GTCIC2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define DTCE_GPTW2_GTCIC2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IER_GPTW2_GTCIC2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IPR_GPTW2_GTCIC2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IEN_GPTW2_GTCIC2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define VECT_GPTW2_GTCIC2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IR_GPTW2_GTCID2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define DTCE_GPTW2_GTCID2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IER_GPTW2_GTCID2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IPR_GPTW2_GTCID2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IEN_GPTW2_GTCID2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define VECT_GPTW2_GTCID2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IR_GPTW2_GDTE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define DTCE_GPTW2_GDTE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IER_GPTW2_GDTE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IPR_GPTW2_GDTE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IEN_GPTW2_GDTE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define VECT_GPTW2_GDTE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IR_GPTW2_GTCIE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define DTCE_GPTW2_GTCIE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IER_GPTW2_GTCIE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IPR_GPTW2_GTCIE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IEN_GPTW2_GTCIE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define VECT_GPTW2_GTCIE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IR_GPTW2_GTCIF2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define DTCE_GPTW2_GTCIF2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IER_GPTW2_GTCIF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IPR_GPTW2_GTCIF2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IEN_GPTW2_GTCIF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define VECT_GPTW2_GTCIF2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IR_GPTW2_GTCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define DTCE_GPTW2_GTCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IER_GPTW2_GTCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IPR_GPTW2_GTCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IEN_GPTW2_GTCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define VECT_GPTW2_GTCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IR_GPTW2_GTCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define DTCE_GPTW2_GTCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IER_GPTW2_GTCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IPR_GPTW2_GTCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IEN_GPTW2_GTCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define VECT_GPTW2_GTCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IR_GPTW3_GTCIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define DTCE_GPTW3_GTCIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IER_GPTW3_GTCIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IPR_GPTW3_GTCIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IEN_GPTW3_GTCIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define VECT_GPTW3_GTCIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IR_GPTW3_GTCIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define DTCE_GPTW3_GTCIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IER_GPTW3_GTCIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IPR_GPTW3_GTCIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IEN_GPTW3_GTCIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define VECT_GPTW3_GTCIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IR_GPTW3_GTCIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define DTCE_GPTW3_GTCIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IER_GPTW3_GTCIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IPR_GPTW3_GTCIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IEN_GPTW3_GTCIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define VECT_GPTW3_GTCIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IR_GPTW3_GTCID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define DTCE_GPTW3_GTCID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IER_GPTW3_GTCID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IPR_GPTW3_GTCID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IEN_GPTW3_GTCID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define VECT_GPTW3_GTCID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IR_GPTW3_GDTE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define DTCE_GPTW3_GDTE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IER_GPTW3_GDTE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IPR_GPTW3_GDTE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IEN_GPTW3_GDTE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define VECT_GPTW3_GDTE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IR_GPTW3_GTCIE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define DTCE_GPTW3_GTCIE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IER_GPTW3_GTCIE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IPR_GPTW3_GTCIE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IEN_GPTW3_GTCIE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define VECT_GPTW3_GTCIE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IR_GPTW3_GTCIF3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define DTCE_GPTW3_GTCIF3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IER_GPTW3_GTCIF3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IPR_GPTW3_GTCIF3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IEN_GPTW3_GTCIF3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define VECT_GPTW3_GTCIF3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IR_GPTW3_GTCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define DTCE_GPTW3_GTCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IER_GPTW3_GTCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IPR_GPTW3_GTCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IEN_GPTW3_GTCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define VECT_GPTW3_GTCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IR_GPTW3_GTCIU3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define DTCE_GPTW3_GTCIU3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IER_GPTW3_GTCIU3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IPR_GPTW3_GTCIU3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IEN_GPTW3_GTCIU3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define VECT_GPTW3_GTCIU3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IR_EPTPC_IPLS BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define DTCE_EPTPC_IPLS BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IER_EPTPC_IPLS BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IPR_EPTPC_IPLS BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IEN_EPTPC_IPLS BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define VECT_EPTPC_IPLS BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IR_PMGI0_PMGI0I BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define DTCE_PMGI0_PMGI0I BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IER_PMGI0_PMGI0I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IPR_PMGI0_PMGI0I BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IEN_PMGI0_PMGI0I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define VECT_PMGI0_PMGI0I BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IR_PMGI1_PMGI1I BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define DTCE_PMGI1_PMGI1I BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IER_PMGI1_PMGI1I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IPR_PMGI1_PMGI1I BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IEN_PMGI1_PMGI1I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define VECT_PMGI1_PMGI1I BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_MAPPED_INTERRUPTS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h new file mode 100644 index 000000000..edd0636ae --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h @@ -0,0 +1,360 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts_private.h +* Description : This module contains macros used for mapping interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_PRIVATE_H +#define MCU_MAPPED_INTERRUPTS_PRIVATE_H + +/* These macros are calculated values for x % 8. These macros are used when preprocessor arithmetic cannot be used. + * For example, 'IEN0'-'IEN7' needs to be defined for a macro based on 'vector_number % 8' but preprocessor arithmetic + * is only evaluated at compile-time when it is used in a preprocessor conditional. For this reason the calculated + * value of 'vector_number % 8' must be calculated before compile-time. + */ +#define BSP_PRV_CALC_128_MOD_8 0 +#define BSP_PRV_CALC_129_MOD_8 1 +#define BSP_PRV_CALC_130_MOD_8 2 +#define BSP_PRV_CALC_131_MOD_8 3 +#define BSP_PRV_CALC_132_MOD_8 4 +#define BSP_PRV_CALC_133_MOD_8 5 +#define BSP_PRV_CALC_134_MOD_8 6 +#define BSP_PRV_CALC_135_MOD_8 7 +#define BSP_PRV_CALC_136_MOD_8 0 +#define BSP_PRV_CALC_137_MOD_8 1 +#define BSP_PRV_CALC_138_MOD_8 2 +#define BSP_PRV_CALC_139_MOD_8 3 +#define BSP_PRV_CALC_140_MOD_8 4 +#define BSP_PRV_CALC_141_MOD_8 5 +#define BSP_PRV_CALC_142_MOD_8 6 +#define BSP_PRV_CALC_143_MOD_8 7 +#define BSP_PRV_CALC_144_MOD_8 0 +#define BSP_PRV_CALC_145_MOD_8 1 +#define BSP_PRV_CALC_146_MOD_8 2 +#define BSP_PRV_CALC_147_MOD_8 3 +#define BSP_PRV_CALC_148_MOD_8 4 +#define BSP_PRV_CALC_149_MOD_8 5 +#define BSP_PRV_CALC_150_MOD_8 6 +#define BSP_PRV_CALC_151_MOD_8 7 +#define BSP_PRV_CALC_152_MOD_8 0 +#define BSP_PRV_CALC_153_MOD_8 1 +#define BSP_PRV_CALC_154_MOD_8 2 +#define BSP_PRV_CALC_155_MOD_8 3 +#define BSP_PRV_CALC_156_MOD_8 4 +#define BSP_PRV_CALC_157_MOD_8 5 +#define BSP_PRV_CALC_158_MOD_8 6 +#define BSP_PRV_CALC_159_MOD_8 7 +#define BSP_PRV_CALC_160_MOD_8 0 +#define BSP_PRV_CALC_161_MOD_8 1 +#define BSP_PRV_CALC_162_MOD_8 2 +#define BSP_PRV_CALC_163_MOD_8 3 +#define BSP_PRV_CALC_164_MOD_8 4 +#define BSP_PRV_CALC_165_MOD_8 5 +#define BSP_PRV_CALC_166_MOD_8 6 +#define BSP_PRV_CALC_167_MOD_8 7 +#define BSP_PRV_CALC_168_MOD_8 0 +#define BSP_PRV_CALC_169_MOD_8 1 +#define BSP_PRV_CALC_170_MOD_8 2 +#define BSP_PRV_CALC_171_MOD_8 3 +#define BSP_PRV_CALC_172_MOD_8 4 +#define BSP_PRV_CALC_173_MOD_8 5 +#define BSP_PRV_CALC_174_MOD_8 6 +#define BSP_PRV_CALC_175_MOD_8 7 +#define BSP_PRV_CALC_176_MOD_8 0 +#define BSP_PRV_CALC_177_MOD_8 1 +#define BSP_PRV_CALC_178_MOD_8 2 +#define BSP_PRV_CALC_179_MOD_8 3 +#define BSP_PRV_CALC_180_MOD_8 4 +#define BSP_PRV_CALC_181_MOD_8 5 +#define BSP_PRV_CALC_182_MOD_8 6 +#define BSP_PRV_CALC_183_MOD_8 7 +#define BSP_PRV_CALC_184_MOD_8 0 +#define BSP_PRV_CALC_185_MOD_8 1 +#define BSP_PRV_CALC_186_MOD_8 2 +#define BSP_PRV_CALC_187_MOD_8 3 +#define BSP_PRV_CALC_188_MOD_8 4 +#define BSP_PRV_CALC_189_MOD_8 5 +#define BSP_PRV_CALC_190_MOD_8 6 +#define BSP_PRV_CALC_191_MOD_8 7 +#define BSP_PRV_CALC_192_MOD_8 0 +#define BSP_PRV_CALC_193_MOD_8 1 +#define BSP_PRV_CALC_194_MOD_8 2 +#define BSP_PRV_CALC_195_MOD_8 3 +#define BSP_PRV_CALC_196_MOD_8 4 +#define BSP_PRV_CALC_197_MOD_8 5 +#define BSP_PRV_CALC_198_MOD_8 6 +#define BSP_PRV_CALC_199_MOD_8 7 +#define BSP_PRV_CALC_200_MOD_8 0 +#define BSP_PRV_CALC_201_MOD_8 1 +#define BSP_PRV_CALC_202_MOD_8 2 +#define BSP_PRV_CALC_203_MOD_8 3 +#define BSP_PRV_CALC_204_MOD_8 4 +#define BSP_PRV_CALC_205_MOD_8 5 +#define BSP_PRV_CALC_206_MOD_8 6 +#define BSP_PRV_CALC_207_MOD_8 7 +#define BSP_PRV_CALC_208_MOD_8 0 +#define BSP_PRV_CALC_209_MOD_8 1 +#define BSP_PRV_CALC_210_MOD_8 2 +#define BSP_PRV_CALC_211_MOD_8 3 +#define BSP_PRV_CALC_212_MOD_8 4 +#define BSP_PRV_CALC_213_MOD_8 5 +#define BSP_PRV_CALC_214_MOD_8 6 +#define BSP_PRV_CALC_215_MOD_8 7 +#define BSP_PRV_CALC_216_MOD_8 0 +#define BSP_PRV_CALC_217_MOD_8 1 +#define BSP_PRV_CALC_218_MOD_8 2 +#define BSP_PRV_CALC_219_MOD_8 3 +#define BSP_PRV_CALC_220_MOD_8 4 +#define BSP_PRV_CALC_221_MOD_8 5 +#define BSP_PRV_CALC_222_MOD_8 6 +#define BSP_PRV_CALC_223_MOD_8 7 +#define BSP_PRV_CALC_224_MOD_8 0 +#define BSP_PRV_CALC_225_MOD_8 1 +#define BSP_PRV_CALC_226_MOD_8 2 +#define BSP_PRV_CALC_227_MOD_8 3 +#define BSP_PRV_CALC_228_MOD_8 4 +#define BSP_PRV_CALC_229_MOD_8 5 +#define BSP_PRV_CALC_230_MOD_8 6 +#define BSP_PRV_CALC_231_MOD_8 7 +#define BSP_PRV_CALC_232_MOD_8 0 +#define BSP_PRV_CALC_233_MOD_8 1 +#define BSP_PRV_CALC_234_MOD_8 2 +#define BSP_PRV_CALC_235_MOD_8 3 +#define BSP_PRV_CALC_236_MOD_8 4 +#define BSP_PRV_CALC_237_MOD_8 5 +#define BSP_PRV_CALC_238_MOD_8 6 +#define BSP_PRV_CALC_239_MOD_8 7 +#define BSP_PRV_CALC_240_MOD_8 0 +#define BSP_PRV_CALC_241_MOD_8 1 +#define BSP_PRV_CALC_242_MOD_8 2 +#define BSP_PRV_CALC_243_MOD_8 3 +#define BSP_PRV_CALC_244_MOD_8 4 +#define BSP_PRV_CALC_245_MOD_8 5 +#define BSP_PRV_CALC_246_MOD_8 6 +#define BSP_PRV_CALC_247_MOD_8 7 +#define BSP_PRV_CALC_248_MOD_8 0 +#define BSP_PRV_CALC_249_MOD_8 1 +#define BSP_PRV_CALC_250_MOD_8 2 +#define BSP_PRV_CALC_251_MOD_8 3 +#define BSP_PRV_CALC_252_MOD_8 4 +#define BSP_PRV_CALC_253_MOD_8 5 +#define BSP_PRV_CALC_254_MOD_8 6 +#define BSP_PRV_CALC_255_MOD_8 7 + +/* These macros are used to determine if the SLIBXRn or SLIBRn select register should be written to. */ +#define BSP_PRV_INT_B_SELECT_128 ICU.SLIBXR128.BYTE +#define BSP_PRV_INT_B_SELECT_129 ICU.SLIBXR129.BYTE +#define BSP_PRV_INT_B_SELECT_130 ICU.SLIBXR130.BYTE +#define BSP_PRV_INT_B_SELECT_131 ICU.SLIBXR131.BYTE +#define BSP_PRV_INT_B_SELECT_132 ICU.SLIBXR132.BYTE +#define BSP_PRV_INT_B_SELECT_133 ICU.SLIBXR133.BYTE +#define BSP_PRV_INT_B_SELECT_134 ICU.SLIBXR134.BYTE +#define BSP_PRV_INT_B_SELECT_135 ICU.SLIBXR135.BYTE +#define BSP_PRV_INT_B_SELECT_136 ICU.SLIBXR136.BYTE +#define BSP_PRV_INT_B_SELECT_137 ICU.SLIBXR137.BYTE +#define BSP_PRV_INT_B_SELECT_138 ICU.SLIBXR138.BYTE +#define BSP_PRV_INT_B_SELECT_139 ICU.SLIBXR139.BYTE +#define BSP_PRV_INT_B_SELECT_140 ICU.SLIBXR140.BYTE +#define BSP_PRV_INT_B_SELECT_141 ICU.SLIBXR141.BYTE +#define BSP_PRV_INT_B_SELECT_142 ICU.SLIBXR142.BYTE +#define BSP_PRV_INT_B_SELECT_143 ICU.SLIBXR143.BYTE +#define BSP_PRV_INT_B_SELECT_144 ICU.SLIBR144.BYTE +#define BSP_PRV_INT_B_SELECT_145 ICU.SLIBR145.BYTE +#define BSP_PRV_INT_B_SELECT_146 ICU.SLIBR146.BYTE +#define BSP_PRV_INT_B_SELECT_147 ICU.SLIBR147.BYTE +#define BSP_PRV_INT_B_SELECT_148 ICU.SLIBR148.BYTE +#define BSP_PRV_INT_B_SELECT_149 ICU.SLIBR149.BYTE +#define BSP_PRV_INT_B_SELECT_150 ICU.SLIBR150.BYTE +#define BSP_PRV_INT_B_SELECT_151 ICU.SLIBR151.BYTE +#define BSP_PRV_INT_B_SELECT_152 ICU.SLIBR152.BYTE +#define BSP_PRV_INT_B_SELECT_153 ICU.SLIBR153.BYTE +#define BSP_PRV_INT_B_SELECT_154 ICU.SLIBR154.BYTE +#define BSP_PRV_INT_B_SELECT_155 ICU.SLIBR155.BYTE +#define BSP_PRV_INT_B_SELECT_156 ICU.SLIBR156.BYTE +#define BSP_PRV_INT_B_SELECT_157 ICU.SLIBR157.BYTE +#define BSP_PRV_INT_B_SELECT_158 ICU.SLIBR158.BYTE +#define BSP_PRV_INT_B_SELECT_159 ICU.SLIBR159.BYTE +#define BSP_PRV_INT_B_SELECT_160 ICU.SLIBR160.BYTE +#define BSP_PRV_INT_B_SELECT_161 ICU.SLIBR161.BYTE +#define BSP_PRV_INT_B_SELECT_162 ICU.SLIBR162.BYTE +#define BSP_PRV_INT_B_SELECT_163 ICU.SLIBR163.BYTE +#define BSP_PRV_INT_B_SELECT_164 ICU.SLIBR164.BYTE +#define BSP_PRV_INT_B_SELECT_165 ICU.SLIBR165.BYTE +#define BSP_PRV_INT_B_SELECT_166 ICU.SLIBR166.BYTE +#define BSP_PRV_INT_B_SELECT_167 ICU.SLIBR167.BYTE +#define BSP_PRV_INT_B_SELECT_168 ICU.SLIBR168.BYTE +#define BSP_PRV_INT_B_SELECT_169 ICU.SLIBR169.BYTE +#define BSP_PRV_INT_B_SELECT_170 ICU.SLIBR170.BYTE +#define BSP_PRV_INT_B_SELECT_171 ICU.SLIBR171.BYTE +#define BSP_PRV_INT_B_SELECT_172 ICU.SLIBR172.BYTE +#define BSP_PRV_INT_B_SELECT_173 ICU.SLIBR173.BYTE +#define BSP_PRV_INT_B_SELECT_174 ICU.SLIBR174.BYTE +#define BSP_PRV_INT_B_SELECT_175 ICU.SLIBR175.BYTE +#define BSP_PRV_INT_B_SELECT_176 ICU.SLIBR176.BYTE +#define BSP_PRV_INT_B_SELECT_177 ICU.SLIBR177.BYTE +#define BSP_PRV_INT_B_SELECT_178 ICU.SLIBR178.BYTE +#define BSP_PRV_INT_B_SELECT_179 ICU.SLIBR179.BYTE +#define BSP_PRV_INT_B_SELECT_180 ICU.SLIBR180.BYTE +#define BSP_PRV_INT_B_SELECT_181 ICU.SLIBR181.BYTE +#define BSP_PRV_INT_B_SELECT_182 ICU.SLIBR182.BYTE +#define BSP_PRV_INT_B_SELECT_183 ICU.SLIBR183.BYTE +#define BSP_PRV_INT_B_SELECT_184 ICU.SLIBR184.BYTE +#define BSP_PRV_INT_B_SELECT_185 ICU.SLIBR185.BYTE +#define BSP_PRV_INT_B_SELECT_186 ICU.SLIBR186.BYTE +#define BSP_PRV_INT_B_SELECT_187 ICU.SLIBR187.BYTE +#define BSP_PRV_INT_B_SELECT_188 ICU.SLIBR188.BYTE +#define BSP_PRV_INT_B_SELECT_189 ICU.SLIBR189.BYTE +#define BSP_PRV_INT_B_SELECT_190 ICU.SLIBR190.BYTE +#define BSP_PRV_INT_B_SELECT_191 ICU.SLIBR191.BYTE +#define BSP_PRV_INT_B_SELECT_192 ICU.SLIBR192.BYTE +#define BSP_PRV_INT_B_SELECT_193 ICU.SLIBR193.BYTE +#define BSP_PRV_INT_B_SELECT_194 ICU.SLIBR194.BYTE +#define BSP_PRV_INT_B_SELECT_195 ICU.SLIBR195.BYTE +#define BSP_PRV_INT_B_SELECT_196 ICU.SLIBR196.BYTE +#define BSP_PRV_INT_B_SELECT_197 ICU.SLIBR197.BYTE +#define BSP_PRV_INT_B_SELECT_198 ICU.SLIBR198.BYTE +#define BSP_PRV_INT_B_SELECT_199 ICU.SLIBR199.BYTE +#define BSP_PRV_INT_B_SELECT_200 ICU.SLIBR200.BYTE +#define BSP_PRV_INT_B_SELECT_201 ICU.SLIBR201.BYTE +#define BSP_PRV_INT_B_SELECT_202 ICU.SLIBR202.BYTE +#define BSP_PRV_INT_B_SELECT_203 ICU.SLIBR203.BYTE +#define BSP_PRV_INT_B_SELECT_204 ICU.SLIBR204.BYTE +#define BSP_PRV_INT_B_SELECT_205 ICU.SLIBR205.BYTE +#define BSP_PRV_INT_B_SELECT_206 ICU.SLIBR206.BYTE +#define BSP_PRV_INT_B_SELECT_207 ICU.SLIBR207.BYTE +/* Interrupt A interrupts are also defined even though there is only 1 select register. */ +#define BSP_PRV_INT_A_SELECT_208 ICU.SLIAR208.BYTE +#define BSP_PRV_INT_A_SELECT_209 ICU.SLIAR209.BYTE +#define BSP_PRV_INT_A_SELECT_210 ICU.SLIAR210.BYTE +#define BSP_PRV_INT_A_SELECT_211 ICU.SLIAR211.BYTE +#define BSP_PRV_INT_A_SELECT_212 ICU.SLIAR212.BYTE +#define BSP_PRV_INT_A_SELECT_213 ICU.SLIAR213.BYTE +#define BSP_PRV_INT_A_SELECT_214 ICU.SLIAR214.BYTE +#define BSP_PRV_INT_A_SELECT_215 ICU.SLIAR215.BYTE +#define BSP_PRV_INT_A_SELECT_216 ICU.SLIAR216.BYTE +#define BSP_PRV_INT_A_SELECT_217 ICU.SLIAR217.BYTE +#define BSP_PRV_INT_A_SELECT_218 ICU.SLIAR218.BYTE +#define BSP_PRV_INT_A_SELECT_219 ICU.SLIAR219.BYTE +#define BSP_PRV_INT_A_SELECT_220 ICU.SLIAR220.BYTE +#define BSP_PRV_INT_A_SELECT_221 ICU.SLIAR221.BYTE +#define BSP_PRV_INT_A_SELECT_222 ICU.SLIAR222.BYTE +#define BSP_PRV_INT_A_SELECT_223 ICU.SLIAR223.BYTE +#define BSP_PRV_INT_A_SELECT_224 ICU.SLIAR224.BYTE +#define BSP_PRV_INT_A_SELECT_225 ICU.SLIAR225.BYTE +#define BSP_PRV_INT_A_SELECT_226 ICU.SLIAR226.BYTE +#define BSP_PRV_INT_A_SELECT_227 ICU.SLIAR227.BYTE +#define BSP_PRV_INT_A_SELECT_228 ICU.SLIAR228.BYTE +#define BSP_PRV_INT_A_SELECT_229 ICU.SLIAR229.BYTE +#define BSP_PRV_INT_A_SELECT_230 ICU.SLIAR230.BYTE +#define BSP_PRV_INT_A_SELECT_231 ICU.SLIAR231.BYTE +#define BSP_PRV_INT_A_SELECT_232 ICU.SLIAR232.BYTE +#define BSP_PRV_INT_A_SELECT_233 ICU.SLIAR233.BYTE +#define BSP_PRV_INT_A_SELECT_234 ICU.SLIAR234.BYTE +#define BSP_PRV_INT_A_SELECT_235 ICU.SLIAR235.BYTE +#define BSP_PRV_INT_A_SELECT_236 ICU.SLIAR236.BYTE +#define BSP_PRV_INT_A_SELECT_237 ICU.SLIAR237.BYTE +#define BSP_PRV_INT_A_SELECT_238 ICU.SLIAR238.BYTE +#define BSP_PRV_INT_A_SELECT_239 ICU.SLIAR239.BYTE +#define BSP_PRV_INT_A_SELECT_240 ICU.SLIAR240.BYTE +#define BSP_PRV_INT_A_SELECT_241 ICU.SLIAR241.BYTE +#define BSP_PRV_INT_A_SELECT_242 ICU.SLIAR242.BYTE +#define BSP_PRV_INT_A_SELECT_243 ICU.SLIAR243.BYTE +#define BSP_PRV_INT_A_SELECT_244 ICU.SLIAR244.BYTE +#define BSP_PRV_INT_A_SELECT_245 ICU.SLIAR245.BYTE +#define BSP_PRV_INT_A_SELECT_246 ICU.SLIAR246.BYTE +#define BSP_PRV_INT_A_SELECT_247 ICU.SLIAR247.BYTE +#define BSP_PRV_INT_A_SELECT_248 ICU.SLIAR248.BYTE +#define BSP_PRV_INT_A_SELECT_249 ICU.SLIAR249.BYTE +#define BSP_PRV_INT_A_SELECT_250 ICU.SLIAR250.BYTE +#define BSP_PRV_INT_A_SELECT_251 ICU.SLIAR251.BYTE +#define BSP_PRV_INT_A_SELECT_252 ICU.SLIAR252.BYTE +#define BSP_PRV_INT_A_SELECT_253 ICU.SLIAR253.BYTE +#define BSP_PRV_INT_A_SELECT_254 ICU.SLIAR254.BYTE +#define BSP_PRV_INT_A_SELECT_255 ICU.SLIAR255.BYTE + +/* Start and end of Interrupt B and A vectors. */ +#define BSP_PRV_B_INT_VECTOR_START (128) +#define BSP_PRV_B_INT_VECTOR_END (207) +#define BSP_PRV_A_INT_VECTOR_START (208) +#define BSP_PRV_A_INT_VECTOR_END (255) + +/* Start and end of Interrupt B select registers. */ +#define BSP_PRV_SLIBXR_START (128) +#define BSP_PRV_SLIBXR_END (143) +#define BSP_PRV_SLIBR_START (144) +#define BSP_PRV_SLIBR_END (207) + +/* Starting IER register for mapped interrupts. This is used for calculating the IER register based on the + * given vector number. + */ +#define BSP_PRV_MAP_INT_IER_START (0x10) + +/* These are used in function-like macros to expand to letters. */ +#define BSP_PRV_A A +#define BSP_PRV_B B + +/* Test to see if chosen vector is valid for a mapped interrupt. */ +#define BSP_PRV_VALID_MAP_INT(x, y) (((y + 0) >= BSP_PRV_ ## x ## _INT_VECTOR_START) && \ + ((y + 0) <= BSP_PRV_ ## x ## _INT_VECTOR_END)) + +/* Calculation for getting IER register. */ +#define BSP_PRIV_CALC_IER_REG(x) (((x - BSP_PRV_B_INT_VECTOR_START)/8) + BSP_PRV_MAP_INT_IER_START) + +/* These macros generate the macros needed to use the function-like macros from iodefine.h */ +#define BSP_PRV_IR(x, y) _BSP_PRV_IR(x, y) +#define _BSP_PRV_IR(x, y) IR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_DTCE(x, y) _BSP_PRV_DTCE(x, y) +#define _BSP_PRV_DTCE(x, y) DTCE_PERI ## x ## _INT ## x ## y +#define BSP_PRV_IPR(x, y) _BSP_PRV_IPR(x, y) +#define _BSP_PRV_IPR(x, y) IPR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_VECT(x, y) _BSP_PRV_VECT(x, y) +#define _BSP_PRV_VECT(x, y) VECT_PERI ## x ## _INT ## x ## y + +#define BSP_PRV_IEN(x) _BSP_PRV_IEN(x) +#define _BSP_PRV_IEN(x) __BSP_PRV_IEN(BSP_PRV_CALC_ ## x ## _MOD_8) +#define __BSP_PRV_IEN(x) ___BSP_PRV_IEN(x) +#define ___BSP_PRV_IEN(x) IEN ## x + +/* Chooses the correct interrupt select register. */ +#define BSP_PRV_INT_SELECT(x, y) _BSP_PRV_INT_SELECT(x, y) +#define _BSP_PRV_INT_SELECT(x, y) BSP_PRV_INT_ ## x ## _SELECT_ ## y + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* MCU_MAPPED_INTERRUPTS_PRIVATE_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h new file mode 100644 index 000000000..3e389b0f0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.h +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef CPU_H +#define CPU_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The different types of registers that can be protected. */ +typedef enum +{ + /* PRC0 + Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR2, SCKCR3, PACKCR, PLLCR, + PLLCR2, PPLLCR, PPLLCR2, BCKCR, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOCOCR2, OSTDCR, OSTDSR, CKOCR. */ + BSP_REG_PROTECT_CGC = 0, + + /* PRC1 + Enables writing to the registers related to operating modes, low power consumption, the clock generation circuit, + and software reset: SYSCR0, SYSCR1, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD, OPCCR, RSTCKCR, + DPSBYCR, DPSIER0, DPSIER1, DPSIER2, DPSIER3, DPSIFR0, DPSIFR1, DPSIFR2, DPSIFR3, + DPSIEGR0, DPSIEGR1, DPSIEGR2, DPSIEGR3, MOSCWTCR, SOSCWTCR, MOFCR, HOCOPCR, SWRR. */ + BSP_REG_PROTECT_LPC_CGC_SWR, + + /* PRC3 + Enables writing to the registers related to the LVD:LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /* MPC.PWPR + Enables writing to MPC's PFS registers. */ + BSP_REG_PROTECT_MPC, + + /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/ + BSP_REG_PROTECT_TOTAL_ITEMS +} bsp_reg_protect_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptsDisable(void); +void R_BSP_InterruptsEnable(void); +uint32_t R_BSP_CpuInterruptLevelRead(void); +bool R_BSP_CpuInterruptLevelWrite(uint32_t level); +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareReset(void); + +void bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL. +void bsp_ram_initialize(void); + +#endif /* CPU_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h new file mode 100644 index 000000000..184e6624a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.h +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Lock types. */ +#include "mcu_locks.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOCKING_H +#define LOCKING_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bool R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_HardwareLock(mcu_lock_t const hw_index); +bool R_BSP_HardwareUnlock(mcu_lock_t const hw_index); + +#if BSP_CFG_USER_LOCKING_ENABLED != 0 +/* Is user is using their own lock functions then these are the prototypes. */ +bool BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t const hw_index); +bool BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t const hw_index); +#endif + +#endif /* LOCKING_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/register_access/iccrx/iodefine.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/register_access/iccrx/iodefine.h new file mode 100644 index 000000000..997cc58b8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/register_access/iccrx/iodefine.h @@ -0,0 +1,20925 @@ +/* IAR file generator: v1.0 */ + +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/******************************************************************************* +* +* Device : RX/RX700/RX72N +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : V0.50 (2019-03-15) [Hardware Manual Revision : 0.50] +* V1.00C (2019-07-17) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2019 Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX72N */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(BSC,BUSERR) = 0; expands to : */ +/* ICU.IR[16].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(ICU,SWINT2) = 2; expands to : */ +/* IPR(ICU,SWI ) = 2; // SWINT2,SWINT share IPR level. */ +/* ICU.IPR[3].BIT.IPR = 2; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,... expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5,TPUA expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX72NIODEFINE_HEADER__ +#define __RX72NIODEFINE_HEADER__ + +#ifdef __IAR_SYSTEMS_ICC__ +#pragma language=save +#pragma language=extended +#ifndef _SYSTEM_BUILD +#pragma system_include +#endif +#endif + +#ifdef __IAR_SYSTEMS_ICC__ +#define __evenaccess +#else +#define __sfr +#endif + + + +#define IEN_BSC_BUSERR IEN0 +#define IEN_ICU_GROUPIE0 IEN1 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_SSIE0_SSITXI0 IEN6 +#define IEN_SSIE0_SSIRXI0 IEN7 +#define IEN_SSIE1_SSIRTI1 IEN0 +#define IEN_RIIC1_RXI1 IEN2 +#define IEN_RIIC1_TXI1 IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCI8_RXI8 IEN4 +#define IEN_SCI8_TXI8 IEN5 +#define IEN_SCI9_RXI9 IEN6 +#define IEN_SCI9_TXI9 IEN7 +#define IEN_SCI10_RXI10 IEN0 +#define IEN_SCI10_TXI10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL2 IEN3 +#define IEN_RSPI2_SPRI2 IEN4 +#define IEN_RSPI2_SPTI2 IEN5 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCI11_RXI11 IEN2 +#define IEN_SCI11_TXI11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OSTDI IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_ICU_GROUPIE0 17 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_SSIE0_SSITXI0 46 +#define VECT_SSIE0_SSIRXI0 47 +#define VECT_SSIE1_SSIRTI1 48 +#define VECT_RIIC1_RXI1 50 +#define VECT_RIIC1_TXI1 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCI8_RXI8 100 +#define VECT_SCI8_TXI8 101 +#define VECT_SCI9_RXI9 102 +#define VECT_SCI9_TXI9 103 +#define VECT_SCI10_RXI10 104 +#define VECT_SCI10_TXI10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL2 107 +#define VECT_RSPI2_SPRI2 108 +#define VECT_RSPI2_SPTI2 109 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCI11_RXI11 114 +#define VECT_SCI11_TXI11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OSTDI 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPUA SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_GPTW SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW0 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW1 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW2 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW3 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_POEG SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_ETHERC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_PMGI0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ETHERC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_EDMAC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_PMGI1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_EPTPC SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_EPTPC0 SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_EPTPC1 SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_PTPEDMAC SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_GLCDC SYSTEM.MSTPCRC.BIT.MSTPC29 +#define MSTP_DRW2D SYSTEM.MSTPCRC.BIT.MSTPC28 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_ECCRAM SYSTEM.MSTPCRC.BIT.MSTPC6 +#define MSTP_RAM2 SYSTEM.MSTPCRC.BIT.MSTPC2 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_TSIP SYSTEM.MSTPCRD.BIT.MSTPD27 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSIE0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_SSIE1 SYSTEM.MSTPCRD.BIT.MSTPD14 + +#define IS_DPFPU_DPFPUEX IS0 +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_CAN2_ERS2 IS2 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRI IS26 +#define IS_CAC_MENDI IS27 +#define IS_CAC_OVFI IS28 +#define IS_DOC_DOPCI IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_SSIE0_SSIF0 IS17 +#define IS_SSIE1_SSIF1 IS18 +#define IS_S12AD_S12CMPAI IS20 +#define IS_S12AD_S12CMPBI IS21 +#define IS_S12AD1_S12CMPAI1 IS22 +#define IS_S12AD1_S12CMPBI1 IS23 +#define IS_RIIC1_TEI1 IS28 +#define IS_RIIC1_EEI1 IS29 +#define IS_POEG_POEGGAI IS7 +#define IS_POEG_POEGGBI IS8 +#define IS_POEG_POEGGCI IS9 +#define IS_POEG_POEGGDI IS10 +#define IS_SCI8_TEI8 IS0 +#define IS_SCI8_ERI8 IS1 +#define IS_SCI9_TEI9 IS4 +#define IS_SCI9_ERI9 IS5 +#define IS_SCI10_TEI10 IS8 +#define IS_SCI10_ERI10 IS9 +#define IS_SCI11_TEI11 IS12 +#define IS_SCI11_ERI11 IS13 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_RSPI2_SPII2 IS20 +#define IS_RSPI2_SPEI2 IS21 +#define IS_SCI7_TEI7 IS22 +#define IS_SCI7_ERI7 IS23 +#define IS_EPTPC_MINT IS0 +#define IS_PTPEDMAC_PINT IS1 +#define IS_EDMAC0_EINT0 IS4 +#define IS_EDMAC1_EINT1 IS5 +#define IS_GLCDC_VPOS IS8 +#define IS_GLCDC_GR1UF IS9 +#define IS_GLCDC_GR2UF IS10 +#define IS_DRW2D_DRWIRQ IS11 + +#define EN_DPFPU_DPFPUEX EN0 +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_CAN2_ERS2 EN2 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRI EN26 +#define EN_CAC_MENDI EN27 +#define EN_CAC_OVFI EN28 +#define EN_DOC_DOPCI EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_SSIE0_SSIF0 EN17 +#define EN_SSIE1_SSIF1 EN18 +#define EN_S12AD_S12CMPAI EN20 +#define EN_S12AD_S12CMPBI EN21 +#define EN_S12AD1_S12CMPAI1 EN22 +#define EN_S12AD1_S12CMPBI1 EN23 +#define EN_RIIC1_TEI1 EN28 +#define EN_RIIC1_EEI1 EN29 +#define EN_POEG_POEGGAI EN7 +#define EN_POEG_POEGGBI EN8 +#define EN_POEG_POEGGCI EN9 +#define EN_POEG_POEGGDI EN10 +#define EN_SCI8_TEI8 EN0 +#define EN_SCI8_ERI8 EN1 +#define EN_SCI9_TEI9 EN4 +#define EN_SCI9_ERI9 EN5 +#define EN_SCI10_TEI10 EN8 +#define EN_SCI10_ERI10 EN9 +#define EN_SCI11_TEI11 EN12 +#define EN_SCI11_ERI11 EN13 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_RSPI2_SPII2 EN20 +#define EN_RSPI2_SPEI2 EN21 +#define EN_SCI7_TEI7 EN22 +#define EN_SCI7_ERI7 EN23 +#define EN_EPTPC_MINT EN0 +#define EN_PTPEDMAC_PINT EN1 +#define EN_EDMAC0_EINT0 EN4 +#define EN_EDMAC1_EINT1 EN5 +#define EN_GLCDC_VPOS EN8 +#define EN_GLCDC_GR1UF EN9 +#define EN_GLCDC_GR2UF EN10 +#define EN_DRW2D_DRWIRQ EN11 + +#define CLR_DPFPU_DPFPUEX CLR0 +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 +#define CLR_CAN2_ERS2 CLR2 + +#define GEN_DPFPU_DPFPUEX GENIE0 +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_CAN2_ERS2 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRI GENBL0 +#define GEN_CAC_MENDI GENBL0 +#define GEN_CAC_OVFI GENBL0 +#define GEN_DOC_DOPCI GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_SSIE0_SSIF0 GENBL1 +#define GEN_SSIE1_SSIF1 GENBL1 +#define GEN_S12AD_S12CMPAI GENBL1 +#define GEN_S12AD_S12CMPBI GENBL1 +#define GEN_S12AD1_S12CMPAI1 GENBL1 +#define GEN_S12AD1_S12CMPBI1 GENBL1 +#define GEN_RIIC1_TEI1 GENBL1 +#define GEN_RIIC1_EEI1 GENBL1 +#define GEN_POEG_POEGGAI GENBL2 +#define GEN_POEG_POEGGBI GENBL2 +#define GEN_POEG_POEGGCI GENBL2 +#define GEN_POEG_POEGGDI GENBL2 +#define GEN_SCI8_TEI8 GENAL0 +#define GEN_SCI8_ERI8 GENAL0 +#define GEN_SCI9_TEI9 GENAL0 +#define GEN_SCI9_ERI9 GENAL0 +#define GEN_SCI10_TEI10 GENAL0 +#define GEN_SCI10_ERI10 GENAL0 +#define GEN_SCI11_TEI11 GENAL0 +#define GEN_SCI11_ERI11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_RSPI2_SPII2 GENAL0 +#define GEN_RSPI2_SPEI2 GENAL0 +#define GEN_SCI7_TEI7 GENAL0 +#define GEN_SCI7_ERI7 GENAL0 +#define GEN_EPTPC_MINT GENAL1 +#define GEN_PTPEDMAC_PINT GENAL1 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_EDMAC1_EINT1 GENAL1 +#define GEN_GLCDC_VPOS GENAL1 +#define GEN_GLCDC_GR1UF GENAL1 +#define GEN_GLCDC_GR2UF GENAL1 +#define GEN_DRW2D_DRWIRQ GENAL1 + +#define GRP_DPFPU_DPFPUEX GRPIE0 +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_CAN2_ERS2 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRI GRPBL0 +#define GRP_CAC_MENDI GRPBL0 +#define GRP_CAC_OVFI GRPBL0 +#define GRP_DOC_DOPCI GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_SSIE0_SSIF0 GRPBL1 +#define GRP_SSIE1_SSIF1 GRPBL1 +#define GRP_S12AD_S12CMPAI GRPBL1 +#define GRP_S12AD_S12CMPBI GRPBL1 +#define GRP_S12AD1_S12CMPAI1 GRPBL1 +#define GRP_S12AD1_S12CMPBI1 GRPBL1 +#define GRP_RIIC1_TEI1 GRPBL1 +#define GRP_RIIC1_EEI1 GRPBL1 +#define GRP_POEG_POEGGAI GRPBL2 +#define GRP_POEG_POEGGBI GRPBL2 +#define GRP_POEG_POEGGCI GRPBL2 +#define GRP_POEG_POEGGDI GRPBL2 +#define GRP_SCI8_TEI8 GRPAL0 +#define GRP_SCI8_ERI8 GRPAL0 +#define GRP_SCI9_TEI9 GRPAL0 +#define GRP_SCI9_ERI9 GRPAL0 +#define GRP_SCI10_TEI10 GRPAL0 +#define GRP_SCI10_ERI10 GRPAL0 +#define GRP_SCI11_TEI11 GRPAL0 +#define GRP_SCI11_ERI11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_RSPI2_SPII2 GRPAL0 +#define GRP_RSPI2_SPEI2 GRPAL0 +#define GRP_SCI7_TEI7 GRPAL0 +#define GRP_SCI7_ERI7 GRPAL0 +#define GRP_EPTPC_MINT GRPAL1 +#define GRP_PTPEDMAC_PINT GRPAL1 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_EDMAC1_EINT1 GRPAL1 +#define GRP_GLCDC_VPOS GRPAL1 +#define GRP_GLCDC_GR1UF GRPAL1 +#define GRP_GLCDC_GR2UF GRPAL1 +#define GRP_DRW2D_DRWIRQ GRPAL1 + +#define GCR_DPFPU_DPFPUEX GCRIE0 +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 +#define GCR_CAN2_ERS2 GCRBE0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc __sfr __evenaccess *)0x81300) +#define CAC (*(volatile struct st_cac __sfr __evenaccess *)0x8B000) +#define CAN0 (*(volatile struct st_can __sfr __evenaccess *)0x90200) +#define CAN1 (*(volatile struct st_can __sfr __evenaccess *)0x91200) +#define CAN2 (*(volatile struct st_can __sfr __evenaccess *)0x92200) +#define CMT (*(volatile struct st_cmt __sfr __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __sfr __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __sfr __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __sfr __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __sfr __evenaccess *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw __sfr __evenaccess *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw __sfr __evenaccess *)0x94280) +#define CRC (*(volatile struct st_crc __sfr __evenaccess *)0x88280) +#define DA (*(volatile struct st_da __sfr __evenaccess *)0x88040) +#define DMAC (*(volatile struct st_dmac __sfr __evenaccess *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 __sfr __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x820C0) +#define DMAC4 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 __sfr __evenaccess *)0x821C0) +#define DOC (*(volatile struct st_doc __sfr __evenaccess *)0x8B080) +#define DRW2D (*(volatile struct st_drw2d __sfr __evenaccess *)0xE3000) +#define DTC (*(volatile struct st_dtc __sfr __evenaccess *)0x82400) +#define ECCRAM (*(volatile struct st_eccram __sfr __evenaccess *)0x812C0) +#define EDMAC0 (*(volatile struct st_edmac __sfr __evenaccess *)0xC0000) +#define EDMAC1 (*(volatile struct st_edmac __sfr __evenaccess *)0xC0200) +#define ELC (*(volatile struct st_elc __sfr __evenaccess *)0x8B100) +#define EPTPC (*(volatile struct st_eptpc __sfr __evenaccess *)0xC0500) +#define EPTPC0 (*(volatile struct st_eptpc0 __sfr __evenaccess *)0xC4800) +#define EPTPC1 (*(volatile struct st_eptpc0 __sfr __evenaccess *)0xC4C00) +#define ETHERC0 (*(volatile struct st_etherc __sfr __evenaccess *)0xC0100) +#define ETHERC1 (*(volatile struct st_etherc __sfr __evenaccess *)0xC0300) +#define EXDMAC (*(volatile struct st_exdmac __sfr __evenaccess *)0x82A00) +#define EXDMAC0 (*(volatile struct st_exdmac0 __sfr __evenaccess *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 __sfr __evenaccess *)0x82840) +#define FLASH (*(volatile struct st_flash __sfr __evenaccess *)0x81000) +#define GLCDC (*(volatile struct st_glcdc __sfr __evenaccess *)0xE0000) +#define GPTW0 (*(volatile struct st_gptw __sfr __evenaccess *)0xC2000) +#define GPTW1 (*(volatile struct st_gptw __sfr __evenaccess *)0xC2100) +#define GPTW2 (*(volatile struct st_gptw __sfr __evenaccess *)0xC2200) +#define GPTW3 (*(volatile struct st_gptw __sfr __evenaccess *)0xC2300) +#define ICU (*(volatile struct st_icu __sfr __evenaccess *)0x87000) +#define IWDT (*(volatile struct st_iwdt __sfr __evenaccess *)0x88030) +#define MMCIF (*(volatile struct st_mmcif __sfr __evenaccess *)0x88500) +#define MPC (*(volatile struct st_mpc __sfr __evenaccess *)0x8C100) +#define MPU (*(volatile struct st_mpu __sfr __evenaccess *)0x86400) +#define MTU (*(volatile struct st_mtu __sfr __evenaccess *)0xC120A) +#define MTU0 (*(volatile struct st_mtu0 __sfr __evenaccess *)0xC1290) +#define MTU1 (*(volatile struct st_mtu1 __sfr __evenaccess *)0xC1290) +#define MTU2 (*(volatile struct st_mtu2 __sfr __evenaccess *)0xC1292) +#define MTU3 (*(volatile struct st_mtu3 __sfr __evenaccess *)0xC1200) +#define MTU4 (*(volatile struct st_mtu4 __sfr __evenaccess *)0xC1200) +#define MTU5 (*(volatile struct st_mtu5 __sfr __evenaccess *)0xC1A94) +#define MTU6 (*(volatile struct st_mtu6 __sfr __evenaccess *)0xC1A00) +#define MTU7 (*(volatile struct st_mtu7 __sfr __evenaccess *)0xC1A00) +#define MTU8 (*(volatile struct st_mtu8 __sfr __evenaccess *)0xC1298) +#define OFSM (*(volatile struct st_ofsm __sfr __evenaccess *)0xFE7F5D00) +#define PDC (*(volatile struct st_pdc __sfr __evenaccess *)0xA0500) +#define PMGI0 (*(volatile struct st_pmgi __sfr __evenaccess *)0xC5880) +#define PMGI1 (*(volatile struct st_pmgi __sfr __evenaccess *)0xC5890) +#define POE3 (*(volatile struct st_poe __sfr __evenaccess *)0x8C4C0) +#define POEG (*(volatile struct st_poeg __sfr __evenaccess *)0x9E000) +#define PORT0 (*(volatile struct st_port0 __sfr __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __sfr __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __sfr __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __sfr __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __sfr __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __sfr __evenaccess *)0x8C005) +#define PORT6 (*(volatile struct st_port6 __sfr __evenaccess *)0x8C006) +#define PORT7 (*(volatile struct st_port7 __sfr __evenaccess *)0x8C007) +#define PORT8 (*(volatile struct st_port8 __sfr __evenaccess *)0x8C008) +#define PORT9 (*(volatile struct st_port9 __sfr __evenaccess *)0x8C009) +#define PORTA (*(volatile struct st_porta __sfr __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __sfr __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __sfr __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __sfr __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __sfr __evenaccess *)0x8C00E) +#define PORTF (*(volatile struct st_portf __sfr __evenaccess *)0x8C00F) +#define PORTG (*(volatile struct st_portg __sfr __evenaccess *)0x8C010) +#define PORTH (*(volatile struct st_porth __sfr __evenaccess *)0x8C011) +#define PORTJ (*(volatile struct st_portj __sfr __evenaccess *)0x8C012) +#define PORTK (*(volatile struct st_portk __sfr __evenaccess *)0x8C013) +#define PORTL (*(volatile struct st_portl __sfr __evenaccess *)0x8C014) +#define PORTM (*(volatile struct st_portm __sfr __evenaccess *)0x8C015) +#define PORTN (*(volatile struct st_portn __sfr __evenaccess *)0x8C016) +#define PORTQ (*(volatile struct st_portq __sfr __evenaccess *)0x8C017) +#define PPG0 (*(volatile struct st_ppg0 __sfr __evenaccess *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 __sfr __evenaccess *)0x881F0) +#define PTPEDMAC (*(volatile struct st_ptpedmac __sfr __evenaccess *)0xC0400) +#define QSPI (*(volatile struct st_qspi __sfr __evenaccess *)0x89E00) +#define RAM (*(volatile struct st_ram __sfr __evenaccess *)0x81200) +#define RIIC0 (*(volatile struct st_riic __sfr __evenaccess *)0x88300) +#define RIIC1 (*(volatile struct st_riic __sfr __evenaccess *)0x88320) +#define RIIC2 (*(volatile struct st_riic __sfr __evenaccess *)0x88340) +#define RSPI0 (*(volatile struct st_rspi __sfr __evenaccess *)0xD0100) +#define RSPI1 (*(volatile struct st_rspi __sfr __evenaccess *)0xD0140) +#define RSPI2 (*(volatile struct st_rspi __sfr __evenaccess *)0xD0300) +#define RTC (*(volatile struct st_rtc __sfr __evenaccess *)0x8C400) +#define S12AD (*(volatile struct st_s12ad __sfr __evenaccess *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 __sfr __evenaccess *)0x89100) +#define SCI0 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A040) +#define SCI3 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A060) +#define SCI4 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A080) +#define SCI5 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __sfr __evenaccess *)0x8A0C0) +#define SCI7 (*(volatile struct st_sci7 __sfr __evenaccess *)0xD00E0) +#define SCI8 (*(volatile struct st_sci7 __sfr __evenaccess *)0xD0000) +#define SCI9 (*(volatile struct st_sci7 __sfr __evenaccess *)0xD0020) +#define SCI10 (*(volatile struct st_sci7 __sfr __evenaccess *)0xD0040) +#define SCI11 (*(volatile struct st_sci7 __sfr __evenaccess *)0xD0060) +#define SCI12 (*(volatile struct st_sci12 __sfr __evenaccess *)0x8B300) +#define SDHI (*(volatile struct st_sdhi __sfr __evenaccess *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci __sfr __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci __sfr __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci __sfr __evenaccess *)0x8A040) +#define SMCI3 (*(volatile struct st_smci __sfr __evenaccess *)0x8A060) +#define SMCI4 (*(volatile struct st_smci __sfr __evenaccess *)0x8A080) +#define SMCI5 (*(volatile struct st_smci __sfr __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci __sfr __evenaccess *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci __sfr __evenaccess *)0xD00E0) +#define SMCI8 (*(volatile struct st_smci __sfr __evenaccess *)0xD0000) +#define SMCI9 (*(volatile struct st_smci __sfr __evenaccess *)0xD0020) +#define SMCI10 (*(volatile struct st_smci __sfr __evenaccess *)0xD0040) +#define SMCI11 (*(volatile struct st_smci __sfr __evenaccess *)0xD0060) +#define SMCI12 (*(volatile struct st_smci __sfr __evenaccess *)0x8B300) +#define SSIE0 (*(volatile struct st_ssie __sfr __evenaccess *)0x8A500) +#define SSIE1 (*(volatile struct st_ssie __sfr __evenaccess *)0x8A540) +#define SYSTEM (*(volatile struct st_system __sfr __evenaccess *)0x80000) +#define TEMPS (*(volatile struct st_temps __sfr __evenaccess *)0x8C500) +#define TMR0 (*(volatile struct st_tmr0 __sfr __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __sfr __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __sfr __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __sfr __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __sfr __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __sfr __evenaccess *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 __sfr __evenaccess *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 __sfr __evenaccess *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 __sfr __evenaccess *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 __sfr __evenaccess *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 __sfr __evenaccess *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 __sfr __evenaccess *)0x8810C) +#define TPUA (*(volatile struct st_tpua __sfr __evenaccess *)0x88100) +#define USB (*(volatile struct st_usb __sfr __evenaccess *)0xA0400) +#define USB0 (*(volatile struct st_usb0 __sfr __evenaccess *)0xA0000) +#define WDT (*(volatile struct st_wdt __sfr __evenaccess *)0x88020) +#define FLASHCONST (*(volatile struct st_flashconst __sfr __evenaccess *)0xFE7F7D90) +#define TEMPSCONST (*(volatile struct st_tempsconst __sfr __evenaccess *)0xFE7F7D7C) + +typedef enum enum_ir { +IR_BSC_BUSERR=16,IR_ICU_GROUPIE0=17, +IR_RAM_RAMERR, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT2=26,IR_ICU_SWINT, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMTW0_CMWI0, +IR_CMTW1_CMWI1, +IR_USB0_D0FIFO0=34,IR_USB0_D1FIFO0, +IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0, +IR_RSPI1_SPRI1,IR_RSPI1_SPTI1, +IR_QSPI_SPRI,IR_QSPI_SPTI, +IR_SDHI_SBFAI, +IR_MMCIF_MBFAI, +IR_SSIE0_SSITXI0,IR_SSIE0_SSIRXI0, +IR_SSIE1_SSIRTI1, +IR_RIIC1_RXI1=50,IR_RIIC1_TXI1, +IR_RIIC0_RXI0,IR_RIIC0_TXI0, +IR_RIIC2_RXI2,IR_RIIC2_TXI2, +IR_SCI0_RXI0=58,IR_SCI0_TXI0, +IR_SCI1_RXI1,IR_SCI1_TXI1, +IR_SCI2_RXI2,IR_SCI2_TXI2, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_SCI3_RXI3,IR_SCI3_TXI3, +IR_SCI4_RXI4,IR_SCI4_TXI4, +IR_SCI5_RXI5,IR_SCI5_TXI5, +IR_SCI6_RXI6,IR_SCI6_TXI6, +IR_LVD1_LVD1, +IR_LVD2_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_IWDT_IWUNI=95, +IR_WDT_WUNI, +IR_PDC_PCDFI, +IR_SCI7_RXI7,IR_SCI7_TXI7, +IR_SCI8_RXI8,IR_SCI8_TXI8, +IR_SCI9_RXI9,IR_SCI9_TXI9, +IR_SCI10_RXI10,IR_SCI10_TXI10, +IR_ICU_GROUPBE0,IR_ICU_GROUPBL2, +IR_RSPI2_SPRI2,IR_RSPI2_SPTI2, +IR_ICU_GROUPBL0,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1, +IR_SCI11_RXI11,IR_SCI11_TXI11, +IR_SCI12_RXI12,IR_SCI12_TXI12, +IR_DMAC_DMAC0I=120,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I, +IR_OST_OSTDI, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_PERIB_INTB128,IR_PERIB_INTB129,IR_PERIB_INTB130,IR_PERIB_INTB131,IR_PERIB_INTB132, +IR_PERIB_INTB133,IR_PERIB_INTB134,IR_PERIB_INTB135,IR_PERIB_INTB136,IR_PERIB_INTB137, +IR_PERIB_INTB138,IR_PERIB_INTB139,IR_PERIB_INTB140,IR_PERIB_INTB141,IR_PERIB_INTB142, +IR_PERIB_INTB143,IR_PERIB_INTB144,IR_PERIB_INTB145,IR_PERIB_INTB146,IR_PERIB_INTB147, +IR_PERIB_INTB148,IR_PERIB_INTB149,IR_PERIB_INTB150,IR_PERIB_INTB151,IR_PERIB_INTB152, +IR_PERIB_INTB153,IR_PERIB_INTB154,IR_PERIB_INTB155,IR_PERIB_INTB156,IR_PERIB_INTB157, +IR_PERIB_INTB158,IR_PERIB_INTB159,IR_PERIB_INTB160,IR_PERIB_INTB161,IR_PERIB_INTB162, +IR_PERIB_INTB163,IR_PERIB_INTB164,IR_PERIB_INTB165,IR_PERIB_INTB166,IR_PERIB_INTB167, +IR_PERIB_INTB168,IR_PERIB_INTB169,IR_PERIB_INTB170,IR_PERIB_INTB171,IR_PERIB_INTB172, +IR_PERIB_INTB173,IR_PERIB_INTB174,IR_PERIB_INTB175,IR_PERIB_INTB176,IR_PERIB_INTB177, +IR_PERIB_INTB178,IR_PERIB_INTB179,IR_PERIB_INTB180,IR_PERIB_INTB181,IR_PERIB_INTB182, +IR_PERIB_INTB183,IR_PERIB_INTB184,IR_PERIB_INTB185,IR_PERIB_INTB186,IR_PERIB_INTB187, +IR_PERIB_INTB188,IR_PERIB_INTB189,IR_PERIB_INTB190,IR_PERIB_INTB191,IR_PERIB_INTB192, +IR_PERIB_INTB193,IR_PERIB_INTB194,IR_PERIB_INTB195,IR_PERIB_INTB196,IR_PERIB_INTB197, +IR_PERIB_INTB198,IR_PERIB_INTB199,IR_PERIB_INTB200,IR_PERIB_INTB201,IR_PERIB_INTB202, +IR_PERIB_INTB203,IR_PERIB_INTB204,IR_PERIB_INTB205,IR_PERIB_INTB206,IR_PERIB_INTB207, +IR_PERIA_INTA208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212, +IR_PERIA_INTA213,IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217, +IR_PERIA_INTA218,IR_PERIA_INTA219,IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222, +IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225,IR_PERIA_INTA226,IR_PERIA_INTA227, +IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231,IR_PERIA_INTA232, +IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237, +IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242, +IR_PERIA_INTA243,IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247, +IR_PERIA_INTA248,IR_PERIA_INTA249,IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252, +IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255 +} enum_ir_t; + +typedef enum enum_dtce { +DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USB0_D0FIFO0=34,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSIE0_SSITXI0,DTCE_SSIE0_SSIRXI0, +DTCE_SSIE1_SSIRTI1, +DTCE_RIIC1_RXI1=50,DTCE_RIIC1_TXI1, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0=58,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI=97, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10,DTCE_SCI10_TXI10, +DTCE_RSPI2_SPRI2=108,DTCE_RSPI2_SPTI2, +DTCE_SCI11_RXI11=114,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I=120,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I=126,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +} enum_dtce_t; + +typedef enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_ICU_GROUPIE0=0x02, +IER_RAM_RAMERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMTW0_CMWI0=0x03, +IER_CMTW1_CMWI1=0x03, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04, +IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05, +IER_QSPI_SPRI=0x05,IER_QSPI_SPTI=0x05, +IER_SDHI_SBFAI=0x05, +IER_MMCIF_MBFAI=0x05, +IER_SSIE0_SSITXI0=0x05,IER_SSIE0_SSIRXI0=0x05, +IER_SSIE1_SSIRTI1=0x06, +IER_RIIC1_RXI1=0x06,IER_RIIC1_TXI1=0x06, +IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06, +IER_RIIC2_RXI2=0x06,IER_RIIC2_TXI2=0x06, +IER_SCI0_RXI0=0x07,IER_SCI0_TXI0=0x07, +IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07, +IER_SCI2_RXI2=0x07,IER_SCI2_TXI2=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_SCI3_RXI3=0x0A,IER_SCI3_TXI3=0x0A, +IER_SCI4_RXI4=0x0A,IER_SCI4_TXI4=0x0A, +IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A, +IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A, +IER_LVD1_LVD1=0x0B, +IER_LVD2_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_IWDT_IWUNI=0x0B, +IER_WDT_WUNI=0x0C, +IER_PDC_PCDFI=0x0C, +IER_SCI7_RXI7=0x0C,IER_SCI7_TXI7=0x0C, +IER_SCI8_RXI8=0x0C,IER_SCI8_TXI8=0x0C, +IER_SCI9_RXI9=0x0C,IER_SCI9_TXI9=0x0C, +IER_SCI10_RXI10=0x0D,IER_SCI10_TXI10=0x0D, +IER_ICU_GROUPBE0=0x0D,IER_ICU_GROUPBL2=0x0D, +IER_RSPI2_SPRI2=0x0D,IER_RSPI2_SPTI2=0x0D, +IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E, +IER_SCI11_RXI11=0x0E,IER_SCI11_TXI11=0x0E, +IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E, +IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F, +IER_OST_OSTDI=0x0F, +IER_EXDMAC_EXDMAC0I=0x0F,IER_EXDMAC_EXDMAC1I=0x0F, +IER_PERIB_INTB128=0x10,IER_PERIB_INTB129=0x10,IER_PERIB_INTB130=0x10,IER_PERIB_INTB131=0x10,IER_PERIB_INTB132=0x10, +IER_PERIB_INTB133=0x10,IER_PERIB_INTB134=0x10,IER_PERIB_INTB135=0x10,IER_PERIB_INTB136=0x11,IER_PERIB_INTB137=0x11, +IER_PERIB_INTB138=0x11,IER_PERIB_INTB139=0x11,IER_PERIB_INTB140=0x11,IER_PERIB_INTB141=0x11,IER_PERIB_INTB142=0x11, +IER_PERIB_INTB143=0x11,IER_PERIB_INTB144=0x12,IER_PERIB_INTB145=0x12,IER_PERIB_INTB146=0x12,IER_PERIB_INTB147=0x12, +IER_PERIB_INTB148=0x12,IER_PERIB_INTB149=0x12,IER_PERIB_INTB150=0x12,IER_PERIB_INTB151=0x12,IER_PERIB_INTB152=0x13, +IER_PERIB_INTB153=0x13,IER_PERIB_INTB154=0x13,IER_PERIB_INTB155=0x13,IER_PERIB_INTB156=0x13,IER_PERIB_INTB157=0x13, +IER_PERIB_INTB158=0x13,IER_PERIB_INTB159=0x13,IER_PERIB_INTB160=0x14,IER_PERIB_INTB161=0x14,IER_PERIB_INTB162=0x14, +IER_PERIB_INTB163=0x14,IER_PERIB_INTB164=0x14,IER_PERIB_INTB165=0x14,IER_PERIB_INTB166=0x14,IER_PERIB_INTB167=0x14, +IER_PERIB_INTB168=0x15,IER_PERIB_INTB169=0x15,IER_PERIB_INTB170=0x15,IER_PERIB_INTB171=0x15,IER_PERIB_INTB172=0x15, +IER_PERIB_INTB173=0x15,IER_PERIB_INTB174=0x15,IER_PERIB_INTB175=0x15,IER_PERIB_INTB176=0x16,IER_PERIB_INTB177=0x16, +IER_PERIB_INTB178=0x16,IER_PERIB_INTB179=0x16,IER_PERIB_INTB180=0x16,IER_PERIB_INTB181=0x16,IER_PERIB_INTB182=0x16, +IER_PERIB_INTB183=0x16,IER_PERIB_INTB184=0x17,IER_PERIB_INTB185=0x17,IER_PERIB_INTB186=0x17,IER_PERIB_INTB187=0x17, +IER_PERIB_INTB188=0x17,IER_PERIB_INTB189=0x17,IER_PERIB_INTB190=0x17,IER_PERIB_INTB191=0x17,IER_PERIB_INTB192=0x18, +IER_PERIB_INTB193=0x18,IER_PERIB_INTB194=0x18,IER_PERIB_INTB195=0x18,IER_PERIB_INTB196=0x18,IER_PERIB_INTB197=0x18, +IER_PERIB_INTB198=0x18,IER_PERIB_INTB199=0x18,IER_PERIB_INTB200=0x19,IER_PERIB_INTB201=0x19,IER_PERIB_INTB202=0x19, +IER_PERIB_INTB203=0x19,IER_PERIB_INTB204=0x19,IER_PERIB_INTB205=0x19,IER_PERIB_INTB206=0x19,IER_PERIB_INTB207=0x19, +IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A, +IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A,IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B, +IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B,IER_PERIA_INTA222=0x1B, +IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C, +IER_PERIA_INTA228=0x1C,IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D, +IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D,IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D, +IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E, +IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E, +IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F,IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F, +IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F +} enum_ier_t; + +typedef enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_ICU_GROUPIE0=0, +IPR_RAM_RAMERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMTW0_CMWI0=6, +IPR_CMTW1_CMWI1=7, +IPR_USB0_D0FIFO0=34,IPR_USB0_D1FIFO0=35, +IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39, +IPR_RSPI1_SPRI1=40,IPR_RSPI1_SPTI1=41, +IPR_QSPI_SPRI=42,IPR_QSPI_SPTI=43, +IPR_SDHI_SBFAI=44, +IPR_MMCIF_MBFAI=45, +IPR_SSIE0_SSITXI0=46,IPR_SSIE0_SSIRXI0=47, +IPR_SSIE1_SSIRTI1=48, +IPR_RIIC1_RXI1=50,IPR_RIIC1_TXI1=51, +IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53, +IPR_RIIC2_RXI2=54,IPR_RIIC2_TXI2=55, +IPR_SCI0_RXI0=58,IPR_SCI0_TXI0=59, +IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61, +IPR_SCI2_RXI2=62,IPR_SCI2_TXI2=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_SCI3_RXI3=80,IPR_SCI3_TXI3=81, +IPR_SCI4_RXI4=82,IPR_SCI4_TXI4=83, +IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85, +IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87, +IPR_LVD1_LVD1=88, +IPR_LVD2_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_IWDT_IWUNI=95, +IPR_WDT_WUNI=96, +IPR_PDC_PCDFI=97, +IPR_SCI7_RXI7=98,IPR_SCI7_TXI7=99, +IPR_SCI8_RXI8=100,IPR_SCI8_TXI8=101, +IPR_SCI9_RXI9=102,IPR_SCI9_TXI9=103, +IPR_SCI10_RXI10=104,IPR_SCI10_TXI10=105, +IPR_ICU_GROUPBE0=106,IPR_ICU_GROUPBL2=107, +IPR_RSPI2_SPRI2=108,IPR_RSPI2_SPTI2=109, +IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113, +IPR_SCI11_RXI11=114,IPR_SCI11_TXI11=115, +IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117, +IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124, +IPR_OST_OSTDI=125, +IPR_EXDMAC_EXDMAC0I=126,IPR_EXDMAC_EXDMAC1I=127, +IPR_PERIB_INTB128=128,IPR_PERIB_INTB129=129,IPR_PERIB_INTB130=130,IPR_PERIB_INTB131=131,IPR_PERIB_INTB132=132, +IPR_PERIB_INTB133=133,IPR_PERIB_INTB134=134,IPR_PERIB_INTB135=135,IPR_PERIB_INTB136=136,IPR_PERIB_INTB137=137, +IPR_PERIB_INTB138=138,IPR_PERIB_INTB139=139,IPR_PERIB_INTB140=140,IPR_PERIB_INTB141=141,IPR_PERIB_INTB142=142, +IPR_PERIB_INTB143=143,IPR_PERIB_INTB144=144,IPR_PERIB_INTB145=145,IPR_PERIB_INTB146=146,IPR_PERIB_INTB147=147, +IPR_PERIB_INTB148=148,IPR_PERIB_INTB149=149,IPR_PERIB_INTB150=150,IPR_PERIB_INTB151=151,IPR_PERIB_INTB152=152, +IPR_PERIB_INTB153=153,IPR_PERIB_INTB154=154,IPR_PERIB_INTB155=155,IPR_PERIB_INTB156=156,IPR_PERIB_INTB157=157, +IPR_PERIB_INTB158=158,IPR_PERIB_INTB159=159,IPR_PERIB_INTB160=160,IPR_PERIB_INTB161=161,IPR_PERIB_INTB162=162, +IPR_PERIB_INTB163=163,IPR_PERIB_INTB164=164,IPR_PERIB_INTB165=165,IPR_PERIB_INTB166=166,IPR_PERIB_INTB167=167, +IPR_PERIB_INTB168=168,IPR_PERIB_INTB169=169,IPR_PERIB_INTB170=170,IPR_PERIB_INTB171=171,IPR_PERIB_INTB172=172, +IPR_PERIB_INTB173=173,IPR_PERIB_INTB174=174,IPR_PERIB_INTB175=175,IPR_PERIB_INTB176=176,IPR_PERIB_INTB177=177, +IPR_PERIB_INTB178=178,IPR_PERIB_INTB179=179,IPR_PERIB_INTB180=180,IPR_PERIB_INTB181=181,IPR_PERIB_INTB182=182, +IPR_PERIB_INTB183=183,IPR_PERIB_INTB184=184,IPR_PERIB_INTB185=185,IPR_PERIB_INTB186=186,IPR_PERIB_INTB187=187, +IPR_PERIB_INTB188=188,IPR_PERIB_INTB189=189,IPR_PERIB_INTB190=190,IPR_PERIB_INTB191=191,IPR_PERIB_INTB192=192, +IPR_PERIB_INTB193=193,IPR_PERIB_INTB194=194,IPR_PERIB_INTB195=195,IPR_PERIB_INTB196=196,IPR_PERIB_INTB197=197, +IPR_PERIB_INTB198=198,IPR_PERIB_INTB199=199,IPR_PERIB_INTB200=200,IPR_PERIB_INTB201=201,IPR_PERIB_INTB202=202, +IPR_PERIB_INTB203=203,IPR_PERIB_INTB204=204,IPR_PERIB_INTB205=205,IPR_PERIB_INTB206=206,IPR_PERIB_INTB207=207, +IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212, +IPR_PERIA_INTA213=213,IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217, +IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219,IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222, +IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225,IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227, +IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231,IPR_PERIA_INTA232=232, +IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237, +IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242, +IPR_PERIA_INTA243=243,IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247, +IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249,IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252, +IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255, +IPR_ICU_SWI=3, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_CMTW0_=6, +IPR_CMTW1_=7, +IPR_SDHI_=44, +IPR_MMCIF_=45, +IPR_SSIE1_=48, +IPR_LVD1_=88, +IPR_LVD2_=89, +IPR_IWDT_=95, +IPR_WDT_=96, +IPR_PDC_=97, +IPR_OST_=125 +} enum_ipr_t; + +#ifdef __IAR_SYSTEMS_ICC__ +#pragma bitfields=reversed +#else +#pragma bit_order left +#endif + +#ifndef __IAR_SYSTEMS_ICC__ +#pragma unpack +#endif + + +typedef struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + unsigned short :3; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short BPEB:2; + unsigned short BPFB:2; + unsigned short BPHB:2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS4WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS5WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS6WCR2; + char wk11[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS7WCR2; + char wk12[1926]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS4CR; + char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS4REC; + char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS5CR; + char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS5REC; + char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS6CR; + char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS6REC; + char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS7CR; + char wk27[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS7REC; + char wk28[4]; + union { + unsigned short WORD; + struct { + unsigned short RCVENM7:1; + unsigned short RCVENM6:1; + unsigned short RCVENM5:1; + unsigned short RCVENM4:1; + unsigned short RCVENM3:1; + unsigned short RCVENM2:1; + unsigned short RCVENM1:1; + unsigned short RCVENM0:1; + unsigned short RCVEN7:1; + unsigned short RCVEN6:1; + unsigned short RCVEN5:1; + unsigned short RCVEN4:1; + unsigned short RCVEN3:1; + unsigned short RCVEN2:1; + unsigned short RCVEN1:1; + unsigned short RCVEN0:1; + } BIT; + } CSRECEN; + char wk29[894]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BSIZE:2; + unsigned char :3; + unsigned char EXENB:1; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EMODE:1; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BE:1; + } BIT; + } SDAMOD; + char wk30[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SFEN:1; + } BIT; + } SDSELF; + char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short REFW:4; + unsigned short RFC:12; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RFEN:1; + } BIT; + } SDRFEN; + char wk32[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char INIRQ:1; + } BIT; + } SDICR; + char wk33[3]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short PRC:3; + unsigned short ARFC:4; + unsigned short ARFI:4; + } BIT; + } SDIR; + char wk34[26]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MXC:2; + } BIT; + } SDADR; + char wk35[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RAS:3; + unsigned long :2; + unsigned long RCD:2; + unsigned long RP:3; + unsigned long WR:1; + unsigned long :5; + unsigned long CL:3; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short MR:15; + } BIT; + } SDMOD; + char wk36[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SRFST:1; + unsigned char INIST:1; + unsigned char :2; + unsigned char MRSST:1; + } BIT; + } SDSR; + char wk37[269231]; + union { + unsigned long LONG; + struct { + unsigned long PRERR:1; + unsigned long :12; + unsigned long PR5SEL:3; + unsigned long :1; + unsigned long PR4SEL:3; + unsigned long :1; + unsigned long PR3SEL:3; + unsigned long :1; + unsigned long PR2SEL:3; + unsigned long :1; + unsigned long PR1SEL:3; + } BIT; + } EBMAPCR; +} st_bsc_t; + +typedef struct st_cac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CFME:1; + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + unsigned char EDGES:2; + unsigned char TCSS:2; + unsigned char FMCS:3; + unsigned char CACREFE:1; + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + unsigned char DFS:2; + unsigned char RCDS:2; + unsigned char RSCS:3; + unsigned char RPS:1; + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char OVFFCL:1; + unsigned char MENDFCL:1; + unsigned char FERRFCL:1; + unsigned char :1; + unsigned char OVFIE:1; + unsigned char MENDIE:1; + unsigned char FERRIE:1; + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OVFF:1; + unsigned char MENDF:1; + unsigned char FERRF:1; + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :3; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR1; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MKIVLR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char TRMABT:1; + unsigned char TRMACTIVE:1; + unsigned char SENTDATA:1; + } TX; + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char MSGLOST:1; + unsigned char INVALDATA:1; + unsigned char NEWDATA:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :2; + unsigned char RBOC:1; + unsigned char BOM:2; + unsigned char SLPM:1; + unsigned char CANM:2; + unsigned char TSPS:2; + unsigned char TSRC:1; + unsigned char TPM:1; + unsigned char MLM:1; + unsigned char IDFM:2; + unsigned char MBM:1; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :1; + unsigned char RECST:1; + unsigned char TRMST:1; + unsigned char BOST:1; + unsigned char EPST:1; + unsigned char SLPST:1; + unsigned char HLTST:1; + unsigned char RSTST:1; + unsigned char EST:1; + unsigned char TABST:1; + unsigned char FMLST:1; + unsigned char NMLST:1; + unsigned char TFST:1; + unsigned char RFST:1; + unsigned char SDST:1; + unsigned char NDST:1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long TSEG1:4; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long SJW:2; + unsigned long :1; + unsigned long TSEG2:3; + unsigned long :7; + unsigned long CCLKS:1; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEST:1; + unsigned char RFWST:1; + unsigned char RFFST:1; + unsigned char RFMLF:1; + unsigned char RFUST:3; + unsigned char RFE:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFEST:1; + unsigned char TFFST:1; + unsigned char :2; + unsigned char TFUST:3; + unsigned char TFE:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BLIE:1; + unsigned char OLIE:1; + unsigned char ORIE:1; + unsigned char BORIE:1; + unsigned char BOEIE:1; + unsigned char EPIE:1; + unsigned char EWIE:1; + unsigned char BEIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BLIF:1; + unsigned char OLIF:1; + unsigned char ORIF:1; + unsigned char BORIF:1; + unsigned char BOEIF:1; + unsigned char EPIF:1; + unsigned char EWIF:1; + unsigned char BEIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char EDPM:1; + unsigned char ADEF:1; + unsigned char BE0F:1; + unsigned char BE1F:1; + unsigned char CEF:1; + unsigned char AEF:1; + unsigned char FEF:1; + unsigned char SEF:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char SEST:1; + unsigned char :2; + unsigned char MBNST:5; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MBSM:2; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TSTM:2; + unsigned char TSTE:1; + } BIT; + } TCR; +} st_can_t; + +typedef struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +} st_cmt_t; + +typedef struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_cmtw { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short STR:1; + } BIT; + } CMWSTR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short CCLR:3; + unsigned short :3; + unsigned short CMS:1; + unsigned short :1; + unsigned short OC1IE:1; + unsigned short OC0IE:1; + unsigned short IC1IE:1; + unsigned short IC0IE:1; + unsigned short CMWIE:1; + unsigned short :1; + unsigned short CKS:2; + } BIT; + } CMWCR; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short CMWE:1; + unsigned short :1; + unsigned short OC1E:1; + unsigned short OC0E:1; + unsigned short OC1:2; + unsigned short OC0:2; + unsigned short :2; + unsigned short IC1E:1; + unsigned short IC0E:1; + unsigned short IC1:2; + unsigned short IC0:2; + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +} st_cmtw_t; + +typedef struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char LMS:1; + unsigned char :3; + unsigned char GPS:3; + } BIT; + } CRCCR; + char wk0[3]; + union { + unsigned long LONG; + unsigned char BYTE; + } CRCDIR; + union { + unsigned long LONG; + unsigned short WORD; + unsigned char BYTE; + } CRCDOR; +} st_crc_t; + +typedef struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char DAE:1; + unsigned char :5; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + unsigned char :7; + } BIT; + } DAADSCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAAMP1:1; + unsigned char DAAMP0:1; + unsigned char :6; + } BIT; + } DAAMPCR; + char wk1[19]; + union { + unsigned char BYTE; + struct { + unsigned char DAASW1:1; + unsigned char DAASW0:1; + unsigned char :6; + } BIT; + } DAASWCR; + char wk2[17763]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char AMADSEL1:1; + unsigned char :1; + } BIT; + } DAADUSR; +} st_da_t; + +typedef struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char DMIS7:1; + unsigned char DMIS6:1; + unsigned char DMIS5:1; + unsigned char DMIS4:1; + unsigned char :4; + } BIT; + } DMIST; +} st_dmac_t; + +typedef struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +} st_dmac0_t; + +typedef struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +} st_dmac1_t; + +typedef struct st_doc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DOPCFCL:1; + unsigned char DOPCF:1; + unsigned char DOPCIE:1; + unsigned char :1; + unsigned char DCSEL:1; + unsigned char OMS:2; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +} st_doc_t; + +typedef struct st_drw2d { + union { + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long SPANSTR:1; + unsigned long SPANABT:1; + unsigned long UNIONCD:1; + unsigned long UNIONAB:1; + unsigned long UNION56:1; + unsigned long UNION34:1; + unsigned long UNION12:1; + unsigned long BAND2EN:1; + unsigned long BAND1EN:1; + unsigned long LIM6TH:1; + unsigned long LIM5TH:1; + unsigned long LIM4TH:1; + unsigned long LIM3TH:1; + unsigned long LIM2TH:1; + unsigned long LIM1TH:1; + unsigned long QUAD3EN:1; + unsigned long QUAD2EN:1; + unsigned long QUAD1EN:1; + unsigned long LIM6EN:1; + unsigned long LIM5EN:1; + unsigned long LIM4EN:1; + unsigned long LIM3EN:1; + unsigned long LIM2EN:1; + unsigned long LIM1EN:1; + } BIT; + } CONTROL; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long DLIR:1; + unsigned long ENUIR:1; + unsigned long DLSTACT:1; + unsigned long CACHEDTY:1; + unsigned long BSYWR:1; + unsigned long BSYENUM:1; + } BIT; + } STATUS; + }; + union { + union { + unsigned long LONG; + struct { + unsigned long RLEPIXW:2; + unsigned long BDIA:1; + unsigned long BSIA:1; + unsigned long CLUTFORM:1; + unsigned long COLKEYEN:1; + unsigned long CLUTEN:1; + unsigned long RLEEN:1; + unsigned long WRALPHA:2; + unsigned long WRFMT:2; + unsigned long RDFMT:2; + unsigned long TEXFILTY:1; + unsigned long TEXFILTX:1; + unsigned long TEXCLPY:1; + unsigned long TEXCLPX:1; + unsigned long BC2:1; + unsigned long BDI:1; + unsigned long BSI:1; + unsigned long BDF:1; + unsigned long BSF:1; + unsigned long WRFMT2:1; + unsigned long BDFA:1; + unsigned long BSFA:1; + unsigned long RDFMT2:2; + unsigned long USEACB:1; + unsigned long PTNSRCL5:1; + unsigned long TEXENA:1; + unsigned long PTNEN:1; + } BIT; + } CONTROL2; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long ACBLD:1; + unsigned long :1; + unsigned long COLKEY:1; + unsigned long TEXCLUT256:1; + unsigned long RLEUNIT:1; + unsigned long :1; + unsigned long TEXCLUT:1; + unsigned long PERFCNT:1; + unsigned long TXCACHE:1; + unsigned long FBCACHE:1; + unsigned long DLR:1; + unsigned long :5; + unsigned long REV:12; + } BIT; + } HWVER; + }; + char wk0[8]; + unsigned long L1START; + unsigned long L2START; + unsigned long L3START; + unsigned long L4START; + unsigned long L5START; + unsigned long L6START; + unsigned long L1XADD; + unsigned long L2XADD; + unsigned long L3XADD; + unsigned long L4XADD; + unsigned long L5XADD; + unsigned long L6XADD; + unsigned long L1YADD; + unsigned long L2YADD; + unsigned long L3YADD; + unsigned long L4YADD; + unsigned long L5YADD; + unsigned long L6YADD; + unsigned long L1BAND; + unsigned long L2BAND; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long COL1A:8; + unsigned long COL1R:8; + unsigned long COL1G:8; + unsigned long COL1B:8; + } BIT; + } COLOR1; + union { + unsigned long LONG; + struct { + unsigned long COL2A:8; + unsigned long COL2R:8; + unsigned long COL2G:8; + unsigned long COL2B:8; + } BIT; + } COLOR2; + char wk2[8]; + unsigned long PATTERN; + union { + unsigned long LONG; + struct { + unsigned long Y:16; + unsigned long X:16; + } BIT; + } SIZE; + union { + unsigned long LONG; + struct { + unsigned long SSD:16; + unsigned long PITCH:16; + } BIT; + } PITCH; + unsigned long ORIGIN; + char wk3[12]; + unsigned long LUST; + unsigned long LUXADD; + unsigned long LUYADD; + unsigned long LVSTI; + unsigned long LVSTF; + unsigned long LVXADDI; + unsigned long LVYADDI; + union { + unsigned long LONG; + struct { + unsigned long LVYADDF:16; + unsigned long LVXADDF:16; + } BIT; + } LVYXADDF; + char wk4[4]; + unsigned long TEXPITCH; + union { + unsigned long LONG; + struct { + unsigned long TEXVMSK:21; + unsigned long TEXUMSK:11; + } BIT; + } TEXMSK; + unsigned long TEXORG; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long DLIRCLR:1; + unsigned long ENUIRCLR:1; + unsigned long DLIREN:1; + unsigned long ENUIREN:1; + } BIT; + } IRQCTL; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CFLUTX:1; + unsigned long CENTX:1; + unsigned long CFLUFX:1; + unsigned long CENFX:1; + } BIT; + } CACHECTL; + unsigned long DLISTST; + unsigned long PERFCNT1; + unsigned long PERFCNT2; + union { + unsigned long LONG; + struct { + unsigned long TRG2:16; + unsigned long TRG1:16; + } BIT; + } PERFTRG; + char wk5[4]; + unsigned long TEXCLADDR; + unsigned long TEXCLDATA; + unsigned long TEXCLOFST; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } COLKEY; +} st_drw2d_t; + +typedef struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + unsigned char :4; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; + void *DTCIBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SQTFRL:1; + } BIT; + } DTCOR; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ESPSEL:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSQE; + unsigned long DTCDISP; +} st_dtc_t; + +typedef struct st_eccram { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RAMMOD:2; + } BIT; + } ECCRAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC2ERR:1; + } BIT; + } ECCRAM2STS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC1STSEN:1; + } BIT; + } ECCRAM1STSEN; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC1ERR:1; + } BIT; + } ECCRAM1STS; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char PRCR:1; + } BIT; + } ECCRAMPRCR; + char wk0[3]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ECC2EAD:12; + unsigned long :3; + } BIT; + } ECCRAM2ECAD; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ECC1EAD:12; + unsigned long :3; + } BIT; + } ECCRAM1ECAD; + union { + unsigned char BYTE; + struct { + unsigned char KW2:7; + unsigned char PRCR2:1; + } BIT; + } ECCRAMPRCR2; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TSTBYP:1; + } BIT; + } ECCRAMETST; +} st_eccram_t; + +typedef struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long RABT:1; + unsigned long RFCOF:1; + unsigned long :1; + unsigned long ECI:1; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :4; + unsigned long CND:1; + unsigned long DLC:1; + unsigned long CD:1; + unsigned long TRO:1; + unsigned long RMAF:1; + unsigned long :2; + unsigned long RRF:1; + unsigned long RTLF:1; + unsigned long RTSF:1; + unsigned long PRE:1; + unsigned long CERF:1; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long RABTIP:1; + unsigned long RFCOFIP:1; + unsigned long :1; + unsigned long ECIIP:1; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :4; + unsigned long CNDIP:1; + unsigned long DLCIP:1; + unsigned long CDIP:1; + unsigned long TROIP:1; + unsigned long RMAFIP:1; + unsigned long :2; + unsigned long RRFIP:1; + unsigned long RTLFIP:1; + unsigned long RTSFIP:1; + unsigned long PREIP:1; + unsigned long CERFIP:1; + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RMAFCE:1; + unsigned long :2; + unsigned long RRFCE:1; + unsigned long :4; + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RNR:1; + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long ELB:1; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_edmac_t; + +typedef struct st_elc { + union { + unsigned char BYTE; + struct { + unsigned char ELCON:1; + unsigned char :7; + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR0; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR7; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR10; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR11; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR12; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR13; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR16; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR18; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR19; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR20; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR21; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR22; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR23; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR25; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR26; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR27; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR28; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char MTU3MD:2; + unsigned char :4; + unsigned char MTU0MD:2; + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTU4MD:2; + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CMT1MD:2; + unsigned char :2; + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + unsigned char TMR3MD:2; + unsigned char TMR2MD:2; + unsigned char TMR1MD:2; + unsigned char TMR0MD:2; + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL3; + union { + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; + } BIT; +#endif + } ELSEGR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR33; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR35; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR36; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR37; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR38; + char wk8[6]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR45; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char TPU3MD:2; + unsigned char TPU2MD:2; + unsigned char TPU1MD:2; + unsigned char TPU0MD:2; + } BIT; + } ELOPF; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMTW0MD:2; + } BIT; + } ELOPH; + char wk11[4]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR48; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR49; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR50; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR51; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR52; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR53; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR54; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR55; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR56; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR57; +} st_elc_t; + +typedef struct st_eptpc { + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RESET:1; + } BIT; + } PTRSTR; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long SCLKSEL:3; + unsigned long :5; + unsigned long SCLKDIV:3; + } BIT; + } STCSELR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long BYPASS1:1; + unsigned long :15; + unsigned long BYPASS0:1; + } BIT; + } SYBYPSR; + char wk0[15092]; + unsigned long MIESR; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long CYC5:1; + unsigned long CYC4:1; + unsigned long CYC3:1; + unsigned long CYC2:1; + unsigned long CYC1:1; + unsigned long CYC0:1; + unsigned long :12; + unsigned long PR:1; + unsigned long SY1:1; + unsigned long SY0:1; + unsigned long ST:1; + } BIT; + } MIEIPR; + char wk1[8]; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + unsigned long PLSP:1; + unsigned long :2; + unsigned long CYCN5:1; + unsigned long CYCN4:1; + unsigned long CYCN3:1; + unsigned long CYCN2:1; + unsigned long CYCN1:1; + unsigned long CYCN0:1; + unsigned long :2; + unsigned long CYCP5:1; + unsigned long CYCP4:1; + unsigned long CYCP3:1; + unsigned long CYCP2:1; + unsigned long CYCP1:1; + unsigned long CYCP0:1; + } BIT; + } ELIPPR; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + unsigned long PLSP:1; + unsigned long :2; + unsigned long CYCN5:1; + unsigned long CYCN4:1; + unsigned long CYCN3:1; + unsigned long CYCN2:1; + unsigned long CYCN1:1; + unsigned long CYCN0:1; + unsigned long :2; + unsigned long CYCP5:1; + unsigned long CYCP4:1; + unsigned long CYCP3:1; + unsigned long CYCP2:1; + unsigned long CYCP1:1; + unsigned long CYCP0:1; + } BIT; + } ELIPACR; + char wk2[40]; + unsigned long STSR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long W10D:1; + unsigned long SYNTOUT:1; + unsigned long :1; + unsigned long SYNCOUT:1; + unsigned long SYNC:1; + } BIT; + } STIPR; + char wk3[8]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long STCF:2; + } BIT; + } STCFR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long ALEN1:1; + unsigned long ALEN0:1; + unsigned long :4; + unsigned long DVTH:4; + unsigned long SYTH:4; + unsigned long W10S:1; + unsigned long :1; + unsigned long CMOD:1; + unsigned long :5; + unsigned long WINT:8; + } BIT; + } STMR; + unsigned long SYNTOR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long IPTSEL5:1; + unsigned long IPTSEL4:1; + unsigned long IPTSEL3:1; + unsigned long IPTSEL2:1; + unsigned long IPTSEL1:1; + unsigned long IPTSEL0:1; + } BIT; + } IPTSELR; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long MINTEN5:1; + unsigned long MINTEN4:1; + unsigned long MINTEN3:1; + unsigned long MINTEN2:1; + unsigned long MINTEN1:1; + unsigned long MINTEN0:1; + } BIT; + } MITSELR; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long ELTDIS5:1; + unsigned long ELTDIS4:1; + unsigned long ELTDIS3:1; + unsigned long ELTDIS2:1; + unsigned long ELTDIS1:1; + unsigned long ELTDIS0:1; + } BIT; + } ELTSELR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SYSEL:1; + } BIT; + } STCHSELR; + char wk5[16]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long STR:1; + } BIT; + } SYNSTARTR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LOAD:1; + } BIT; + } LCIVLDR; + char wk6[8]; + unsigned long SYNTDARU; + unsigned long SYNTDARL; + unsigned long SYNTDBRU; + unsigned long SYNTDBRL; + char wk7[16]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long VALU:16; + } BIT; + } LCIVRU; + unsigned long LCIVRM; + unsigned long LCIVRL; + char wk8[104]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long GW10:1; + } BIT; + } GETW10R; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long LMTU:31; + } BIT; + } PLIMITRU; + unsigned long PLIMITRM; + unsigned long PLIMITRL; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long LMTU:31; + } BIT; + } MLIMITRU; + unsigned long MLIMITRM; + unsigned long MLIMITRL; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long INFO:1; + } BIT; + } GETINFOR; + char wk9[44]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CNTU:16; + } BIT; + } LCCVRU; + unsigned long LCCVRM; + unsigned long LCCVRL; + char wk10[148]; + unsigned long PW10VRU; + unsigned long PW10VRM; + unsigned long PW10VRL; + char wk11[180]; + unsigned long MW10RU; + unsigned long MW10RM; + unsigned long MW10RL; + char wk12[36]; + unsigned long TMSTTRU0; + unsigned long TMSTTRL0; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR0; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR0; + unsigned long TMSTTRU1; + unsigned long TMSTTRL1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR1; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR1; + unsigned long TMSTTRU2; + unsigned long TMSTTRL2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR2; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR2; + unsigned long TMSTTRU3; + unsigned long TMSTTRL3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR3; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR3; + unsigned long TMSTTRU4; + unsigned long TMSTTRL4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR4; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR4; + unsigned long TMSTTRU5; + unsigned long TMSTTRL5; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR5; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR5; + char wk13[28]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } TMSTARTR; + char wk14[128]; + unsigned long PRSR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long URE1:1; + unsigned long URE0:1; + unsigned long :19; + unsigned long MACE:1; + unsigned long :4; + unsigned long OVRE3:1; + unsigned long OVRE2:1; + unsigned long OVRE1:1; + unsigned long OVRE0:1; + } BIT; + } PRIPR; + char wk15[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PRMACRU0; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PRMACRL0; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PRMACRU1; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PRMACRL1; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long TDIS:2; + } BIT; + } TRNDISR; + char wk16[12]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long FWD1:1; + unsigned long FWD0:1; + unsigned long :7; + unsigned long MOD:1; + } BIT; + } TRNMR; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long THVAL:11; + } BIT; + } TRNCTTDR; +} st_eptpc_t; + +typedef struct st_eptpc0 { + unsigned long SYSR; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long GENDN:1; + unsigned long RESDN:1; + unsigned long :1; + unsigned long INFABT:1; + unsigned long :1; + unsigned long RECLP:1; + unsigned long :5; + unsigned long DRQOVR:1; + unsigned long INTDEV:1; + unsigned long DRPTO:1; + unsigned long :1; + unsigned long MPDUD:1; + unsigned long INTCHG:1; + unsigned long OFMUD:1; + } BIT; + } SYIPR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } SYMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } SYMACRL; + unsigned long SYLLCCTLR; + unsigned long SYIPADDRR; + char wk1[32]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TRSP:4; + unsigned long VER:4; + } BIT; + } SYSPVRR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long DNUM:8; + } BIT; + } SYDOMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long :1; + unsigned long FLAG8:1; + unsigned long :2; + unsigned long FLAG5:1; + unsigned long FLAG4:1; + unsigned long FLAG3:1; + unsigned long FLAG2:1; + unsigned long FLAG1:1; + unsigned long FLAG0:1; + } BIT; + } ANFR; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long :8; + } BIT; + } SYNFR; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long :10; + } BIT; + } DYRQFR; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long :8; + } BIT; + } DYRPFR; + unsigned long SYCIDRU; + unsigned long SYCIDRL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PNUM:16; + } BIT; + } SYPNUMR; + char wk3[20]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long ANUP:1; + unsigned long STUP:1; + unsigned long BMUP:1; + } BIT; + } SYRVLDR; + char wk4[12]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long PDFUP:3; + unsigned long :1; + unsigned long PDRP:3; + unsigned long :1; + unsigned long PDRQ:3; + unsigned long :1; + unsigned long DRP:3; + unsigned long :1; + unsigned long DRQ:3; + unsigned long :1; + unsigned long FUP:3; + unsigned long :1; + unsigned long SYNC:3; + unsigned long :2; + unsigned long ANCE:2; + } BIT; + } SYRFL1R; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long ILL:2; + unsigned long :22; + unsigned long SIG:2; + unsigned long :2; + unsigned long MAN:2; + } BIT; + } SYRFL2R; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long PDRQ:1; + unsigned long :3; + unsigned long DRQ:1; + unsigned long :3; + unsigned long SYNC:1; + unsigned long :3; + unsigned long ANCE:1; + } BIT; + } SYTRENR; + char wk5[4]; + unsigned long MTCIDU; + unsigned long MTCIDL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PNUM:16; + } BIT; + } MTPID; + char wk6[20]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DREQ:8; + unsigned long SYNC:8; + unsigned long ANCE:8; + } BIT; + } SYTLIR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DRESP:8; + unsigned long SYNC:8; + unsigned long ANCE:8; + } BIT; + } SYRLIR; + unsigned long OFMRU; + unsigned long OFMRL; + unsigned long MPDRU; + unsigned long MPDRL; + char wk7[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long GMPR1:8; + unsigned long :8; + unsigned long GMPR2:8; + } BIT; + } GMPR; + unsigned long GMCQR; + unsigned long GMIDRU; + unsigned long GMIDRL; + union { + unsigned long LONG; + struct { + unsigned long CUTO:16; + unsigned long :8; + unsigned long TSRC:8; + } BIT; + } CUOTSR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long SRMV:16; + } BIT; + } SRR; + char wk8[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PPMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PPMACRL; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PDMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PDMACRL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TYPE:16; + } BIT; + } PETYPER; + char wk9[12]; + unsigned long PPIPR; + unsigned long PDIPR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long EVTO:8; + } BIT; + } PETOSR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long GETO:8; + } BIT; + } PGTOSR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long PRTL:8; + } BIT; + } PPTTLR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long PDTL:8; + } BIT; + } PDTTLR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EVUPT:16; + } BIT; + } PEUDPR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long GEUPT:16; + } BIT; + } PGUDPR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long EXTPRM:1; + unsigned long :13; + unsigned long ENB:1; + unsigned long PRT:1; + unsigned long SEL:1; + } BIT; + } FFLTR; + char wk10[28]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } FMAC0RU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } FMAC0RL; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } FMAC1RU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } FMAC1RL; + char wk11[80]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ASYMU:16; + } BIT; + } DASYMRU; + unsigned long DASYMRL; + union { + unsigned long LONG; + struct { + unsigned long INGP:16; + unsigned long EGP:16; + } BIT; + } TSLATR; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TCMOD:1; + unsigned long :3; + unsigned long FILDIS:1; + unsigned long :3; + unsigned long SBDIS:1; + unsigned long :4; + unsigned long TCYC:8; + } BIT; + } SYCONFR; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long FORM1:1; + unsigned long FORM0:1; + } BIT; + } SYFORMR; + unsigned long RSTOUTR; +} st_eptpc0_t; + +typedef struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TPC:1; + unsigned long ZPF:1; + unsigned long PFR:1; + unsigned long RXF:1; + unsigned long TXF:1; + unsigned long :3; + unsigned long PRCEF:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long RE:1; + unsigned long TE:1; + unsigned long :1; + unsigned long ILB:1; + unsigned long RTM:1; + unsigned long DM:1; + unsigned long PRM:1; + } BIT; + } ECMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long RFL:12; + } BIT; + } RFLR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFR:1; + unsigned long PSRTO:1; + unsigned long :1; + unsigned long LCHNG:1; + unsigned long MPD:1; + unsigned long ICD:1; + } BIT; + } ECSR; + char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFSIPR:1; + unsigned long PSRTOIP:1; + unsigned long :1; + unsigned long LCHNGIP:1; + unsigned long MPDIP:1; + unsigned long ICDIP:1; + } BIT; + } ECSIPR; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long MDI:1; + unsigned long MDO:1; + unsigned long MMD:1; + unsigned long MDC:1; + } BIT; + } PIR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LMON:1; + } BIT; + } PSR; + char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long RMD:20; + } BIT; + } RDMLR; + char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long IPG:5; + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long AP:16; + } BIT; + } APR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MP:16; + } BIT; + } MPR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RPAUSE:8; + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TPAUSE:16; + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TXP:8; + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long BCF:16; + } BIT; + } BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MA:16; + } BIT; + } MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +} st_etherc_t; + +typedef struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +} st_exdmac_t; + +typedef struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char DACKSEL:1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +} st_exdmac0_t; + +typedef struct st_exdmac1 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char DACKSEL:1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +} st_exdmac1_t; + +typedef struct st_flash { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ROMCEN:1; + } BIT; + } ROMCE; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ROMCIV:1; + } BIT; + } ROMCIV; + char wk1[58]; + unsigned long NCRG0; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long NCSZ:17; + unsigned long NC3E:1; + unsigned long NC2E:1; + unsigned long NC1E:1; + unsigned long :1; + } BIT; + } NCRC0; + unsigned long NCRG1; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long NCSZ:17; + unsigned long NC3E:1; + unsigned long NC2E:1; + unsigned long NC1E:1; + unsigned long :1; + } BIT; + } NCRC1; + char wk2[45638]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char FLWE:2; + } BIT; + } FWEPROR; + char wk3[7798185]; + unsigned char EEPFCLK; + char wk4[8143]; + union { + unsigned char BYTE; + struct { + unsigned char CFAE:1; + unsigned char :2; + unsigned char CMDLK:1; + unsigned char DFAE:1; + unsigned char :3; + } BIT; + } FASTAT; + char wk5[3]; + union { + unsigned char BYTE; + struct { + unsigned char CFAEIE:1; + unsigned char :2; + unsigned char CMDLKIE:1; + unsigned char DFAEIE:1; + unsigned char :3; + } BIT; + } FAEINT; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRDYIE:1; + } BIT; + } FRDYIE; + char wk7[23]; + union { + unsigned long LONG; + struct { + unsigned long FSADDR:32; + } BIT; + } FSADDR; + union { + unsigned long LONG; + struct { + unsigned long FEADDR:32; + } BIT; + } FEADDR; + char wk8[72]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ILGCOMERR:1; + unsigned long FESETERR:1; + unsigned long SECERR:1; + unsigned long OTERR:1; + unsigned long :4; + unsigned long FRDY:1; + unsigned long ILGLERR:1; + unsigned long ERSERR:1; + unsigned long PRGERR:1; + unsigned long SUSRDY:1; + unsigned long DBFULL:1; + unsigned long ERSSPD:1; + unsigned long PRGSPD:1; + unsigned long :1; + unsigned long FLWEERR:1; + unsigned long :6; + } BIT; + } FSTATR; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRYC:1; + } BIT; + } FENTRYR; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short SUINIT:1; + } BIT; + } FSUINITR; + char wk10[18]; + union { + unsigned short WORD; + struct { + unsigned short CMDR:8; + unsigned short PCMDR:8; + } BIT; + } FCMDR; + char wk11[46]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCDIR:1; + } BIT; + } FBCCNT; + char wk12[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCST:1; + } BIT; + } FBCSTAT; + char wk13[3]; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long PSADR:17; + } BIT; + } FPSADDR; + union { + unsigned long LONG; + struct { + unsigned long BTFLG:1; + unsigned long :3; + unsigned long FAWE:12; + unsigned long FSPR:1; + unsigned long :3; + unsigned long FAWS:12; + } BIT; + } FAWMON; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ESUSPMD:1; + } BIT; + } FCPSR; + char wk14[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short PCKA:8; + } BIT; + } FPCKAR; + char wk15[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short SAS:2; + } BIT; + } FSUACR; +} st_flash_t; + +typedef struct st_glcdc { + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR1CLUT0[256]; + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR1CLUT1[256]; + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR2CLUT0[256]; + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR2CLUT1[256]; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SWRST:1; + unsigned long :7; + unsigned long VEN:1; + unsigned long :7; + unsigned long EN:1; + } BIT; + } BGEN; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long FV:11; + unsigned long :5; + unsigned long FH:11; + } BIT; + } BGPERI; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long VP:4; + unsigned long :12; + unsigned long HP:4; + } BIT; + } BGSYNC; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long VP:11; + unsigned long :5; + unsigned long VW:11; + } BIT; + } BGVSIZE; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HP:11; + unsigned long :5; + unsigned long HW:11; + } BIT; + } BGHSIZE; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } BGCOLOR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SWRST:1; + unsigned long :7; + unsigned long VEN:1; + unsigned long :7; + unsigned long EN:1; + } BIT; + } BGMON; + char wk0[228]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GR1VEN; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RENB:1; + } BIT; + } GR1FLMRD; + char wk1[4]; + unsigned long GR1FLM2; + union { + unsigned long LONG; + struct { + unsigned long LNOFF:16; + unsigned long :16; + } BIT; + } GR1FLM3; + char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long LNNUM:11; + unsigned long DATANUM:16; + } BIT; + } GR1FLM5; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long FORMAT:3; + unsigned long :28; + } BIT; + } GR1FLM6; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long ARCON:1; + unsigned long :3; + unsigned long ARCDISPON:1; + unsigned long :3; + unsigned long GRCDISPON:1; + unsigned long :2; + unsigned long DISPSEL:2; + } BIT; + } GR1AB1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCVS:11; + unsigned long :5; + unsigned long GRCVW:11; + } BIT; + } GR1AB2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCHS:11; + unsigned long :5; + unsigned long GRCHW:11; + } BIT; + } GR1AB3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCVS:11; + unsigned long :5; + unsigned long ARCVW:11; + } BIT; + } GR1AB4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCHS:11; + unsigned long :5; + unsigned long ARCHW:11; + } BIT; + } GR1AB5; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long ARCCOEF:9; + unsigned long :8; + unsigned long ARCRATE:8; + } BIT; + } GR1AB6; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ARCDEF:8; + unsigned long :15; + unsigned long CKON:1; + } BIT; + } GR1AB7; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long CKKG:8; + unsigned long CKKB:8; + unsigned long CKKR:8; + } BIT; + } GR1AB8; + union { + unsigned long LONG; + struct { + unsigned long CKA:8; + unsigned long CKG:8; + unsigned long CKB:8; + unsigned long CKR:8; + } BIT; + } GR1AB9; + char wk3[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long G:8; + unsigned long B:8; + unsigned long R:8; + } BIT; + } GR1BASE; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SEL:1; + unsigned long :5; + unsigned long LINE:11; + } BIT; + } GR1CLUTINT; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long UFST:1; + unsigned long :15; + unsigned long ARCST:1; + } BIT; + } GR1MON; + char wk4[168]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GR2VEN; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RENB:1; + } BIT; + } GR2FLMRD; + char wk5[4]; + unsigned long GR2FLM2; + union { + unsigned long LONG; + struct { + unsigned long LNOFF:16; + unsigned long :16; + } BIT; + } GR2FLM3; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long LNNUM:11; + unsigned long DATANUM:16; + } BIT; + } GR2FLM5; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long FORMAT:3; + unsigned long :28; + } BIT; + } GR2FLM6; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long ARCON:1; + unsigned long :3; + unsigned long ARCDISPON:1; + unsigned long :3; + unsigned long GRCDISPON:1; + unsigned long :2; + unsigned long DISPSEL:2; + } BIT; + } GR2AB1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCVS:11; + unsigned long :5; + unsigned long GRCVW:11; + } BIT; + } GR2AB2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCHS:11; + unsigned long :5; + unsigned long GRCHW:11; + } BIT; + } GR2AB3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCVS:11; + unsigned long :5; + unsigned long ARCVW:11; + } BIT; + } GR2AB4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCHS:11; + unsigned long :5; + unsigned long ARCHW:11; + } BIT; + } GR2AB5; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long ARCCOEF:9; + unsigned long :8; + unsigned long ARCRATE:8; + } BIT; + } GR2AB6; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ARCDEF:8; + unsigned long :15; + unsigned long CKON:1; + } BIT; + } GR2AB7; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long CKKG:8; + unsigned long CKKB:8; + unsigned long CKKR:8; + } BIT; + } GR2AB8; + union { + unsigned long LONG; + struct { + unsigned long CKA:8; + unsigned long CKG:8; + unsigned long CKB:8; + unsigned long CKR:8; + } BIT; + } GR2AB9; + char wk7[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long G:8; + unsigned long B:8; + unsigned long R:8; + } BIT; + } GR2BASE; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SEL:1; + unsigned long :5; + unsigned long LINE:11; + } BIT; + } GR2CLUTINT; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long UFST:1; + unsigned long :15; + unsigned long ARCST:1; + } BIT; + } GR2MON; + char wk8[168]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GAMGVEN; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long GAMON:1; + } BIT; + } GAMSW; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN00:11; + unsigned long :5; + unsigned long GAIN01:11; + } BIT; + } GAMGLUT1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN02:11; + unsigned long :5; + unsigned long GAIN03:11; + } BIT; + } GAMGLUT2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN04:11; + unsigned long :5; + unsigned long GAIN05:11; + } BIT; + } GAMGLUT3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN06:11; + unsigned long :5; + unsigned long GAIN07:11; + } BIT; + } GAMGLUT4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN08:11; + unsigned long :5; + unsigned long GAIN09:11; + } BIT; + } GAMGLUT5; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN10:11; + unsigned long :5; + unsigned long GAIN11:11; + } BIT; + } GAMGLUT6; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN12:11; + unsigned long :5; + unsigned long GAIN13:11; + } BIT; + } GAMGLUT7; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN14:11; + unsigned long :5; + unsigned long GAIN15:11; + } BIT; + } GAMGLUT8; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH01:10; + unsigned long TH02:10; + unsigned long TH03:10; + } BIT; + } GAMGAREA1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH04:10; + unsigned long TH05:10; + unsigned long TH06:10; + } BIT; + } GAMGAREA2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH07:10; + unsigned long TH08:10; + unsigned long TH09:10; + } BIT; + } GAMGAREA3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH10:10; + unsigned long TH11:10; + unsigned long TH12:10; + } BIT; + } GAMGAREA4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH13:10; + unsigned long TH14:10; + unsigned long TH15:10; + } BIT; + } GAMGAREA5; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GAMBVEN; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN00:11; + unsigned long :5; + unsigned long GAIN01:11; + } BIT; + } GAMBLUT1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN02:11; + unsigned long :5; + unsigned long GAIN03:11; + } BIT; + } GAMBLUT2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN04:11; + unsigned long :5; + unsigned long GAIN05:11; + } BIT; + } GAMBLUT3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN06:11; + unsigned long :5; + unsigned long GAIN07:11; + } BIT; + } GAMBLUT4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN08:11; + unsigned long :5; + unsigned long GAIN09:11; + } BIT; + } GAMBLUT5; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN10:11; + unsigned long :5; + unsigned long GAIN11:11; + } BIT; + } GAMBLUT6; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN12:11; + unsigned long :5; + unsigned long GAIN13:11; + } BIT; + } GAMBLUT7; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN14:11; + unsigned long :5; + unsigned long GAIN15:11; + } BIT; + } GAMBLUT8; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH01:10; + unsigned long TH02:10; + unsigned long TH03:10; + } BIT; + } GAMBAREA1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH04:10; + unsigned long TH05:10; + unsigned long TH06:10; + } BIT; + } GAMBAREA2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH07:10; + unsigned long TH08:10; + unsigned long TH09:10; + } BIT; + } GAMBAREA3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH10:10; + unsigned long TH11:10; + unsigned long TH12:10; + } BIT; + } GAMBAREA4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH13:10; + unsigned long TH14:10; + unsigned long TH15:10; + } BIT; + } GAMBAREA5; + char wk11[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GAMRVEN; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN00:11; + unsigned long :5; + unsigned long GAIN01:11; + } BIT; + } GAMRLUT1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN02:11; + unsigned long :5; + unsigned long GAIN03:11; + } BIT; + } GAMRLUT2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN04:11; + unsigned long :5; + unsigned long GAIN05:11; + } BIT; + } GAMRLUT3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN06:11; + unsigned long :5; + unsigned long GAIN07:11; + } BIT; + } GAMRLUT4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN08:11; + unsigned long :5; + unsigned long GAIN09:11; + } BIT; + } GAMRLUT5; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN10:11; + unsigned long :5; + unsigned long GAIN11:11; + } BIT; + } GAMRLUT6; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN12:11; + unsigned long :5; + unsigned long GAIN13:11; + } BIT; + } GAMRLUT7; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN14:11; + unsigned long :5; + unsigned long GAIN15:11; + } BIT; + } GAMRLUT8; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH01:10; + unsigned long TH02:10; + unsigned long TH03:10; + } BIT; + } GAMRAREA1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH04:10; + unsigned long TH05:10; + unsigned long TH06:10; + } BIT; + } GAMRAREA2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH07:10; + unsigned long TH08:10; + unsigned long TH09:10; + } BIT; + } GAMRAREA3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH10:10; + unsigned long TH11:10; + unsigned long TH12:10; + } BIT; + } GAMRAREA4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH13:10; + unsigned long TH14:10; + unsigned long TH15:10; + } BIT; + } GAMRAREA5; + char wk13[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } OUTVEN; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long ENDIANON:1; + unsigned long :3; + unsigned long SWAPON:1; + unsigned long :10; + unsigned long FORMAT:2; + unsigned long :2; + unsigned long FRQSEL:1; + unsigned long :4; + unsigned long DIRSEL:1; + unsigned long :2; + unsigned long PHASE:2; + } BIT; + } OUTSET; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long BRTG:10; + } BIT; + } BRIGHT1; + union { + unsigned long LONG; + struct { + unsigned long :6; + unsigned long BRTB:10; + unsigned long :6; + unsigned long BRTR:10; + } BIT; + } BRIGHT2; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long CONTG:8; + unsigned long CONTB:8; + unsigned long CONTR:8; + } BIT; + } CONTRAST; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long SEL:2; + unsigned long :2; + unsigned long FORM:2; + unsigned long :2; + unsigned long PA:2; + unsigned long :2; + unsigned long PB:2; + unsigned long :2; + unsigned long PC:2; + unsigned long :2; + unsigned long PD:2; + } BIT; + } PANELDTHA; + char wk14[12]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long FRONTGAM:1; + unsigned long :3; + unsigned long LCDEDG:1; + unsigned long :1; + unsigned long TCON0EDG:1; + unsigned long TCON1EDG:1; + unsigned long TCON2EDG:1; + unsigned long TCON3EDG:1; + unsigned long :3; + } BIT; + } CLKPHASE; + char wk15[28]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HALF:11; + unsigned long :5; + unsigned long OFFSET:11; + } BIT; + } TCONTIM; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long VS:11; + unsigned long :5; + unsigned long VW:11; + } BIT; + } TCONSTVA1; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTVA2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long VS:11; + unsigned long :5; + unsigned long VW:11; + } BIT; + } TCONSTVB1; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTVB2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HS:11; + unsigned long :5; + unsigned long HW:11; + } BIT; + } TCONSTHA1; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long HSSEL:1; + unsigned long :3; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTHA2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HS:11; + unsigned long :5; + unsigned long HW:11; + } BIT; + } TCONSTHB1; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long HSSEL:1; + unsigned long :3; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTHB2; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long INV:1; + } BIT; + } TCONDE; + char wk16[20]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UFDTC:1; + unsigned long GR1UFDTC:1; + unsigned long VPOSDTC:1; + } BIT; + } DTCTEN; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UFINTEN:1; + unsigned long GR1UFINTEN:1; + unsigned long VPOSINTEN:1; + } BIT; + } INTEN; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UFCLR:1; + unsigned long GR1UFCLR:1; + unsigned long VPOSCLR:1; + } BIT; + } STCLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UF:1; + unsigned long GR1UF:1; + unsigned long VPOS:1; + } BIT; + } STMON; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long PIXSEL:1; + unsigned long :3; + unsigned long CLKSEL:1; + unsigned long :1; + unsigned long CLKEN:1; + unsigned long DCDR:6; + } BIT; + } PANELCLK; +} st_glcdc_t; + +typedef struct st_gptw { + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PRKEY:8; + unsigned long :3; + unsigned long CMNWP:1; + unsigned long CLRWP:1; + unsigned long STPWP:1; + unsigned long STRWP:1; + unsigned long WP:1; + } BIT; + } GTWP; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CSTRT3:1; + unsigned long CSTRT2:1; + unsigned long CSTRT1:1; + unsigned long CSTRT0:1; + } BIT; + } GTSTR; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CSTOP3:1; + unsigned long CSTOP2:1; + unsigned long CSTOP1:1; + unsigned long CSTOP0:1; + } BIT; + } GTSTP; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CCLR3:1; + unsigned long CCLR2:1; + unsigned long CCLR1:1; + unsigned long CCLR0:1; + } BIT; + } GTCLR; + union { + unsigned long LONG; + struct { + unsigned long CSTRT:1; + unsigned long :7; + unsigned long SSELCH:1; + unsigned long SSELCG:1; + unsigned long SSELCF:1; + unsigned long SSELCE:1; + unsigned long SSELCD:1; + unsigned long SSELCC:1; + unsigned long SSELCB:1; + unsigned long SSELCA:1; + unsigned long SSCBFAH:1; + unsigned long SSCBFAL:1; + unsigned long SSCBRAH:1; + unsigned long SSCBRAL:1; + unsigned long SSCAFBH:1; + unsigned long SSCAFBL:1; + unsigned long SSCARBH:1; + unsigned long SSCARBL:1; + unsigned long SSGTRGDF:1; + unsigned long SSGTRGDR:1; + unsigned long SSGTRGCF:1; + unsigned long SSGTRGCR:1; + unsigned long SSGTRGBF:1; + unsigned long SSGTRGBR:1; + unsigned long SSGTRGAF:1; + unsigned long SSGTRGAR:1; + } BIT; + } GTSSR; + union { + unsigned long LONG; + struct { + unsigned long CSTOP:1; + unsigned long :7; + unsigned long PSELCH:1; + unsigned long PSELCG:1; + unsigned long PSELCF:1; + unsigned long PSELCE:1; + unsigned long PSELCD:1; + unsigned long PSELCC:1; + unsigned long PSELCB:1; + unsigned long PSELCA:1; + unsigned long PSCBFAH:1; + unsigned long PSCBFAL:1; + unsigned long PSCBRAH:1; + unsigned long PSCBRAL:1; + unsigned long PSCAFBH:1; + unsigned long PSCAFBL:1; + unsigned long PSCARBH:1; + unsigned long PSCARBL:1; + unsigned long PSGTRGDF:1; + unsigned long PSGTRGDR:1; + unsigned long PSGTRGCF:1; + unsigned long PSGTRGCR:1; + unsigned long PSGTRGBF:1; + unsigned long PSGTRGBR:1; + unsigned long PSGTRGAF:1; + unsigned long PSGTRGAR:1; + } BIT; + } GTPSR; + union { + unsigned long LONG; + struct { + unsigned long CCLR:1; + unsigned long :7; + unsigned long CSELCH:1; + unsigned long CSELCG:1; + unsigned long CSELCF:1; + unsigned long CSELCE:1; + unsigned long CSELCD:1; + unsigned long CSELCC:1; + unsigned long CSELCB:1; + unsigned long CSELCA:1; + unsigned long CSCBFAH:1; + unsigned long CSCBFAL:1; + unsigned long CSCBRAH:1; + unsigned long CSCBRAL:1; + unsigned long CSCAFBH:1; + unsigned long CSCAFBL:1; + unsigned long CSCARBH:1; + unsigned long CSCARBL:1; + unsigned long CSGTRGDF:1; + unsigned long CSGTRGDR:1; + unsigned long CSGTRGCF:1; + unsigned long CSGTRGCR:1; + unsigned long CSGTRGBF:1; + unsigned long CSGTRGBR:1; + unsigned long CSGTRGAF:1; + unsigned long CSGTRGAR:1; + } BIT; + } GTCSR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long USELCH:1; + unsigned long USELCG:1; + unsigned long USELCF:1; + unsigned long USELCE:1; + unsigned long USELCD:1; + unsigned long USELCC:1; + unsigned long USELCB:1; + unsigned long USELCA:1; + unsigned long USCBFAH:1; + unsigned long USCBFAL:1; + unsigned long USCBRAH:1; + unsigned long USCBRAL:1; + unsigned long USCAFBH:1; + unsigned long USCAFBL:1; + unsigned long USCARBH:1; + unsigned long USCARBL:1; + unsigned long USGTRGDF:1; + unsigned long USGTRGDR:1; + unsigned long USGTRGCF:1; + unsigned long USGTRGCR:1; + unsigned long USGTRGBF:1; + unsigned long USGTRGBR:1; + unsigned long USGTRGAF:1; + unsigned long USGTRGAR:1; + } BIT; + } GTUPSR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DSELCH:1; + unsigned long DSELCG:1; + unsigned long DSELCF:1; + unsigned long DSELCE:1; + unsigned long DSELCD:1; + unsigned long DSELCC:1; + unsigned long DSELCB:1; + unsigned long DSELCA:1; + unsigned long DSCBFAH:1; + unsigned long DSCBFAL:1; + unsigned long DSCBRAH:1; + unsigned long DSCBRAL:1; + unsigned long DSCAFBH:1; + unsigned long DSCAFBL:1; + unsigned long DSCARBH:1; + unsigned long DSCARBL:1; + unsigned long DSGTRGDF:1; + unsigned long DSGTRGDR:1; + unsigned long DSGTRGCF:1; + unsigned long DSGTRGCR:1; + unsigned long DSGTRGBF:1; + unsigned long DSGTRGBR:1; + unsigned long DSGTRGAF:1; + unsigned long DSGTRGAR:1; + } BIT; + } GTDNSR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ASELCH:1; + unsigned long ASELCG:1; + unsigned long ASELCF:1; + unsigned long ASELCE:1; + unsigned long ASELCD:1; + unsigned long ASELCC:1; + unsigned long ASELCB:1; + unsigned long ASELCA:1; + unsigned long ASCBFAH:1; + unsigned long ASCBFAL:1; + unsigned long ASCBRAH:1; + unsigned long ASCBRAL:1; + unsigned long ASCAFBH:1; + unsigned long ASCAFBL:1; + unsigned long ASCARBH:1; + unsigned long ASCARBL:1; + unsigned long ASGTRGDF:1; + unsigned long ASGTRGDR:1; + unsigned long ASGTRGCF:1; + unsigned long ASGTRGCR:1; + unsigned long ASGTRGBF:1; + unsigned long ASGTRGBR:1; + unsigned long ASGTRGAF:1; + unsigned long ASGTRGAR:1; + } BIT; + } GTICASR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long BSELCH:1; + unsigned long BSELCG:1; + unsigned long BSELCF:1; + unsigned long BSELCE:1; + unsigned long BSELCD:1; + unsigned long BSELCC:1; + unsigned long BSELCB:1; + unsigned long BSELCA:1; + unsigned long BSCBFAH:1; + unsigned long BSCBFAL:1; + unsigned long BSCBRAH:1; + unsigned long BSCBRAL:1; + unsigned long BSCAFBH:1; + unsigned long BSCAFBL:1; + unsigned long BSCARBH:1; + unsigned long BSCARBL:1; + unsigned long BSGTRGDF:1; + unsigned long BSGTRGDR:1; + unsigned long BSGTRGCF:1; + unsigned long BSGTRGCR:1; + unsigned long BSGTRGBF:1; + unsigned long BSGTRGBR:1; + unsigned long BSGTRGAF:1; + unsigned long BSGTRGAR:1; + } BIT; + } GTICBSR; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long TPCS:4; + unsigned long :4; + unsigned long MD:3; + unsigned long :7; + unsigned long ICDS:1; + unsigned long :7; + unsigned long CST:1; + } BIT; + } GTCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long OBDTYR:1; + unsigned long OBDTYF:1; + unsigned long OBDTY:2; + unsigned long :4; + unsigned long OADTYR:1; + unsigned long OADTYF:1; + unsigned long OADTY:2; + unsigned long :14; + unsigned long UDF:1; + unsigned long UD:1; + } BIT; + } GTUDDTYC; + union { + unsigned long LONG; + struct { + unsigned long NFCSB:2; + unsigned long NFBEN:1; + unsigned long :2; + unsigned long OBDF:2; + unsigned long OBE:1; + unsigned long OBHLD:1; + unsigned long OBDFLT:1; + unsigned long :1; + unsigned long GTIOB:5; + unsigned long NFCSA:2; + unsigned long NFAEN:1; + unsigned long :2; + unsigned long OADF:2; + unsigned long OAE:1; + unsigned long OAHLD:1; + unsigned long OADFLT:1; + unsigned long :1; + unsigned long GTIOA:5; + } BIT; + } GTIOR; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long GRPABL:1; + unsigned long GRPABH:1; + unsigned long GRPDTE:1; + unsigned long :2; + unsigned long GRP:2; + unsigned long :4; + unsigned long ADTRBDEN:1; + unsigned long ADTRBUEN:1; + unsigned long ADTRADEN:1; + unsigned long ADTRAUEN:1; + unsigned long :8; + unsigned long GTINTPR:2; + unsigned long GTINTF:1; + unsigned long GTINTE:1; + unsigned long GTINTD:1; + unsigned long GTINTC:1; + unsigned long GTINTB:1; + unsigned long GTINTA:1; + } BIT; + } GTINTAD; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long OABLF:1; + unsigned long OABHF:1; + unsigned long DTEF:1; + unsigned long :3; + unsigned long ODF:1; + unsigned long :4; + unsigned long ADTRBDF:1; + unsigned long ADTRBUF:1; + unsigned long ADTRADF:1; + unsigned long ADTRAUF:1; + unsigned long TUCF:1; + unsigned long :4; + unsigned long ITCNT:3; + unsigned long :8; + } BIT; + } GTST; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long ADTDB:1; + unsigned long ADTTB:2; + unsigned long :1; + unsigned long ADTDA:1; + unsigned long ADTTA:2; + unsigned long :1; + unsigned long CCRSWT:1; + unsigned long PR:2; + unsigned long CCRB:2; + unsigned long CCRA:2; + unsigned long :5; + unsigned long DBRTECB:1; + unsigned long :1; + unsigned long DBRTECA:1; + unsigned long :4; + unsigned long BD:4; + } BIT; + } GTBER; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ADTBL:1; + unsigned long :1; + unsigned long ADTAL:1; + unsigned long :1; + unsigned long IVTT:3; + unsigned long IVTC:2; + unsigned long ITLF:1; + unsigned long ITLE:1; + unsigned long ITLD:1; + unsigned long ITLC:1; + unsigned long ITLB:1; + unsigned long ITLA:1; + } BIT; + } GTITC; + unsigned long GTCNT; + unsigned long GTCCRA; + unsigned long GTCCRB; + unsigned long GTCCRC; + unsigned long GTCCRE; + unsigned long GTCCRD; + unsigned long GTCCRF; + unsigned long GTPR; + unsigned long GTPBR; + unsigned long GTPDBR; + unsigned long GTADTRA; + unsigned long GTADTBRA; + unsigned long GTADTDBRA; + unsigned long GTADTRB; + unsigned long GTADTBRB; + unsigned long GTADTDBRB; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long TDFER:1; + unsigned long :2; + unsigned long TDBDE:1; + unsigned long TDBUE:1; + unsigned long :3; + unsigned long TDE:1; + } BIT; + } GTDTCR; + unsigned long GTDVU; + unsigned long GTDVD; + unsigned long GTDBU; + unsigned long GTDBD; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long SOS:2; + } BIT; + } GTSOS; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SOTR:1; + } BIT; + } GTSOTR; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long ADSMEN1:1; + unsigned long :6; + unsigned long ADSMS1:2; + unsigned long :7; + unsigned long ADSMEN0:1; + unsigned long :6; + unsigned long ADSMS0:2; + } BIT; + } GTADSMR; + union { + unsigned long LONG; + struct { + unsigned long EITCNT2:4; + unsigned long EITCNT2IV:4; + unsigned long EIVTT2:4; + unsigned long :2; + unsigned long EIVTC2:2; + unsigned long EITCNT1:4; + unsigned long :4; + unsigned long EIVTT1:4; + unsigned long :2; + unsigned long EIVTC1:2; + } BIT; + } GTEITC; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long EITLU:3; + unsigned long :1; + unsigned long EITLV:3; + unsigned long :1; + unsigned long EITLF:3; + unsigned long :1; + unsigned long EITLE:3; + unsigned long :1; + unsigned long EITLD:3; + unsigned long :1; + unsigned long EITLC:3; + unsigned long :1; + unsigned long EITLB:3; + unsigned long :1; + unsigned long EITLA:3; + } BIT; + } GTEITLI1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long EADTBL:3; + unsigned long :1; + unsigned long EADTAL:3; + } BIT; + } GTEITLI2; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long EBTLDVD:3; + unsigned long :1; + unsigned long EBTLDVU:3; + unsigned long :1; + unsigned long EBTLADB:3; + unsigned long :1; + unsigned long EBTLADA:3; + unsigned long :5; + unsigned long EBTLPR:3; + unsigned long :1; + unsigned long EBTLCB:3; + unsigned long :1; + unsigned long EBTLCA:3; + } BIT; + } GTEITLB; + char wk0[24]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long SECSEL3:1; + unsigned long SECSEL2:1; + unsigned long SECSEL1:1; + unsigned long SECSEL0:1; + } BIT; + } GTSECSR; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long SBDDD:1; + unsigned long SBDAD:1; + unsigned long SBDPD:1; + unsigned long SBDCD:1; + unsigned long :4; + unsigned long SBDDE:1; + unsigned long SBDAE:1; + unsigned long SBDPE:1; + unsigned long SBDCE:1; + } BIT; + } GTSECR; +} st_gptw_t; + +typedef struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT2:1; + } BIT; + } SWINT2R; + char wk1[14]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + unsigned char :2; + } BIT; + } IRQCR[16]; + char wk11[16]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN15:1; + unsigned char FLTEN14:1; + unsigned char FLTEN13:1; + unsigned char FLTEN12:1; + unsigned char FLTEN11:1; + unsigned char FLTEN10:1; + unsigned char FLTEN9:1; + unsigned char FLTEN8:1; + } BIT; + } IRQFLTE1; + char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL15:2; + unsigned short FCLKSEL14:2; + unsigned short FCLKSEL13:2; + unsigned short FCLKSEL12:2; + unsigned short FCLKSEL11:2; + unsigned short FCLKSEL10:2; + unsigned short FCLKSEL9:2; + unsigned short FCLKSEL8:2; + } BIT; + } IRQFLTC1; + char wk13[84]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char EXNMIST:1; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char WDTST:1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char EXNMIEN:1; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char WDTEN:1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char WDTCLR:1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + unsigned char :3; + } BIT; + } NMICR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DPFPUST:1; + unsigned char RAMST:1; + } BIT; + } EXNMISR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DPFPUEN:1; + unsigned char RAMEN:1; + } BIT; + } EXNMIER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DPFPUCLR:1; + unsigned char :1; + } BIT; + } EXNMICLR; + char wk14[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk15[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; + char wk16[27]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPIE0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENIE0; + union { + unsigned long LONG; + struct { + unsigned long CLR31:1; + unsigned long CLR30:1; + unsigned long CLR29:1; + unsigned long CLR28:1; + unsigned long CLR27:1; + unsigned long CLR26:1; + unsigned long CLR25:1; + unsigned long CLR24:1; + unsigned long CLR23:1; + unsigned long CLR22:1; + unsigned long CLR21:1; + unsigned long CLR20:1; + unsigned long CLR19:1; + unsigned long CLR18:1; + unsigned long CLR17:1; + unsigned long CLR16:1; + unsigned long CLR15:1; + unsigned long CLR14:1; + unsigned long CLR13:1; + unsigned long CLR12:1; + unsigned long CLR11:1; + unsigned long CLR10:1; + unsigned long CLR9:1; + unsigned long CLR8:1; + unsigned long CLR7:1; + unsigned long CLR6:1; + unsigned long CLR5:1; + unsigned long CLR4:1; + unsigned long CLR3:1; + unsigned long CLR2:1; + unsigned long CLR1:1; + unsigned long CLR0:1; + } BIT; + } GCRIE0; + char wk17[68]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBE0; + char wk18[44]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL0; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL1; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL2; + char wk19[4]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBE0; + char wk20[44]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL1; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL2; + char wk21[4]; + union { + unsigned long LONG; + struct { + unsigned long CLR31:1; + unsigned long CLR30:1; + unsigned long CLR29:1; + unsigned long CLR28:1; + unsigned long CLR27:1; + unsigned long CLR26:1; + unsigned long CLR25:1; + unsigned long CLR24:1; + unsigned long CLR23:1; + unsigned long CLR22:1; + unsigned long CLR21:1; + unsigned long CLR20:1; + unsigned long CLR19:1; + unsigned long CLR18:1; + unsigned long CLR17:1; + unsigned long CLR16:1; + unsigned long CLR15:1; + unsigned long CLR14:1; + unsigned long CLR13:1; + unsigned long CLR12:1; + unsigned long CLR11:1; + unsigned long CLR10:1; + unsigned long CLR9:1; + unsigned long CLR8:1; + unsigned long CLR7:1; + unsigned long CLR6:1; + unsigned long CLR5:1; + unsigned long CLR4:1; + unsigned long CLR3:1; + unsigned long CLR2:1; + unsigned long CLR1:1; + unsigned long CLR0:1; + } BIT; + } GCRBE0; + char wk22[124]; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR0; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR1; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR2; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR3; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR4; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR5; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR6; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR7; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR8; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR9; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBRA; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBRB; + char wk23[116]; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR128; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR129; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR130; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR131; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR132; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR133; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR134; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR135; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR136; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR137; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR138; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR139; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR140; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR141; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR142; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR143; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR144; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR145; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR146; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR147; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR148; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR149; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR150; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR151; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR152; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR153; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR154; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR155; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR156; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR157; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR158; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR159; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR160; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR161; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR162; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR163; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR164; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR165; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR166; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR167; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR168; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR169; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR170; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR171; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR172; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR173; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR174; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR175; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR176; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR177; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR178; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR179; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR180; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR181; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR182; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR183; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR184; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR185; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR186; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR187; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR188; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR189; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR190; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR191; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR192; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR193; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR194; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR195; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR196; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR197; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR198; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR199; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR200; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR201; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR202; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR203; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR204; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR205; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR206; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR207; + char wk24[96]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPAL0; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPAL1; + char wk25[56]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENAL0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENAL1; + char wk26[136]; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR0; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR1; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR2; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR3; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR4; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR5; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR6; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR7; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR8; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR9; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIARA; + char wk27[1]; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIARC; + char wk28[195]; + union { + unsigned char BYTE; + } SLIAR208; + union { + unsigned char BYTE; + } SLIAR209; + union { + unsigned char BYTE; + } SLIAR210; + union { + unsigned char BYTE; + } SLIAR211; + union { + unsigned char BYTE; + } SLIAR212; + union { + unsigned char BYTE; + } SLIAR213; + union { + unsigned char BYTE; + } SLIAR214; + union { + unsigned char BYTE; + } SLIAR215; + union { + unsigned char BYTE; + } SLIAR216; + union { + unsigned char BYTE; + } SLIAR217; + union { + unsigned char BYTE; + } SLIAR218; + union { + unsigned char BYTE; + } SLIAR219; + union { + unsigned char BYTE; + } SLIAR220; + union { + unsigned char BYTE; + } SLIAR221; + union { + unsigned char BYTE; + } SLIAR222; + union { + unsigned char BYTE; + } SLIAR223; + union { + unsigned char BYTE; + } SLIAR224; + union { + unsigned char BYTE; + } SLIAR225; + union { + unsigned char BYTE; + } SLIAR226; + union { + unsigned char BYTE; + } SLIAR227; + union { + unsigned char BYTE; + } SLIAR228; + union { + unsigned char BYTE; + } SLIAR229; + union { + unsigned char BYTE; + } SLIAR230; + union { + unsigned char BYTE; + } SLIAR231; + union { + unsigned char BYTE; + } SLIAR232; + union { + unsigned char BYTE; + } SLIAR233; + union { + unsigned char BYTE; + } SLIAR234; + union { + unsigned char BYTE; + } SLIAR235; + union { + unsigned char BYTE; + } SLIAR236; + union { + unsigned char BYTE; + } SLIAR237; + union { + unsigned char BYTE; + } SLIAR238; + union { + unsigned char BYTE; + } SLIAR239; + union { + unsigned char BYTE; + } SLIAR240; + union { + unsigned char BYTE; + } SLIAR241; + union { + unsigned char BYTE; + } SLIAR242; + union { + unsigned char BYTE; + } SLIAR243; + union { + unsigned char BYTE; + } SLIAR244; + union { + unsigned char BYTE; + } SLIAR245; + union { + unsigned char BYTE; + } SLIAR246; + union { + unsigned char BYTE; + } SLIAR247; + union { + unsigned char BYTE; + } SLIAR248; + union { + unsigned char BYTE; + } SLIAR249; + union { + unsigned char BYTE; + } SLIAR250; + union { + unsigned char BYTE; + } SLIAR251; + union { + unsigned char BYTE; + } SLIAR252; + union { + unsigned char BYTE; + } SLIAR253; + union { + unsigned char BYTE; + } SLIAR254; + union { + unsigned char BYTE; + } SLIAR255; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char WPRC:1; + } BIT; + } SLIPRCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SELEXD1:1; + unsigned char SELEXD0:1; + } BIT; + } SELEXDR; +} st_icu_t; + +typedef struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + unsigned char :7; + } BIT; + } IWDTCSTPR; +} st_iwdt_t; + +typedef struct st_mmcif { + union { + unsigned long LONG; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned long :1; + unsigned long BOOT:1; + unsigned long CMD:6; + unsigned long RTYP:2; + unsigned long RBSY:1; + unsigned long :1; + unsigned long WDAT:1; + unsigned long DWEN:1; + unsigned long CMLTE:1; + unsigned long CMD12EN:1; + unsigned long RIDXC:2; + unsigned long RCRC7C:2; + unsigned long :1; + unsigned long CRC16C:1; + unsigned long BOOTACK:1; + unsigned long CRCSTE:1; + unsigned long TBIT:1; + unsigned long OPDM:1; + unsigned long :2; + unsigned long SBIT:1; + unsigned long :1; + unsigned long DATW:2; + } BIT; +#endif + } CECMDSET; + char wk0[4]; + union { + unsigned long LONG; + } CEARG; + union { + unsigned long LONG; + struct { + unsigned long C12ARG:32; + } BIT; + } CEARGCMD12; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long BREAK:1; + } BIT; + } CECMDCTRL; + union { + unsigned long LONG; + struct { + unsigned long BLKCNT:16; + unsigned long BLKSIZ:16; + } BIT; + } CEBLOCKSET; + union { + unsigned long LONG; + struct { + unsigned long MMCBUSBSY:1; + unsigned long :6; + unsigned long CLKEN:1; + unsigned long :4; + unsigned long CLKDIV:4; + unsigned long :2; + unsigned long SRSPTO:2; + unsigned long SRBSYTO:4; + unsigned long SRWDTO:4; + unsigned long :4; + } BIT; + } CECLKCTRL; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long DMATYP:1; + unsigned long DMAWEN:1; + unsigned long DMAREN:1; + unsigned long :7; + unsigned long ATYP:1; + unsigned long :16; + } BIT; + } CEBUFACC; + unsigned long CERESP3; + unsigned long CERESP2; + unsigned long CERESP1; + unsigned long CERESP0; + union { + unsigned long LONG; + struct { + unsigned long RSP12:32; + } BIT; + } CERESPCMD12; + unsigned long CEDATA; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long SBTCLKDIV:4; + unsigned long SBTACKTO:4; + unsigned long SFSTBTDATTO:4; + unsigned long SBTDATTO:4; + unsigned long :16; + } BIT; + } CEBOOT; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long CMD12DRE:1; + unsigned long CMD12RBE:1; + unsigned long CMD12CRE:1; + unsigned long DTRANE:1; + unsigned long BUFRE:1; + unsigned long BUFWEN:1; + unsigned long BUFREN:1; + unsigned long :2; + unsigned long RBSYE:1; + unsigned long CRSPE:1; + unsigned long CMDVIO:1; + unsigned long BUFVIO:1; + unsigned long :2; + unsigned long WDATERR:1; + unsigned long RDATERR:1; + unsigned long RIDXERR:1; + unsigned long RSPERR:1; + unsigned long :3; + unsigned long CRCSTO:1; + unsigned long WDATTO:1; + unsigned long RDATTO:1; + unsigned long RBSYTO:1; + unsigned long RSPTO:1; + } BIT; + } CEINT; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long MCMD12DRE:1; + unsigned long MCMD12RBE:1; + unsigned long MCMD12CRE:1; + unsigned long MDTRANE:1; + unsigned long MBUFRE:1; + unsigned long MBUFWEN:1; + unsigned long MBUFREN:1; + unsigned long :2; + unsigned long MRBSYE:1; + unsigned long MCRSPE:1; + unsigned long MCMDVIO:1; + unsigned long MBUFVIO:1; + unsigned long :2; + unsigned long MWDATERR:1; + unsigned long MRDATERR:1; + unsigned long MRIDXERR:1; + unsigned long MRSPERR:1; + unsigned long :3; + unsigned long MCRCSTO:1; + unsigned long MWDATTO:1; + unsigned long MRDATTO:1; + unsigned long MRBSYTO:1; + unsigned long MRSPTO:1; + } BIT; + } CEINTEN; + union { + unsigned long LONG; + struct { + unsigned long CMDSEQ:1; + unsigned long CMDSIG:1; + unsigned long RSPIDX:6; + unsigned long DATSIG:8; + unsigned long RCVBLK:16; + } BIT; + } CEHOSTSTS1; + union { + unsigned long LONG; + struct { + unsigned long CRCSTE:1; + unsigned long CRC16E:1; + unsigned long AC12CRCE:1; + unsigned long RSPCRC7E:1; + unsigned long CRCSTEBE:1; + unsigned long RDATEBE:1; + unsigned long AC12REBE:1; + unsigned long RSPEBE:1; + unsigned long AC12IDXE:1; + unsigned long RSPIDXE:1; + unsigned long BTACKPATE:1; + unsigned long BTACKEBE:1; + unsigned long :1; + unsigned long CRCST:3; + unsigned long :1; + unsigned long STRDATTO:1; + unsigned long DATBSYTO:1; + unsigned long CRCSTTO:1; + unsigned long AC12BSYTO:1; + unsigned long RSPBSYTO:1; + unsigned long AC12RSPTO:1; + unsigned long STRSPTO:1; + unsigned long BTACKTO:1; + unsigned long FSTBTDATTO:1; + unsigned long BTDATTO:1; + unsigned long :5; + } BIT; + } CEHOSTSTS2; + char wk2[32]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CDSIG:1; + unsigned long CDRISE:1; + unsigned long CDFALL:1; + unsigned long :6; + unsigned long MCDRISE:1; + unsigned long MCDFALL:1; + unsigned long :4; + } BIT; + } CEDETECT; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long RESNOUT:1; + unsigned long :1; + unsigned long CLKMAIN:1; + unsigned long :19; + } BIT; + } CEADDMODE; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long SWRST:1; + unsigned long :15; + unsigned long VERSION:16; + } BIT; + } CEVERSION; +} st_mmcif_t; + +typedef struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PFCSE; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CS3S:2; + unsigned char CS2S:2; + unsigned char CS1S:2; + unsigned char :1; + unsigned char CS0S:1; + } BIT; + } PFCSS0; + union { + unsigned char BYTE; + struct { + unsigned char CS7S:2; + unsigned char CS6S:2; + unsigned char CS5S:2; + unsigned char CS4S:2; + } BIT; + } PFCSS1; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char A9E:1; + unsigned char A8E:1; + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + unsigned char WR32BC32E:1; + unsigned char WR1BC1E:1; + unsigned char DH32E:1; + unsigned char DHE:1; + unsigned char BCLKO:1; + unsigned char ADRHMS2:1; + unsigned char ADRHMS:1; + unsigned char ADRLE:1; + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + unsigned char SDCLKE:1; + unsigned char DQM1E:1; + unsigned char :1; + unsigned char MDSDE:1; + unsigned char ALES:1; + unsigned char ALEOE:1; + unsigned char WAITS:2; + } BIT; + } PFBCR1; + union { + unsigned char BYTE; + struct { + unsigned char D3S:2; + unsigned char D2S:2; + unsigned char D1S:2; + unsigned char D0S:2; + } BIT; + } PFBCR2; + union { + unsigned char BYTE; + struct { + unsigned char WAITS2:1; + unsigned char SDCLKDRV:1; + unsigned char :5; + unsigned char DLHS:1; + } BIT; + } PFBCR3; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PHYMODE1:1; + unsigned char PHYMODE0:1; + unsigned char :4; + } BIT; + } PFENET; + char wk2[16]; + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + unsigned char :6; + } BIT; + } PWPR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P01PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P02PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P03PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P05PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P52PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P56PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P57PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P60PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P61PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P62PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P63PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P64PFS; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P66PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P67PFS; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P71PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P72PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P76PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P77PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P82PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P83PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P84PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P85PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P86PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P87PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P93PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P94PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P95PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P96PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P97PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF2PFS; + char wk10[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } PF5PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ3PFS; + char wk12[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ5PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN5PFS; + char wk14[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ7PFS; +} st_mpc_t; + +typedef struct st_mpu { + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long MPEN:1; + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long UBAC:3; + unsigned long :1; + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long CLR:1; + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long DRW:1; + unsigned long DMPER:1; + unsigned long IMPER:1; + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long DEA:32; + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long SA:32; + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short S:1; + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short INV:1; + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITI:8; + unsigned long :12; + unsigned long UHACI:3; + unsigned long :1; + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITD:8; + unsigned long :12; + unsigned long UHACD:3; + unsigned long :1; + } BIT; + } MHITD; +} st_mpu_t; + +typedef struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOERA; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCRA; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1A; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR1A; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT1A; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTERA; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDERA; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBRA; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TITM:1; + } BIT; + } TITMRA; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG4COR:3; + } BIT; + } TITCR2A; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG4CNT:3; + } BIT; + } TITCNT2A; + char wk7[35]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :5; + unsigned char SCC:1; + unsigned char WRE:1; + } BIT; + } TWCRA; + char wk8[15]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DRS:1; + } BIT; + } TMDR2A; + char wk9[15]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :2; + unsigned char CST8:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTRA; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYRA; + union { + unsigned char BYTE; + struct { + unsigned char SCH0:1; + unsigned char SCH1:1; + unsigned char SCH2:1; + unsigned char SCH3:1; + unsigned char SCH4:1; + unsigned char :1; + unsigned char SCH6:1; + unsigned char SCH7:1; + } BIT; + } TCSYSTR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWERA; + char wk11[1925]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE7D:1; + unsigned char OE7C:1; + unsigned char OE6D:1; + unsigned char OE7B:1; + unsigned char OE7A:1; + unsigned char OE6B:1; + } BIT; + } TOERB; + char wk12[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1B; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union { + unsigned char BYTE; + struct { + unsigned char T6AEN:1; + unsigned char T6ACOR:3; + unsigned char T7VEN:1; + unsigned char T7VCOR:3; + } BIT; + } TITCR1B; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T6ACNT:3; + unsigned char :1; + unsigned char T7VCNT:3; + } BIT; + } TITCNT1B; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTERB; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDERB; + char wk17[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBRB; + char wk18[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TITM:1; + } BIT; + } TITMRB; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG7COR:3; + } BIT; + } TITCR2B; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG7CNT:3; + } BIT; + } TITCNT2B; + char wk19[35]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :5; + unsigned char SCC:1; + unsigned char WRE:1; + } BIT; + } TWCRB; + char wk20[15]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DRS:1; + } BIT; + } TMDR2B; + char wk21[15]; + union { + unsigned char BYTE; + struct { + unsigned char CST7:1; + unsigned char CST6:1; + unsigned char :6; + } BIT; + } TSTRB; + union { + unsigned char BYTE; + struct { + unsigned char SYNC7:1; + unsigned char SYNC6:1; + unsigned char :6; + } BIT; + } TSYRB; + char wk22[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWERB; +} st_mtu_t; + +typedef struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR0; + char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCRC; + char wk1[102]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char TTGE2:1; + unsigned char :5; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; +} st_mtu0_t; + +typedef struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR1; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PHCKSEL:1; + unsigned char LWA:1; + } BIT; + } TMDR3; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PCB:2; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +} st_mtu1_t; + +typedef struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR2; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PCB:2; + unsigned char TPSC2:3; + } BIT; + } TCR2; +} st_mtu2_t; + +typedef struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR3; +} st_mtu3_t; + +typedef struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR4; +} st_mtu4_t; + +typedef struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2U; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2V; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2W; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk4[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +} st_mtu5_t; + +typedef struct st_mtu6 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk9[3]; + union { + unsigned char BYTE; + struct { + unsigned char CE0A:1; + unsigned char CE0B:1; + unsigned char CE0C:1; + unsigned char CE0D:1; + unsigned char CE1A:1; + unsigned char CE1B:1; + unsigned char CE2A:1; + unsigned char CE2B:1; + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR6; +} st_mtu6_t; + +typedef struct st_mtu7 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT7AE:1; + unsigned short DT7AE:1; + unsigned short UT7BE:1; + unsigned short DT7BE:1; + unsigned short ITA6AE:1; + unsigned short ITA7VE:1; + unsigned short ITB6AE:1; + unsigned short ITB7VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR7; +} st_mtu7_t; + +typedef struct st_mtu8 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR8; + char wk0[871]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +} st_mtu8_t; + +typedef struct st_ofsm { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long BANKMD:3; + unsigned long :1; + unsigned long MDE:3; + } BIT; + } MDE; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WDTRSTIRQS:1; + unsigned long WDTRPSS:2; + unsigned long WDTRPES:2; + unsigned long WDTCKS:4; + unsigned long WDTTOPS:2; + unsigned long WDTSTRT:1; + unsigned long :2; + unsigned long IWDTSLCSTP:1; + unsigned long :1; + unsigned long IWDTRSTIRQS:1; + unsigned long IWDTRPSS:2; + unsigned long IWDTRPES:2; + unsigned long IWDTCKS:4; + unsigned long IWDTTOPS:2; + unsigned long IWDTSTRT:1; + unsigned long :1; + } BIT; + } OFS0; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long HOCOEN:1; + unsigned long :5; + unsigned long LVDAS:1; + unsigned long VDSEL:2; + } BIT; + } OFS1; + char wk0[4]; + unsigned long TMINF; + char wk1[12]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long BANKSWP:3; + } BIT; + } BANKSEL; + char wk2[28]; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long SPE:1; + unsigned long :27; + } BIT; + } SPCC; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TMEFDB:3; + unsigned long :1; + unsigned long TMEF:3; + unsigned long :24; + } BIT; + } TMEF; + char wk4[4]; + union { + struct { + unsigned long ID4:8; + unsigned long ID3:8; + unsigned long ID2:8; + unsigned long ID1:8; + unsigned long ID8:8; + unsigned long ID7:8; + unsigned long ID6:8; + unsigned long ID5:8; + unsigned long ID12:8; + unsigned long ID11:8; + unsigned long ID10:8; + unsigned long ID9:8; + unsigned long ID16:8; + unsigned long ID15:8; + unsigned long ID14:8; + unsigned long ID13:8; + } BIT; + } OSIS; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long BTFLG:1; + unsigned long :3; + unsigned long FAWE:12; + unsigned long FSPR:1; + unsigned long :3; + unsigned long FAWS:12; + } BIT; + } FAW; + char wk6[8]; + union { + unsigned long LONG; + struct { + unsigned long CODE:32; + } BIT; + } ROMCODE; +} st_ofsm_t; + +typedef struct st_pdc { + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long EDS:1; + unsigned long PCKDIV:3; + unsigned long PCKOE:1; + unsigned long HERIE:1; + unsigned long VERIE:1; + unsigned long UDRIE:1; + unsigned long OVIE:1; + unsigned long FEIE:1; + unsigned long DFIE:1; + unsigned long PRST:1; + unsigned long HPS:1; + unsigned long VPS:1; + unsigned long PCKE:1; + } BIT; + } PCCR0; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long PCE:1; + } BIT; + } PCCR1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long HERF:1; + unsigned long VERF:1; + unsigned long UDRF:1; + unsigned long OVRF:1; + unsigned long FEF:1; + unsigned long FEMPF:1; + unsigned long FBSY:1; + } BIT; + } PCSR; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long HSYNC:1; + unsigned long VSYNC:1; + } BIT; + } PCMONR; + union { + unsigned long LONG; + } PCDR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long VSZ:12; + unsigned long :4; + unsigned long VST:12; + } BIT; + } VCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long HSZ:12; + unsigned long :4; + unsigned long HST:12; + } BIT; + } HCR; +} st_pdc_t; + +typedef struct st_pmgi { + union { + unsigned long LONG; + struct { + unsigned long :9; + unsigned long PSMCT:3; + unsigned long :1; + unsigned long PSMHT:3; + unsigned long PSMDP:1; + unsigned long :1; + unsigned long PSMCS:6; + unsigned long :8; + } BIT; + } PMGCR; + union { + unsigned long LONG; + struct { + unsigned long PRD:16; + unsigned long :3; + unsigned long PRA:5; + unsigned long PDA:5; + unsigned long :1; + unsigned long PSMAD:1; + unsigned long PSME:1; + } BIT; + } PSMR; +} st_pmgi_t; + +typedef struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE0F:1; + unsigned short :3; + unsigned short PIE1:1; + unsigned short :6; + unsigned short POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short OSF1:1; + unsigned short :5; + unsigned short OCE1:1; + unsigned short OIE1:1; + unsigned short :8; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE4F:1; + unsigned short :3; + unsigned short PIE2:1; + unsigned short :6; + unsigned short POE4M:2; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short OSF2:1; + unsigned short :5; + unsigned short OCE2:1; + unsigned short OIE2:1; + unsigned short :8; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE8F:1; + unsigned short :2; + unsigned short POE8E:1; + unsigned short PIE3:1; + unsigned short :6; + unsigned short POE8M:2; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char MTUCH0HIZ:1; + unsigned char MTUCH67HIZ:1; + unsigned char MTUCH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MTU0DZE:1; + unsigned char MTU0CZE:1; + unsigned char MTU0BZE:1; + unsigned char MTU0AZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short MTU3BDZE:1; + unsigned short MTU4ACZE:1; + unsigned short MTU4BDZE:1; + unsigned short :5; + unsigned short MTU6BDZE:1; + unsigned short MTU7ACZE:1; + unsigned short MTU7BDZE:1; + } BIT; + } POECR2; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short IC5ADDMT67ZE:1; + unsigned short IC4ADDMT67ZE:1; + unsigned short IC3ADDMT67ZE:1; + unsigned short :1; + unsigned short IC1ADDMT67ZE:1; + unsigned short :3; + unsigned short IC5ADDMT34ZE:1; + unsigned short IC4ADDMT34ZE:1; + unsigned short IC3ADDMT34ZE:1; + unsigned short IC2ADDMT34ZE:1; + unsigned short :2; + } BIT; + } POECR4; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short IC5ADDMT0ZE:1; + unsigned short IC4ADDMT0ZE:1; + unsigned short :1; + unsigned short IC2ADDMT0ZE:1; + unsigned short IC1ADDMT0ZE:1; + unsigned short :1; + } BIT; + } POECR5; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE10F:1; + unsigned short :2; + unsigned short POE10E:1; + unsigned short PIE4:1; + unsigned short :6; + unsigned short POE10M:2; + } BIT; + } ICSR4; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE11F:1; + unsigned short :2; + unsigned short POE11E:1; + unsigned short PIE5:1; + unsigned short :6; + unsigned short POE11M:2; + } BIT; + } ICSR5; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OLSEN:1; + unsigned short :1; + unsigned short OLSG2B:1; + unsigned short OLSG2A:1; + unsigned short OLSG1B:1; + unsigned short OLSG1A:1; + unsigned short OLSG0B:1; + unsigned short OLSG0A:1; + } BIT; + } ALR1; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short OSTSTF:1; + unsigned short :2; + unsigned short OSTSTE:1; + unsigned short :9; + } BIT; + } ICSR6; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char M0BSEL:4; + unsigned char M0ASEL:4; + } BIT; + } M0SELR1; + union { + unsigned char BYTE; + struct { + unsigned char M0DSEL:4; + unsigned char M0CSEL:4; + } BIT; + } M0SELR2; + union { + unsigned char BYTE; + struct { + unsigned char M3DSEL:4; + unsigned char M3BSEL:4; + } BIT; + } M3SELR; + union { + unsigned char BYTE; + struct { + unsigned char M4CSEL:4; + unsigned char M4ASEL:4; + } BIT; + } M4SELR1; + union { + unsigned char BYTE; + struct { + unsigned char M4DSEL:4; + unsigned char M4BSEL:4; + } BIT; + } M4SELR2; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char M6DSEL:4; + unsigned char M6BSEL:4; + } BIT; + } M6SELR; +} st_poe_t; + +typedef struct st_poeg { + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGA; + char wk0[252]; + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGB; + char wk1[252]; + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGC; + char wk2[252]; + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGD; +} st_poeg_t; + +typedef struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :3; + unsigned char B2:1; + unsigned char :2; + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port0_t; + +typedef struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char :1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char :1; + } BIT; + } DSCR2; +} st_port1_t; + +typedef struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :7; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :3; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port2_t; + +typedef struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :3; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[103]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port3_t; + +typedef struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +} st_port4_t; + +typedef struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port5_t; + +typedef struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[103]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port6_t; + +typedef struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port7_t; + +typedef struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[54]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port8_t; + +typedef struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port9_t; + +typedef struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_porta_t; + +typedef struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portb_t; + +typedef struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portc_t; + +typedef struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portd_t; + +typedef struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_porte_t; + +typedef struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[46]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[47]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +} st_portf_t; + +typedef struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[47]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portg_t; + +typedef struct st_porth { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[48]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[45]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_porth_t; + +typedef struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :2; + } BIT; + } ODR1; + char wk4[44]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portj_t; + +typedef struct st_portk { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[50]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[43]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portk_t; + +typedef struct st_portl { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[51]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[42]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portl_t; + +typedef struct st_portm { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[52]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[41]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portm_t; + +typedef struct st_portn { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[53]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[40]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portn_t; + +typedef struct st_portq { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[54]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[39]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portq_t; + +typedef struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER15:1; + unsigned char NDER14:1; + unsigned char NDER13:1; + unsigned char NDER12:1; + unsigned char NDER11:1; + unsigned char NDER10:1; + unsigned char NDER9:1; + unsigned char NDER8:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER7:1; + unsigned char NDER6:1; + unsigned char NDER5:1; + unsigned char NDER4:1; + unsigned char NDER3:1; + unsigned char NDER2:1; + unsigned char NDER1:1; + unsigned char NDER0:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD15:1; + unsigned char POD14:1; + unsigned char POD13:1; + unsigned char POD12:1; + unsigned char POD11:1; + unsigned char POD10:1; + unsigned char POD9:1; + unsigned char POD8:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD7:1; + unsigned char POD6:1; + unsigned char POD5:1; + unsigned char POD4:1; + unsigned char POD3:1; + unsigned char POD2:1; + unsigned char POD1:1; + unsigned char POD0:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR15:1; + unsigned char NDR14:1; + unsigned char NDR13:1; + unsigned char NDR12:1; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR7:1; + unsigned char NDR6:1; + unsigned char NDR5:1; + unsigned char NDR4:1; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL2; +} st_ppg0_t; + +typedef struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PTRSL:1; + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER31:1; + unsigned char NDER30:1; + unsigned char NDER29:1; + unsigned char NDER28:1; + unsigned char NDER27:1; + unsigned char NDER26:1; + unsigned char NDER25:1; + unsigned char NDER24:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER23:1; + unsigned char NDER22:1; + unsigned char NDER21:1; + unsigned char NDER20:1; + unsigned char NDER19:1; + unsigned char NDER18:1; + unsigned char NDER17:1; + unsigned char NDER16:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD31:1; + unsigned char POD30:1; + unsigned char POD29:1; + unsigned char POD28:1; + unsigned char POD27:1; + unsigned char POD26:1; + unsigned char POD25:1; + unsigned char POD24:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD23:1; + unsigned char POD22:1; + unsigned char POD21:1; + unsigned char POD20:1; + unsigned char POD19:1; + unsigned char POD18:1; + unsigned char POD17:1; + unsigned char POD16:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR31:1; + unsigned char NDR30:1; + unsigned char NDR29:1; + unsigned char NDR28:1; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR23:1; + unsigned char NDR22:1; + unsigned char NDR21:1; + unsigned char NDR20:1; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL2; +} st_ppg1_t; + +typedef struct st_ptpedmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long :1; + unsigned long RFCOF:1; + unsigned long :2; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :7; + unsigned long MACE:1; + unsigned long RPORT:1; + unsigned long :2; + unsigned long PVER:1; + unsigned long TYPE:4; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long :1; + unsigned long RFCOFIP:1; + unsigned long :2; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :7; + unsigned long MACEIP:1; + unsigned long RPORTIP:1; + unsigned long :2; + unsigned long PVERIP:1; + unsigned long :4; + } BIT; + } EESIPR; + char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RNR:1; + } BIT; + } RMCR; + char wk10[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + char wk11[4]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_ptpedmac_t; + +typedef struct st_qspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char :1; + unsigned char MSTR:1; + unsigned char :1; + unsigned char SPSSLIE:1; + unsigned char :1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SSLP:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :1; + unsigned char IO3FV:1; + unsigned char IO2FV:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRFF:1; + unsigned char TREND:1; + unsigned char SPTEF:1; + unsigned char SPSSLF:1; + unsigned char :4; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SPSC:2; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SPSS:2; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPBR7:1; + unsigned char SPBR6:1; + unsigned char SPBR5:1; + unsigned char SPBR4:1; + unsigned char SPBR3:1; + unsigned char SPBR2:1; + unsigned char SPBR1:1; + unsigned char SPBR0:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char TXDMY:1; + unsigned char :7; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned char BYTE; + struct { + unsigned char TXRST:1; + unsigned char RXRST:1; + unsigned char TXTRG:2; + unsigned char TXTRGEX:1; + unsigned char RXTRG:3; + } BIT; + } SPBFCR; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TXBC:6; + unsigned short :2; + unsigned short RXBC:6; + } BIT; + } SPBDCR; + unsigned long SPBMUL0; + unsigned long SPBMUL1; + unsigned long SPBMUL2; + unsigned long SPBMUL3; +} st_qspi_t; + +typedef struct st_ram { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RAMMODE:2; + } BIT; + } RAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RAMERR:1; + } BIT; + } RAMSTS; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char RAMPRCR:1; + } BIT; + } RAMPRCR; + char wk1[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long READ:16; + unsigned long :3; + } BIT; + } RAMECAD; + char wk2[52]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char EXRAMMODE:2; + } BIT; + } EXRAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EXRAMERR:1; + } BIT; + } EXRAMSTS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char EXRAMPRCR:1; + } BIT; + } EXRAMPRCR; + char wk4[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long READ:16; + unsigned long :3; + } BIT; + } EXRAMECAD; +} st_ram_t; + +typedef struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + unsigned char :1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char FMPE:1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +} st_riic_t; + +typedef struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :2; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRF:1; + unsigned char :1; + unsigned char SPTEF:1; + unsigned char UDRF:1; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPBYT:1; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char :2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SCKASE:1; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BYSW:1; + } BIT; + } SPDCR2; +} st_rspi_t; + +typedef struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT1; + }; + char wk2[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT2; + }; + char wk3[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT3; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT0AR; + }; + char wk7[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT1AR; + }; + char wk8[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT2AR; + }; + char wk9[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT3AR; + }; + char wk10[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT0AER; + }; + char wk11[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT1AER; + }; + char wk12[1]; + union { + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ENB:8; + } BIT; + } BCNT2AER; + }; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :7; + } BIT; + } RYRAREN; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT3AER; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char RTCOS:1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char CNTMD:1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCDV:3; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RCKSEL:1; + } BIT; + } RCR4; + char wk17[1]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RFC:1; + } BIT; + } RFRH; + union { + unsigned short WORD; + struct { + unsigned short RFC:16; + } BIT; + } RFRL; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; + char wk18[17]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR2; + char wk21[13]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT0CP0; + }; + char wk22[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT1CP0; + }; + char wk23[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT2CP0; + }; + char wk24[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT3CP0; + }; + char wk25[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP0; + char wk26[5]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT0CP1; + }; + char wk27[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT1CP1; + }; + char wk28[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT2CP1; + }; + char wk29[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT3CP1; + }; + char wk30[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP1; + char wk31[5]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT0CP2; + }; + char wk32[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT1CP2; + }; + char wk33[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT2CP2; + }; + char wk34[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT3CP2; + }; + char wk35[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP2; +} st_rtc_t; + +typedef struct st_s12ad { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :2; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSA007:1; + unsigned short ANSA006:1; + unsigned short ANSA005:1; + unsigned short ANSA004:1; + unsigned short ANSA003:1; + unsigned short ANSA002:1; + unsigned short ANSA001:1; + unsigned short ANSA000:1; + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ADS007:1; + unsigned short ADS006:1; + unsigned short ADS005:1; + unsigned short ADS004:1; + unsigned short ADS003:1; + unsigned short ADS002:1; + unsigned short ADS001:1; + unsigned short ADS000:1; + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :4; + unsigned char ADC:3; + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short ADPRC:2; + unsigned short :1; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSB007:1; + unsigned short ANSB006:1; + unsigned short ANSB005:1; + unsigned short ANSB004:1; + unsigned short ANSB003:1; + unsigned short ANSB002:1; + unsigned short ANSB001:1; + unsigned short ANSB000:1; + } BIT; + } ADANSB0; + char wk5[2]; + union { + unsigned short WORD; + } ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk7[51]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PRO:2; + } BIT; + } ADSAMPR; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SHANS:3; + unsigned short SSTSH:8; + } BIT; + } ADSHCR; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short SAM:1; + unsigned short :5; + } BIT; + } ADSAM; + char wk10[10]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHMD:1; + } BIT; + } ADSHMSR; + char wk12[3]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short LGRRS:1; + unsigned short :12; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk13[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk14[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MONCMPB:1; + unsigned char MONCMPA:1; + unsigned char :3; + unsigned char MONCOMB:1; + } BIT; + } ADWINMON; + char wk15[3]; + union { + unsigned short WORD; + struct { + unsigned short CMPAIE:1; + unsigned short WCMPE:1; + unsigned short CMPBIE:1; + unsigned short :1; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBE:1; + unsigned short :7; + unsigned short CMPAB:2; + } BIT; + } ADCMPCR; + char wk16[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPCHA007:1; + unsigned short CMPCHA006:1; + unsigned short CMPCHA005:1; + unsigned short CMPCHA004:1; + unsigned short CMPCHA003:1; + unsigned short CMPCHA002:1; + unsigned short CMPCHA001:1; + unsigned short CMPCHA000:1; + } BIT; + } ADCMPANSR0; + char wk17[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPLCHA007:1; + unsigned short CMPLCHA006:1; + unsigned short CMPLCHA005:1; + unsigned short CMPLCHA004:1; + unsigned short CMPLCHA003:1; + unsigned short CMPLCHA002:1; + unsigned short CMPLCHA001:1; + unsigned short CMPLCHA000:1; + } BIT; + } ADCMPLR0; + char wk18[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPSTCHA007:1; + unsigned short CMPSTCHA006:1; + unsigned short CMPSTCHA005:1; + unsigned short CMPSTCHA004:1; + unsigned short CMPSTCHA003:1; + unsigned short CMPSTCHA002:1; + unsigned short CMPSTCHA001:1; + unsigned short CMPSTCHA000:1; + } BIT; + } ADCMPSR0; + char wk19[4]; + union { + unsigned char BYTE; + struct { + unsigned char CMPLB:1; + unsigned char :1; + unsigned char CMPCHB:6; + } BIT; + } ADCMPBNSR; + char wk20[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CMPSTB:1; + } BIT; + } ADCMPBSR; + char wk21[39]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSC007:1; + unsigned short ANSC006:1; + unsigned short ANSC005:1; + unsigned short ANSC004:1; + unsigned short ANSC003:1; + unsigned short ANSC002:1; + unsigned short ANSC001:1; + unsigned short ANSC000:1; + } BIT; + } ADANSC0; + char wk22[3]; + union { + unsigned char BYTE; + struct { + unsigned char GRCE:1; + unsigned char GCADIE:1; + unsigned char TRSC:6; + } BIT; + } ADGCTRGR; + char wk23[6]; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +} st_s12ad_t; + +typedef struct st_s12ad1 { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :2; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short ANSA015:1; + unsigned short ANSA014:1; + unsigned short ANSA013:1; + unsigned short ANSA012:1; + unsigned short ANSA011:1; + unsigned short ANSA010:1; + unsigned short ANSA009:1; + unsigned short ANSA008:1; + unsigned short ANSA007:1; + unsigned short ANSA006:1; + unsigned short ANSA005:1; + unsigned short ANSA004:1; + unsigned short ANSA003:1; + unsigned short ANSA002:1; + unsigned short ANSA001:1; + unsigned short ANSA000:1; + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSA104:1; + unsigned short ANSA103:1; + unsigned short ANSA102:1; + unsigned short ANSA101:1; + unsigned short ANSA100:1; + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + unsigned short ADS015:1; + unsigned short ADS014:1; + unsigned short ADS013:1; + unsigned short ADS012:1; + unsigned short ADS011:1; + unsigned short ADS010:1; + unsigned short ADS009:1; + unsigned short ADS008:1; + unsigned short ADS007:1; + unsigned short ADS006:1; + unsigned short ADS005:1; + unsigned short ADS004:1; + unsigned short ADS003:1; + unsigned short ADS002:1; + unsigned short ADS001:1; + unsigned short ADS000:1; + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ADS104:1; + unsigned short ADS103:1; + unsigned short ADS102:1; + unsigned short ADS101:1; + unsigned short ADS100:1; + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :4; + unsigned char ADC:3; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short ADPRC:2; + unsigned short :1; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + unsigned short EXOEN:1; + unsigned short EXSEL:2; + unsigned short :1; + unsigned short OCSB:1; + unsigned short TSSB:1; + unsigned short OCSA:1; + unsigned short TSSA:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + unsigned short ANSB015:1; + unsigned short ANSB014:1; + unsigned short ANSB013:1; + unsigned short ANSB012:1; + unsigned short ANSB011:1; + unsigned short ANSB010:1; + unsigned short ANSB009:1; + unsigned short ANSB008:1; + unsigned short ANSB007:1; + unsigned short ANSB006:1; + unsigned short ANSB005:1; + unsigned short ANSB004:1; + unsigned short ANSB003:1; + unsigned short ANSB002:1; + unsigned short ANSB001:1; + unsigned short ANSB000:1; + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSB104:1; + unsigned short ANSB103:1; + unsigned short ANSB102:1; + unsigned short ANSB101:1; + unsigned short ANSB100:1; + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk2[25]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PRO:2; + } BIT; + } ADSAMPR; + char wk3[10]; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short SAM:1; + unsigned short :5; + } BIT; + } ADSAM; + char wk4[10]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk5[5]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short LGRRS:1; + unsigned short :12; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MONCMPB:1; + unsigned char MONCMPA:1; + unsigned char :3; + unsigned char MONCOMB:1; + } BIT; + } ADWINMON; + char wk8[3]; + union { + unsigned short WORD; + struct { + unsigned short CMPAIE:1; + unsigned short WCMPE:1; + unsigned short CMPBIE:1; + unsigned short :1; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBE:1; + unsigned short :7; + unsigned short CMPAB:2; + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPSOC:1; + unsigned char CMPSTS:1; + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPLOC:1; + unsigned char CMPLTS:1; + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + unsigned short CMPCHA015:1; + unsigned short CMPCHA014:1; + unsigned short CMPCHA013:1; + unsigned short CMPCHA012:1; + unsigned short CMPCHA011:1; + unsigned short CMPCHA010:1; + unsigned short CMPCHA009:1; + unsigned short CMPCHA008:1; + unsigned short CMPCHA007:1; + unsigned short CMPCHA006:1; + unsigned short CMPCHA005:1; + unsigned short CMPCHA004:1; + unsigned short CMPCHA003:1; + unsigned short CMPCHA002:1; + unsigned short CMPCHA001:1; + unsigned short CMPCHA000:1; + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPCHA104:1; + unsigned short CMPCHA103:1; + unsigned short CMPCHA102:1; + unsigned short CMPCHA101:1; + unsigned short CMPCHA100:1; + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + unsigned short CMPLCHA015:1; + unsigned short CMPLCHA014:1; + unsigned short CMPLCHA013:1; + unsigned short CMPLCHA012:1; + unsigned short CMPLCHA011:1; + unsigned short CMPLCHA010:1; + unsigned short CMPLCHA009:1; + unsigned short CMPLCHA008:1; + unsigned short CMPLCHA007:1; + unsigned short CMPLCHA006:1; + unsigned short CMPLCHA005:1; + unsigned short CMPLCHA004:1; + unsigned short CMPLCHA003:1; + unsigned short CMPLCHA002:1; + unsigned short CMPLCHA001:1; + unsigned short CMPLCHA000:1; + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPLCHA104:1; + unsigned short CMPLCHA103:1; + unsigned short CMPLCHA102:1; + unsigned short CMPLCHA101:1; + unsigned short CMPLCHA100:1; + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short CMPSTCHA015:1; + unsigned short CMPSTCHA014:1; + unsigned short CMPSTCHA013:1; + unsigned short CMPSTCHA012:1; + unsigned short CMPSTCHA011:1; + unsigned short CMPSTCHA010:1; + unsigned short CMPSTCHA009:1; + unsigned short CMPSTCHA008:1; + unsigned short CMPSTCHA007:1; + unsigned short CMPSTCHA006:1; + unsigned short CMPSTCHA005:1; + unsigned short CMPSTCHA004:1; + unsigned short CMPSTCHA003:1; + unsigned short CMPSTCHA002:1; + unsigned short CMPSTCHA001:1; + unsigned short CMPSTCHA000:1; + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPSTCHA104:1; + unsigned short CMPSTCHA103:1; + unsigned short CMPSTCHA102:1; + unsigned short CMPSTCHA101:1; + unsigned short CMPSTCHA100:1; + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPFOC:1; + unsigned char CMPFTS:1; + } BIT; + } ADCMPSER; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char CMPLB:1; + unsigned char :1; + unsigned char CMPCHB:6; + } BIT; + } ADCMPBNSR; + char wk10[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CMPSTB:1; + } BIT; + } ADCMPBSR; + char wk11[39]; + union { + unsigned short WORD; + struct { + unsigned short ANSC015:1; + unsigned short ANSC014:1; + unsigned short ANSC013:1; + unsigned short ANSC012:1; + unsigned short ANSC011:1; + unsigned short ANSC010:1; + unsigned short ANSC009:1; + unsigned short ANSC008:1; + unsigned short ANSC007:1; + unsigned short ANSC006:1; + unsigned short ANSC005:1; + unsigned short ANSC004:1; + unsigned short ANSC003:1; + unsigned short ANSC002:1; + unsigned short ANSC001:1; + unsigned short ANSC000:1; + } BIT; + } ADANSC0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSC104:1; + unsigned short ANSC103:1; + unsigned short ANSC102:1; + unsigned short ANSC101:1; + unsigned short ANSC100:1; + } BIT; + } ADANSC1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char OCSC:1; + unsigned char TSSC:1; + } BIT; + } ADGCEXCR; + union { + unsigned char BYTE; + struct { + unsigned char GRCE:1; + unsigned char GCADIE:1; + unsigned char TRSC:6; + } BIT; + } ADGCTRGR; + char wk12[3]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + unsigned char ADSSTR8; + unsigned char ADSSTR9; + unsigned char ADSSTR10; + unsigned char ADSSTR11; + unsigned char ADSSTR12; + unsigned char ADSSTR13; + unsigned char ADSSTR14; + unsigned char ADSSTR15; +} st_s12ad1_t; + +typedef struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char ABCSE:1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + unsigned char DCME:1; + unsigned char IDSEL:1; + unsigned char :1; + unsigned char DFER:1; + unsigned char DPER:1; + unsigned char :2; + unsigned char DCMF:1; + } BIT; + } DCCR; + char wk0[6]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :7; + unsigned short CMPD:9; + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPB2IO:1; + unsigned char SPB2DT:1; + unsigned char RXDMON:1; + } BIT; + } SPTR; +} st_sci0_t; + +typedef struct st_sci7 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + union { + unsigned char BYTE; + struct { + unsigned char TDFE:1; + unsigned char RDF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char :1; + unsigned char DR:1; + } BIT; + } SSRFIFO; + }; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char ABCSE:1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :6; + unsigned short MPBT:1; + unsigned short TDAT:9; + } BIT; + } FTDR; + }; + union { + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :1; + unsigned short RDF:1; + unsigned short ORER:1; + unsigned short FER:1; + unsigned short PER:1; + unsigned short DR:1; + unsigned short MPB:1; + unsigned short RDAT:9; + } BIT; + } FRDR; + }; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + unsigned char DCME:1; + unsigned char IDSEL:1; + unsigned char :1; + unsigned char DFER:1; + unsigned char DPER:1; + unsigned char :2; + unsigned char DCMF:1; + } BIT; + } DCCR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char RSTRG:4; + unsigned char RTRG:4; + unsigned char TTRG:4; + unsigned char DRES:1; + unsigned char TFRST:1; + unsigned char RFRST:1; + unsigned char FM:1; + } BIT; + } FCR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char T:5; + unsigned char :3; + unsigned char R:5; + } BIT; + } FDR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char PNUM:5; + unsigned char :1; + unsigned char FNUM:5; + unsigned char :1; + unsigned char ORER:1; + } BIT; + } LSR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :7; + unsigned short CMPD:9; + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPB2IO:1; + unsigned char SPB2DT:1; + unsigned char RXDMON:1; + } BIT; + } SPTR; +} st_sci7_t; + +typedef struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + unsigned char :1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_sdhi { + union { + unsigned long LONG; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned long :16; + unsigned long CMD12AT:2; + unsigned long TRSTP:1; + unsigned long CMDRW:1; + unsigned long CMDTP:1; + unsigned long RSPTP:3; + unsigned long ACMD:2; + unsigned long CMDIDX:6; + } BIT; +#endif + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long SDBLKCNTEN:1; + unsigned long :7; + unsigned long STP:1; + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long SDD3MON:1; + unsigned long SDD3IN:1; + unsigned long SDD3RM:1; + unsigned long SDWPMON:1; + unsigned long :1; + unsigned long SDCDMON:1; + unsigned long SDCDIN:1; + unsigned long SDCDRM:1; + unsigned long ACEND:1; + unsigned long :1; + unsigned long RSPEND:1; + } BIT; + } SDSTS1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILA:1; + unsigned long CBSY:1; + unsigned long SDCLKCREN:1; + unsigned long :3; + unsigned long BWE:1; + unsigned long BRE:1; + unsigned long SDD0MON:1; + unsigned long RSPTO:1; + unsigned long ILR:1; + unsigned long ILW:1; + unsigned long DTO:1; + unsigned long ENDE:1; + unsigned long CRCE:1; + unsigned long CMDE:1; + } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long SDD3INM:1; + unsigned long SDD3RMM:1; + unsigned long :3; + unsigned long SDCDINM:1; + unsigned long SDCDRMM:1; + unsigned long ACENDM:1; + unsigned long :1; + unsigned long RSPENDM:1; + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILAM:1; + unsigned long :5; + unsigned long BWEM:1; + unsigned long BREM:1; + unsigned long :1; + unsigned long RSPTOM:1; + unsigned long ILRM:1; + unsigned long ILWM:1; + unsigned long DTTOM:1; + unsigned long ENDEM:1; + unsigned long CRCEM:1; + unsigned long CMDEM:1; + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long CLKCTRLEN:1; + unsigned long CLKEN:1; + unsigned long CLKSEL:8; + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long LEN:10; + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long WIDTH:1; + unsigned long :7; + unsigned long TOP:4; + unsigned long CTOP:4; + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CRCTK:3; + unsigned long CRCTKE:1; + unsigned long RDCRCE:1; + unsigned long RSPCRCE1:1; + unsigned long RSPCRCE0:1; + unsigned long :2; + unsigned long CRCLENE:1; + unsigned long RDLENE:1; + unsigned long RSPLENE1:1; + unsigned long RSPLENE0:1; + unsigned long CMDE1:1; + unsigned long CMDE0:1; + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long CRCBSYTO:1; + unsigned long CRCTO:1; + unsigned long RDTO:1; + unsigned long BSYTO1:1; + unsigned long BSYTO0:1; + unsigned long RSPTO1:1; + unsigned long RSPTO0:1; + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long C52PUB:1; + unsigned long IOABT:1; + unsigned long :5; + unsigned long RWREQ:1; + unsigned long :1; + unsigned long INTEN:1; + } BIT; + } SDIOMD; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWT:1; + unsigned long EXPUB52:1; + unsigned long :13; + unsigned long IOIRQ:1; + } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWTM:1; + unsigned long EXPUB52M:1; + unsigned long :13; + unsigned long IOIRQM:1; + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long DMAEN:1; + unsigned long :1; + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SDRST:1; + } BIT; + } SDRST; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CPRM:1; + unsigned long CLKRAT:1; + unsigned long :2; + unsigned long IP2:4; + unsigned long IP1:8; + } BIT; + } SDVER; + char wk10[24]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long BRSWP:1; + unsigned long BWSWP:1; + unsigned long :6; + } BIT; + } SDSWAP; +} st_sdhi_t; + +typedef struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +} st_smci_t; + +typedef struct st_ssie { + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIEN:1; + unsigned long TOIEN:1; + unsigned long RUIEN:1; + unsigned long ROIEN:1; + unsigned long IIEN:1; + unsigned long :1; + unsigned long FRM:2; + unsigned long DWL:3; + unsigned long SWL:3; + unsigned long :1; + unsigned long MST:1; + unsigned long BCKP:1; + unsigned long LRCKP:1; + unsigned long SPDP:1; + unsigned long SDTA:1; + unsigned long PDTA:1; + unsigned long DEL:1; + unsigned long CKDV:4; + unsigned long MUEN:1; + unsigned long :1; + unsigned long TEN:1; + unsigned long REN:1; + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIRQ:1; + unsigned long TOIRQ:1; + unsigned long RUIRQ:1; + unsigned long ROIRQ:1; + unsigned long IIRQ:1; + unsigned long :25; + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long AUCKE:1; + unsigned long :14; + unsigned long SSIRST:1; + unsigned long :4; + unsigned long BSW:1; + unsigned long :7; + unsigned long TIE:1; + unsigned long RIE:1; + unsigned long TFRST:1; + unsigned long RFRST:1; + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TDC:6; + unsigned long :7; + unsigned long TDE:1; + unsigned long :2; + unsigned long RDC:6; + unsigned long :7; + unsigned long RDF:1; + } BIT; + } SSIFSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SSIFTDR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SSIFRDR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long BCKASTP:1; + unsigned long LRCONT:1; + unsigned long :6; + unsigned long OMOD:2; + } BIT; + } SSIOFR; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TDES:5; + unsigned long :3; + unsigned long RDFS:5; + } BIT; + } SSISCR; +} st_ssie_t; + +typedef struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SBYRAME:1; + unsigned short ECCRAME:1; + unsigned short :5; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + unsigned short :14; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long ACSE:1; + unsigned long :1; + unsigned long MSTPA29:1; + unsigned long MSTPA28:1; + unsigned long MSTPA27:1; + unsigned long :2; + unsigned long MSTPA24:1; + unsigned long :4; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long MSTPA16:1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long MSTPA13:1; + unsigned long :1; + unsigned long MSTPA11:1; + unsigned long MSTPA10:1; + unsigned long MSTPA9:1; + unsigned long :1; + unsigned long MSTPA7:1; + unsigned long :1; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :2; + unsigned long MSTPA1:1; + unsigned long MSTPA0:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long MSTPB28:1; + unsigned long MSTPB27:1; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long MSTPB24:1; + unsigned long MSTPB23:1; + unsigned long MSTPB22:1; + unsigned long MSTPB21:1; + unsigned long MSTPB20:1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long MSTPB16:1; + unsigned long MSTPB15:1; + unsigned long MSTPB14:1; + unsigned long MSTPB13:1; + unsigned long :3; + unsigned long MSTPB9:1; + unsigned long MSTPB8:1; + unsigned long :1; + unsigned long MSTPB6:1; + unsigned long :1; + unsigned long MSTPB4:1; + unsigned long :1; + unsigned long MSTPB2:1; + unsigned long MSTPB1:1; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long MSTPC29:1; + unsigned long MSTPC28:1; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long MSTPC25:1; + unsigned long MSTPC24:1; + unsigned long MSTPC23:1; + unsigned long MSTPC22:1; + unsigned long :2; + unsigned long MSTPC19:1; + unsigned long :1; + unsigned long MSTPC17:1; + unsigned long :9; + unsigned long MSTPC7:1; + unsigned long MSTPC6:1; + unsigned long :3; + unsigned long MSTPC2:1; + unsigned long :1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long MSTPD27:1; + unsigned long :5; + unsigned long MSTPD21:1; + unsigned long :1; + unsigned long MSTPD19:1; + unsigned long :3; + unsigned long MSTPD15:1; + unsigned long MSTPD14:1; + unsigned long :6; + unsigned long MSTPD7:1; + unsigned long MSTPD6:1; + unsigned long MSTPD5:1; + unsigned long MSTPD4:1; + unsigned long MSTPD3:1; + unsigned long MSTPD2:1; + unsigned long MSTPD1:1; + unsigned long MSTPD0:1; + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long PSTOP0:1; + unsigned long :2; + unsigned long BCK:4; + unsigned long PCKA:4; + unsigned long PCKB:4; + unsigned long PCKC:4; + unsigned long PCKD:4; + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short UCK:4; + unsigned short :4; + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + unsigned short :8; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :3; + unsigned short PLLSRCSEL:1; + unsigned short :2; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk3[5]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char HCFRQ:2; + } BIT; + } HOCOCR2; + char wk5[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PPLOVF:1; + unsigned char ILCOVF:1; + unsigned char HCOVF:1; + unsigned char PLOVF:1; + unsigned char SOOVF:1; + unsigned char MOOVF:1; + } BIT; + } OSCOVFSR; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short CKOSTP:1; + unsigned short CKODIV:3; + unsigned short :1; + unsigned short CKOSEL:3; + unsigned short :8; + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short UPLLSEL:1; + unsigned short :7; + unsigned short OUTCKSEL:1; + unsigned short :4; + } BIT; + } PACKCR; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short PPLSTC:6; + unsigned short :6; + unsigned short PPLIDIV:2; + } BIT; + } PPLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PPLLEN:1; + } BIT; + } PPLLCR2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PPLCK:4; + } BIT; + } PPLLCR3; + char wk9[84]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char MSTS:8; + } BIT; + } MOSCWTCR; + union { + unsigned char BYTE; + struct { + unsigned char SSTS:8; + } BIT; + } SOSCWTCR; + char wk10[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char WDTRF:1; + unsigned char IWDTRF:1; + } BIT; + } RSTSR2; + char wk11[1]; + unsigned short SWRR; + char wk12[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD1IRQSEL:1; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD2IRQSEL:1; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk13[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short :1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk14[3100]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MEMWAIT:1; + } BIT; + } MEMWAIT; + char wk15[45667]; + union { + unsigned char BYTE; + struct { + unsigned char DPSBY:1; + unsigned char IOKEEP:1; + unsigned char :4; + unsigned char DEEPCUT:2; + } BIT; + } DPSBYCR; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7E:1; + unsigned char DIRQ6E:1; + unsigned char DIRQ5E:1; + unsigned char DIRQ4E:1; + unsigned char DIRQ3E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ0E:1; + } BIT; + } DPSIER0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15E:1; + unsigned char DIRQ14E:1; + unsigned char DIRQ13E:1; + unsigned char DIRQ12E:1; + unsigned char DIRQ11E:1; + unsigned char DIRQ10E:1; + unsigned char DIRQ9E:1; + unsigned char DIRQ8E:1; + } BIT; + } DPSIER1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIE:1; + unsigned char DRIICCIE:1; + unsigned char DRIICDIE:1; + unsigned char DNMIE:1; + unsigned char DRTCAIE:1; + unsigned char DRTCIIE:1; + unsigned char DLVD2IE:1; + unsigned char DLVD1IE:1; + } BIT; + } DPSIER2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIE:1; + } BIT; + } DPSIER3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7F:1; + unsigned char DIRQ6F:1; + unsigned char DIRQ5F:1; + unsigned char DIRQ4F:1; + unsigned char DIRQ3F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ0F:1; + } BIT; + } DPSIFR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15F:1; + unsigned char DIRQ14F:1; + unsigned char DIRQ13F:1; + unsigned char DIRQ12F:1; + unsigned char DIRQ11F:1; + unsigned char DIRQ10F:1; + unsigned char DIRQ9F:1; + unsigned char DIRQ8F:1; + } BIT; + } DPSIFR1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIF:1; + unsigned char DRIICCIF:1; + unsigned char DRIICDIF:1; + unsigned char DNMIF:1; + unsigned char DRTCAIF:1; + unsigned char DRTCIIF:1; + unsigned char DLVD2IF:1; + unsigned char DLVD1IF:1; + } BIT; + } DPSIFR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIF:1; + } BIT; + } DPSIFR3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7EG:1; + unsigned char DIRQ6EG:1; + unsigned char DIRQ5EG:1; + unsigned char DIRQ4EG:1; + unsigned char DIRQ3EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ0EG:1; + } BIT; + } DPSIEGR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15EG:1; + unsigned char DIRQ14EG:1; + unsigned char DIRQ13EG:1; + unsigned char DIRQ12EG:1; + unsigned char DIRQ11EG:1; + unsigned char DIRQ10EG:1; + unsigned char DIRQ9EG:1; + unsigned char DIRQ8EG:1; + } BIT; + } DPSIEGR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DRIICCEG:1; + unsigned char DRIICDEG:1; + unsigned char DNMIEG:1; + unsigned char :2; + unsigned char DLVD2EG:1; + unsigned char DLVD1EG:1; + } BIT; + } DPSIEGR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIEG:1; + } BIT; + } DPSIEGR3; + char wk17[2]; + union { + unsigned char BYTE; + struct { + unsigned char DPSRSTF:1; + unsigned char :3; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char LVD0RF:1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk18[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MOSEL:1; + unsigned char MODRV2:2; + unsigned char :3; + unsigned char MOFXIN:1; + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HOCOPCNT:1; + } BIT; + } HOCOPCR; + char wk19[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + unsigned char :5; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char LVD2LVL:4; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk20[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char LVD1FSAMP:2; + unsigned char :1; + unsigned char LVD1CMPE:1; + unsigned char LVD1DFDIS:1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char LVD2FSAMP:2; + unsigned char :1; + unsigned char LVD2CMPE:1; + unsigned char LVD2DFDIS:1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; + char wk21[4]; + unsigned char DPSBKR[32]; +} st_system_t; + +typedef struct st_temps { + union { + unsigned char BYTE; + struct { + unsigned char TSEN:1; + unsigned char :2; + unsigned char TSOE:1; + unsigned char :4; + } BIT; + } TSCR; +} st_temps_t; + +typedef struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADTE:1; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +} st_tmr0_t; + +typedef struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +} st_tmr1_t; + +typedef struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +} st_tmr01_t; + +typedef struct st_tpu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu0_t; + +typedef struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu1_t; + +typedef struct st_tpu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu2_t; + +typedef struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu3_t; + +typedef struct st_tpu4 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu4_t; + +typedef struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu5_t; + +typedef struct st_tpua { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST5:1; + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC5:1; + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; +} st_tpua_t; + +typedef struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBSTS0:1; + unsigned long :1; + unsigned long DOVCB0:1; + unsigned long DOVCA0:1; + unsigned long :2; + unsigned long DM0:1; + unsigned long DP0:1; + unsigned long :11; + unsigned long FIXPHY0:1; + unsigned long DRPD0:1; + unsigned long :1; + unsigned long RPUE0:1; + unsigned long SRPC0:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBINT0:1; + unsigned long :1; + unsigned long DOVRCRB0:1; + unsigned long DOVRCRA0:1; + unsigned long :2; + unsigned long DMINT0:1; + unsigned long DPINT0:1; + unsigned long :8; + unsigned long DVBSE0:1; + unsigned long :1; + unsigned long DOVRCRBE0:1; + unsigned long DOVRCRAE0:1; + unsigned long :2; + unsigned long DMINTE0:1; + unsigned long DPINTE0:1; + } BIT; + } DPUSR1R; +} st_usb_t; + +typedef struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SCKE:1; + unsigned short :3; + unsigned short DCFM:1; + unsigned short DRPD:1; + unsigned short DPRPU:1; + unsigned short :3; + unsigned short USBE:1; + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short SOFEA:1; + unsigned short :2; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short HNPBTOA:1; + unsigned short EXICEN:1; + unsigned short VBUSEN:1; + unsigned short WKUP:1; + unsigned short RWUPE:1; + unsigned short USBRST:1; + unsigned short RESUME:1; + unsigned short UACT:1; + unsigned short :1; + unsigned short RHST:3; + } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + unsigned short :8; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short OVRCRE:1; + unsigned short BCHGE:1; + unsigned short :1; + unsigned short DTCHE:1; + unsigned short ATTCHE:1; + unsigned short :4; + unsigned short EOFERRE:1; + unsigned short SIGNE:1; + unsigned short SACKE:1; + unsigned short :4; + } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short TRNENSEL:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + unsigned short :4; + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short OVRCR:1; + unsigned short BCHG:1; + unsigned short :1; + unsigned short DTCH:1; + unsigned short ATTCH:1; + unsigned short :4; + unsigned short EOFERR:1; + unsigned short SIGN:1; + unsigned short SACK:1; + unsigned short :4; + } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDY:1; + unsigned short PIPE8NRDY:1; + unsigned short PIPE7NRDY:1; + unsigned short PIPE6NRDY:1; + unsigned short PIPE5NRDY:1; + unsigned short PIPE4NRDY:1; + unsigned short PIPE3NRDY:1; + unsigned short PIPE2NRDY:1; + unsigned short PIPE1NRDY:1; + unsigned short PIPE0NRDY:1; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMP:1; + unsigned short PIPE8BEMP:1; + unsigned short PIPE7BEMP:1; + unsigned short PIPE6BEMP:1; + unsigned short PIPE5BEMP:1; + unsigned short PIPE4BEMP:1; + unsigned short PIPE3BEMP:1; + unsigned short PIPE2BEMP:1; + unsigned short PIPE1BEMP:1; + unsigned short PIPE0BEMP:1; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short DVCHG:1; + unsigned short :15; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short STSRECOV:4; + unsigned short :1; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short :4; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :5; + unsigned short MXPS:7; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short SUREQ:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short PIPESEL:4; + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :3; + unsigned short MXPS:9; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD5; + char wk16[20]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long SLEWF01:1; + unsigned long SLEWF00:1; + unsigned long SLEWR01:1; + unsigned long SLEWR00:1; + } BIT; + } PHYSLEW; +} st_usb0_t; + +typedef struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } WDTRCR; +} st_wdt_t; + +typedef struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +} st_flashconst_t; + +typedef struct st_tempsconst { + unsigned long TSCDR; +} st_tempsconst_t; + +#ifdef __IAR_SYSTEMS_ICC__ +#pragma bitfields=default +#pragma language=restore +#else +#pragma bit_order +#endif + +#ifndef __IAR_SYSTEMS_ICC__ +#pragma packoption +#endif + + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c new file mode 100644 index 000000000..b36242303 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c @@ -0,0 +1,202 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.c +* Device(s) : RX72N +* Description : Definition of the exception vector table, reset vector, and user boot options. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* BSP configuration. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION); +R_BSP_UB_POR_FUNCTION(R_BSP_UB_POWER_ON_RESET_FUNCTION); + +/*********************************************************************************************************************** +* The following array fills in the option function select registers, fixed vector table, and the ID code protection +* bytes. +***********************************************************************************************************************/ +#ifdef __BIG + #define BSP_PRV_MDE_VALUE (0xfffffff8) /* big */ +#else + #define BSP_PRV_MDE_VALUE (0xffffffff) /* little */ +#endif + +#if BSP_CFG_CODE_FLASH_BANK_MODE == 0 + #define BSP_PRV_BANK_MODE_VALUE (0xffffff8f) /* dual */ +#else + #define BSP_PRV_BANK_MODE_VALUE (0xffffffff) /* linear */ +#endif + +#if BSP_CFG_CODE_FLASH_START_BANK == 0 + /* The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xffffffff) +#else + /* The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xfffffff8) +#endif + +#if defined(__CCRX__) + +#pragma address __MDEreg = 0xFE7F5D00 +#pragma address __OFS0reg = 0xFE7F5D04 +#pragma address __OFS1reg = 0xFE7F5D08 +#pragma address __TMINFreg = 0xFE7F5D10 +#pragma address __BANKSELreg = 0xFE7F5D20 +#pragma address __SPCCreg = 0xFE7F5D40 +#pragma address __TMEFreg = 0xFE7F5D48 +#pragma address __OSIS1reg = 0xFE7F5D50 +#pragma address __OSIS2reg = 0xFE7F5D54 +#pragma address __OSIS3reg = 0xFE7F5D58 +#pragma address __OSIS4reg = 0xFE7F5D5C +#pragma address __FAWreg = 0xFE7F5D64 +#pragma address __ROMCODEreg = 0xFE7F5D70 + +const uint32_t __MDEreg = (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE); +const uint32_t __OFS0reg = BSP_CFG_OFS0_REG_VALUE; +const uint32_t __OFS1reg = BSP_CFG_OFS1_REG_VALUE; +const uint32_t __TMINFreg = 0xffffffff; +const uint32_t __BANKSELreg = BSP_PRV_START_BANK_VALUE; +const uint32_t __SPCCreg = 0xffffffff; +const uint32_t __TMEFreg = BSP_CFG_TRUSTED_MODE_FUNCTION; +const uint32_t __OSIS1reg = BSP_CFG_ID_CODE_LONG_1; +const uint32_t __OSIS2reg = BSP_CFG_ID_CODE_LONG_2; +const uint32_t __OSIS3reg = BSP_CFG_ID_CODE_LONG_3; +const uint32_t __OSIS4reg = BSP_CFG_ID_CODE_LONG_4; +const uint32_t __FAWreg = BSP_CFG_FAW_REG_VALUE; +const uint32_t __ROMCODEreg = BSP_CFG_ROMCODE_REG_VALUE; + +#elif defined(__GNUC__) + +const st_ofsm_sec_ofs1_t __ofsm_sec_ofs1 __attribute__ ((section(".ofs1"))) = { + (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE), /* __MDEreg */ + BSP_CFG_OFS0_REG_VALUE, /* __OFS0reg */ + BSP_CFG_OFS1_REG_VALUE /* __OFS1reg */ +}; +const uint32_t __TMINFreg __attribute__ ((section(".ofs2"))) = 0xffffffff; +const uint32_t __BANKSELreg __attribute__ ((section(".ofs3"))) = BSP_PRV_START_BANK_VALUE; +const uint32_t __SPCCreg __attribute__ ((section(".ofs4"))) = 0xffffffff; +const uint32_t __TMEFreg __attribute__ ((section(".ofs5"))) = BSP_CFG_TRUSTED_MODE_FUNCTION; +const st_ofsm_sec_ofs6_t __ofsm_sec_ofs6 __attribute__ ((section(".ofs6"))) = { + BSP_CFG_ID_CODE_LONG_1, /* __OSIS1reg */ + BSP_CFG_ID_CODE_LONG_2, /* __OSIS2reg */ + BSP_CFG_ID_CODE_LONG_3, /* __OSIS3reg */ + BSP_CFG_ID_CODE_LONG_4 /* __OSIS4reg */ +}; +const uint32_t __FAWreg __attribute__ ((section(".ofs7"))) = BSP_CFG_FAW_REG_VALUE; +const uint32_t __ROMCODEreg __attribute__ ((section(".ofs8"))) = BSP_CFG_ROMCODE_REG_VALUE; + +#elif defined(__ICCRX__) + +#pragma public_equ = "__MDE", (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE) +#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE +#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE +#pragma public_equ = "__TMINF", 0xffffffff +#pragma public_equ = "__BANKSEL", BSP_PRV_START_BANK_VALUE +#pragma public_equ = "__SPCC", 0xffffffff +#pragma public_equ = "__TMEF", BSP_CFG_TRUSTED_MODE_FUNCTION +#pragma public_equ = "__OSIS_1", BSP_CFG_ID_CODE_LONG_1 +#pragma public_equ = "__OSIS_2", BSP_CFG_ID_CODE_LONG_2 +#pragma public_equ = "__OSIS_3", BSP_CFG_ID_CODE_LONG_3 +#pragma public_equ = "__OSIS_4", BSP_CFG_ID_CODE_LONG_4 +#pragma public_equ = "__FAW", BSP_CFG_FAW_REG_VALUE +#pragma public_equ = "__ROM_CODE", BSP_CFG_ROMCODE_REG_VALUE + +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* The following array fills in the exception vector table. +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* System configurator generates the ritble.src as interrupt & exception vector tables. */ +#else /* BSP_CFG_RTOS_USED!=4 */ + +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT void (* const Except_Vectors[])(void) = +{ + /* Offset from EXTB: Reserved area - must be all 0xFF */ + (void (*)(void))0xFFFFFFFF, /* 0x00 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x04 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x08 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x0c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x10 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x14 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x18 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x1c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x20 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x24 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x28 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x2c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x30 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x34 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x38 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x3c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x40 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x44 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x48 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x4c - Reserved */ + + /* Exception vector table */ + excep_supervisor_inst_isr, /* 0x50 Exception(Supervisor Instruction) */ + excep_access_isr, /* 0x54 Exception(Access exception) */ + undefined_interrupt_source_isr, /* 0x58 Reserved */ + excep_undefined_inst_isr, /* 0x5c Exception(Undefined Instruction) */ + undefined_interrupt_source_isr, /* 0x60 Reserved */ + excep_floating_point_isr, /* 0x64 Exception(Floating Point) */ + undefined_interrupt_source_isr, /* 0x68 Reserved */ + undefined_interrupt_source_isr, /* 0x6c Reserved */ + undefined_interrupt_source_isr, /* 0x70 Reserved */ + undefined_interrupt_source_isr, /* 0x74 Reserved */ + non_maskable_isr, /* 0x78 NMI */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +* The following array fills in the reset vector. +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT void (* const Reset_Vector[])(void) = +{ + R_BSP_POWER_ON_RESET_FUNCTION /* 0xfffffffc RESET */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h new file mode 100644 index 000000000..802a4e950 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.h +* Description : Has function prototypes for exception callback functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef VECTTBL_HEADER_INC +#define VECTTBL_HEADER_INC + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if defined(__GNUC__) +typedef struct st_ofsm_sec_ofs1 +{ + uint32_t __MDEreg; + uint32_t __OFS0reg; + uint32_t __OFS1reg; +} st_ofsm_sec_ofs1_t; + +typedef struct st_ofsm_sec_ofs6 +{ + uint32_t __OSIS1reg; + uint32_t __OSIS2reg; + uint32_t __OSIS3reg; + uint32_t __OSIS4reg; +} st_ofsm_sec_ofs6_t; +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* VECTTBL_HEADER_INC */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/platform.h new file mode 100644 index 000000000..43921b899 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/platform.h @@ -0,0 +1,224 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : platform.h +* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using +* is not listed below, please add your own or use the default 'User Board'. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.11.2011 1.00 First Release +* : 13.01.2012 1.10 Moved from having platform defined using macro definition, to having platform defined +* by choosing an include path. This makes this file simpler and cleans up the issue +* where HEW shows all header files for all platforms under 'Dependencies'. +* : 14.02.2012 1.20 Added RX210 BSP. +* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding +* locking.c and locking.h in board folders. Also, r_bsp can now be configured through +* r_bsp_config.h. +* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using +* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort +* to remove any extra files that the user would need to touch. Removed the flash_options.c +* file and put its contents in vecttbl.c. +* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT +* macro options in r_bsp_config.h. Added some extra code to handle exceptions in +* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks. +* : 09.08.2012 1.60 Added IO_LIB_ENABLE macro to r_bsp_config_reference.h. +* : 14.11.2012 1.70 Added RSKRX62G, RSKRX63T, and RSKRX111 support. +* : 28.11.2012 2.00 Updated to be compliant with v1.00 r_bsp specification. +* : 21.01.2013 2.10 Added RSKRX63T_144PIN support. +* : 10.05.2013 2.20 Added new packages and memory variants to RX210. All iodefine.h files have been updated +* to latest revisions. On reset, all MCUs will now initialize non-bonded out pins to +* reduce current draw. r_bsp_common.c and .h files were added to support functionality +* common to all BSPs. cpu.c and cpu.h files were added to all MCU groups to support +* CPU functions such as enabling/disabling interrupts, setting the IPL, and controlling +* register protection. mcu_init.c and mcu_init.h were add to all MCU groups to support +* initialization functions that are common to a MCU group such as non-bonded pin init. +* Choosing MCU endian has been removed from r_bsp_config.h and is now automatically +* set based on compiler macros. RX-C, IAR, and GCC endian macros are supported. RX210 +* now has support for choosing HOCO frequency. All r_bsp_config.h files now have macro +* for defining Vcc which is needed by some FIT modules. IRQ locks were added for all +* MCU groups. BSP_PACKAGE_PINS macro was added to mcu_info.h which defines number of pins +* for the currently chosen package. RX111 and RX210 now have the option of using the +* r_cgc_rx module for clock management based on BSP_CFG_USE_CGC_MODULE macro in +* r_bsp_config.h. +* : 31.05.2013 2.21 Added latest iodefine.h files for RX111 (v0.9a), RX630 (v1,50a), and RX63N (v1.60). Also +* added 'doc' folder to root of r_bsp. Currently the only the document in there is the +* preliminary version of the r_bsp User's Manual. For RX210, the ability to choose chip +* version C was added to its r_bsp_config.h file. +* : 01.07.2013 2.30 Removed RSPI pin setup in RSKRX111 which caused excess current draw in low power +* modes. Changed FIT_NO_PTR and FIT_NO_FUNC macros to 0x10000000 which works for all +* RX MCUs. Added ability for user to use 1 or 2 stacks for RX MCUs. Added new interrupt +* handling features which allows for interrupt callback registration. This feature allows +* all interrupts that map to the NMI vector to be used and replaces the static callback +* definitions that were in r_bsp_config.h previously. RX111 information has been updated +* according to v1.00 HW manual. This includes support for 40-pin packages. All compiler +* messages and warnings for lowsrc.c have been cleaned up. Non-existent port init has +* been moved to end of hardware_setup() to ensure user does not overwrite the settings. +* Added blank lines between clock macros in r_bsp_config.h to aid in readability. Added +* '(void *)' cast to FIT_NO_PTR to remove compiler warnings. All r_bsp.h files now include +* r_bsp_common.h which has common includes (stdint.h, stddef.h, & stdbool.h) and uses +* r_typedefs.h when C99 is not available. RX111 and RX210 MCUs have the option of using +* the r_cgc_rx module for clock management. When this is used, the clock info macros in +* mcu_info.h (e.g. BSP_ICLK_HZ) will now make calls to the r_cgc_rx module instead of +* providing static info. For debug console output, lowlvl.src was replaced by lowlvl.c +* (assembly converted to C source). +* : 10.02.2014 2.40 Added support for the RSKRX110, RPBRX111, RSKRX220, and HSBRX21AP. Made sure +* in hwsetup.c files that the PMR registers are set after the MPC registers. Replaced +* use of stdint.h, stdbool.h, and stddef.h with platform.h to remove compiler warnings. +* Removed includes for machine.h since it is compiler specific and replaced with +* platform.h. Fixed bug in resetprg.c for many boards where LOCO was not being turned off +* when it was not being used. RX100 code now uses the oscillation stabilization flags +* instead of SW delay loop. Changed size_t to unsigned long. Defined PRC2 in register +* protection section for RX111. Fixed bug in non-existent pin setup for RX111. No +* platform is chosen by default (used to be the RSKRX111). This makes it easier to +* understand the problem when you build a new project and have not selected your platform. +* : 24.03.2014 2.50 Added support for the RSKRX64M. +* : 16.06.2014 2.60 Added version control for r_bsp_config.h Two user callback functions may now be +* configured allowing callbacks from PowerON_Reset_PC() for warm start detection. +* Stdio charget() and charput() functions may now be redirected to user defined functions. +* Added support for RSKRX631 and RDKRX631. +* : 05.08.2014 2.70 Added support for RSKRX113. +* : 29.09.2014 2.80 Added support for RSKRX71M. +* : 22.12.2014 2.90 Added support for RSKRX231. +* : 30.09.2015 3.00 Added support for RSSKRX23T and RSKRX23T. +* : 30.09.2015 3.01 Fix for RSKRX231 and RSKRX23T(RSSKRX23T). +* : 01.12.2015 3.10 Added support for RSKRX130. +* : 01.02.2016 3.20 Added support for RSKRX24T. +* : 29.02.2016 3.30 Added support for RSKRX230. +* : 01.10.2016 3.40 Added support for RSKRX65N. +* : 22.08.2016 3.50 Added support for RSKRX24U. +* : 15.05.2017 3.60 Added support for RSKRX65N-2MB. +* Added support for GENERIC_RX65N. +* Added support for RSKRX130-512KB. +* : 01.11.2017 3.70 Added support for GENERIC_RX130. +* Added support for GENERIC_RX110. +* Added support for GENERIC_RX111. +* Added support for GENERIC_RX113. +* Added support for GENERIC_RX230. +* Added support for GENERIC_RX231. +* Added support for GENERIC_RX23T. +* Added support for GENERIC_RX24T. +* Added support for GENERIC_RX24U. +* Added support for GENERIC_RX64M. +* Added support for GENERIC_RX71M. +* Added support for ENVISIONRX65N. +* : 01.11.2017 3.71 Corrected typo in Rev3.70 BSP. +* : 01.07.2018 3.80 Added support for TARGETBOARDRX65N. +* Added support for TARGETBOARDRX231. +* Added support for TARGETBOARDRX130. +* : 27.07.2018 3.90 Added support for GENERIC_RX66T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSKRX64M, RSKRX65N, RSKRX65N_2MB, TARGETBOARDRX65N, ENVISIONRX65N, RSKRX71M, +* RSKRX230, RSKRX231, TARGETBOARDRX231, RSKRX110, RSKRX111, RPBRX111, RSKRX113, +* RSKRX130, RSKRX130_512KB, and TARGETBOARDRX130 +* : 31.10.2018 4.00 Added support for GENERIC_RX72T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSSKRX23T, RSKRX23T, RSKRX24T, and RSKRX24U +* : 28.02.2019 5.00 Deleted the below board folders. +* - RSKRX610, RSKRX62N, RSKRX62T, RSKRX62G, RDKRX62N, RSKRX630, RSKRX631, RSKRX63T_64PIN, +* RSKRX63T_144PIN, RDKRX63N, RDKRX631, RSKRX210, HSBRX21AP and RSKRX220 +* : 29.03.2019 5.10 Added support for GENERIC_RX23W. +* : 08.04.2019 5.20 Added support for GENERIC_RX72M. +* : 26.07.2019 5.30 Added support for GENERIC_RX13T. +* : 31.07.2019 5.40 Added support for GENERIC_RX23E-A. +* : 08.10.2019 5.50 Added support for GENERIC_RX72N, and GENERIC_RX66N. +* Deleted the board folders of RSKRX63N. +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef PLATFORM_H +#define PLATFORM_H + +/*********************************************************************************************************************** +DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING. +***********************************************************************************************************************/ +/* GENERIC_RX64M */ +//#include "./board/generic_rx64m/r_bsp.h" + +/* GENERIC_RX65N */ +//#include "./board/generic_rx65n/r_bsp.h" + +/* GENERIC_RX66N */ +//#include "./board/generic_rx66n/r_bsp.h" + +/* GENERIC_RX66T */ +//#include "./board/generic_rx66t/r_bsp.h" + +/* GENERIC_RX71M */ +//#include "./board/generic_rx71m/r_bsp.h" + +/* GENERIC_RX72M */ +//#include "./board/generic_rx72m/r_bsp.h" + +/* GENERIC_RX72N */ +#include "./board/generic_rx72n/r_bsp.h" + +/* GENERIC_RX72T */ +//#include "./board/generic_rx72t/r_bsp.h" + +/* GENERIC_RX230 */ +//#include "./board/generic_rx230/r_bsp.h" + +/* GENERIC_RX231 */ +//#include "./board/generic_rx231/r_bsp.h" + +/* GENERIC_RX23E-A */ +//#include "./board/generic_rx23e-a/r_bsp.h" + +/* GENERIC_RX23T */ +//#include "./board/generic_rx23t/r_bsp.h" + +/* GENERIC_RX23W */ +//#include "./board/generic_rx23w/r_bsp.h" + +/* GENERIC_RX24T */ +//#include "./board/generic_rx24t/r_bsp.h" + +/* GENERIC_RX24U */ +//#include "./board/generic_rx24u/r_bsp.h" + +/* GENERIC_RX111 */ +//#include "./board/generic_rx111/r_bsp.h" + +/* GENERIC_RX110 */ +//#include "./board/generic_rx110/r_bsp.h" + +/* GENERIC_RX113 */ +//#include "./board/generic_rx113/r_bsp.h" + +/* GENERIC_RX130 */ +//#include "./board/generic_rx130/r_bsp.h" + +/* GENERIC_RX13T */ +//#include "./board/generic_rx13t/r_bsp.h" + +/* User Board - Define your own board here. */ +//#include "./board/user/r_bsp.h" + +/*********************************************************************************************************************** +MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT +***********************************************************************************************************************/ +#ifndef PLATFORM_DEFINED +#error "Error - No platform defined in platform.h!" +#endif + +#endif /* PLATFORM_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/readme.txt new file mode 100644 index 000000000..25aa74e4c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_bsp/readme.txt @@ -0,0 +1,57 @@ +r_bsp Package +============= + +Overview +-------- +The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU +information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder contains files +that are common to a MCU group. These files provide functionality such as easy register access, CPU functions, +and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board +and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help +configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each +supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which +board they are using by uncommenting the include path that applies to their board. For example, if you are using the +RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add +their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a +reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it +to r_bsp_config.h, and use the options inside the file to configure the BSP for their project. + + +Features +-------- +* Provides foundation to build code on top of. +* Provides MCU startup code. +* Provides SFR access through iodefine.h +* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware. +* Easily configure BSP through r_bsp_config.h. +* Choose MCU easily by inputting part number details in r_bsp_config.h. +* Provides callbacks for MCU exceptions and the bus error interrupt. +* Supports initializing non-bonded out pins to reduce power +* Provides API to control CPU functions such as setting the IPL, enabling/disabling interrupts, and controlling + register protection + + + +File Structure +-------------- +r_bsp +| platform.h +| readme.txt +| ++---board +| +---generic_rx111 +| | : +| : +| \---user +| ++---doc +| +---en +| r01an1685ej{VERSION_NUMBER}-rx-bsp.pdf +| +---ja +| r01an1685jj{VERSION_NUMBER}-rx-bsp.pdf +| +\---mcu + +---all + +---rx111 + | : + : \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/r_byteq_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/r_byteq_if.h new file mode 100644 index 000000000..1bd93830d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/r_byteq_if.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_if.h +* Description : Functions for using byte queues/circular buffers +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 01.22.2015 1.30 Updated version to 1.30 for RX71M release +* : 04.04.2015 1.40 Updated version to 1.40 for RX231 release +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Updated version to 1.60 for correspondence to RX Family +* : 01.06.2018 1.70 Updated version to 1.70 +* : 03.12.2018 1.71 Updated version to 1.71 for update of xml file. +* : 07.02.2019 1.80 Updated version to 1.80. +***********************************************************************************************************************/ + +#ifndef BYTEQ_IF_H +#define BYTEQ_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Version Number of API. */ +#define BYTEQ_VERSION_MAJOR (1) +#define BYTEQ_VERSION_MINOR (80) + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef enum e_byteq_err // BYTEQ API error codes +{ + BYTEQ_SUCCESS = 0, + BYTEQ_ERR_NULL_PTR, // received null ptr; missing required argument + BYTEQ_ERR_INVALID_ARG, // argument is not valid for parameter + BYTEQ_ERR_MALLOC_FAIL, // can't allocate memory for ctrl block; increase heap + BYTEQ_ERR_NO_MORE_CTRL_BLKS, // no more control blocks, increase BYTEQ_MAX_CTRL_BLKS + BYTEQ_ERR_QUEUE_FULL, // queue full; cannot add another byte + BYTEQ_ERR_QUEUE_EMPTY // queue empty; no byte to fetch +} byteq_err_t; + + +/* BYTE QUEUE HANDLE */ + +typedef struct st_byteq_ctrl * byteq_hdl_t; + + +/***************************************************************************** +Public Functions +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl); + +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte); + +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte); + +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +uint32_t R_BYTEQ_GetVersion(void); + + +#endif /* BYTEQ_IF_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/readme.txt new file mode 100644 index 000000000..1173711e1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/readme.txt @@ -0,0 +1,48 @@ + +r_byteq +======= + +Overview +-------------------------------------------------------------------------------- +The r_byteq module is a collection of circular buffer routines for byte data. +The application passes a buffer to be used as a circular buffer to the Open() +function which assigns a queue control block to it to handle indexing. The +Open() function returns a handle which is then used as a queue/buffer id for all +other API functions. These functions include routines for adding and removing +data from a queue, inspecting the amount of data in a queue, and the ability to +flush a queue. + +The queue control blocks can be allocated at compile time or dynamically at run +time. A configuration option for this exists in "r_config\r_byteq_config.h". +An original copy of the configuration file is stored in "r_byteq\ref\ +r_byteq_config_reference.h". + + +Features +-------- +* Statically or dynamically allocated queue control blocks. +* Number of queues limited only by the amount of RAM available on the mcu. + +File Structure +-------------- +r_byteq +| readme.txt +| r_byteq_if.h +| ++---doc +| +---en +| | r01an1683ej{VERSION_NUMBER}-rx.pdf +| | +| +---ja +| r01an1683jj{VERSION_NUMBER}-rx.pdf +| ++---ref +| r_byteq_config_reference.h +| ++---src + r_byteq.c + r_byteq_private.h + +r_config + r_byteq_config.h + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h new file mode 100644 index 000000000..40675c419 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + + +#endif /* BYTEQ_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/src/r_byteq.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/src/r_byteq.c new file mode 100644 index 000000000..816a88be8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/src/r_byteq.c @@ -0,0 +1,422 @@ +/***************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +******************************************************************************/ +/***************************************************************************** +* File Name : r_byteq.c +* Description : Functions for using byte queues/circular buffers. +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Fixed the initial setting process in the R_LONGQ_Open function. +* Fixed a program according to the Renesas coding rules. +* : 01.06.2018 1.70 Added the comment to while statement. +* : 07.02.2019 1.80 Deleted the inline expansion of the R_BYTEQ_GetVersion function. +******************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +/* Used functions of malloc() and the free() */ +#include + +/* Used the common type */ +#include "platform.h" + +/* Defines for BYTEQ support */ +#include "r_byteq_private.h" +#include "r_byteq_if.h" +#include "r_byteq_config.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK ALLOCATIONS */ + +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) +static byteq_ctrl_t g_qcb[BYTEQ_CFG_MAX_CTRL_BLKS]; +#endif + + +/***************************************************************************** +* Function Name: R_BYTEQ_Open +* Description : Allocates or assigns a queue control block for the buffer +* pointed to by p_buf (see BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS in +* config.h). Initializes the queue to an empty state and +* provides a Handle to its control structure in p_hdl which is +* then used as a queue ID for the other API functions. +* Arguments : p_buf - +* Pointer to byte buffer. +* size - +* Buffer size in bytes. +* p_hdl - +* Pointer to a handle for queue (value set here) +* Return Value : SCI_SUCCESS - +* queue initialized successfully +* BYTEQ_ERR_NULL_PTR +* received null ptr; missing required argument +* BYTEQ_ERR_INVALID_ARG +* argument is not valid for parameter +* BYTEQ_ERR_MALLOC_FAIL +* can't allocate memory for ctrl block; increase heap +* BYTEQ_ERR_NO_MORE_CTRL_BLKS +* no more control blocks, increase BYTEQ_CFG_MAX_CTRL_BLKS +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl) +{ + byteq_ctrl_t *p_qcb = 0; +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) + uint32_t i; + static bool qcb_init = false; +#endif + + /* CHECK ARGUMENTS */ + +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == p_hdl) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } + if (NULL == p_buf) + { + return BYTEQ_ERR_NULL_PTR; // return if no buffer pointer + } + if (size < 2) + { + return BYTEQ_ERR_INVALID_ARG; // return insufficient buffer size + } +#endif + + /* GET QUEUE CONTROL BLOCK */ + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + + /* allocate memory for a QCB */ + p_qcb = (byteq_ctrl_t *)malloc(sizeof(byteq_ctrl_t)); + if (NULL == p_qcb) + { + return BYTEQ_ERR_MALLOC_FAIL; + } +#else + /* if first Open call, mark all QCBs as being available */ + if (false == qcb_init) + { + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + g_qcb[i].buffer = NULL; + } + qcb_init = true; + } + + /* locate first available QCB */ + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + if (NULL == g_qcb[i].buffer) + { + p_qcb = &g_qcb[i]; + break; + } + } + + /* return error if none available */ + if (BYTEQ_CFG_MAX_CTRL_BLKS == i) + { + return BYTEQ_ERR_NO_MORE_CTRL_BLKS; + } +#endif + + + /* INITIALIZE QCB FIELDS */ + + p_qcb->buffer = p_buf; + p_qcb->size = size; + p_qcb->count = 0; + p_qcb->in_index = 0; + p_qcb->out_index = 0; + + + /* SET HANDLE */ + + *p_hdl = p_qcb; + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Put +* Description : This function adds a byte of data to the queue. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* byte - +* Byte to add to queue. +* Return Value : BYTEQ_SUCCESS - +* Successful; byte sent or queued for transmit +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_QUEUE_FULL - +* Queue full; cannot add byte to queue. +******************************************************************************/ +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } +#endif + + if (hdl->count >= hdl->size) + { + return BYTEQ_ERR_QUEUE_FULL; // return if queue is full + } + + /* load byte into queue */ + hdl->buffer[hdl->in_index++] = byte; // add byte + if (hdl->in_index >= hdl->size) // adjust index + { + hdl->in_index = 0; + } + hdl->count++; // adjust count + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Get +* Description : This function removes a byte of data from the queue. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* p_byte - +* Pointer to load byte to. +* Return Value : BYTEQ_SUCCESS - +* Successful; byte sent or queued for transmit +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_byte is NULL +* BYTEQ_ERR_QUEUE_EMPTY - +* Queue empty; no data available to fetch +******************************************************************************/ +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } + if (NULL == p_byte) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + if (0 == hdl->count) + { + return BYTEQ_ERR_QUEUE_EMPTY; // return if queue empty + } + + *p_byte = hdl->buffer[hdl->out_index++]; // get byte + if (hdl->out_index >= hdl->size) // adjust index + { + hdl->out_index = 0; + } + hdl->count--; // adjust count + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Flush +* Description : This function resets a queue to an empty state. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* Return Value : BYTEQ_SUCCESS - +* Successful; queue is reset to en ampty state +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + + /* RESET QUEUE */ + + hdl->in_index = 0; + hdl->out_index = 0; + hdl->count = 0; + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Used +* Description : This function provides the number of data bytes in the queue. +* Arguments : hdl - +* Handle for queue. +* p_cnt - +* Pointer to load queue data count to. +* Return Value : BYTEQ_SUCCESS - +* Successful; *p_cnt loaded with number of bytes in queue +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_cnt is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + *p_cnt = hdl->count; + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Unused +* Description : This function provides the number of data bytes available +* for storage in the queue. +* Arguments : hdl - +* Handle for queue. +* p_cnt - +* Pointer to load queue unused byte count to. +* Return Value : BYTEQ_SUCCESS - +* Successful; *p_cnt loaded with number of bytes available in +* queue +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_cnt is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + *p_cnt = (uint16_t) (hdl->size - hdl->count); + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Close +* Description : If the control block associated with this Handle was allocated +* dynamically at run time (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS set to 1 +* in config.h), then that memory is free()d by this function. If +* the control block was statically allocated at compile time +* (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS set to 0 in config.h), then this +* function marks the control block as available for use by another +* buffer. Nothing is done to the contents of the buffer referenced +* by this Handle. +* Arguments : hdl - +* handle for queue +* Return Value : BYTEQ_SUCCESS - +* Successful; control block freed +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL. +******************************************************************************/ +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + free(hdl); // free QCB memory +#else + hdl->buffer = NULL; // mark QCB as free +#endif + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_GetVersion +* Description : Returns the version of this module. The version number is +* encoded such that the top two bytes are the major version +* number and the bottom two bytes are the minor version number. +* Arguments : none +* Return Value : version number +******************************************************************************/ +uint32_t R_BYTEQ_GetVersion(void) +{ + + uint32_t const version = (BYTEQ_VERSION_MAJOR << 16) | BYTEQ_VERSION_MINOR; + return version; +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/src/r_byteq_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/src/r_byteq_private.h new file mode 100644 index 000000000..8f14acced --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_byteq/src/r_byteq_private.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_private.h +* Description : Definitions internal to byte queue module +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.0 Initial Release +* : 30.09.2015 1.50 Added dependency to BSP +***********************************************************************************************************************/ + +#ifndef BYTEQ_PRIVATE_H +#define BYTEQ_PRIVATE_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK */ + +typedef struct st_byteq_ctrl // Byte Queue Control Block (for handle) +{ + uint8_t *buffer; // pointer to buffer + uint16_t size; // buffer size + uint16_t count; // number data bytes in queue + uint16_t in_index; // index used by Put function to add data + uint16_t out_index; // index used by Get function to remove data +} byteq_ctrl_t; + + +#endif /* BYTEQ_PRIVATE_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_config.h new file mode 100644 index 000000000..32438d2ef --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_config.h @@ -0,0 +1,774 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX72N +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release. +***********************************************************************************************************************/ +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/* Include for various workarounds. */ +#include "smc_workaround.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX72N. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 57 2N N D D BD + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FC = 0x0 = LFQFP/176/0.50 + BG = 0x1 = LFBGA/176/0.80 + BD = 0x2 = LFBGA/224/0.80 + FB = 0x3 = LFQFP/144/0.50 + LK = 0x4 = TFLGA/145/0.50 + FP = 0x5 = LFQFP/100/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x3) /* Generated value. Do not edit this manually */ + +/* Whether Encryption is included or not. + Character(s) = Value for macro = Description + D = 0xD = Encryption module not included + H = 0x11 = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0x11) /* Generated value. Do not edit this manually */ + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + D = 0xD = 2MB/1MB/32KB + N = 0x17 = 4MB/1MB/32KB +NOTE: The RAM areas are not contiguous.It is separated by 512 KB each. +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x17) /* Generated value. Do not edit this manually */ + +/* Group name. + Character(s) = Value for macro = Description + 2N = 0x0 = RX72N Group +*/ +#define BSP_CFG_MCU_PART_GROUP (0x0) /* Generated value. Do not edit this manually */ + +/* Series name. + Character(s) = Value for macro = Description + 57 = 0x0 = RX700 Series +*/ +#define BSP_CFG_MCU_PART_SERIES (0x0) /* Generated value. Do not edit this manually */ + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) /* Generated value. Do not edit this manually */ + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (0) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x0) +#endif + +/* Interrupt Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x0) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit (default) +*/ +#define BSP_CFG_CLOCK_SOURCE (4) /* Generated value. Do not edit this manually */ + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator (default) + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (0) /* Generated value. Do not edit this manually */ + +/* USB Clock source select (UPLLSEL). Choose which clock source to input to the USB circuit. + 0 = System Clock (PLL Circuit/No division) (This is not available.) + 1 = USB PLL Circuit (This is not available.) + 2 = PLL Circuit (UDIVCLK) (default) + 3 = PPLL Circuit (PPLLDIVCLK) +*/ +#define BSP_CFG_USB_CLOCK_SOURCE (2) /* Generated value. Do not edit this manually */ + +/* Ethernet-PHY clock source (OUTCKSEL). Choose which clock source to input to the Ethernet PHY LSI. + Available clock sources: + 0 = PLL circuit + 1 = PPLL circuit (default) + 2 = Ethernet-PHY not use +*/ +#define BSP_CFG_PHY_CLOCK_SOURCE (1) /* Generated value. Do not edit this manually */ + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 6 = PPLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE (1) /* Generated value. Do not edit this manually */ + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE (0) /* Generated value. Do not edit this manually */ + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP (0) /* Generated value. Do not edit this manually */ + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, BCLK is 80MHz, + USB Clock is 48MHz, ESC Clock is 100MHz, Ether-Phy Clock is 25MHz then the settings would be: + + BSP_CFG_XTAL_HZ = 24000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz) + BSP_CFG_PPLL_DIV = 3 (divide by 3) + BSP_CFG_PPLL_MUL = 25.0 (8MHz x 25.0 = 200MHz) + BSP_CFG_PPLCK_DIV = 2 (divide by 2) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 240MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_BCK_DIV = 3 : External Bus Clock (BCK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 80MHz + BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (16000000) /* Generated value. Do not edit this manually */ + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#define BSP_CFG_HOCO_FREQUENCY (2) /* Generated value. Do not edit this manually */ + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC (1) /* Generated value. Do not edit this manually */ + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (1) /* Generated value. Do not edit this manually */ + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL (12.0) /* Generated value. Do not edit this manually */ + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (1) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (2) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (4) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (4) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (4) /* Generated value. Do not edit this manually */ + +/* External Bus Clock Divider (BCLK). + Available divisors = /1 (no division), /2, /3, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_BCK_DIV (3) /* Generated value. Do not edit this manually */ + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (4) /* Generated value. Do not edit this manually */ + +/* USB Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_UCK_DIV (2) /* Generated value. Do not edit this manually */ + +/* PPLL Input Frequency Division Ratio Select (PPLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PPLL_DIV (1) /* Generated value. Do not edit this manually */ + +/* PPLL Frequency Multiplication Factor Select (PPLSTC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PPLL_MUL (10.0) /* Generated value. Do not edit this manually */ + +/* PPLL Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_PPLCK_DIV (2) /* Generated value. Do not edit this manually */ + +/* Configure BCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency +*/ +#define BSP_CFG_BCLK_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* Configure SDCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency + NOTE: The definition is invalid. +*/ +#define BSP_CFG_SDCLK_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV (0) /* Generated value. Do not edit this manually */ + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) /* Generated value. Do not edit this manually */ + +/* Sub-Clock Oscillator Wait Time (SOSCWTCR). + The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation + by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384 + (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h). +*/ +#define BSP_CFG_SOSC_WAIT_TIME (0x21) /* Generated value. Do not edit this manually */ + +/* ROM Cache Enable Register (ROMCE). + 0 = ROM cache operation disabled. + 1 = ROM cache operation enabled. +*/ +#define BSP_CFG_ROM_CACHE_ENABLE (1) + +/* Configure non-cacheable area 0 of the ROM cache function. + 0 = Non-cacheable area 0 settings disabled. + 1 = Non-cacheable area 0 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ENABLE (0) + +/* Specifies the start address of non-cacheable area 0. + Selects the start address of non-cacheable area 0. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 0. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of IF cache disabled. + 1 = Non-cacheable area 0 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of OA cache disabled. + 1 = Non-cacheable area 0 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of DM cache disabled. + 1 = Non-cacheable area 0 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE (1) + +/* Configure non-cacheable area 1 of the ROM cache function. + 0 = Non-cacheable area 1 settings disabled. + 1 = Non-cacheable area 1 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ENABLE (0) + +/* Specifies the start address of non-cacheable area 1. + Selects the start address of non-cacheable area 1. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 1. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of IF cache disabled. + 1 = Non-cacheable area 1 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of OA cache disabled. + 1 = Non-cacheable area 1 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of DM cache disabled. + 1 = Non-cacheable area 1 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE (1) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 78 and 79 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEFF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b26] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area + - 1: FFFF E000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory + when the flash programmer is used during off-board programming. + ROMCODE - ROM Code Protection Register + b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1). + 0000 0001h: ROM code protection enabled (ROM code protection 2). + Other than above: ROM code protection disabled. + Note: The ROMCODE register should be set in 32-bit units. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. +*/ +#if !defined(BSP_CFG_RTOS_USED) || (BSP_CFG_RTOS_USED == 0) +#if defined(BSP_CFG_RTOS_USED) +#undef BSP_CFG_RTOS_USED +#endif +#define BSP_CFG_RTOS_USED (0) /* Generated value. Do not edit this manually */ +#endif +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC + graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and + display list data read). + The default priority order in bsp is below + GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC. + Priority can be changed with this macro. + + Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */ +#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */ +#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */ +#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */ +#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */ + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) /* Generated value. Do not edit this manually */ + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (1) /* Generated value. Do not edit this manually */ + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (0) +#define BSP_CFG_SWINT_UNIT2_ENABLE (1) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_config_readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_config_readme.txt new file mode 100644 index 000000000..6a9002cf4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_config_readme.txt @@ -0,0 +1,12 @@ +FIT r_config folder +------------------- +The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration +files. Putting the files in one place makes them easy to find, backup, and put in a version control system. + +FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example, +the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are +provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the +user should copy this reference configuration file to this folder and remove '_reference' from the filename +(r_bsp_config_reference.h is renamed to r_bsp_config.h). For the r_bsp the reference configuration file can be found in +the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file +can be found in the 'ref' folder of the FIT Module. diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_interrupt_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_interrupt_config.h new file mode 100644 index 000000000..189b6ef5d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_bsp_interrupt_config.h @@ -0,0 +1,222 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupt_config.h +* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 31.05.2019 1.00 First Release +***********************************************************************************************************************/ +#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE +#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you + * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you + * would do the following: + * + * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 + */ + +/* Interrupt B Sources. + * -Valid vector numbers are 128-207. + * -There are more vector slots for B sources than actual B sources. By default none of the CAN2 interrupts are + * mapped. + * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default. + * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be + * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0' + * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots. + */ +#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128 +#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175 +#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 192 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 193 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 194 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 195 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 196 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 197 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 198 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 199 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 200 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 201 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 202 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 203 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 204 + +/* Interrupt A Sources. + * -Valid vector numbers are 208-255. + * -There are more A sources than A vector slots. By default none of the GPTW interrupts and the ESC interrupts are + * mapped. + * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default. + */ +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3 +#define BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS 251 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I 252 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I 253 + +#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_byteq_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_byteq_config.h new file mode 100644 index 000000000..512a28eb2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_byteq_config.h @@ -0,0 +1,62 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + + +#endif /* BYTEQ_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_dtc_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_dtc_rx_config.h new file mode 100644 index 000000000..c0ac30518 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_dtc_rx_config.h @@ -0,0 +1,97 @@ +/* Generated configuration header file - do not edit */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_config.h +* Description : Configures the DTC drivers +******************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.01.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Added #define DTC_CFG_USE_SEQUENCE_TRANSFER. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +*******************************************************************************/ +#ifndef DTC_RX_CONFIG_H +#define DTC_RX_CONFIG_H + +#define DTC_DISABLE (0) +#define DTC_ENABLE (1) +/* + * SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + * 0 : Compiles out parameter checking. + * 1 : Includes parameter checking. + * Default value is set to BSP_CFG_PARAM_CHECKING_ENABLE to + * re-use the system default setting. +*/ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* + * SPECIFY WHETHER THE DTCER REGISTERS WILL BE CLEARED IN R_DTC_OPEN() + * DTC_DISABLE : Do nothing. + * DTC_ENABLE : Clear all DTCER registers in R_DTC_Open(). +*/ +#define DTC_CFG_DISABLE_ALL_ACT_SOURCE (DTC_ENABLE) + +/* + * SPECIFY WHICH ADDRESS MODE IS SUPPORTED BY DTC + * DTC_DISABLE : Select the Full address mode. + * DTC_ENABLE : Select the Short address mode. +*/ +#define DTC_CFG_SHORT_ADDRESS_MODE (DTC_DISABLE) + +/* + * SPECIFY WHETHER THE TRANSFER DATA READ SKIP IS ENABLED + * DTC_DISABLE : Disable Transfer Data Read Skip. + * DTC_ENABLE : Enable Transfer Data Read Skip. +*/ +#define DTC_CFG_TRANSFER_DATA_READ_SKIP_EN (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE DMAC FIT MODULE IS USED WITH DTC FIT MODULE + * DTC_DISABLE : DMAC FIT module is not used with DTC FIT module. + * DTC_ENABLE : DMAC FIT module is used with DTC FIT module. +*/ +#define DTC_CFG_USE_DMAC_FIT_MODULE (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE SEQUENCE TRANSFER IS USED + * Also, set DTC_DISABLE to DTC_CFG_SHORT_ADDRESS_MODE. + * DTC_DISABLE : Not use sequence transfer. + * DTC_ENABLE : Use sequence transfer. +*/ +#define DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_ENABLE) + + +#endif /* DTC_RX_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_gpio_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_gpio_rx_config.h new file mode 100644 index 000000000..6966431d9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_gpio_rx_config.h @@ -0,0 +1,47 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_sci_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_sci_rx_config.h new file mode 100644 index 000000000..dd172ccf9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_config/r_sci_rx_config.h @@ -0,0 +1,199 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (1) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * RX MCU supported channels + * + * CH# 110 111 113 130 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N RX23E-A + * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------- + * CH0 X Xa X X X X Xn X X X + * CH1 X X* X* Xu X X Xu Xu Xu X X Xs X X X X X X X Xu + * CH2 X X X Xu X X X + * CH3 X X Xs X X X + * CH4 X X Xn X X X + * CH5 X X X X X Xu X X X X X X X X X X X X X X + * CH6 X X X X X X X X Xn X X Xu X X X + * CH7 Xu Xu Xn X X X + * CH8 X Xa X X X X X X Xu X X X + * CH9 X Xa X X X Xs X X X X X + * CH10 X X X X + * CH11 X Xs X X X X X + * CH12 X X X X X X X X Xs X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (0) +#define SCI_CFG_CH1_INCLUDED (0) +#define SCI_CFG_CH2_INCLUDED (1) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (0) +#define SCI_CFG_CH6_INCLUDED (0) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (0) +#define SCI_CFG_CH9_INCLUDED (1) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (1) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY) 1 lowest, 15 highest */ + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj and SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +#endif /* SCI_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h new file mode 100644 index 000000000..5dee62a9f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h @@ -0,0 +1,297 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_if.h +* Description : Functions for DTC driver +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Moved struct dtc_transfer_data_cfg_t to r_dtc_rx_target_if.h +* : Added include pass of target mcu interface header file. +* : Added R_DTC_CreateSeq() function. +* : 31.01.2017 2.06 Modified r_dtc_rx.c. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 18.06.2019 3.01 Modified r_dtc_rx_private.h. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. + : 12.11.2019 3.21 Removed definitions for MTU5 in DTC activation interrupt source for RX23W. +* : 25.11.2019 3.30 Added support for RX13T. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +* : 31.03.2020 3.50 Added support for RX23E-A. +*******************************************************************************/ +#ifndef DTC_RX_IF_H +#define DTC_RX_IF_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Configuration for this package. */ +#include "r_dtc_rx_config.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define DTC_VERSION_MAJOR (3) +#define DTC_VERSION_MINOR (50) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +/* Configurable options for DTC Transfer mode */ +typedef enum e_dtc_transfer_mode +{ + DTC_TRANSFER_MODE_NORMAL = (0), /* = (0 << 6): Normal mode */ + DTC_TRANSFER_MODE_REPEAT = (1 << 6), /* Repeat mode */ + DTC_TRANSFER_MODE_BLOCK = (2 << 6) /* Block mode */ +} dtc_transfer_mode_t; + +/* Configurable options for DTC Data transfer size */ +typedef enum e_dtc_data_size +{ + DTC_DATA_SIZE_BYTE = (0), /* = (0 << 4): 8-bit (byte) data */ + DTC_DATA_SIZE_WORD = (1 << 4), /* 16-bit (word) data */ + DTC_DATA_SIZE_LWORD = (2 << 4) /* 32-bit (long word) data */ +} dtc_data_size_t; + +/* Configurable options for Source address addressing mode */ +typedef enum e_dtc_src_addr_mode +{ + DTC_SRC_ADDR_FIXED = (0), /* = (0 << 2): Source address is fixed. */ + DTC_SRC_ADDR_INCR = (2 << 2), /* Source address is incremented after each transfer. */ + DTC_SRC_ADDR_DECR = (3 << 2) /* Source address is decremented after each transfer. */ +} dtc_src_addr_mode_t; + +/* Configurable options for Chain transfer */ +typedef enum e_dtc_chain_transfer +{ + DTC_CHAIN_TRANSFER_DISABLE = (0), /* Disable Chain transfer. */ + DTC_CHAIN_TRANSFER_ENABLE = (1 << 7) /* Enable Chain transfer. */ +} dtc_chain_transfer_t; + +/* Configurable options for how chain transfer is performed. */ +typedef enum e_dtc_chain_transfer_mode +{ + DTC_CHAIN_TRANSFER_CONTINUOUSLY = (0), /* = (0 << 6): Chain transfer is performed continuously. */ + DTC_CHAIN_TRANSFER_NORMAL = (1 << 6) /* Chain transfer is performed only when the counter is changed to 0 or CRAH. */ +} dtc_chain_transfer_mode_t; + +/* Configurable options for Interrupt */ +typedef enum e_dtc_interrupt +{ + DTC_INTERRUPT_AFTER_ALL_COMPLETE = (0), /* Interrupt is generated when specified data transfer is completed. */ + DTC_INTERRUPT_PER_SINGLE_TRANSFER = (1 << 5) /* Interrupt is generated when each transfer time is completed. */ +} dtc_interrupt_t; + +/* Configurable options for Side to be repeat or block */ +typedef enum e_dtc_repeat_block_side +{ + DTC_REPEAT_BLOCK_DESTINATION = (0), /* = (0 << 4): Destination is repeat or block area. */ + DTC_REPEAT_BLOCK_SOURCE = (1 << 4) /* Source is repeat or block area. */ +} dtc_repeat_block_side_t; + +/* Configurable options for Destination address addressing mode */ +typedef enum e_dtc_dest_addr_mode +{ + DTC_DES_ADDR_FIXED = (1 << 2), /* Destination address is fixed. */ + DTC_DES_ADDR_INCR = (2 << 2), /* Destination address is incremented after each transfer. */ + DTC_DES_ADDR_DECR = (3 << 2) /* Destination address is decremented after each transfer. */ +} dtc_dest_addr_mode_t; + +/* Configurable options for Write-back Disable */ +typedef enum e_dtc_write_back +{ + DTC_WRITEBACK_ENABLE = (0), + DTC_WRITEBACK_DISABLE = (1) +} dtc_write_back_t; + +/* Configurable options for Sequence Transfer End */ +typedef enum e_dtc_sequence_end +{ + DTC_SEQUENCE_TRANSFER_CONTINUE = (0), + DTC_SEQUENCE_TRANSFER_END = (1) +} dtc_sequence_end_t; + +/* Configurable options for Index Table Reference */ +typedef enum e_dtc_refer_index_table +{ + DTC_REFER_INDEX_TABLE_DISABLE = (0), + DTC_REFER_INDEX_TABLE_ENABLE = (1 << 1) +} dtc_refer_index_table_t; + +/* Configurable options for Displacement Addition */ +typedef enum e_dtc_disp_add +{ + DTC_SRC_ADDR_DISP_ADD_DISABLE = (0), + DTC_SRC_ADDR_DISP_ADD_ENABLE = (1) +} dtc_disp_add_t; + +/* Enumerate list that can be selected as DTC activation source + * enum enum_dtce: is included from iodefine.h + */ +typedef enum enum_dtce dtc_activation_source_t; + +typedef enum e_dtc_command { + DTC_CMD_DTC_START, /* DTC will can accept activation requests. */ + DTC_CMD_DTC_STOP, /* DTC will not accept new activation request. */ + DTC_CMD_ACT_SRC_ENABLE, /* Enable an activation source specified by vector number. */ + DTC_CMD_ACT_SRC_DISABLE, /* Disable an activation source specified by vector number. */ + DTC_CMD_DATA_READ_SKIP_ENABLE, /* Enable Transfer Data Read Skip. */ + DTC_CMD_DATA_READ_SKIP_DISABLE, /* Disable Transfer Data Read Skip. */ + DTC_CMD_STATUS_GET, /* Get the current status of DTC. */ + DTC_CMD_CHAIN_TRANSFER_ABORT, /* Abort the current Chain transfer process. */ + DTC_CMD_SEQUENCE_TRANSFER_ENABLE, /* Sequence transfer is enabled. */ + DTC_CMD_SEQUENCE_TRANSFER_DISABLE, /* Sequence transfer is disabled. */ + DTC_CMD_SEQUENCE_TRANSFER_ABORT, /* Abort the sequence transfer. */ + DTC_CMD_CHANGING_DATA_FORCIBLY_SET /* Changing data forcibly set by R_DTC_Create(). */ +} dtc_command_t; + +typedef enum e_dtc_err /* DTC API error codes */ +{ + DTC_SUCCESS_DMAC_BUSY = 0, /* One or some DMAC resources are locked by another process. */ + DTC_SUCCESS, + DTC_ERR_OPENED, /* DTC was initialized already. */ + DTC_ERR_NOT_OPEN, /* DTC module is not initialized yet. */ + DTC_ERR_INVALID_ARG, /* Arguments are invalid. */ + DTC_ERR_INVALID_COMMAND, /* Command parameters are invalid. Or, forced data change failed. */ + DTC_ERR_NULL_PTR, /* Argument pointers are NULL. */ + DTC_ERR_BUSY, /* The DTC resources are locked by another process. */ + DTC_ERR_ACT /* Data transfer is in progress. */ +} dtc_err_t; + +/* Transfer data type */ +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ + +typedef struct st_transfer_data { /* 3 long-words */ + uint32_t lw1; + uint32_t lw2; + uint32_t lw3; +} dtc_transfer_data_t; + +#else /* Full-address mode */ +typedef struct st_transfer_data { /* 4 long-words */ + uint32_t lw1; + uint32_t lw2; + uint32_t lw3; + uint32_t lw4; +} dtc_transfer_data_t; +#endif + +/* Transfer data configuration */ +/* Moved struct dtc_transfer_data_cfg_t to r_dtc_rx_target_if.h */ +/* Include target mcu interface header file. */ +#if defined(BSP_MCU_RX23T) + #include ".\src\targets\rx23t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX24T) + #include ".\src\targets\rx24t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX24U) + #include ".\src\targets\rx24u\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX130) + #include ".\src\targets\rx130\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX113) + #include ".\src\targets\rx113\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX111) + #include ".\src\targets\rx111\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX110) + #include ".\src\targets\rx110\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX64M) + #include ".\src\targets\rx64m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX71M) + #include ".\src\targets\rx71m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72T) + #include ".\src\targets\rx72t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX231) + #include ".\src\targets\rx231\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX23E_A) + #include ".\src\targets\rx23e-a\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX230) + #include ".\src\targets\rx230\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX65N) + #include ".\src\targets\rx65n\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX66T) + #include ".\src\targets\rx66t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX66N) + #include ".\src\targets\rx66n\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX23W) + #include ".\src\targets\rx23w\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72M) + #include ".\src\targets\rx72m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX13T) + #include ".\src\targets\rx13t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72N) + #include ".\src\targets\rx72n\r_dtc_rx_target_if.h" +#else + #error "This MCU is not supported by the current r_dtc_rx module." +#endif + +typedef struct st_dtc_stat { + uint8_t vect_nr; /* the current vector number */ + bool in_progress; /* Active flag of DTC module */ +} dtc_stat_t; + +typedef struct st_dtc_cmd_arg { + dtc_activation_source_t act_src; /* The activation source will be controlled */ + uint32_t chain_transfer_nr; /* Number of chain transfer when command is DTC_CMD_CHAIN_TRANSFER_ABORT. */ + dtc_transfer_data_t *p_transfer_data; /* Pointer to start address of Transfer data area on RAM */ + dtc_transfer_data_cfg_t *p_data_cfg; /* Pointer to contains the settings for Transfer data */ +} dtc_cmd_arg_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +dtc_err_t R_DTC_Open(void); +dtc_err_t R_DTC_Create(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t chain_transfer_nr); +dtc_err_t R_DTC_CreateSeq(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t sequence_transfer_nr, + uint8_t sequence_no); +dtc_err_t R_DTC_Close(void); +dtc_err_t R_DTC_Control(dtc_command_t command, dtc_stat_t *p_stat, dtc_cmd_arg_t *p_args); +uint32_t R_DTC_GetVersion(void); + +#endif /* DTC_RX_IF_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/readme.txt new file mode 100644 index 000000000..f68a15cab --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/readme.txt @@ -0,0 +1,245 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION + +r_dtc_rx +========= + +Document Number +--------------- +R01AN1819EJ0350 +R01AN1819JJ0350 + +Version +------- +v3.50 + +Overview +-------- +The DTC driver provides a method to transmit the data using Data Transfer Controller (DTC). +The driver includes API functions to initialize DTC, create Transfer data, Control and get status of DTC. +The driver can be reduced in size by removing code used for parameter checking. +All configuration options can be found in "r_config\r_dtc_rx_config.h". +An original copy of the configuration file is stored in "r_dtc_rx\ref\r_dtc_rx_config_reference.h". + +Features +-------- +* Support Normal trasnsfer mode, Repeat trasnsfer mode and Block trasnsfer mode. +* Support chain transfer + +Supported MCUs +-------------- +* RX110 MCU +* RX111 MCU +* RX113 MCU +* RX130 MCU +* RX230 MCU +* RX231 MCU +* RX23E-A MCU +* RX64M MCU +* RX71M MCU +* RX23T MCU +* RX24T MCU +* RX24U MCU +* RX65N MCU +* RX651 MCU +* RX66T MCU +* RX66N MCU +* RX72T MCU +* RX23W MCU +* RX72M MCU +* RX13T MCU +* RX72N MCU + +Boards Tested On +---------------- +* RSKRX110 +* RSKRX111 +* RSKRX113 +* RSKRX130 +* RSKRX130_512KB +* RSKRX230 +* RSKRX231 +* RSKRX23E-A +* RSKRX64M +* RSKRX71M +* RSKRX23T +* RSKRX24T +* RSKRX24U +* RSKRX65N +* RSKRX65N_2MB +* RSKRX66T +* RSKRX66N +* RSKRX72T +* RSKRX23W +* RSKRX72M +* RSKRX13T +* RSKRX72N +Limitations +----------- +* None + +Peripherals Used Directly +------------------------- +* Data Transfer Controller (DTC) + +Required Packages +----------------- +* r_bsp + +How to add to your project +-------------------------- +This module must be added to each project in which it is used. +Renesas recommends using "Smart Configurator" described in (1) or (3). +However, "Smart Configurator" only supports some RX devices. +Please use the methods of (2) or (4) for unsupported RX devices. + +(1) Adding the FIT module to your project using "Smart Configurator" in e2 studio +By using the "Smart Configurator" in e2 studio, +the FIT module is automatically added to your project. +Refer to "Renesas e2 studio Smart Configurator User Guide (R20AN0451)" for details. + +(2) Adding the FIT module to your project using "FIT Configurator" in e2 studio +By using the "FIT Configurator" in e2 studio, +the FIT module is automatically added to your project. +Refer to "Adding Firmware Integration Technology Modules to Projects (R01AN1723)" for details. + +(3) Adding the FIT module to your project using "Smart Configurator" on CS+ +By using the "Smart Configurator Standalone version" in CS+, +the FIT module is automatically added to your project. +Refer to "Renesas e2 studio Smart Configurator User Guide (R20AN0451)" for details. + +(4) Adding the FIT module to your project in CS+ +In CS+, please manually add the FIT module to your project. +Refer to "Adding Firmware Integration Technology Modules to CS+ Projects (R01AN1826)" for details. + +Toolchain(s) Used +----------------- +* Renesas RX v3.02.00 +* GCC for Renesas RX 8.03.00.201904 +* IAR C/C++ Compiler for Renesas RX 4.12.1 + +File Structure +-------------- +r_dtc_rx +| r_dtc_rx_if.h +| readme.txt +| ++---doc +| | +| +---en +| | r01an1819ej{VERSION_NUMBER}-rx-dtc-dmac2.pdf +| +---ja +| r01an1819jj{VERSION_NUMBER}-rx-dtc-dmac2.pdf +| ++---ref +| r_dtc_rx_config_reference.h +| ++---src + | r_dtc_rx.c + | r_dtc_rx_private.h + | + +---targets + | + +---rx23t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx23w + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx24t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx24u + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx64m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx65n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx66t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx66n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx71m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx110 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx111 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx113 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx130 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx13t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx230 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx231 + r_dtc_rx_target.c + r_dtc_rx_target.h + r_dtc_rx_target_if.h + | + +---rx23E-A + r_dtc_rx_target.c + r_dtc_rx_target.h + r_dtc_rx_target_if.h + +r_config + r_dtc_rx_config.h + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h new file mode 100644 index 000000000..d0058ed06 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h @@ -0,0 +1,96 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_config.h +* Description : Configures the DTC drivers +******************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.01.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Added #define DTC_CFG_USE_SEQUENCE_TRANSFER. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +*******************************************************************************/ +#ifndef DTC_RX_CONFIG_H +#define DTC_RX_CONFIG_H + +#define DTC_DISABLE (0) +#define DTC_ENABLE (1) +/* + * SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + * 0 : Compiles out parameter checking. + * 1 : Includes parameter checking. + * Default value is set to BSP_CFG_PARAM_CHECKING_ENABLE to + * re-use the system default setting. +*/ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* + * SPECIFY WHETHER THE DTCER REGISTERS WILL BE CLEARED IN R_DTC_OPEN() + * DTC_DISABLE : Do nothing. + * DTC_ENABLE : Clear all DTCER registers in R_DTC_Open(). +*/ +#define DTC_CFG_DISABLE_ALL_ACT_SOURCE (DTC_ENABLE) + +/* + * SPECIFY WHICH ADDRESS MODE IS SUPPORTED BY DTC + * DTC_DISABLE : Select the Full address mode. + * DTC_ENABLE : Select the Short address mode. +*/ +#define DTC_CFG_SHORT_ADDRESS_MODE (DTC_DISABLE) + +/* + * SPECIFY WHETHER THE TRANSFER DATA READ SKIP IS ENABLED + * DTC_DISABLE : Disable Transfer Data Read Skip. + * DTC_ENABLE : Enable Transfer Data Read Skip. +*/ +#define DTC_CFG_TRANSFER_DATA_READ_SKIP_EN (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE DMAC FIT MODULE IS USED WITH DTC FIT MODULE + * DTC_DISABLE : DMAC FIT module is not used with DTC FIT module. + * DTC_ENABLE : DMAC FIT module is used with DTC FIT module. +*/ +#define DTC_CFG_USE_DMAC_FIT_MODULE (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE SEQUENCE TRANSFER IS USED + * Also, set DTC_DISABLE to DTC_CFG_SHORT_ADDRESS_MODE. + * DTC_DISABLE : Not use sequence transfer. + * DTC_ENABLE : Use sequence transfer. +*/ +#define DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) + + +#endif /* DTC_RX_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c new file mode 100644 index 000000000..1d46b93ee --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c @@ -0,0 +1,1127 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +/******************************************************************************* +* File Name : r_dtc_rx.c +* Description : Functions for using DTC on RX devices. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Changed Tool-Chain version. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : Added RX130, RX23T and RX24T. +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Supported sequence transfer. +* : Added R_DTC_CreateSeq() function. +* : Added DTC_CMD_SEQUENCE_TRANSFER_ENABLE, +* : DTC_CMD_SEQUENCE_TRANSFER_DISABLE and DTC_CMD_SEQUENCE_TRANSFER_ABORT +* : to R_DTC_Control(). +* : 31.01.2017 2.06 Added the default setting of "writeback_disable", "sequence_end", +* : "refer_index_table_enable" and "disp_add_enable" in R_DTC_Create() +* : if the DTC IP version is DTCb or later. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : Fixed to correspond to Renesas coding rule. +* : Added DTC_CMD_CHANGING_DATA_FORCIBLY_SET command to R_DTC_Control(). +* : 28.09.2018 2.10 Supported RX66T. +* : Fixed to correspond to Renesas coding rule. +* : Add WAIT_LOOP comments. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +* Fixed DTC setting procedure. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. + Fixed warnings in IAR. +* : 25.11.2019 3.30 Added support for RX13T. +* : Modified comment of API function to Doxygen style. +* : Fixed to comply with GSCE Coding Standards Rev.6.00. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Defines for DTC support */ +#include +#include "r_dtc_rx_if.h" +#include ".\src\r_dtc_rx_private.h" + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DTC_PRV_ACT_BIT_MASK (0x8000) /* DTC Active flag (DTCSTS.ACT) bit mask */ +#define DTC_PRV_VECT_NR_MASK (0x00FF) /* DTC-Activating Vector Number bits mask */ +#define DTC_PRV_MAX_16BITS_COUNT_VAL (65536) /* The maximum value of 16bit count value */ +#define DTC_PRV_MAX_8BITS_COUNT_VAL (256) /* The maximum value of 8bit count value */ +#define DTC_PRV_MIN_COUNT_VAL (1) /* The minimum of count value and block size */ +#define DTC_PRV_ESPSEL_BIT_MASK (0x8000) /* DTC Sequence transfer vector number setting bit mask */ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +extern const dtc_activation_source_t g_source_array[]; +uint32_t * gp_dtc_table_work[2]; + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ +static bool s_is_opened = false; /* Indicate whether DTC is opened. */ + +static dtc_err_t r_dtc_set_transfer_data(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_cfg); +static void r_dtc_clear_all_dtce_bits(void); +static bool r_dtc_abort_chain_transfer(uint32_t chain_transfer_nr); +static bool r_dtc_acquire_hw_lock(void); +static void r_dtc_release_hw_lock(void); +static bool r_dtc_check_dmac_locking_sw(void); +static dtc_err_t r_dtc_check_create_param(dtc_transfer_data_t *p_transfer_data, dtc_transfer_data_cfg_t *p_data_cfg); + + + +/*********************************************************************************************************************** +* Function Name: R_DTC_Open +********************************************************************************************************************//** +* @brief This function is run first when using the APIs of the DTC FIT module. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_OPENED DTC has been initialized already. +* @retval DTC_ERR_BUSY Resource has been locked by other process. +* @details Locks*1 the DTC and starts supplying clock to DTC, then initializes DTC vector table, address mode, +* Data Transfer Read Skip. When setting DTC_CFG_DISABLE_ALL_ACT_SOURCE to DTC_ENABLE in r_dtc_rx_config.h, all DTCER +* registers are cleared. When setting DTC_CFG_USE_SEQUENCE_TRANSFER to DTC_ENABLE, the area used in DTC index table is +* secured.\n\n +* Note: 1. The DTC FIT module uses the r_bsp default lock function. As a result, the DTC is in the locked state after a +* successful end. +* @note Set \#define BSP_CFG_HEAP_BYTES in r_bsp_config.h to the value greater than \#define DTC_VECTOR_TABLE_SIZE_BYTES +* in r_dtc_rx_target.h. This is to secure the DTC Vector table area using the malloc() function in the DTC FIT module. +*/ +dtc_err_t R_DTC_Open(void) +{ + uint8_t * p_dtc_table_work2 = 0; + + /* Check hw lock require */ + if (false == r_dtc_acquire_hw_lock()) + { + /* Lock has already been acquired by another task. Need to try again later. */ + return DTC_ERR_BUSY; + } + + if (true == s_is_opened) /* DTC is opened. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_OPENED; + } + + /* Allocate memory size */ + gp_dtc_table_work[0] = (uint32_t *)malloc(DTC_VECTOR_TABLE_SIZE_BYTES); + + if (0 == gp_dtc_table_work[0]) + { + r_dtc_release_hw_lock(); + return DTC_ERR_OPENED; + } + + gp_dtc_table_work[1] = gp_dtc_table_work[0]; + + /* Cast type of "gp_dtc_table_work" to match type of "p_dtc_table_work2" */ + p_dtc_table_work2 = (uint8_t *)gp_dtc_table_work[1]; + p_dtc_table_work2 = (p_dtc_table_work2 + 0x400); + + /* Cast type of "p_dtc_table_work2" to match type of "p_dtc_table_work2" */ + p_dtc_table_work2 = (uint8_t *)((uint32_t)p_dtc_table_work2 & 0xfffffc00); + +#if (DTC_ENABLE == DTC_CFG_DISABLE_ALL_ACT_SOURCE) /* Clear all DTCER registers. */ + + r_dtc_clear_all_dtce_bits(); + +#endif /* DTC_ENABLE == DTC_CFG_DISABLE_ALL_ACT_SOURCE */ + + /* Cancel module stop for DMAC and DTC. */ + r_dtc_module_enable(); + + /* Set DTC Vector Table Base Register. */ + DTC.DTCVBR = p_dtc_table_work2; + +#if (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) + p_dtc_table_work2 = (p_dtc_table_work2 + 0x400); + + /* Set address of the dtc index table. */ + DTC.DTCIBR = p_dtc_table_work2; +#endif /* (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ + + /* Set DTC address mode. */ +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + /*Turn on Short Address Mode*/ + DTC.DTCADMOD.BIT.SHORT = 1; +#else /* Full-address mode */ + DTC.DTCADMOD.BIT.SHORT = 0; +#endif /* DTC_CFG_SHORT_ADDRESS_MODE */ + + /* Set the Transfer Data Read Skip bit. */ +#if (DTC_ENABLE == DTC_CFG_TRANSFER_DATA_READ_SKIP_EN) /* Enable Data Read Skip. */ + DTC.DTCCR.BIT.RRS = 1; +#else /* Disable Data Read Skip. */ + DTC.DTCCR.BIT.RRS = 0; +#endif /* DTC_TRANSFER_DATA_READ_SKIP_EN */ + s_is_opened = true; /* DTC module is initialized successfully. */ + + return DTC_SUCCESS; +} +/* End of function R_DTC_Open */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Create +********************************************************************************************************************//** +* @brief This function is used to make DTC register settings and to specify the activation source. +* @param[in] act_source Activation source. +* @param[in] p_transfer_data Pointer to start address of Transfer data area on RAM. +* @param[in] p_data_cfg Pointer to settings for Transfer data. In the case of DTCb, the setting to the following +* structure members is invalid. This function sets the following values.\n +* p_data_cfg->writeback_disable = DTC_WRITEBACK_ENABLE;\n +* p_data_cfg->sequence_end = DTC_SEQUENCE_TRANSFER_CONTINUE;\n +* p_data_cfg->refer_index_table_enable = DTC_REFER_INDEX_TABLE_DISABLE;\n +* p_data_cfg->disp_add_enable = DTC_SRC_ADDR_DISP_ADD_DISABLE;\n +* @param[in] chain_transfer_nr Number of chain transfer.\n +* The number of Transfer data and corresponding configurations is (number of chain transfer + 1). +* Example: if chain_transfer_nr = 1, it means that there are 2 continuous Transfer data and 2 corresponding configurations +* and the first configuration enable the chain transfer.\n +* See Section 3 in application note for details. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_NOT_OPEN DTC is not initialized yet. +* @retval DTC_ERR_INVALID_ARG Parameters are invalid. +* @retval DTC_ERR_NULL_PTR Argument pointers are NULL. +* @details Writes the configuration to Transfer data. Writes the start address of Transfer data corresponding to interrupt +* number into DTC vector table. +* @note Before calling R_DTC_Create(), user must disable the current interrupt request (the interrupt source is passed to +* R_DTC_Create()) by clearing Interrupt Request Enable bit IERm.IENj:\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* Then, enable the interrupt request disabled after R_DTC_Create() is ended. The correspondence between IERm.IENj bit and +* interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of User's Manual: Hardware. +*/ +dtc_err_t R_DTC_Create(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t chain_transfer_nr) +{ + uint32_t count = chain_transfer_nr + 1; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_err_t ret = DTC_SUCCESS; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + + ret = r_dtc_check_create_param(p_transfer_data, p_data_cfg); + if (DTC_SUCCESS != ret) + { + return ret; + } + + if (false == s_is_opened) /* DTC is not initialized yet. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[act_source].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[act_source].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + +#if (DTC_IP_VER_DTCb <= DTC_IP) + /* Set the 0 value. */ + p_data_cfg->writeback_disable = DTC_WRITEBACK_ENABLE; + p_data_cfg->sequence_end = DTC_SEQUENCE_TRANSFER_CONTINUE; + p_data_cfg->refer_index_table_enable = DTC_REFER_INDEX_TABLE_DISABLE; + p_data_cfg->disp_add_enable = DTC_SRC_ADDR_DISP_ADD_DISABLE; +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + if (r_dtc_set_transfer_data(p_transfer_data, p_data_cfg) != DTC_SUCCESS) + { + /* Fail to apply configurations for Transfer data. */ + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_ARG; + } + else + { + p_data_cfg++; + p_transfer_data++; + } + count--; + } + + /* The row in Vector table corresponding to act_source */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCVBR + (4 * act_source)); + + /* Write start address of Transfer data to Vector table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + + /* Restore RRS bit. */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + + return DTC_SUCCESS; +} +/* End of function R_DTC_Create */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_CreateSeq +********************************************************************************************************************//** +* @brief This function performs the setting of the DTC register used in the sequence transfer and the activation source. +* @param[in] act_source Activation source +* @param[in] p_transfer_data Pointer to the start address in the transfer information area in RAM. +* @param[in] p_data_cfg Pointer to the transfer information setting\n +* Set the following structure members.\n +* p_data_cfg->writeback_disable\n +* p_data_cfg->sequence_end\n +* p_data_cfg->refer_index_table_enable\n +* p_data_cfg->disp_add_enable\n +* @param[in] sequence_transfer_nr Transfer information counts per sequence transfer (0 - 4294967295)\n +* See Section 3 in application note for details.\n\n +* @param[in] sequence_no Sequence number (0 - 255)\n +* The type definition of the transfer information and the data structure are the same as R_DTC_Create(). Total of 256 ways +* of the sequence information can be set. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_NOT_OPEN DTC is not initialized yet. +* @retval DTC_ERR_INVALID_ARG Arguments are invalid. +* @retval DTC_ERR_NULL_PTR Argument pointers are NULL. +* @details This function writes the setting information to the transfer information. Start address of the transfer +* information for the sequence number is written to DTC index table. +* @note Before calling R_DTC_CreateSeq(), user must disable the current interrupt request (the interrupt source is passed +* to R_DTC_CreateSeq()) by clearing Interrupt Request Enable bit (IERm.IENj):\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* Then, enable the interrupt request disabled after R_DTC_CreateSeq() is ended. The correspondence between IERm.IENj bit +* and interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of User's Manual: +* Hardware. +*/ +dtc_err_t R_DTC_CreateSeq(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t sequence_transfer_nr, + uint8_t sequence_no) +{ +#if (DTC_DISABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) + return DTC_ERR_INVALID_ARG; +#else + uint32_t count = sequence_transfer_nr; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_err_t ret = DTC_SUCCESS; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + + if (0 != count) + { + ret = r_dtc_check_create_param(p_transfer_data, p_data_cfg); + if (DTC_SUCCESS != ret) + { + return ret; + } + } + + if (false == s_is_opened) /* DTC is not initialized yet. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[act_source].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[act_source].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + /* The row in dtc index table corresponding to sequence_no. */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCIBR + (4 * sequence_no)); + + if (0 == count) + { + /* Set the cpu interrupt to the sequence number. */ + *p_ptr = DTC_INVALID_CMND; + } + else + { + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + /* Fail to apply configurations for Transfer data. */ + if (r_dtc_set_transfer_data(p_transfer_data, p_data_cfg) != DTC_SUCCESS) + { + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_ARG; + } + else + { + p_data_cfg++; + p_transfer_data++; + } + count--; + } + + /* Write start address of Transfer data to dtc index table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + } + + /* Restore RRS bit. */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + + return DTC_SUCCESS; +#endif /* (DTC_DISABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ +} +/* End of function R_DTC_CreateSeq */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Close +********************************************************************************************************************//** +* @brief This function is used to release the resources of the DTC. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_SUCCESS_DMAC_BUSY Successful operation.One or some DMAC resources are locked. +* @details Unlocks*1 the DTC and disable all DTC activation source by clearing the DTC Activation Enable Register DTCERn; +* stop supplying clock to DTC and put it to Module stop state. If in addition all DMAC channels have been unlocked, the +* function sets the DMAC and DTC to the module stop state.*2\n\n +* Note:\n 1. The DTC FIT module uses the r_bsp default lock function. As a result, the DTC is in the unlocked state after +* a successful end.\n 2. Because a shared bit is used as both the DMAC module stop setting bit and the DTC module stop +* setting bit, the function confirms that all DMAC channels are unlocked before making the module stop setting. (For +* details, see the "Low Power Consumption" section in the User's Manual: Hardware.)\n +* See Section 3 in application note for details. +* @note When controlling the DMAC without using the DMAC FIT module, make sure to monitor the usage of the DMAC and +* control locking and unlocking of the DMAC so that calling this function does not set the DMAC to the module stop state. +* Note that even if the DMAC has not been activated, it is necessary to keep it in the locked state when not making DMAC +* transfer settings. +*/ +dtc_err_t R_DTC_Close(void) +{ + /* Clear DTCE bits. */ + r_dtc_clear_all_dtce_bits(); + + /* Stop DTC module. */ + DTC.DTCST.BIT.DTCST = 0; + + /* DTC is closed. */ + s_is_opened = false; + + /* Cast type of "gp_dtc_table_work" to match type of parameter in "free" function */ + free((void *)gp_dtc_table_work[1]); + gp_dtc_table_work[1] = NULL; + + /* Check DMAC locking. */ + if (true == r_dtc_check_dmac_locking_sw()) + { + /* Disable the power for DTC and DMAC module. */ + r_dtc_module_disable(); + + /* Release hardware lock. */ + r_dtc_release_hw_lock(); + } + else + { + /* Release hardware lock. */ + r_dtc_release_hw_lock(); + return DTC_SUCCESS_DMAC_BUSY; + } + + return DTC_SUCCESS; +} +/* End of function R_DTC_Close */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Control +********************************************************************************************************************//** +* @brief This function controls the operation of the DTC. +* @param[in] command DTC control command +* @param[in] p_stat Pointer to the status when command is DTC_CMD_STATUS_GET.\n +* See Section 3 in application note for details. +* @param[in] p_args Pointer to the argument structure when command is DTC_CMD_ACT_SRC_ENABLE,DTC_CMD_ACT_SRC_DISABLE, +* DTC_CMD_CHAIN_TRANSFER_ABORT, DTC_CMD_SEQUENCE_TRANSFER_ENABLE, or DTC_CMD_CHANGING_DATA_FORCIBLY_SET.\n +* See Section 3 in application note for details. +* @retval [DTC_SUCCESS] Successful operation +* @retval [DTC_ERR_NOT_OPEN] DTC is not initialized yet. +* @retval [DTC_ERR_INVALID_COMMAND] Command parameters are invalid or DTC_CMD_CHANGING_DATA_FORCIBLY_SET command error. +* @retval [DTC_ERR_NULL_PTR] Argument pointers are NULL. +* @retval [DTC_ERR_ACT] Data transfer is in progress. +* @details Processing is performed depending on the command.\n +* See Section 3 in application note for details. +* @note When the command is DTC_CMD_GET_STATUS, the vector number is valid if only the DTC is in the progress +* (p_stat->in_progress is true). With command DTC_CMD_ENABLE_ACT_SRC, DTC_CMD_DISABLE_ACT_SRC or +* DTC_CMD_SEQUENCE_TRANSFER_ABORT, before calling R_DTC_Control(), user must disable the current interrupt request +* (the interrupt source is passed to R_DTC_Control()) by clearing Interrupt Request Enable bit (IERm.IENj);\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* After processing of R_DTC_Control() is ended, the interrupt request disabled is enabled. The correspondence between +* IERm.IENj bit and interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of +* User's Manual: Hardware. With abort processing, user must re-create the Chain transfer data after the transfer is +* aborted because the old Transfer data are destroyed. If an invalid value is attempted to set with +* DTC_CMD_CHANGING_DATA_FORCIBLY_SET, R_DTC_Control() returns DTC_ERR_INVALID_COMMAND R_DTC_Control() may already update +* some registers before the invalid value is detected. This occurs only when users try +* to change FORCIBLY DTC with Invalid Value. +*/ +dtc_err_t R_DTC_Control(dtc_command_t command, dtc_stat_t *p_stat, dtc_cmd_arg_t *p_args) +{ + uint32_t count = 0; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + +#if (1 == DTC_CFG_PARAM_CHECKING_ENABLE) + + if ((DTC_CMD_STATUS_GET == command) && (NULL == p_stat)) + { + return DTC_ERR_NULL_PTR; + } + else if ((((DTC_CMD_ACT_SRC_ENABLE == command) || (DTC_CMD_ACT_SRC_DISABLE == command)) || + (DTC_CMD_CHAIN_TRANSFER_ABORT == command)) || (DTC_CMD_SEQUENCE_TRANSFER_ENABLE == command)) + { + if (NULL == p_args) /* Require argument */ + { + return DTC_ERR_NULL_PTR; + } + } + else if (DTC_CMD_CHANGING_DATA_FORCIBLY_SET == command) + { + if (NULL == p_args) /* Require argument */ + { + return DTC_ERR_INVALID_COMMAND; + } + if (r_dtc_check_create_param(p_args->p_transfer_data, p_args->p_data_cfg) != DTC_SUCCESS) + { + return DTC_ERR_INVALID_COMMAND; + } + } + else + { + /* do nothing */ + } + +#endif /* DTC_CFG_PARAM_CHECKING_ENABLE */ + + if (false == s_is_opened) + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + switch (command) + { + case DTC_CMD_DTC_START: /* Start DTC module. */ + { + /* DTC Module start*/ + DTC.DTCST.BIT.DTCST = 1; + break; + } + + case DTC_CMD_DTC_STOP: /* Stop DTC module. */ + { + /* DTC Module stop*/ + DTC.DTCST.BIT.DTCST = 0; + break; + } + + case DTC_CMD_DATA_READ_SKIP_ENABLE: /* Enable Transfer Data Read Skip. */ + { + /* Set Read Skip Enable bit*/ + DTC.DTCCR.BIT.RRS = 1; + break; + } + + case DTC_CMD_DATA_READ_SKIP_DISABLE: /* Disable Transfer Data Read Skip. */ + { + /* Clear Read Skip Enable bit*/ + DTC.DTCCR.BIT.RRS = 0; + break; + } + + case DTC_CMD_ACT_SRC_ENABLE: /* Select one interrupt as a DTC activation source. */ + { + /* Set Activation source for DTC*/ + ICU.DTCER[p_args->act_src].BIT.DTCE = 1; + break; + } + + case DTC_CMD_ACT_SRC_DISABLE: /* Remove one interrupt as a DTC activation source. */ + { + /* Clear Activation source*/ + ICU.DTCER[p_args->act_src].BIT.DTCE = 0; + break; + } + + case DTC_CMD_STATUS_GET: + { + /* Check DTC Status*/ + if (0 == (DTC.DTCSTS.WORD & DTC_PRV_ACT_BIT_MASK)) /* DTC transfer operation is not in progress. */ + { + p_stat->in_progress = false; + + /* DTC is not in progress. -> vector number is invalid. */ + } + else /* DTC transfer operation is in progress. */ + { + p_stat->in_progress = true; + + /* Get the current vector number. */ + p_stat->vect_nr = (uint8_t)(DTC.DTCSTS.WORD & DTC_PRV_VECT_NR_MASK); /* get lower 8 bits: 0-7*/ + } + break; + } + + case DTC_CMD_CHAIN_TRANSFER_ABORT: + { + r_dtc_abort_chain_transfer(p_args->chain_transfer_nr); + break; + } + +#if (DTC_IP_VER_DTCb <= DTC_IP) + + case DTC_CMD_SEQUENCE_TRANSFER_ENABLE: + + /* Set the sequence transfer vector number and sequence transfer is enabled. */ + DTC.DTCSQE.WORD = (DTC_PRV_ESPSEL_BIT_MASK | (uint16_t)p_args->act_src); + break; + + case DTC_CMD_SEQUENCE_TRANSFER_DISABLE: + + /* Sequence transfer is disabled. */ + DTC.DTCSQE.WORD &= (~DTC_PRV_ESPSEL_BIT_MASK); + break; + + case DTC_CMD_SEQUENCE_TRANSFER_ABORT: + + /* DTC transfer operation is in progress. */ + if (DTC.DTCSTS.WORD & DTC_PRV_ACT_BIT_MASK) + { + /* Store value of VECN of DTCSQE Register to "tmp" variable */ + uint16_t tmp = DTC.DTCSQE.BIT.VECN; + + /* Compare value of VECN of DTCSTS Register with "tmp" variable */ + if (DTC.DTCSTS.BIT.VECN == tmp) + { + return DTC_ERR_ACT; + } + } + + /* Abort the sequence transfer. */ + DTC.DTCOR.BIT.SQTFRL = 1; + break; + +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + case DTC_CMD_CHANGING_DATA_FORCIBLY_SET: + { + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_args->p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[p_args->act_src].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[p_args->act_src].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + count = p_args->chain_transfer_nr + 1; + + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + if (r_dtc_set_transfer_data(p_args->p_transfer_data, p_args->p_data_cfg) != DTC_SUCCESS) + { + /* Fail to apply configurations for Transfer data. */ + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[p_args->act_src].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_COMMAND; + } + else + { + p_args->p_transfer_data++; + p_args->p_data_cfg++; + } + count--; + } + + /* The row in Vector table corresponding to act_source */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCVBR + (4 * p_args->act_src)); + + /* Write start address of Transfer data to Vector table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[p_args->act_src].BIT.DTCE = dtce_backup; + break; + } + default: + { + return DTC_ERR_INVALID_COMMAND; + break; + } + } + + return DTC_SUCCESS; +} +/* End of function R_DTC_Control */ + +/******************************************************************************* +* Function Name: R_DTC_GetVersion +****************************************************************************//** +* @brief This function is used to get the driver version information. +* @return Version_number Upper 2 bytes: major version, lower 2 bytes: minor version +* @details Returns the version information. +* @note None +*/ +uint32_t R_DTC_GetVersion(void) +{ + uint32_t version = 0; + + version = (DTC_VERSION_MAJOR << 16) | DTC_VERSION_MINOR; + + return version; +} +/* End of function R_DTC_GetVersion */ + +/******************************************************************************* +* Function Name: r_dtc_set_transfer_data +* Description : Applies configurations to a Transfer data area, it is an internal +* function called by R_DTC_Create(); and all arguments are validated +* in R_DTC_Create() +* Arguments : transfer_data - +* Start address of Transfer data +* data_cfg - +* Contains configurations for the Transfer data +* Return Value : DTC_SUCCESS - +* Apply configurations for Transfer data successfully. +* DTC_ERR_INVALID_ARG +* Fail to apply configurations for Transfer data. +*******************************************************************************/ +static dtc_err_t r_dtc_set_transfer_data(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_cfg) +{ + dtc_mra_t t_mra; + dtc_mrb_t t_mrb; + dtc_cra_t t_cra; + dtc_crb_t t_crb; + + /* Cast type of "p_transfer_data" to match type of "p_td_ptr" */ + volatile dtc_internal_registers_t *p_td_ptr = (volatile dtc_internal_registers_t *)p_transfer_data; + + /* Set for MRA - . */ +#if (DTC_IP_VER_DTCb <= DTC_IP) +#if (DTC_ENABLE != DTC_CFG_SHORT_ADDRESS_MODE) /* Full-address mode */ + dtc_mrc_t t_mrc; + + /* Casting to match type of "t_mrc.BYTE" */ + t_mrc.BYTE = (uint8_t)(p_cfg->disp_add_enable); +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ + /* Casting to match type of "t_mra.BYTE" */ + t_mra.BYTE = ((((uint8_t)p_cfg->writeback_disable | (uint8_t)p_cfg->src_addr_mode) | (uint8_t)p_cfg->data_size) | (uint8_t)p_cfg->transfer_mode); + + /* Casting to match type of "t_mrb.BYTE" */ + t_mrb.BYTE = (((((((uint8_t)p_cfg->sequence_end |(uint8_t)p_cfg->refer_index_table_enable) | (uint8_t)p_cfg->dest_addr_mode) | + (uint8_t)p_cfg->repeat_block_side) | (uint8_t)p_cfg->response_interrupt) | + (uint8_t)p_cfg->chain_transfer_enable) | (uint8_t)p_cfg->chain_transfer_mode); +#else + /* Casting to match type of "t_mra.BYTE" */ + t_mra.BYTE = (uint8_t)(p_cfg->src_addr_mode | p_cfg->data_size | p_cfg->transfer_mode); + + /* Casting to match type of "t_mrb.BYTE" */ + t_mrb.BYTE = (uint8_t)(p_cfg->dest_addr_mode | p_cfg->repeat_block_side | p_cfg->response_interrupt | + p_cfg->chain_transfer_enable | p_cfg->chain_transfer_mode); +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + switch (t_mra.BIT.MD) /* DTC transfer mode */ + { + case 0x0: /* Normal mode */ + { + if (DTC_PRV_MAX_16BITS_COUNT_VAL == p_cfg->transfer_count)/* Transfer count = 65536 */ + { + t_cra.WORD = 0x0000; + } + else /* 1 - 65535 */ + { + /* Cast type of "p_cfg->transfer_count" to uint16_t to match type of "t_cra.WORD" */ + t_cra.WORD = (uint16_t)p_cfg->transfer_count; + } + break; + } + + case 0x1: /* Repeat mode */ + { + /* Set counter. */ + if (p_cfg->transfer_count < DTC_PRV_MAX_8BITS_COUNT_VAL) /* count 1-255 */ + { + /* Cast type of "p_cfg->transfer_count" to match type of "t_cra.BYTE.CRA_H" */ + t_cra.BYTE.CRA_H = (uint8_t)p_cfg->transfer_count; + + /* Cast type of "p_cfg->transfer_count" to match type of "t_cra.BYTE.CRA_L" */ + t_cra.BYTE.CRA_L = (uint8_t)p_cfg->transfer_count; + } + else if (DTC_PRV_MAX_8BITS_COUNT_VAL == p_cfg->transfer_count) + { + t_cra.BYTE.CRA_H = 0x00; + t_cra.BYTE.CRA_L = 0x00; + } + else /* Transfer count > 256 */ + { + return DTC_ERR_INVALID_ARG; + } + break; + } + + case 0x2: /* DTC_TRANSFER_MODE_BLOCK - Block transfer mode */ + { + /* Set counter. */ + if (DTC_PRV_MAX_16BITS_COUNT_VAL == p_cfg->transfer_count)/* Transfer count = 65536 */ + { + t_crb.WORD = 0x0000; + } + else /* 1 - 65535 */ + { + /* Cast type of "p_cfg->transfer_count" to uint16_t to match type of "t_cra.WORD" */ + t_crb.WORD = (uint16_t)p_cfg->transfer_count; + } + + if (p_cfg->block_size < DTC_PRV_MAX_8BITS_COUNT_VAL) /* Block size 1-255 */ + { + /* Cast type of "p_cfg->block_size" to match type of "t_cra.BYTE.CRA_H" */ + t_cra.BYTE.CRA_H = (uint8_t)p_cfg->block_size; + + /* Cast type of "p_cfg->block_size" to match type of "t_cra.BYTE.CRA_L" */ + t_cra.BYTE.CRA_L = (uint8_t)p_cfg->block_size; + } + else if (DTC_PRV_MAX_8BITS_COUNT_VAL == p_cfg->block_size) /* Block size = 256 */ + { + t_cra.BYTE.CRA_H = 0; + t_cra.BYTE.CRA_L = 0; + } + else /* Invalid block size */ + { + return DTC_ERR_INVALID_ARG; + } + break; + } + + default: + { + return DTC_ERR_INVALID_ARG; + break; + } + } + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ + /* settings for fist long word: MRA & SAR */ + p_td_ptr->FIRST_LWORD.LWORD = 0; /* clear */ + p_td_ptr->FIRST_LWORD.REG.MRA = t_mra; /* 1 byte MRA */ + p_td_ptr->FIRST_LWORD.LWORD |= (p_cfg->source_addr & 0x00FFFFFF); /* 3 byte SAR */ + + /* settings for second long word: MRB & DAR */ + p_td_ptr->SECOND_LWORD.LWORD = 0; /* clear */ + p_td_ptr->SECOND_LWORD.REG.MRB = t_mrb; /* 1 byte MRB */ + p_td_ptr->SECOND_LWORD.LWORD |= (p_cfg->dest_addr & 0x00FFFFFF); /* 3 byte DAR */ + + /* settings for third long word: CRA & CRB */ + p_td_ptr->THIRD_LWORD.REG.CRA.WORD = t_cra.WORD; + p_td_ptr->THIRD_LWORD.REG.CRB.WORD = t_crb.WORD; + +#else /* Full-address mode */ + /* settings for fist long word: MRA & MRB */ + p_td_ptr->FIRST_LWORD.REG.MRA.BYTE = t_mra.BYTE; /* 1 byte MRA */ + p_td_ptr->FIRST_LWORD.REG.MRB.BYTE = t_mrb.BYTE; /* 1 byte MRB */ +#if (DTC_IP_VER_DTCb <= DTC_IP) + p_td_ptr->FIRST_LWORD.REG.MRC.BYTE = t_mrc.BYTE; /* 1 byte MRC */ +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + /* settings for second long word: SAR */ + p_td_ptr->SECOND_LWORD.SAR = p_cfg->source_addr; /* 4 byte SAR */ + + /* settings for third long word: DAR */ + p_td_ptr->THIRD_LWORD.DAR = p_cfg->dest_addr; /* 4 byte DAR */ + + /* settings for fourth long word: CRA & CRB */ + p_td_ptr->FOURTH_LWORD.REG.CRA.WORD = t_cra.WORD; + p_td_ptr->FOURTH_LWORD.REG.CRB.WORD = t_crb.WORD; +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ + return DTC_SUCCESS; +} +/* End of function r_dtc_set_transfer_data */ + +/******************************************************************************* +* Function Name: r_dtc_clear_all_dtce_bits +* Description : Clears all DTCERn.DTCE bit corresponding to the interrupt that +* can be selected as DTC activation sources. +* Arguments : addr - +* Address need to be validated +* Return Value : true - +* The address is valid. +* false - +* The address is invalid. +*******************************************************************************/ +static void r_dtc_clear_all_dtce_bits(void) +{ + volatile uint32_t dtce_cnt = 0; + + /* Clear all DTCER registers. + * Scan through all available DTCER registers in Array. + */ + /* WAIT_LOOP */ + while (dtce_cnt < DTC_NUM_INTERRUPT_SRC) + { + /* Clear Activation source*/ + ICU.DTCER[g_source_array[dtce_cnt]].BIT.DTCE = 0; + dtce_cnt++; + } + + return; +} +/* End of function r_dtc_clear_all_dtce_bits */ + +/******************************************************************************* +* Function Name: r_dtc_abort_chain_transfer +* Description : Aborts the current active chain transfer. +* Arguments : chain_transfer_nr - +* Number of chain transfer +* Return Value : true - +* Abort successfully. +* false +* Can not abort. +*******************************************************************************/ +static bool r_dtc_abort_chain_transfer(uint32_t chain_transfer_nr) +{ + volatile uint32_t cnt = 0; + uint16_t status_reg = 0; + + /* Set status register*/ + status_reg = DTC.DTCSTS.WORD; + + volatile dtc_internal_registers_t *p_td_ptr = NULL; + + if (0 == (status_reg & 0x8000)) /* DTC is not active. */ + { + return false; + } + + status_reg &= 0xFF; /* Get the vector number. */ + p_td_ptr = (((volatile dtc_internal_registers_t *)*((uint32_t *)DTC.DTCVBR + status_reg)) + chain_transfer_nr) - 1; + + /* Clear all CHNE bit */ + /* WAIT_LOOP */ + while (cnt < chain_transfer_nr) + { +#if (DTC_DISABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Full address mode */ + p_td_ptr->FIRST_LWORD.REG.MRB.BIT.CHNE = 0; +#else /* Short address mode */ + p_td_ptr->SECOND_LWORD.REG.MRB.BIT.CHNE = 0; +#endif + p_td_ptr--; + cnt++; + } + + return true; +} +/* End of function r_dtc_abort_chain_transfer */ + +/******************************************************************************* +* Function Name: r_dtc_acquire_hw_lock +* Description : Gets the hardware lock BSP_LOCK_DTC. +* Arguments : None. +* Return Value : true - +* The lock is acquired successfully +* false - +* Fails to get the lock +*******************************************************************************/ +static bool r_dtc_acquire_hw_lock(void) +{ + return R_BSP_HardwareLock(BSP_LOCK_DTC); +} +/* End of function r_dtc_acquire_hw_lock */ + +/******************************************************************************* +* Function Name: r_dtc_release_hw_lock +* Description : release hardware lock BSP_LOCK_DTC. +* Arguments : None. +* Return Value : None. +*******************************************************************************/ +static void r_dtc_release_hw_lock(void) +{ + R_BSP_HardwareUnlock(BSP_LOCK_DTC); + return; +} +/* End of function r_dtc_release_hw_lock */ + + +/******************************************************************************* +* Function Name: r_dtc_check_dmac_locking_sw +* Description : Checks all DMAC channel locking. +* Arguments : none - +* Return Value : true - +* All DMAC channels are unlocked. +* false - +* One or some DMAC channels are locked. +*******************************************************************************/ +static bool r_dtc_check_dmac_locking_sw(void) +{ + bool ret = true; + +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) + /* defined(0 != BSP_CFG_USER_LOCKING_ENABLED) */ + /* or defined(DTC_ENABLE !=DTC_CFG_USE_DMAC_FIT_MODULE) */ + /* or defined(bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) */ + /* User has to do the locking check of DMAC by themselves. */ + ret = r_dtc_check_DMAC_locking_byUSER(); +#else + uint32_t channel; + uint32_t dmac_lock_num = 0; + + /* Check locking status of all DMAC channels */ + /* WAIT_LOOP */ + for (channel = 0; channel < DMAC_NUM_CHANNELS; channel++) + { + /* Checks if DMAC channel is not locking */ + if (false == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_DMAC0 + channel))) + { + dmac_lock_num++; + } + else + { + /* Unlock DMAC channel */ + R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_DMAC0 + channel)); + } + } + + if (0 == dmac_lock_num) + { + ret = true; + } + else + { + ret = false; + } +#endif + + return ret; +} +/* End of function r_dtc_check_dmac_locking_sw */ + +/******************************************************************************* +* Function Name: r_dtc_check_create_param +* Description : Checks creating function parameter. +* Arguments : none - +* Return Value : DTC_SUCCESS - +* Successful operation +* DTC_ERR_INVALID_ARG - +* Parameters are invalid. +* DTC_ERR_NULL_PTR - +* The pointers are NULL. +*******************************************************************************/ +static dtc_err_t r_dtc_check_create_param(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg) +{ +#if (1 == DTC_CFG_PARAM_CHECKING_ENABLE) + + if ((NULL == p_data_cfg) || (NULL == p_transfer_data)) + { + return DTC_ERR_NULL_PTR; + } + + if ((p_data_cfg->transfer_count < DTC_PRV_MIN_COUNT_VAL) || + (p_data_cfg->transfer_count > DTC_PRV_MAX_16BITS_COUNT_VAL)) + { + return DTC_ERR_INVALID_ARG; + } + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ +/* Address must be in: 0x00000000h to 0x007FFFFF and 0xFF800000 to 0xFFFFFFFF */ + if ((p_data_cfg->source_addr > 0x007FFFFF) && (p_data_cfg->source_addr < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } + + if ((p_data_cfg->dest_addr > 0x007FFFFF) && (p_data_cfg->dest_addr < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } + /* Casting to match type of "uint32_t" */ + if (((uint32_t)p_transfer_data > 0x007FFFFF) && ((uint32_t)p_transfer_data < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ +#endif /* (1 == DTC_CFG_PARAM_CHECKING_ENABLE) */ + return DTC_SUCCESS; +} +/* End of function r_dtc_check_create_param */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h new file mode 100644 index 000000000..4995ce1cd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h @@ -0,0 +1,409 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_private.h +* Description : Functions for using DTC on RX devices. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : Added RX130, RX23T and RX24T. +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Supported sequence transfer. +* : Added DTC IP version definitions. +* : 13.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 18.06.2019 3.01 Removed "defined(__BIG_ENDIAN__)" from DTC_BIG_ENDIAN macro definition. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. +* : 25.11.2019 3.30 Added support for RX13T. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +* : 31.03.2020 3.50 Added support for RX23E-A. +*******************************************************************************/ +#ifndef DTC_RX_PRIVATE_H +#define DTC_RX_PRIVATE_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Fixed width integer support. */ +#include +/* Bool support */ +#include + +#if defined(BSP_MCU_RX23T) + #include ".\src\targets\rx23t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24T) + #include ".\src\targets\rx24t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24U) + #include ".\src\targets\rx24u\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX130) + #include ".\src\targets\rx130\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX13T) + #include ".\src\targets\rx13t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX113) + #include ".\src\targets\rx113\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX111) + #include ".\src\targets\rx111\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX110) + #include ".\src\targets\rx110\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX64M) + #include ".\src\targets\rx64m\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX71M) + #include ".\src\targets\rx71m\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX231) + #include ".\src\targets\rx231\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX23E_A) + #include ".\src\targets\rx23e-a\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX23W) + #include ".\src\targets\rx23w\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX230) + #include ".\src\targets\rx230\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX65N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx65n\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX66T) + #include ".\src\targets\rx66t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX66N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx66n\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX72T) + #include ".\src\targets\rx72t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX72M) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx72m\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX72N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx72n\r_dtc_rx_target.h" +#else + #error "This MCU is not supported by the current r_dtc_rx module." +#endif + +/***************************************************************************** +Macro definitions +******************************************************************************/ +#define DTC_BIG_ENDIAN (defined(__BIG) || defined(__RX_BIG_ENDIAN__)) +#define DTC_INVALID_CMND ((uint32_t)0x00000001) +/* DTC IP version */ +#define DTC_IP_VER_DTC (0) +#define DTC_IP_VER_DTCa (1) +#define DTC_IP_VER_DTCb (2) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +/* The DTC Mode Register A (MRA) structure */ + +R_BSP_PRAGMA_UNPACK; + +#if (DTC_IP_VER_DTCa == DTC_IP) +typedef union dtc_mra { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4 ( + uint8_t MD:2, /* b7,b6: DTC Transfer Mode Select */ + uint8_t SZ:2, /* DTC Data Transfer Size */ + uint8_t SM:2, /* Transfer Source Address Addressing Mode */ + uint8_t rs:2 /* reserved */ + ) BIT; + +} dtc_mra_t; + +/* The DTC Mode Register B (MRB) structure */ +typedef union dtc_mrb { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6 ( + uint8_t CHNE :1, /* b7: DTC Chain Transfer Enable */ + uint8_t CHNS :1, /* DTC Chain Transfer Select */ + uint8_t DISEL:1, /* DTC Interrupt Select */ + uint8_t DTS :1, /* DTC Transfer Mode Select */ + uint8_t DM :2, /* Transfer Destination Address Addressing Mode */ + uint8_t rs :2 /* reserved */ + ) BIT; + +} dtc_mrb_t; +#else +typedef union dtc_mra { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5 ( + uint8_t MD:2, /* b7,b6: DTC Transfer Mode Select */ + uint8_t SZ:2, /* DTC Data Transfer Size */ + uint8_t SM:2, /* Transfer Source Address Addressing Mode */ + uint8_t rs:1, /* reserved */ + uint8_t WBDIS:1 /* Write-back Disable */ + ) BIT; + +} dtc_mra_t; + +/* The DTC Mode Register B (MRB) structure */ +typedef union dtc_mrb { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7 ( + uint8_t CHNE :1, /* b7: DTC Chain Transfer Enable */ + uint8_t CHNS :1, /* DTC Chain Transfer Select */ + uint8_t DISEL:1, /* DTC Interrupt Select */ + uint8_t DTS :1, /* DTC Transfer Mode Select */ + uint8_t DM :2, /* Transfer Destination Address Addressing Mode */ + uint8_t INDX:1, /* Index Table Reference */ + uint8_t SQEND:1 /* Sequence Transfer End */ + ) BIT; + +} dtc_mrb_t; + +/* The DTC Mode Register C (MRC) structure */ +typedef union dtc_mrc { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2 ( + uint8_t rs :7, /* reserved */ + uint8_t DISPE :1 + ) BIT; + +} dtc_mrc_t; +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + +/* The DTC Transfer Count Register A (CRA) structure */ +typedef union dtc_cra { + uint16_t WORD; + struct { +#if (DTC_BIG_ENDIAN) + uint8_t CRA_H; + uint8_t CRA_L; +#else /* little endian */ + uint8_t CRA_L; + uint8_t CRA_H; +#endif /* (DTC_BIG_ENDIAN) */ + } BYTE; +} dtc_cra_t; + +/* The DTC Transfer Count Register B (CRB) structure */ +typedef union dtc_crb { + uint16_t WORD; +} dtc_crb_t; + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Transfer data in short-address mode */ +typedef struct st_dtc_short_transfer_data { + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mra_t MRA; + uint8_t SAR[3]; +#else /* Little-Endian */ + uint8_t SAR[3]; + dtc_mra_t MRA; +#endif /* (DTC_BIG_ENDIAN) */ + + } REG; + + } FIRST_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mrb_t MRB; + uint8_t DAR[3]; +#else /* Little-Endian */ + uint8_t SAR[3]; + dtc_mrb_t MRB; +#endif /* (DTC_BIG_ENDIAN) */ + + } REG; + } SECOND_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_cra_t CRA; + dtc_crb_t CRB; +#else /* Little-Endian */ + dtc_crb_t CRB; + dtc_cra_t CRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } THIRD_LWORD; +} dtc_internal_registers_t; + +#else /* Transfer data in full-address mode */ +typedef struct st_dtc_full_transfer_data { + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mra_t MRA; + dtc_mrb_t MRB; +#if (DTC_IP_VER_DTCa == DTC_IP) + uint16_t reserver; /* reserve area */ +#else + dtc_mrc_t MRC; + uint8_t reserver; /* reserve area */ +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + +#else /* Little-Endian */ +#if (DTC_IP_VER_DTCa == DTC_IP) + uint16_t reserver; /* reserve area */ +#else + uint8_t reserver; /* reserve area */ + dtc_mrc_t MRC; +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + dtc_mrb_t MRB; + dtc_mra_t MRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } FIRST_LWORD; + union { + uint32_t SAR; + } SECOND_LWORD; + union { + uint32_t DAR; + } THIRD_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_cra_t CRA; + dtc_crb_t CRB; +#else /* Little-Endian */ + dtc_crb_t CRB; + dtc_cra_t CRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } FOURTH_LWORD; +} dtc_internal_registers_t; + +#endif /* DTC_CFG_SHORT_ADDRESS_MODE */ + +R_BSP_PRAGMA_PACKOPTION; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void r_dtc_module_enable(void); +void r_dtc_module_disable(void); +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) +bool r_dtc_check_DMAC_locking_byUSER(void); +#endif + + +#endif /* DTC_RX_PRIVATE_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c new file mode 100644 index 000000000..ac86b0d7d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c @@ -0,0 +1,207 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target.c +* Device : RX72N +* Tool-Chain : Renesas RXC Toolchain v3.01.00 +* OS : not use +* H/W Platform : not use +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Defines for DTC support */ +#include "r_dtc_rx_if.h" +#include ".\src\r_dtc_rx_private.h" + +/* Check MCU Group */ +#if defined(BSP_MCU_RX72N) + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +/* The array of all interrupt source */ +const dtc_activation_source_t g_source_array[DTC_NUM_INTERRUPT_SRC] = +{ +DTCE_ICU_SWINT2,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USB0_D0FIFO0,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSIE0_SSITXI0,DTCE_SSIE0_SSIRXI0, +DTCE_SSIE1_SSIRTI1, +DTCE_RIIC1_RXI1,DTCE_RIIC1_TXI1, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10,DTCE_SCI10_TXI10, +DTCE_RSPI2_SPRI2,DTCE_RSPI2_SPTI2, +DTCE_SCI11_RXI11,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +}; + + +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) +/******************************************************************************* +* Function Name: r_dtc_check_DMAC_locking_byUSER +* Description : Checks all DMAC channel locking. +* Arguments : none - +* Return Value : true - +* All DMAC channels are unlocked. +* false - +* One or some DMAC channels are locked. +* +*******************************************************************************/ +bool r_dtc_check_DMAC_locking_byUSER(void) +{ + bool ret = true; + + /* User has to check the locking of DMAC by themselves. */ + /* do something */ + + return ret; +} +#endif + + +/******************************************************************************* +* Function Name: r_dtc_module_enable +* Description : Releases module stop state. +* Arguments : None +* Return Value : None +*******************************************************************************/ +void r_dtc_module_enable(void) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) +bsp_int_ctrl_t int_ctrl; +#endif + /* Enable writing to MSTP registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + /* Release from module stop state. */ + MSTP(DTC) = 0; + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + /* Disable writing to MSTP registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} +/****************************************************************************** + End of function r_dtc_module_enable + *****************************************************************************/ + +/******************************************************************************* +* Function Name: r_dtc_module_disable +* Description : Sets to module stop state. +* Arguments : None +* Return Value : None +*******************************************************************************/ +void r_dtc_module_disable(void) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) +bsp_int_ctrl_t int_ctrl; +#endif + /* Enable writing to MSTP registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + /* Set to module stop state. */ + MSTP(DTC) = 1; + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + /* Disable writing to MSTP registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} +/****************************************************************************** + End of function r_dtc_module_disable + *****************************************************************************/ + +#endif /* defined(BSP_MCU_RX72N) */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h new file mode 100644 index 000000000..918d5456f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target.h +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ +#ifndef DTC_RX_TARGET_H +#define DTC_RX_TARGET_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* The number of activation sources */ +#if defined(BSP_MCU_RX72N) +#define DTC_NUM_INTERRUPT_SRC (204) +#endif /* defined(BSP_MCU_RX72N) */ + +#if (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) +/* Size of DTC Vector table and DTC Index table (in byte units) */ +#define DTC_VECTOR_TABLE_SIZE_BYTES (0x400 + 0x400 + 0x400) +#else +/* Size of DTC Vector table (in byte units) */ +#define DTC_VECTOR_TABLE_SIZE_BYTES (0x400 + 0x400) +#endif /* (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ + +/* Definition of num of DMAC channel. */ +#define DMAC_NUM_CHANNELS (8) + +/* DTC IP Version */ +#define DTC_IP (DTC_IP_VER_DTCb) + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif /* DTC_RX_TARGET_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h new file mode 100644 index 000000000..d2234ccf5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target_if.h +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ +#ifndef DTC_RX_TARGET_IF_H +#define DTC_RX_TARGET_IF_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +/* Transfer data configuration */ +typedef struct st_dtc_transfer_data_cfg { + dtc_transfer_mode_t transfer_mode; /* DTC transfer mode */ + dtc_data_size_t data_size; /* Size of data */ + dtc_src_addr_mode_t src_addr_mode; /* Address mode of source */ + dtc_chain_transfer_t chain_transfer_enable; /* Chain transfer is enabled or not. */ + dtc_chain_transfer_mode_t chain_transfer_mode; /* How chain transfer is performed. */ + dtc_interrupt_t response_interrupt; /* How response interrupt is raised */ + dtc_repeat_block_side_t repeat_block_side; /* The side being repeat or block in repeat / block transfer mode. */ + dtc_dest_addr_mode_t dest_addr_mode; /* Address mode of destination */ + uint32_t source_addr; /* Start address of source */ + uint32_t dest_addr; /* Start address of destination */ + uint32_t transfer_count; /* Transfer count */ + uint16_t block_size; /* Size of a block in block transfer mode */ + uint16_t rsv; /* Reserved */ + dtc_write_back_t writeback_disable; /* Write-back disable or enable */ + dtc_sequence_end_t sequence_end; /* Sequence transfer end or continue */ + dtc_refer_index_table_t refer_index_table_enable; /* Index table refer or not refer */ + dtc_disp_add_t disp_add_enable; /* The displacement value is added or not added */ +} dtc_transfer_data_cfg_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif /* DTC_RX_TARGET_IF_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h new file mode 100644 index 000000000..67885fe4a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_if.h +* Description : General Purpose I/O driver for RX MCUs. This interface file has everything the user needs to use this +* module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 23.04.2014 1.20 Add support for RX63N, and RX110 +* : 28.05.2014 1.30 Add support for RX64M +* : 28.11.2014 1.40 Add support for RX113 +* : 02.09.2015 1.50 Add support for RX71M, increased the minor version number to 50. +* : Added GPIO_CMD_DSCR_DISABLE and GPIO_CMD_DSCR_ENABLE commands in gpio_cmd_t +* : 06.04.2015 1.60 Add support for RX231 +* : 30.09.2015 1.70 Add support for RX23T +* : 01.10.2015 1.80 Add support for RX130 +* : 01.12.2015 1.90 Add support for RX24T +* : 01.02.2016 2.00 Add support for RX230 +* : 15.06.2016 2.01 Added the demo of the RX64M group. +* : 01.10.2016 2.10 Add support for RX65N +* : 19.12.2016 2.20 Add support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Add support for RX65N-2M, RX130-512KB +* : 31.10.2017 2.31 Added the demo for RX65N, RX65N-2M +* : 28.09.2018 2.40 Add support for RX66T +* : 16.11.2018 2.41 Added XML document number +* : 01.02.2019 2.50 Add support for RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Removed support for Generation 1 devices. +* : 30.12.2019 3.40 Added support RX72N, RX66N +* : 31.03.2020 3.50 Added support for RX23E-A +***********************************************************************************************************************/ + +#ifndef GPIO_RX_INTERFACE_HEADER_FILE +#define GPIO_RX_INTERFACE_HEADER_FILE + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Module configuration. */ +#include "r_gpio_rx_config.h" + +/* Include specifics for chosen MCU. Go to the header file for your MCU to see available ports and pins. */ +#if defined(BSP_MCU_RX113) + #include "./src/targets/rx113/r_gpio_rx113.h" +#elif defined(BSP_MCU_RX110) + #include "./src/targets/rx110/r_gpio_rx110.h" +#elif defined(BSP_MCU_RX111) + #include "./src/targets/rx111/r_gpio_rx111.h" +#elif defined(BSP_MCU_RX130) + #include "./src/targets/rx130/r_gpio_rx130.h" +#elif defined(BSP_MCU_RX13T) + #include "./src/targets/rx13t/r_gpio_rx13t.h" +#elif defined(BSP_MCU_RX230) + #include "./src/targets/rx230/r_gpio_rx230.h" +#elif defined(BSP_MCU_RX231) + #include "./src/targets/rx231/r_gpio_rx231.h" +#elif defined(BSP_MCU_RX23T) + #include "./src/targets/rx23t/r_gpio_rx23t.h" +#elif defined(BSP_MCU_RX23W) + #include "./src/targets/rx23w/r_gpio_rx23w.h" +#elif defined(BSP_MCU_RX23E_A) + #include "./src/targets/rx23e-a/r_gpio_rx23e-a.h" +#elif defined(BSP_MCU_RX24T) + #include "./src/targets/rx24t/r_gpio_rx24t.h" +#elif defined(BSP_MCU_RX24U) + #include "./src/targets/rx24u/r_gpio_rx24u.h" +#elif defined(BSP_MCU_RX64M) + #include "./src/targets/rx64m/r_gpio_rx64m.h" +#elif defined(BSP_MCU_RX65N) + #include "./src/targets/rx65n/r_gpio_rx65n.h" +#elif defined(BSP_MCU_RX66T) + #include "./src/targets/rx66t/r_gpio_rx66t.h" +#elif defined(BSP_MCU_RX66N) + #include "./src/targets/rx66n/r_gpio_rx66n.h" +#elif defined(BSP_MCU_RX71M) + #include "./src/targets/rx71m/r_gpio_rx71m.h" +#elif defined(BSP_MCU_RX72T) + #include "./src/targets/rx72t/r_gpio_rx72t.h" +#elif defined(BSP_MCU_RX72M) + #include "./src/targets/rx72m/r_gpio_rx72m.h" +#elif defined(BSP_MCU_RX72N) + #include "./src/targets/rx72n/r_gpio_rx72n.h" +#else + #error "This MCU is not supported by the current r_gpio_rx module." +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define GPIO_RX_VERSION_MAJOR (3) +#define GPIO_RX_VERSION_MINOR (50) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The gpio_port_t and gpio_port_pin_t enums are located in the 'targets' folder for each MCU. For example, to see + * these enums for a RX111 look at the following file: r_gpio_rx/src/targets/rx111/r_gpio_rx111.h + */ + +/* Levels that can be set and read for individual pins. */ +typedef enum +{ + GPIO_LEVEL_LOW = 0, + GPIO_LEVEL_HIGH +} gpio_level_t; + +/* Options that can be used with the R_GPIO_PortDirectionSet() and R_GPIO_PinDirectionSet() functions. */ +typedef enum +{ + GPIO_DIRECTION_INPUT = 0, + GPIO_DIRECTION_OUTPUT +} gpio_dir_t; + +/* Commands that can be used with the R_GPIO_PinControl() function. This list will vary depending on the MCU chosen. */ +typedef enum +{ + GPIO_CMD_OUT_CMOS = 0, + GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN, + GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN, + GPIO_CMD_IN_PULL_UP_DISABLE, + GPIO_CMD_IN_PULL_UP_ENABLE, + GPIO_CMD_ASSIGN_TO_PERIPHERAL, + GPIO_CMD_ASSIGN_TO_GPIO, + GPIO_CMD_DSCR_DISABLE, + GPIO_CMD_DSCR_ENABLE, + GPIO_CMD_DSCR2_DISABLE, + GPIO_CMD_DSCR2_ENABLE +} gpio_cmd_t; + +/* Function return type. */ +typedef enum +{ + GPIO_SUCCESS = 0, + GPIO_ERR_INVALID_MODE, // The mode specified cannot be applied to this pin + GPIO_ERR_INVALID_CMD // The input command is not supported +} gpio_err_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_GPIO_PortWrite(gpio_port_t port, uint8_t value); +uint8_t R_GPIO_PortRead(gpio_port_t port); +void R_GPIO_PortDirectionSet(gpio_port_t port, gpio_dir_t dir, uint8_t mask); +void R_GPIO_PinWrite(gpio_port_pin_t pin, gpio_level_t level); +gpio_level_t R_GPIO_PinRead(gpio_port_pin_t pin); +void R_GPIO_PinDirectionSet(gpio_port_pin_t pin, gpio_dir_t dir); +gpio_err_t R_GPIO_PinControl(gpio_port_pin_t pin, gpio_cmd_t cmd); +uint32_t R_GPIO_GetVersion(void); + +#endif /* GPIO_RX_INTERFACE_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/readme.txt new file mode 100644 index 000000000..87c7b140f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/readme.txt @@ -0,0 +1,50 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS MODULE FOR MORE INFORMATION + +r_gpio_rx +========= + +Overview +-------- +This code implements a General Purpose Input/Output driver. Common features such as reading, writing, and setting the +direction of ports and pins are supported. Enabling features such as open-drain outputs and internal pull-ups are also +supported. + +Features +-------- +* Read ports and pins +* Write ports and pins +* Set ports and pins as inputs and outputs +* Enable features of pins such as internal pull-ups or open-drain outputs + +File Structure +-------------- +r_gpio_rx +| readme.txt +| r_gpio_rx_if.h +| ++---doc +| +---ja +| | r01an1721jj{VERSION_NUMBER}-rx-gpio.pdf +| +---en +| r01an1721ej{VERSION_NUMBER}-rx-gpio.pdf +| ++---ref +| r_gpio_rx_config_reference.h +| +\---src + | r_gpio_rx.c + | + \---targets + +---rx110 + | r_gpio_rx110.c + | r_gpio_rx110.h + | + +---rx111 + | r_gpio_rx111.c + | r_gpio_rx111.h + | + : + +r_config + r_gpio_rx_config.h + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h new file mode 100644 index 000000000..bfeb0766e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h @@ -0,0 +1,46 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c new file mode 100644 index 000000000..8ddb93940 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c @@ -0,0 +1,573 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx.c +* Description : General Purpose Input/Output driver for RX MCUs. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 21.11.2014 1.40 Added support for RX113 +* : 02.09.2015 1.50 Added support for RX71M +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR_ENABLE/_DISABLE commands. +* : 01.10.2016 2.10 Added support for RX65N +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR2_ENABLE/_DISABLE commands. +* : 19.12.2016 2.20 Added support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Added support for RX65N-2M, RX130-512KB. +* : 28.09.2018 2.40 Added support for RX66T. +* Update according to GSCE Code Checker +* : 01.02.2019 2.50 Added support for RX72T, RX65N-64pin +* Update according to GSCE Code Checker +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Modified comment of API function to Doxygen style. +* : 30.12.2019 3.40 Added support RX72N, RX66N. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +* Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Typedef definitions +***********************************************************************************************************************/ +/* Different pin output options. */ +typedef enum +{ + GPIO_PIN_OUT_CMOS = 0, + GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN = 1, + GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN = 2 +} gpio_pin_output_t; + +/*********************************************************************************************************************** +* Private global variables and functions +***********************************************************************************************************************/ +uint8_t volatile * gpio_port_addr_get(uint8_t volatile * base_addr, uint16_t index); +bool gpio_pin_function_check(uint8_t const * check_array, uint8_t port_number, uint8_t pin_number); +void gpio_set_output_type(gpio_port_pin_t pin, gpio_pin_output_t out_type); + +/*********************************************************************************************************************** +* Export global variables +***********************************************************************************************************************/ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + extern const uint8_t g_gpio_open_drain_n_support[]; + extern const uint8_t g_gpio_open_drain_p_support[]; + extern const uint8_t g_gpio_pull_up_support[]; + #if defined (GPIO_DSCR_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr_support[]; + #endif + #if defined (GPIO_DSCR2_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr2_support[]; + #endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortWrite +********************************************************************************************************************//** +* @brief This function writes the levels of all pins on a port. +* @param[in] port - Which port to write to. See Section 2.10.1, Ports. +* @param[in] value - The value to write to the port. Each bit corresponds to a pin on the port (e.g. bit 0 of value +* will be written to pin 0 on supplied port) +* @details The input value will be written to the specified port. Each bit in the value parameter corresponds to a pin +* on the port. For example, bit 7 of write value corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* @note In the interest of performance, this function does not automatically check for non-existent pins when the +* port-wide write function is called. It is up to the user’s application to insure that only valid pins are written to. +* +*/ +void R_GPIO_PortWrite (gpio_port_t port, uint8_t value) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)port); + + /* Write to the selected port. */ + *podr = value; +} /* End of function R_GPIO_PortWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortRead +********************************************************************************************************************//** +* @brief This function reads the levels of all pins on a port. +* @param[in] port - Which port to read. See Section 2.10.1, Ports. +* @return The value of the port. +* @details The specified port will be read, and the levels for all the pins will be returned. Each bit in the returned +* value corresponds to a pin on the port. For example, bit 7 of read value corresponds to pin 7, bit 6 corresponds to +* pin 6, and so forth. +*/ +uint8_t R_GPIO_PortRead (gpio_port_t port) +{ + /* PIDR register addresses are incremental in memory starting with PORT0.PIDR. Even if a port is not available + * on this MCU, the address is reserved. */ + + /* Read the selected port. */ + return *gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)port); +} /* End of function R_GPIO_PortRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortDirectionSet +********************************************************************************************************************//** +* @brief This function sets multiple pins on a port to inputs or outputs at once. +* @param[in] port - Which port to use. See Section 2.10.1, Ports. +* @param[in] dir - Which direction to use. See Section 2.10.5, Pin Direction. +* @param[in] mask - Mask of which pins to change. 1 = set direction, 0 = do not change. +* @details Multiple pins on a port can be set to inputs or outputs at once. Each bit in the mask parameter corresponds +* to a pin on the port. For example, bit 7 of mask corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* If a bit is set to 1 then the corresponding pin will be changed to an input or output as specified by the dir +* parameter. If a bit is set to 0 then the direction of the pin will not be changed. +* @note This function does not allow the user to specify the use of special modes such as input pull-up resistors or +* open-drain outputs. To enable these modes use the R_GPIO_PinControl() function. +*/ +void R_GPIO_PortDirectionSet (gpio_port_t port, gpio_dir_t dir, uint8_t mask) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)port); + + /* Write to the selected register. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) & (~mask)); + } + else + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) | mask); + } +} /* End of function R_GPIO_PortDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinWrite +********************************************************************************************************************//** +* @brief This function sets the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] level - What level to set the pin to. +* @details Pins can either be set as high (‘1’) or low (‘0’). +*/ +void R_GPIO_PinWrite (gpio_port_pin_t pin, gpio_level_t level) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_LEVEL_LOW == level) + { + /* Set value to port */ + *podr = (uint8_t)((*podr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Set value to port */ + *podr = (uint8_t)((*podr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinRead +********************************************************************************************************************//** +* @brief This function reads the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @return The level of the specified pin. +* @details The specified pin will be read and the level returned. +*/ +gpio_level_t R_GPIO_PinRead (gpio_port_pin_t pin) +{ + uint8_t volatile * pidr; + + /* PIDR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pidr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)pin); + + /* Mask to get the individual bit. */ + if (((*pidr) & (1 << (pin & 0x00FFu))) != 0) + { + return GPIO_LEVEL_HIGH; + } + else + { + return GPIO_LEVEL_LOW; + } +} /* End of function R_GPIO_PinRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinDirectionSet +********************************************************************************************************************//** +* @brief This function sets the direction (input/output) of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] dir - Which direction to use for this pin. See Section 2.10.5, Pin Direction. +* @details This function sets pins as inputs or outputs. For enabling other settings such as open-drain outputs or +* internal pull-ups see the R_GPIO_PinControl() function. +*/ +void R_GPIO_PinDirectionSet (gpio_port_pin_t pin, gpio_dir_t dir) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinControl +********************************************************************************************************************//** +* @brief This function allows the user to control various settings of a pin. +* @param[in] pin -Which pin to use. See Section 2.10.2, Pins +* @param[in] cmd - Which command to execute for this pin. See Section 2.10.6, Control Commands for available commands. +* @retval [GPIO_SUCCESS] Successful; pin modified as specified by command. +* @retval [GPIO_ERR_INVALID_MODE] Error; this pin does not support the specified option. +* @retval [GPIO_ERR_INVALID_CMD] Error; the input command is not supported. +* @details Depending on the MCU, pins have various settings that can be configured other than the direction and +* output level. Some examples include enabling open-drain outputs, internal pull-ups, and changing drive capacity +* levels. These features vary per chip which means that the options for this function will also vary. +*/ +gpio_err_t R_GPIO_PinControl (gpio_port_pin_t pin, gpio_cmd_t cmd) +{ + gpio_err_t err; + uint8_t volatile * addr; + uint8_t pin_number; + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + uint8_t port_number; + + /* Get port number */ + port_number = (uint8_t)(pin >> 8); +#endif + + err = GPIO_SUCCESS; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + switch (cmd) + { + +#if defined (GPIO_DSCR_IS_SUPPORTED) + case GPIO_CMD_DSCR_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + case GPIO_CMD_DSCR_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* GPIO_DSCR_IS_SUPPORTED */ +#if defined (GPIO_DSCR2_IS_SUPPORTED) + case GPIO_CMD_DSCR2_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_DSCR2_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* GPIO_DSCR2_IS_SUPPORTED */ + case GPIO_CMD_ASSIGN_TO_GPIO: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_ASSIGN_TO_PERIPHERAL: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_IN_PULL_UP_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_IN_PULL_UP_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_OUT_CMOS: + { + gpio_set_output_type(pin, GPIO_PIN_OUT_CMOS); + + break; + } + + case GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_n_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN); + + break; + } + case GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN: + { + #if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_p_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } + #endif + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN); + + break; + } + + default: + { + err = GPIO_ERR_INVALID_CMD; + break; + } + } + + return err; +} /* End of function R_GPIO_PinControl */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_GetVersion +********************************************************************************************************************//** +* @brief Returns the current version of this API. +* @return Version of this API. +* @details This function will return the version of the currently running API. The version number is encoded where +* the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example, +* Version 4.25 would be returned as 0x00040019. +*/ +uint32_t R_GPIO_GetVersion (void) +{ + /* These version macros are defined in r_gpio_rx_if.h. */ + return ((((uint32_t)GPIO_RX_VERSION_MAJOR) << 16) | (uint32_t)GPIO_RX_VERSION_MINOR); +} /* End of function R_GPIO_GetVersion */ + +/*********************************************************************************************************************** +* Function Name: gpio_port_addr_get +* Description : Get the address for a port register based on a base port register address. +* Arguments : base_addr - +* First port register of this type (e.g. &PORT0.PODR.BYTE) +* index - +* Index off the base. (e.g. for PORT4 it would be 0x0400) +* Return Value : Address of the register that was requested +***********************************************************************************************************************/ + +R_BSP_PRAGMA_INLINE (gpio_port_addr_get) +uint8_t volatile * gpio_port_addr_get (uint8_t volatile * base_addr, uint16_t index) +{ + /* Add port number to 'index' to correct register. */ + return (uint8_t volatile *)((((uint32_t)index >> 8) & 0x000000FFuL) + (uint32_t)base_addr); +} /* End of function gpio_port_addr_get */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +/*********************************************************************************************************************** +* Function Name: gpio_pin_function_check +* Description : Checks to see if a pin supports a certain function. +* Arguments : check_array - +* Which support array to use. +* port_number - +* Which port to use. +* pin_number - +* Which pin to use. +* Return Value : true - +* Functionality is supported on this pin. +* false - +* Functionality is not supported on this pin. +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE (gpio_pin_function_check) +bool gpio_pin_function_check (uint8_t const * check_array, uint8_t port_number, uint8_t pin_number) +{ + if ((check_array[port_number] & (1 << pin_number)) != 0) + { + return true; + } + else + { + return false; + } +} /* End of function gpio_pin_function_check */ +#endif + +/*********************************************************************************************************************** +* Function Name: gpio_set_output_type +* Description : Configures pin output type (e.g. CMOS, open-drain) +* Arguments : pin - +* Which pin to change output type for +* out_type - +* What output type to use for this pin +* Return Value : None +***********************************************************************************************************************/ +void gpio_set_output_type (gpio_port_pin_t pin, gpio_pin_output_t out_type) +{ + uint8_t volatile * addr; + uint8_t pin_number; + uint8_t bit_offset; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + /* 'pin' is multiplied by 2 because the ODR0 and ODR1 registers are staggered. This means that PORT0.ODR0 + * and PORT1.ODR0 are separated by 2 bytes instead of 1 as with the other port registers. */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUT_TYPE, (uint16_t)(((uint16_t)pin)*2)); + + /* ODR bit fields are 2-bits a piece. This means bits 0-3 are in the 1st byte (ODR0) and bits 4-7 are in + * the 2nd byte (ODR1). + */ + if (pin_number > 3) + { + /* Bit field is in ODR1. Increment address by 1 for ODR1 register for this port. */ + addr += 1; + + /* Subtract 4 from pin number since pins 4-7 are stored in ODR1 which is an 8-bit register. + * Multiple pin number by 2 since each pin is represented by 2 bits. + */ + bit_offset = (uint8_t)((pin_number - 4) * 2); + } + else + { + /* Multiple pin number by 2 since each pin is represented by 2 bits. */ + bit_offset = (uint8_t)(pin_number * 2); + } + + /* Clear the bits we intend to change. */ + *addr = (uint8_t)((*addr) & (~(3 << bit_offset))); + + /* Set the bits again if needed. */ + *addr = (uint8_t)((*addr) | (((uint8_t)out_type) << bit_offset)); +} /* End of function gpio_set_output_type */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c new file mode 100644 index 000000000..2d8a61f6f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c @@ -0,0 +1,206 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx72n.c +* Description : Data for r_gpio_rx driver specific to RX72N. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" + +#if defined(BSP_MCU_RX72N) + +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* These arrays hold which pins have extra functionality. For example, not all pins have the option of enabling + * open-drain N-channel output instead of the default CMOS output. Each entry in the array corresponds to a port. + * Each bit in each entry corresponds to a pin on that port. If bit 3 of array entry [4] was set to 1 then that would + * mean that PORT 4 PIN 3 supported the feature that array represented. + * + * These arrays are only used when GPIO_CFG_PARAM_CHECKING_ENABLE is set to 1 (checking enabled). If you know that + * your code does not need to check the pins then you can set this macro to 0 and save a little execution time + * and ROM space. + * + * Note: These arrays are defined for the largest package part. For smaller packages where some pins do not exist, + * pin checking is filtered by the enumerated port_pin list for that package as defined in r_gpio_rx72n.h. + */ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0xAF, // P0: P00 to P03, P05, P07 + 0xFF, // P1: P10 to P17 + 0xFF, // P2: P20 to P27 + 0xDF, // P3: P30 to P34, P36, P37 + 0xFF, // P4: P40 to P47 + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFF, // P7: P70 to P77 + 0xFF, // P8: P80 to P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x3F, // PF: PF0 to PF5 + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x2F, // PJ: PJ0 to PJ3, PJ5 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, // P0: - + 0x00, // P1: - + 0x00, // P2: - + 0x00, // P3: - + 0x00, // P4: - + 0x00, // P5: - + 0x00, // P6: - + 0x00, // P7: - + 0x00, // P8: - + 0x00, // P9: - + 0x00, // PA: - + 0x00, // PB: - + 0x00, // PC: - + 0x00, // PD: - + 0x02, // PE: PE1 + 0x00, // PF: - + 0x00, // PG: - + 0x00, // PH: - + 0x00, // PJ: - + 0x00, // PK: - + 0x00, // PL: - + 0x00, // PM: - + 0x00, // PN: - + 0x00, // PQ: - +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0xAF, // P0: P00 to P03, P05, P07 + 0xFF, // P1: P10 to P17 + 0xFF, // P2: P20 to P27 + 0xDF, // P3: P30 to P34, P36, P37 + 0xFF, // P4: P40 to P47 + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFF, // P7: P70 to P77 + 0xFF, // P8: P80 to P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x3F, // PF: PF0 to PF5 + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x2F, // PJ: PJ0 to PJ3, PJ5 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_dscr_support[GPIO_INFO_NUM_PORTS] = +{ + 0x07, // P0: P00 to P02 + 0x1E, // P1: P11 to P14 + 0x80, // P2: P27 + 0x00, // P3: - + 0x00, // P4: - + 0xF7, // P5: P50 to P52, P54 to P57 + 0x00, // P6: - + 0xF4, // P7: P72, P74 to P77 + 0x3F, // P8: P80 to P85 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x00, // PF: - + 0x03, // PG: PG0, PG1 + 0xFF, // PH: PH0 to PH7 + 0x07, // PJ: PJ0 to PJ2 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_dscr2_support[GPIO_INFO_NUM_PORTS] = +{ + 0x07, // P0: P00 to P02 + 0x9E, // P1: P11 to P14, P17 + 0x8F, // P2: P20 to P23, P27 + 0x03, // P3: P30, P31 + 0x00, // P4: - + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFD, // P7: P70, P72 to P77 + 0xBF, // P8: P80 to P85, P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x00, // PF: - + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x07, // PJ: PJ0 to PJ2 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +#endif /* GPIO_CFG_PARAM_CHECKING_ENABLE */ + +#endif /* BSP_MCU_RX72N */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h new file mode 100644 index 000000000..6734a9632 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h @@ -0,0 +1,810 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx72n.h +* Description : Specifics for the r_gpio_rx driver for the RX72N. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ +#ifndef GPIO_RX72N +#define GPIO_RX72N + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +#if defined(BSP_MCU_RX72N) /* Prevents the compiler from finding multiple definitions of constant in this file. */ + +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* General information about number of ports and pins on this device. */ +#define GPIO_INFO_NUM_PORTS (24) + +#if (BSP_PACKAGE_PINS == 224) + #define GPIO_INFO_NUM_PINS (183) +#elif (BSP_PACKAGE_PINS == 176) + #define GPIO_INFO_NUM_PINS (137) +#elif (BSP_PACKAGE_PINS == 145 || BSP_PACKAGE_PINS == 144) + #define GPIO_INFO_NUM_PINS (112) +#elif (BSP_PACKAGE_PINS == 100) + #define GPIO_INFO_NUM_PINS (79) +#else + #error "r_gpio_rx does not have information about this RX72N package. Please update r_gpio_rx72N.h" +#endif + +/* For testing we will allocate virtual IO ports. */ +#if !defined(GPIO_TESTING) +/* Base registers used for offsets on output data registers. */ +#define GPIO_PRV_BASE_ADDR_OUTPUT ((uint8_t volatile *)&PORT0.PODR.BYTE) +/* Base registers used for offsets on input data registers. */ +#define GPIO_PRV_BASE_ADDR_INPUT ((uint8_t volatile *)&PORT0.PIDR.BYTE) +/* Base registers used for offsets on direction registers. */ +#define GPIO_PRV_BASE_ADDR_DIRECTION ((uint8_t volatile *)&PORT0.PDR.BYTE) +/* Base registers used for offsets on mode registers. */ +#define GPIO_PRV_BASE_ADDR_MODE ((uint8_t volatile *)&PORT0.PMR.BYTE) +/* Base registers used for offsets on output type registers. */ +#define GPIO_PRV_BASE_ADDR_OUT_TYPE ((uint8_t volatile *)&PORT0.ODR0.BYTE) +/* Base registers used for offsets on pull-up registers. */ +#define GPIO_PRV_BASE_ADDR_PULL_UP ((uint8_t volatile *)&PORT0.PCR.BYTE) +/* Base registers used for offsets on drive capacity control registers. */ +#define GPIO_PRV_BASE_ADDR_DSCR ((uint8_t volatile *)&PORT0.DSCR.BYTE) +/* Base registers used for offsets on drive capacity control registers 2. (high-speed interface high-drive) */ +#define GPIO_PRV_BASE_ADDR_DSCR2 ((uint8_t volatile *)&PORT0.DSCR2.BYTE) + +#endif + +#define GPIO_DSCR_IS_SUPPORTED /* High-drive output is supported for the RX72N */ +#define GPIO_DSCR2_IS_SUPPORTED /* Large current output, high-drive output is supported for the RX72N */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (BSP_PACKAGE_PINS == 224) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200, + GPIO_PORT_K = 0x1300, + GPIO_PORT_L = 0x1400, + GPIO_PORT_M = 0x1500, + GPIO_PORT_N = 0x1600, + GPIO_PORT_Q = 0x1700, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFF, /* Available pins: P10 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0xFF, /* Available pins: P50 to P57 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xFF, /* Available pins: P80 to P87 */ + GPIO_PORT9_PIN_MASK = 0xFF, /* Available pins: P90 to P97 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x3F, /* Available pins: PF0 to PF5 */ + GPIO_PORTG_PIN_MASK = 0xFF, /* Available pins: PG0 to PG7 */ + GPIO_PORTH_PIN_MASK = 0xFF, /* Available pins: PH0 to PH7 */ + GPIO_PORTJ_PIN_MASK = 0x2F, /* Available pins: PJ0 to PJ3, PJ5 */ + GPIO_PORTK_PIN_MASK = 0xFF, /* Available pins: PK0 to PK7 */ + GPIO_PORTL_PIN_MASK = 0xFF, /* Available pins: PL0 to PL7 */ + GPIO_PORTM_PIN_MASK = 0xFF, /* Available pins: PM0 to PM7 */ + GPIO_PORTN_PIN_MASK = 0x3F, /* Available pins: PN0 to PN5 */ + GPIO_PORTQ_PIN_MASK = 0xFF, /* Available pins: PQ0 to PQ7 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_5_PIN_7 = 0x0507, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_4 = 0x0804, + GPIO_PORT_8_PIN_5 = 0x0805, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_9_PIN_7 = 0x0907, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_0 = 0x0F00, + GPIO_PORT_F_PIN_1 = 0x0F01, + GPIO_PORT_F_PIN_2 = 0x0F02, + GPIO_PORT_F_PIN_3 = 0x0F03, + GPIO_PORT_F_PIN_4 = 0x0F04, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_G_PIN_0 = 0x1000, + GPIO_PORT_G_PIN_1 = 0x1001, + GPIO_PORT_G_PIN_2 = 0x1002, + GPIO_PORT_G_PIN_3 = 0x1003, + GPIO_PORT_G_PIN_4 = 0x1004, + GPIO_PORT_G_PIN_5 = 0x1005, + GPIO_PORT_G_PIN_6 = 0x1006, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_H_PIN_4 = 0x1104, + GPIO_PORT_H_PIN_5 = 0x1105, + GPIO_PORT_H_PIN_6 = 0x1106, + GPIO_PORT_H_PIN_7 = 0x1107, + GPIO_PORT_J_PIN_0 = 0x1200, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_2 = 0x1202, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, + GPIO_PORT_K_PIN_0 = 0x1300, + GPIO_PORT_K_PIN_1 = 0x1301, + GPIO_PORT_K_PIN_2 = 0x1302, + GPIO_PORT_K_PIN_3 = 0x1303, + GPIO_PORT_K_PIN_4 = 0x1304, + GPIO_PORT_K_PIN_5 = 0x1305, + GPIO_PORT_K_PIN_6 = 0x1306, + GPIO_PORT_K_PIN_7 = 0x1307, + GPIO_PORT_L_PIN_0 = 0x1400, + GPIO_PORT_L_PIN_1 = 0x1401, + GPIO_PORT_L_PIN_2 = 0x1402, + GPIO_PORT_L_PIN_3 = 0x1403, + GPIO_PORT_L_PIN_4 = 0x1404, + GPIO_PORT_L_PIN_5 = 0x1405, + GPIO_PORT_L_PIN_6 = 0x1406, + GPIO_PORT_L_PIN_7 = 0x1407, + GPIO_PORT_M_PIN_0 = 0x1500, + GPIO_PORT_M_PIN_1 = 0x1501, + GPIO_PORT_M_PIN_2 = 0x1502, + GPIO_PORT_M_PIN_3 = 0x1503, + GPIO_PORT_M_PIN_4 = 0x1504, + GPIO_PORT_M_PIN_5 = 0x1505, + GPIO_PORT_M_PIN_6 = 0x1506, + GPIO_PORT_M_PIN_7 = 0x1507, + GPIO_PORT_N_PIN_0 = 0x1600, + GPIO_PORT_N_PIN_1 = 0x1601, + GPIO_PORT_N_PIN_2 = 0x1602, + GPIO_PORT_N_PIN_3 = 0x1603, + GPIO_PORT_N_PIN_4 = 0x1604, + GPIO_PORT_N_PIN_5 = 0x1605, + GPIO_PORT_Q_PIN_0 = 0x1700, + GPIO_PORT_Q_PIN_1 = 0x1701, + GPIO_PORT_Q_PIN_2 = 0x1702, + GPIO_PORT_Q_PIN_3 = 0x1703, + GPIO_PORT_Q_PIN_4 = 0x1704, + GPIO_PORT_Q_PIN_5 = 0x1705, + GPIO_PORT_Q_PIN_6 = 0x1706, + GPIO_PORT_Q_PIN_7 = 0x1707, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 176) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFF, /* Available pins: P10 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0xFF, /* Available pins: P50 to P57 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xFF, /* Available pins: P80 to P87 */ + GPIO_PORT9_PIN_MASK = 0xFF, /* Available pins: P90 to P97 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x3F, /* Available pins: PF0 to PF5 */ + GPIO_PORTG_PIN_MASK = 0xFF, /* Available pins: PG0 to PG7 */ + GPIO_PORTJ_PIN_MASK = 0x2F, /* Available pins: PJ0 to PJ3, PJ5 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_5_PIN_7 = 0x0507, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_4 = 0x0804, + GPIO_PORT_8_PIN_5 = 0x0805, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_9_PIN_7 = 0x0907, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_0 = 0x0F00, + GPIO_PORT_F_PIN_1 = 0x0F01, + GPIO_PORT_F_PIN_2 = 0x0F02, + GPIO_PORT_F_PIN_3 = 0x0F03, + GPIO_PORT_F_PIN_4 = 0x0F04, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_G_PIN_0 = 0x1000, + GPIO_PORT_G_PIN_1 = 0x1001, + GPIO_PORT_G_PIN_2 = 0x1002, + GPIO_PORT_G_PIN_3 = 0x1003, + GPIO_PORT_G_PIN_4 = 0x1004, + GPIO_PORT_G_PIN_5 = 0x1005, + GPIO_PORT_G_PIN_6 = 0x1006, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_J_PIN_0 = 0x1200, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_2 = 0x1202, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 145 || BSP_PACKAGE_PINS == 144) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x7F, /* Available pins: P50 to P56 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xCF, /* Available pins: P80 to P83, P86, P87 */ + GPIO_PORT9_PIN_MASK = 0x0F, /* Available pins: P90 to P93 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x32, /* Available pins: PF5 */ + GPIO_PORTJ_PIN_MASK = 0x40, /* Available pins: PJ3, PJ5 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 100) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xA0, /* Available pins: P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x3F, /* Available pins: P50 to P55 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTJ_PIN_MASK = 0x08, /* Available pins: PJ3 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_J_PIN_3 = 0x1203, +} gpio_port_pin_t; + +#endif /* BSP_PACKAGE_PINS */ + + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* BSP_MCU_RX72N */ +#endif /* GPIO_RX72N */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/Pin.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/Pin.c new file mode 100644 index 000000000..5dd8ec142 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/Pin.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.c +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Pins_Create +* Description : This function initializes Smart Configurator pins +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Pins_Create(void) +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set CLKOUT25M pin */ + MPC.P56PFS.BYTE = 0x2AU; + PORT5.PMR.BYTE |= 0x40U; + + /* Set RXD2 pin */ + MPC.P12PFS.BYTE = 0x0AU; + PORT1.PMR.BYTE |= 0x04U; + + /* Set RXD9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BYTE |= 0x40U; + + /* Set TXD2 pin */ + PORT1.PODR.BYTE |= 0x08U; + MPC.P13PFS.BYTE = 0x0AU; + PORT1.PDR.BYTE |= 0x08U; + // PORT1.PMR.BIT.B3 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD9 pin */ + PORTB.PODR.BYTE |= 0x80U; + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PDR.BYTE |= 0x80U; + // PORTB.PMR.BIT.B7 = 1U; // Please set the PMR bit after TE bit is set to 1. + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/Pin.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/Pin.h new file mode 100644 index 000000000..563b57a07 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/Pin.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.h +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +#ifndef PIN_H +#define PIN_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Pins_Create(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_pinset.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_pinset.h new file mode 100644 index 000000000..33cd297df --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_pinset.h @@ -0,0 +1,34 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_pinset.h.h +* Version : 1.0.1 +* Description : Declares all pin code headers into a single file +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +#ifndef R_PINSET_H +#define R_PINSET_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" + +#endif /* R_PINSET_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_sci_rx_pinset.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_sci_rx_pinset.c new file mode 100644 index 000000000..8b23ce348 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_sci_rx_pinset.c @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.c +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" +#include "platform.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI2 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI2() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD2/SMISO2 pin */ + MPC.P12PFS.BYTE = 0x0AU; + PORT1.PMR.BIT.B2 = 1U; + + /* Set TXD2/SMOSI2 pin */ + MPC.P13PFS.BYTE = 0x0AU; + PORT1.PMR.BIT.B3 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI9 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI9() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD9/SMISO9/SSCL9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B6 = 1U; + + /* Set TXD9/SMOSI9/SSDA9 pin */ + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B7 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_sci_rx_pinset.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_sci_rx_pinset.h new file mode 100644 index 000000000..2212975ba --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_pincfg/r_sci_rx_pinset.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.h +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +#ifndef R_SCI_RX_H +#define R_SCI_RX_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +void R_SCI_PinSet_SCI2(); +void R_SCI_PinSet_SCI9(); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/r_sci_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/r_sci_rx_if.h new file mode 100644 index 000000000..c85c67cc3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/r_sci_rx_if.h @@ -0,0 +1,313 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_if.h +* Description : Functions for using SCI on RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Bumped revision for RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added RX113 support +* 11.03.2015 1.40 Consolidated with r_sci_rx64m and added support for RX71M +* 11.05.2015 1.60 Added RX231 support +* 30.09.2015 1.70 Added RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added RX24U support +* SCI_CMD_EN_TEI was Changed to ineffective, because it is meaningless command. +* 07.03.2017 2.00 Fixed a bug that send/receive is incorrect when changed setting when FIFO enabled. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 31.10.2017 2.01 Added the demo for RX65N, RX65N-2M. +* 28.09.2018 2.10 Added support RX66T +* Added SCI_CMD_COMPARE_RECEIVED_DATA command +* Added SCI_EVT_RX_CHAR_MATCH for receiving data match event +* Fixed section layout follow GSCE 5.0 +* 16.11.2018 2.11 Added XML document number +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support RX23W +* 15.08.2019 3.20 Added support RX72M +* 16.09.2019 3.21 Fixed issue in RX631/RX63N sci_initialize_ints() +* 25.11.2019 3.30 Added support RX13T. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ + +#ifndef SCI_IF_H +#define SCI_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_config.h" /* SCI config definitions */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define SCI_VERSION_MAJOR (3) +#define SCI_VERSION_MINOR (50) + +#define SCI_CLK_INT (0x00U) /* use internal clock for baud generation */ +#define SCI_CLK_EXT8X (0x03U) /* use external clock 8x baud rate (ASYNC) */ +#define SCI_CLK_EXT16X (0x02U) /* use external clock 16x baud rate (ASYNC) */ +#define SCI_DATA_7BIT (0x40U) +#define SCI_DATA_8BIT (0x00U) +#define SCI_PARITY_ON (0x20U) +#define SCI_PARITY_OFF (0x00U) +#define SCI_ODD_PARITY (0x10U) +#define SCI_EVEN_PARITY (0x00U) +#define SCI_STOPBITS_2 (0x08U) +#define SCI_STOPBITS_1 (0x00U) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +typedef enum e_sci_ch // SCI channel numbers +{ + SCI_CH0=0, + SCI_CH1, + SCI_CH2, + SCI_CH3, + SCI_CH4, + SCI_CH5, + SCI_CH6, + SCI_CH7, + SCI_CH8, + SCI_CH9, + SCI_CH10, + SCI_CH11, + SCI_CH12, + SCI_NUM_CH +} sci_ch_t; + + +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_MAX, // End of modes currently supported +} sci_mode_t; + + +typedef enum e_sci_err /* SCI API error codes */ +{ + SCI_SUCCESS=0, + SCI_ERR_BAD_CHAN, // non-existent channel number + SCI_ERR_OMITTED_CHAN, // SCI_CHx_INCLUDED is 0 in config.h + SCI_ERR_CH_NOT_CLOSED, // chan still running in another mode + SCI_ERR_BAD_MODE, // unsupported or incorrect mode for channel + SCI_ERR_INVALID_ARG, // argument is not one of the predefined values + SCI_ERR_NULL_PTR, // received null ptr; missing required argument + SCI_ERR_XCVR_BUSY, // cannot start data transfer; transceiver busy + + /* Asynchronous mode only */ + SCI_ERR_QUEUE_UNAVAILABLE, // can't open tx or rx queue or both + SCI_ERR_INSUFFICIENT_SPACE, // not enough space in transmit queue + SCI_ERR_INSUFFICIENT_DATA, // not enough data in receive queue + + /* Synchronous/SSPI modes only */ + SCI_ERR_XFER_NOT_DONE // data transfer still in progress +} sci_err_t; + + +/* CHANNEL CONTROL BLOCK HANDLE */ + +typedef struct st_sci_ch_ctrl * sci_hdl_t; + + +/* SCI_OPEN() ARGUMENT DEFINITIONS (do NOT change values) */ + +typedef enum e_sci_spi_mode +{ + SCI_SPI_MODE_OFF = 1, /* channel is in synchronous mode */ + + SCI_SPI_MODE_0 = 0x80, /* SPMR Register CKPH=1, CKPOL=0 + Mode 0: 00 CPOL=0 resting lo, CPHA=0 leading edge/rising */ + SCI_SPI_MODE_1 = 0x40, /* SPMR Register CKPH=0, CKPOL=1 + Mode 1: 01 CPOL=0 resting lo, CPHA=1 trailing edge/falling */ + SCI_SPI_MODE_2 = 0xC0, /* SPMR Register CKPH=1, CKPOL=1 + Mode 2: 10 CPOL=1 resting hi, CPHA=0 leading edge/falling */ + SCI_SPI_MODE_3 = 0x00 /* SPMR Register CKPH=0, CKPOL=0 + Mode 3: 11 CPOL=1 resting hi, CPHA=1 trailing edge/rising */ +} sci_spi_mode_t; + + +/* Open() p_cfg structure when mode=SCI_MODE_ASYNC */ +typedef struct st_sci_uart +{ + uint32_t baud_rate; // ie 9600, 19200, 115200 + uint8_t clk_src; // use SCI_CLK_INT/EXT8X/EXT16X + uint8_t data_size; // use SCI_DATA_nBIT + uint8_t parity_en; // use SCI_PARITY_ON/OFF + uint8_t parity_type; // use SCI_ODD/EVEN_PARITY + uint8_t stop_bits; // use SCI_STOPBITS_1/2 + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_uart_t; + + +/* Open() p_cfg structure when mode = SCI_MODE_SYNC or SCI_MODE_SSPI */ +typedef struct st_sci_sync_sspi +{ + sci_spi_mode_t spi_mode; // clock polarity and phase; unused for sync + uint32_t bit_rate; // ie 1000000 for 1Mbps + bool msb_first; + bool invert_data; + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_sync_sspi_t; + +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; +} sci_cfg_t; + + +/* CALLBACK FUNCTION ARGUMENT DEFINITIONS */ + +typedef enum e_sci_cb_evt // callback function events +{ + /* Async Events */ + SCI_EVT_TEI, // TEI interrupt occurred; transmitter is idle + SCI_EVT_RX_CHAR, // received a character; already placed in queue + SCI_EVT_RX_CHAR_MATCH, // received a matched character; already placed in queue + SCI_EVT_RXBUF_OVFL, // rx queue is full; can't save anymore data + SCI_EVT_FRAMING_ERR, // receiver hardware framing error + SCI_EVT_PARITY_ERR, // receiver hardware parity error + + /* SSPI/Sync Events */ + SCI_EVT_XFER_DONE, // transfer completed + SCI_EVT_XFER_ABORTED, // transfer aborted + + /* Common Events */ + SCI_EVT_OVFL_ERR // receiver hardware overrun error +} sci_cb_evt_t; + +typedef struct st_sci_cb_args // callback arguments +{ + sci_hdl_t hdl; + sci_cb_evt_t event; + uint8_t byte; // byte read when error occurred (unused for TEI, XFER_DONE) + uint8_t num; // Number of bytes were stored to queue (used only async(FIFO)) +} sci_cb_args_t; + + +/* SCI_CONTROL() ARGUMENT DEFINITIONS */ + +/* commands */ +typedef enum e_sci_cmd +{ + /* All modes */ + SCI_CMD_CHANGE_BAUD, /* change baud/bit rate */ +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || (SCI_CFG_CH8_FIFO_INCLUDED) || (SCI_CFG_CH9_FIFO_INCLUDED) || (SCI_CFG_CH10_FIFO_INCLUDED) || (SCI_CFG_CH11_FIFO_INCLUDED)) + SCI_CMD_CHANGE_TX_FIFO_THRESH, /* change TX FIFO threshold */ + SCI_CMD_CHANGE_RX_FIFO_THRESH, /* change RX FIFO threshold */ +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + SCI_CMD_SET_RXI_PRIORITY, /* change RXI priority level */ + SCI_CMD_SET_TXI_PRIORITY, /* change TXI priority level */ +#endif + + /* Async commands */ + SCI_CMD_EN_NOISE_CANCEL, /* enable noise cancellation */ + SCI_CMD_EN_TEI, /* SCI_CMD_EN_TEI is obsolete command, + but it exists only for compatibility with older version. */ + SCI_CMD_OUTPUT_BAUD_CLK, /* output baud clock on the SCK pin */ + SCI_CMD_START_BIT_EDGE, /* detect start bit as falling edge of RXDn pin + (default detect as low level on RXDn pin) */ + SCI_CMD_GENERATE_BREAK, /* generate break condition */ + SCI_CMD_TX_Q_FLUSH, /* flush transmit queue */ + SCI_CMD_RX_Q_FLUSH, /* flush receive queue */ + SCI_CMD_TX_Q_BYTES_FREE, /* get count of unused transmit queue bytes */ + SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ, /* get num bytes ready for reading */ + SCI_CMD_COMPARE_RECEIVED_DATA, /* Compare received data with comparison data */ + + /* Async/Sync commands */ + SCI_CMD_EN_CTS_IN, /* enable CTS input (default RTS output) */ + + /* SSPI/Sync commands */ + SCI_CMD_CHECK_XFER_DONE, /* see if send, rcv, or both are done; SCI_SUCCESS if yes */ + SCI_CMD_ABORT_XFER, + SCI_CMD_XFER_LSB_FIRST, /* start from LSB bit when sending */ + SCI_CMD_XFER_MSB_FIRST, /* start from MSB bit when sending */ + SCI_CMD_INVERT_DATA, /* logic level of send/receive data is invert */ + + /* SSPI commands */ + SCI_CMD_CHANGE_SPI_MODE /* change clock polarity and phase in SSPI mode */ +} sci_cmd_t; + +/* SCI_CMD_CHANGE_BAUD/CHANGE_BITRATE take a ptr to this structure for *p_args */ +typedef struct st_sci_baud +{ + uint32_t pclk; // peripheral clock speed; e.g. 24000000 is 24MHz + uint32_t rate; // e.g. 9600, 19200, 115200 +} sci_baud_t; + +/* SCI_CMD_TX_Q_BYTES_FREE and SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ take a pointer + to a uint16_t for p_args */ + +/* SCI_CMD_SET_RXI_PRIORITY and SCI_CMD_SET_TXI_PRIORITY take a pointer to a + uint8_t for p_args */ + +/* SCI_CMD_CHANGE_SPI_MODE takes a pointer to an sci_spi_mode_t for p_args */ + +/***************************************************************************** +Public Functions +******************************************************************************/ +sci_err_t R_SCI_Open(uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl); + +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, // SSPI/SYNC only + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length); + +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); + +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); + +sci_err_t R_SCI_Close(sci_hdl_t const hdl); + +uint32_t R_SCI_GetVersion(void); + + +#endif /* SCI_IF_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/readme.txt new file mode 100644 index 000000000..8ff173dcb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/readme.txt @@ -0,0 +1,78 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS DRIVER FOR MORE INFORMATION + +r_sci_rx +======== + +Overview +-------------------------------------------------------------------------------- +The r_sci_rx module is a multi-channel, multi-mode, interrupt-driven driver which +supports Asynchronous, Master Synchronous, and Single Master Simple SPI (SSPI) +operation for the SCI peripherals. The API includes standard functions +to initialize a channel and to send and receive data, as well as a special control +function for taking actions such as issuing a break signal or enabling noise +cancellation. The driver supports all channels available on the mcu. The driver +can be reduced in size by removing code used for parameter checking, unused +channels, or unused modes. These configuration options can be found in +"r_config\r_sci_rx_config.h". An original copy of the configuration file +is stored in "r_sci_rx\ref\r_sci_rx_config_reference.h". + + +Features +-------- +* (RX110/111/113, RX65N/651) Simultaneous operation of up to 13 channels. +* (RX231/230) Simultaneous operation of up to 7 channels. +* (RX23T) Simultaneous operation of up to 2 channels. +* (RX23W) Simultaneous operation of up to 4 channels. +* (RX64M, RX71M) Simultaneous operation of up to 9 channels. +* (RX130) Simultaneous operation of up to 4 channels. +* (RX13T) Simultaneous operation of up to 3 channels. +* (RX24T) Simultaneous operation of up to 3 channels. +* (RX24U) Simultaneous operation of up to 6 channels. +* (RX66T) Simultaneous operation of up to 7 channels +* (RX72T) Simultaneous operation of up to 7 channels +* (RX72M) Simultaneous operation of up to 13 channels +* (RX72N) Simultaneous operation of up to 13 channels +* (RX66N) Simultaneous operation of up to 13 channels +* (RX23E-A) Simultaneous operation of up to 4 channels +* Simultaneous operation of Async, Sync, or SSPI modes on different channels. +* Queueing of incoming and outgoing data for Asynchronous channels. +* Interrupt driven. + + +File Structure +-------------- +r_sci_rx +| readme.txt +| r_sci_rx_if.h +| ++---doc +| +---ja +| | r01an1815jj{VERSION_NUMBER}-rx-serial.pdf +| +---en +| r01an1815ej{VERSION_NUMBER}-rx-serial.pdf +| ++---ref +| r_sci_rx_config_reference.h +| ++---src + | r_sci_rx.c + | r_sci_rx_platform.h + | r_sci_rx_private.h + | + +---targets + | + +---rx110 + | r_sci_rx110.c + | r_sci_rx110_data.c + | r_sci_rx110_private.h + +---rx111 + | r_sci_rx111.c + | r_sci_rx111_data.c + | r_sci_rx111_private.h + : + +r_config + r_sci_rx_config.h + +r_sci_rx.ftl + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h new file mode 100644 index 000000000..ea287d649 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h @@ -0,0 +1,198 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (1) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * RX MCU supported channels + * + * CH# 110 111 113 130 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N RX23E-A + * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------- + * CH0 X Xa X X X X Xn X X X + * CH1 X X* X* Xu X X Xu Xu Xu X X Xs X X X X X X X Xu + * CH2 X X X Xu X X X + * CH3 X X Xs X X X + * CH4 X X Xn X X X + * CH5 X X X X X Xu X X X X X X X X X X X X X X + * CH6 X X X X X X X X Xn X X Xu X X X + * CH7 Xu Xu Xn X X X + * CH8 X Xa X X X X X X Xu X X X + * CH9 X Xa X X X Xs X X X X X + * CH10 X X X X + * CH11 X Xs X X X X X + * CH12 X X X X X X X X Xs X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (0) +#define SCI_CFG_CH1_INCLUDED (1) +#define SCI_CFG_CH2_INCLUDED (0) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (0) +#define SCI_CFG_CH6_INCLUDED (0) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (0) +#define SCI_CFG_CH9_INCLUDED (0) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (0) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY) 1 lowest, 15 highest */ + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj and SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +#endif /* SCI_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx.c new file mode 100644 index 000000000..d103e1438 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx.c @@ -0,0 +1,2349 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016-2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx.c +* Description : Functions for using SCI on RX devices. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 FIT_NO_PTR check added to NULL check. +* Fixed a bug that may receive data more than the specified number of bytes +* on Clock Synchronous Mode. +* Fixed that R_SCI_Control function returns SCI_ERR_INVALID_ARG +* when using SCI_CMD_EN_CTS_IN on Simple SPI mode. +* Fix to clear error flag even if callback function is not set. +* Deleted unnecessary bit mask of SSR register from sci_error function. +* 07.03.2017 2.00 Fixed a bug that error condition not clear when FIFO enabled. +* Fixed a bug that where commands used only when FIFO mode is enable did not NULL check. +* Fixed a bug that sending data is overwrote by new R_SCI_Send() when FIFO(async) enabled. +* Fixed a bug that sending data is break up by new R_SCI_Send() when FIFO(sync) enabled. +* Fixed a bug that the new FIFO threshold was retained only on first receive. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 28.09.2018 2.10 Added support RX66T +* Add WAIT_LOOP comments. +* Fixed a bug that leaking memory in R_SCI_Open() when FIFO(async) enabled. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin. +* Fix GSCE Code Checker errors. +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support for RX72M +* 25.11.2019 3.30 Added support RX13T. +* Modified comment of API function to Doxygen style. +* Added support for atomic control. +* Fixed to comply with GSCE Coding Standards Rev.6.00. +* Fixed a bug that error when a reception interrupt occurs before incrementing "u_tx_data.buf" +* in "sci_send_sync_data" and "sci_receive" functions +* 30.12.2019 3.40 Added support RX66N, RX72N. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +/* Defines for SCI support */ +#include "r_sci_rx_private.h" + +/* Include specifics for chosen MCU. */ +#include "r_sci_rx_platform.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_init_queues(uint8_t const chan); + +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte); + +static void sci_transfer(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_transfer(sci_hdl_t const hdl); +#endif + +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static sci_err_t sci_init_sync(sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data); + +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +static void power_on(sci_hdl_t const hdl); +static void power_off(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static sci_err_t sci_init_fifo(sci_hdl_t const hdl); +#endif + +static void sci_receive(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static void sci_fifo_receive_sync(sci_hdl_t const hdl); +#endif + +static void sci_fifo_receive(sci_hdl_t const hdl); + +#endif + +#if SCI_CFG_DATA_MATCH_INCLUDED +static void sci_receive_data_match(sci_hdl_t const hdl); +#endif + +static void sci_error(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_error(sci_hdl_t const hdl); +#endif + +/* queue buffers */ +#if (SCI_CFG_ASYNC_INCLUDED) + +#if SCI_CFG_CH0_INCLUDED +static uint8_t ch0_tx_buf[SCI_CFG_CH0_TX_BUFSIZ]; +static uint8_t ch0_rx_buf[SCI_CFG_CH0_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH1_INCLUDED +static uint8_t ch1_tx_buf[SCI_CFG_CH1_TX_BUFSIZ]; +static uint8_t ch1_rx_buf[SCI_CFG_CH1_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH2_INCLUDED +static uint8_t ch2_tx_buf[SCI_CFG_CH2_TX_BUFSIZ]; +static uint8_t ch2_rx_buf[SCI_CFG_CH2_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH3_INCLUDED +static uint8_t ch3_tx_buf[SCI_CFG_CH3_TX_BUFSIZ]; +static uint8_t ch3_rx_buf[SCI_CFG_CH3_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH4_INCLUDED +static uint8_t ch4_tx_buf[SCI_CFG_CH4_TX_BUFSIZ]; +static uint8_t ch4_rx_buf[SCI_CFG_CH4_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH5_INCLUDED +static uint8_t ch5_tx_buf[SCI_CFG_CH5_TX_BUFSIZ]; +static uint8_t ch5_rx_buf[SCI_CFG_CH5_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH6_INCLUDED +static uint8_t ch6_tx_buf[SCI_CFG_CH6_TX_BUFSIZ]; +static uint8_t ch6_rx_buf[SCI_CFG_CH6_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH7_INCLUDED +static uint8_t ch7_tx_buf[SCI_CFG_CH7_TX_BUFSIZ]; +static uint8_t ch7_rx_buf[SCI_CFG_CH7_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH8_INCLUDED +static uint8_t ch8_tx_buf[SCI_CFG_CH8_TX_BUFSIZ]; +static uint8_t ch8_rx_buf[SCI_CFG_CH8_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH9_INCLUDED +static uint8_t ch9_tx_buf[SCI_CFG_CH9_TX_BUFSIZ]; +static uint8_t ch9_rx_buf[SCI_CFG_CH9_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH10_INCLUDED +static uint8_t ch10_tx_buf[SCI_CFG_CH10_TX_BUFSIZ]; +static uint8_t ch10_rx_buf[SCI_CFG_CH10_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH11_INCLUDED +static uint8_t ch11_tx_buf[SCI_CFG_CH11_TX_BUFSIZ]; +static uint8_t ch11_rx_buf[SCI_CFG_CH11_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH12_INCLUDED +static uint8_t ch12_tx_buf[SCI_CFG_CH12_TX_BUFSIZ]; +static uint8_t ch12_rx_buf[SCI_CFG_CH12_RX_BUFSIZ]; +#endif + +#endif /* #if (SCI_CFG_ASYNC_INCLUDED) */ + +extern const sci_hdl_t g_handles[SCI_NUM_CH]; + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Open +********************************************************************************************************************//** +* @brief This function applies power to the SCI channel, initializes the associated registers, enables interrupts, and +* provides the channel handle for use with other API functions. This function must be called before calling any +* other API functions +* @param[in] chan Channel to initialize. +* +* @param[in] mode Operational mode (see enumeration below) +* @code +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_MAX // End of modes currently supported +} sci_mode_t; +* @endcode +* @param[in] p_cfg Pointer to configuration union, structure elements (see below) are specific to mode +* @code +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; +} sci_cfg_t; +* @endcode +* +* @param[in] p_callback Pointer to function called from interrupt when an RXI or receiver error is detected or +* for transmit end (TEI) condition. See Section 2.11 Callback Function in application note for details. +* +* @param[in] p_hdl Pointer to a handle for channel (value set here) +* Confirm the return value from R_SCI_Open is “SCI_SUCCESS” and then set the first parameter for the +* other APIs except R_SCI_GetVersion(). See Section 2.9 Parameters in the application note for details. +* +* +* @retval SCI_SUCCESS Successful; channel initialized +* +* @retval SCI_ERR_BAD_CHAN Channel number is invalid for part +* +* @retval SCI_ERR_OMITTED_CHAN Corresponding SCI_CHx_INCLUDED is invalid (0) +* +* @retval SCI_ERR_CH_NOT_CLOSED Channel currently in operation; Perform R_SCI_Close() first +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_NULL_PTR p_cfg pointer is NULL +* +* @retval SCI_ERR_INVALID_ARG An element of the p_cfg structure contains an invalid value. +* +* @retval SCI_ERR_QUEUE_UNAVAILABLE Cannot open transmit or receive queue or both (Asynchronous mode). +* @details Initializes an SCI channel for a particular mode and provides a Handle in *p_hdl for use with other API +* functions. RXI and ERI interrupts are enabled in all modes. TXI is enabled in Asynchronous mode +* @note The driver calculates the optimum values for BRR, SEMR.ABCS, and SMR.CKS using BSP_PCLKA_HZ and +* BSP_PCLKB_HZ as defined in mcu_info.h of the board support package. This however does not guarantee +* a low bit error rate for all peripheral clock/baud rate combinations. +* If an external clock is used in Asynchronous mode, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Open() in the application note for details. +*/ +sci_err_t R_SCI_Open(uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl) +{ + sci_err_t err = SCI_SUCCESS; + uint8_t priority = 1; + + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + err = sci_mcu_param_check(chan); + if (SCI_SUCCESS != err) + { + return err; + } + + /* Check argument g_handles */ + if ((NULL == g_handles[chan]) || (FIT_NO_PTR == g_handles[chan])) + { + return SCI_ERR_OMITTED_CHAN; + } + if (SCI_MODE_OFF != g_handles[chan]->mode) + { + return SCI_ERR_CH_NOT_CLOSED; + } + if ((SCI_MODE_OFF == mode) || (SCI_MODE_MAX <= mode)) + { + return SCI_ERR_BAD_MODE; + } + + /* Check argument p_cfg, p_hdl */ + if (((NULL == p_cfg) || (NULL == p_hdl)) || ((FIT_NO_PTR == p_cfg) || (FIT_NO_PTR == p_hdl))) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* APPLY POWER TO CHANNEL */ + power_on(g_handles[chan]); + + /* INITIALIZE REGISTER */ + sci_init_register(g_handles[chan]); + + /* INITIALIZE MODE SPECIFIC FEATURES */ + g_handles[chan]->mode = mode; + if (SCI_MODE_ASYNC == mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_uart_t type is valid */ + err = sci_init_async(g_handles[chan], (sci_uart_t *)p_cfg, &priority); +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_sync_sspi_t type is valid */ + err = sci_init_sync(g_handles[chan], (sci_sync_sspi_t *)p_cfg, &priority); +#endif + } + + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + g_handles[chan]->callback = p_callback; + + /* INITIALIZE TX AND RX QUEUES */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == mode) + { + err = sci_init_queues(chan); + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + +#if SCI_CFG_FIFO_INCLUDED + if (true == g_handles[chan]->fifo_ctrl) + { + /* INITIALIZE TX AND RX FIFO */ + err = sci_init_fifo(g_handles[chan]); + if (SCI_SUCCESS != err) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* DE-INITIALIZE TX AND RX QUEUES */ + if (SCI_MODE_ASYNC == mode) + { + R_BYTEQ_Close(g_handles[chan]->u_tx_data.que); + R_BYTEQ_Close(g_handles[chan]->u_rx_data.que); + } +#endif + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + + /* ENABLE INTERRUPTS */ + sci_initialize_ints(g_handles[chan], priority); + + /* FINISH */ + *p_hdl = g_handles[chan]; + + return SCI_SUCCESS; +} /* End of function R_SCI_Open() */ + +/***************************************************************************** +* Function Name: power_on +* Description : This function provides power to the channel referenced by +* the handle by taking it out of the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_on(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) &= (~hdl->rom->stop_mask); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_on() */ + +/***************************************************************************** +* Function Name: power_off +* Description : This function removes power to the channel referenced by +* handle by putting it into the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_off(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) |= (hdl->rom->stop_mask); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_off() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_queues +* Description : This function attaches transmit and receive queues to the +* channel. +* +* Arguments : chan - +* channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_QUEUE_UNAVAILABLE - +* no queue control blocks available +******************************************************************************/ +static sci_err_t sci_init_queues(uint8_t const chan) +{ + byteq_err_t q_err1 = BYTEQ_ERR_INVALID_ARG; + byteq_err_t q_err2 = BYTEQ_ERR_INVALID_ARG; + sci_err_t err = SCI_SUCCESS; + + /* channel number verified as legal prior to calling this function */ + switch (chan) + { +#if SCI_CFG_CH0_INCLUDED + case (SCI_CH0): + { + q_err1 = R_BYTEQ_Open(ch0_tx_buf, SCI_CFG_CH0_TX_BUFSIZ, &g_handles[SCI_CH0]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch0_rx_buf, SCI_CFG_CH0_RX_BUFSIZ, &g_handles[SCI_CH0]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH1_INCLUDED + case (SCI_CH1): + { + q_err1 = R_BYTEQ_Open(ch1_tx_buf, SCI_CFG_CH1_TX_BUFSIZ, &g_handles[SCI_CH1]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch1_rx_buf, SCI_CFG_CH1_RX_BUFSIZ, &g_handles[SCI_CH1]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH2_INCLUDED + case (SCI_CH2): + { + q_err1 = R_BYTEQ_Open(ch2_tx_buf, SCI_CFG_CH2_TX_BUFSIZ, &g_handles[SCI_CH2]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch2_rx_buf, SCI_CFG_CH2_RX_BUFSIZ, &g_handles[SCI_CH2]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH3_INCLUDED + case (SCI_CH3): + { + q_err1 = R_BYTEQ_Open(ch3_tx_buf, SCI_CFG_CH3_TX_BUFSIZ, &g_handles[SCI_CH3]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch3_rx_buf, SCI_CFG_CH3_RX_BUFSIZ, &g_handles[SCI_CH3]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH4_INCLUDED + case (SCI_CH4): + { + q_err1 = R_BYTEQ_Open(ch4_tx_buf, SCI_CFG_CH4_TX_BUFSIZ, &g_handles[SCI_CH4]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch4_rx_buf, SCI_CFG_CH4_RX_BUFSIZ, &g_handles[SCI_CH4]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH5_INCLUDED + case (SCI_CH5): + { + q_err1 = R_BYTEQ_Open(ch5_tx_buf, SCI_CFG_CH5_TX_BUFSIZ, &g_handles[SCI_CH5]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch5_rx_buf, SCI_CFG_CH5_RX_BUFSIZ, &g_handles[SCI_CH5]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH6_INCLUDED + case (SCI_CH6): + { + q_err1 = R_BYTEQ_Open(ch6_tx_buf, SCI_CFG_CH6_TX_BUFSIZ, &g_handles[SCI_CH6]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch6_rx_buf, SCI_CFG_CH6_RX_BUFSIZ, &g_handles[SCI_CH6]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH7_INCLUDED + case (SCI_CH7): + { + q_err1 = R_BYTEQ_Open(ch7_tx_buf, SCI_CFG_CH7_TX_BUFSIZ, &g_handles[SCI_CH7]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch7_rx_buf, SCI_CFG_CH7_RX_BUFSIZ, &g_handles[SCI_CH7]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH8_INCLUDED + case (SCI_CH8): + { + q_err1 = R_BYTEQ_Open(ch8_tx_buf, SCI_CFG_CH8_TX_BUFSIZ, &g_handles[SCI_CH8]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch8_rx_buf, SCI_CFG_CH8_RX_BUFSIZ, &g_handles[SCI_CH8]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH9_INCLUDED + case (SCI_CH9): + { + q_err1 = R_BYTEQ_Open(ch9_tx_buf, SCI_CFG_CH9_TX_BUFSIZ, &g_handles[SCI_CH9]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch9_rx_buf, SCI_CFG_CH9_RX_BUFSIZ, &g_handles[SCI_CH9]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH10_INCLUDED + case (SCI_CH10): + { + q_err1 = R_BYTEQ_Open(ch10_tx_buf, SCI_CFG_CH10_TX_BUFSIZ, &g_handles[SCI_CH10]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch10_rx_buf, SCI_CFG_CH10_RX_BUFSIZ, &g_handles[SCI_CH10]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH11_INCLUDED + case (SCI_CH11): + { + q_err1 = R_BYTEQ_Open(ch11_tx_buf, SCI_CFG_CH11_TX_BUFSIZ, &g_handles[SCI_CH11]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch11_rx_buf, SCI_CFG_CH11_RX_BUFSIZ, &g_handles[SCI_CH11]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH12_INCLUDED + case (SCI_CH12): + { + q_err1 = R_BYTEQ_Open(ch12_tx_buf, SCI_CFG_CH12_TX_BUFSIZ, &g_handles[SCI_CH12]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch12_rx_buf, SCI_CFG_CH12_RX_BUFSIZ, &g_handles[SCI_CH12]->u_rx_data.que); + break; + } +#endif + default: + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + break; + } + } + + if ((BYTEQ_SUCCESS != q_err1) || (BYTEQ_SUCCESS != q_err2)) + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + } + return err; +} /* End of function sci_init_queues() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_init_fifo +* Description : This function the setting of the FIFO mode, reset of the +* TX/RX FIFO, and the threshold setting of the TX/RX FIFO. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* fifo initialized successfully +* SCI_ERR_INVALID_ARG - +* element of hdl contains illegal value +******************************************************************************/ +static sci_err_t sci_init_fifo(sci_hdl_t const hdl) +{ + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (hdl->tx_dflt_thresh > 15) + { + return SCI_ERR_INVALID_ARG; + } + if ((hdl->rx_dflt_thresh < 1) || (hdl->rx_dflt_thresh > 15)) + { + return SCI_ERR_INVALID_ARG; + } +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if (hdl->tx_dflt_thresh != hdl->rx_dflt_thresh) + { + return SCI_ERR_INVALID_ARG; + } +#endif +#endif + + /* FIFO Mode Select (1:FIFO mode) */ + hdl->rom->regs->FCR.BIT.FM = 0x01; + + /* reset TX/RX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* set TX/RX FIFO threshold initial value */ + hdl->rom->regs->FCR.BIT.TTRG = hdl->tx_dflt_thresh; + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_dflt_thresh; + + return SCI_SUCCESS; +} /* End of function sci_init_fifo() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_async +* Description : This function initializes the control block and UART +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to Uart configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (((SCI_DATA_8BIT != p_cfg->data_size) && (SCI_DATA_7BIT != p_cfg->data_size)) + || ((SCI_STOPBITS_1 != p_cfg->stop_bits) && (SCI_STOPBITS_2 != p_cfg->stop_bits)) + || ((p_cfg->int_priority < (BSP_MCU_IPL_MIN+1)) || (p_cfg->int_priority > BSP_MCU_IPL_MAX))) + { + return SCI_ERR_INVALID_ARG; + } + + if (SCI_PARITY_ON == p_cfg->parity_en) + { + if ((SCI_EVEN_PARITY != p_cfg->parity_type) && (SCI_ODD_PARITY != p_cfg->parity_type)) + { + return SCI_ERR_INVALID_ARG; + } + } + else if (SCI_PARITY_OFF != p_cfg->parity_en) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + if (SCI_CLK_INT == p_cfg->clk_src) + { + if (0 == p_cfg->baud_rate) + { + return SCI_ERR_INVALID_ARG; + } + } + else if ((SCI_CLK_EXT8X != p_cfg->clk_src) && (SCI_CLK_EXT16X != p_cfg->clk_src)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + + + /* Configure SMR for asynchronous mode, single processor, and user settings */ + if (SCI_PARITY_OFF == p_cfg->parity_en) + { + p_cfg->parity_type = 0; // ensure random value is not ORed into SMR + } + + /* Configure SMR */ + hdl->rom->regs->SMR.BYTE = (uint8_t)((p_cfg->data_size | p_cfg->stop_bits) | (p_cfg->parity_en | p_cfg->parity_type)); + + /* SETUP CLOCK FOR BAUD RATE */ + + if (SCI_CLK_INT == p_cfg->clk_src) + { + /* Use internal clock for baud rate */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->baud_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = p_cfg->baud_rate; // save baud rate for break generation + } + } + else + { + /* Use external clock for baud rate */ + hdl->rom->regs->SCR.BIT.CKE = 0x02; + hdl->rom->regs->SEMR.BIT.ABCS = (SCI_CLK_EXT8X == p_cfg->clk_src) ? 1 : 0; + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_async() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_sync +* Description : This function initializes the control block and SYNC/SSPI +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to SSPI configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_sync(sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err = SCI_SUCCESS; + int32_t bit_err; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((SCI_MODE_SSPI == hdl->mode) + && (SCI_SPI_MODE_0 != p_cfg->spi_mode) && (SCI_SPI_MODE_1 != p_cfg->spi_mode) + && (SCI_SPI_MODE_2 != p_cfg->spi_mode) && (SCI_SPI_MODE_3 != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else if ((SCI_MODE_SYNC == hdl->mode) && (SCI_SPI_MODE_OFF != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + + if (0 == p_cfg->bit_rate) + { + return SCI_ERR_INVALID_ARG; + } + + if ((0 == p_cfg->int_priority) || (p_cfg->int_priority > BSP_MCU_IPL_MAX)) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + hdl->tx_dummy = false; + + /* Configure SMR for SSPI/SYNC mode */ + hdl->rom->regs->SMR.BYTE = 0x80; + hdl->rom->regs->SCMR.BIT.SMIF = 0; /* default */ + hdl->rom->regs->SIMR1.BIT.IICM = 0; /* default */ + + /* Configure SPI register for clock polarity/phase and single master */ + if (SCI_MODE_SSPI == hdl->mode) + { + hdl->rom->regs->SPMR.BYTE = p_cfg->spi_mode; + } + else /* synchronous operation */ + { + hdl->rom->regs->SPMR.BYTE = 0; + } + + /* Configure data inversion */ + hdl->rom->regs->SCMR.BIT.SINV = (uint8_t)((true == p_cfg->invert_data) ? 1 : 0); + + /* Configure bit order */ + hdl->rom->regs->SCMR.BIT.SDIR = (uint8_t)((true == p_cfg->msb_first) ? 1 : 0); + + + /* SETUP CLOCK FOR BIT RATE */ + + /* Use internal clock for bit rate (master) */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->bit_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; /* impossible bit rate; 100% error */ + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_sync() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Send +********************************************************************************************************************//** +* @brief Initiates transmit if transmitter is not in use. Queues data for later transmit when in Asynchronous mode. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_src Pointer to data to transmit +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Transmit initiated or loaded into queue (Asynchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_SPACE Insufficient space in queue to load all data (Asynchronous) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous) +* +* +* @details In asynchronous mode, this function places data into a transmit queue if the transmitter for the SCI channel +* referenced by the handle is not in use. In SSPI and Synchronous modes, no data is queued and transmission begins immediately +* if the transceiver is not already in use. All transmissions are handled at the interrupt level.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave Select line +* for the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* @note None +*/ +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err=SCI_SUCCESS; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_src */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl)) || ((NULL == p_src) || (FIT_NO_PTR == p_src))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_send_async_data(hdl, p_src, length); +#endif + } + else + { + /* SSPI or SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_send_sync_data(hdl, p_src, NULL, length, false); +#endif + } + + return err; +} /* End of function R_SCI_Send() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_async_data +* Description : This function determines if the tx byte queue of the channel +* referenced by the handle is not full, and call the byte +* transmission function. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* length - +* number of bytes to send and possibly receive +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_ERR_QUEUE_FULL; + + if (true != hdl->tx_idle ) + { + return SCI_ERR_XCVR_BUSY; + } + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* TX FIFO use check */ + if (0x00 < hdl->rom->regs->FDR.BIT.T) + { + return SCI_ERR_XCVR_BUSY; + } + + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + } +#endif + + /* Determine amount of space left in tx queue */ + R_BYTEQ_Unused(hdl->u_tx_data.que, &cnt); + + if (cnt < length) + { + /* If can't fit, return */ + return SCI_ERR_INSUFFICIENT_SPACE; + } + + /* Else load bytes into tx queue for transmission */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { + byteq_err = sci_put_byte(hdl, *p_src++); + if (BYTEQ_SUCCESS != byteq_err) + { + /* If the return value is not BYTEQ_SUCCESS. */ + err = SCI_ERR_INSUFFICIENT_SPACE; + break; + } + } + + if (SCI_SUCCESS == err) + { + hdl->tx_idle = false; + ENABLE_TXI_INT; + } + + return err; +} /* End of function sci_send_async_data() */ + +/***************************************************************************** +* Function Name: sci_put_byte +* Description : Transmits byte if channel is not busy. Otherwise, byte is +* stored in tx queue until can transmit. If buffer is full +* and cannot store it, an error code is returned. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* byte - +* byte to transmit +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte) +{ + byteq_err_t err = BYTEQ_ERR_QUEUE_FULL; + + /* else load next byte into tx queue (space checked in calling func) */ + err = R_BYTEQ_Put(hdl->u_tx_data.que, byte); + + return err; +} /* End of function sci_put_byte() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and begins the data transfer process +* (both sending and receiving data). +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* p_dst - +* ptr to buffer to store receive data (optional) +* length - +* number of bytes to send and possibly receive +* save_rx_data - +* true if data clocked in should be saved to p_dst. +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + if (true == hdl->tx_idle) + { + if (true == save_rx_data) + { + hdl->u_rx_data.buf = p_dst; + } + hdl->save_rx_data = save_rx_data; + + hdl->u_tx_data.buf = p_src; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_idle = false; + hdl->tx_dummy = false; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + + thresh_cnt = hdl->rom->regs->FCR.BIT.RTRG; + + hdl->tx_cnt -= thresh_cnt; + + /* Repeated FIFO RX threshold count */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + if(0 != cnt) + { + hdl->u_tx_data.buf++; + } + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + } + else +#endif + { + hdl->tx_cnt--; + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_send_sync_data() */ +#endif /* SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/*********************************************************************************************************************** +* Function Name: R_SCI_SendReceive +********************************************************************************************************************//** +* @brief For Synchronous and SSPI modes only. Transmits and receives data simultaneously if the transceiver is not +* in use. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* @param[in] p_src Pointer to data to transmit +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Data transfer initiated +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Channel mode not SSPI or Synchronous +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy +* @details If the transceiver is not in use, this function clocks out data from the p_src buffer while simultaneously +* clocking in data and placing it in the p_dst buffer. +* Note that the toggling of Slave Select lines for SSPI is not handled by this driver. The Slave Select line for +* the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +*/ +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check arguments */ + if ((((NULL == hdl) || (FIT_NO_PTR == hdl)) /* Check if hdl is available or not */ + || ((NULL == p_src) || (FIT_NO_PTR == p_src))) /* Check if p_src is available or not */ + || ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) /* Check if p_dst is available or not */ + { + return SCI_ERR_NULL_PTR; + } + + if ((SCI_MODE_SSPI != hdl->mode) && (SCI_MODE_SYNC != hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + err = sci_send_sync_data(hdl, p_src, p_dst, length, true); + + return err; +} /* End of function R_SCI_SendReceive() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_transfer +* Description : Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_transfer(sci_hdl_t const hdl) +{ + uint16_t num; + uint8_t byte; + + /* Get bytes from tx queue */ + (void)R_BYTEQ_Get(hdl->u_tx_data.que, (uint8_t *)&byte); + + /* TDR/FTDR register write access */ + SCI_TDR(byte); + + /* Get data byte number from que and if the number of data bytes is 0, to disable the transfer */ + R_BYTEQ_Used(hdl->u_tx_data.que, &num); + if (0 >= num) + { + /* Disable transmit interrupt */ + DISABLE_TXI_INT; +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + hdl->tx_idle = true; // set flag if queue empty + } +} /* End of function sci_transfer() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_transfer +* Description : FIFO Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_transfer(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num; + + /* Repeated empty FIFO buffer count */ + fifo_num = SCI_FIFO_FRAME_SIZE - hdl->rom->regs->FDR.BIT.T; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* SCI Transfer */ + sci_transfer(hdl); + + /* If the queue is empty(true == hdl->tx_idle), exit from FIFO transfer loop */ + if (true == hdl->tx_idle) + { + break; + } + } + + /* When the settings of transmit data are completed, set the SSRFIFO.TDFE flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + /* Casting register 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } +} /* End of function sci_fifo_transfer() */ +#endif /*End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: txi_handler +* Description : TXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void txi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Transfer */ + sci_fifo_transfer(hdl); + } + else +#endif + { + /* SCI Transfer */ + sci_transfer(hdl); + } +} /* End of function txi_handler() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* Function Name: tei_handler +* Description : TEI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void tei_handler(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + + /* Disable transmit end interrupt */ + DISABLE_TEI_INT; + hdl->rom->regs->SCR.BIT.TEIE = 0; + + /* Activate callback function if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_TEI; + + /* Activate callback function */ + hdl->callback((void *)&args); + } +} /* End of function tei_handler() */ +#endif + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Receive +********************************************************************************************************************//** +* @brief In Asynchronous mode, fetches data from a queue which is filled by RXI interrupts. In other modes, initiates +* reception if transceiver is not in use. +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to read +* +* @retval SCI_SUCCESS Requested number of bytes were loaded into p_dst (Asynchronous) Clocking in of data initiated +* (SSPI/Synchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_DATA Insufficient data in receive queue to fetch all data (Asynchronous) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous) +* +* @details In Asynchronous mode, this function gets data received on an SCI channel referenced by the handle from its +* receive queue. This function will not block if the requested number of bytes is not available. In +* SSPI/Synchronous modes, the clocking in of data begins immediately if the transceiver is not already in use. +* The value assigned to SCI_CFG_DUMMY_TX_BYTE in r_sci_config.h is clocked out while the receive data is being clocked in.\n +* If any errors occurred during reception, the callback function specified in R_SCI_Open() is executed. Check +* an event passed with the argument of the callback function to see if the reception has been successfully +* completed. See Section 2.11 Callback Function in application note for details.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave +* Select line for the target device must be enabled prior to calling this function. +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +* In Asynchronous mode, when data match detected, received data stored in a queue and notify to user by callback function +* with event SCI_EVT_RX_CHAR_MATCH. +*/ +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +sci_err_t err = SCI_SUCCESS; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_dst */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl))|| ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_receive_async_data(hdl, p_dst, length); +#endif + } + + else + { + /* mode is SSPI/SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_receive_sync_data(hdl, p_dst, length); +#endif + } + + return err; +} /* End of function R_SCI_Receive() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_async_data +* Description : This function determines if the rx byte queue of the channel +* referenced by the handle, the requested number of bytes +* is available, and get the data from the rx byte queue. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_INSUFFICIENT_DATA - +* rx queue does not contain requested amount of data +******************************************************************************/ +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_SUCCESS; + + /* CHECK FOR SUFFICIENT DATA IN QUEUE, AND FETCH IF AVAILABLE */ + R_BYTEQ_Used(hdl->u_rx_data.que, &cnt); + + if (cnt < length) + { + return SCI_ERR_INSUFFICIENT_DATA; + } + + /* Get bytes from rx queue */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { + /* Disable RXI Interrupt */ + DISABLE_RXI_INT; + byteq_err = R_BYTEQ_Get(hdl->u_rx_data.que, p_dst++); + ENABLE_RXI_INT; + if (BYTEQ_SUCCESS != byteq_err) + { + err = SCI_ERR_INSUFFICIENT_DATA; + break; + } + } + + return err; +} /* End of function sci_receive_async_data() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and dummy data send. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + /* IF TRANCEIVER NOT IN USE, START DUMMY TRANSMIT TO CLOCK IN DATA */ + if (true == hdl->tx_idle) + { + hdl->u_rx_data.buf = p_dst; + hdl->save_rx_data = true; /* save the data clocked in */ + hdl->tx_idle = false; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_dummy = true; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + if (length > SCI_FIFO_FRAME_SIZE) + { + thresh_cnt = SCI_FIFO_FRAME_SIZE; + } + else + { + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + thresh_cnt = length; + } + + hdl->tx_cnt -= thresh_cnt; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transmit */ + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transfer */ + } + + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_receive_sync_data() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +* Function Name: sci_receive +* Description : Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + /* Read byte */ + SCI_RDR(byte); + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + hdl->rx_cnt--; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + *hdl->u_rx_data.buf++ = byte; + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (0 < hdl->tx_cnt) + { + /* send another byte */ + if (true == hdl->tx_dummy) + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + else + { + hdl->tx_cnt--; + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + else + { + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } + } +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + } +} /* End of function sci_receive() */ + +#if SCI_CFG_FIFO_INCLUDED +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_fifo_receive_sync +* Description : FIFO Receive for SCI mode is SYNC and SSPI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive_sync(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num_rx; + uint8_t fifo_num_tx; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; + + fifo_num_rx = hdl->rom->regs->FDR.BIT.R; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + SCI_RDR(byte_rx[cnt]); + } + + hdl->rx_cnt -= fifo_num_rx; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + /* SCI Receive */ + *hdl->u_rx_data.buf++ = byte_rx[cnt]; + } + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (hdl->rom->regs->FCR.BIT.RTRG > hdl->rx_cnt) + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_cnt; + } + + if (0 < hdl->tx_cnt) + { + if (hdl->tx_cnt > fifo_num_rx) + { + fifo_num_tx = fifo_num_rx; + hdl->tx_cnt -= fifo_num_rx; + } + else + { + fifo_num_tx = hdl->tx_cnt; + hdl->tx_cnt = 0; + } + + /* send another byte */ + if (true == hdl->tx_dummy) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + } + else + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + } + else + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_curr_thresh; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + } +} /* End of function sci_fifo_receive_sync() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_receive +* Description : FIFO Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive(sci_hdl_t const hdl) +{ +#if (SCI_CFG_ASYNC_INCLUDED) + uint16_t cnt; + uint16_t fifo_num; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting unsigned char type to uint16_t type is valid */ + fifo_num = (uint16_t)hdl->rom->regs->FDR.BIT.R; + + /* RX FIFO flush */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* Read byte */ + SCI_RDR(byte_rx[cnt]); + } + + /* Determine amount of space left in rx queue */ + (void)R_BYTEQ_Unused(hdl->u_rx_data.que, &cnt); + if (cnt >= fifo_num) + { + /* free space is enough */ + args.event = SCI_EVT_RX_CHAR; + } + else + { + /* insufficient free space, store as much as possible */ + fifo_num = cnt; + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* store bytes to rx queue for R_SCI_Receive */ + (void)R_BYTEQ_Put(hdl->u_rx_data.que, byte_rx[cnt]); + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + + /* Number of bytes were stored to queue */ + args.num = (uint8_t)fifo_num; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED*/ + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* SCI Receive */ + sci_fifo_receive_sync(hdl); +#endif + } + + /* When the readings of receive data are completed, set the SSRFIFO.RDF flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.RDF) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_RDF_MASK; + } + + if (SCI_MODE_ASYNC == hdl->mode) + { + if (1 == hdl->rom->regs->SSRFIFO.BIT.DR) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_DR_MASK; + } + } +} /* End of function sci_fifo_receive() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED +/***************************************************************************** +* Function Name: sci_receive_data_match +* Description : SCI receive data match +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive_data_match(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (0 == hdl->rom->regs->DCCR.BIT.DCME) /* DCME automatically set 0 when data matched */ + { + hdl->rom->regs->DCCR.BIT.DCMF = 0; /* Clear Data Match Flag */ + + if ((0 == hdl->rom->regs->DCCR.BIT.DFER ) && (0 == hdl->rom->regs->DCCR.BIT.DPER )) /* Check framing error and parity error */ + { + /* Casting unsigned char type to unin8_t type is valid */ + byte = (uint8_t)(hdl->rom->regs->CDR.BYTE.L); /* Read data from comparison data register */ + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR_MATCH; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + } +} /* End of function sci_receive_data_match() */ +#endif /* End of SCI_CFG_DATA_MATCH_INCLUDED */ + +/***************************************************************************** +* Function Name: rxi_handler +* Description : RXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void rxi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_DATA_MATCH_INCLUDED + if (1 == hdl->rom->regs->DCCR.BIT.DCMF) /* Check Data match flag */ + { + sci_receive_data_match(hdl); + } + else +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Receive */ + sci_fifo_receive(hdl); + } + else +#endif + { + /* SCI Receive */ + sci_receive(hdl); + } +} /* End of function rxi_handler() */ + + +/***************************************************************************** +* Function Name: sci_error +* Description : Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + uint8_t reg; + + reg = SCI_SSR; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Flush register */ + SCI_RDR(byte); + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + SCI_RDR(byte); + + reg = SCI_SSR; + reg &= (~SCI_RCVR_ERR_MASK); + reg |= SCI_SSR_CLR_MASK; + SCI_SSR = reg; + + if (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + +} /* End of function sci_error() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_error +* Description : FIFO Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t reg; + volatile uint8_t ssrfifo_data; + volatile uint16_t dummy; + + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = 0; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + + /* if error condition don't clear in callback when it clear at here */ + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + /* Flush register */ + /* WAIT_LOOP */ + while (0 != hdl->rom->regs->FDR.BIT.R) + { + dummy = hdl->rom->regs->FRDR.WORD; /* FRDR dummy read */ + } + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) /* Check PER, FER, ORER flags */ + { + ssrfifo_data = SCI_SSRFIFO; /* SSRFIFO dummy read */ + SCI_SSRFIFO = (uint8_t)~SCI_RCVR_ERR_MASK; /* PER, FER, ORER clear */ + if (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + } + } + + return; +} /* End of function sci_fifo_error() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: eri_handler +* Description : ERI interrupt handler for SCI UART mode +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void eri_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Error */ + sci_fifo_error(hdl); + } + else +#endif + { + /* SCI error */ + sci_error(hdl); + } +} /* End of function eri_handler() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Control +********************************************************************************************************************//** +* @brief This function configures and controls the operating mode for the SCI channel. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] cmd Command to run (see Section 3. R_SCI_Control() in application note for details) +* +* @param[in] p_args Pointer to arguments (see Section 3. R_SCI_Control() in application note for details) specific to +* command, casted to void * +* +* @retval SCI_SUCCESS Successful; channel initialized. +* +* @retval SCI_ERR_NULL_PTR hdl or p_args pointer is NULL (when required) +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INVALID_ARG +* The cmd value or an element of p_args contains an invalid value. +* @details This function is used for configuring special hardware features such as changing driver configuration and +* obtaining driver status. +* The CTS/ RTS pin functions as RTS by default hardware control. By issuing an SCI_CMD_EN_CTS_IN, the pin functions as CTS. +* @note When SCI_CMD_CHANGE_BAUD is used, the optimum values for BRR, SEMR.ABCS, and SMR.CKS is calculated based on +* the bit rate specified. This however does not guarantee a low bit error rate for all peripheral clock/baud rate +* combinations.\n +* If the command SCI_CMD_EN_CTS_IN is to be used, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Control() for details. +*/ +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err = SCI_SUCCESS; + sci_baud_t *baud; + int32_t bit_err; + + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } + + /* Check argument p_args*/ + if ((NULL == p_args) || (FIT_NO_PTR == p_args)) + { + if (SCI_CMD_CHANGE_BAUD == cmd) + { + return SCI_ERR_NULL_PTR; + } +#if SCI_CFG_FIFO_INCLUDED + if ((SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) || (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } +#if SCI_CFG_FIFO_INCLUDED + if (SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if (15 < (*(uint8_t *)p_args)) + { + return SCI_ERR_INVALID_ARG; + } + } + if (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (15 < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd)) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (BSP_MCU_IPL_MAX < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + /* COMMANDS COMMON TO ALL MODES */ + + switch (cmd) + { + case (SCI_CMD_CHANGE_BAUD): + { + /* Casting void* type is valid */ + baud = (sci_baud_t *)p_args; +#if (SCI_CFG_ASYNC_INCLUDED) + hdl->pclk_speed = baud->pclk; // save for break generation +#endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, baud->pclk, baud->rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = baud->rate; // save for break generation + } + break; + } + + case (SCI_CMD_EN_CTS_IN): + { + if (SCI_MODE_SSPI != hdl->mode) + { + /* PFS & port pins must be configured for CTS prior to calling this */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BIT.CTSE = 1; // enable CTS input + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + /* Can not use CTS in smart card interface mode, simple SPI mode, and simple I2C mode */ + err = SCI_ERR_INVALID_ARG; + } + break; + } + +#if SCI_CFG_FIFO_INCLUDED + case (SCI_CMD_CHANGE_TX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + /* save current TX FIFO threshold */ + hdl->tx_curr_thresh = *((uint8_t *)p_args); + + /* change TX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.TTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } + + case (SCI_CMD_CHANGE_RX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + /* save current RX FIFO threshold */ + hdl->rx_curr_thresh = *((uint8_t *)p_args); + + /* change RX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.RTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + case (SCI_CMD_SET_TXI_PRIORITY): + { + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_txi = *((uint8_t *)p_args); + break; + } + + case (SCI_CMD_SET_RXI_PRIORITY): + { + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_rxi = *((uint8_t *)p_args); + break; + } +#endif + + default: + { + /* ASYNC-SPECIFIC COMMANDS */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_async_cmds(hdl, cmd, p_args); +#endif + } + + /* SSPI/SYNC-SPECIFIC COMMANDS */ + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_sync_cmds(hdl, cmd, p_args); +#endif + } + break; + } + } + + return err; +} /* End of function R_SCI_Control() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Close +********************************************************************************************************************//** +* @brief This function removes power from the SCI channel and disables the associated interrupts. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @retval SCI_SUCCESS Successful; channel closed +* +* @retval SCI_ERR_NULL_PTR hdl is NULL +* +* @details Disables the SCI channel designated by the handle and enters module-stop state. +* @note This function will abort any transmission or reception that may be in progress. +*/ +sci_err_t R_SCI_Close(sci_hdl_t const hdl) +{ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* disable ICU interrupts */ + sci_disable_ints(hdl); + + /* free tx and rx queues */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + R_BYTEQ_Close(hdl->u_tx_data.que); + R_BYTEQ_Close(hdl->u_rx_data.que); + } +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset FIFO threshold */ + hdl->rx_curr_thresh = hdl->rx_dflt_thresh; + hdl->tx_curr_thresh = hdl->tx_dflt_thresh; + } +#endif + + /* mark the channel as not in use and power down */ + hdl->mode = SCI_MODE_OFF; + power_off(hdl); + + return SCI_SUCCESS; +} /* End of function R_SCI_Close() */ + + +/*********************************************************************************************************************** +* Function Name: R_SCI_GetVersion +********************************************************************************************************************//** +* @brief This function returns the driver version number at runtime. +* @return Version number. +* @details Returns the version of this module. The version number is encoded such that the top 2 bytes are the major +* version number and the bottom 2 bytes are the minor version number. +* @note None +*/ +uint32_t R_SCI_GetVersion(void) +{ + uint32_t const version = (SCI_VERSION_MAJOR << 16) | SCI_VERSION_MINOR; + + return version; +} /* End of function R_SCI_GetVersion() */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h new file mode 100644 index 000000000..892f8820c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_platform.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 Added RX24U support +* 28.09.2018 2.10 Added RX66T support +* 01.02.2019 2.20 Added RX72T, RX65N-64pin support +* 28.06.2019 3.10 Added RX23W support +* 15.08.2019 3.20 Added RX72M support +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +************************************************************************************************************************/ + +#ifndef SCI_RX_PLATFORM_H +#define SCI_RX_PLATFORM_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sci_rx_if.h" + +#if defined(BSP_MCU_RX110) +#include "./targets/rx110/r_sci_rx110_private.h" /* RX110 */ +#elif defined(BSP_MCU_RX111) +#include "./targets/rx111/r_sci_rx111_private.h" /* RX111 */ +#elif defined(BSP_MCU_RX113) +#include "./targets/rx113/r_sci_rx113_private.h" /* RX113 */ +#elif defined(BSP_MCU_RX130) +#include "./targets/rx130/r_sci_rx130_private.h" /* RX130 */ +#elif defined(BSP_MCU_RX13T) +#include "./targets/rx13t/r_sci_rx13t_private.h" /* RX13T */ +#elif defined(BSP_MCU_RX230) +#include "./targets/rx230/r_sci_rx230_private.h" /* RX230 */ +#elif defined(BSP_MCU_RX231) +#include "./targets/rx231/r_sci_rx231_private.h" /* RX231 */ +#elif defined(BSP_MCU_RX23E_A) +#include "./targets/rx23e-a/r_sci_rx23e-a_private.h" /* RX23E-A */ +#elif defined(BSP_MCU_RX23T) +#include "./targets/rx23t/r_sci_rx23t_private.h" /* RX23T */ +#elif defined(BSP_MCU_RX23W) +#include "./targets/rx23w/r_sci_rx23w_private.h" /* RX23W */ +#elif defined(BSP_MCU_RX24T) +#include "./targets/rx24t/r_sci_rx24t_private.h" /* RX24T */ +#elif defined(BSP_MCU_RX24U) +#include "./targets/rx24u/r_sci_rx24u_private.h" /* RX24U */ +#elif defined(BSP_MCU_RX64M) +#include "./targets/rx64m/r_sci_rx64m_private.h" /* RX64M */ +#elif defined(BSP_MCU_RX65N) +#include "./targets/rx65n/r_sci_rx65n_private.h" /* RX65N */ +#elif defined(BSP_MCU_RX66T) +#include "./targets/rx66t/r_sci_rx66t_private.h" /* RX66T */ +#elif defined(BSP_MCU_RX66N) +#include "./targets/rx66n/r_sci_rx66n_private.h" /* RX66N */ +#elif defined(BSP_MCU_RX71M) +#include "./targets/rx71m/r_sci_rx71m_private.h" /* RX71M */ +#elif defined(BSP_MCU_RX72T) +#include "./targets/rx72t/r_sci_rx72t_private.h" /* RX72T */ +#elif defined(BSP_MCU_RX72M) +#include "./targets/rx72m/r_sci_rx72m_private.h" /* RX72M */ +#elif defined(BSP_MCU_RX72N) +#include "./targets/rx72n/r_sci_rx72n_private.h" /* RX72N */ +#else +#error "ERROR - r_sci_rxXXX_private.h not included." +#endif + +#endif /* SCI_RX_PLATFORM_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h new file mode 100644 index 000000000..72ed5f11f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h @@ -0,0 +1,184 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_private.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 28.09.2018 2.10 Added SCI_CFG_DATA_MATCH_INCLUDED for configuration data match function. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support received data match function for RX65N (SCI10 and SCI11). +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0 to SCI11). +* Added support FIFO mode for RX72M (SCI7 to SCI11). +***********************************************************************************************************************/ + +#ifndef SCI_RX_H +#define SCI_RX_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../r_sci_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Bit position masks */ +#define BIT0_MASK (0x00000001U) +#define BIT1_MASK (0x00000002U) +#define BIT2_MASK (0x00000004U) +#define BIT3_MASK (0x00000008U) +#define BIT4_MASK (0x00000010U) +#define BIT5_MASK (0x00000020U) +#define BIT6_MASK (0x00000040U) +#define BIT7_MASK (0x00000080U) +#define BIT8_MASK (0x00000100U) +#define BIT9_MASK (0x00000200U) +#define BIT10_MASK (0x00000400U) +#define BIT11_MASK (0x00000800U) +#define BIT12_MASK (0x00001000U) +#define BIT13_MASK (0x00002000U) +#define BIT14_MASK (0x00004000U) +#define BIT15_MASK (0x00008000U) +#define BIT16_MASK (0x00010000U) +#define BIT17_MASK (0x00020000U) +#define BIT18_MASK (0x00040000U) +#define BIT19_MASK (0x00080000U) +#define BIT20_MASK (0x00100000U) +#define BIT21_MASK (0x00200000U) +#define BIT22_MASK (0x00400000U) +#define BIT23_MASK (0x00800000U) +#define BIT24_MASK (0x01000000U) +#define BIT25_MASK (0x02000000U) +#define BIT26_MASK (0x04000000U) +#define BIT27_MASK (0x08000000U) +#define BIT28_MASK (0x10000000U) +#define BIT29_MASK (0x20000000U) +#define BIT30_MASK (0x40000000U) +#define BIT31_MASK (0x80000000U) + +#ifndef NULL /* Resolves e2studio code analyzer false error message. */ + #define NULL (0) +#endif + +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || \ + (SCI_CFG_CH8_FIFO_INCLUDED) || \ + (SCI_CFG_CH9_FIFO_INCLUDED) || \ + (SCI_CFG_CH10_FIFO_INCLUDED) || \ + (SCI_CFG_CH11_FIFO_INCLUDED)) + #define SCI_CFG_FIFO_INCLUDED (1) +#endif + +#if ((SCI_CFG_CH0_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH1_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH2_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH3_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH4_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH5_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH6_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH7_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH8_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH9_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH10_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH11_DATA_MATCH_INCLUDED)) + #define SCI_CFG_DATA_MATCH_INCLUDED (1) +#endif + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_ORER (hdl->rom->regs->SSRFIFO.BIT.ORER) +#define SCI_SSRFIFO_PER (hdl->rom->regs->SSRFIFO.BIT.PER) +#define SCI_SSRFIFO_FER (hdl->rom->regs->SSRFIFO.BIT.FER) +#define SCI_SSRFIFO_RDF (hdl->rom->regs->SSRFIFO.BIT.RDF) +#define SCI_SSRFIFO (hdl->rom->regs->SSRFIFO.BYTE) +#endif +#define SCI_SSR_ORER (hdl->rom->regs->SSR.BIT.ORER) +#define SCI_SSR_PER (hdl->rom->regs->SSR.BIT.PER) +#define SCI_SSR_FER (hdl->rom->regs->SSR.BIT.FER) +#define SCI_SSR (hdl->rom->regs->SSR.BYTE) + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_FIFO_FRAME_SIZE (16) +#endif + +/* SCR register dummy read */ +#define SCI_SCR_DUMMY_READ \ + if (0x00 == hdl->rom->regs->SCR.BYTE) \ + { \ + R_BSP_NOP(); \ + } + +/* Interrupt Request register flag clear */ +#define SCI_IR_TXI_CLEAR (*hdl->rom->ir_txi = 0) + +/* TDR/FTDR register write access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_TDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + hdl->rom->regs->FTDR.BYTE.L = (byte); \ + } \ + else \ + { \ + hdl->rom->regs->TDR = (byte); \ + } +#else +#define SCI_TDR(byte) \ + hdl->rom->regs->TDR = (byte); +#endif + +/* RDR/FRDR register read access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_RDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + (byte) = hdl->rom->regs->FRDR.BYTE.L; \ + } \ + else \ + { \ + (byte) = hdl->rom->regs->RDR; \ + } +#else +#define SCI_RDR(byte) \ + (byte) = hdl->rom->regs->RDR; +#endif + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +extern void txi_handler(sci_hdl_t const hdl); +#endif + +#if SCI_CFG_TEI_INCLUDED +extern void tei_handler(sci_hdl_t const hdl); +#endif + +extern void rxi_handler(sci_hdl_t const hdl); + +extern void eri_handler(sci_hdl_t const hdl); + +#endif /* SCI_RX_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c new file mode 100644 index 000000000..10c9f9974 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c @@ -0,0 +1,1448 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx72n.c +* Description : Functions for using SCI on the RX72N device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx72n_private.h" + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/***************************************************************************** +* Function Name: sci_mcu_param_check +* Description : This function parameters check on MCU. +* (channel range, interrupt priority, etc...) +* Arguments : chan - +* channel to check +* Return Value : SCI_SUCCESS - +* parameter check all successfully +* SCI_ERR_BAD_CHAN - +* channel number invalid for part +* SCI_ERR_INVALID_ARG - +* interrupt priority out of range +******************************************************************************/ +sci_err_t sci_mcu_param_check(uint8_t const chan) +{ + /* channel range parameter check */ + if (SCI_NUM_CH <= chan) + { + return SCI_ERR_BAD_CHAN; + } + + /* interrupt priority configuration parameter check */ + if ((1 > SCI_CFG_ERI_TEI_PRIORITY) || (15 < SCI_CFG_ERI_TEI_PRIORITY)) + { + return SCI_ERR_INVALID_ARG; + } + + return SCI_SUCCESS; +} /* End of function sci_mcu_param_check() */ + +/***************************************************************************** +* Function Name: sci_init_register +* Description : This function initializes the register for SCI. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_init_register(sci_hdl_t const hdl) +{ + /* SCI transmit enable bit and receive enable bit check & disable */ + /* WAIT_LOOP */ + while ((0 != hdl->rom->regs->SCR.BIT.TE) || (0 != hdl->rom->regs->SCR.BIT.RE)) + { + if (0 != hdl->rom->regs->SCR.BIT.TE) + { + hdl->rom->regs->SCR.BIT.TE = 0; // transmit disable + } + + if (0 != hdl->rom->regs->SCR.BIT.RE) + { + hdl->rom->regs->SCR.BIT.RE = 0; // receive disable + } + } + + /* SMR register initialize */ + hdl->rom->regs->SMR.BYTE = 0x00; + + /* SCR register initialize */ + hdl->rom->regs->SCR.BYTE = 0x00; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SSRFIFO register initialize */ + if (1 == SCI_SSRFIFO_ORER) + { + SCI_SSRFIFO_ORER = 0; + } + + if (1 == SCI_SSRFIFO_PER) + { + SCI_SSRFIFO_PER = 0; + } + + if (1 == SCI_SSRFIFO_FER) + { + SCI_SSRFIFO_FER = 0; + } + + if (1 == SCI_SSRFIFO_RDF) + { + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + SCI_SSRFIFO_RDF = 0; + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { + /* SSR register initialize */ + if (1 == SCI_SSR_ORER) + { + SCI_SSR_ORER = 0; + } + + if (1 == SCI_SSR_PER) + { + SCI_SSR_PER = 0; + } + + if (1 == SCI_SSR_FER) + { + SCI_SSR_FER = 0; + } + } + + /* SCMR register initialize */ + hdl->rom->regs->SCMR.BIT.SMIF = 0; + hdl->rom->regs->SCMR.BIT.SINV = 0; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + + /* BRR register initialize */ + hdl->rom->regs->BRR = 0xFF; + + /* SEMR register initialize */ + hdl->rom->regs->SEMR.BIT.BRME = 0; + hdl->rom->regs->SEMR.BIT.ABCS = 0; + hdl->rom->regs->SEMR.BIT.NFEN = 0; + hdl->rom->regs->SEMR.BIT.BGDM = 0; + hdl->rom->regs->SEMR.BIT.RXDESEL = 0; + + /* SNFR register initialize */ + hdl->rom->regs->SNFR.BYTE = 0; + + /* SPMR register initialize */ + hdl->rom->regs->SPMR.BIT.CTSE = 0; + hdl->rom->regs->SPMR.BIT.CKPOL = 0; + hdl->rom->regs->SPMR.BIT.CKPH = 0; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* FCR register initialize */ + hdl->rom->regs->FCR.BIT.FM = 0; + hdl->rom->regs->FCR.BIT.TFRST = 0; + hdl->rom->regs->FCR.BIT.RFRST = 0; + hdl->rom->regs->FCR.BIT.TTRG = 0; + hdl->rom->regs->FCR.BIT.RTRG = 8; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED + /* DCCR register initialize */ + hdl->rom->regs->DCCR.BIT.DCME = 0; + hdl->rom->regs->DCCR.BIT.DCMF = 0; + hdl->rom->regs->DCCR.BIT.DFER = 0; + hdl->rom->regs->DCCR.BIT.DPER = 0; + hdl->rom->regs->DCCR.BIT.IDSEL = 0; + + /* CDR register initialize */ + hdl->rom->regs->CDR.BYTE.L = 0; + + /* Set initial value of receive in 8-bit data length */ + hdl->rom->regs->SMR.BIT.CHR = 0; + hdl->rom->regs->SCMR.BIT.CHR1 = 1; +#endif + + return; +} /* End of function sci_init_register() */ + +/***************************************************************************** +* Function Name: sci_init_bit_rate +* Description : This function determines the best possible settings for the +* baud rate registers for the specified peripheral clock speed +* and baud rate. Note that this does not guarantee a low bit +* error rate, just the best possible one. The bit rate error is +* returned in .1% increments. If the hardware cannot support +* the specified combination, a value of 1000 (100% error) is +* returned. +* +* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled +* prior to calling this function. +* +* The application must pause for 1 bit time after the BRR register +* is loaded before transmitting/receiving to allow time for the clock +* to settle. +* +* Arguments : hdl - +* Handle for channel (ptr to chan control block) +* NOTE: mode element must be already set +* pclk - +* Peripheral clock speed; e.g. 24000000 for 24MHz +* baud - +* Baud rate; 19200, 57600, 115200, etc. +* Return Value : bit error in .1% increments; e.g. 16 = 1.6% bit rate error +* a value of 1000 denotes 100% error; no registers set +******************************************************************************/ +int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud) +{ + uint32_t i; + uint32_t num_divisors = 0; + uint32_t ratio; + uint32_t tmp; + baud_divisor_t const *p_baud_info = NULL; + + uint32_t divisor; + uint32_t int_M; + float float_M; + float error; + float abs_error; + +#if SCI_CFG_FIFO_INCLUDED + uint8_t brr; +#endif + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((0 == pclk) || (0 == baud)) + { + return 1000; + } +#endif + + /* SELECT PROPER TABLE BASED UPON MODE */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + p_baud_info = async_baud; + num_divisors = NUM_DIVISORS_ASYNC; +#endif + } + else + { + /* SYNC or SSPI */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + p_baud_info = sync_baud; + num_divisors = NUM_DIVISORS_SYNC; +#endif + } + + /* FIND DIVISOR; table has associated ABCS, BGDM and CKS values */ + /* BRR must be 255 or less */ + /* the "- 1" is ignored in some steps for approximations */ + /* BRR = (PCLK/(divisor * baud)) - 1 */ + /* BRR = (ratio / divisor) - 1 */ + ratio = pclk/baud; + + /* WAIT_LOOP */ + for(i = 0; i < num_divisors; i++) + { + /* Casting int16_t to uint32_t is valid. Because clock divisor is positive integer */ + if (ratio < (uint32_t)(p_baud_info[i].divisor * 256)) + { + break; + } + } + + /* RETURN IF BRR WILL BE >255 OR LESS THAN 0 */ + if (i == num_divisors) + { + return(1000); // impossible baud rate requested; return 100% error + } + + /* Casting int16_t to uint32_t is valid. Because clock divisor is a positive integer */ + divisor = (uint32_t)p_baud_info[i].divisor; + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + if(0 == tmp) + { + return(1000); // illegal value; return 100% error + } + + /* SET BRR, ABCS, BDGM, and CKS */ + tmp = ratio / (divisor/2); // divide by half the divisor + +#if SCI_CFG_FIFO_INCLUDED + /* Casting is valid. Because result of calculation is in range uint8_t type */ + brr = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + if (0 == brr) + { + if (true == hdl->fifo_ctrl) + { + if (1 == hdl->rom->regs->SMR.BIT.CM) + { + if (0 == hdl->rom->regs->SMR.BIT.CKS) + { + return(1000); + } + } + } + } +#endif + + /* if odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */ + hdl->rom->regs->BRR = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + hdl->rom->regs->SEMR.BIT.ABCS = p_baud_info[i].abcs; + hdl->rom->regs->SEMR.BIT.BGDM = p_baud_info[i].bgdm; + hdl->rom->regs->SMR.BIT.CKS = p_baud_info[i].cks; + + /* CALCULATE BIT RATE ERROR. + * RETURN IF ERROR LESS THAN 1% OR IF IN SYNCHRONOUS/SSPI MODE. + */ + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + + /* Casting uint32_t to float is valid */ + error = ( ((float)pclk / ((baud * divisor) * tmp)) - 1) * 100; + abs_error = (error < 0) ? (-error) : error; + + if ((abs_error <= 1.0) || (SCI_MODE_ASYNC != hdl->mode)) + { + hdl->rom->regs->SEMR.BIT.BRME = 0; // disable MDDR + + /* Casting float to uint32_t */ + return (uint32_t)(error*10); + } + + /* CALCULATE M ASSUMING A 0% ERROR then WRITE REGISTER */ + hdl->rom->regs->BRR = (uint8_t)(tmp-1); + + /* Casting uint32_t to float is valid */ + float_M = ((float)((baud * divisor) * 256) * tmp) / pclk; + float_M *= 2; + + /* Casting float to uint32_t */ + int_M = (uint32_t)float_M; + int_M = (int_M & 0x01) ? ((int_M/2) + 1) : (int_M/2); + + /* Casting uint32_t type to uint8_t type in this case is valid. Range value of m is not exceed uint8_t */ + hdl->rom->regs->MDDR = (uint8_t)int_M; // write M + hdl->rom->regs->SEMR.BIT.BRME = 1; // enable MDDR + + /* Casting uint32_t to float is valid*/ + error = (( (float)(pclk) / (((divisor * tmp) * baud) * ((float)(256)/int_M)) ) - 1) * 100; + + /* Casting float to int32_t */ + return (int32_t)(error*10); +} /* End of function sci_init_bit_rate() */ + +/***************************************************************************** +* Function Name: sci_initialize_ints +* Description : This function sets priority, clears flags, and sets +* interrupts in both the ICU and SCI peripheral. These include +* RXI, TXI, TEI, and ERI/GROUP12 interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* priority - +* priority for interrupts +* Return Value : none +******************************************************************************/ +void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority) +{ + volatile bsp_int_ctrl_t group_priority; + + /* SET PRIORITY FOR INTERRUPTS */ + *hdl->rom->ipr_rxi = priority; // can set separately using Control() + *hdl->rom->ipr_txi = priority; + + group_priority.ipl = 0x00000000; +#if ((SCI_CFG_CH0_INCLUDED == 1) || (SCI_CFG_CH1_INCLUDED == 1) || (SCI_CFG_CH2_INCLUDED == 1) || \ + (SCI_CFG_CH3_INCLUDED == 1) || (SCI_CFG_CH4_INCLUDED == 1) || (SCI_CFG_CH5_INCLUDED == 1) || \ + (SCI_CFG_CH6_INCLUDED == 1) || (SCI_CFG_CH12_INCLUDED == 1)) + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPBL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } +#endif + + +#if ((SCI_CFG_CH7_INCLUDED == 1) || (SCI_CFG_CH8_INCLUDED == 1) || (SCI_CFG_CH9_INCLUDED == 1) || \ + (SCI_CFG_CH10_INCLUDED == 1) || (SCI_CFG_CH11_INCLUDED == 1)) + + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPAL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } +#endif + + /* DISABLE ERI INTERRUPT */ + DISABLE_ERI_INT; + + /* DISABLE RXI INTERRUPT */ + DISABLE_RXI_INT; + + /* DISABLE TXI INTERRUPT */ + DISABLE_TXI_INT; + + /* DISABLE TEI INTERRUPT */ + DISABLE_TEI_INT; + + /* CLEAR INTERRUPT FLAGS */ + *hdl->rom->ir_rxi = 0; + *hdl->rom->ir_txi = 0; + (*hdl->rom->icu_grp) &= (~hdl->rom->tei_ch_mask); + (*hdl->rom->icu_grp) &= (~hdl->rom->eri_ch_mask); + + /* REGISTER GROUP INTERRUPTS WITH BSP */ + #if SCI_CFG_TEI_INCLUDED + R_BSP_InterruptWrite(hdl->rom->tei_vector, hdl->rom->tei_isr); + #endif + R_BSP_InterruptWrite(hdl->rom->eri_vector, hdl->rom->eri_isr); + + /* ENABLE GROUP INTERRUPTS */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, (void *)&group_priority); + + /* ENABLE ERI AND RXI INTERRUPTS REQUESTS */ + ENABLE_ERI_INT; + ENABLE_RXI_INT; + + /* ENABLE INTERRUPTS IN SCI PERIPHERAL */ + /* Note: Enable interrupts after xcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; // enable TE, RE, TXI, and RXI/ERI + + return; +} /* End of function sci_initialize_ints() */ + +/***************************************************************************** +* Function Name: sci_disable_ints +* Description : This function disable interrupts in both the ICU and SCI +* peripheral. These include RXI, TXI, TEI, ERI, and group +* interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_disable_ints(sci_hdl_t const hdl) +{ + volatile bsp_int_ctrl_t group_priority; + + /* Disable ICU RXI interrupt */ + DISABLE_RXI_INT; + + /* Disable ICU TXI interrupt */ + DISABLE_TXI_INT; + + /* Disable ICU ERI interrupt */ + DISABLE_ERI_INT; + + /* Disable ICU TEI interrupt */ + DISABLE_TEI_INT; + + /* disable peripheral interrupts and xcvr (TE and RE) */ + hdl->rom->regs->SCR.BYTE = 0; + + /* disable group interrupts */ + group_priority.ipl = 0x00000000; + + /* Casting pointer to void* is valid */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, (void *)&group_priority); + + return; +} /* End of function sci_disable_ints() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_async_cmds +* Description : This function configures non-standard UART hardware and +* performs special software operations. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +******************************************************************************/ +sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + uint32_t slow_baud; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + + /* Check parameters */ + if (((NULL == p_args) || (FIT_NO_PTR == p_args)) + && ((SCI_CMD_TX_Q_BYTES_FREE == cmd) || (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ == cmd)|| (SCI_CMD_COMPARE_RECEIVED_DATA == cmd))) + { + return SCI_ERR_NULL_PTR; + } + +#endif + + switch(cmd) + { + case (SCI_CMD_EN_NOISE_CANCEL): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.NFEN = 1; /* enable noise filter */ + hdl->rom->regs->SNFR.BYTE = 0; /* clock divided by 1 (default) */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_OUTPUT_BAUD_CLK): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCR.BIT.CKE = 0x01; /* output baud clock on SCK pin */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_START_BIT_EDGE): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.RXDESEL = 1; /* detect start bit on falling edge */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + #if SCI_CFG_TEI_INCLUDED + case (SCI_CMD_EN_TEI): /* SCI_CMD_EN_TEI is obsolete command, but it exists only for compatibility with older version. */ + { + break; + } + #endif + + case (SCI_CMD_TX_Q_FLUSH): + { + /* Disable TXI interrupt */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + break; + } + + case (SCI_CMD_RX_Q_FLUSH): + { + /* Disable RXI interrupt */ + DISABLE_RXI_INT; + R_BYTEQ_Flush(hdl->u_rx_data.que); + ENABLE_RXI_INT; + break; + } + + case (SCI_CMD_TX_Q_BYTES_FREE): + { + /* Casting pointer void* to uint16_t* type is valid */ + R_BYTEQ_Unused(hdl->u_tx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ): + { + /* Casting pointer void* type to uint16_t* type is valid */ + R_BYTEQ_Used(hdl->u_rx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_GENERATE_BREAK): + { + /* flush transmit queue */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + + /* NOTE: the following steps will abort anything being sent */ + + /* set baud rate 1.5x slower */ + slow_baud = (hdl->baud_rate << 1) / 3; + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, slow_baud); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; + } + else + { + /* transmit "0" and wait for completion */ + SCI_TDR(0); + + /* WAIT_LOOP */ + while (0 == hdl->rom->regs->SSR.BIT.TEND) + { + R_BSP_NOP(); + } + + /* restore original baud rate */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + sci_init_bit_rate(hdl, hdl->pclk_speed, hdl->baud_rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + break; + } + + #if SCI_CFG_DATA_MATCH_INCLUDED + case SCI_CMD_COMPARE_RECEIVED_DATA: + { + hdl->rom->regs->DCCR.BIT.DFER = 0; /* Clear Match Data Framing Error Flag */ + hdl->rom->regs->DCCR.BIT.DPER = 0; /* Clear Match Data Parity Error Flag */ + hdl->rom->regs->DCCR.BIT.DCME = 1; /* Enable Data match function */ + hdl->rom->regs->CDR.BYTE.L = *((unsigned char *)p_args); /* Comparison data */ + break; + } + #endif + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_async_cmds() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_sync_cmds +* Description : This function performs special software operations specific +* to the SSPI and SYNC protocols. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +* May be due to mode channel is operating in. +******************************************************************************/ +sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_spi_mode_t spi_mode; + sci_cb_args_t args; + sci_err_t err = SCI_SUCCESS; + + switch (cmd) + { + case (SCI_CMD_CHECK_XFER_DONE): + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XFER_NOT_DONE; + } + break; + } + + case (SCI_CMD_XFER_LSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_XFER_MSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_INVERT_DATA): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SINV ^= 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_ABORT_XFER): + { + /* Disable receive interrupts in ICU and peripheral */ + DISABLE_RXI_INT; + DISABLE_ERI_INT; + + hdl->rom->regs->SCR.BYTE &= (~(SCI_SCR_REI_MASK | SCI_SCR_RE_MASK | SCI_SCR_TE_MASK)); + + hdl->tx_cnt = 0; + hdl->tx_dummy = false; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_ABORTED; + + /* Casting pointer to void* is valid */ + hdl->callback((void *)&args); + } + + *hdl->rom->ir_rxi = 0; /* clear rxi interrupt flag */ + (*hdl->rom->icu_grp) &= (~hdl->rom->eri_ch_mask); /* clear eri interrupt flag */ + + ENABLE_ERI_INT; /* enable rx err interrupts in ICU */ + ENABLE_RXI_INT; /* enable receive interrupts in ICU */ + + /* Enable receive interrupt in peripheral after rcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK); + hdl->rom->regs->SCR.BYTE |= SCI_SCR_REI_MASK; + break; + } + + case (SCI_CMD_CHANGE_SPI_MODE): + { + #if SCI_CFG_PARAM_CHECKING_ENABLE + + if (SCI_MODE_SSPI != hdl->mode) + { + return SCI_ERR_INVALID_ARG; + } + + /* Check parameters */ + if ((NULL == p_args ) || (FIT_NO_PTR == p_args)) + { + return SCI_ERR_NULL_PTR; + } + + /* Casting pointer void* type is valid */ + spi_mode = *((sci_spi_mode_t *)p_args); + + if ((SCI_SPI_MODE_0 != spi_mode) && (SCI_SPI_MODE_1 != spi_mode) + && (SCI_SPI_MODE_2 != spi_mode) && (SCI_SPI_MODE_3 != spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + #endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BYTE &= 0x3F; /* clear previous mode */ + hdl->rom->regs->SPMR.BYTE |= (*((uint8_t *)p_args)); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_sync_cmds() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +ISRs +******************************************************************************/ + + +#if (SCI_CFG_ASYNC_INCLUDED) + +/***************************************************************************** +* sciN_txiN_isr +* Description : TXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_txi0_isr + * Description : TXI interrupt routines for SCI0 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_txi0_isr, VECT(SCI0,TXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_txi0_isr(void) +{ + txi_handler(&ch0_ctrl); +} /* End of function sci0_txi0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED  */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_txi1_isr + * Description : TXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_txi1_isr, VECT(SCI1,TXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void) +{ + txi_handler(&ch1_ctrl); +} /* End of function sci1_txi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED  */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_txi2_isr + * Description : TXI interrupt routines for SCI2 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci2_txi2_isr, VECT(SCI2,TXI2)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci2_txi2_isr(void) +{ + txi_handler(&ch2_ctrl); +} /* End of function sci2_txi2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED  */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_txi3_isr + * Description : TXI interrupt routines for SCI3 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci3_txi3_isr, VECT(SCI3,TXI3)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci3_txi3_isr(void) +{ + txi_handler(&ch3_ctrl); +} /* End of function sci3_txi3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED  */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_txi4_isr + * Description : TXI interrupt routines for SCI4 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci4_txi4_isr, VECT(SCI4,TXI4)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci4_txi4_isr(void) +{ + txi_handler(&ch4_ctrl); +} /* End of function sci4_txi4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED  */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_txi5_isr + * Description : TXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_txi5_isr, VECT(SCI5,TXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void) +{ + txi_handler(&ch5_ctrl); +} /* End of function sci5_txi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED  */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_txi6_isr + * Description : TXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_txi6_isr, VECT(SCI6,TXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void) +{ + txi_handler(&ch6_ctrl); +} /* End of function sci6_txi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED  */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_txi7_isr + * Description : TXI interrupt routines for SCI7 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci7_txi7_isr, VECT(SCI7,TXI7)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci7_txi7_isr(void) +{ + txi_handler(&ch7_ctrl); +} /* End of function sci7_txi7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED  */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_txi8_isr + * Description : TXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_txi8_isr, VECT(SCI8,TXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void) +{ + txi_handler(&ch8_ctrl); +} /* End of function sci8_txi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED  */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_txi9_isr + * Description : TXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_txi9_isr, VECT(SCI9,TXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void) +{ + txi_handler(&ch9_ctrl); +} /* End of function sci9_txi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED  */ + +#if SCI_CFG_CH10_INCLUDED +/******************************************************************************* + * Function Name: sci10_txi10_isr + * Description : TXI interrupt routines for SCI10 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci10_txi10_isr, VECT(SCI10,TXI10)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci10_txi10_isr(void) +{ + txi_handler(&ch10_ctrl); +} /* End of function sci10_txi10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED  */ + +#if SCI_CFG_CH11_INCLUDED +/******************************************************************************* + * Function Name: sci11_txi11_isr + * Description : TXI interrupt routines for SCI11 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci11_txi11_isr, VECT(SCI11,TXI11)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci11_txi11_isr(void) +{ + txi_handler(&ch11_ctrl); +} /* End of function sci11_txi11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED  */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_txi12_isr + * Description : TXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_txi12_isr, VECT(SCI12,TXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void) +{ + txi_handler(&ch12_ctrl); +} /* End of function sci12_txi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED  */ + +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* sciN_teiN_isr +* +* Description : TEI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_tei0_isr + * Description : TEI interrupt routines for SCI0 channel. + ******************************************************************************/ +void sci0_tei0_isr(void *cb_args) +{ + tei_handler(&ch0_ctrl); +} /* End of function sci0_tei0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_tei1_isr + * Description : TEI interrupt routines for SCI1 channel. + ******************************************************************************/ +void sci1_tei1_isr(void *cb_args) +{ + tei_handler(&ch1_ctrl); +} /* End of function sci1_tei1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_tei2_isr + * Description : TEI interrupt routines for SCI2 channel. + ******************************************************************************/ +void sci2_tei2_isr(void *cb_args) +{ + tei_handler(&ch2_ctrl); +} /* End of function sci2_tei2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_tei3_isr + * Description : TEI interrupt routines for SCI3 channel. + ******************************************************************************/ +void sci3_tei3_isr(void *cb_args) +{ + tei_handler(&ch3_ctrl); +} /* End of function sci3_tei3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_tei4_isr + * Description : TEI interrupt routines for SCI4 channel. + ******************************************************************************/ +void sci4_tei4_isr(void *cb_args) +{ + tei_handler(&ch4_ctrl); +} /* End of function sci4_tei4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_tei5_isr + * Description : TEI interrupt routines for SCI5 channel. + ******************************************************************************/ +void sci5_tei5_isr(void *cb_args) +{ + tei_handler(&ch5_ctrl); +} /* End of function sci5_tei5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_tei6_isr + * Description : TEI interrupt routines for SCI6 channel. + ******************************************************************************/ +void sci6_tei6_isr(void *cb_args) +{ + tei_handler(&ch6_ctrl); +} /* End of function sci6_tei6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_tei7_isr + * Description : TEI interrupt routines for SCI7 channel. + ******************************************************************************/ +void sci7_tei7_isr(void *cb_args) +{ + tei_handler(&ch7_ctrl); +} /* End of function sci7_tei7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function Name: sci8_tei8_isr +* Description : TEI interrupt routines for SCI8 channel. +******************************************************************************/ +void sci8_tei8_isr(void *cb_args) +{ + tei_handler(&ch8_ctrl); +} /* End of function sci8_tei8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_tei9_isr +* Description : TEI interrupt routines for SCI9 channel. +******************************************************************************/ +void sci9_tei9_isr(void *cb_args) +{ + tei_handler(&ch9_ctrl); +} /* End of function sci9_tei9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/***************************************************************************** +* Function Name: sci10_tei10_isr +* Description : TEI interrupt routines for SCI10 channel. +******************************************************************************/ +void sci10_tei10_isr(void *cb_args) +{ + tei_handler(&ch10_ctrl); +} /* End of function sci10_tei10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/***************************************************************************** +* Function name: sci11_tei11_isr +* Description : TEI interrupt routines for SCI11 channel. +******************************************************************************/ +void sci11_tei11_isr(void *cb_args) +{ + tei_handler(&ch11_ctrl); +} /* End of function sci11_tei11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function Name: sci12_tei12_isr +* Description : TEI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_tei12_isr(void *cb_args) +{ + tei_handler(&ch12_ctrl); +} /* End of function sci12_tei12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +#endif /* SCI_CFG_TEI_INCLUDED */ + +/***************************************************************************** +* sciN_rxiN_isr +* Description : RXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_rxi0_isr + * Description : RXI interrupt routines for SCI0 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_rxi0_isr, VECT(SCI0,RXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_rxi0_isr(void) +{ + rxi_handler(&ch0_ctrl); +} /* End of function sci0_rxi0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_rxi1_isr + * Description : RXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_rxi1_isr, VECT(SCI1,RXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void) +{ + rxi_handler(&ch1_ctrl); +} /* End of function sci1_rxi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_rxi2_isr + * Description : RXI interrupt routines for SCI2 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci2_rxi2_isr, VECT(SCI2,RXI2)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci2_rxi2_isr(void) +{ + rxi_handler(&ch2_ctrl); +} /* End of function sci2_rxi2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_rxi3_isr + * Description : RXI interrupt routines for SCI3 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci3_rxi3_isr, VECT(SCI3,RXI3)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci3_rxi3_isr(void) +{ + rxi_handler(&ch3_ctrl); +} /* End of function sci3_rxi3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_rxi4_isr + * Description : RXI interrupt routines for SCI4 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci4_rxi4_isr, VECT(SCI4,RXI4)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci4_rxi4_isr(void) +{ + rxi_handler(&ch4_ctrl); +} /* End of function sci4_rxi4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_rxi5_isr + * Description : RXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_rxi5_isr, VECT(SCI5,RXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void) +{ + rxi_handler(&ch5_ctrl); +} /* End of function sci5_rxi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_rxi6_isr + * Description : RXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_rxi6_isr, VECT(SCI6,RXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void) +{ + rxi_handler(&ch6_ctrl); +} /* End of function sci6_rxi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_rxi7_isr + * Description : RXI interrupt routines for SCI7 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci7_rxi7_isr, VECT(SCI7,RXI7)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci7_rxi7_isr(void) +{ + rxi_handler(&ch7_ctrl); +} /* End of function sci7_rxi7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_rxi8_isr + * Description : RXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_rxi8_isr, VECT(SCI8,RXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void) +{ + rxi_handler(&ch8_ctrl); +} /* End of function sci8_rxi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_rxi9_isr + * Description : RXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_rxi9_isr, VECT(SCI9,RXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void) +{ + rxi_handler(&ch9_ctrl); +} /* End of function sci9_rxi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/******************************************************************************* + * Function Name: sci10_rxi10_isr + * Description : RXI interrupt routines for SCI10 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci10_rxi10_isr, VECT(SCI10,RXI10)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci10_rxi10_isr(void) +{ + rxi_handler(&ch10_ctrl); +} /* End of function sci10_rxi10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/******************************************************************************* + * Function Name: sci11_rxi11_isr + * Description : RXI interrupt routines for SCI11 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci11_rxi11_isr, VECT(SCI11,RXI11)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci11_rxi11_isr(void) +{ + rxi_handler(&ch11_ctrl); +} /* End of function sci11_rxi11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_rxi12_isr + * Description : RXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_rxi12_isr, VECT(SCI12,RXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void) +{ + rxi_handler(&ch12_ctrl); +} /* End of function sci12_rxi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +/***************************************************************************** +* sciN_eriN_isr +* +* Description : ERI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/***************************************************************************** +* Function name: sci0_eri0_isr +* Description : ERI interrupt routines for SCI0 channel. +******************************************************************************/ +void sci0_eri0_isr(void *cb_args) +{ + eri_handler(&ch0_ctrl); +} /* End of function sci0_eri0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/***************************************************************************** +* Function name: sci1_eri1_isr +* Description : ERI interrupt routines for SCI1 channel. +******************************************************************************/ +void sci1_eri1_isr(void *cb_args) +{ + eri_handler(&ch1_ctrl); +} /* End of function sci1_eri1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/***************************************************************************** +* Function name: sci2_eri2_isr +* Description : ERI interrupt routines for SCI2 channel. +******************************************************************************/ +void sci2_eri2_isr(void *cb_args) +{ + eri_handler(&ch2_ctrl); +} /* End of function sci2_eri2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/***************************************************************************** +* Function name: sci3_eri3_isr +* Description : ERI interrupt routines for SCI3 channel. +******************************************************************************/ +void sci3_eri3_isr(void *cb_args) +{ + eri_handler(&ch3_ctrl); +} /* End of function sci3_eri3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/***************************************************************************** +* Function name: sci4_eri4_isr +* Description : ERI interrupt routines for SCI4 channel. +******************************************************************************/ +void sci4_eri4_isr(void *cb_args) +{ + eri_handler(&ch4_ctrl); +} /* End of function sci4_eri4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/***************************************************************************** +* Function name: sci5_eri5_isr +* Description : ERI interrupt routines for SCI5 channel. +******************************************************************************/ +void sci5_eri5_isr(void *cb_args) +{ + eri_handler(&ch5_ctrl); +} /* End of function sci5_eri5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/***************************************************************************** +* Function name: sci6_eri6_isr +* Description : ERI interrupt routines for SCI6 channel. +******************************************************************************/ +void sci6_eri6_isr(void *cb_args) +{ + eri_handler(&ch6_ctrl); +} /* End of function sci6_eri6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/***************************************************************************** +* Function name: sci7_eri7_isr +* Description : ERI interrupt routines for SCI7 channel. +******************************************************************************/ +void sci7_eri7_isr(void *cb_args) +{ + eri_handler(&ch7_ctrl); +} /* End of function sci7_eri7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function name: sci8_eri8_isr +* Description : ERI interrupt routines for SCI8 channel. +******************************************************************************/ +void sci8_eri8_isr(void *cb_args) +{ + eri_handler(&ch8_ctrl); +} /* End of function sci8_eri8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_eri9_isr +* Description : ERI interrupt routines for SCI9 channel. +******************************************************************************/ +void sci9_eri9_isr(void *cb_args) +{ + eri_handler(&ch9_ctrl); +} /* End of function sci9_eri9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/***************************************************************************** +* Function name: sci10_eri10_isr +* Description : ERI interrupt routines for SCI10 channel. +******************************************************************************/ +void sci10_eri10_isr(void *cb_args) +{ + eri_handler(&ch10_ctrl); +} /* End of function sci10_eri10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/***************************************************************************** +* Function name: sci11_eri11_isr +* Description : ERI interrupt routines for SCI11 channel. +******************************************************************************/ +void sci11_eri11_isr(void *cb_args) +{ + eri_handler(&ch11_ctrl); +} /* End of function sci11_eri11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function name: sci12_eri12_isr +* Description : ERI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_eri12_isr(void *cb_args) +{ + eri_handler(&ch12_ctrl); +} /* End of function sci12_eri12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c new file mode 100644 index 000000000..734b852dd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c @@ -0,0 +1,641 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx72n_data.c +* Description : Functions for using SCI on the RX72N device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx72n_private.h" + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* BAUD DIVISOR INFO */ + +/* Asynchronous */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=0 & bgdm=0, divisor = 64*pow(2,2n-1) */ +/* when abcs=1 & bgdm=0 OR abcs=0 & bgdm=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=1 & bgdm=1, divisor = 16*pow(2,2n-1) */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/* NOTE: diff than SCI async baud table, but should provide same results */ +const baud_divisor_t async_baud[NUM_DIVISORS_ASYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {8, 1, 1, 0}, + {16, 0, 1, 0}, + {32, 0, 0, 0}, + {64, 0, 1, 1}, + {128, 0, 0, 1}, + {256, 0, 1, 2}, + {512, 0, 0, 2}, + {1024, 0, 1, 3}, + {2048, 0, 0, 3} +}; +#endif + +/* Synchronous and Simple SPI */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* abcs=0, bdgm=0, divisor = 8*pow(2,2n-1) */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/* NOTE: Identical to SCI sync baud table */ +const baud_divisor_t sync_baud[NUM_DIVISORS_SYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {4, 0, 0, 0}, + {16, 0, 0, 1}, + {64, 0, 0, 2}, + {256, 0, 0, 3} +}; +#endif + + +/* CHANNEL MEMORY ALLOCATIONS */ + +#if SCI_CFG_CH0_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch0_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI0, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT31_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI0_TEI0, sci0_tei0_isr, + #endif + BSP_INT_SRC_BL0_SCI0_ERI0, sci0_eri0_isr, + BIT0_MASK, BIT1_MASK, + &ICU.IPR[IPR_SCI0_RXI0].BYTE, + &ICU.IPR[IPR_SCI0_TXI0].BYTE, + &ICU.IR[IR_SCI0_RXI0].BYTE, + &ICU.IR[IR_SCI0_TXI0].BYTE, + &ICU.IER[IER_SCI0_RXI0].BYTE, + &ICU.IER[IER_SCI0_TXI0].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch0_ctrl = {&ch0_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH0_INCLUDED */ + + +#if SCI_CFG_CH1_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch1_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI1, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT30_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI1_TEI1, sci1_tei1_isr, + #endif + BSP_INT_SRC_BL0_SCI1_ERI1, sci1_eri1_isr, + BIT2_MASK, BIT3_MASK, + &ICU.IPR[IPR_SCI1_RXI1].BYTE, + &ICU.IPR[IPR_SCI1_TXI1].BYTE, + &ICU.IR[IR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_TXI1].BYTE, + &ICU.IER[IER_SCI1_RXI1].BYTE, + &ICU.IER[IER_SCI1_TXI1].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch1_ctrl = {&ch1_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH1_INCLUDED */ + + +#if SCI_CFG_CH2_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch2_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI2, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT29_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI2_TEI2, sci2_tei2_isr, + #endif + BSP_INT_SRC_BL0_SCI2_ERI2, sci2_eri2_isr, + BIT4_MASK, BIT5_MASK, + &ICU.IPR[IPR_SCI2_RXI2].BYTE, + &ICU.IPR[IPR_SCI2_TXI2].BYTE, + &ICU.IR[IR_SCI2_RXI2].BYTE, + &ICU.IR[IR_SCI2_TXI2].BYTE, + &ICU.IER[IER_SCI2_RXI2].BYTE, + &ICU.IER[IER_SCI2_TXI2].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch2_ctrl = {&ch2_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH2_INCLUDED */ + + +#if SCI_CFG_CH3_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch3_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI3, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT28_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI3_TEI3, sci3_tei3_isr, + #endif + BSP_INT_SRC_BL0_SCI3_ERI3, sci3_eri3_isr, + BIT6_MASK, BIT7_MASK, + &ICU.IPR[IPR_SCI3_RXI3].BYTE, + &ICU.IPR[IPR_SCI3_TXI3].BYTE, + &ICU.IR[IR_SCI3_RXI3].BYTE, + &ICU.IR[IR_SCI3_TXI3].BYTE, + &ICU.IER[IER_SCI3_RXI3].BYTE, + &ICU.IER[IER_SCI3_TXI3].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT0_MASK, BIT1_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch3_ctrl = {&ch3_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH3_INCLUDED */ + + +#if SCI_CFG_CH4_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch4_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI4, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT27_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI4_TEI4, sci4_tei4_isr, + #endif + BSP_INT_SRC_BL0_SCI4_ERI4, sci4_eri4_isr, + BIT8_MASK, BIT9_MASK, + &ICU.IPR[IPR_SCI4_RXI4].BYTE, + &ICU.IPR[IPR_SCI4_TXI4].BYTE, + &ICU.IR[IR_SCI4_RXI4].BYTE, + &ICU.IR[IR_SCI4_TXI4].BYTE, + &ICU.IER[IER_SCI4_RXI4].BYTE, + &ICU.IER[IER_SCI4_TXI4].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch4_ctrl = {&ch4_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH4_INCLUDED */ + + +#if SCI_CFG_CH5_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch5_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI5, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI5_TEI5, sci5_tei5_isr, + #endif + BSP_INT_SRC_BL0_SCI5_ERI5, sci5_eri5_isr, + BIT10_MASK, BIT11_MASK, + &ICU.IPR[IPR_SCI5_RXI5].BYTE, + &ICU.IPR[IPR_SCI5_TXI5].BYTE, + &ICU.IR[IR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_TXI5].BYTE, + &ICU.IER[IER_SCI5_RXI5].BYTE, + &ICU.IER[IER_SCI5_TXI5].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch5_ctrl = {&ch5_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH5_INCLUDED */ + + +#if SCI_CFG_CH6_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch6_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI6, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI6_TEI6, sci6_tei6_isr, + #endif + BSP_INT_SRC_BL0_SCI6_ERI6, sci6_eri6_isr, + BIT12_MASK, BIT13_MASK, + &ICU.IPR[IPR_SCI6_RXI6].BYTE, + &ICU.IPR[IPR_SCI6_TXI6].BYTE, + &ICU.IR[IR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_TXI6].BYTE, + &ICU.IER[IER_SCI6_RXI6].BYTE, + &ICU.IER[IER_SCI6_TXI6].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch6_ctrl = {&ch6_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH6_INCLUDED */ + + +#if SCI_CFG_CH7_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch7_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI7, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT24_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI7_TEI7, sci7_tei7_isr, + #endif + BSP_INT_SRC_AL0_SCI7_ERI7, sci7_eri7_isr, + BIT22_MASK, BIT23_MASK, + &ICU.IPR[IPR_SCI7_RXI7].BYTE, + &ICU.IPR[IPR_SCI7_TXI7].BYTE, + &ICU.IR[IR_SCI7_RXI7].BYTE, + &ICU.IR[IR_SCI7_TXI7].BYTE, + &ICU.IER[IER_SCI7_RXI7].BYTE, + &ICU.IER[IER_SCI7_TXI7].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch7_ctrl = {&ch7_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH7_FIFO_INCLUDED + , SCI_CFG_CH7_RX_FIFO_THRESH + , SCI_CFG_CH7_RX_FIFO_THRESH + , SCI_CFG_CH7_TX_FIFO_THRESH + , SCI_CFG_CH7_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH7_INCLUDED */ + + +#if SCI_CFG_CH8_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch8_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI8, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT27_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI8_TEI8, sci8_tei8_isr, + #endif + BSP_INT_SRC_AL0_SCI8_ERI8, sci8_eri8_isr, + BIT0_MASK, BIT1_MASK, + &ICU.IPR[IPR_SCI8_RXI8].BYTE, + &ICU.IPR[IPR_SCI8_TXI8].BYTE, + &ICU.IR[IR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_TXI8].BYTE, + &ICU.IER[IER_SCI8_RXI8].BYTE, + &ICU.IER[IER_SCI8_TXI8].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch8_ctrl = {&ch8_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH8_FIFO_INCLUDED + , SCI_CFG_CH8_RX_FIFO_THRESH + , SCI_CFG_CH8_RX_FIFO_THRESH + , SCI_CFG_CH8_TX_FIFO_THRESH + , SCI_CFG_CH8_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch9_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI9, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI9_TEI9, sci9_tei9_isr, + #endif + BSP_INT_SRC_AL0_SCI9_ERI9, sci9_eri9_isr, + BIT4_MASK, BIT5_MASK, + &ICU.IPR[IPR_SCI9_RXI9].BYTE, + &ICU.IPR[IPR_SCI9_TXI9].BYTE, + &ICU.IR[IR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_TXI9].BYTE, + &ICU.IER[IER_SCI9_RXI9].BYTE, + &ICU.IER[IER_SCI9_TXI9].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch9_ctrl = {&ch9_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH9_FIFO_INCLUDED + , SCI_CFG_CH9_RX_FIFO_THRESH + , SCI_CFG_CH9_RX_FIFO_THRESH + , SCI_CFG_CH9_TX_FIFO_THRESH + , SCI_CFG_CH9_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH9_INCLUDED */ + + +#if SCI_CFG_CH10_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch10_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI10, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI10_TEI10, sci10_tei10_isr, + #endif + BSP_INT_SRC_AL0_SCI10_ERI10, sci10_eri10_isr, + BIT8_MASK, BIT9_MASK, + &ICU.IPR[IPR_SCI10_RXI10].BYTE, + &ICU.IPR[IPR_SCI10_TXI10].BYTE, + &ICU.IR[IR_SCI10_RXI10].BYTE, + &ICU.IR[IR_SCI10_TXI10].BYTE, + &ICU.IER[IER_SCI10_RXI10].BYTE, + &ICU.IER[IER_SCI10_TXI10].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT0_MASK, BIT1_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch10_ctrl = {&ch10_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH10_FIFO_INCLUDED + , SCI_CFG_CH10_RX_FIFO_THRESH + , SCI_CFG_CH10_RX_FIFO_THRESH + , SCI_CFG_CH10_TX_FIFO_THRESH + , SCI_CFG_CH10_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH10_INCLUDED */ + + +#if SCI_CFG_CH11_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch11_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI11, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT24_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI11_TEI11, sci11_tei11_isr, + #endif + BSP_INT_SRC_AL0_SCI11_ERI11, sci11_eri11_isr, + BIT12_MASK, BIT13_MASK, + &ICU.IPR[IPR_SCI11_RXI11].BYTE, + &ICU.IPR[IPR_SCI11_TXI11].BYTE, + &ICU.IR[IR_SCI11_RXI11].BYTE, + &ICU.IR[IR_SCI11_TXI11].BYTE, + &ICU.IER[IER_SCI11_RXI11].BYTE, + &ICU.IER[IER_SCI11_TXI11].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch11_ctrl = {&ch11_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH11_FIFO_INCLUDED + , SCI_CFG_CH11_RX_FIFO_THRESH + , SCI_CFG_CH11_RX_FIFO_THRESH + , SCI_CFG_CH11_TX_FIFO_THRESH + , SCI_CFG_CH11_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH11_INCLUDED */ + + +#if SCI_CFG_CH12_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch12_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI12, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT4_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI12_TEI12, sci12_tei12_isr, + #endif + BSP_INT_SRC_BL0_SCI12_ERI12, sci12_eri12_isr, + BIT16_MASK, BIT17_MASK, + &ICU.IPR[IPR_SCI12_RXI12].BYTE, + &ICU.IPR[IPR_SCI12_TXI12].BYTE, + &ICU.IR[IR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_TXI12].BYTE, + &ICU.IER[IER_SCI12_RXI12].BYTE, + &ICU.IER[IER_SCI12_TXI12].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch12_ctrl = {&ch12_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH12_INCLUDED */ + + +/* SCI HANDLE-ARRAY DECLARATION */ + +const sci_hdl_t g_handles[SCI_NUM_CH] = +{ +#if SCI_CFG_CH0_INCLUDED + &ch0_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH1_INCLUDED + &ch1_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH2_INCLUDED + &ch2_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH3_INCLUDED + &ch3_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH4_INCLUDED + &ch4_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH5_INCLUDED + &ch5_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH6_INCLUDED + &ch6_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH7_INCLUDED + &ch7_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH8_INCLUDED + &ch8_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH9_INCLUDED + &ch9_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH10_INCLUDED + &ch10_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH11_INCLUDED + &ch11_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH12_INCLUDED + &ch12_ctrl +#else + NULL +#endif +}; + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h new file mode 100644 index 000000000..6760bf730 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h @@ -0,0 +1,320 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx72n_private.h +* Description : Functions for using SCI on the RX72N device. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +#ifndef SCI_RX72N_H +#define SCI_RX72N_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../../r_sci_rx_private.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* Mask of all active channels */ +#define SCI_CFG_CH_INCLUDED_MASK ((SCI_CFG_CH0_INCLUDED << 0) | \ + (SCI_CFG_CH1_INCLUDED << 1) | \ + (SCI_CFG_CH2_INCLUDED << 2) | \ + (SCI_CFG_CH3_INCLUDED << 3) | \ + (SCI_CFG_CH4_INCLUDED << 4) | \ + (SCI_CFG_CH5_INCLUDED << 5) | \ + (SCI_CFG_CH6_INCLUDED << 6) | \ + (SCI_CFG_CH7_INCLUDED << 7) | \ + (SCI_CFG_CH8_INCLUDED << 8) | \ + (SCI_CFG_CH9_INCLUDED << 9) | \ + (SCI_CFG_CH10_INCLUDED << 10) | \ + (SCI_CFG_CH11_INCLUDED << 11) | \ + (SCI_CFG_CH12_INCLUDED << 12)) + +/* SCI SCR register masks */ +#define SCI_SCR_TEI_MASK (0x80U) /* transmit interrupt enable */ +#define SCI_SCR_REI_MASK (0x40U) /* receive interrupt enable */ +#define SCI_SCR_TE_MASK (0x20U) /* transmitter enable */ +#define SCI_SCR_RE_MASK (0x10U) /* receiver enable */ +#define SCI_EN_XCVR_MASK (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK | SCI_SCR_REI_MASK | SCI_SCR_TEI_MASK) + +/* SCI SSR register receiver error masks */ +#define SCI_SSR_ORER_MASK (0x20U) /* overflow error */ +#define SCI_SSR_FER_MASK (0x10U) /* framing error */ +#define SCI_SSR_PER_MASK (0x08U) /* parity err */ +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) +#define SCI_SSR_CLR_MASK (0xC0U) /* SSR register cleare mask (11000000b) */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_CLR_MASK (0xC6U) /* SSR register cleare mask (11000110b) */ +#define SCI_SSRFIFO_TDFE_MASK (0x80U) /* SSR register transmit data empty flag mask (10000000b) */ +#define SCI_SSRFIFO_RDF_MASK (0x40U) /* SSR register receive FIFO full flag mask (01000000b) */ +#define SCI_SSRFIFO_DR_MASK (0x01U) /* SSR register receive DR flag mask (00000001b) */ +#endif + +/* Macros to enable and disable ICU interrupts */ +#define ENABLE_RXI_INT (*hdl->rom->icu_rxi |= hdl->rom->rxi_en_mask) +#define DISABLE_RXI_INT (*hdl->rom->icu_rxi &= (uint8_t)~hdl->rom->rxi_en_mask) +#define ENABLE_TXI_INT (*hdl->rom->icu_txi |= hdl->rom->txi_en_mask) +#define DISABLE_TXI_INT (*hdl->rom->icu_txi &= (uint8_t)~hdl->rom->txi_en_mask) + +#define ENABLE_ERI_INT (*hdl->rom->icu_grp |= hdl->rom->eri_ch_mask) +#define DISABLE_ERI_INT (*hdl->rom->icu_grp &= ~hdl->rom->eri_ch_mask) +#define ENABLE_TEI_INT (*hdl->rom->icu_grp |= hdl->rom->tei_ch_mask) +#define DISABLE_TEI_INT (*hdl->rom->icu_grp &= ~hdl->rom->tei_ch_mask) + +#define NUM_DIVISORS_ASYNC (9) +#define NUM_DIVISORS_SYNC (4) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* ROM INFO */ + +typedef struct st_sci_ch_rom /* SCI ROM info for channel control block */ +{ + volatile struct st_sci7 R_BSP_EVENACCESS_SFR *regs; /* base ptr to ch registers */ + volatile uint32_t R_BSP_EVENACCESS_SFR *mstp; /* ptr to mstp register */ + uint32_t stop_mask; /* mstp mask to disable ch */ +#if SCI_CFG_TEI_INCLUDED + bsp_int_src_t tei_vector; + bsp_int_cb_t tei_isr; +#endif + bsp_int_src_t eri_vector; + bsp_int_cb_t eri_isr; + uint32_t tei_ch_mask; /* ICU IR and IEN mask */ + uint32_t eri_ch_mask; /* ICU IR and IEN mask */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_rxi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_txi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_rxi; /* ptr to RXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_txi; /* ptr to TXI IR register */ + + /* + * DO NOT use the enable/disable interrupt bits in the SCR + * register. Pending interrupts can be lost that way. + */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_rxi; /* ptr to ICU register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_txi; + volatile uint32_t R_BSP_EVENACCESS_SFR *icu_grp; + uint8_t rxi_en_mask; /* ICU enable/disable rxi mask */ + uint8_t txi_en_mask; /* ICU enable/disable txi mask */ +} sci_ch_rom_t; + + +/* CHANNEL CONTROL BLOCK */ + +typedef struct st_sci_ch_ctrl /* SCI channel control (for handle) */ +{ + sci_ch_rom_t const *rom; /* pointer to rom info */ + sci_mode_t mode; /* operational mode */ + uint32_t baud_rate; /* baud rate */ + void (*callback)(void *p_args); /* function ptr for rcvr errs */ + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async transmit queue handle */ +#endif + uint8_t *buf; /* sspi/sync tx buffer ptr */ + } u_tx_data; + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async receive queue handle */ +#endif + uint8_t *buf; /* sspi/sync rx buffer ptr */ + } u_rx_data; + bool tx_idle; /* TDR is empty (async); TSR is empty (sync/sspi) */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + bool save_rx_data; /* save the data that is clocked in */ + uint16_t tx_cnt; /* number of bytes to transmit */ + uint16_t rx_cnt; /* number of bytes to receive */ + bool tx_dummy; /* transmit dummy byte, not buffer */ +#endif + uint32_t pclk_speed; /* saved peripheral clock speed for break generation */ +#if SCI_CFG_FIFO_INCLUDED + uint8_t fifo_ctrl; /* fifo ctrl (enable/disable) flag */ + uint8_t rx_dflt_thresh; /* RX FIFO threshold(default) */ + uint8_t rx_curr_thresh; /* RX FIFO threshold(current) */ + uint8_t tx_dflt_thresh; /* TX FIFO threshold(default) */ + uint8_t tx_curr_thresh; /* TX FIFO threshold(current) */ +#endif +} sci_ch_ctrl_t; + + +/* BAUD DIVISOR INFO */ + +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=0, divisor = 64*pow(2,2n-1) */ + +typedef struct st_baud_divisor +{ + int16_t divisor; // clock divisor + uint8_t abcs; // abcs value to get divisor + uint8_t bgdm; // bdgm value to get divisor + uint8_t cks; // cks value to get divisor (cks = n) +} baud_divisor_t; + + + +/***************************************************************************** +Exported global variables and functions +******************************************************************************/ +extern const sci_hdl_t g_sci_handles[]; + +#if (SCI_CFG_ASYNC_INCLUDED) +extern const baud_divisor_t async_baud[]; +#endif +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern const baud_divisor_t sync_baud[]; +#endif + +#if (SCI_CFG_CH0_INCLUDED) +extern const sci_ch_rom_t ch0_rom; +extern sci_ch_ctrl_t ch0_ctrl; +#endif + +#if (SCI_CFG_CH1_INCLUDED) +extern const sci_ch_rom_t ch1_rom; +extern sci_ch_ctrl_t ch1_ctrl; +#endif + +#if (SCI_CFG_CH2_INCLUDED) +extern const sci_ch_rom_t ch2_rom; +extern sci_ch_ctrl_t ch2_ctrl; +#endif + +#if (SCI_CFG_CH3_INCLUDED) +extern const sci_ch_rom_t ch3_rom; +extern sci_ch_ctrl_t ch3_ctrl; +#endif + +#if (SCI_CFG_CH4_INCLUDED) +extern const sci_ch_rom_t ch4_rom; +extern sci_ch_ctrl_t ch4_ctrl; +#endif + +#if (SCI_CFG_CH5_INCLUDED) +extern const sci_ch_rom_t ch5_rom; +extern sci_ch_ctrl_t ch5_ctrl; +#endif + +#if (SCI_CFG_CH6_INCLUDED) +extern const sci_ch_rom_t ch6_rom; +extern sci_ch_ctrl_t ch6_ctrl; +#endif + +#if (SCI_CFG_CH7_INCLUDED) +extern const sci_ch_rom_t ch7_rom; +extern sci_ch_ctrl_t ch7_ctrl; +#endif + +#if (SCI_CFG_CH8_INCLUDED) +extern const sci_ch_rom_t ch8_rom; +extern sci_ch_ctrl_t ch8_ctrl; +#endif + +#if (SCI_CFG_CH9_INCLUDED) +extern const sci_ch_rom_t ch9_rom; +extern sci_ch_ctrl_t ch9_ctrl; +#endif + +#if (SCI_CFG_CH10_INCLUDED) +extern const sci_ch_rom_t ch10_rom; +extern sci_ch_ctrl_t ch10_ctrl; +#endif + +#if (SCI_CFG_CH11_INCLUDED) +extern const sci_ch_rom_t ch11_rom; +extern sci_ch_ctrl_t ch11_ctrl; +#endif + +#if (SCI_CFG_CH12_INCLUDED) +extern const sci_ch_rom_t ch12_rom; +extern sci_ch_ctrl_t ch12_ctrl; +#endif + +/***************************************************************************** +Exported global functions +******************************************************************************/ +#if SCI_CFG_TEI_INCLUDED +extern void sci0_tei0_isr(void *cb_args); +extern void sci1_tei1_isr(void *cb_args); +extern void sci2_tei2_isr(void *cb_args); +extern void sci3_tei3_isr(void *cb_args); +extern void sci4_tei4_isr(void *cb_args); +extern void sci5_tei5_isr(void *cb_args); +extern void sci6_tei6_isr(void *cb_args); +extern void sci7_tei7_isr(void *cb_args); +extern void sci8_tei8_isr(void *cb_args); +extern void sci9_tei9_isr(void *cb_args); +extern void sci10_tei10_isr(void *cb_args); +extern void sci11_tei11_isr(void *cb_args); +extern void sci12_tei12_isr(void *cb_args); +#endif /* End of SCI_CFG_TEI_INCLUDED */ + +extern void sci0_eri0_isr(void *cb_args); +extern void sci1_eri1_isr(void *cb_args); +extern void sci2_eri2_isr(void *cb_args); +extern void sci3_eri3_isr(void *cb_args); +extern void sci4_eri4_isr(void *cb_args); +extern void sci5_eri5_isr(void *cb_args); +extern void sci6_eri6_isr(void *cb_args); +extern void sci7_eri7_isr(void *cb_args); +extern void sci8_eri8_isr(void *cb_args); +extern void sci9_eri9_isr(void *cb_args); +extern void sci10_eri10_isr(void *cb_args); +extern void sci11_eri11_isr(void *cb_args); +extern void sci12_eri12_isr(void *cb_args); + +extern void sci_init_register(sci_hdl_t const hdl); + +#if (SCI_CFG_ASYNC_INCLUDED) +extern sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +extern sci_err_t sci_mcu_param_check(uint8_t const chan); + +extern int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud); + +extern void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority); + +extern void sci_disable_ints(sci_hdl_t const hdl); + +#endif /* SCI_RX72N_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/CC_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/CC_patch.h new file mode 100644 index 000000000..5f604deb9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/CC_patch.h @@ -0,0 +1,22 @@ +#ifndef CC_PATCH_H +#define CC_PATCH_H + +#if defined(__CCRX__) + +/* This file has to be included by using CC-RX's -preinclude option. */ + +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#ifndef _FEVAL +#define _FEVAL 0 +#endif +#ifndef _FEVVAL +#define _FEVVAL 0 +#endif +#ifndef _HAS_C9X_FAST_FMA +#define _HAS_C9X_FAST_FMA 0 +#endif + +#endif /* defined(__CCRX__) */ + +#endif /* CC_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/CG_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/CG_patch.h new file mode 100644 index 000000000..d390aeb5b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/CG_patch.h @@ -0,0 +1,9 @@ +#ifndef CG_PATCH_H +#define CG_PATCH_H + +/* Workaround for warning messages caused by missing function declaration. + */ +void R_CGC_Create_UserInit(void); +void r_undefined_exception(void); + +#endif /* CG_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch.c new file mode 100644 index 000000000..4f6af1b8e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch.c @@ -0,0 +1,63 @@ +#include "platform.h" +#include + +#if BSP_CFG_RTOS_USED != 0 + +/* Replacement to be thread-safe (in case of other than using heap_3.c). */ +void *malloc( size_t xWantedSize ) +{ +#if BSP_CFG_RTOS_USED == 1 + /* FreeRTOS */ + + return pvPortMalloc( xWantedSize ); +#else + /* SEGGER embOS */ + /* Micrium MicroC/OS */ + /* Renesas RI600V4 & RI600PX */ + + #error "Unsupported RTOS is selected." +#endif +} + +/* Replacement to be thread-safe (in case of other than using heap_3.c). */ +void free( void *pv ) +{ +#if BSP_CFG_RTOS_USED == 1 + /* FreeRTOS */ + + vPortFree( pv ); +#else + /* SEGGER embOS */ + /* Micrium MicroC/OS */ + /* Renesas RI600V4 & RI600PX */ + + #error "Unsupported RTOS is selected." +#endif +} + +#if defined(__GNUC__) + +int8_t *sbrk( size_t size ); + +/* Maybe not called but necessary for linking without an undefined error. */ +int8_t *sbrk( size_t size ) +{ + ( void ) size; + return (int8_t *)-1; +} + +#endif /* defined(__GNUC__) */ + +#if defined(__ICCRX__) + +void main( void ); + +/* Never called but necessary for linking without an undefined error. */ +void main( void ) +{ + /* Nothing to do. */ +} + +#endif /* defined(__ICCRX__) */ + +#endif /* BSP_CFG_RTOS_USED != 0 */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch.h new file mode 100644 index 000000000..cfc555838 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch.h @@ -0,0 +1,32 @@ +#ifndef FIT_PATCH_H +#define FIT_PATCH_H + +/* Workaround for the stand alone RX SmartConfigurator's missing support of FreeRTOS project. + */ +#define BSP_CFG_RTOS_USED (1) + +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#define SCI_CFG_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_FIFO_INCLUDED (0) + +/* Workaround for warning messages caused by missing 'void' argument prototype. + */ +void R_SCI_PinSet_SCI2(void); +void R_SCI_PinSet_SCI9(void); + +#if defined(__ICCRX__) + +/* Workaround to reduce the following remark messages caused in the r_rx_compiler.h. + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * Turn off the remark messages temporarily. + */ +#pragma diag_suppress = Pe007 + +#endif /* defined(__ICCRX__) */ + +#endif /* FIT_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch2.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch2.h new file mode 100644 index 000000000..010be9edb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/FIT_patch2.h @@ -0,0 +1,60 @@ +#ifndef FIT_PATCH2_H +#define FIT_PATCH2_H + +#if defined(__ICCRX__) + +/* Workaround to reduce the following remark messages caused in the r_rx_compiler.h. + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * Turn on the remark messages here. + */ +#pragma diag_default = Pe007 + +/* Workaround to reduce the following remark messages. (The following is example.) + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * R_BSP_ASM( SUB #01H, R1 ) + * ^ + * "XXX\r_bsp_common.c",NNN Remark[Pe010]: "#" not expected here + * + * R_BSP_ASM_BEGIN + * ^ + * "XXX\r_bsp_common.c",NNN Remark[Pa174]: inline assembler statement has no declared + * side-effect. All optimizations around it will be disabled. Either add side-effect + * declarations or add volatile. + * + * Now redefine the following macros. + */ +#if !defined(__CDT_PARSER__) + +#undef _R_BSP_ASM +#undef R_BSP_ASM +/* #undef R_BSP_ASM_LAB_NEXT */ /* no change */ +/* #undef R_BSP_ASM_LAB_PREV */ /* no change */ +/* #undef R_BSP_ASM_LAB */ /* no change */ +#undef R_BSP_ASM_BEGIN +#undef R_BSP_ASM_END + +#define _R_BSP_ASM(...) #__VA_ARGS__ "\n" +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__) +/* #define R_BSP_ASM_LAB_NEXT(n) _lab##n */ /* no change */ +/* #define R_BSP_ASM_LAB_PREV(n) _lab##n */ /* no change */ +/* #define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) */ /* no change */ +#define R_BSP_ASM_BEGIN R_BSP_PRAGMA(diag_suppress = Pa174)\ + R_BSP_PRAGMA(diag_suppress = Pe010)\ + __asm volatile( +#define R_BSP_ASM_END );\ + R_BSP_PRAGMA(diag_default = Pe010)\ + R_BSP_PRAGMA(diag_default = Pa174) + +#endif /* !defined(__CDT_PARSER__) */ + +#endif /* defined(__ICCRX__) */ + +#endif /* FIT_PATCH2_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/IDE_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/IDE_patch.h new file mode 100644 index 000000000..0c5dcdbb1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/IDE_patch.h @@ -0,0 +1,42 @@ +#ifndef IDE_PATCH_H +#define IDE_PATCH_H + +#if defined(__CDT_PARSER__) + +#if defined(__CCRX__) + +/* Workaround for missing pre-defined macro in the Renesas Toolchain Builtin + * Language Settings. + */ +#ifndef __TFU +#define __TFU 1 +#endif + +/* Workaround for wrong pre-defined macro in the Renesas Toolchain Builtin + * Language Settings. + */ +#ifdef __DBL4 +#undef __DBL4 +#endif +#ifndef __DBL8 +#define __DBL8 1 +#endif + +#endif /* defined(__CCRX__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. + */ +#ifndef __asm +#define __asm asm +#endif +#ifndef __attribute__ +#define __attribute__(...) +#endif + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +#endif /* defined(__CDT_PARSER__) */ + +#endif /* IDE_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_bsp_patch/platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_bsp_patch/platform.h new file mode 100644 index 000000000..d7cec9d35 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_bsp_patch/platform.h @@ -0,0 +1,17 @@ +#ifndef PLATFORM_PATCH_H +#define PLATFORM_PATCH_H + +#include "../smc_gen/r_bsp/platform.h" + +/* In case of stand alone Smart Configurator and CS+, generating source code places + * the /src/smc_gen/r_bsp folder prior to the /src/smc_workaround/r_bsp_patch folder + * in the include folder list so that including patch files here is not recommended + * when CC-RX is used. + */ +#if defined(__GNUC__) || defined(__ICCRX__) + +#include "FIT_patch2.h" + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +#endif /* PLATFORM_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c new file mode 100644 index 000000000..ee873a979 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c @@ -0,0 +1,5 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#include "../../smc_gen/r_dtc_rx/r_dtc_rx_if.h" +#include "../../smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h" +#include "../../smc_gen/r_dtc_rx/src/r_dtc_rx.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h new file mode 100644 index 000000000..8b78568b8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h @@ -0,0 +1,4 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#define bsp_lock_t 0 +#include "../smc_gen/r_dtc_rx/src/r_dtc_rx_private.h" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c new file mode 100644 index 000000000..aa7a135b1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c @@ -0,0 +1,5 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#include "../../smc_gen/r_dtc_rx/r_dtc_rx_if.h" +#include "../../smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h" +#include "../../smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/smc_workaround.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/smc_workaround.h new file mode 100644 index 000000000..13abedd52 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_IAR_e2studio_EWRX/src/smc_workaround/smc_workaround.h @@ -0,0 +1,33 @@ +#ifndef SMC_WORKAROUND_H +#define SMC_WORKAROUND_H + +#include "CC_patch.h" +#include "IDE_patch.h" +#include "CG_patch.h" +#include "FIT_patch.h" + +#if defined(__GNUC__) + +/* Just for convenience. + */ +#define brk() R_BSP_BRK() +#define int_exception(x) R_BSP_INT(x) +#define wait() R_BSP_WAIT() +#define nop() R_BSP_NOP() + +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) + +/* Just for convenience. + */ +#define setpsw_i() R_BSP_SETPSW_I() +#define clrpsw_i() R_BSP_CLRPSW_I() + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/* Just for convenience. For example, memcmp(), memcpy(), memset(), and so on. + */ +#include + +#endif /* SMC_WORKAROUND_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.cproject b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.cproject new file mode 100644 index 000000000..3530d5333 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.cproject @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.project b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.project new file mode 100644 index 000000000..3396379b4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.project @@ -0,0 +1,247 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + com.renesas.cdt.managedbuild.renesas.misrachecker.builder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS + 2 + virtual:/virtual + + + src/FreeRTOS/Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/FreeRTOS_Demo/Full_Demo/FreeRTOS-Plus-CLI + 2 + FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI + + + src/FreeRTOS_Demo/Full_Demo/Sample-CLI-commands.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c + + + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/FreeRTOS_Demo/Full_Demo/UARTCommandConsole.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c + + + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 0 + src/FreeRTOS/Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 0 + src/FreeRTOS/Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 0 + src/FreeRTOS/Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Renesas + + + + 1442773470090 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442773470090 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442773470100 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442773470100 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442773470110 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442773470110 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442773470120 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442773470120 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442773470130 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442773470130 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442773470140 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442773470140 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442773470150 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442773470150 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442773470160 + src/FreeRTOS_Demo/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 0 + src/FreeRTOS/Source/portable/Renesas + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX700v3_DPFPU + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..52d4e3fd0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,2 @@ +DependecyMode=ScanBuildDep +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/fittemp/r_sci_rx.ftl b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/fittemp/r_sci_rx.ftl new file mode 100644 index 000000000..a505f3edd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/fittemp/r_sci_rx.ftl @@ -0,0 +1,85 @@ +<#-- + Copyright(C) 2015 Renesas Electronics Corporation + RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + This program must be used solely for the purpose for which it was furnished + by Renesas Electronics Corporation. No part of this program may be reproduced + or disclosed to others, in any form, without the prior written permission of + Renesas Electronics Corporation. +--> +<#-- = DECLARE FUNCTION INFORMATION HERE =================== --> +<#-- + (Step 1) Explanation: These variables are necessary information for the function header. + Please fill up or leave blank, but do not delete +--> +<#assign Function_Base_Name = "R_SCI_PinSet"> +<#assign Function_Description = "This function initializes pins for r_sci_rx module"> +<#assign Function_Arg = "none"> +<#assign Function_Ret = "none"> +<#assign Version = 1.00> + +<#-- = DECLARE FUNCTION CONTENT HERE ======================= --> +<#-- + (Step 2) Explanation: Function content. + - Macro [initialsection] : + Any text that goes into this section will be printed out 1 time per function + input [postfix] :Use this variable to add the channel number to the function base name. +--> +<#macro initialsection postfix> +<#assign Function_Name = "${Function_Base_Name}${postfix}"> +<#include "lib/functionheader.ftl"> +void ${Function_Name}() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + +<#-- + (Step 3) Explanation: Function content. + - Macro [peripheralpincode] : Any text that goes into this section will be printed out 1 time per peripheral + - input [pin] : Available info includes: + pin.pinName :The name of pin, eg “SSLA0” + pin.assignedPinName :The pin assigned to, eg “P32” + pin.pinMPC :The port number of assigned pin, eg “P32” has portNume = “3” + pin.portNum :The bit number of the assigned pin, eg “P32” has pinBitNum = “2” + pin.pinBitNum :The value of MPC +--> +<#macro peripheralpincode pin> + + +<#-- + (Step 4) Explanation: Function content. + - Macro [channelpincode] : Any text that goes into this section will be printed out 1 time per channel + - input [pin] : Same as above +--> +<#macro channelpincode pin> + + /* Set ${pin.pinName} pin */ + MPC.${pin.assignedPinName}PFS.BYTE = 0x${pin.pinMPC}U; + PORT${pin.portNum}.PMR.BIT.B${pin.pinBitNum} = 1U; + + +<#macro channelpincodeextra pin postfix> + + +<#-- + (Step 5) Explanation: Function content. + - Macro [endsection] : Any text that goes into this section will be printed out 1 time last +--> +<#macro endsection> + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + + +<#-- + (Step 6) Explanation: Header file content + - Macro [headerfilesection] : Any text that goes into this section will be printed out 1 time in the header file + - input [postfix] :Use this variable to add the channel number to the function base name. +--> +<#macro headerfilesection postfix> +void ${Function_Base_Name}${postfix}(); + + +<#macro headerfilesectionExtra postfix> + + +<#-- = END OF FILE ========================================= --> \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/org.eclipse.cdt.core.prefs b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 000000000..0b8fbc2fb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,14 @@ +eclipse.preferences.version=1 +indexer/indexAllFiles=false +indexer/indexAllHeaderVersions=true +indexer/indexAllVersionsSpecificHeaders= +indexer/indexOnOpen=false +indexer/indexUnusedHeadersWithDefaultLang=false +indexer/indexerId=org.eclipse.cdt.core.fastIndexer +indexer/skipFilesLargerThanMB=8 +indexer/skipImplicitReferences=false +indexer/skipIncludedFilesLargerThanMB=16 +indexer/skipMacroReferences=false +indexer/skipReferences=false +indexer/skipTypeReferences=false +indexer/useHeuristicIncludeResolution=false diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/section_bkup.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/section_bkup.txt new file mode 100644 index 000000000..c57475b66 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/section_bkup.txt @@ -0,0 +1,5 @@ +B_1,R_1,B_2,R_2,B,R,B_8,R_8,SU,SI/4 +PResetPRG/FFC00000 +C_1,C_2,C,C_8,C$DSEC,C$BSEC,C$INIT,C$VTBL,C$VECT,D_1,D_2,D,D_8,P,PIntPRG,W_1,W_2,W,L/FFC00100 +EXCEPTVECT/FFFFFF80 +RESETVECT/FFFFFFFC diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/smartconfigurator/generate_skeleton.xml b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/smartconfigurator/generate_skeleton.xml new file mode 100644 index 000000000..ed82f286e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/.settings/smartconfigurator/generate_skeleton.xml @@ -0,0 +1,4 @@ + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..db20c1aa4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/RTOSDemo HardwareDebug.launch @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/RTOSDemo.mtpj b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/RTOSDemo.mtpj new file mode 100644 index 000000000..e4ca73f65 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/RTOSDemo.mtpj @@ -0,0 +1,5361 @@ + + 9.04.00.00 + + + 2.0 + 9.4 + e4273b99-1a26-4344-a4c9-23e0249a53c2 + 4383b424-c21b-4ce9-b8e1-16a5757c589c + fd4185a5-5fcd-4bc6-8caf-a515c94051dd + fb98844b-2c27-4275-9804-f6e63e204da0 + e4273b99-1a26-4344-a4c9-23e0249a53c2 + + + src + Category + fd4185a5-5fcd-4bc6-8caf-a515c94051dd + + + Smart Configurator Tips + Category + fd4185a5-5fcd-4bc6-8caf-a515c94051dd + 09a6ca83-00c4-4904-a7d0-c09333730bae + + + Smart Configurator + Category + fd4185a5-5fcd-4bc6-8caf-a515c94051dd + + + FreeRTOS + Category + 88be1680-c8f2-4a5d-80c4-8fbcf3a8fb33 + + + FreeRTOS_Demo + Category + 88be1680-c8f2-4a5d-80c4-8fbcf3a8fb33 + + + frtos_config + Category + 88be1680-c8f2-4a5d-80c4-8fbcf3a8fb33 + + + frtos_skeleton + Category + 88be1680-c8f2-4a5d-80c4-8fbcf3a8fb33 + + + frtos_startup + Category + 88be1680-c8f2-4a5d-80c4-8fbcf3a8fb33 + + + Source + Category + daa05621-30c3-4bac-b56d-420e4f898dc9 + + + include + Category + 9abf74df-121e-492c-aef7-750eb4355685 + + + portable + Category + 9abf74df-121e-492c-aef7-750eb4355685 + + + event_groups.c + File + ..\..\Source\event_groups.c + 941832c1-fc3b-4e1b-94e8-01ea17128b42 + 9abf74df-121e-492c-aef7-750eb4355685 + + + list.c + File + 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a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..4f08d0f62 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Blinky_Demo/main_blinky.c @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It sends the value 100 to the queue every 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. It blocks on the queue to wait for data to arrive from the + * queue send task - toggling the LED each time it receives the value 100. The + * queue send task writes to the queue every 200ms, so the LED should toggle + * every 200ms. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "platform.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200UL ) ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..0d900caa8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.c @@ -0,0 +1,130 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This file contains the non-portable and therefore RX specific parts of the + * IntQueue standard demo task - namely the configuration of the timers that + * generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Renesas includes. */ +#include "platform.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2000UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_2_3_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set priority and enable interrupt. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IEN( PERIB, INTB128 ) = 1; + + /* Ensure that the flag is set to 0, otherwise the interrupt will not be + accepted. */ + IR( PERIB, INTB128 ) = 0; + + /* Do the same for TMR2, but to vector 129. */ + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IEN( PERIB, INTB129 ) = 1; + IR( PERIB, INTB129 ) = 0; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +R_BSP_PRAGMA_STATIC_INTERRUPT( prvIntQTimer_0_1_ISR, VECT( PERIB, INTB128) ) +R_BSP_ATTRIB_STATIC_INTERRUPT void prvIntQTimer_0_1_ISR( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + setpsw_i(); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +R_BSP_PRAGMA_STATIC_INTERRUPT( prvIntQTimer_2_3_ISR, VECT( PERIB, INTB129) ) +R_BSP_ATTRIB_STATIC_INTERRUPT void prvIntQTimer_2_3_ISR( void ) +{ + /* Enable interrupts to allow interrupt nesting. */ + setpsw_i(); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..49c2351d8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/IntQueueTimer.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c new file mode 100644 index 000000000..05eda5290 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/main_full.c @@ -0,0 +1,847 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates a set of demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "FreeRTOS+CLI command console" - The command console uses SCI1 for its + * input and output. The baud rate is set to 19200. Type "help" to see a list + * of registered commands. The FreeRTOS+CLI license is different to the + * FreeRTOS license, see http://www.FreeRTOS.org/cli for license and usage + * details. + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks are not only still executing, + * but are executing without reporting any errors. If the check task discovers + * that a task has either stalled, or reported an error, then it changes its own + * execution period from the initial three seconds, to just 200ms. The check + * task also toggles an LED on each iteration of its loop. This provides a + * visual indication of the system status: If the LED toggles every three + * seconds, then no issues have been discovered. If the LED toggles every + * 200ms, then an issue has been discovered with at least one task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include "platform.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The period of the check task, in ms, provided no errors have been reported by +any of the standard demo tasks. ms are converted to the equivalent in ticks +using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) + +/* The period of the check task, in ms, if an error has been reported in one of +the standard demo tasks. ms are converted to the equivalent in ticks using the +portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL ); + + /* Start the tasks that implements the command console on the UART, as + described above. */ + vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); + + /* Register the standard CLI commands. */ + vRegisterSampleCLICommands(); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = pdMS_TO_TICKS( 35 ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + +#if defined(__DPFPU) + + /* Tell the kernel that this task require a DPFPU context before any DPFPU + instructions are executed. */ + portTASK_USES_DPFPU(); + +#endif /* defined(__DPFPU) */ + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + +#if defined(__DPFPU) + + /* Tell the kernel that this task require a DPFPU context before any DPFPU + instructions are executed. */ + portTASK_USES_DPFPU(); + +#endif /* defined(__DPFPU) */ + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +R_BSP_PRAGMA_STATIC_INLINE_ASM( prvRegTest1Implementation ) +void prvRegTest1Implementation( void ) +{ +R_BSP_ASM_BEGIN + + /* Put a known value in each register. */ + R_BSP_ASM( MOV.L #1, R1 ) + R_BSP_ASM( MOV.L #2, R2 ) + R_BSP_ASM( MOV.L #3, R3 ) + R_BSP_ASM( MOV.L #4, R4 ) + R_BSP_ASM( MOV.L #5, R5 ) + R_BSP_ASM( MOV.L #6, R6 ) + R_BSP_ASM( MOV.L #7, R7 ) + R_BSP_ASM( MOV.L #8, R8 ) + R_BSP_ASM( MOV.L #9, R9 ) + R_BSP_ASM( MOV.L #10, R10 ) + R_BSP_ASM( MOV.L #11, R11 ) + R_BSP_ASM( MOV.L #12, R12 ) + R_BSP_ASM( MOV.L #13, R13 ) + R_BSP_ASM( MOV.L #14, R14 ) + R_BSP_ASM( MOV.L #15, R15 ) + +#if defined(__DPFPU) + /* Put a known value in each DPFPU register. (DR0 is the same value as DR15.) */ + R_BSP_ASM( ITOD R1, DR1 ) + R_BSP_ASM( ITOD R2, DR2 ) + R_BSP_ASM( ITOD R3, DR3 ) + R_BSP_ASM( ITOD R4, DR4 ) + R_BSP_ASM( ITOD R5, DR5 ) + R_BSP_ASM( ITOD R6, DR6 ) + R_BSP_ASM( ITOD R7, DR7 ) + R_BSP_ASM( ITOD R8, DR8 ) + R_BSP_ASM( ITOD R9, DR9 ) + R_BSP_ASM( ITOD R10, DR10 ) + R_BSP_ASM( ITOD R11, DR11 ) + R_BSP_ASM( ITOD R12, DR12 ) + R_BSP_ASM( ITOD R13, DR13 ) + R_BSP_ASM( ITOD R14, DR14 ) + R_BSP_ASM( ITOD R15, DR15 ) + R_BSP_ASM( ITOD R15, DR0 ) +#endif /* defined(__DPFPU) */ + + /* Loop, checking each iteration that each register still contains the + expected value. */ +R_BSP_ASM_LAB(1:) /* TestLoop1: */ + + /* Push the registers that are going to get clobbered. */ + R_BSP_ASM( PUSHM R14-R15 ) + + /* Increment the loop counter to show this task is still getting CPU time. */ + R_BSP_ASM( MOV.L #_ulRegTest1LoopCounter, R14 ) + R_BSP_ASM( MOV.L [ R14 ], R15 ) + R_BSP_ASM( ADD #1, R15 ) + R_BSP_ASM( MOV.L R15, [ R14 ] ) + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + R_BSP_ASM( MOV.L #1, R14 ) + R_BSP_ASM( MOV.L #0872E0H, R15 ) + R_BSP_ASM( MOV.B R14, [R15] ) + R_BSP_ASM( NOP ) + R_BSP_ASM( NOP ) + + /* Restore the clobbered registers. */ + R_BSP_ASM( POPM R14-R15 ) + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + R_BSP_ASM( CMP #1, R1 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #2, R2 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #3, R3 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #4, R4 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #5, R5 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #6, R6 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #7, R7 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #8, R8 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #9, R9 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #10, R10 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #11, R11 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #12, R12 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #13, R13 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #14, R14 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( CMP #15, R15 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + +#if defined(__DPFPU) + /* Now compare each DPFPU register to ensure it still contains the value that was + set before this loop was entered. (DR0 is the same value as DR15.) */ + R_BSP_ASM( DCMPEQ DR0, DR15 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R1, DR0 ) + R_BSP_ASM( DCMPEQ DR1, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R2, DR0 ) + R_BSP_ASM( DCMPEQ DR2, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R3, DR0 ) + R_BSP_ASM( DCMPEQ DR3, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R4, DR0 ) + R_BSP_ASM( DCMPEQ DR4, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R5, DR0 ) + R_BSP_ASM( DCMPEQ DR5, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R6, DR0 ) + R_BSP_ASM( DCMPEQ DR6, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R7, DR0 ) + R_BSP_ASM( DCMPEQ DR7, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R8, DR0 ) + R_BSP_ASM( DCMPEQ DR8, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R9, DR0 ) + R_BSP_ASM( DCMPEQ DR9, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R10, DR0 ) + R_BSP_ASM( DCMPEQ DR10, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R11, DR0 ) + R_BSP_ASM( DCMPEQ DR11, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R12, DR0 ) + R_BSP_ASM( DCMPEQ DR12, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R13, DR0 ) + R_BSP_ASM( DCMPEQ DR13, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R14, DR0 ) + R_BSP_ASM( DCMPEQ DR14, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R15, DR0 ) + R_BSP_ASM( DCMPEQ DR15, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(11) ) /* BNE RegTest1Error */ +#endif /* defined(__DPFPU) */ + + /* All comparisons passed, start a new itteratio of this loop. */ + R_BSP_ASM( BRA.W R_BSP_ASM_LAB_PREV(1) ) /* BRA TestLoop1 */ + +R_BSP_ASM_LAB(11:) /* RegTest1Error: */ + /* A compare failed, just loop here so the loop counter stops incrementing + causing the check task to indicate the error. */ + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_PREV(11) ) /* BRA RegTest1Error */ + +R_BSP_ASM_END +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +R_BSP_PRAGMA_STATIC_INLINE_ASM( prvRegTest2Implementation ) +void prvRegTest2Implementation( void ) +{ +R_BSP_ASM_BEGIN + + /* Put a known value in each register. */ + R_BSP_ASM( MOV.L #10, R1 ) + R_BSP_ASM( MOV.L #20, R2 ) + R_BSP_ASM( MOV.L #30, R3 ) + R_BSP_ASM( MOV.L #40, R4 ) + R_BSP_ASM( MOV.L #50, R5 ) + R_BSP_ASM( MOV.L #60, R6 ) + R_BSP_ASM( MOV.L #70, R7 ) + R_BSP_ASM( MOV.L #80, R8 ) + R_BSP_ASM( MOV.L #90, R9 ) + R_BSP_ASM( MOV.L #100, R10 ) + R_BSP_ASM( MOV.L #110, R11 ) + R_BSP_ASM( MOV.L #120, R12 ) + R_BSP_ASM( MOV.L #130, R13 ) + R_BSP_ASM( MOV.L #140, R14 ) + R_BSP_ASM( MOV.L #150, R15 ) + +#if defined(__DPFPU) + /* Put a known value in each DPFPU register. (DR0 is the same value as DR15.) */ + R_BSP_ASM( ITOD R1, DR1 ) + R_BSP_ASM( ITOD R2, DR2 ) + R_BSP_ASM( ITOD R3, DR3 ) + R_BSP_ASM( ITOD R4, DR4 ) + R_BSP_ASM( ITOD R5, DR5 ) + R_BSP_ASM( ITOD R6, DR6 ) + R_BSP_ASM( ITOD R7, DR7 ) + R_BSP_ASM( ITOD R8, DR8 ) + R_BSP_ASM( ITOD R9, DR9 ) + R_BSP_ASM( ITOD R10, DR10 ) + R_BSP_ASM( ITOD R11, DR11 ) + R_BSP_ASM( ITOD R12, DR12 ) + R_BSP_ASM( ITOD R13, DR13 ) + R_BSP_ASM( ITOD R14, DR14 ) + R_BSP_ASM( ITOD R15, DR15 ) + R_BSP_ASM( ITOD R15, DR0 ) +#endif /* defined(__DPFPU) */ + + /* Loop, checking on each iteration that each register still contains the + expected value. */ +R_BSP_ASM_LAB(2:) /* TestLoop2: */ + + /* Push the registers that are going to get clobbered. */ + R_BSP_ASM( PUSHM R14-R15 ) + + /* Increment the loop counter to show this task is still getting CPU time. */ + R_BSP_ASM( MOV.L #_ulRegTest2LoopCounter, R14 ) + R_BSP_ASM( MOV.L [ R14 ], R15 ) + R_BSP_ASM( ADD #1, R15 ) + R_BSP_ASM( MOV.L R15, [ R14 ] ) + + /* Restore the clobbered registers. */ + R_BSP_ASM( POPM R14-R15 ) + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + R_BSP_ASM( CMP #10, R1 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #20, R2 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #30, R3 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #40, R4 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #50, R5 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #60, R6 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #70, R7 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #80, R8 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #90, R9 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #100, R10 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #110, R11 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #120, R12 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #130, R13 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #140, R14 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + R_BSP_ASM( CMP #150, R15 ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest2Error */ + +#if defined(__DPFPU) + /* Now compare each DPFPU register to ensure it still contains the value that was + set before this loop was entered. (DR0 is the same value as DR15.) */ + R_BSP_ASM( DCMPEQ DR0, DR15 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R1, DR0 ) + R_BSP_ASM( DCMPEQ DR1, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R2, DR0 ) + R_BSP_ASM( DCMPEQ DR2, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R3, DR0 ) + R_BSP_ASM( DCMPEQ DR3, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R4, DR0 ) + R_BSP_ASM( DCMPEQ DR4, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R5, DR0 ) + R_BSP_ASM( DCMPEQ DR5, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R6, DR0 ) + R_BSP_ASM( DCMPEQ DR6, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R7, DR0 ) + R_BSP_ASM( DCMPEQ DR7, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R8, DR0 ) + R_BSP_ASM( DCMPEQ DR8, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R9, DR0 ) + R_BSP_ASM( DCMPEQ DR9, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R10, DR0 ) + R_BSP_ASM( DCMPEQ DR10, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R11, DR0 ) + R_BSP_ASM( DCMPEQ DR11, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R12, DR0 ) + R_BSP_ASM( DCMPEQ DR12, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R13, DR0 ) + R_BSP_ASM( DCMPEQ DR13, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R14, DR0 ) + R_BSP_ASM( DCMPEQ DR14, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ + R_BSP_ASM( ITOD R15, DR0 ) + R_BSP_ASM( DCMPEQ DR15, DR0 ) + R_BSP_ASM( MVFDR ) + R_BSP_ASM( BNE.W R_BSP_ASM_LAB_NEXT(22) ) /* BNE RegTest1Error */ +#endif /* defined(__DPFPU) */ + + /* All comparisons passed, start a new itteratio of this loop. */ + R_BSP_ASM( BRA.W R_BSP_ASM_LAB_PREV(2) ) /* BRA TestLoop2 */ + +R_BSP_ASM_LAB(22:) /* RegTest2Error: */ + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_PREV(22) ) /* BRA RegTest2Error */ + +R_BSP_ASM_END +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c new file mode 100644 index 000000000..330530546 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/Full_Demo/serial.c @@ -0,0 +1,208 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program includes. */ +#include "serial.h" + +/* Renesas includes. */ +#include "platform.h" +#include "r_dtc_rx_if.h" +#include "r_sci_rx_if.h" +#include "r_byteq_if.h" + +/* Eval board specific definitions. */ +#include "demo_specific_io.h" + +/* Characters received from the UART are stored in this queue, ready to be +received by the application. ***NOTE*** Using a queue in this way is very +convenient, but also very inefficient. It can be used here because characters +will only arrive slowly. In a higher bandwidth system a circular RAM buffer or +DMA should be used in place of this queue. */ +static QueueHandle_t xRxQueue = NULL; + +/* When a task calls vSerialPutString() its handle is stored in xSendingTask, +before being placed into the Blocked state (so does not use any CPU time) to +wait for the transmission to end. The task handle is then used from the UART +transmit end interrupt to remove the task from the Blocked state. */ +static TaskHandle_t xSendingTask = NULL; + +/* Callback function which is called from Renesas API's interrupt service routine. */ +void vSerialSciCallback( void *pvArgs ) +{ +sci_cb_args_t *pxArgs = (sci_cb_args_t *)pvArgs; + + /* Renesas API has a built-in queue but we will ignore it. If the queue is not + full, a received character is passed with SCI_EVT_RX_CHAR event. If the queue + is full, a received character is passed with SCI_EVT_RXBUF_OVFL event. */ + if( SCI_EVT_RX_CHAR == pxArgs->event || SCI_EVT_RXBUF_OVFL == pxArgs->event ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + configASSERT( xRxQueue ); + + /* Characters received from the UART are stored in this queue, ready to be + received by the application. ***NOTE*** Using a queue in this way is very + convenient, but also very inefficient. It can be used here because + characters will only arrive slowly. In a higher bandwidth system a circular + RAM buffer or DMA should be used in place of this queue. */ + xQueueSendFromISR( xRxQueue, &pxArgs->byte, &xHigherPriorityTaskWoken ); + + /* See http://www.freertos.org/xQueueOverwriteFromISR.html for information + on the semantics of this ISR. */ + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + /* Renesas API notifies the completion of transmission by SCI_EVT_TEI event. */ + else if( SCI_EVT_TEI == pxArgs->event ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + if( xSendingTask != NULL ) + { + /* A task is waiting for the end of the Tx, unblock it now. + http://www.freertos.org/vTaskNotifyGiveFromISR.html */ + vTaskNotifyGiveFromISR( xSendingTask, &xHigherPriorityTaskWoken ); + xSendingTask = NULL; + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + } +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + ( void ) ulWantedBaud; + ( void ) uxQueueLength; + + /* Characters received from the UART are stored in this queue, ready to be + received by the application. ***NOTE*** Using a queue in this way is very + convenient, but also very inefficient. It can be used here because + characters will only arrive slowly. In a higher bandwidth system a circular + RAM buffer or DMA should be used in place of this queue. */ + xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) ); + configASSERT( xRxQueue ); + + /* Set interrupt priority. (Other UART settings had been initialized in the + src/smc_gen/general/r_cg_hardware_setup.c.) */ + uint8_t ucInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + R_SCI_Control( xSerialSciHandle, SCI_CMD_SET_RXI_PRIORITY, ( void * ) &ucInterruptPriority ); + R_SCI_Control( xSerialSciHandle, SCI_CMD_SET_TXI_PRIORITY, ( void * ) &ucInterruptPriority ); + + /* Only one UART is supported, so it doesn't matter what is returned + here. */ + return 0; +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength ) +{ +const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 5000 ); + + /* Only one port is supported. */ + ( void ) pxPort; + + /* Don't send the string unless the previous string has been sent. */ + if( ( xSendingTask == NULL ) && ( usStringLength > 0 ) ) + { + /* Ensure the calling task's notification state is not already + pending. */ + xTaskNotifyStateClear( NULL ); + + /* Store the handle of the transmitting task. This is used to unblock + the task when the transmission has completed. */ + xSendingTask = xTaskGetCurrentTaskHandle(); + + /* Send the string using the Renesas API with a workaround. */ + if( usStringLength > 1 ) + { + /* Set up Data Transfer Control. */ + dtc_cmd_arg_t xSerialTxDtcArg; + dtc_transfer_data_cfg_t xSerialTxDtcConfig; + + xSerialTxDtcArg.act_src = U_DTC_UART_CLI_TX_ACT; + xSerialTxDtcConfig.transfer_mode = DTC_TRANSFER_MODE_NORMAL; + xSerialTxDtcConfig.data_size = DTC_DATA_SIZE_BYTE; + xSerialTxDtcConfig.src_addr_mode = DTC_SRC_ADDR_INCR; + xSerialTxDtcConfig.dest_addr_mode = DTC_DES_ADDR_FIXED; + xSerialTxDtcConfig.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + xSerialTxDtcConfig.repeat_block_side = DTC_REPEAT_BLOCK_SOURCE; + xSerialTxDtcConfig.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + xSerialTxDtcConfig.chain_transfer_mode = (dtc_chain_transfer_mode_t)0; + xSerialTxDtcConfig.source_addr = ( uint32_t ) pcString; + xSerialTxDtcConfig.dest_addr = ( uint32_t ) &U_DTC_UART_CLI_TX_DR; + xSerialTxDtcConfig.transfer_count = ( uint32_t ) usStringLength - 1; + xSerialTxDtcArg.chain_transfer_nr = 0; + xSerialTxDtcArg.p_transfer_data = &xSerialTxDtcInfo; + xSerialTxDtcArg.p_data_cfg = &xSerialTxDtcConfig; + + R_DTC_Create( xSerialTxDtcArg.act_src, &xSerialTxDtcInfo, &xSerialTxDtcConfig, 0 ); + R_DTC_Control( DTC_CMD_ACT_SRC_ENABLE, NULL, &xSerialTxDtcArg ); + R_SCI_Send( xSerialSciHandle, ( uint8_t * ) (pcString + usStringLength - 1), 1 ); + } + else + { + R_SCI_Send( xSerialSciHandle, ( uint8_t * ) pcString, 1 ); + } + + /* Wait in the Blocked state (so not using any CPU time) until the + transmission has completed. */ + ulTaskNotifyTake( pdTRUE, xMaxBlockTime ); + + /* A breakpoint can be set here for debugging. */ + nop(); + } +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime ) +{ + /* Only one UART is supported. */ + ( void ) pxPort; + + /* Return a received character, if any are available. Otherwise block to + wait for a character. */ + return xQueueReceive( xRxQueue, pcRxedChar, xBlockTime ); +} + +/* Function required in order to link UARTCommandConsole.c - which is used by +multiple different demo application. */ +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime ) +{ + /* Just mapped to vSerialPutString() so the block time is not used. */ + ( void ) xBlockTime; + + vSerialPutString( pxPort, &cOutChar, sizeof( cOutChar ) ); + return pdPASS; +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_main.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_main.h new file mode 100644 index 000000000..caa38e9d4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_main.h @@ -0,0 +1,13 @@ +#ifndef DEMO_MAIN_H +#define DEMO_MAIN_H + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/* demo_main() is placed in the src/frtos_startup/freertos_start.c and it calls +main_blinky() or main_full() according to the mainCREATE_SIMPLE_BLINKY_DEMO_ONLY +setting. */ +extern void demo_main( void ); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h new file mode 100644 index 000000000..f3a19fa11 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/FreeRTOS_Demo/demo_specific_io.h @@ -0,0 +1,78 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef LED_IO_H +#define LED_IO_H + + #define EnvisionRX72N + +/* Board support settings. */ + + #ifdef EnvisionRX72N + + /* R5F572NDHDFB 144pin LQFP */ + + /* General Values */ + #define LED_ON (0) + #define LED_OFF (1) + #define SW_PUSH (0) + #define SW_RELEASE (1) + + /* Switches (and its notation in the User's Manual) */ + #define SW1/*(SW2)*/ (PORT0.PIDR.BIT.B7) + #define U_GPIO_PIN_SW1/*(SW2)*/ (GPIO_PORT_0_PIN_7) + + /* LED port settings (and its notation in the User's Manual) */ + #define LED0/*(LED2)*/ (PORT4.PODR.BIT.B0) + #define U_GPIO_PIN_LED0/*(LED2)*/ (GPIO_PORT_4_PIN_0) + + /* FreeRTOS CLI Command Console */ + #define U_SCI_UART_CLI_PINSET() R_SCI_PinSet_SCI2() + #define U_SCI_UART_CLI_SCI_CH (SCI_CH2) + #define U_DTC_UART_CLI_TX_ACT ((dtc_activation_source_t)VECT(SCI2,TXI2)) + #define U_DTC_UART_CLI_TX_DR (SCI2.TDR) + + #endif /* EnvisionRX72N */ + + #ifndef LED0 + #error The hardware platform is not defined + #endif + +/* Board Support Data Structures. */ + +#include "r_sci_rx_if.h" +#include "r_dtc_rx_if.h" + +extern sci_hdl_t xSerialSciHandle; +extern dtc_transfer_data_t xSerialTxDtcInfo; + +/* Board Support Callback Functions. */ + +extern void vSerialSciCallback( void *pvArgs ); + +#endif /* LED_IO_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h new file mode 100644 index 000000000..0b8a0ea27 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_config/FreeRTOSConfig.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ (BSP_ICLK_HZ) +#define configPERIPHERAL_CLOCK_HZ (BSP_PCLKB_HZ) +#define configTICK_RATE_HZ (( TickType_t ) 1000) +#define configMINIMAL_STACK_SIZE (( unsigned short ) 170) +#define configTOTAL_HEAP_SIZE_N (60) +#define configTOTAL_HEAP_SIZE (( size_t ) ( configTOTAL_HEAP_SIZE_N * 1024 )) +#define configMAX_TASK_NAME_LEN (12) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES (7) +#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_TASK_NOTIFICATIONS 1 +#define configRECORD_STACK_HIGH_ADDRESS 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + +/* Dynamic allocation and static allocation. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 0 + +/* Run time stats gathering definitions. */ +unsigned long ulGetRunTimeCounterValue( void ); +void vConfigureTimerForRunTimeStats( void ); +#define configGENERATE_RUN_TIME_STATS 0 +//#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() +//#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (6) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will +be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before +making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then +tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has +no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care +of any DPFPU context (even if DPFPU registers are used). */ +#define configUSE_TASK_DPFPU_SUPPORT 1 + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() + +/* The buffer into which output generated by FreeRTOS+CLI is placed. This must +be at least big enough to contain the output of the task-stats command, as the +example implementation does not include buffer overlow checking. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 3500 +#define configINCLUDE_QUERY_HEAP_COMMAND 1 + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY (( configMAX_PRIORITIES - 3 )) +#define bktSECONDARY_PRIORITY (( configMAX_PRIORITIES - 4 )) +#define intqHIGHER_PRIORITY (( configMAX_PRIORITIES - 3 )) + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be used. */ +#define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_skeleton/task_function.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_skeleton/task_function.h new file mode 100644 index 000000000..c25944146 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_skeleton/task_function.h @@ -0,0 +1,23 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef TASK_FUNCTION_H_ +#define TASK_FUNCTION_H_ + +#endif /* TASK_FUNCTION_H_ */ \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_object_init.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_object_init.c new file mode 100644 index 000000000..829831d0f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_object_init.c @@ -0,0 +1,80 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name : freertos_object_init.c + * Version : 1.0 + * Description : + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 07.12.2018 1.00 First Release + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "FreeRTOS.h" +#include "freertos_start.h" +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Kernel_Object_init (void); +void Object_init_manual (void); +/*********************************************************************************************************************** + * Function Name: Kernel_Object_init + * Description : This function initializes FreeRTOS objects. + * Arguments : None. + * Return Value : None. + **********************************************************************************************************************/ +void Kernel_Object_init (void) +{ + /************** task creation ****************************/ + + /************** semaphore creation ***********************/ + + /************** queue creation ***************************/ + + /************** software time creation **************************/ + + /************** event groups creation ********************/ + + /************** stream buffer creation *************************/ + + /************** message buffer creation *********************/ + +} /* End of function Kernel_Object_init()*/ + +/*********************************************************************************************************************** + * Function Name : Object_init_manual + * Description : This function re-initializes FreeRTOS objects and should be called at runtime. + * Arguments : None. + * Return value : None. + **********************************************************************************************************************/ +void Object_init_manual (void) +{ + /************** task creation ****************************/ +} /* End of function Object_init_manual()*/ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_start.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_start.c new file mode 100644 index 000000000..25a9af682 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_start.c @@ -0,0 +1,483 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : freertos_start.c +* Version : 1.0 +* Description : Contains FreeRTOS user-defined functions. +******************************************************************************/ +/***************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2016 1.00 First Release +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" +#include "freertos_start.h" +#include "demo_main.h" +#include "demo_specific_io.h" + +#if (BSP_CFG_RTOS_USED == 1) + +#if (RTOS_USB_SUPPORT == 1) +#include "r_usb_basic_if.h" +#include "r_usb_cstd_rtos.h" +#endif + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/************* semaphore initialization *****************/ + +/****************************************************************************** +Exported global variables (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ + +/* FreeRTOS's system timer. */ +void vApplicationSetupTimerInterrupt(void); + +/* Hook functions used by FreeRTOS. */ +void vAssertCalled(void); +void vApplicationIdleHook(void); +void vApplicationTickHook(void); +void vApplicationMallocFailedHook(void); +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName); + +/* FreeRTOS's processing before start the kernel. */ +void Processing_Before_Start_Kernel(void); + +/* Main task. */ +extern void main_task(void *pvParameters); + + +/****************************************************************************** +* Function Name: vApplicationSetupTimerInterrupt +* Description : Initialize system timer for FreeRTOS with tick interrupt 1ms. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationSetupTimerInterrupt(void) +{ + /* CMT channel 0 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 0) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Stop counter. */ + CMT.CMSTR0.BIT.STR0 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT0.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT0, CMI0) = 0; + + /* Enable the interrupt. */ + IEN(CMT0, CMI0) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 0. */ + CMT.CMSTR0.BIT.STR0 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 0) */ + + /* CMT channel 1 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 1) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 1. */ + MSTP( CMT1 ) = 0; + + /* Stop counter. */ + CMT.CMSTR0.BIT.STR1 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT1.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT1.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT1.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT1, CMI1) = 0; + + /* Enable the interrupt. */ + IEN(CMT1, CMI1) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT1, CMI1) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 1. */ + CMT.CMSTR0.BIT.STR1 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 1) */ + + /* CMT channel 2 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 2) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 2. */ + MSTP( CMT2 ) = 0; + + /* Stop counter. */ + CMT.CMSTR1.BIT.STR2 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT2.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT2.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT2, CMI2) = 0; + + /* Enable the interrupt. */ + IEN(CMT2, CMI2) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT2, CMI2) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 2. */ + CMT.CMSTR1.BIT.STR2 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 2) */ + + /* CMT channel 3 is configured as RTOS's system timer. */ +#if (BSP_CFG_RTOS_SYSTEM_TIMER == 3) + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Enable compare match timer 3. */ + MSTP( CMT3 ) = 0; + + /* Stop counter. */ + CMT.CMSTR1.BIT.STR3 = 0; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + /* Enable interrupt on compare match. + * Divide the PCLK by 8. */ + CMT3.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @60MHz + + /* Set the compare match value. */ + CMT3.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); + + /* Clear counter. */ + CMT3.CMCNT = 0; + + /* Clear any previously pending interrupts. */ + IR(CMT3, CMI3) = 0; + + /* Enable the interrupt. */ + IEN(CMT3, CMI3) = 1; + + /* Set its priority to the application defined kernel priority. */ + IPR(CMT3, CMI3) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer 3. */ + CMT.CMSTR1.BIT.STR3 = 1; +#endif /* (BSP_CFG_RTOS_SYSTEM_TIMER == 3) */ + +} /* End of function vApplicationSetupTimerInterrupt() */ + +/****************************************************************************** +* Function Name: vAssertCalled +* Description : This function is used to validate the input parameters. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vAssertCalled(void) +{ + volatile unsigned long ul = 0; + + taskENTER_CRITICAL(); + { + /* Use the debugger to set ul to a non-zero value in order to step out + of this function to determine why it was called. */ + while( 0 == ul ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); + +} /* End of function vAssertCalled() */ + +/****************************************************************************** +* Function Name: vApplicationIdleHook +* Description : This function will be called on each cycle of the idle task. +* NOTE: vApplicationIdleHook() MUST NOT CALL A FUNCTION +* THAT MIGHT BLOCK UNDER ANY CIRCUMSTANCES. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationIdleHook(void) +{ + volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; + +} /* End of function vApplicationIdleHook() */ + +/****************************************************************************** +* Function Name: vApplicationTickHook +* Description : This function will be called every tick interrupt. +* NOTE: vApplicationTickHook() EXECUTES FROM WITHIN AN ISR, +* SO MUST BE VERY SHORT AND NOT USE MUCH STACK. +* IN ADDITION, NOT CALL ANY APIs WITHOUT "FromISR" OR +* "FROM_ISR" AT THE END. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationTickHook(void) +{ + /* The tick hook is not used by the blinky demo, but is by the full demo. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif + +} /* End of function vApplicationTickHook() */ + +/****************************************************************************** +* Function Name: vApplicationMallocFailedHook +* Description : This function is to capture the failure while +* memory allocation. +* Arguments : None. +* Return Value : None. +******************************************************************************/ +void vApplicationMallocFailedHook(void) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); + + taskDISABLE_INTERRUPTS(); + for( ; ; ) + { + /* Loop here */ + }; + +} /* End of function vApplicationMallocFailedHook() */ + +/****************************************************************************** +* Function Name: vApplicationStackOverflowHook +* Description : Hook function is to capture the failure when the stack size +* is insufficient for processing. +* Arguments : pxTask - +* Task handler +* pcTaskName - +* Pointer of where to store the task's name +* Return Value : None. +******************************************************************************/ +void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); + + taskDISABLE_INTERRUPTS(); + for( ; ; ) + { + /* Loop here */ + }; + +} /* End of function vApplicationStackOverflowHook() */ + +/****************************************************************************** +* Function Name : Processing_Before_Start_Kernel +* Description : Create a main task, FreeRTOS's objects (e.g. mailbox, task, +* semaphore, mutex...) if required. +* Arguments : None. +* Return value : None. +******************************************************************************/ +void Processing_Before_Start_Kernel(void) +{ +#if 0 /* Generated Renesas Code */ + + BaseType_t ret; + + /************** semaphore creation ***********************/ + + + + /************** mutex creation ***************************/ + + + /************** queues creation **************************/ + + + /************** event groups creation ********************/ + + + /************** mailbox creation *************************/ + + + /************** memory pool creation *********************/ + + /** USB RTOS Configuration **/ +#if (RTOS_USB_SUPPORT == 1) + usb_rtos_err_t err = usb_rtos_configuration(); + if (UsbRtos_Success != err) + { + while(1) + { + /** Failure of UsbRtos Configuration **/ + } + } +#endif + + Kernel_Object_init(); + + /************** task creation ****************************/ + /* Main task. */ + ret = xTaskCreate(main_task, "MAIN_TASK", 512, NULL, 3, NULL); + if (pdPASS != ret) + { + while(1) + { + /* Failed! Task can not be created. */ + } + } + +#else /* Run FreeRTOS Demo */ + + demo_main(); + +#endif + +} /* End of function Processing_Before_Start_Kernel() */ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +void demo_main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + /* Should never get reached. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Turn on LED0 at start. (The system initialization had been done in the + src/smc_gen/general/r_cg_hardware_setup.c.) */ + LED0 = LED_ON; +} +/*-----------------------------------------------------------*/ + +#endif /* (BSP_CFG_RTOS_USED == 1) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_start.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_start.h new file mode 100644 index 000000000..f91a1efb7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/frtos_startup/freertos_start.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : freertos_start.h +* Version : 1.0 +* Description : FreeRTOS's user-defined functions header file. +******************************************************************************/ +/***************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2016 1.00 First Release +******************************************************************************/ + +#ifndef FREERTOS_START_H_ +#define FREERTOS_START_H_ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* USB FIT module support macro */ +#define RTOS_USB_SUPPORT 0 + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Exported global variables +******************************************************************************/ +/************* semaphore handler *****************/ + + + +/************* mutex handler *********************/ + + +/************** queues handler *******************/ + + +/************** event groups handler *************/ + + +/************** mailbox handler ******************/ + + +/************** memory pool handler **************/ + + +/************** task handler *********************/ + + +/****************************************************************************** +Exported global functions (to be accessed by other files) +******************************************************************************/ +extern void Processing_Before_Start_Kernel(void); +extern void Kernel_Object_init(void); + +#endif /* FREERTOS_START_H_ */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_hardware_setup.c new file mode 100644 index 000000000..757e3fe38 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_hardware_setup.c @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : Initialization file for code generation configurations. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_cgc.h" +#include "r_smc_interrupt.h" +/* Start user code for include. Do not edit comment generated here */ +#include "r_gpio_rx_if.h" +#include "r_sci_rx_pinset.h" +#include "r_sci_rx_if.h" +#include "r_dtc_rx_if.h" +#include "demo_specific_io.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +/* Board Support Data Structures. */ +sci_hdl_t xSerialSciHandle; +dtc_transfer_data_t xSerialTxDtcInfo; + +/* Workaround to execute FIT Board Support Settings */ +void R_CG_Config_Create(void); +void R_FIT_Board_Support_Settings(void); +void R_Systeminit(void) +{ + R_CG_Config_Create(); + R_FIT_Board_Support_Settings(); +} +#define R_Systeminit R_CG_Config_Create + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_undefined_exception +* Description : This function is undefined interrupt service routine +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void r_undefined_exception(void) +{ + /* Start user code for r_undefined_exception. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every configuration +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50BU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Write 0 to the target bits in the POECR2 registers */ + POE3.POECR2.WORD = 0x0000U; + + /* Initialize clocks settings */ + R_CGC_Create(); + + /* Register undefined interrupt */ + R_BSP_InterruptWrite(BSP_INT_SRC_UNDEFINED_INTERRUPT,(bsp_int_cb_t)r_undefined_exception); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} + +/* Start user code for adding. Do not edit comment generated here */ + +void R_FIT_Board_Support_Settings(void) +{ + /* Do not call any functions which enables generating any interrupt requests. */ + + /* GPIO for LED */ + R_GPIO_PinWrite(U_GPIO_PIN_LED0, (gpio_level_t)LED_OFF); // for the initial level after input --> output + R_GPIO_PinDirectionSet(U_GPIO_PIN_LED0, GPIO_DIRECTION_OUTPUT); + + /* GPIO for SW */ + R_GPIO_PinDirectionSet(U_GPIO_PIN_SW1, GPIO_DIRECTION_INPUT ); + + /* FreeRTOS CLI Command Console */ + U_SCI_UART_CLI_PINSET(); + sci_cfg_t xSerialSciConfig; + xSerialSciConfig.async.baud_rate = 115200; + xSerialSciConfig.async.clk_src = SCI_CLK_INT; + xSerialSciConfig.async.data_size = SCI_DATA_8BIT; + xSerialSciConfig.async.parity_en = SCI_PARITY_OFF; + xSerialSciConfig.async.parity_type = SCI_EVEN_PARITY; + xSerialSciConfig.async.stop_bits = SCI_STOPBITS_1; + xSerialSciConfig.async.int_priority = 1; /* lowest at first. */ + R_SCI_Open(U_SCI_UART_CLI_SCI_CH, SCI_MODE_ASYNC, &xSerialSciConfig, vSerialSciCallback, &xSerialSciHandle); + R_DTC_Open(); + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); +} + +/* End user code. Do not edit comment generated here */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_macrodriver.h new file mode 100644 index 000000000..230f817dc --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_macrodriver.h @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : Macro header file for code generation. +***********************************************************************************************************************/ + +#ifndef MACRODRIVER_H +#define MACRODRIVER_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "platform.h" +#include "r_smc_interrupt.h" +#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Systeminit(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_userdefine.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_userdefine.h new file mode 100644 index 000000000..660ad8706 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_cg_userdefine.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : User header file for code generation. +***********************************************************************************************************************/ + +#ifndef CG_USER_DEF_H +#define CG_USER_DEF_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* Start user code for register. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Start user code for macro define. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Start user code for type define. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc.c new file mode 100644 index 000000000..1c0709116 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc.c @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc.c +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : This file implements CGC setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_CGC_Create(void) +{ + /* Set CLKOUT25M pin */ + MPC.P56PFS.BYTE = 0x2AU; + PORT5.DSCR2.BYTE |= 0x40U; + PORT5.PMR.BYTE |= 0x40U; + + R_CGC_Create_UserInit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc.h new file mode 100644 index 000000000..0a594c2a8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc.h @@ -0,0 +1,174 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc.h +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : CGC setting header file. +***********************************************************************************************************************/ + +#ifndef SMC_CGC_H +#define SMC_CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PLL Clock Source Select (PLLSRCSEL) */ +#define _0000_CGC_PLL_SOURCE_MAIN (0x0000U) /* Main clock oscillator */ +#define _0010_CGC_PLL_SOURCE_HOCO (0x0010U) /* HOCO */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_16 (0x00U) /* 16 MHz */ +#define _01_CGC_HOCO_CLK_18 (0x01U) /* 18 MHz */ +#define _02_CGC_HOCO_CLK_20 (0x02U) /* 20 MHz */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Clock Oscillator Forced Oscillation (MOFXIN) */ +#define _00_CGC_MAINOSC_NOT_CONTROLLED (0x00U) /* Oscillator is not controlled by this bit */ +#define _01_CGC_MAINOSC_FORCE_OSCILLATED (0x01U) /* The main clock oscillator is forcedly oscillated */ +/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */ +#define _00_CGC_MAINOSC_UNDER24M (0x00U) /* 20.1 to 24 MHz */ +#define _10_CGC_MAINOSC_UNDER20M (0x10U) /* 16.1 to 20 MHz */ +#define _20_CGC_MAINOSC_UNDER16M (0x20U) /* 8.1 to 16 MHz */ +#define _30_CGC_MAINOSC_EQUATE8M (0x30U) /* 8 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + PPLL Control Register (PPLLCR) +*/ +/* PPLL Input Pulse Frequency Division Ratio Select (PPLIDIV[1:0]) */ +#define _0000_CGC_PPLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PPLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PPLL_FREQ_DIV_3 (0x0002U) /* x1/3 */ +/* PPLL Frequency Multiplier Setting (PPLSTC[5:0]) */ +#define _1300_CGC_PPLL_FREQ_MUL_10_0 (0x1300U) /* x10.0 */ +#define _1400_CGC_PPLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PPLL_FREQ_MUL_11_0 (0x1500U) /* x11.0 */ +#define _1600_CGC_PPLL_FREQ_MUL_11_5 (0x1600U) /* x11.5 */ +#define _1700_CGC_PPLL_FREQ_MUL_12_0 (0x1700U) /* x12.0 */ +#define _1800_CGC_PPLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PPLL_FREQ_MUL_13_0 (0x1900U) /* x13.0 */ +#define _1A00_CGC_PPLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +#define _1B00_CGC_PPLL_FREQ_MUL_14_0 (0x1B00U) /* x14.0 */ +#define _1C00_CGC_PPLL_FREQ_MUL_14_5 (0x1C00U) /* x14.5 */ +#define _1D00_CGC_PPLL_FREQ_MUL_15_0 (0x1D00U) /* x15.0 */ +#define _1E00_CGC_PPLL_FREQ_MUL_15_5 (0x1E00U) /* x15.5 */ +#define _1F00_CGC_PPLL_FREQ_MUL_16_0 (0x1F00U) /* x16.0 */ +#define _2000_CGC_PPLL_FREQ_MUL_16_5 (0x2000U) /* x16.5 */ +#define _2100_CGC_PPLL_FREQ_MUL_17_0 (0x2100U) /* x17.0 */ +#define _2200_CGC_PPLL_FREQ_MUL_17_5 (0x2200U) /* x17.5 */ +#define _2300_CGC_PPLL_FREQ_MUL_18_0 (0x2300U) /* x18.0 */ +#define _2400_CGC_PPLL_FREQ_MUL_18_5 (0x2400U) /* x18.5 */ +#define _2500_CGC_PPLL_FREQ_MUL_19_0 (0x2500U) /* x19.0 */ +#define _2600_CGC_PPLL_FREQ_MUL_19_5 (0x2600U) /* x19.5 */ +#define _2700_CGC_PPLL_FREQ_MUL_20_0 (0x2700U) /* x20.0 */ +#define _2800_CGC_PPLL_FREQ_MUL_20_5 (0x2800U) /* x20.5 */ +#define _2900_CGC_PPLL_FREQ_MUL_21_0 (0x2900U) /* x21.0 */ +#define _2A00_CGC_PPLL_FREQ_MUL_21_5 (0x2A00U) /* x21.5 */ +#define _2B00_CGC_PPLL_FREQ_MUL_22_0 (0x2B00U) /* x22.0 */ +#define _2C00_CGC_PPLL_FREQ_MUL_22_5 (0x2C00U) /* x22.5 */ +#define _2D00_CGC_PPLL_FREQ_MUL_23_0 (0x2D00U) /* x23.0 */ +#define _2E00_CGC_PPLL_FREQ_MUL_23_5 (0x2E00U) /* x23.5 */ +#define _2F00_CGC_PPLL_FREQ_MUL_24_0 (0x2F00U) /* x24.0 */ +#define _3000_CGC_PPLL_FREQ_MUL_24_5 (0x3000U) /* x24.5 */ +#define _3100_CGC_PPLL_FREQ_MUL_25_0 (0x3100U) /* x25.0 */ +#define _3200_CGC_PPLL_FREQ_MUL_25_5 (0x3200U) /* x25.5 */ +#define _3300_CGC_PPLL_FREQ_MUL_26_0 (0x3300U) /* x26.0 */ +#define _3400_CGC_PPLL_FREQ_MUL_26_5 (0x3400U) /* x26.5 */ +#define _3500_CGC_PPLL_FREQ_MUL_27_0 (0x3500U) /* x27.0 */ +#define _3600_CGC_PPLL_FREQ_MUL_27_5 (0x3600U) /* x27.5 */ +#define _3700_CGC_PPLL_FREQ_MUL_28_0 (0x3700U) /* x28.0 */ +#define _3800_CGC_PPLL_FREQ_MUL_28_5 (0x3800U) /* x28.5 */ +#define _3900_CGC_PPLL_FREQ_MUL_29_0 (0x3900U) /* x29.0 */ +#define _3A00_CGC_PPLL_FREQ_MUL_29_5 (0x3A00U) /* x29.5 */ +#define _3B00_CGC_PPLL_FREQ_MUL_30_0 (0x3B00U) /* x30.0 */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); +void R_CGC_Create_UserInit(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc_user.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc_user.c new file mode 100644 index 000000000..e4d862c1e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_cgc_user.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_cgc_user.c +* Version : 1.6.101 +* Device(s) : R5F572NNHxFB +* Description : This file implements CGC setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create_UserInit +* Description : This function adds user code after initializing CGC +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_CGC_Create_UserInit(void) +{ + /* Start user code for user init. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_entry.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_entry.h new file mode 100644 index 000000000..e91c0784e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_entry.h @@ -0,0 +1,53 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_entry.h +* Version : 1.0.101 +* Device(s) : R5F572NNHxFB +* Description : SMC platform header file. +***********************************************************************************************************************/ + +#ifndef SMC_ENTRY_H +#define SMC_ENTRY_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_interrupt.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_interrupt.c new file mode 100644 index 000000000..b1695cab5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_interrupt.c @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_interrupt.c +* Version : 1.1.0 +* Device(s) : R5F572NNHxFB +* Description : This file implements interrupt setting. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_smc_interrupt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Interrupt_Create +* Description : This function Used to set the fast interrupt or group interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Interrupt_Create(void) +{ + /* No fast interrupt and group settings have been configured in the Interrupts tab. */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_interrupt.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_interrupt.h new file mode 100644 index 000000000..07913ebcc --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/general/r_smc_interrupt.h @@ -0,0 +1,295 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_smc_interrupt.h +* Version : 1.1.0 +* Device(s) : R5F572NNHxFB +* Description : This file implements interrupt setting. +***********************************************************************************************************************/ + +#ifndef SMC_INTERRUPT_H +#define SMC_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* Priority level of interrupt source. + * These macro definitions are used to set the IPR register directly + */ +#define _00_ICU_PRIORITY_LEVEL0 (0x00U) /* Level 0 (disabled) */ +#define _01_ICU_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_ICU_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_ICU_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_ICU_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_ICU_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_ICU_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_ICU_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_ICU_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_ICU_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_ICU_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */ +#define _0B_ICU_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */ +#define _0C_ICU_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */ +#define _0D_ICU_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */ +#define _0E_ICU_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */ +#define _0F_ICU_PRIORITY_LEVEL15 (0x0FU) /* Level 15 */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR (0) + +/* The macro definitions below list the full set of priority levels as selected in the Interrupts tab + * Please do not modify this file manually + */ +#define ICU_BSC_BUSERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPIE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RAM_RAMERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_FCU_FIFERR_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_FCU_FRDYI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_SWINT2_PRIORITY (_01_ICU_PRIORITY_LEVEL1) +#define ICU_ICU_SWINT_PRIORITY (_01_ICU_PRIORITY_LEVEL1) +#define ICU_CMT0_CMI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT1_CMI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_CMWI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_CMWI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_D0FIFO0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_D1FIFO0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI0_SPRI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI0_SPTI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI1_SPRI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI1_SPTI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_QSPI_SPRI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_QSPI_SPTI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SDHI_SBFAI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MMCIF_MBFAI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE0_SSITXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE0_SSIRXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SSIE1_SSIRTI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC1_RXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC1_TXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC0_RXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC0_TXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC2_RXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RIIC2_TXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI0_RXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI0_TXI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI1_RXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI1_TXI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI2_RXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI2_TXI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ13_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ14_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_IRQ15_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI3_RXI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI3_TXI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI4_RXI4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI4_TXI4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI5_RXI5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI5_TXI5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI6_RXI6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI6_TXI6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_LVD1_LVD1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_LVD2_LVD2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_USBR0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_ALM_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_PRD_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_IWDT_IWUNI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_WDT_WUNI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PDC_PCDFI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI7_RXI7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI7_TXI7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI8_RXI8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI8_TXI8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI9_RXI9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI9_TXI9_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI10_RXI10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI10_TXI10_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI2_SPRI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RSPI2_SPTI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPBL1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPAL0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ICU_GROUPAL1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI11_RXI11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI11_TXI11_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI12_RXI12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_SCI12_TXI12_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC2I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC3I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_DMAC_DMAC74I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_OST_OSTDI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EXDMAC_EXDMAC0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EXDMAC_EXDMAC1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT2_CMI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMT3_CMI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0C_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TGI0D_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU0_TCI0V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TGI1B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TCI1V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TCI1U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TGI2A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TGI2B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TCI2V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU2_TCI2U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU1_TGI1A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3C_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_CMIA0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_CMIB0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR0_OVI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_CMIA1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_CMIB1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR1_OVI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_CMIA2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_CMIB2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR2_OVI2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_CMIA3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_CMIB3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TMR3_OVI3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TGI3D_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU3_TCI3V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TGI4A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TGI4B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TCI4V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU4_TCI4U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TGI5A_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TGI5B_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TCI5V_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TPU5_TCI5U_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_IC0I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_IC1I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_OC0I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW0_OC1I0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_IC0I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_IC1I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_OC0I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CMTW1_OC1I1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_RTC_CUP_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_RXF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_TXF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_RXM0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN0_TXM0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_RXF1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_TXF1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_RXM1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_CAN1_TXM1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_USB0_USBI0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12ADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12GBADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD_S12GCADI_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12ADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12GBADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_S12AD1_S12GCADI1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ELC_ELSR18I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_ELC_ELSR19I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_PROC_BUSY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_ROMOK_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_LONG_PLG_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_TEST_BUSY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_WRRDY4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_RDRDY0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_RDRDY1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_INTEGRATE_WRRDY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_TSIP_INTEGRATE_RDRDY_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB205_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB206_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIB_INTB207_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TGIA1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIA0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIB0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIC0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGID0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TCIV0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIE0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU0_TGIF0_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TGIB1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TCIV1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU1_TCIU1_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TGIA2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TGIB2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TCIV2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU2_TCIU2_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIA3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIB3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGIC3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TGID3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU3_TCIV3_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIA4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIB4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGIC4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TGID4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU4_TCIV4_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIU5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIV5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU5_TGIW5_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIA6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIB6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGIC6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TGID6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU6_TCIV6_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIA7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIB7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGIC7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TGID7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU7_TCIV7_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIA8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIB8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGIC8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TGID8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_MTU8_TCIV8_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_EPTPC_IPLS_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PMGI0_PMGI0I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PMGI1_PMGI1I_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIA_INTA254_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) +#define ICU_PERIA_INTA255_PRIORITY (_0F_ICU_PRIORITY_LEVEL15) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Interrupt_Create(void); +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c new file mode 100644 index 000000000..0620d7fe2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.c @@ -0,0 +1,414 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.c +* Device(s) : RX +* H/W Platform : GENERIC_RX72N +* Description : Defines the initialization routines used each time the MCU is restarted. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* I/O Register and board definitions */ +#include "platform.h" +#if BSP_CFG_CONFIGURATOR_SELECT == 1 +#include "r_cg_macrodriver.h" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +R_BSP_PRAGMA_UNPACK +typedef struct bsp_bsc { + union { + uint32_t u_long; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13( + uint32_t prerr:1, + uint32_t :1, + uint32_t rpstop:1, + uint32_t :10, + uint32_t pr5sel:3, + uint32_t :1, + uint32_t pr4sel:3, + uint32_t :1, + uint32_t pr3sel:3, + uint32_t :1, + uint32_t pr2sel:3, + uint32_t :1, + uint32_t pr1sel:3 + ) bit; + } ebmapcr; +} st_bsp_bsc_t; +R_BSP_PRAGMA_PACKOPTION + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +/* ROM cache configuration function declaration */ +#if BSP_CFG_ROM_CACHE_ENABLE == 1 +static void rom_cache_function_set(void); +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 +static void rom_cache_noncacheable_area0_set(void); +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 +static void rom_cache_noncacheable_area1_set(void); +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/* MCU I/O port configuration function declaration */ +static void output_ports_configure(void); + +/* Interrupt configuration function declaration */ +static void interrupts_configure(void); + +/* MCU peripheral module configuration function declaration */ +static void peripheral_modules_enable(void); + +/* ADC initial configuration function declaration */ +static void bsp_adc_initial_configure(void); + +/* BUS initial configuration function declaration */ +static void bsp_bsc_initial_configure(void); + +/*********************************************************************************************************************** +* Function name: hardware_setup +* Description : Contains setup functions called at device restart +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void hardware_setup(void) +{ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +#if BSP_CFG_ROM_CACHE_ENABLE == 1 + /* Initialize ROM cache function */ + rom_cache_function_set(); +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + + output_ports_configure(); + interrupts_configure(); + peripheral_modules_enable(); + bsp_non_existent_port_init(); + bsp_adc_initial_configure(); + bsp_bsc_initial_configure(); +} /* End of function hardware_setup() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +#if BSP_CFG_ROM_CACHE_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_function_set +* Description : Configures the rom cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_function_set (void) +{ +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 + rom_cache_noncacheable_area0_set(); +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ + +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 + rom_cache_noncacheable_area1_set(); +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ + + /* Invalidates the contents of the ROM cache. */ + FLASH.ROMCIV.WORD = 0x0001; + + /* Enables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0001; +} /* End of function rom_cache_function_set() */ + +#if BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_noncacheable_area0_set +* Description : Configures non-cacheable area 0 of the ROM cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_noncacheable_area0_set (void) +{ + /* Used to specify the value written to the NCRC0 register. */ + uint32_t tmp_ncrc = 0; + + /* Disables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0000; + + /* Makes settings to the NCRG0 register. */ +#if (BSP_CFG_NONCACHEABLE_AREA0_ADDR >= 0xFFC00000) \ + && ((BSP_CFG_NONCACHEABLE_AREA0_ADDR & 0x0000000F) == 0x00000000) + FLASH.NCRG0 = BSP_CFG_NONCACHEABLE_AREA0_ADDR; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA0_ADDR in r_bsp_config.h" +#endif + + /* Sets the value of the NCSZ bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x0 + /* Do nothing since NCRC0 bits should be 0. */ +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x1 + tmp_ncrc |= 0x00000010; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x2 + tmp_ncrc |= 0x00000030; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x3 + tmp_ncrc |= 0x00000070; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x4 + tmp_ncrc |= 0x000000F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x5 + tmp_ncrc |= 0x000001F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x6 + tmp_ncrc |= 0x000003F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x7 + tmp_ncrc |= 0x000007F0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x8 + tmp_ncrc |= 0x00000FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x9 + tmp_ncrc |= 0x00001FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xA + tmp_ncrc |= 0x00003FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xB + tmp_ncrc |= 0x00007FF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xC + tmp_ncrc |= 0x0000FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xD + tmp_ncrc |= 0x0001FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xE + tmp_ncrc |= 0x0003FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0xF + tmp_ncrc |= 0x0007FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x10 + tmp_ncrc |= 0x000FFFF0; +#elif BSP_CFG_NONCACHEABLE_AREA0_SIZE == 0x11 + tmp_ncrc |= 0x001FFFF0; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA0_SIZE in r_bsp_config.h" +#endif + + /* Sets the value of the NC1E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE == 1 + tmp_ncrc |= 0x00000002; +#endif + + /* Sets the value of the NC2E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE == 1 + tmp_ncrc |= 0x00000004; +#endif + + /* Sets the value of the NC3E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE == 1 + tmp_ncrc |= 0x00000008; +#endif + + /* Makes settings to the NCRC0 register. */ + FLASH.NCRC0.LONG = tmp_ncrc; +} /* End of function rom_cache_noncacheable_area0_set() */ +#endif /* BSP_CFG_NONCACHEABLE_AREA0_ENABLE == 1 */ + +#if BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 +/*********************************************************************************************************************** +* Function name: rom_cache_noncacheable_area1_set +* Description : Configures non-cacheable area 1 of the ROM cache function. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void rom_cache_noncacheable_area1_set (void) +{ + /* Used to specify the value written to the NCRC1 register. */ + uint32_t tmp_ncrc = 0; + + /* Disables the ROM cache. */ + FLASH.ROMCE.WORD = 0x0000; + + /* Makes settings to the NCRG1 register. */ +#if (BSP_CFG_NONCACHEABLE_AREA1_ADDR >= 0xFFC00000) \ + && ((BSP_CFG_NONCACHEABLE_AREA1_ADDR & 0x0000000F) == 0x00000000) + FLASH.NCRG1 = BSP_CFG_NONCACHEABLE_AREA1_ADDR; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA1_ADDR in r_bsp_config.h" +#endif + + /* Sets the value of the NCSZ bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x0 + /* Do nothing since NCRC1 bits should be 0. */ +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x1 + tmp_ncrc |= 0x00000010; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x2 + tmp_ncrc |= 0x00000030; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x3 + tmp_ncrc |= 0x00000070; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x4 + tmp_ncrc |= 0x000000F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x5 + tmp_ncrc |= 0x000001F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x6 + tmp_ncrc |= 0x000003F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x7 + tmp_ncrc |= 0x000007F0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x8 + tmp_ncrc |= 0x00000FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x9 + tmp_ncrc |= 0x00001FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xA + tmp_ncrc |= 0x00003FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xB + tmp_ncrc |= 0x00007FF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xC + tmp_ncrc |= 0x0000FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xD + tmp_ncrc |= 0x0001FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xE + tmp_ncrc |= 0x0003FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0xF + tmp_ncrc |= 0x0007FFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x10 + tmp_ncrc |= 0x000FFFF0; +#elif BSP_CFG_NONCACHEABLE_AREA1_SIZE == 0x11 + tmp_ncrc |= 0x001FFFF0; +#else + #error "Error! Invalid setting for BSP_CFG_NONCACHEABLE_AREA1_SIZE in r_bsp_config.h" +#endif + + /* Sets the value of the NC1E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE == 1 + tmp_ncrc |= 0x00000002; +#endif + + /* Sets the value of the NC2E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE == 1 + tmp_ncrc |= 0x00000004; +#endif + + /* Sets the value of the NC3E bits. */ +#if BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE == 1 + tmp_ncrc |= 0x00000008; +#endif + + /* Makes settings to the NCRC1 register. */ + FLASH.NCRC1.LONG = tmp_ncrc; +} /* End of function rom_cache_noncacheable_area1_set() */ +#endif /* BSP_CFG_NONCACHEABLE_AREA1_ENABLE == 1 */ +#endif /* BSP_CFG_ROM_CACHE_ENABLE == 1 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function name: output_ports_configure +* Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void output_ports_configure(void) +{ + /* Add code here to setup additional output ports */ + R_BSP_NOP(); +} /* End of function output_ports_configure() */ + +/*********************************************************************************************************************** +* Function name: interrupts_configure +* Description : Configures interrupts used +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void interrupts_configure(void) +{ + /* Add code here to setup additional interrupts */ + R_BSP_NOP(); +} /* End of function interrupts_configure() */ + +/*********************************************************************************************************************** +* Function name: peripheral_modules_enable +* Description : Enables and configures peripheral devices on the MCU +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void peripheral_modules_enable(void) +{ + /* Add code here to enable peripherals used by the application */ +#if BSP_CFG_CONFIGURATOR_SELECT == 1 + /* Smart Configurator initialization function */ + R_Systeminit(); +#endif +} /* End of function peripheral_modules_enable() */ + +/*********************************************************************************************************************** +* Function name: bsp_adc_initial_configure +* Description : Configures the ADC initial settings +* Arguments : none +* Return value : none +* Note : This function should be called when the PSW.I bit is 0 (interrupt disabled). +* This function should be called when the ADCSR.ADST bit is 0. +***********************************************************************************************************************/ +static void bsp_adc_initial_configure(void) +{ + uint32_t tmp_mstp; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Store the value of the MSTPCR. */ + tmp_mstp = MSTP(S12AD1); + + /* Release from the module-stop state */ + MSTP(S12AD1) = 0; + + /* Writing to the A/D conversion time setting register is enabled. */ + S12AD1.ADSAMPR.BYTE = 0x03; + + /* Sets conversion time for middle-speed for S12AD unit 1. */ + S12AD1.ADSAM.WORD = 0x0020; + + /* Writing to the A/D conversion time setting register is disabled. */ + S12AD1.ADSAMPR.BYTE = 0x02; + + /* Restore the value of the MSTPCR. */ + MSTP(S12AD1) = tmp_mstp; + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_adc_initial_configure() */ + +/*********************************************************************************************************************** +* Function name: bsp_bsc_initial_configure +* Description : Configures the BUS initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_bsc_initial_configure(void) +{ + st_bsp_bsc_t bsp_bsc; + + /* Setting priority when bus right request contention occurs. */ + bsp_bsc.ebmapcr.u_long = BSC.EBMAPCR.LONG; + bsp_bsc.ebmapcr.bit.pr1sel = BSP_CFG_EBMAPCR_1ST_PRIORITY; + bsp_bsc.ebmapcr.bit.pr2sel = BSP_CFG_EBMAPCR_2ND_PRIORITY; + bsp_bsc.ebmapcr.bit.pr3sel = BSP_CFG_EBMAPCR_3RD_PRIORITY; + bsp_bsc.ebmapcr.bit.pr4sel = BSP_CFG_EBMAPCR_4TH_PRIORITY; + bsp_bsc.ebmapcr.bit.pr5sel = BSP_CFG_EBMAPCR_5TH_PRIORITY; + + /* Set to EBMAPCR register */ + BSC.EBMAPCR.LONG = bsp_bsc.ebmapcr.u_long; +} /* End of function bsp_bsc_initial_configure() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h new file mode 100644 index 000000000..6c25e0f30 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/hwsetup.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : hwsetup.h +* Description : Hardware setup header file. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef HWSETUP_H +#define HWSETUP_H + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void hardware_setup(void); //r_bsp internal function. DO NOT CALL. + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h new file mode 100644 index 000000000..28180a97e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* H/W Platform : GENERIC_RX72N +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +#include "mcu/all/r_bsp_common.h" +#include "r_bsp_config.h" +#include "mcu/all/r_rx_compiler.h" + +#include "r_bsp_interrupt_config.h" + +#include "mcu/all/lowlvl.h" +#include "mcu/all/lowsrc.h" +#include "mcu/all/r_bsp_mcu_startup.h" + +#if defined(__CCRX__) +#include "mcu/rx72n/register_access/ccrx/iodefine.h" +#elif defined(__GNUC__) +#include "mcu/rx72n/register_access/gnuc/iodefine.h" +#elif defined(__ICCRX__) +#include "mcu/rx72n/register_access/iccrx/iodefine.h" +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "mcu/rx72n/r_bsp_cpu.h" +#include "mcu/rx72n/r_bsp_locking.h" +#include "mcu/rx72n/mcu_clocks.h" +#include "mcu/rx72n/mcu_info.h" +#include "mcu/rx72n/mcu_init.h" +#include "mcu/rx72n/mcu_interrupts.h" +#include "mcu/rx72n/mcu_locks.h" +#include "mcu/rx72n/mcu_mapped_interrupts_private.h" +#include "mcu/rx72n/mcu_mapped_interrupts.h" +#include "mcu/rx72n/vecttbl.h" + +#include "board/generic_rx72n/hwsetup.h" + +#include "mcu/all/r_bsp_interrupts.h" +#include "mcu/all/r_bsp_software_interrupt.h" +#include "mcu/all/r_rx_intrinsic_functions.h" +#include "mcu/all/r_rtos.h" + +#ifdef __cplusplus +} +#endif + +#ifndef BSP_BOARD_GENERIC_RX72N +#define BSP_BOARD_GENERIC_RX72N + +#endif /* BSP_BOARD_GENERIC_RX72N */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h new file mode 100644 index 000000000..be9268128 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_config_reference.h @@ -0,0 +1,766 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX72N +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release. +***********************************************************************************************************************/ +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX72N. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 57 2N N D D BD + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FC = 0x0 = LFQFP/176/0.50 + BG = 0x1 = LFBGA/176/0.80 + BD = 0x2 = LFBGA/224/0.80 + FB = 0x3 = LFQFP/144/0.50 + LK = 0x4 = TFLGA/145/0.50 + FP = 0x5 = LFQFP/100/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x2) + +/* Whether Encryption is included or not. + Character(s) = Value for macro = Description + D = 0xD = Encryption module not included + H = 0x11 = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0xD) + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + D = 0xD = 2MB/1MB/32KB + N = 0x17 = 4MB/1MB/32KB +NOTE: The RAM areas are not contiguous.It is separated by 512 KB each. +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x17) + +/* Group name. + Character(s) = Value for macro = Description + 2N = 0x0 = RX72N Group +*/ +#define BSP_CFG_MCU_PART_GROUP (0x0) + +/* Series name. + Character(s) = Value for macro = Description + 57 = 0x0 = RX700 Series +*/ +#define BSP_CFG_MCU_PART_SERIES (0x0) + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (1) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x1000) +#endif + +/* Interrupt Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x400) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit (default) +*/ +#define BSP_CFG_CLOCK_SOURCE (4) + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator (default) + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (0) + +/* USB Clock source select (UPLLSEL). Choose which clock source to input to the USB circuit. + 0 = System Clock (PLL Circuit/No division) (This is not available.) + 1 = USB PLL Circuit (This is not available.) + 2 = PLL Circuit (UDIVCLK) (default) + 3 = PPLL Circuit (PPLLDIVCLK) +*/ +#define BSP_CFG_USB_CLOCK_SOURCE (2) + +/* Ethernet-PHY clock source (OUTCKSEL). Choose which clock source to input to the Ethernet PHY LSI. + Available clock sources: + 0 = PLL circuit + 1 = PPLL circuit (default) + 2 = Ethernet-PHY not use +*/ +#define BSP_CFG_PHY_CLOCK_SOURCE (1) + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 6 = PPLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE (2) + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE (0) + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP (0) + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, BCLK is 80MHz, + USB Clock is 48MHz, ESC Clock is 100MHz, Ether-Phy Clock is 25MHz then the settings would be: + + BSP_CFG_XTAL_HZ = 24000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz) + BSP_CFG_PPLL_DIV = 3 (divide by 3) + BSP_CFG_PPLL_MUL = 25.0 (8MHz x 25.0 = 200MHz) + BSP_CFG_PPLCK_DIV = 2 (divide by 2) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 240MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_BCK_DIV = 3 : External Bus Clock (BCK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 80MHz + BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (24000000) + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#define BSP_CFG_HOCO_FREQUENCY (0) + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC (0) + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (1) + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL (10.0) + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (1) + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (2) + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (4) + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (4) + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (4) + +/* External Bus Clock Divider (BCLK). + Available divisors = /1 (no division), /2, /3, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_BCK_DIV (3) + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (4) + +/* USB Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_UCK_DIV (5) + +/* PPLL Input Frequency Division Ratio Select (PPLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PPLL_DIV (3) + +/* PPLL Frequency Multiplication Factor Select (PPLSTC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PPLL_MUL (25.0) + +/* PPLL Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_PPLCK_DIV (2) + +/* Configure BCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency +*/ +#define BSP_CFG_BCLK_OUTPUT (0) + +/* Configure SDCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency + NOTE: The definition is invalid. +*/ +#define BSP_CFG_SDCLK_OUTPUT (0) + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV (0) + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT (0) + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) + +/* Sub-Clock Oscillator Wait Time (SOSCWTCR). + The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation + by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384 + (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h). +*/ +#define BSP_CFG_SOSC_WAIT_TIME (0x21) + +/* ROM Cache Enable Register (ROMCE). + 0 = ROM cache operation disabled. + 1 = ROM cache operation enabled. +*/ +#define BSP_CFG_ROM_CACHE_ENABLE (1) + +/* Configure non-cacheable area 0 of the ROM cache function. + 0 = Non-cacheable area 0 settings disabled. + 1 = Non-cacheable area 0 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ENABLE (0) + +/* Specifies the start address of non-cacheable area 0. + Selects the start address of non-cacheable area 0. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 0. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of IF cache disabled. + 1 = Non-cacheable area 0 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of OA cache disabled. + 1 = Non-cacheable area 0 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of DM cache disabled. + 1 = Non-cacheable area 0 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE (1) + +/* Configure non-cacheable area 1 of the ROM cache function. + 0 = Non-cacheable area 1 settings disabled. + 1 = Non-cacheable area 1 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ENABLE (0) + +/* Specifies the start address of non-cacheable area 1. + Selects the start address of non-cacheable area 1. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 1. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of IF cache disabled. + 1 = Non-cacheable area 1 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of OA cache disabled. + 1 = Non-cacheable area 1 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of DM cache disabled. + 1 = Non-cacheable area 1 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE (1) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 78 and 79 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEFF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b26] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area + - 1: FFFF E000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory + when the flash programmer is used during off-board programming. + ROMCODE - ROM Code Protection Register + b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1). + 0000 0001h: ROM code protection enabled (ROM code protection 2). + Other than above: ROM code protection disabled. + Note: The ROMCODE register should be set in 32-bit units. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. +*/ +#define BSP_CFG_RTOS_USED (0) + +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC + graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and + display list data read). + The default priority order in bsp is below + GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC. + Priority can be changed with this macro. + + Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */ +#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */ +#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */ +#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */ +#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */ + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (0) + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (1) +#define BSP_CFG_SWINT_UNIT2_ENABLE (1) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h new file mode 100644 index 000000000..697280fd6 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/generic_rx72n/r_bsp_interrupt_config_reference.h @@ -0,0 +1,222 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupt_config.h +* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ +#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE +#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you + * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you + * would do the following: + * + * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 + */ + +/* Interrupt B Sources. + * -Valid vector numbers are 128-207. + * -There are more vector slots for B sources than actual B sources. By default none of the CAN2 interrupts are + * mapped. + * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default. + * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be + * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0' + * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots. + */ +#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128 +#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175 +#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 192 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 193 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 194 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 195 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 196 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 197 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 198 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 199 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 200 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 201 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 202 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 203 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 204 + +/* Interrupt A Sources. + * -Valid vector numbers are 208-255. + * -There are more A sources than A vector slots. By default none of the GPTW interrupts and the ESC interrupts are + * mapped. + * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default. + */ +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3 +#define BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS 251 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I 252 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I 253 + +#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/user/r_bsp.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/user/r_bsp.h new file mode 100644 index 000000000..94ecab164 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/board/user/r_bsp.h @@ -0,0 +1,54 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 13.01.2012 1.00 First Release +* : 27.06.2012 1.10 Updated with new information to reflect udpated r_bsp structure. +***********************************************************************************************************************/ + +#ifndef BSP_BOARD_USER +#define BSP_BOARD_USER + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +/* This is a user defined board. Start off by: + 1)Copy and rename one of the 'board' folders that most closely matches your system (same MCU Series and Group). + 2)Substitute in your MCU Group for the *MCU Group* option in the #include below for mcu_info.h. + 3)Copy the other #includes from the r_bsp.h in the 'board' folder that you copied earlier. + 4)Configure the BSP for your board by modifying the r_bsp_config_reference.h. + 5)Copy r_bsp_config_reference.h to your project directory and rename it r_bsp_config.h. + You can also add your own include files here as well. */ +#include "r_bsp_config.h" +#include "mcu/*MCU Group*/mcu_info.h" + +#endif /* BSP_BOARD_USER */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/dbsct.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/dbsct.c new file mode 100644 index 000000000..9f71dec6c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/dbsct.c @@ -0,0 +1,133 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : dbsct.c +* Description : Defines the structure of the ROM and RAM areas. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Added definition for section of D_8, B_8, and C_8. +* : 08.10.2019 3.01 Added section for Renesas RTOS (RI600V4 or RI600PX). +* : 14.02.2020 3.02 Corrected pragma declaration of unpack. +***********************************************************************************************************************/ + +#if defined(__CCRX__) +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/* Preprocessor directive */ +#pragma unpack + +/* MCU ROM and RAM structure definition */ +typedef struct +{ + uint8_t *rom_s; /* Start address of the initialized data section in ROM */ + uint8_t *rom_e; /* End address of the initialized data section in ROM */ + uint8_t *ram_s; /* Start address of the initialized data section in RAM */ +} st_dtbl_t; + +typedef struct +{ + uint8_t *b_s; /* Start address of non-initialized data section */ + uint8_t *b_e; /* End address of non-initialized data section */ +} st_btbl_t; + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/* Section start */ +#pragma section C C$DSEC + +extern st_dtbl_t const _DTBL[] = { +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + { __sectop("D_8"), __secend("D_8"), __sectop("R_8") }, +#endif + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX) + ,{ __sectop("DRI_ROM"), __secend("DRI_ROM"), __sectop("RRI_RAM") } +#endif /* Renesas RI600PX */ +}; + +/* Section start */ +#pragma section C C$BSEC + +extern st_btbl_t const _BTBL[] = { +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + { __sectop("B_8"), __secend("B_8") }, +#endif + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4) + ,{ __sectop("BRI_RAM"), __secend("BRI_RAM") } +#endif /* Renesas RI600V4 */ +}; + +/* Section start */ +#pragma section + +#if (BSP_CFG_RTOS_USED == 4) && (BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX) +#pragma section C CS +#endif /* Renesas RI600PX */ + +/* CTBL prevents excessive output of L1100 messages when linking. + Even if CTBL is deleted, the operation of the program does not change. */ +uint8_t * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + __sectop("C_8"), +#endif + __sectop("W_1"), __sectop("W_2"), __sectop("W") +}; + +/* Preprocessor directive */ +#pragma packoption + +/* This is to ensure compatibility with new L section in version 1.1 and up of the RXC compiler. Do not remove! */ +#pragma section C L +const uint32_t deadSpace = 0xDEADDEAD; +#pragma section + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +#endif /* defined(__CCRX__) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowlvl.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowlvl.c new file mode 100644 index 000000000..b17b9c02b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowlvl.c @@ -0,0 +1,126 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowlvl.c +* Description : Functions to support stream I/O to the E1 virtual Console +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_E1_DBG_PORT (*(volatile st_dbg_t R_BSP_EVENACCESS_SFR *)0x84080) +#define BSP_PRV_TXFL0EN (0x00000100) /* debug tx flow control bit */ +#define BSP_PRV_RXFL0EN (0x00001000) /* debug RX flow control bit */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef struct +{ + uint32_t tx_data; /* Debug Virtual Console TX data */ + char wk1[12]; /* spacer */ + uint32_t rx_data; /* Debug Virtual Console RX data */ + char wk2[44]; /* spacer */ + uint32_t dbgstat; /* Debug Virtual Console Status */ +} st_dbg_t; + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +#if BSP_CFG_USER_CHARPUT_ENABLED != 0 +/* If user has indicated they want to provide their own charput function then this is the prototype. */ +void BSP_CFG_USER_CHARPUT_FUNCTION(char output_char); +#endif + +#if BSP_CFG_USER_CHARGET_ENABLED != 0 +/* If user has indicated they want to provide their own charget function then this is the prototype. */ +char BSP_CFG_USER_CHARGET_FUNCTION(void); +#endif + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: charput +* Description : Outputs a character on a serial port +* Arguments : character to output +* Return Value : none +***********************************************************************************************************************/ +void charput (char output_char) +{ + /* If user has provided their own charput() function, then call it. */ +#if BSP_CFG_USER_CHARPUT_ENABLED == 1 + BSP_CFG_USER_CHARPUT_FUNCTION(output_char); +#else + /* Wait for transmit buffer to be empty */ + /* WAIT_LOOP */ + while(0 != (BSP_PRV_E1_DBG_PORT.dbgstat & BSP_PRV_TXFL0EN)) + { + /* do nothing */ + R_BSP_NOP(); + } + + /* Write the character out */ + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_E1_DBG_PORT.tx_data = (int32_t)output_char; +#endif +} /* End of function charput() */ + +/*********************************************************************************************************************** +* Function Name: charget +* Description : Gets a character on a serial port +* Arguments : none +* Return Value : received character +***********************************************************************************************************************/ +char charget (void) +{ + /* If user has provided their own charget() function, then call it. */ +#if BSP_CFG_USER_CHARGET_ENABLED == 1 + return BSP_CFG_USER_CHARGET_FUNCTION(); +#else + /* Wait for rx buffer buffer to be ready */ + /* WAIT_LOOP */ + while(0 == (BSP_PRV_E1_DBG_PORT.dbgstat & BSP_PRV_RXFL0EN)) + { + /* do nothing */ + R_BSP_NOP(); + } + + /* Read data, send back up */ + /* Casting is valid because it matches the type to the retern value. */ + return (char)BSP_PRV_E1_DBG_PORT.rx_data; +#endif +} /* End of function charget() */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowlvl.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowlvl.h new file mode 100644 index 000000000..9ca8db79d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowlvl.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowlvl.h +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef LOWLVL_H +#define LOWLVL_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/* Output one character to standard output (the E1 Virtual Console or a serial port via user own charput function) */ +void charput (char output_char); + +/* Input one character from standard input (the E1 Virtual Console or a serial port via user own charget function) */ +char charget (void); + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowsrc.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowsrc.c new file mode 100644 index 000000000..36078db9c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowsrc.c @@ -0,0 +1,571 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowsrc.c +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) +#include +#include +#endif /* defined(__CCRX__) */ +#include "r_bsp_common.h" +#include "r_bsp_config.h" +#include "lowlvl.h" +#include "lowsrc.h" + + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/* Do not include this file if stdio is disabled in r_bsp_config. */ +#if BSP_CFG_IO_LIB_ENABLE == 1 + +#if defined(__CCRX__) + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/*Number of I/O Stream*/ +#define BSP_PRV_IOSTREAM (20) + +/* file number */ +#define BSP_PRV_STDIN (0) /* Standard input (console) */ +#define BSP_PRV_STDOUT (1) /* Standard output (console) */ +#define BSP_PRV_STDERR (2) /* Standard error output (console) */ + +#define BSP_PRV_FLMIN (0) /* Minimum file number */ +#define BSP_PRV_MOPENR (0x1) +#define BSP_PRV_MOPENW (0x2) +#define BSP_PRV_MOPENA (0x4) +#define BSP_PRV_MTRUNC (0x8) +#define BSP_PRV_MCREAT (0x10) +#define BSP_PRV_MBIN (0x20) +#define BSP_PRV_MEXCL (0x40) +#define BSP_PRV_MALBUF (0x40) +#define BSP_PRV_MALFIL (0x80) +#define BSP_PRV_MEOF (0x100) +#define BSP_PRV_MERR (0x200) +#define BSP_PRV_MLBF (0x400) +#define BSP_PRV_MNBF (0x800) +#define BSP_PRV_MREAD (0x1000) +#define BSP_PRV_MWRITE (0x2000) +#define BSP_PRV_MBYTE (0x4000) +#define BSP_PRV_MWIDE (0x8000) +/* File Flags */ +#define BSP_PRV_O_RDONLY (0x0001) /* Read only */ +#define BSP_PRV_O_WRONLY (0x0002) /* Write only */ +#define BSP_PRV_O_RDWR (0x0004) /* Both read and Write */ +#define BSP_PRV_O_CREAT (0x0008) /* A file is created if it is not existed */ +#define BSP_PRV_O_TRUNC (0x0010) /* The file size is changed to 0 if it is existed. */ +#define BSP_PRV_O_APPEND (0x0020) /* The position is set for next reading/writing + 0: Top of the file 1: End of file */ + +/* Special character code */ +#define BSP_PRV_CR (0x0d) /* Carriage return */ +#define BSP_PRV_LF (0x0a) /* Line feed */ + +#define BSP_PRV_FPATH_STDIN "C:\\stdin" +#define BSP_PRV_FPATH_STDOUT "C:\\stdout" +#define BSP_PRV_FPATH_STDERR "C:\\stderr" + +#ifdef _REENTRANT +// For Reentrant Library (generated lbgrx with -reent option) +#define BSP_PRV_MALLOC_SEM (1) /* Semaphore No. for malloc */ +#define BSP_PRV_STRTOK_SEM (2) /* Semaphore No. for strtok */ +#define BSP_PRV_FILE_TBL_SEM (3) /* Semaphore No. for fopen */ +#define BSP_PRV_MBRLEN_SEM (4) /* Semaphore No. for mbrlen */ +#define BSP_PRV_FPSWREG_SEM (5) /* Semaphore No. for FPSW register */ +#define BSP_PRV_FILES_SEM (6) /* Semaphore No. for _Files */ +#define BSP_PRV_SEMSIZE (26) /* BSP_PRV_FILES_SEM + _nfiles (assumed _nfiles=20) */ + +#define BSP_PRV_TRUE (1) +#define BSP_PRV_FALSE (0) +#define BSP_PRV_OK (1) +#define BSP_PRV_NG (0) +#endif /* _REENTRANT */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern const long _nfiles; /* The number of files for input/output files */ +char flmod[BSP_PRV_IOSTREAM]; /* The location for the mode of opened file. */ + +unsigned char sml_buf[BSP_PRV_IOSTREAM]; + +FILE *_Files[BSP_PRV_IOSTREAM]; /* structure for FILE */ +char *env_list[] = { /* Array for environment variables(**environ) */ + "ENV1=temp01", + "ENV2=temp02", + "ENV9=end", + '\0' /* Terminal for environment variables */ +}; + +char **environ = env_list; + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +#ifdef _REENTRANT +static long sem_errno; +static int force_fail_signal_sem = BSP_PRV_FALSE; +static int semaphore[BSP_PRV_SEMSIZE]; +#endif /* _REENTRANT */ + +/*********************************************************************************************************************** +* Function Name: init_iolib +* Description : Initialize C library Functions, if necessary. Define USES_SIMIO on Assembler Option. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void init_iolib(void) +{ + /* A file for standard input/output is opened or created. Each FILE + * structure members are initialized by the library. Each _Buf member + * in it is re-set the end of buffer pointer. + */ + + /* Initializations of File Stream Table */ + _Files[0] = stdin; + _Files[1] = stdout; + _Files[2] = stderr; + + /* Standard Input File */ + if( freopen( BSP_PRV_FPATH_STDIN, "r", stdin ) == NULL ) + { + stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */ + } + stdin->_Mode = BSP_PRV_MOPENR; /* Read only attribute */ + stdin->_Mode |= BSP_PRV_MNBF; /* Non-buffering for data */ + stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */ + + /* Standard Output File */ + if( freopen( BSP_PRV_FPATH_STDOUT, "w", stdout ) == NULL ) + { + stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */ + } + stdout->_Mode |= BSP_PRV_MNBF; /* Non-buffering for data */ + stdout->_Bend = stdout->_Buf + 1; /* Re-set pointer to the end of buffer */ + + /* Standard Error File */ + if( freopen( BSP_PRV_FPATH_STDERR, "w", stderr ) == NULL ) + { + stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */ + } + stderr->_Mode |= BSP_PRV_MNBF; /* Non-buffering for data */ + stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */ +} /* End of function init_iolib() */ + +/*********************************************************************************************************************** +* Function Name: close_all +* Description : Colses the file +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void close_all(void) +{ + long i; + + /* WAIT_LOOP */ + for( i=0; i < _nfiles; i++ ) + { + /* Checks if the file is opened or not */ + if( _Files[i]->_Mode & (BSP_PRV_MOPENR | BSP_PRV_MOPENW | BSP_PRV_MOPENA ) ) + { + fclose( _Files[i] ); /* Closes the file */ + } + } +} /* End of function close_all() */ + +/*********************************************************************************************************************** +* Function Name: open +* Description : file open +* Arguments : name - File name +* mode - Open mode +* flg - Open flag +* Return Value : File number (Pass) +* -1 (Failure) +***********************************************************************************************************************/ +long open(const char *name, long mode, long flg) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(flg); + + if( 0 == strcmp( name, BSP_PRV_FPATH_STDIN ) ) /* Standard Input file? */ + { + if( 0 == ( mode & BSP_PRV_O_RDONLY ) ) + { + return -1; + } + flmod[BSP_PRV_STDIN] = mode; + return BSP_PRV_STDIN; + } + else if( 0 == strcmp( name, BSP_PRV_FPATH_STDOUT ) ) /* Standard Output file? */ + { + if( 0 == ( mode & BSP_PRV_O_WRONLY ) ) + { + return -1; + } + flmod[BSP_PRV_STDOUT] = mode; + return BSP_PRV_STDOUT; + } + else if( 0 == strcmp(name, BSP_PRV_FPATH_STDERR ) ) /* Standard Error file? */ + { + if( 0 == ( mode & BSP_PRV_O_WRONLY ) ) + { + return -1; + } + flmod[BSP_PRV_STDERR] = mode; + return BSP_PRV_STDERR; + } + else + { + return -1; /*Others */ + } +} /* End of function open() */ + +/*********************************************************************************************************************** +* Function Name: close +* Description : dummy +* Arguments : fileno - File number +* Return Value : 1 +***********************************************************************************************************************/ +long close(long fileno) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + return 1; +} /* End of function close() */ + +/*********************************************************************************************************************** +* Function Name: write +* Description : Data write +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to write +* Return Value : Number of write characters (Pass) +* -1 (Failure) +***********************************************************************************************************************/ +long write(long fileno, const unsigned char *buf, long count) +{ + long i; /* A variable for counter */ + unsigned char c; /* An output character */ + + /* Checking the mode of file , output each character + * Checking the attribute for Write-Only, Read-Only or Read-Write + */ + if((flmod[fileno]&BSP_PRV_O_WRONLY) || (flmod[fileno]&BSP_PRV_O_RDWR)) + { + if( BSP_PRV_STDIN == fileno ) + { + return -1; /* Standard Input */ + } + else if( (BSP_PRV_STDOUT == fileno) || (BSP_PRV_STDERR == fileno) ) /* Standard Error/output */ + { + /* WAIT_LOOP */ + for( i = count; i > 0; --i ) + { + c = *buf++; + charput(c); + } + return count; /*Return the number of written characters */ + } + else + { + return -1; /* Incorrect file number */ + } + } + else + { + return -1; /* An error */ + } +} /* End of function write() */ + +/*********************************************************************************************************************** +* Function Name: read +* Description : Data read +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to read +* Return Value : Number of read characters (Pass) +* -1 (Failure) +***********************************************************************************************************************/ +long read(long fileno, unsigned char *buf, long count) +{ + long i; + + /* Checking the file mode with the file number, each character is input and stored the buffer */ + + if((flmod[fileno]&BSP_PRV_MOPENR) || (flmod[fileno]&BSP_PRV_O_RDWR)) + { + /* WAIT_LOOP */ + for(i = count; i > 0; i--) + { + *buf = charget(); + if(BSP_PRV_CR == (*buf)) + { + *buf = BSP_PRV_LF; /* Replace the new line character */ + } + buf++; + } + return count; + } + else + { + return -1; + } +} /* End of function read() */ + +/*********************************************************************************************************************** +* Function Name: lseek +* Description : dummy +* Arguments : fileno - File number +* offset - Offset indicating reading / writing position +* base - Offset starting point +* Return Value : -1L +***********************************************************************************************************************/ +long lseek(long fileno, long offset, long base) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(offset); + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(base); + + return -1L; +} /* End of function lseek() */ + +#ifdef _REENTRANT +/*********************************************************************************************************************** +* Function Name: errno_addr +* Description : Acquisition of errno address +* Arguments : none +* Return Value : errno address +***********************************************************************************************************************/ +long *errno_addr(void) +{ + /* Return the errno address of the current task */ + return (&sem_errno); +} + +/*********************************************************************************************************************** +* Function Name: wait_sem +* Description : Defines the specified numbers of semaphores +* Arguments : semnum - Semaphore ID +* Return Value : BSP_PRV_OK(=1) (Normal) +* BSP_PRV_NG(=0) (Error) +***********************************************************************************************************************/ +long wait_sem(long semnum) /* Semaphore ID */ +{ + if((0 < semnum) && (semnum < BSP_PRV_SEMSIZE)) { + if(semaphore[semnum] == BSP_PRV_FALSE) { + semaphore[semnum] = BSP_PRV_TRUE; + return(BSP_PRV_OK); + } + } + return(BSP_PRV_NG); +} + +/*********************************************************************************************************************** +* Function Name: signal_sem +* Description : Releases the specified numbers of semaphores +* Arguments : semnum - Semaphore ID +* Return Value : BSP_PRV_OK(=1) (Normal) +* BSP_PRV_NG(=0) (Error) +***********************************************************************************************************************/ +long signal_sem(long semnum) /* Semaphore ID */ +{ + if(!force_fail_signal_sem) { + if((0 <= semnum) && (semnum < BSP_PRV_SEMSIZE)) { + if( semaphore[semnum] == BSP_PRV_TRUE ) { + semaphore[semnum] = BSP_PRV_FALSE; + return(BSP_PRV_OK); + } + } + } + return(BSP_PRV_NG); +} +#endif /* _REENTRANT */ + +#endif /* defined(__CCRX__) */ + +#endif /* BSP_CFG_IO_LIB_ENABLE */ + +#if defined(__GNUC__) +/*********************************************************************************************************************** +* Function Name: write +* Description : Data write (for GNURX+NEWLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to write +* Return Value : Number of write characters (Pass) +***********************************************************************************************************************/ +int write(int fileno, char *buf, int count) +{ + int i; + char c; + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + /* WAIT_LOOP */ + for(i = count; i > 0; --i) + { + c = *buf++; + charput(c); + } + + return count; +} + +/*********************************************************************************************************************** +* Function Name: read +* Description : Data read (for GNURX+NEWLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to read +* Return Value : 1 (Pass) +***********************************************************************************************************************/ +int read(int fileno, char *buf, int count) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + INTERNAL_NOT_USED(count); + + *buf = charget(); + return 1; +} + +/*********************************************************************************************************************** +* Function Name: _write +* Description : Data write (for GNURX+OPTLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to write +* Return Value : Number of write characters (Pass) +***********************************************************************************************************************/ +int _write(int fileno, char *buf, int count) +{ + int i; + char c; + + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + + /* WAIT_LOOP */ + for(i = count; i > 0; --i) + { + c = *buf++; + charput(c); + } + + return count; +} + +/*********************************************************************************************************************** +* Function Name: read +* Description : Data read (for GNURX+OPTLIB) +* Arguments : fileno - File number +* buf - The address of destination buffer +* count - The number of chacter to read +* Return Value : 1 (Pass) +***********************************************************************************************************************/ +int _read(int fileno, char *buf, int count) +{ + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(fileno); + INTERNAL_NOT_USED(count); + + *buf = charget(); + return 1; +} + +/*********************************************************************************************************************** +* Function Name: close +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void close (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +/*********************************************************************************************************************** +* Function Name: fstat +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void fstat (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +/*********************************************************************************************************************** +* Function Name: isatty +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void isatty (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +/*********************************************************************************************************************** +* Function Name: lseek +* Description : dummy +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void lseek (void) +{ + /* This is dummy function. + This function is used to suppress the warning messages of GNU compiler. + Plese edit the function as required. */ +} + +#endif /* defined(__GNUC__) */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowsrc.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowsrc.h new file mode 100644 index 000000000..15b2426fd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/lowsrc.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lowsrc.h +* Description : Functions to support stream I/O +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOWSRC_H +#define LOWSRC_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__CCRX__) +void init_iolib(void); +void close_all(void); +long open(const char *name, long mode, long flg); +long close(long fileno); +long write(long fileno, const unsigned char *buf, long count); +long read(long fileno, unsigned char *buf, long count); +long lseek(long fileno, long offset, long base); +#ifdef _REENTRANT +long *errno_addr(void) +long wait_sem(long semnum) +long signal_sem(long semnum) +#endif +#endif /* defined(__CCRX__) */ + +#if defined(__GNUC__) +int write(int fileno, char *buf, int count); +int read(int fileno, char *buf, int count); +int _write(int fileno, char *buf, int count); +int _read(int fileno, char *buf, int count); +void close(void); +void fstat(void); +void isatty(void); +void lseek(void); +#endif /* defined(__GNUC__) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/mcu_locks.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/mcu_locks.c new file mode 100644 index 000000000..4fb5c24b3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/mcu_locks.c @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.c +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Used for getting MCU information to accurately reflect available MCU resources. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +/* Below are locks for controlling access to MCU resources. */ +BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[BSP_NUM_LOCKS]; + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c new file mode 100644 index 000000000..ab902b064 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_common.c @@ -0,0 +1,225 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.c +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 26.03.2014 1.10 Added R_BSP_SoftwareDelay() function +* : 03.09.2014 1.20 Corrected R_BSP_SoftwareDelay() timing when using an RX64M +* : 30.09.2015 1.30 Added RX23T +* : 01.02.2016 1.40 Added RX24T +* Changed the value of the following macro definition. +* - OVERHEAD_CYCLES +* - OVERHEAD_CYCLES_64 +* : 29.02.2016 1.50 Added RX230 +* : 01.10.2016 1.60 Added RX65N +* : 22.08.2016 1.70 Added RX24U +* : 15.05.2017 1.80 Changed method of selecting the number of CPU cycles required to execute +* the delayWait() loop. +* : 27.07.2018 1.90 Changed the value of the following macro definition, because added RX66T. +* - CPU_CYCLES_PER_LOOP +* : 28.02.2019 2.00 Deleted the following definition. +* (The following definition moved to the common file (mcu_info.h).) +* - CPU_CYCLES_PER_LOOP +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_OVERHEAD_CYCLES +* - BSP_PRV_OVERHEAD_CYCLES_64 +* - BSP_PRV_CKSEL_LOCO +* Renamed following function. +* - delay_wait +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get information about current board and MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_OVERHEAD_CYCLES (2) /* R_BSP_SoftwareDelay() overhead per call */ +#define BSP_PRV_OVERHEAD_CYCLES_64 (2) /* R_BSP_SoftwareDelay() overhead per call using 64-bit ints */ + +#define BSP_PRV_CKSEL_LOCO (0x0) /* SCKCR3 register setting for LOCO */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_GetVersion + ******************************************************************************************************************//** + * @brief Returns the current version of the r_bsp. + * @return Version of the r_bsp. + * @details This function will return the version of the currently installed r_bsp. The version number is encoded + * where the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For + * example, Version 4.25 would be returned as 0x00040019. + */ +uint32_t R_BSP_GetVersion (void) +{ + /* These version macros are defined in platform.h. */ + return ((((uint32_t)R_BSP_VERSION_MAJOR) << 16) | (uint32_t)R_BSP_VERSION_MINOR); +} /* End of function R_BSP_GetVersion() */ + + +/*********************************************************************************************************************** +* Function Name: delay_wait +* Description : This asm loop executes a known number (5) of CPU cycles. If a value of '4' is passed +* in as an argument, then this function would consume 20 CPU cycles before returning. +* Arguments : loop_cnt - A single 32-bit value is provided as the number of loops to execute. +* Return Value : None +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(delay_wait) +void delay_wait (unsigned long loop_cnt) +{ + R_BSP_ASM_INTERNAL_USED(loop_cnt) + R_BSP_ASM_BEGIN + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_NEXT(0) ) + R_BSP_ASM( NOP ) + R_BSP_ASM_LAB(0: ) + R_BSP_ASM( NOP ) + R_BSP_ASM( SUB #01H, R1 ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_PREV(0) ) + R_BSP_ASM_END +} /* End of function delay_wait() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_GetIClkFreqHz + ******************************************************************************************************************//** + * @brief Returns the system clock frequency. + * @return System clock frequency specified by the r_bsp. + * @details This function returns the system clock frequency. For example, when the system clock is set to 120 MHz in + * r_bsp_config_h and the r_bsp has completed to specify the clock setting, then even if the user changed the system + * clock frequency to 60 MHz, the return value is '60000000'. + */ +uint32_t R_BSP_GetIClkFreqHz(void) +{ + return get_iclk_freq_hz(); // Get the MCU specific ICLK frequency +} /* End of function R_BSP_GetIClkFreqHz() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareDelay + ******************************************************************************************************************//** + * @brief Delay the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' for the units specified. + * @retval true True if delay executed. + * @retval false False if delay/units combination resulted in overflow/underflow. + * @details This is function that may be called for all MCU targets to implement a specific wait time. + * The actual delay time is plus the overhead at a specified duration. The overhead changes under the influence of + * the compiler, operating frequency and ROM cache. When the operating frequency is low, or the specified duration in + * units of microsecond level, please note that the error becomes large. + */ +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units) +{ + volatile uint32_t iclk_rate; + volatile uint32_t delay_cycles; + volatile uint32_t loop_cnt; + volatile uint64_t delay_cycles_64; + volatile uint64_t loop_cnt_64; + +#ifdef BSP_CFG_PARAM_CHECKING_ENABLE + if ((BSP_DELAY_MICROSECS != units) && (BSP_DELAY_MILLISECS != units) && (BSP_DELAY_SECS != units)) + { + return(false); + } +#endif + + iclk_rate = R_BSP_GetIClkFreqHz(); /* Get the current ICLK frequency */ + + /* + * In order to handle all possible combinations of delay/ICLK it is necessary to use 64-bit + * integers (not all MCUs have floating point support). However, there is no native hw support + * for 64 bit integers so it requires many more clock cycles. This is not an issue if the + * requested delay is long enough and the ICLK is fast, but for delays in the low microseconds + * and/or a slow ICLK we use 32 bit integers to reduce the overhead cycles of this function + * by approximately a third and stand the best chance of achieving the requested delay. + */ + if ( (BSP_DELAY_MICROSECS == units) && + (delay <= (0xFFFFFFFFUL / iclk_rate)) ) /* Ensure (iclk_rate * delay) will not exceed 32 bits */ + { + delay_cycles = ((iclk_rate * delay) / units); + + if (delay_cycles > BSP_PRV_OVERHEAD_CYCLES) + { + delay_cycles -= BSP_PRV_OVERHEAD_CYCLES; + } + else + { + delay_cycles = 0; + } + + loop_cnt = delay_cycles / CPU_CYCLES_PER_LOOP; + + if (0 == loop_cnt) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + } + else + { + /* Casting is valid because it matches the type to the right side or argument. */ + delay_cycles_64 = (((uint64_t)iclk_rate * (uint64_t)delay) / units); + + if (delay_cycles_64 > BSP_PRV_OVERHEAD_CYCLES_64) + { + delay_cycles_64 -= BSP_PRV_OVERHEAD_CYCLES_64; + } + else + { + delay_cycles = 0; + } + + loop_cnt_64 = delay_cycles_64 / CPU_CYCLES_PER_LOOP; + + if ((loop_cnt_64 > 0xFFFFFFFFUL) || (0 == loop_cnt_64)) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + + /* Casting is valid because it matches the type to the right side or argument. */ + loop_cnt = (uint32_t)loop_cnt_64; + } + + delay_wait(loop_cnt); + + return(true); +} /* End of function R_BSP_SoftwareDelay() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h new file mode 100644 index 000000000..f5146b7ce --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_common.h @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.h +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 25.06.2013 1.10 Now contains standard includes (stdint.h, stdbool.h, etc) as well as include for +* r_typedefs.h when needed. +* : 02.07.2013 1.11 Added #include for machine.h. +* : 10.02.2014 1.12 Changed minor version to '40'. +* : 24.03.2014 1.12 Changed minor version to '60'. +* : 14.04.2014 1.12 Added typedef for fit_callback_t. +* : 30.09.2015 1.13 Changed Major/Minor version to 3.00 +* : 30.09.2015 1.14 Changed Minor version to 3.01 +* : 01.12.2015 1.15 Changed Minor version to 3.10 +* : 01.02.2016 1.16 Changed Minor version to 3.20 +* : 29.02.2016 1.17 Changed Minor version to 3.30 +* : 13.04.2016 1.18 Changed Minor version to 3.31 +* : 01.10.2016 1.19 Changed Minor version to 3.40 +* : 04.11.2016 1.20 Changed Minor version to 3.50 +* : 15.05.2017 1.21 Changed Minor version to 3.60 +* : 01.11.2017 1.22 Changed Minor version to 3.70 +* : 01.12.2017 1.23 Changed Minor version to 3.71 +* : 01.07.2018 1.24 Changed Minor version to 3.80 +* : 27.07.2018 1.25 Changed Minor version to 3.90. +* : 31.08.2018 1.26 Changed Minor version to 3.91. +* : 31.10.2018 1.27 Changed Major/Minor version to 4.00. +* : 11.01.2019 1.28 Changed Minor version to 4.01. +* : 28.02.2019 1.29 Changed Major version to 5.00. +* Added the following macro definition. +* - INTERNAL_NOT_USED(p) +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 29.03.2019 1.30 Changed Minor version to 5.10. +* : 08.04.2019 1.31 Changed Minor version to 5.20. +* : 23.07.2019 1.32 Changed Minor version to 5.21. +* : 26.07.2019 1.33 Changed Minor version to 5.30. +* : 31.07.2019 1.34 Changed Minor version to 5.40. +* : 08.10.2019 1.35 Changed Minor version to 5.50. +* : 10.12.2019 1.36 Changed Minor version to 5.51. +* : 14.02.2020 1.37 Changed Minor version to 5.52. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* C99 (or later) is necessary because r_rx_compiler.h uses Pragma operator and variadic macros. + * This means that r_typedefs.h is not used in any case. */ +#if !defined(__cplusplus) && !defined(CPPAPP) +/* All implementation is C99 (or later) */ +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#include +#include +#include +#include +#else +#error "This version of FIT needs C99 (or later)." +#endif +#else /* defined(__cplusplus) || defined(CPPAPP) */ +/* Interface might be referred from C++ */ +#include +#include +#include +#include +#endif /* !defined(__cplusplus) && !defined(CPPAPP) */ + +#if defined(__CCRX__) || defined(__ICCRX__) +/* Intrinsic functions provided by compiler. */ +#include +#elif defined(__GNUC__) +/* No header file for intrinsic functions. */ +#else +/* PORT: Use header file for other compiler and port r_rx_compiler.h. */ +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_BSP_COMMON_H +#define R_BSP_COMMON_H + +/* Version Number of r_bsp. */ +#define R_BSP_VERSION_MAJOR (5) +#define R_BSP_VERSION_MINOR (52) + +/* This macro is used to suppress compiler messages about not only a parameter but also a auto variable not being used + * in a function. The nice thing about using this implementation is that it does not take any extra RAM or ROM. + * This macro is available for the followings: + * CC-RX's 'M0520826:Parameter "XXXX" was never referenced' + * CC-RX's 'W0520550:Variable "XXXX" was set but never used' + * GNURX's 'unused parameter 'XXXX' [-Wunused-parameter]' + * GNURX's 'variable 'XXXX' set but not used [-Wunused-but-set-variable]' + * When the variable is declared as volatile, the '&' can be applied like 'R_INTERNAL_NOT_USED(&volatile_variable);'. + */ +#define INTERNAL_NOT_USED(p) ((void)(p)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available delay units. */ +typedef enum +{ + BSP_DELAY_MICROSECS = 1000000, // Requested delay amount is in microseconds + BSP_DELAY_MILLISECS = 1000, // Requested delay amount is in milliseconds + BSP_DELAY_SECS = 1 // Requested delay amount is in seconds +} bsp_delay_units_t; + +/* Easy to use typedef for FIT module callback functions. */ +typedef void (*fit_callback_t)(void *p_args); + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t R_BSP_GetVersion(void); +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +uint32_t R_BSP_GetIClkFreqHz(void); + +/* End of multiple inclusion prevention macro */ +#endif /* R_BSP_COMMON_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c new file mode 100644 index 000000000..b575b5736 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_cpu.c @@ -0,0 +1,672 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.c +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 3.10 Added the API function(R_BSP_SoftwareReset). +* Modified comment of API function to Doxygen style. +* Added the vbatt_voltage_stability_wait function. +* Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +* : 31.07.2019 3.11 Deleted the compile condition for R_BSP_SoftwareReset. +* : 08.10.2019 3.12 Changed the following functions. +* - R_BSP_InterruptsDisable +* - R_BSP_InterruptsEnable +* - R_BSP_CpuInterruptLevelWrite +* : 10.12.2019 3.13 Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500) +#endif + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/* The macro definition for combinations where settings of USBVON bit conflict. */ +#define BSP_PRV_USBVON_CONFLICT (BSP_VOL_USB_POWEROFF | BSP_VOL_USB_POWERON) +/* The macro definition for combinations where settings of PGAVLS bit conflict. */ +#define BSP_PRV_PGAVLS_CONFLICT (BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT | BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT) +/* The macro definition for combinations where settings of RICVLS bit conflict. */ +#define BSP_PRV_RICVLS_CONFLICT (BSP_VOL_RIIC_4_5V_OROVER | BSP_VOL_RIIC_UNDER_4_5V) +/* Bit number of VOLSR register. */ +#define BSP_PRV_VOLSR_RICVLS_BIT_NUM (7) +#define BSP_PRV_VOLSR_PGAVLS_BIT_NUM (6) +#define BSP_PRV_VOLSR_USBVON_BIT_NUM (2) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Used for holding reference counters for protection bits. */ +static volatile uint16_t s_protect_counters[BSP_REG_PROTECT_TOTAL_ITEMS]; + +/* Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t s_prcr_masks[BSP_REG_PROTECT_TOTAL_ITEMS-1] = +{ +#ifdef BSP_MCU_RCPC_PRC0 + 0x0001, /* PRC0. */ +#endif +#ifdef BSP_MCU_RCPC_PRC1 + 0x0002, /* PRC1. */ +#endif +#ifdef BSP_MCU_RCPC_PRC2 + 0x0004, /* PRC2. */ +#endif +#ifdef BSP_MCU_RCPC_PRC3 + 0x0008, /* PRC3. */ +#endif +}; +#endif + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsDisable + ******************************************************************************************************************//** + * @brief Globally disables interrupts. + * @details This function globally disables interrupts. This is performed by clearing the 'I' bit in the CPU's + * Processor Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsDisable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to clear the I flag. */ + R_BSP_CLRPSW_I(); + } + +} /* End of function R_BSP_InterruptsDisable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsEnable + ******************************************************************************************************************//** + * @brief Globally enable interrupts. + * @details This function globally enables interrupts. This is performed by setting the 'I' bit in the CPU's Processor + * Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsEnable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to set the I flag. */ + R_BSP_SETPSW_I(); + } + +} /* End of function R_BSP_InterruptsEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelRead + ******************************************************************************************************************//** + * @brief Reads the CPU's Interrupt Priority Level. + * @return The CPU's Interrupt Priority Level. + * @details This function reads the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. + */ +uint32_t R_BSP_CpuInterruptLevelRead (void) +{ + /* Use the compiler intrinsic function to read the CPU IPL. */ + uint32_t psw_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + psw_value = (uint32_t)R_BSP_GET_PSW(); + psw_value = psw_value & 0x0f000000; + psw_value = psw_value >> 24; + + return psw_value; +} /* End of function R_BSP_CpuInterruptLevelRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelWrite + ******************************************************************************************************************//** + * @brief Writes the CPU's Interrupt Priority Level. + * @param[in] level The level to write to the CPU's IPL. + * @retval true Successful, CPU's IPL has been written. + * @retval false Failure, provided 'level' has invalid IPL value or called when the CPU is in User Mode. + * @details This function writes the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. This function does check to make sure that the IPL being written is valid. + * The maximum and minimum valid settings for the CPU IPL are defined in mcu_info.h using the BSP_MCU_IPL_MAX and + * BSP_MCU_IPL_MIN macros. + * @note The CPU's IPL can only be modified by the user when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does not control IPL and return false. + */ +bool R_BSP_CpuInterruptLevelWrite (uint32_t level) +{ + bool ret; + uint32_t pmode; + + /* The R_BSP_SET_IPL() function use the MVTIPL instruction. + The MVTIPL instruction needs to set an immediate value to src. */ + + ret = false; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + ret = true; + + /* Use the compiler intrinsic function to set the CPU IPL. */ + switch (level) + { + case (0): + + /* IPL = 0 */ + R_BSP_SET_IPL(0); + break; + + case (1): + + /* IPL = 1 */ + R_BSP_SET_IPL(1); + break; + + case (2): + + /* IPL = 2 */ + R_BSP_SET_IPL(2); + break; + + case (3): + + /* IPL = 3 */ + R_BSP_SET_IPL(3); + break; + + case (4): + + /* IPL = 4 */ + R_BSP_SET_IPL(4); + break; + + case (5): + + /* IPL = 5 */ + R_BSP_SET_IPL(5); + break; + + case (6): + + /* IPL = 6 */ + R_BSP_SET_IPL(6); + break; + + case (7): + + /* IPL = 7 */ + R_BSP_SET_IPL(7); + break; + + #if 7 < BSP_MCU_IPL_MAX + case (8): + + /* IPL = 8 */ + R_BSP_SET_IPL(8); + break; + + case (9): + + /* IPL = 9 */ + R_BSP_SET_IPL(9); + break; + + case (10): + + /* IPL = 10 */ + R_BSP_SET_IPL(10); + break; + + case (11): + + /* IPL = 11 */ + R_BSP_SET_IPL(11); + break; + + case (12): + + /* IPL = 12 */ + R_BSP_SET_IPL(12); + break; + + case (13): + + /* IPL = 13 */ + R_BSP_SET_IPL(13); + break; + + case (14): + + /* IPL = 14 */ + R_BSP_SET_IPL(14); + break; + + case (15): + + /* IPL = 15 */ + R_BSP_SET_IPL(15); + break; + #endif /* BSP_MCU_IPL_MAX */ + + default: + ret = false; + break; + } + } + + return ret; +} /* End of function R_BSP_CpuInterruptLevelWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectEnable + ******************************************************************************************************************//** + * @brief Enables write protection for selected registers. + * @param[in] regs_to_protect Which registers to enable write protection for. + * @details This function enables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectDisable(), use counters for each entry in the bsp_reg_protect_t enum so + * that users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. An + * example of why this is needed is shown below in the Special Notes section below. + * @note + * (1) About why counters are needed. \n + * See Section 5.7 in the application note for details.\n + * (2) Notes on user mode \n + * The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control with + * this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* Is it safe to disable write access? */ + if (0 != s_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + s_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0 == s_protect_counters[regs_to_protect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_protect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + disable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) & (~s_prcr_masks[regs_to_protect])); + } + else + { + /* Enable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. It could be assumed that the B0WI bit is still cleared from a call to + protection disable function, but it is written here to make sure that the PFSWE bit always gets + cleared. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Disable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 0; + + /* Disable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 1; + } + } + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_protect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectDisable + ******************************************************************************************************************//** + * @brief Disables write protection for selected registers. + * @param[in] regs_to_unprotect Which registers to disable write protection for. + * @details This function disables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectEnable(), use counters for each entry in the bsp_reg_protect_t enum so that + * users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. + * @note The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control + * with this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* If this is first entry then disable protection. */ + if (0 == s_protect_counters[regs_to_unprotect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_unprotect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. + Set lower bits to 1 to enable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) | s_prcr_masks[regs_to_unprotect]); + } + else + { + /* Disable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Enable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 1; + } + } + + /* Increment the protect counter */ + s_protect_counters[regs_to_unprotect]++; + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_unprotect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectDisable() */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/********************************************************************************************************************** + * Function Name: R_BSP_VoltageLevelSetting + ******************************************************************************************************************//** + * @brief This API function is used excessively with the RX66T and RX72T. It makes settings to the voltage level + * setting register (VOLSR) that are necessary in order to use the USB, AD, and RIIC peripheral modules. Call this + * function only when it is necessary to change the register settings. + * @param[in] ctrl_ptn Register Setting Patterns + * The following setting patterns cannot be selected at the same time. + * When specifying more than one pattern at the same time, use the "|" (OR) operator. + * - BSP_VOL_USB_POWEROFF and BSP_VOL_USB_POWERON + * - BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT and BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT + * - BSP_VOL_RIIC_4_5V_OROVER and BSP_VOL_RIIC_UNDER_4_5V + * + * BSP_VOL_USB_POWEROFF: Updates the USBVON bit to 0. + * + * BSP_VOL_USB_POWERON: Updates the USBVON bit to 1. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT: Updates the PGAVLS bit to 0. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT: Updates the PGAVLS bit to 1. + * + * BSP_VOL_RIIC_4_5V_OROVER: Updates the RICVLS bit to 0. + * + * BSP_VOL_RIIC_UNDER_4_5V: Updates the RICVLS bit to 1. + * @retval true Processing completed, register successfully updated. + * @retval false The function was called under the following conditions, so the register setting was not updated. + * - Setting patterns that cannot be selected at the same time were selected. + * - A setting pattern related to the USB was selected when the USB was not in the module stop state. + * - A setting pattern related to the AD was selected when the AD was not in the module stop state. + * - A setting pattern related to the RIIC was selected when the RIIC was not in the module stop state. + * @details This function initializes the voltage level setting register (VOLSR), which is necessary in order to use + * the USB, AD and RIIC peripheral modules. When specifying a setting pattern related to the USB, call this function + * before the USB is released from the module stop state. When specifying a setting pattern related to the AD, call + * this function before the AD (unit 0 and unit 1) is released from the module stop state. When specifying a setting + * pattern related to the RIIC, call this function before the RIIC is released from the module stop state. If the + * function is called with a setting pattern related to the USB specified after the USB is released from the module + * stop state, the function returns "false" as the return value and does not update the register settings. If the + * function is called with a setting pattern related to the AD specified after the AD (unit 0 and unit 1) is released + * from the module stop state, the function returns "false" as the return value and does not update the register + * settings. Finally, if the function is called with a setting pattern related to the RIIC specified after the RIIC is + * released from the module stop state, the function returns "false" as the return value and does not update the + * register settings. + */ +bool R_BSP_VoltageLevelSetting (uint8_t ctrl_ptn) +{ + uint8_t *p_volsr_addr; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* ---- CHECK ARGUMENTS ---- */ + if (BSP_PRV_USBVON_CONFLICT == (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + return false; + } + + if (BSP_PRV_PGAVLS_CONFLICT == (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + return false; + } + + if (BSP_PRV_RICVLS_CONFLICT == (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + return false; + } +#endif + + /* Check USB module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(USB0)) + { + return false; + } + } + + /* Check AD module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if((0 == MSTP(S12AD)) || (0 == MSTP(S12AD1))) + { + return false; + } + } + + /* Check RIIC module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(RIIC0)) + { + return false; + } + } + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_volsr_addr = (uint8_t *)&SYSTEM.VOLSR.BYTE; + + /* Updated the RICVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_RIIC_UNDER_4_5V)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_RIIC_4_5V_OROVER)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + /* Updated the PGAVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + /* Updated the USBVON bit. */ + if(0 != (ctrl_ptn & BSP_VOL_USB_POWERON)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_USB_POWEROFF)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + return true; +} /* End of function R_BSP_VoltageLevelSetting() */ +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareReset + ******************************************************************************************************************//** + * @details Reset the MCU by Software Reset. + */ +void R_BSP_SoftwareReset(void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + /* Protect off. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); +#endif + + /* Resets the MCU. */ + SYSTEM.SWRR = 0xA501; + + /* WAIT_LOOP */ + while(1) + { + R_BSP_NOP(); + } +} /* End of function R_BSP_SoftwareReset() */ + +/*********************************************************************************************************************** +* Function Name: bsp_register_protect_open +* Description : Initializes variables needed for register protection functionality. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_register_protect_open (void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + uint32_t i; + + /* Initialize reference counters to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_REG_PROTECT_TOTAL_ITEMS; i++) + { + s_protect_counters[i] = 0; + } +#else + /* No registers to protect. */ +#endif +} /* End of function bsp_register_protect_open() */ + +/*********************************************************************************************************************** +* Function Name: bsp_ram_initialize +* Description : Initialize ram variable. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_ram_initialize (void) +{ + uint32_t i; + + /* Initialize g_bsp_Locks to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_NUM_LOCKS; i++) + { + g_bsp_Locks[i].lock = 0; + } +} /* End of function bsp_ram_initialize() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c new file mode 100644 index 000000000..a72ade038 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.c @@ -0,0 +1,1085 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.c +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.04.2019 1.01 Added process for Group IE0 interrupts. +* Added process for EXNMI interrupts. +* : 26.07.2019 1.10 Modified comment of API function to Doxygen style. +* Modified the following function for added function. +* - R_BSP_InterruptControl +* Added the following functions. +* - bsp_fit_interrupts_control +* - bsp_fit_interrupt_enable +* - bsp_fit_interrupt_disable +* Fixed coding style. +* : 08.10.2019 1.11 Added process for software interrupt. +* : 10.12.2019 1.12 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_FLOATING_POINT +/* Defines CV, CO, CZ, CU, CX, and CE bits. */ +#define BSP_PRV_FPU_CAUSE_FLAGS (0x000000FC) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* This array holds callback functions. */ +static void (* g_bsp_vectors[BSP_INT_SRC_TOTAL_ITEMS])(void * pdata); + +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata); + +#ifdef BSP_MCU_GROUP_INTERRUPT +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl); +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestEnable + ******************************************************************************************************************//** + * @brief Enable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Enable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector number + * of the argument, and set "1" to that bit. The macro defined in iodefine.h can be used to the setting of the + * argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestEnable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_SET(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestDisable + ******************************************************************************************************************//** + * @brief Disable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Disable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector + * number of the argument, and clear "0" to that bit. The macro defined in iodefine.h can be used to the setting of + * the argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestDisable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_CLEAR(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestDisable() */ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_open +* Description : Initialize callback function array. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_interrupt_open (void) +{ + uint32_t i; + + /* WAIT_LOOP */ + for (i = 0; i < BSP_INT_SRC_TOTAL_ITEMS; i++) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[i] = FIT_NO_FUNC; + } + +#ifdef BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT + /* Initialize mapped interrupts. */ + bsp_mapped_interrupt_open(); +#endif + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT1); +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT2); +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ +} /* End of function bsp_interrupt_open() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptWrite + ******************************************************************************************************************//** + * @brief Registers a callback function for an interrupt. + * @param[in] vector Which interrupt to register a callback for. + * @param[in] callback Pointer to function to call when interrupt occurs. + * @retval BSP_INT_SUCCESS Successful, callback has been registered. + * @retval BSP_INT_ERR_INVALID_ARG Invalid function address input, any previous function has been unregistered. + * @details This function registers a callback function for an interrupt. If FIT_NO_FUNC, NULL, or any other invalid + * function address is passed for the callback argument then any previously registered callbacks are unregistered. + * If one of the interrupts that is handled by this code is triggered then the interrupt handler will query this code + * to see if a valid callback function is registered. If one is found then the callback function will be called. + * If one is not found then the interrupt handler will clear the appropriate flag(s) and exit. If the user has a + * callback function registered and wishes to no longer handle the interrupt then the user should call this function + * again with FIT_NO_FUNC as the vector parameter. + * @note Use of FIT_NO_FUNC is preferred over NULL since access to the address defined by FIT_NO_FUNC will cause a + * bus error which is easy for the user to catch. NULL typically resolves to 0 which is a valid address on RX MCUs. + */ +bsp_int_err_t R_BSP_InterruptWrite (bsp_int_src_t vector, bsp_int_cb_t callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)callback == (uint32_t)NULL) || ((uint32_t)callback == (uint32_t)FIT_NO_FUNC)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[vector] = FIT_NO_FUNC; + } + else + { + g_bsp_vectors[vector] = callback; + } + + return err; +} /* End of function R_BSP_InterruptWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRead + ******************************************************************************************************************//** + * @brief Gets the callback for an interrupt if one is registered. + * @param[in] vector Which interrupt to read the callback for. + * @param[out] callback Pointer to where to store callback address. + * @retval BSP_INT_SUCCESS Successful, callback address has been returned. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @details This function returns the callback function address for an interrupt if one has been registered. If a + * callback function has not been registered then an error is returned and nothing is stored to the callback address. + */ +bsp_int_err_t R_BSP_InterruptRead (bsp_int_src_t vector, bsp_int_cb_t * callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)g_bsp_vectors[vector] == (uint32_t)NULL) || ((uint32_t)g_bsp_vectors[vector] == (uint32_t)FIT_NO_FUNC)) + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + else + { + *callback = g_bsp_vectors[vector]; + } + + return err; +} /* End of function R_BSP_InterruptRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptControl + ******************************************************************************************************************//** + * @brief Controls various interrupt operations. + * @param[in] vector Which interrupt to control for.\n + * If the interrupt control commands is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE or the BSP_INT_CMD_FIT_INTERRUPT_DISABLE + * commands, set BSP_INT_SRC_EMPTY to "vector" because no arguments are used. + * @param[in] cmd Interrupt control command. + * @param[in,out] pdata Pointer to the argument for each interrupt control command. Typecasted to void*. See typedef + * defines of bsp_int_ctrl_t. \n + * Most of the interrupt control commands do not need the argument and take FIT_NO_PTR for + * this parameter. If the interrupt control command is the BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command, set the + * interrupt priority level for group interrupts as the argument. If the interrupt control command is the + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE command, set the address of a variable for saving the current processor interrupt + * priority level in the argument. If the interrupt control command is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE command, + * set the address of a variable used in the BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + * @retval BSP_INT_SUCCESS Successful. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @retval BSP_INT_ERR_INVALID_ARG The command passed is invalid. + * @retval BSP_INT_ERR_UNSUPPORTED This processing is not supported. + * @retval BSP_INT_ERR_GROUP_STILL_ENABLED Group interrupt request remains enabled. + * @retval BSP_INT_ERR_INVALID_IPL Illegal IPL value input. + * @details This function controls the interrupt callback function call and enabling/disabling interrupts such as bus + * error interrupt, floating-point exception, NMI pin interrupt, and group interrupts, and enabling/disabling + * interrupts by controlling the Processor Interrupt Priority Level. When BSP_INT_CMD_GROUP_INTERRUPT_ENABLE is set as + * the interrupt control command, the interrupt request (IER) for group interrupts is enabled and also the interrupt + * priority level is set. The interrupt priority level set must be higher than the current level. When + * BSP_INT_CMD_GROUP_INTERRUPT_DISABLE is set as the interrupt control command, the interrupt request (IER) for group + * interrupts is disabled. Note that the interrupt request (IER) for group interrupts cannot be disabled as long as + * all interrupt requests (GEN) caused by grouped interrupt sources are disabled. When + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE is set as the interrupt control command, the current processor interrupt priority + * level (IPL) is saved to the address specified by pdata as an argument, and disables interrupts by controlling the + * IPL. The value of IPL to be set is the value of BSP_CFG_FIT_IPL_MAX. When BSP_INT_CMD_FIT_INTERRUPT_ENABLE is set + * as the interrupt control command, the interrupt is enabled by setting the value stored in the address specified by + * pdata to IPL. These two commands are valid only in supervisor mode. When BSP_INT_CMD_FIT_INTERRUPT_DISABLE and + * BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands are executed in user mode, Controlling IPL is not executed and an error + * code BSP_INT_ERR_UNSUPPORTED is returned. + * @note BSP_INT_CMD_FIT_INTERRUPT_DISABLE and BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands can be used to secure + * atomicity of critical sections. However, these commands are valid only in supervisor mode. When these commands are + * executed in user mode, atomicity is not to secure.\n + * See Section 5.15 in the application note for more information. + */ +bsp_int_err_t R_BSP_InterruptControl (bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata) +{ + bsp_int_err_t err; + bsp_int_cb_args_t cb_args; + + err = BSP_INT_SUCCESS; + +#ifdef BSP_MCU_GROUP_INTERRUPT + /* nothing */ +#else + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(pdata); +#endif + + switch (cmd) + { + case (BSP_INT_CMD_CALL_CALLBACK): + + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)g_bsp_vectors[vector] != (uint32_t)NULL) && ((uint32_t)g_bsp_vectors[vector] != (uint32_t)FIT_NO_FUNC)) + { + /* Fill in callback info. */ + cb_args.vector = vector; + + g_bsp_vectors[vector](&cb_args); + } + else + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + break; + + case (BSP_INT_CMD_INTERRUPT_ENABLE): + err = bsp_interrupt_enable_disable(vector, true); + break; + + case (BSP_INT_CMD_INTERRUPT_DISABLE): + err = bsp_interrupt_enable_disable(vector, false); + break; + +#ifdef BSP_MCU_GROUP_INTERRUPT + case (BSP_INT_CMD_GROUP_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_gr_int_enable_disable(vector, true, ((bsp_int_ctrl_t *)pdata)->ipl); + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + break; + + case (BSP_INT_CMD_GROUP_INTERRUPT_DISABLE): + err = bsp_gr_int_enable_disable(vector, false, 0); + break; +#endif + + case (BSP_INT_CMD_FIT_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(true, (bsp_int_ctrl_t *)pdata); + break; + + case (BSP_INT_CMD_FIT_INTERRUPT_DISABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(false, (bsp_int_ctrl_t *)pdata); + break; + + default: + err = BSP_INT_ERR_INVALID_ARG; + break; + } + + return err; +} /* End of function R_BSP_InterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_fit_interrupts_control +* Description : +* Arguments : enable - +* Whether to enable or disable the interrupt. +* pdata - +* Pointer to variable for saves ipl or restore ipl. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid argument input. +* BSP_INT_ERR_INVALID_IPL - +* Invalid IPL input. +* BSP_INT_ERR_UNSUPPORTED - +* This processing is not supported. (Executed in user mode.) +***********************************************************************************************************************/ +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata) +{ + bsp_int_err_t err; + uint32_t pmode; + bool ret; + uint32_t ipl_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + err = BSP_INT_SUCCESS; + + if (true == enable) + { + ipl_value = pdata->ipl; + } + else + { + /* Get the current Processor Interrupt Priority Level (IPL) and save IPL value. */ + pdata->ipl = R_BSP_CpuInterruptLevelRead(); + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + ipl_value = BSP_CFG_FIT_IPL_MAX; + } + + if (pdata->ipl < BSP_CFG_FIT_IPL_MAX) + { + ret = R_BSP_CpuInterruptLevelWrite(ipl_value); + if (false == ret) + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_UNSUPPORTED; + } + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_fit_interrupts_control() */ + +#ifdef BSP_MCU_GROUP_INTERRUPT +/*********************************************************************************************************************** +* Function Name: bsp_gr_int_enable_disable +* Description : Either enables or disables a group interrupt. If a group interrupt is called multiple times to be +* enabled then it will use the highest given IPL. A group interrupt will only be disabled when all +* interrupt sources for that group are already disabled. +* Arguments : vector - +* An interrupt source inside the group that is to be enabled/disabled. +* enable - +* Whether to enable or disable the interrupt. +* ipl - +* If enabling a group interrupt, what IPL to use. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid IPL or vector +* BSP_INT_ERR_GROUP_STILL_ENABLED - +* Not all group interrupts were disabled so group interrupt was not disabled. +***********************************************************************************************************************/ +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl) +{ + bsp_int_err_t err = BSP_INT_SUCCESS; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* If interrupt is going to be enabled, verify that IPL is valid. */ + if ((true == enable) && ((BSP_MCU_IPL_MIN == ipl) || (ipl > BSP_MCU_IPL_MAX))) + { + return BSP_INT_ERR_INVALID_ARG; + } +#endif + + if ((vector > BSP_INT_SRC_GR_INT_IE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BE0_TOP)) + { + /* Group IE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_IE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPIE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = (uint8_t)((ipl > IPR(ICU, GROUPIE0)) ? ipl : IPR(ICU, GROUPIE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPIE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENIE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL0_TOP)) + { + /* Group BE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = (uint8_t)((ipl > IPR(ICU, GROUPBE0)) ? ipl : IPR(ICU, GROUPBE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL1_TOP)) + { + /* Group BL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = (uint8_t)((ipl > IPR(ICU, GROUPBL0)) ? ipl : IPR(ICU, GROUPBL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL1_TOP) && (vector < BSP_INT_SRC_GR_INT_BL2_TOP)) + { + /* Group BL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = (uint8_t)((ipl > IPR(ICU, GROUPBL1)) ? ipl : IPR(ICU, GROUPBL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL2_TOP) && (vector < BSP_INT_SRC_GR_INT_AL0_TOP)) + { + /* Group BL2. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL2 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL2) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = (uint8_t)((ipl > IPR(ICU, GROUPBL2)) ? ipl : IPR(ICU, GROUPBL2)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL2)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL2.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL0_TOP) && (vector < BSP_INT_SRC_GR_INT_AL1_TOP)) + { + /* Group AL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = (uint8_t)((ipl > IPR(ICU, GROUPAL0)) ? ipl : IPR(ICU, GROUPAL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL1_TOP) && (vector < BSP_INT_SRC_GR_INT_END)) + { + /* Group AL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = (uint8_t)((ipl > IPR(ICU, GROUPAL1)) ? ipl : IPR(ICU, GROUPAL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + } + else + { + /* Vector given was not part of a group. */ + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_gr_int_enable_disable() */ +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_supervisor_inst_isr +* Description : Supervisor Instruction Violation ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_supervisor_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_SUPERVISOR_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_supervisor_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +/*********************************************************************************************************************** +* Function name: excep_access_isr +* Description : Access exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_access_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_ACCESS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_access_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_undefined_inst_isr +* Description : Undefined instruction exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_undefined_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_UNDEFINED_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_undefined_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +/*********************************************************************************************************************** +* Function name: excep_floating_point_isr +* Description : Floating point exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_floating_point_isr(void) +{ +#ifdef __FPU + /* Used for reading FPSW register. */ + uint32_t tmp_fpsw; +#endif + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_FPU, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + +#ifdef __FPU + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW(tmp_fpsw & ((uint32_t)~BSP_PRV_FPU_CAUSE_FLAGS)); +#endif +} /* End of function excep_floating_point_isr() */ +#endif + +#ifdef BSP_MCU_NON_MASKABLE_ISR +/*********************************************************************************************************************** +* Function name: non_maskable_isr +* Description : Non-maskable interrupt ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void non_maskable_isr(void) +{ + /* Determine what is the cause of this interrupt. */ + +#ifdef BSP_MCU_NMI_EXC_NMI_PIN + /* EXC_NMI_PIN */ + if ((1 == ICU.NMISR.BIT.NMIST) && (1 == ICU.NMIER.BIT.NMIEN)) + { + /* NMI pin interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_NMI_PIN, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear NMI pin interrupt flag. */ + ICU.NMICLR.BIT.NMICLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_OSC_STOP_DETECT + /* OSC_STOP_DETECT */ + if ((1 == ICU.NMISR.BIT.OSTST) && (1 == ICU.NMIER.BIT.OSTEN)) + { + /* Oscillation stop detection interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_OSC_STOP_DETECT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear oscillation stop detect flag. */ + ICU.NMICLR.BIT.OSTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_WDT_ERROR + /* WDT_ERROR */ + if ((1 == ICU.NMISR.BIT.WDTST) && (1 == ICU.NMIER.BIT.WDTEN)) + { + /* WDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_WDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear WDT flag. */ + ICU.NMICLR.BIT.WDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD + /* LVD */ + if ((1 == ICU.NMISR.BIT.LVDST) && (1 == ICU.NMIER.BIT.LVDEN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +#endif + +#ifdef BSP_MCU_NMI_IWDT_ERROR + /* IWDT_ERROR */ + if ((1 == ICU.NMISR.BIT.IWDTST) && (1 == ICU.NMIER.BIT.IWDTEN)) + { + /* IWDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_IWDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear IWDT flag. */ + ICU.NMICLR.BIT.IWDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD1 + /* LVD1 */ + if ((1 == ICU.NMISR.BIT.LVD1ST) && (1 == ICU.NMIER.BIT.LVD1EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD1 flag. */ + ICU.NMICLR.BIT.LVD1CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD2 + /* LVD2 */ + if ((1 == ICU.NMISR.BIT.LVD2ST) && (1 == ICU.NMIER.BIT.LVD2EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.LVD2CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_VBATT + /* VBATT */ + if ((1 == ICU.NMISR.BIT.VBATST) && (1 == ICU.NMIER.BIT.VBATEN)) + { + /* VBATT monitoring interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_VBATT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.VBATCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_ECCRAM + /* ECCRAM */ + if ((1 == ICU.NMISR.BIT.ECCRAMST) && (1 == ICU.NMIER.BIT.ECCRAMEN)) + { + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + } +#endif + +#ifdef BSP_MCU_NMI_RAM + /* RAM */ + if ((1 == ICU.NMISR.BIT.RAMST) && (1 == ICU.NMIER.BIT.RAMEN)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_ECCRAM */ + } +#endif /* BSP_MCU_NMI_RAM */ + +#ifdef BSP_MCU_NMI_EXNMI + /* EXNMI */ + if ((1 == ICU.NMISR.BIT.EXNMIST) && (1 == ICU.NMIER.BIT.EXNMIEN)) + { + #ifdef BSP_MCU_NMI_EXNMI_RAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.RAMST) && (1 == ICU.EXNMIER.BIT.RAMEN)) + { + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_EXNMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_EXNMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_ECCRAM */ + } + #endif /* BSP_MCU_NMI_EXNMI_RAM */ + + #ifdef BSP_MCU_NMI_EXNMI_DPFPUEX + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.DPFPUST) && (1 == ICU.EXNMIER.BIT.DPFPUEN)) + { + /* Double-Precision Floating-Point Exception interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear DPFPUST flag. */ + ICU.EXNMICLR.BIT.DPFPUCLR = 1; + } + #endif /* BSP_MCU_NMI_EXNMI_DPFPUEX */ + } +#endif /* BSP_MCU_NMI_EXNMI */ + + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Return from Non-maskable interrupt handlling routine is prohibited. + Never use the non-maskable interrupt with an attempt to return to the program that was being executed at + the time of interrupt generation after the exception handling routine is ended. + */ + R_BSP_NOP(); + } +} /* End of function non_maskable_isr() */ +#endif /* BSP_MCU_NON_MASKABLE_ISR */ + +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +/*********************************************************************************************************************** +* Function name: undefined_interrupt_source_isr +* Description : All undefined interrupt vectors point to this function. +* Set a breakpoint in this function to determine which source is creating unwanted interrupts. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void undefined_interrupt_source_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_UNDEFINED_INTERRUPT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function undefined_interrupt_source_isr() */ +#endif + +#ifdef BSP_MCU_BUS_ERROR_ISR +/*********************************************************************************************************************** +* Function name: bus_error_isr +* Description : By default, this demo code enables the Bus Error Interrupt. This interrupt will fire if the user tries +* to access code or data from one of the reserved areas in the memory map, including the areas covered +* by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint +* during debugging and development, and further handling should be added by the user for their +* application. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void bus_error_isr (void) +{ + /* Clear the bus error */ + BSC.BERCLR.BIT.STSCLR = 1; + + /* + To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD. + The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units) + */ + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function bus_error_isr() */ +#endif + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h new file mode 100644 index 000000000..d6de101be --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_interrupts.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.h +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptRequestEnable(uint32_t vector); +void R_BSP_InterruptRequestDisable(uint32_t vector); +bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector, bsp_int_cb_t callback); +bsp_int_err_t R_BSP_InterruptRead(bsp_int_src_t vector, bsp_int_cb_t * callback); +bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata); + +void bsp_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_supervisor_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_access_isr) +#endif +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_undefined_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_floating_point_isr) +#endif +#ifdef BSP_MCU_NON_MASKABLE_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(non_maskable_isr) +#endif +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +R_BSP_PRAGMA_INTERRUPT_DEFAULT(undefined_interrupt_source_isr) +#endif +#ifdef BSP_MCU_BUS_ERROR_ISR +R_BSP_PRAGMA_INTERRUPT(bus_error_isr, VECT(BSC,BUSERR)) +#endif + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c new file mode 100644 index 000000000..6170397d7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_locking.c @@ -0,0 +1,187 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.c +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* : 10.12.2019 2.02 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform configuration. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareLock + ******************************************************************************************************************//** + * @brief Attempts to reserve a lock. + * @param[out] plock Pointer to lock structure with lock to try and acquire. + * @retval true Successful, lock was available and acquired. + * @retval false Failure, lock was already acquired and is not available. + * @details This function implements an atomic locking mechanism. Locks can be used in numerous ways. Two common uses + * of locks are to protect critical sections of code and to protect against duplicate resource allocation. + * For protecting critical sections of code the user would require that the code first obtain the critical section's + * lock before executing. An example of protecting against duplicate resource allocation would be if the user had two + * FIT modules that used the same peripheral. For example, the user may have one FIT module that uses the SCI + * peripheral in UART mode and another FIT module that uses the SCI peripheral in I2C mode. To make sure that both + * modules cannot use the same SCI channel, locks can be used. + * Care should be taken when using locks as they do not provide advanced features one might expect from an RTOS + * semaphore or mutex. If used improperly locks can lead to deadlock in the user's system. + * Users can override the default locking mechanisms. + */ +bool R_BSP_SoftwareLock (BSP_CFG_USER_LOCKING_TYPE * const plock) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + bool ret = false; + + /* Variable used in trying to acquire lock. Using the xchg instruction makes this atomic */ + int32_t is_locked = true; + + /* This example uses the RX MCU's atomic xchg() instruction. plock->lock is the lock we are trying to reserve. + The way this works is that 'is_locked' gets the value of the plock->lock and plock->lock gets the value of + 'is_locked' which we just set to 'true'. Basically this is an atomic 'swap' command. If the lock had not yet been + reserved then its value would be 'false' and after the xchg() instruction finished 'is_locked' would have + 'false'. If it had already been reserved then 'is_locked' would have 'true' after the xchg() instruction. Since + plock->lock was already 'true' and we just set it back to 'true' everything is ok. To see if we reserved the lock + we just need to check the value of 'is_locked' after this instruction finishes. */ + + /* Try to acquire semaphore to obtain lock */ + R_BSP_EXCHANGE(&is_locked, &plock->lock); + + /* Check to see if semaphore was successfully taken */ + if (false == is_locked) + { + /* Lock obtained, return success. */ + ret = true; + } + else + { + /* Lock was not obtained, another task already has it. */ + R_BSP_NOP(); + } + + return ret; +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(plock); +#endif +} /* End of function R_BSP_SoftwareLock() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareUnlock + ******************************************************************************************************************//** + * @brief Releases a lock. + * @param[out] plock Pointer to lock structure with lock to release. + * @retval true Successful, lock was released. Or the lock has been already released. + * @retval false Failure, lock could not be released. + * @details This function releases a lock that was previously acquired using the R_BSP_SoftwareLock() function. + */ +bool R_BSP_SoftwareUnlock (BSP_CFG_USER_LOCKING_TYPE * const plock) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Set lock back to unlocked. */ + plock->lock = false; + + return true; +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(plock); +#endif +} /* End of function R_BSP_SoftwareUnlock() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_HardwareLock + ******************************************************************************************************************//** + * @brief Attempts to reserve a hardware peripheral lock. + * @param[in] hw_index Index of lock to acquire from the hardware lock array. + * @retval true Successful, lock was available and acquired. + * @retval false Failure, lock was already acquired and is not available. + * @details This function attempts to acquire the lock for a hardware resource of the MCU. Instead of sending in a + * pointer to a lock as with the R_BSP_SoftwareLock() function, the user sends in an index to an array that holds 1 + * lock per MCU hardware resource. This array is shared amongst all FIT modules and user code therefore allowing + * multiple FIT modules (and user code) to use the same locks. The user can see the available hardware resources by + * looking at the mcu_lock_t enum in mcu_locks.h. These enum values are also the index into the hardware lock array. + * The same atomic locking mechanisms from the R_BSP_SoftwareLock() function are used with this function as well. + * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required + * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum they are not + * using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. The + * user will save 4-bytes per deleted entry. + */ +bool R_BSP_HardwareLock (mcu_lock_t const hw_index) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Pass actual lock to software lock function. */ + return R_BSP_SoftwareLock(&g_bsp_Locks[hw_index]); +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(hw_index); +#endif +} /* End of function R_BSP_HardwareLock() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_HardwareUnlock + ******************************************************************************************************************//** + * @brief Releases a hardware peripheral lock. + * @param[in] hw_index Index of lock to release from the hardware lock array. + * @retval true Successful, lock was released. + * @retval false Failure, lock could not be released. + * @details This function attempts to release the lock for a hardware resource of the MCU that was previously acquired + * using the R_BSP_HardwareLock() function. + * @note Each entry in the mcu_lock_t enum in mcu_locks.h will be allocated a lock. On RX MCUs, each lock is required + * to be 4-bytes. If RAM space is an issue then the user can remove the entries from the mcu_lock_t enum that they are + * not using. For example, if the user is not using the CRC peripheral then they could delete the BSP_LOCK_CRC entry. + * The user will save 4-bytes per deleted entry. + */ +bool R_BSP_HardwareUnlock (mcu_lock_t const hw_index) +{ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 + /* Pass actual lock to software unlock function. */ + return R_BSP_SoftwareUnlock(&g_bsp_Locks[hw_index]); +#else + /* User is going to handle the locking themselves. */ + return BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(hw_index); +#endif +} /* End of function R_BSP_HardwareUnlock() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c new file mode 100644 index 000000000..69a22da8f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.c @@ -0,0 +1,93 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_mcu_startup.c +* Description : This module implements user startup specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* Added Initialization the trigonometric function unit in R_BSP_StartupOpen function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE != 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_StartupOpen + ******************************************************************************************************************//** + * @brief Specifies settings to use the BSP and peripheral FIT modules. Call this function only when the BSP startup + * is disabled. + * @details This function performs initialization for the interrupt callback, register protection, and the hardware + * and pins. These processing are needed for using the BSP and peripheral FIT modules. Thus, this function must be + * called in the beginning of the main function. Call this function only when the BSP startup is disabled. + * @note The R_BSP_StartupOpen function performs a part of processing in the startup function. + * See Section 5.18 in the application note for more information. + */ +void R_BSP_StartupOpen (void) +{ + /* Initializes the trigonometric function unit. */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU + R_BSP_INIT_TFU(); +#endif +#endif + /* Initialize RAM. */ + bsp_ram_initialize(); + + /* Initialize MCU interrupt callbacks. */ + bsp_interrupt_open(); + + /* Initialize register protection functionality. */ + bsp_register_protect_open(); + + /* Configure the MCU and board hardware */ + hardware_setup(); +} /* End of function R_BSP_StartupOpen() */ + +#endif /* BSP_CFG_STARTUP_DISABLE != 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h new file mode 100644 index 000000000..50a8304da --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_mcu_startup.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_mcu_startup.h +* Description : This module implements user startup specific functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_STARTUP_H +#define MCU_STARTUP_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_StartupOpen(void); + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c new file mode 100644 index 000000000..203210da9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.c @@ -0,0 +1,1053 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.c +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_SWINT_TASK_BUFFER_MAX (BSP_CFG_SWINT_TASK_BUFFER_NUMBER + 1) +#define BSP_PRV_SWINT_ACCESS_ACCEPTATION (1) +#define BSP_PRV_SWINT_ACCESS_REJECTION (0) +#define BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT (1) +#define BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +st_bsp_swint_access_control_t g_bsp_swint_access_ctrl[BSP_SWINT_UNIT_MAX]; + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Interrupt functions */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint_isr, VECT(ICU, SWINT)) +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint2_isr, VECT(ICU, SWINT2)) +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + +/* Functions */ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args); +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit); +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args); +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit); +static void bsp_swint_dummy_task(void * p_dummy_context); + +/* Variables */ +static st_bsp_swint_task_t s_bsp_swint_task[BSP_SWINT_UNIT_MAX][BSP_PRV_SWINT_TASK_BUFFER_MAX]; +static uint8_t s_bsp_swint_buf_used[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_top[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_bottom[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_nested_int_status[BSP_SWINT_UNIT_MAX]; + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptOpen + ******************************************************************************************************************//** + * @brief This function initializes software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function locks the hardware, resets the access control status, clears the interrupt request (IR), + * initializes the interrupt priority level (IPR), enables nested-interrupt status, initializes the task buffer, and + * enables interrupts (IEN). + * @note This function is available only when use of software interrupts is enabled in a configuration macro. + * This function is called automatically at BSP startup when the value of BSP_CFG_SWINT_UNITn_ENABLE in r_bsp_config.h + * is 1. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + uint8_t swint_ipr; + + swint_ret = BSP_SWINT_SUCCESS; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + break; + } + + if (BSP_SWINT_SUCCESS == swint_ret) + { + if (true == lock_ret) + { + /* Reset Access Control Status */ + g_bsp_swint_access_ctrl[unit].status = BSP_PRV_SWINT_ACCESS_ACCEPTATION; + + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Set Interrupt Priority(IPR) */ + swint_ipr = BSP_CFG_SWINT_IPR_INITIAL_VALUE; + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, &swint_ipr); + + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Enable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_ENABLE_INTERRUPT, FIT_NO_PTR); + } + else + { + swint_ret = BSP_SWINT_ERR_ALREADY_OPEN; + } + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptOpen() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptClose + ******************************************************************************************************************//** + * @brief This function terminates software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function unlocks the hardware, disables interrupts (IEN), clears the interrupt request (IR), + * initializes the task buffer, and disables nested-interrupt status. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the R_BSP_SoftwareInterruptSetTask function or software interrupt function (bsp_swint_execute_task) is acquiring + * acces control rights and an interrupt is generated and this function is called within the interrupt, the task + * buffer may not be controlled correctly. If this function is used in an interrupt, clear the all task by the + * R_BSP_SoftwareInterruptControl function with the BSP_SWINT_CMD_CLEAR_ALL_TASK command before call this function. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + if (true == lock_ret) + { + swint_ret = BSP_SWINT_SUCCESS; + } + else + { + swint_ret = BSP_SWINT_ERR_NOT_CLOSED; + } + } + else + { + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptClose() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptSetTask + ******************************************************************************************************************//** + * @brief This function sets a task in the software interrupt task buffer. + * @param[in] unit Software interrupt unit + * @param[in] set_task Software interrupt task + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_TASK Invalid task pointer specified. + * @retval BSP_SWINT_ERR_FULL_BUFFER Task buffer full. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function sets the task specified by an argument in the software interrupt task buffer. After setting + * the task, the software interrupt occurs. If the task buffer is full, the task is not set. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_access_control_t access_control; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)FIT_NO_FUNC == (uint32_t)set_task.p_taskAddr) || ((uint32_t)NULL == (uint32_t)set_task.p_taskAddr)) + { + ret = BSP_SWINT_ERR_INVALID_TASK; + } + else if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_used[unit]) + { + ret = BSP_SWINT_ERR_FULL_BUFFER; + } + else + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_top[unit]) + { + s_bsp_swint_buf_top[unit] = 0; + } + else + { + s_bsp_swint_buf_top[unit]++; + } + + s_bsp_swint_buf_used[unit]++; + + /* Set Task Buffer */ + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].status = BSP_SWINT_TASK_STATUS_REQUESTED; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_taskAddr = set_task.p_taskAddr; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_context = set_task.p_context; + + ret = BSP_SWINT_SUCCESS; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptSetTask() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_interrupt_information +* Description : Get the software interrupt information. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args) +{ + st_bsp_swint_int_info_t *p_swint_int_info; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_int_info = (st_bsp_swint_int_info_t *)p_args; + + switch (unit) + { + /* Get Interrupt Information */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + p_swint_int_info->ipr = IPR(ICU, SWINT); + p_swint_int_info->ien = IEN(ICU, SWINT); + p_swint_int_info->ir = IR(ICU, SWINT); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + p_swint_int_info->ipr = IPR(ICU, SWINT2); + p_swint_int_info->ien = IEN(ICU, SWINT2); + p_swint_int_info->ir = IR(ICU, SWINT2); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_get_interrupt_information() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_interrupt +* Description : Enable interrupt. (Set the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Enable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_enable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_interrupt +* Description : Disable interrupt. (Clear the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Disable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_disable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_priority +* Description : Set interrupt priority. (Set the IPR register.) +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_INVALID_IPR - Overflow interrupt priority. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_ipr; + uint8_t ien; + bsp_int_ctrl_t int_ctrl; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_ipr = (uint8_t *)p_args; + + /* Check Interrupt Priority */ + if (BSP_MCU_IPL_MAX < (*p_swint_ipr)) + { + ret = BSP_SWINT_ERR_INVALID_IPR; + } + else + { + /* Set IPL to the maximum value to disable all interrupts*/ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + switch (unit) + { + /* Set Interrupt Priority */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ien = IEN(ICU, SWINT); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ien = IEN(ICU, SWINT2); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT2) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + /* Restore the IPL */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + + ret = BSP_SWINT_SUCCESS; + } + + return ret; +} /* End of function bsp_swint_set_interrupt_priority() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_request +* Description : Set interrupt request. (Set the SWINTR register.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Set Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ICU.SWINTR.BIT.SWINT = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ICU.SWINT2R.BIT.SWINT2 = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_set_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_interrupt_request +* Description : Clear interrupt request. (Clear the IR bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Clear Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + IR(ICU, SWINT) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + IR(ICU, SWINT2) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_clear_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_nested_interrupt +* Description : Set nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_enable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_nested_interrupt +* Description : Clear nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_disable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_task +* Description : Clear the task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +* BSP_SWINT_ERR_INVALID_BUFFER_NUMBER - Set invalid buffer number. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_task_buffer_t *p_swint_task_buffer; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task_buffer = (st_bsp_swint_task_buffer_t *)p_args; + + if (BSP_PRV_SWINT_TASK_BUFFER_MAX > p_swint_task_buffer->number) + { + /* Clear Task Buffer */ + if (BSP_SWINT_TASK_STATUS_EXECUTING != s_bsp_swint_task[unit][p_swint_task_buffer->number].status) + { + s_bsp_swint_task[unit][p_swint_task_buffer->number].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_context = FIT_NO_PTR; + ret = BSP_SWINT_SUCCESS; + } + else + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_BUFFER_NUMBER; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_all_task +* Description : Clear the all task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit) +{ + e_bsp_swint_err_t ret; + uint8_t buf_num; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + ret = BSP_SWINT_SUCCESS; + + /* Check Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][buf_num].status) + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + break; + } + } + + if (BSP_SWINT_SUCCESS == ret) + { + /* Clear ALL Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } + else + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_all_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_all_task_status +* Description : Get the task status of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args) +{ + uint8_t buf_num; + st_bsp_swint_task_t *p_swint_task; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task = (st_bsp_swint_task_t *)p_args; + + /* Clear Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + p_swint_task->status = s_bsp_swint_task[unit][buf_num].status; + p_swint_task->p_taskAddr = s_bsp_swint_task[unit][buf_num].p_taskAddr; + p_swint_task->p_context = s_bsp_swint_task[unit][buf_num].p_context; + p_swint_task++; + } +} /* End of function bsp_swint_get_all_task_status() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptControl + ******************************************************************************************************************//** + * @brief This function controls software interrupts. + * @param[in] unit Software interrupt unit + * @param[in] cmd Software interrupt control command + * @param[in, out] p_args Pointer to arguments for software interrupt control commands. Set the argument type to match + * each software interrupt control command. For commands that do not require arguments, use the setting FIT_NO_PTR. + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_IPR Invalid interrupt priority level specified. + * @retval BSP_SWINT_ERR_INVALID_CMD Invalid command specified. + * @retval BSP_SWINT_ERR_INVALID_BUFFER_NUMBER Invalid task buffer number specified. + * @retval BSP_SWINT_ERR_TASK_EXECUTING Attempt to manipulate a task that is running. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function performs software interrupt control in response to commands. Refer the application note for + * the operation of each command. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * Do not change the interrupt priority level (IPR) while a software interrupt is being processed.\n + * When the BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY command is run, interrupts are disabled temporarily in order to set + * the interrupt priority level (IPR).\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right.\n + * If a software interrupt is generated while this function has the access control right, the software interrupt + * cannot obtain the access control right and interrupt processing ends with the task remaining unexecuted. For this + * reason, after returning from a software interrupt the interrupt request is cleared regardless of whether a task has + * been set in the task buffer. To avoid this, setting of the interrupt request occurs at the end of the processing of + * the BSP_SWINT_CMD_CLEAR_TASK and BSP_SWINT_CMD_CLEAR_ALL_TASK commands. Nevertheless, since all task buffers are + * cleared when processing of the BSP_SWINT_CMD_CLEAR_ALL_TASK command completes successfully, the interrupt request + * is not set. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + ret = BSP_SWINT_SUCCESS; + + /* Execute Command */ + switch (cmd) + { + case BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION: + bsp_swint_get_interrupt_information(unit, p_args); + break; + + case BSP_SWINT_CMD_ENABLE_INTERRUPT: + bsp_swint_enable_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_INTERRUPT: + bsp_swint_disable_interrupt(unit); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY: + ret = bsp_swint_set_interrupt_priority(unit, p_args); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_REQUEST: + bsp_swint_set_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST: + bsp_swint_clear_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT: + bsp_swint_enable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT: + bsp_swint_disable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_CLEAR_TASK: + ret = bsp_swint_clear_task(unit, p_args); + break; + + case BSP_SWINT_CMD_CLEAR_ALL_TASK: + ret = bsp_swint_clear_all_task(unit); + break; + + case BSP_SWINT_CMD_GET_ALL_TASK_STATUS: + bsp_swint_get_all_task_status(unit, p_args); + break; + + case BSP_SWINT_CMD_GET_USED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)s_bsp_swint_buf_used[unit]; + break; + + case BSP_SWINT_CMD_GET_UNUSED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)(BSP_CFG_SWINT_TASK_BUFFER_NUMBER - s_bsp_swint_buf_used[unit]); + break; + + default: + ret = BSP_SWINT_ERR_INVALID_CMD; + break; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_access_control +* Description : Get access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Get access. +* false - Failed to get access. +***********************************************************************************************************************/ +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Get Access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == p_args->status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_get_access_control() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_release_access_control +* Description : Release access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Release access. +* false - Failed to release access. +***********************************************************************************************************************/ +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Release access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == g_bsp_swint_access_ctrl[unit].status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_release_access_control() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_dummy_task +* Description : Dummy task. +* Arguments : p_dummy_context - Dummy arguments. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_dummy_task(void * p_dummy_context) +{ + R_BSP_NOP(); +} /* End of function bsp_swint_dummy_task() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_execute_task +* Description : Execute task of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit) +{ + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Enable Multiple Interrupt */ + if (BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT == s_bsp_swint_nested_int_status[unit]) + { + R_BSP_InterruptsEnable(); + } + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + /* WAIT_LOOP */ + while (0 != s_bsp_swint_buf_used[unit]) + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_bottom[unit]) + { + s_bsp_swint_buf_bottom[unit] = 0; + } + else + { + s_bsp_swint_buf_bottom[unit]++; + } + + if (BSP_SWINT_TASK_STATUS_REQUESTED == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "EXECUTING" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_EXECUTING; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Execute Task */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_taskAddr(s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_context); + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "COMPLETED" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_COMPLETED; + } + } + + if (0 != s_bsp_swint_buf_used[unit]) + { + s_bsp_swint_buf_used[unit]--; + } + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } +} /* End of function bsp_swint_execute_task() */ + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint_isr +* Description : Software interrupt function. (Unit1) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT1); +} /* End of function bsp_swint_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint2_isr +* Description : Software interrupt function. (Unit2) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint2_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT2); +} /* End of function bsp_swint2_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h new file mode 100644 index 000000000..0ce9ba056 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_bsp_software_interrupt.h @@ -0,0 +1,138 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.h +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* Multiple inclusion prevention macro */ +#ifndef SOFTWARE_INTERRUPT_H +#define SOFTWARE_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +typedef enum e_bsp_swint_unit +{ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + BSP_SWINT_UNIT1, +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + BSP_SWINT_UNIT2, +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + BSP_SWINT_UNIT_MAX +} e_bsp_swint_unit_t; + +typedef enum e_bsp_swint_err +{ + BSP_SWINT_SUCCESS = 0, + BSP_SWINT_ERR_ALREADY_OPEN, + BSP_SWINT_ERR_NOT_CLOSED, + BSP_SWINT_ERR_INVALID_UNIT, + BSP_SWINT_ERR_INVALID_IPR, + BSP_SWINT_ERR_INVALID_CMD, + BSP_SWINT_ERR_INVALID_TASK, + BSP_SWINT_ERR_INVALID_BUFFER_NUMBER, + BSP_SWINT_ERR_TASK_EXECUTING, + BSP_SWINT_ERR_FULL_BUFFER, + BSP_SWINT_ERR_ACCESS_REJECTION +} e_bsp_swint_err_t; + +typedef enum e_bsp_swint_cmd +{ + BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION = 0, + BSP_SWINT_CMD_ENABLE_INTERRUPT, + BSP_SWINT_CMD_DISABLE_INTERRUPT, + BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, + BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, + BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, + BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_CLEAR_TASK, + BSP_SWINT_CMD_CLEAR_ALL_TASK, + BSP_SWINT_CMD_GET_ALL_TASK_STATUS, + BSP_SWINT_CMD_GET_USED_BUFFER, + BSP_SWINT_CMD_GET_UNUSED_BUFFER +} e_bsp_swint_cmd_t; + +typedef struct st_bsp_swint_int_info +{ + uint8_t ipr; + uint8_t ien; + uint8_t ir; + uint8_t nested_int; +} st_bsp_swint_int_info_t; + +typedef enum e_bsp_swint_task_status +{ + BSP_SWINT_TASK_STATUS_NO_REQUEST = 0, + BSP_SWINT_TASK_STATUS_REQUESTED, + BSP_SWINT_TASK_STATUS_EXECUTING, + BSP_SWINT_TASK_STATUS_COMPLETED +} e_bsp_swint_task_status_t; + +typedef struct st_bsp_swint_task +{ + e_bsp_swint_task_status_t status; + void (*p_taskAddr)(void *p_task_args); + void *p_context; +} st_bsp_swint_task_t; + +typedef struct st_bsp_swint_task_buffer +{ + uint8_t number; +} st_bsp_swint_task_buffer_t; + +typedef struct st_bsp_swint_access_control +{ + int32_t status; +} st_bsp_swint_access_control_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task); +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args); + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rtos.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rtos.h new file mode 100644 index 000000000..6d4d8268d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rtos.h @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rtos.h +* Description : This module implements functions of rtos. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.10 Added include file and macro definitions for Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_config.h" + +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ +#elif BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "queue.h" +#include "croutine.h" +#include "timers.h" +#include "event_groups.h" +#include "freertos_start.h" +#elif BSP_CFG_RTOS_USED == 2 /* SEGGER embOS */ +#elif BSP_CFG_RTOS_USED == 3 /* Micrium MicroC/OS */ +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#include "kernel.h" +#include "kernel_id.h" + +#define RENESAS_RI600V4 0 +#define RENESAS_RI600PX 1 + +#undef BSP_CFG_RTOS_SYSTEM_TIMER +#define BSP_CFG_RTOS_SYSTEM_TIMER _RI_CLOCK_TIMER +#else +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RTOS_H +#define R_RTOS_H + +#endif /* R_RTOS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h new file mode 100644 index 000000000..d03359072 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_compiler.h @@ -0,0 +1,1638 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_compiler.h +* Description : This is a file for integrating the definitions of different functions for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.01 Modified definition of __RX_DPFPU_INSNS__ to __RX_DFPU_INSNS__ for GNUC. +* Modified definition of TFU for GNUC. +* Modified comment of TFU for ICCRX. +* Added include of r_bsp_config.h. +* Changed the following definitions for added support of Renesas RTOS(RI600V4 or RI600PX). +* - R_BSP_SECNAME_INTVECTTBL +* - R_BSP_SECNAME_EXCEPTVECTTBL +* - R_BSP_SECNAME_FIXEDVECTTBL +* - R_BSP_PRAGMA_INTERRUPT +* - R_BSP_PRAGMA_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_FUNCTION +* - R_BSP_ATTRIB_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_DEFAULT +* - R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT +* Changed the following definitions to definition without __no_init for ICCRX so that +* there is no warning when the initial value is specified. +* - _R_BSP_ATTRIB_SECTION_CHANGE_C1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C8 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D8 +* : 17.12.2019 1.02 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_common.h" +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_COMPILER_H +#define R_RX_COMPILER_H + +/* ========== Check Compiler ========== */ +#if defined(__CCRX__) + /* supported */ +#elif defined(__GNUC__) + /* supported */ +#elif defined(__ICCRX__) + /* supported */ +#else + #error "Unrecognized compiler" +#endif + + +/* ========== Macros ========== */ +#if defined(__CCRX__) + +/* #define __RX 1 */ /* This is automatically defined by CCRX. */ +/* #define __LIT 1 */ /* This is automatically defined by CCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by CCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by CCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by CCRX. */ +/* #define __DPFPU 1 */ /* This is automatically defined by CCRX. */ + +#elif defined(__GNUC__) + +#if !defined(__RX) +#define __RX 1 +#endif + +#if defined(__RX_LITTLE_ENDIAN__) +#if !defined(__LIT) +#define __LIT 1 +#endif +#elif defined(__RX_BIG_ENDIAN__) +#if !defined(__BIG) +#define __BIG 1 +#endif +#endif + +#if defined(__RX_FPU_INSNS__) +#if !defined(__FPU) +#define __FPU 1 +#endif +#endif + +#if defined(__RXv1__) +#if !defined(__RXV1) +#define __RXV1 1 +#endif +#endif + +#if defined(__RXv2__) +#if !defined(__RXV2) +#define __RXV2 1 +#endif +#endif + +#if defined(__RXv3__) +#if !defined(__RXV3) +#define __RXV3 1 +#endif +#endif + +/* #define __TFU 1 */ /* This is automatically defined by GNUC. */ + +#if defined(__RX_DFPU_INSNS__) +#if !defined(__DPFPU) +#define __DPFPU 1 +#endif +#endif + +#elif defined(__ICCRX__) + +#if !defined(__RX) +#define __RX 1 +#endif + +/* #define __LIT 1 */ /* This is automatically defined by ICCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by ICCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by ICCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __DPFPU 1 */ /* Not yet supported. */ + +#endif + + +/* ========== Keywords ========== */ +#if !(defined(__CCRX__) && defined(__cplusplus)) +#define R_BSP_PRAGMA(...) _Pragma(#__VA_ARGS__) +#else +/* CC-RX' C++ mode does not support Pragma operator and variadic macros */ +#define R_BSP_PRAGMA(x) +#endif + +#if defined(__CCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile __evenaccess +#define R_BSP_EVENACCESS __evenaccess +#define R_BSP_EVENACCESS_SFR __evenaccess +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS /* none */ +#define R_BSP_EVENACCESS_SFR /* none */ +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__ICCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS volatile +#define R_BSP_EVENACCESS_SFR __sfr +#define R_BSP_VOLATILE_SFR volatile __sfr +#define R_BSP_SFR __sfr + +#endif + + +/* ========== Sections ========== */ + +/* ---------- Operators ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP(name) __sectop(#name) +#define R_BSP_SECEND(name) __secend(#name) +#define R_BSP_SECSIZE(name) __secsize(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP(name) ((void *)name##_start) +#define R_BSP_SECEND(name) ((void *)name##_end) +#define R_BSP_SECSIZE(name) ((size_t)((uint8_t *)R_BSP_SECEND(name) - (uint8_t *)R_BSP_SECTOP(name))) + +#define R_BSP_SECTION_OPERATORS_INIT(name) extern uint8_t name##_start[], name##_end[]; + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP(name) __section_begin(#name) +#define R_BSP_SECEND(name) __section_end(#name) +#define R_BSP_SECSIZE(name) __section_size(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) R_BSP_PRAGMA(section = #name); + +#endif + +/* ---------- Names ---------- */ +#if defined(__CCRX__) + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_INTVECTTBL "INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_INTVECTTBL "C$VECT" +#endif /* BSP_CFG_RTOS_USED */ + +#if defined(__RXV2) || defined(__RXV3) +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "EXCEPTVECT" +#endif /* BSP_CFG_RTOS_USED */ +#define R_BSP_SECNAME_RESETVECT "RESETVECT" +#else /* __RXV1 */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIXEDVECT" +#endif /* BSP_CFG_RTOS_USED */ +#endif /* defined(__RXV2) || defined(__RXV3) */ +#define R_BSP_SECNAME_UBSETTINGS "UBSETTINGS" + +#elif defined(__GNUC__) + +#define R_BSP_SECNAME_INTVECTTBL ".rvectors" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exvectors" +#define R_BSP_SECNAME_RESETVECT ".fvectors" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".fvectors" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#elif defined(__ICCRX__) + +#define R_BSP_SECNAME_INTVECTTBL ".inttable" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exceptvect" +#define R_BSP_SECNAME_RESETVECT ".resetvect" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".exceptvect" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#endif + +/* ---------- Addresses ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP_INTVECTTBL __sectop(R_BSP_SECNAME_INTVECTTBL) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL __sectop(R_BSP_SECNAME_EXCEPTVECTTBL) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP_INTVECTTBL ((void *)rvectors_start) +extern void * const rvectors_start[]; +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL ((void *)exvectors_start) +extern void * const exvectors_start[]; +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP_INTVECTTBL /* none */ +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL /* none */ +#endif + +#endif + + +/* ========== #pragma Directive ========== */ + +/* ---------- Stack Size ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(_size) _R_BSP_PRAGMA_STACKSIZE_SI(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SI(_size) __R_BSP_PRAGMA_STACKSIZE_SI##_size +#define __R_BSP_PRAGMA_STACKSIZE_SI(size) R_BSP_PRAGMA(stacksize si=size) +#define R_BSP_PRAGMA_STACKSIZE_SU(_size) _R_BSP_PRAGMA_STACKSIZE_SU(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SU(_size) __R_BSP_PRAGMA_STACKSIZE_SU##_size +#define __R_BSP_PRAGMA_STACKSIZE_SU(size) R_BSP_PRAGMA(stacksize su=size) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) static uint8_t istack_area[size] __attribute__((section(".r_bsp_istack"), used)); +#define R_BSP_PRAGMA_STACKSIZE_SU(size) static uint8_t ustack_area[size] __attribute__((section(".r_bsp_ustack"), used)); + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) /* none */ +#define R_BSP_PRAGMA_STACKSIZE_SU(size) /* none */ + +#endif + +/* ---------- Section Switch (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(section C UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT R_BSP_PRAGMA(section C EXCEPTVECT) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT R_BSP_PRAGMA(section C RESETVECT) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT R_BSP_PRAGMA(section C FIXEDVECT) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS __attribute__((section(R_BSP_SECNAME_UBSETTINGS))) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT __attribute__((section(R_BSP_SECNAME_EXCEPTVECTTBL))) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT __attribute__((section(R_BSP_SECNAME_RESETVECT))) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT __attribute__((section(R_BSP_SECNAME_FIXEDVECTTBL))) +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(location=R_BSP_SECNAME_UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT /* none */ +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT /* none */ +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT /* none */ +#endif +#endif + +/* ---------- Section Switch (part2) ---------- */ +#if defined(__CCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(type, section_name) R_BSP_PRAGMA(section type section_name) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(type, section_name) R_BSP_PRAGMA(section type section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P, P##section_tag) + +#if !defined(__cplusplus) +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#else +/* CC-RX' C++ mode does not support variadic macros */ +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, align) _R_BSP_ATTRIB_SECTION_CHANGE_##type##align(section_tag) +#endif + +#define R_BSP_ATTRIB_SECTION_CHANGE_END R_BSP_PRAGMA(section) + +#elif defined(__GNUC__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) __attribute__((section(#section_name))) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) __attribute__((section(#section_name))) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#elif defined(__ICCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) R_BSP_PRAGMA(location=#section_name)\ + __no_init +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) R_BSP_PRAGMA(location=#section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#endif + +/* ---------- Interrupt Function Creation ---------- */ +#if defined(__CCRX__) + +/* Standard */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void); + +#else /* BSP_CFG_RTOS_USED != 4*/ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + static void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because of no corresponding keyword */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT +#else /* BSP_CFG_RTOS_USED !=4 */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because of no corresponding keyword */ +#endif /* BSP_CFG_RTOS_USED */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + static void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + static void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* only this one because of no corresponding keyword */ + +/* Default */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) void function_name(void); +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#elif defined(__GNUC__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((interrupt)); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((interrupt, used)); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because __attribute__((interrupt)) prevents GNURX from generating vector */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because __attribute__((interrupt, used)) prevents GNURX from generating vector */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))) \ + __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)) \ + __attribute__((fast_interrupt, used)); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((fast_interrupt, used)); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* __attribute__((interrupt(fast))) Not necessary, + but Don't forget a R_BSP_PRAGMA_FAST_INTERRUPT() declaration */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* __attribute__((interrupt(fast)), used) Not necessary, + but Don't forget a R_BSP_PRAGMA_STATIC_FAST_INTERRUPT() declaration */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"), used)); + +#elif defined(__ICCRX__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __interrupt void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static __interrupt void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __fast_interrupt void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static __fast_interrupt void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static __interrupt void function_name(void); + +#endif + +/* ---------- Inline Expansion of Function ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + static + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_INLINE(function_name) inline extern __attribute__((always_inline)) +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) inline static __attribute__((always_inline)) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + static + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__GNUC__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) extern __attribute__((naked, noinline)) +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) static __attribute__((naked, noinline)) + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__ICCRX__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* ICCRX requires __task not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* ICCRX requires __task not only at a function declaration but also at a function definition */ + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part2) ---------- */ +#if defined(__CDT_PARSER__) + +#define R_BSP_ASM(...) /* none */ +#define R_BSP_ASM_LAB_NEXT(n) /* none */ +#define R_BSP_ASM_LAB_PREV(n) /* none */ +#define R_BSP_ASM_LAB(n_colon) /* none */ +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#else + +#if defined(__CCRX__) + +#if !defined(__cplusplus) +#define R_BSP_ASM(...) __VA_ARGS__ +#else +/* CC-RX' C++ mode does not support variadic macros */ +#endif +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#elif defined(__GNUC__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN __asm__ volatile ( +#define R_BSP_ASM_END R_BSP_ASM(rts)); + +#elif defined(__ICCRX__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) _lab##n +#define R_BSP_ASM_LAB_PREV(n) _lab##n +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) +#define R_BSP_ASM_BEGIN asm( +#define R_BSP_ASM_END ); + +#endif + +#endif /* defined(__CDT_PARSER__) */ + +/* ---------- Inline Expansion of Assembly-Language Function (part3) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) /* no way */ +#define R_BSP_ASM_INTERNAL_NOT_USED(p) /* no way */ + +#elif defined(__GNUC__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#elif defined(__ICCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#endif + +/* ---------- Bit Field Order Specification ---------- */ + +/* ---------- bit_order=left ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order left)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=reversed_disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- bit_order=right ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order right)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- Alignment Value Specification for Structure Members and Class Members ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(unpack) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(packoption) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#endif + +/* ========== Rename Functions ========== */ + +#if defined(__CCRX__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ + +#elif defined(__GNUC__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC_Prg + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ + +#elif defined(__ICCRX__) + +#define R_BSP_POR_FUNCTION(name) extern int name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION _iar_program_start +#define R_BSP_STARTUP_FUNCTION __low_level_init + +#define R_BSP_UB_POR_FUNCTION(name) extern int name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION _iar_program_start + +#define R_BSP_MAIN_FUNCTION _iar_main_call + +#define _INITSCT __iar_data_init2 +#define excep_supervisor_inst_isr __privileged_handler +#define excep_access_isr __excep_access_inst +#define excep_undefined_inst_isr __undefined_handler +#define excep_floating_point_isr _float_placeholder +#define non_maskable_isr __NMI_handler +#define undefined_interrupt_source_isr __undefined_interrupt_source_handler + +#endif + +#endif /* R_RX_COMPILER_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c new file mode 100644 index 000000000..d344aed03 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.c @@ -0,0 +1,994 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.c +* Description : Defines built-in functions that are in CCRX but not in the GCC and IAR compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.01 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* Added the below functions. +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.02 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 10.12.2019 1.03 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* : 17.12.2019 1.04 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_rx_compiler.h" +#include "r_rx_intrinsic_functions.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpc(uint32_t *data); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_extb(uint32_t *data); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_hi_long(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_mi_long(uint32_t *data); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_dpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_decnt(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_depc(uint32_t *ret); +#endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_BSP_Max +* Description : Selects the greater of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The greater value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2) +{ + return (data1 > data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_Min +* Description : Selects the smaller of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The smaller value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Min(signed long data1, signed long data2) +{ + return (data1 < data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_B +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_W +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_L +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeftWithCarry +* Description : Rotates data including the C flag to left by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* Return Value : data - Result of 1-bit left rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) +{ + __asm("rolc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRightWithCarry +* Description : Rotates data including the C flag to right by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* Return Value : data - Result of 1-bit right rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRightWithCarry(unsigned long data) +{ + __asm("rorc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeft +* Description : Rotates data to left by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* num - Number of bits to be rotated. +* Return Value : data - Result of num-bit left rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) +{ + __asm("rotl %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRight +* Description : Rotates data to right by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* num - Number of bits to be rotated. +* Return Value : result - Result of num-bit right rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num) +{ + __asm("rotr %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SignedMultiplication +* Description : Performs signed multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of signed multiplication. (signed 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) +{ + return ((signed long long)data1) * ((signed long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_UnsignedMultiplication +* Description : Performs unsigned multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of unsigned multiplication. (unsigned 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) +{ + return ((unsigned long long)data1) * ((unsigned long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function name: R_BSP_ChangeToUserMode +* Description : Switches to user mode. The PSW will be changed as following. +* Before Execution After Execution +* PSW.PM PSW.U PSW.PM PSW.U +* 0 (supervisor mode) 0 (interrupt stack) --> 1 (user mode) 1 (user stack) +* 0 (supervisor mode) 1 (user stack) --> 1 (user mode) 1 (user stack) +* 1 (user mode) 1 (user stack) --> NO CHANGE +* 1 (user mode) 0 (interrupt stack)) <== N/A +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_ChangeToUserMode) +void R_BSP_ChangeToUserMode(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM(;_R_BSP_Change_PSW_PM_to_UserMode: ) + R_BSP_ASM( PUSH.L R1 ; push the R1 value ) + R_BSP_ASM( MVFC PSW, R1 ; get the current PSW value ) + R_BSP_ASM( BTST #20, R1 ; check PSW.PM ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_NEXT(0);_psw_pm_is_user_mode ) + R_BSP_ASM(;_psw_pm_is_supervisor_mode: ) + R_BSP_ASM( BSET #20, R1 ; change PM = 0(Supervisor Mode) --> 1(User Mode) ) + R_BSP_ASM( PUSH.L R2 ; push the R2 value ) + R_BSP_ASM( MOV.L R0, R2 ; move the current SP value to the R2 value ) + R_BSP_ASM( XCHG 8[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the return address value of caller and the PSW value) ) + R_BSP_ASM( XCHG 4[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the R1 value of stack and the return address value of caller) ) + R_BSP_ASM( POP R2 ; pop the R2 value of stack ) + R_BSP_ASM( RTE ) + R_BSP_ASM_LAB(0:;_psw_pm_is_user_mode: ) + R_BSP_ASM( POP R1 ; pop the R1 value of stack ) + R_BSP_ASM( ;RTS ) + R_BSP_ASM_END +} /* End of function R_BSP_ChangeToUserMode() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetACC +* Description : Sets a value to ACC. +* Arguments : data - Value to be set to ACC. +* Return Value : none +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +void R_BSP_SetACC(signed long long data) +{ +#if defined(__GNUC__) + __builtin_rx_mvtachi(data >> 32); + __builtin_rx_mvtaclo(data & 0xFFFFFFFF); +#elif defined(__ICCRX__) + int32_t data_hi; + int32_t data_lo; + + data_hi = (int32_t)(data >> 32); + data_lo = (int32_t)(data & 0x00000000FFFFFFFF); + + R_BSP_MoveToAccHiLong(data_hi); + R_BSP_MoveToAccLoLong(data_lo); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetACC +* Description : Refers to the ACC value. +* Arguments : none +* Return Value : result - ACC value. +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_GetACC(void) +{ +#if defined(__GNUC__) + signed long long result = ((signed long long)__builtin_rx_mvfachi()) << 32; + result |= (((signed long long)__builtin_rx_mvfacmi()) << 16) & 0xFFFF0000; + return result; +#elif defined(__ICCRX__) + int64_t result; + + result = ((int64_t)R_BSP_MoveFromAccHiLong()) << 32; + result |= (((int64_t)R_BSP_MoveFromAccMiLong()) << 16) & 0xFFFF0000; + + return result; +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_2byte +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* four bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, the contents of ACC are +* fetched by the MVFACMI instruction and used as the return value of the intrinsic function. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : S(data1[n] * data2[n]) result. +***********************************************************************************************************************/ +#if defined(__GNUC__) +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + return __builtin_rx_mvfacmi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint1 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* The macw1 function performs rounding with the "RACW #1" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(1); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint2 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* the macw2 function performs rounding with the "RACW #2" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(2); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPSW +* Description : Sets a value to BPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPSW) +void R_BSP_SetBPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpsw +* Description : Refers to the BPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpsw) +void bsp_get_bpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPSW +* Description : Refers to the BPSW value. +* Arguments : none +* Return Value : BPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetBPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPC +* Description : Sets a value to BPC. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPC) +void R_BSP_SetBPC(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPC ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPC() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpc +* Description : Refers to the BPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpc) +void bsp_get_bpc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpc() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPC +* Description : Refers to the BPC value. +* Arguments : none +* Return Value : BPC value +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetBPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpc((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetBPC() */ + +#ifdef BSP_MCU_EXCEPTION_TABLE +/*********************************************************************************************************************** +* Function Name: R_BSP_SetEXTB +* Description : Sets a value for EXTB. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetEXTB) +void R_BSP_SetEXTB(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, EXTB ) + R_BSP_ASM_END +} /* End of function R_BSP_SetEXTB() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_extb +* Description : Refers to the EXTB value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_extb) +void bsp_get_extb(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC EXTB, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_extb() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetEXTB +* Description : Refers to the EXTB value. +* Arguments : none +* Return Value : EXTB value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetEXTB(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_extb((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetEXTB() */ +#endif /* BSP_MCU_EXCEPTION_TABLE */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccHiLong +* Description : This function moves the contents of src to the higher-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccHiLong) +void R_BSP_MoveToAccHiLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACHI R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccLoLong +* Description : This function moves the contents of src to the lower-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccLoLong) +void R_BSP_MoveToAccLoLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACLO R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccLoLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_hi_long +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_hi_long) +void bsp_move_from_acc_hi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACHI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_hi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccHiLong +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : none +* Return Value : The higher-order 32 bits of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccHiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_hi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_mi_long +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_mi_long) +void bsp_move_from_acc_mi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACMI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_mi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccMiLong +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : none +* Return Value : The contents of bits 47 to 16 of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccMiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_mi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccMiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitSet +* Description : Sets the specified one bit in the specified 1-byte area to 1. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitSet) +void R_BSP_BitSet(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BSET R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitSet() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitClear +* Description : Sets the specified one bit in the specified 1-byte area to 0. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitClear) +void R_BSP_BitClear(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BCLR R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitClear() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitReverse +* Description : Reverses the value of the specified one bit in the specified 1-byte area. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitReverse) +void R_BSP_BitReverse(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BNOT R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitReverse() */ + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDPSW +* Description : Sets a value to DPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDPSW) +void R_BSP_SetDPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_dpsw +* Description : Refers to the DPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_dpsw) +void bsp_get_dpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_dpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDPSW +* Description : Refers to the DPSW value. +* Arguments : none +* Return Value : DPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_dpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDECNT +* Description : Sets a value to DECNT. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDECNT) +void R_BSP_SetDECNT(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DECNT ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_decnt +* Description : Refers to the DECNT value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_decnt) +void bsp_get_decnt(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DECNT, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDECNT +* Description : Refers to the DECNT value. +* Arguments : none +* Return Value : DECNT value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDECNT(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_decnt((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_depc +* Description : Refers to the DEPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_depc) +void bsp_get_depc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DEPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDEPC +* Description : Refers to the DEPC value. +* Arguments : none +* Return Value : DEPC value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetDEPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_depc((uint32_t *)&ret); + return (void *)ret; +} /* End of function R_BSP_GetDECNT() */ +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +/*********************************************************************************************************************** +* Function Name: R_BSP_InitTFU +* Description : Initialize arithmetic unit for trigonometric functions. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_InitTFU) +void R_BSP_InitTFU(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R1 ) + R_BSP_ASM( MOV.L #81400H, R1 ) + R_BSP_ASM( MOV.B #7, [R1] ) + R_BSP_ASM( MOV.B #7, 1[R1] ) + R_BSP_ASM( POP R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_InitTFU() */ + +#ifdef __FPU +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSine_Cosine +* Description : Uses the trigonometric function unit to calculate the sine and cosine of an angle at the same time +* (single precision). +* Arguments : f - Value in radians from which to calculate the sine and cosine +* : sin - Address for storing the result of the sine operation +* : cos - Address for storing the result of the cosine operation +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcSine_Cosine) +void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R4 ) + R_BSP_ASM( MOV.L #81410H, R4 ) + R_BSP_ASM( MOV.L R1, 4[R4] ) + R_BSP_ASM( MOV.L 4[R4], [R2] ) + R_BSP_ASM( MOV.L [R4], [R3] ) + R_BSP_ASM( POP R4 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcSine_Cosine() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcAtan_SquareRoot +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of +* the sum of squares of these values at the same time (single precision). +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* atan2 - Address for storing the result of the arc tangent operation for y/x +* hypot - Address for storing the result of the square root of the sum of squares of x and y +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcAtan_SquareRoot) +void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSHM R5-R6 ) + R_BSP_ASM( MOV.L #81418H, R5 ) + R_BSP_ASM( MOV.L R2, [R5] ) + R_BSP_ASM( MOV.L R1, 4[R5] ) + R_BSP_ASM( MOV.L 4[R5], [R3] ) + R_BSP_ASM( MOV.L [R5], R6 ) + R_BSP_ASM( FMUL #3F1B74EEH, R6 ) + R_BSP_ASM( MOV.L R6, [R4] ) + R_BSP_ASM( POPM R5-R6 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcAtan_SquareRoot() */ +#endif /* __FPU */ +#endif /* __TFU */ +#endif /* BSP_MCU_TRIGONOMETRIC */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h new file mode 100644 index 000000000..1f418eaa4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_rx_intrinsic_functions.h @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.h +* Description : This is a file for integrating the definitions of built-in functions that differ for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.10 Added the following function. +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.11 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 08.10.2019 1.12 Modified the followind definition of intrinsic function of TFU for ICCRX. +* - R_BSP_INIT_TFU +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* : 17.12.2019 1.13 Modified the comment of description. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_INTRINSIC_FUNCTIONS_H +#define R_RX_INTRINSIC_FUNCTIONS_H + +/* ---------- Maximum value and minimum value ---------- */ +#if defined(__CCRX__) + +/* signed long max(signed long data1, signed long data2) */ +#define R_BSP_MAX(x, y) max((signed long)(x), (signed long)(y)) +/* signed long min(signed long data1, signed long data2) */ +#define R_BSP_MIN(x, y) min((signed long)(x), (signed long)(y)) + +#elif defined(__GNUC__) + +/* signed long R_BSP_Max(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MAX(x, y) R_BSP_Max((signed long)(x), (signed long)(y)) +/* signed long R_BSP_Min(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MIN(x, y) R_BSP_Min((signed long)(x), (signed long)(y)) + +#elif defined(__ICCRX__) + +/* signed long __MAX(signed long, signed long) */ +#define R_BSP_MAX(x, y) __MAX((signed long)(x), (signed long)(y)) +/* signed long __MIN(signed long, signed long) */ +#define R_BSP_MIN(x, y) __MIN((signed long)(x), (signed long)(y)) + +#endif + +/* ---------- Byte switch ---------- */ +#if defined(__CCRX__) + +/* unsigned long revl(unsigned long data) */ +#define R_BSP_REVL(x) revl((unsigned long)(x)) +/* unsigned long revw(unsigned long data) */ +#define R_BSP_REVW(x) revw((unsigned long)(x)) + +#elif defined(__GNUC__) + +/* uint32_t __builtin_bswap32(uint32_t x) */ +#define R_BSP_REVL(x) __builtin_bswap32((uint32_t)(x)) +/* int __builtin_rx_revw(int) */ +#define R_BSP_REVW(x) (unsigned long)__builtin_rx_revw((int)(x)) + +#elif defined(__ICCRX__) + +/* unsigned long __REVL(unsigned long) */ +#define R_BSP_REVL(x) __REVL((unsigned long)(x)) +/* unsigned long __REVW(unsigned long) */ +#define R_BSP_REVW(x) __REVW((unsigned long)(x)) + +#endif + +/* ---------- Data Exchange ---------- */ +#if defined(__CCRX__) + +/* void xchg(signed long *data1, signed long *data2) */ +#define R_BSP_EXCHANGE(x, y) xchg((signed long *)(x), (signed long *)(y)) + +#elif defined(__GNUC__) + +/* void __builtin_rx_xchg (int *, int *) */ +#define R_BSP_EXCHANGE(x, y) __builtin_rx_xchg((int *)(x), (int *)(y)) + +#elif defined(__ICCRX__) + +/* void _builtin_xchg(signed long *, signed long *) */ +#define R_BSP_EXCHANGE(x, y) _builtin_xchg((signed long *)(x), (signed long *)(y)) + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__GNUC__) + +/* long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAB(w, x, y, z) R_BSP_MulAndAccOperation_B((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAW(w, x, y, z) R_BSP_MulAndAccOperation_W((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAL(w, x, y, z) R_BSP_MulAndAccOperation_L((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__ICCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#endif + +/* ---------- Rotation ---------- */ +#if defined(__CCRX__) + +/* unsigned long rolc(unsigned long data) */ +#define R_BSP_ROLC(x) rolc((unsigned long)(x)) +/* unsigned long rorc(unsigned long data) */ +#define R_BSP_RORC(x) rorc((unsigned long)(x)) +/* unsigned long rotl(unsigned long data, unsigned long num) */ +#define R_BSP_ROTL(x, y) rotl((unsigned long)(x), (unsigned long)(y)) +/* unsigned long rotr (unsigned long data, unsigned long num) */ +#define R_BSP_ROTR(x, y) rotr((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_ROLC(x) R_BSP_RotateLeftWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateRightWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_RORC(x) R_BSP_RotateRightWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTL(x, y) R_BSP_RotateLeft((unsigned long)(x), (unsigned long)(y)) +/* unsigned long R_BSP_RotateRight (unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTR(x, y) R_BSP_RotateRight((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* unsigned long __ROLC(unsigned long) */ +#define R_BSP_ROLC(x) __ROLC((unsigned long)(x)) +/* unsigned long __RORC(unsigned long) */ +#define R_BSP_RORC(x) __RORC((unsigned long)(x)) +/* unsigned long __ROTL(unsigned long, unsigned long) */ +#define R_BSP_ROTL(x, y) __ROTL((unsigned long)(y), (unsigned long)(x)) +/* unsigned long __ROTR(unsigned long, unsigned long) */ +#define R_BSP_ROTR(x, y) __ROTR((unsigned long)(y), (unsigned long)(x)) + +#endif + +/* ---------- Special Instructions ---------- */ +#if defined(__CCRX__) + +/* void brk(void) */ +#define R_BSP_BRK() brk() +/* void int_exception(signed long num) */ +#define R_BSP_INT(x) int_exception((signed long)(x)) +/* void wait(void) */ +#define R_BSP_WAIT() wait() +/* void nop(void) */ +#define R_BSP_NOP() nop() + +#elif defined(__GNUC__) + +/* void __builtin_rx_brk (void) */ +#define R_BSP_BRK() __builtin_rx_brk() +/* void __builtin_rx_int (int) */ +#define R_BSP_INT(x) __builtin_rx_int((int)(x)) +/* void __builtin_rx_wait (void) */ +#define R_BSP_WAIT() __builtin_rx_wait() +/* __asm("nop") */ +#define R_BSP_NOP() __asm("nop") + +#elif defined(__ICCRX__) + +/* void __break(void) */ +#define R_BSP_BRK() __break() +/* void __software_interrupt(unsigned char) */ +#define R_BSP_INT(x) __software_interrupt((unsigned char)(x)) +/* void __wait_for_interrupt(void) */ +#define R_BSP_WAIT() __wait_for_interrupt() +/* void __no_operation(void) */ +#define R_BSP_NOP() __no_operation() + +#endif + +/* ---------- Processor interrupt priority level (IPL) ---------- */ +#if defined(__CCRX__) + +/* void set_ipl(signed long level) */ +#define R_BSP_SET_IPL(x) set_ipl((signed long)(x)) +/* unsigned char get_ipl(void) */ +#define R_BSP_GET_IPL() get_ipl() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtipl (int) */ +#define R_BSP_SET_IPL(x) __builtin_rx_mvtipl((int)(x)) +/* uint32_t R_BSP_CpuInterruptLevelRead (void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_IPL() (unsigned char)R_BSP_CpuInterruptLevelRead() + +#elif defined(__ICCRX__) + +/* void __set_interrupt_level(__ilevel_t) */ +#define R_BSP_SET_IPL(x) __set_interrupt_level((__ilevel_t)(x)) +/* __ilevel_t __get_interrupt_level(void) */ +#define R_BSP_GET_IPL() (unsigned char)__get_interrupt_level() + +#endif + +/* ---------- Processor status word (PSW) ---------- */ +#if defined(__CCRX__) + +/* void set_psw(unsigned long data) */ +#define R_BSP_SET_PSW(x) set_psw((unsigned long)(x)) +/* unsigned long get_psw(void) */ +#define R_BSP_GET_PSW() get_psw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_PSW(x) __builtin_rx_mvtc(0x0, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_PSW() (unsigned long)__builtin_rx_mvfc(0x0) + +#elif defined(__ICCRX__) + +/* void __set_PSW_register(unsigned long) */ +#define R_BSP_SET_PSW(x) __set_PSW_register((unsigned long)(x)) +/* unsigned long __get_PSW_register(void) */ +#define R_BSP_GET_PSW() __get_PSW_register() + +#endif + +/* ---------- Floating-point status word (FPSW) ---------- */ +#ifdef __FPU +#if defined(__CCRX__) + +/* void set_fpsw(unsigned long data) */ +#define R_BSP_SET_FPSW(x) set_fpsw((unsigned long)(x)) +/* unsigned long get_fpsw(void) */ +#define R_BSP_GET_FPSW() get_fpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FPSW(x) __builtin_rx_mvtc(0x3, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FPSW() (unsigned long)__builtin_rx_mvfc(0x3) + +#elif defined(__ICCRX__) + +/* void __set_FPSW_register(unsigned long) */ +#define R_BSP_SET_FPSW(x) __set_FPSW_register((unsigned long)(x)) +/* unsigned long __get_FPSW_register(void) */ +#define R_BSP_GET_FPSW() __get_FPSW_register() + +#endif +#endif + +/* ---------- User Stack Pointer (USP) ---------- */ +#if defined(__CCRX__) + +/* void set_usp(void *data) */ +#define R_BSP_SET_USP(x) set_usp((void *)(x)) +/* void *get_usp(void) */ +#define R_BSP_GET_USP() get_usp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_USP(x) __builtin_rx_mvtc(0x2, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_USP() (void *)__builtin_rx_mvfc(0x2) + +#elif defined(__ICCRX__) + +/* void __set_USP_register(unsigned long) */ +#define R_BSP_SET_USP(x) __set_USP_register((unsigned long)(x)) +/* unsigned long __get_USP_register(void) */ +#define R_BSP_GET_USP() (void *)__get_USP_register() + +#endif + +/* ---------- Interrupt Stack Pointer (ISP) ---------- */ +#if defined(__CCRX__) + +/* void set_isp(void *data) */ +#define R_BSP_SET_ISP(x) set_isp((void *)(x)) +/* void *get_isp(void) */ +#define R_BSP_GET_ISP() get_isp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_ISP(x) __builtin_rx_mvtc(0xA, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_ISP() (void *)__builtin_rx_mvfc(0xA) + +#elif defined(__ICCRX__) + +/* void __set_ISP_register(unsigned long) */ +#define R_BSP_SET_ISP(x) __set_ISP_register((unsigned long)(x)) +/* unsigned long __get_ISP_register(void) */ +#define R_BSP_GET_ISP() (void *)__get_ISP_register() + +#endif + +/* ---------- Interrupt Table Register (INTB) ---------- */ +#if defined(__CCRX__) + +/* void set_intb(void *data) */ +#define R_BSP_SET_INTB(x) set_intb((void *)(x)) +/* void *get_intb(void) */ +#define R_BSP_GET_INTB() get_intb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_INTB(x) __builtin_rx_mvtc(0xC, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_INTB() (void *)__builtin_rx_mvfc(0xC) + +#elif defined(__ICCRX__) + +/* void __set_interrupt_table(unsigned long address) */ +#define R_BSP_SET_INTB(x) __set_interrupt_table((unsigned long)(x)) +/* unsigned long __get_interrupt_table(void); */ +#define R_BSP_GET_INTB() (void *)__get_interrupt_table() + +#endif + +/* ---------- Backup PSW (BPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_bpsw(unsigned long data) */ +#define R_BSP_SET_BPSW(x) set_bpsw((unsigned long)(x)) +/* unsigned long get_bpsw(void) */ +#define R_BSP_GET_BPSW() get_bpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPSW(x) __builtin_rx_mvtc(0x8, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPSW() (unsigned long)__builtin_rx_mvfc(0x8) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPSW(x) R_BSP_SetBPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetBPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPSW() R_BSP_GetBPSW() + +#endif + +/* ---------- Backup PC (BPC) ---------- */ +#if defined(__CCRX__) + +/* void set_bpc(void *data) */ +#define R_BSP_SET_BPC(x) set_bpc((void *)(x)) +/* void *get_bpc(void) */ +#define R_BSP_GET_BPC() get_bpc() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPC(x) __builtin_rx_mvtc(0x9, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPC() (void *)__builtin_rx_mvfc(0x9) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPC(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPC(x) R_BSP_SetBPC((void *)(x)) +/* void *R_BSP_GetBPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPC() R_BSP_GetBPC() + +#endif + +/* ---------- Fast Interrupt Vector Register (FINTV) ---------- */ +#if defined(__CCRX__) + +/* void set_fintv(void *data) */ +#define R_BSP_SET_FINTV(x) set_fintv((void *)(x)) +/* void *get_fintv(void) */ +#define R_BSP_GET_FINTV() get_fintv() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FINTV(x) __builtin_rx_mvtc(0xB, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FINTV() (void *)__builtin_rx_mvfc(0xB) + +#elif defined(__ICCRX__) + +/* void __set_FINTV_register(__fast_int_f) */ +#define R_BSP_SET_FINTV(x) __set_FINTV_register((__fast_int_f)(x)) +/* __fast_int_f __get_FINTV_register(void) */ +#define R_BSP_GET_FINTV() (void *)__get_FINTV_register() + +#endif + +/* ---------- Significant 64-bit multiplication ---------- */ +#if defined(__CCRX__) + +/* signed long long emul(signed long data1, signed long data2) */ +#define R_BSP_EMUL(x, y) emul((signed long)(x), (signed long)(y)) +/* unsigned long long emulu(unsigned long data1, unsigned long data2) */ +#define R_BSP_EMULU(x, y) emulu((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#endif + +/* ---------- Processor mode (PM) ---------- */ +#if defined(__CCRX__) + +/* void chg_pmusr(void) */ +#define R_BSP_CHG_PMUSR() chg_pmusr() + +#elif defined(__GNUC__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#elif defined(__ICCRX__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#endif + +/* ---------- Accumulator (ACC) ---------- */ +#if defined(__CCRX__) + +/* void set_acc(signed long long data) */ +#define R_BSP_SET_ACC(x) set_acc((signed long long)(x)) +/* signed long long get_acc(void) */ +#define R_BSP_GET_ACC() get_acc() + +#elif defined(__GNUC__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#endif + +/* ---------- Control of the interrupt enable bits ---------- */ +#if defined(__CCRX__) + +/* void setpsw_i(void) */ +#define R_BSP_SETPSW_I() setpsw_i() +/* void clrpsw_i(void) */ +#define R_BSP_CLRPSW_I() clrpsw_i() + +#elif defined(__GNUC__) + +/* void __builtin_rx_setpsw (int) */ +#define R_BSP_SETPSW_I() __builtin_rx_setpsw('I') +/* void __builtin_rx_clrpsw (int) */ +#define R_BSP_CLRPSW_I() __builtin_rx_clrpsw('I') + +#elif defined(__ICCRX__) + +/* void __enable_interrupt(void) */ +#define R_BSP_SETPSW_I() __enable_interrupt() +/* void __disable_interrupt(void) */ +#define R_BSP_CLRPSW_I() __disable_interrupt() + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long macl(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw1(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw2(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__GNUC__) + +/* long R_BSP_MulAndAccOperation_2byte(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACL(x, y, z) R_BSP_MulAndAccOperation_2byte((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint1(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW1(x, y, z) R_BSP_MulAndAccOperation_FixedPoint1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint2(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW2(x, y, z) R_BSP_MulAndAccOperation_FixedPoint2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__ICCRX__) + +/* long __macl(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) __macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw1(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) __macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw2(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) __macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#endif + +/* ---------- Exception Table Register (EXTB) ---------- */ +#ifdef BSP_MCU_EXCEPTION_TABLE +#if defined(__CCRX__) + +/* void set_extb(void *data) */ +#define R_BSP_SET_EXTB(x) set_extb((void *)(x)) +/* void *get_extb(void) */ +#define R_BSP_GET_EXTB() get_extb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_EXTB(x) __builtin_rx_mvtc(0xD, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_EXTB() (void *)__builtin_rx_mvfc(0xD) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetEXTB(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_EXTB(x) R_BSP_SetEXTB((void *)(x)) +/* void *R_BSP_GetEXTB(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_EXTB() R_BSP_GetEXTB() + +#endif +#endif + +/* ---------- Bit Manipulation ---------- */ +#if defined(__CCRX__) + +/* void __bclr(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_CLEAR(x, y) __bclr((unsigned char *)(x), (unsigned long)(y)) +/* void __bset(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_SET(x, y) __bset((unsigned char *)(x), (unsigned long)(y)) +/* void __bnot(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_REVERSE(x, y) __bnot((unsigned char *)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#elif defined(__ICCRX__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/* ---------- Double-Precision Floating-Point Status Word (DPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_dpsw(unsigned long data) */ +#define R_BSP_SET_DPSW(x) __set_dpsw((unsigned long)(x)) +/* unsigned long get_dpsw(void) */ +#define R_BSP_GET_DPSW() __get_dpsw() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#endif + +/* ---------- Double-precision floating-point exception handling operation control register (DECNT) ---------- */ +#if defined(__CCRX__) + +/* void __set_decnt(unsigned long data) */ +#define R_BSP_SET_DECNT(x) __set_decnt((unsigned long)(x)) +/* unsigned long __get_decnt(void) */ +#define R_BSP_GET_DECNT() __get_decnt() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#endif + +/* ---------- Double-precision floating-point exception program counter (DEPC) ---------- */ +#if defined(__CCRX__) + +/* void *__get_depc(void) */ +#define R_BSP_GET_DEPC() __get_depc() + +#elif defined(__GNUC__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#elif defined(__ICCRX__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#endif +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */ +#ifdef BSP_MCU_TRIGONOMETRIC +#if defined(__CCRX__) + +/* void __init_tfu(void) */ +#define R_BSP_INIT_TFU() __init_tfu() + +#elif defined(__GNUC__) + +/* void R_BSP_InitTFU(void) (This macro uses API function of BSP.) */ +#define R_BSP_INIT_TFU() R_BSP_InitTFU() + +#elif defined(__ICCRX__) + +/* Invalid for ICCRX. + Because the initilaze function of TFU is called automatically when the TFU function is called. */ +#define R_BSP_INIT_TFU() + +#endif + +/* ---------- Calculating the Sine and Cosine of an angle at the same time(single precision) ---------- */ +#if defined(__CCRX__) + +/* void __sincosf(float f, float *sin, float *cos) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) R_BSP_CalcSine_Cosine((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#endif + +/* ---------- Initializing Arithmetic Unit for Trigonometric Functions ---------- */ +#if defined(__CCRX__) + +/* void __atan2hypotf(float y, float x, float *atan2, float *hypot) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) R_BSP_CalcAtan_SquareRoot((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#endif +#endif /* BSP_MCU_TRIGONOMETRIC */ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2); +signed long R_BSP_Min(signed long data1, signed long data2); +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2); +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2); +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2); +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data); +unsigned long R_BSP_RotateRightWithCarry(unsigned long data); +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num); +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num); +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count); +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2); +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2); +void R_BSP_SetACC(signed long long data); +signed long long R_BSP_GetACC(void); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +R_BSP_ATTRIB_INLINE_ASM void R_BSP_ChangeToUserMode(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPSW(uint32_t data); +uint32_t R_BSP_GetBPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPC(void * data); +void *R_BSP_GetBPC(void); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetEXTB(void * data); +void *R_BSP_GetEXTB(void); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitSet(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitClear(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitReverse(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccHiLong(int32_t data); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccLoLong(int32_t data); +int32_t R_BSP_MoveFromAccHiLong(void); +int32_t R_BSP_MoveFromAccMiLong(void); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDPSW(uint32_t data); +uint32_t R_BSP_GetDPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDECNT(uint32_t data); +uint32_t R_BSP_GetDECNT(void); +void *R_BSP_GetDEPC(void); +#endif +#endif +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_InitTFU(void); +#ifdef __FPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot); +#endif /* __FPU */ +#endif /* __TFU */ +#endif + +/* End of multiple inclusion prevention macro */ +#endif /* R_RX_INTRINSIC_FUNCTIONS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_typedefs.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_typedefs.h new file mode 100644 index 000000000..34f975d0b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/r_typedefs.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_typedefs.h +* Description : This has fixed-width integer and bool support for compilers that are not C99 compliant and do not have +* the header files stdint.h, stdbool.h, and stddef.h. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 18.09.2012 1.00 First Release +* : 21.06.2013 1.10 Added NULL and size_t support. +* : 22.11.2013 1.11 Changed size_t to 'unsigned long' from 'unsigned int'. +* : 28.02.2019 1.12 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +#define bool (_Bool) +#define false (0) +#define true (1) +#define NULL (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef signed long long int64_t; +typedef unsigned long long uint64_t; +typedef unsigned int _Bool; +typedef unsigned long size_t; + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/resetprg.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/resetprg.c new file mode 100644 index 000000000..d6fa1bfcd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/resetprg.c @@ -0,0 +1,365 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : resetprg.c +* Description : Defines post-reset routines that are used to configure the MCU prior to the main program starting. +* This is where the program counter starts on power-up or reset. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_PSW_INIT +* - BSP_PRV_FPSW_INIT +* - BSP_PRV_FPU_ROUND +* - BSP_PRV_FPU_DENOM +* Added following macro definitions. +* - BSP_PRV_DPSW_INIT +* : 26.07.2019 3.01 Added vbatt_voltage_stability_wait function. +* : 08.10.2019 3.10 Changed for added support of Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) +/* Defines MCU configuration functions used in this file */ +#include <_h_c_lib.h> +#endif /* defined(__CCRX__) */ + +/* Define the target platform */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + +#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600PX +#pragma section P PS +#pragma section B BS +#pragma section C CS +#pragma section D DS +#else +#include "ri_cmt.h" /* Generated by cfg600 */ +#endif /* BSP_CFG_RENESAS_RTOS_USED */ + +#else /* BSP_CFG_RTOS_USED!=4 */ + +/* Declaration of stack size. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +R_BSP_PRAGMA_STACKSIZE_SU(BSP_CFG_USTACK_BYTES) +#endif +R_BSP_PRAGMA_STACKSIZE_SI(BSP_CFG_ISTACK_BYTES) + +#endif/* BSP_CFG_RTOS_USED */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + #define BSP_PRV_PSW_INIT (0x00000000) /* Supervisor mode & Disable Interrupt */ +#else /* BSP_CFG_RTOS_USED!=4 */ +/* If the user chooses only 1 stack then the 'U' bit will not be set and the CPU will always use the interrupt stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 + #define BSP_PRV_PSW_INIT (0x00030000) +#else + #define BSP_PRV_PSW_INIT (0x00010000) +#endif +#endif/* BSP_CFG_RTOS_USED */ + +#if defined(__CCRX__) || defined(__GNUC__) + +#ifdef BSP_MCU_FLOATING_POINT + /* Initialize FPSW for floating-point operations */ +#define BSP_PRV_FPSW_INIT (0x00000000) /* Currently nothing set by default. */ +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT + /* Initialize DPSW for double-precision floating-point operations */ +#define BSP_PRV_DPSW_INIT (0x00000000) /* Currently nothing set by default. */ +#endif + +#ifdef __ROZ +#define BSP_PRV_FPU_ROUND (0x00000001) /* Let FPSW RMbits=01 (round to zero) */ +#else +#define BSP_PRV_FPU_ROUND (0x00000000) /* Let FPSW RMbits=00 (round to nearest) */ +#endif +#ifdef __DOFF +#define BSP_PRV_FPU_DENOM (0x00000100) /* Let FPSW DNbit=1 (denormal as zero) */ +#else +#define BSP_PRV_FPU_DENOM (0x00000000) /* Let FPSW DNbit=0 (denormal as is) */ +#endif +#endif + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +Pre-processor Directives +***********************************************************************************************************************/ +/* Set this as the entry point from a power-on reset */ +#if defined(__CCRX__) +#pragma entry PowerON_Reset_PC +#endif /* defined(__CCRX__) */ + +/*********************************************************************************************************************** +External function Prototypes +***********************************************************************************************************************/ +/* Initialize C runtime environment */ +extern void _INITSCT(void); + +#if defined(CPPAPP) +/* Initialize C++ global class object */ +extern void _CALL_INIT(void); +#endif + +#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED != 0 +/* If user is requesting warm start callback functions then these are the prototypes. */ +void BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(void); +#endif + +#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED != 0 +/* If user is requesting warm start callback functions then these are the prototypes. */ +void BSP_CFG_USER_WARM_START_POST_C_FUNCTION(void); +#endif + +#if BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ +/* A function is used to create a main task, rtos's objects required to be available in advance. */ +extern void Processing_Before_Start_Kernel(void); +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +/* kernel initialization routine */ +extern void vsta_knl(void); +#endif/* BSP_CFG_RTOS_USED */ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Power-on reset function declaration */ +R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION); + +/* Main program function declaration */ +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ +extern void R_BSP_MAIN_FUNCTION(void); +#endif + +/*********************************************************************************************************************** +* Function name: PowerON_Reset_PC +* Description : This function is the MCU's entry point from a power-on reset. +* The following steps are taken in the startup code: +* 1. The User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) are both set immediately after entry +* to this function. The USP and ISP stack sizes are set in the file bsp_config.h. +* 2. The interrupt vector base register is set to point to the beginning of the relocatable interrupt +* vector table. +* 3. The MCU is setup for floating point operations by setting the initial value of the Floating Point +* Status Word (FPSW). +* 4. The MCU operating frequency is set by configuring the Clock Generation Circuit (CGC) in +* operating_frequency_set. +* 5. Calls are made to functions to setup the C runtime environment which involves initializing all +* initialed data, zeroing all uninitialized variables, and configuring STDIO if used +* (calls to _INITSCT and init_iolib). +* 6. Board-specific hardware setup, including configuring I/O pins on the MCU, in hardware_setup. +* 7. Global interrupts are enabled by setting the I bit in the Program Status Word (PSW), and the stack +* is switched from the ISP to the USP. The initial Interrupt Priority Level is set to zero, enabling +* any interrupts with a priority greater than zero to be serviced. +* 8. The processor is optionally switched to user mode. To run in user mode, set the macro +* BSP_CFG_RUN_IN_USER_MODE above to a 1. +* 9. The bus error interrupt is enabled to catch any accesses to invalid or reserved areas of memory. +* +* Once this initialization is complete, the user's main() function is called. It should not return. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_STARTUP_FUNCTION) +{ + /* Stack pointers are setup prior to calling this function - see comments above */ + + /* You can use auto variables in this function but such variables other than register variables + * will be unavailable after you change the stack from the I stack to the U stack (if change). */ + + /* The bss sections have not been cleared and the data sections have not been initialized + * and constructors of C++ objects have not been executed until the _INITSCT() is executed. */ +#if defined(__GNUC__) +#if BSP_CFG_USER_STACK_ENABLE == 1 + INTERNAL_NOT_USED(ustack_area); +#endif + INTERNAL_NOT_USED(istack_area); +#endif + +#if defined(__CCRX__) || defined(__GNUC__) + + /* Initialize the Interrupt Table Register */ + R_BSP_SET_INTB(R_BSP_SECTOP_INTVECTTBL); + +#ifdef BSP_MCU_EXCEPTION_TABLE + /* Initialize the Exception Table Register */ + R_BSP_SET_EXTB(R_BSP_SECTOP_EXCEPTVECTTBL); +#endif + +#ifdef BSP_MCU_FLOATING_POINT +#ifdef __FPU + /* Initialize the Floating-Point Status Word Register. */ + R_BSP_SET_FPSW(BSP_PRV_FPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM); +#endif +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU + /* Initialize the Double-Precision Floating-Point Status Word Register. */ + R_BSP_SET_DPSW(BSP_PRV_DPSW_INIT | BSP_PRV_FPU_ROUND | BSP_PRV_FPU_DENOM); +#endif +#endif + + /* Initializes the trigonometric function unit. */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU + R_BSP_INIT_TFU(); +#endif +#endif + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + + /* Wait for power voltage stabilization of VBATT function. */ +#if (defined(BSP_CFG_VBATT_ENABLE) && (BSP_CFG_VBATT_ENABLE == 0)) + vbatt_voltage_stability_wait(); +#endif + + /* Switch to high-speed operation */ + mcu_clock_setup(); + + /* If the warm start Pre C runtime callback is enabled, then call it. */ +#if BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED == 1 + BSP_CFG_USER_WARM_START_PRE_C_FUNCTION(); +#endif + + /* Initialize C runtime environment */ + _INITSCT(); + +#if defined(CPPAPP) + /* Initialize C++ global class object */ + _CALL_INIT(); +#endif + + /* Initialize RAM */ + bsp_ram_initialize(); + + /* If the warm start Post C runtime callback is enabled, then call it. */ +#if BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED == 1 + BSP_CFG_USER_WARM_START_POST_C_FUNCTION(); +#endif + +#if BSP_CFG_IO_LIB_ENABLE == 1 + /* Comment this out if not using I/O lib */ +#if defined(__CCRX__) + init_iolib(); +#endif /* defined(__CCRX__) */ +#endif + + /* Initialize MCU interrupt callbacks. */ + bsp_interrupt_open(); + + /* Initialize register protection functionality. */ + bsp_register_protect_open(); + + /* Configure the MCU and board hardware */ + hardware_setup(); + + /* Enable interrupt and select the I stack or the U stack */ + R_BSP_SET_PSW(BSP_PRV_PSW_INIT); + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* Does not change the MCU's user mode to user in Renesas RTOS. */ +#else /* BSP_CFG_RTOS_USED != 4 */ +#if BSP_CFG_RUN_IN_USER_MODE == 1 + /* Change the MCU's user mode from supervisor to user */ + #if BSP_CFG_USER_STACK_ENABLE == 1 + R_BSP_CHG_PMUSR(); + #else + #error "Settings of BSP_CFG_RUN_IN_USER_MODE and BSP_CFG_USER_STACK_ENABLE are inconsistent with each other." + #endif +#endif /* BSP_CFG_RUN_IN_USER_MODE */ +#endif /* BSP_CFG_RTOS_USED */ + + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR); + +#if BSP_CFG_RTOS_USED == 0 /* Non-OS */ + /* Call the main program function (should not return) */ + R_BSP_MAIN_FUNCTION(); +#elif BSP_CFG_RTOS_USED == 1 /* FreeRTOS */ + /* Lock the channel that system timer of RTOS is using. */ + #if (((BSP_CFG_RTOS_SYSTEM_TIMER) >=0) && ((BSP_CFG_RTOS_SYSTEM_TIMER) <= 3)) + if (R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + BSP_CFG_RTOS_SYSTEM_TIMER)) == false) + { + /* WAIT_LOOP */ + while(1); + } + #else + #error "Setting BSP_CFG_RTOS_SYSTEM_TIMER is invalid." + #endif + + /* Prepare the necessary tasks, FreeRTOS's resources... required to be executed at the beginning + * after vTaskStarScheduler() is called. Other tasks can also be created after starting scheduler at any time */ + Processing_Before_Start_Kernel(); + + /* Call the kernel startup (should not return) */ + vTaskStartScheduler(); +#elif BSP_CFG_RTOS_USED == 2 /* SEGGER embOS */ +#elif BSP_CFG_RTOS_USED == 3 /* Micrium MicroC/OS */ +#elif BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#if BSP_CFG_RENESAS_RTOS_USED == RENESAS_RI600V4 + /* Lock a timer resource by r_bsp, if using time function on RTOS. */ + if(R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_CMT0 + _RI_CLOCK_TIMER)) == false) + { + /* WAIT_LOOP */ + while(1); + } + /* Initialize CMT for RI600V4 */ + _RI_init_cmt(); +#else + /* When RI600PX, the above are in _RI_init_cmt_knl called from the kernel. */ +#endif + /* Make sure to disable interrupt. */ + R_BSP_CLRPSW_I();/* clrpsw_i() */ + vsta_knl(); +#endif/* BSP_CFG_RTOS_USED */ + +#if BSP_CFG_IO_LIB_ENABLE == 1 + /* Comment this out if not using I/O lib - cleans up open files */ +#if defined(__CCRX__) + close_all(); +#endif /* defined(__CCRX__) */ +#endif + + /* Infinite loop is intended here. */ + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Put a breakpoint here if you want to catch an exit of main(). */ + R_BSP_NOP(); + } +} /* End of function PowerON_Reset_PC() */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +/* Definition of Kernel data section */ +#include "kernel_ram.h" /* generated by cfg600 */ +#include "kernel_rom.h" /* generated by cfg600 */ +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/sbrk.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/sbrk.c new file mode 100644 index 000000000..30bf1038f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/sbrk.c @@ -0,0 +1,120 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : sbrk.c +* Description : Configures the MCU heap memory. The size of the heap is defined by the macro HEAPSIZE below. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 3.01 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "sbrk.h" + +/* Only use this file if heap is enabled in r_bsp_config. */ +#if BSP_CFG_HEAP_BYTES > 0 + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if defined(__CCRX__) || defined(__GNUC__) + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Declare memory heap area */ +static u_heap_type_t s_heap_area; + +/* End address allocated by sbrk (CC-RX and GNURX+NEWLIB) */ +static int8_t *sp_brk=(int8_t *)&s_heap_area; + +#if defined(__GNUC__) +/* Start address of allocated heap area (GNURX+OPTLIB only) */ +int8_t *_heap_of_memory=(int8_t *)&s_heap_area; +/* End address of allocated heap area (GNURX+OPTLIB only) */ +int8_t *_last_heap_object=(int8_t *)&s_heap_area; +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function name: sbrk +* Description : This function configures MCU memory area allocation. (CC-RX and GNURX+NEWLIB) +* Arguments : size - +* assigned area size +* Return value : Start address of allocated area (pass) +* -1 (failure) +***********************************************************************************************************************/ +int8_t *sbrk(size_t size) +{ + int8_t *p_area; + + if ((sp_brk + size) > (s_heap_area.heap + BSP_CFG_HEAP_BYTES)) + { + /* Empty area size */ + p_area = (int8_t *)-1; + } + else + { + /* Area assignment */ + p_area = sp_brk; + + /* End address update */ + sp_brk += size; + } + + /* Return result */ + return p_area; +} /* End of function sbrk() */ + +#if defined(__GNUC__) +/*********************************************************************************************************************** +* Function name: _top_of_heap +* Description : This function returns end address of reserved heap area. (GNURX+OPTLIB only) +* Arguments : none +* Return value : End address of reserved heap area +***********************************************************************************************************************/ +int8_t *_top_of_heap(void) +{ + return (int8_t *)(s_heap_area.heap + BSP_CFG_HEAP_BYTES); +} /* End of function End of function sbrk()() */ +#endif /* defined(__GNUC__) */ + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +#endif /* BSP_CFG_HEAP_BYTES */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/sbrk.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/sbrk.h new file mode 100644 index 000000000..c05b6d191 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/all/sbrk.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : sbrk.h +* Description : Configures the MCU heap memory. The size of the heap is defined by the macro HEAPSIZE below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_common.h" +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef SBRK_H +#define SBRK_H + +/* Only use this file if heap is enabled in r_bsp_config. */ +#if BSP_CFG_HEAP_BYTES > 0 + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#if defined(__CCRX__) || defined(__GNUC__) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef union +{ + int32_t dummy; /* Dummy for 4-byte boundary */ + int8_t heap[BSP_CFG_HEAP_BYTES]; /* Declaration of the area managed by sbrk*/ +} u_heap_type_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/* const size_t _sbrk_size= // Specifies the minimum unit of */ +/* the defined heap area */ +int8_t *_s1ptr; + +/* Memory allocation function prototype declaration (CC-RX and GNURX+NEWLIB) */ +int8_t *sbrk(size_t size); + +#if defined(__GNUC__) +/* Memory address function prototype declaration (GNURX+OPTLIB only) */ +int8_t *_top_of_heap(void); +#endif /* defined(__GNUC__) */ + +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +#endif /* BSP_CFG_HEAP_BYTES */ + +#endif /* SBRK_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c new file mode 100644 index 000000000..f8c4a0f3c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.c @@ -0,0 +1,1082 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.c +* Description : Contains clock specific routines +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Removed unnecessary processing from the clock_source_select fucntion. +* : 17.12.2019 1.02 Fixed warning of clock_source_select function with IAR compiler. +* : 14.02.2020 1.03 Fixed warning of clock_source_select function with CCRX and IAR compiler. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_CKSEL_LOCO (0x0) +#define BSP_PRV_CKSEL_HOCO (0x1) +#define BSP_PRV_CKSEL_MAIN_OSC (0x2) +#define BSP_PRV_CKSEL_SUBCLOCK (0x3) +#define BSP_PRV_CKSEL_PLL (0x4) + +#define BSP_PRV_NORMALIZE_X10 (10) /* used to avoid floating point arithmetic */ + +/* This macro runs or stops the low-speed on-chip oscillator(LOCO). + If the following conditions are satisfied, LOCO will operate. + 1. System clock source is LOCO. + 2. Clock output enable and CLKOUT source is LOCO. + */ +#if (BSP_CFG_CLOCK_SOURCE == 0) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 0)) + #define BSP_PRV_LOCO_CLK_OPERATING (1) /* LOCO is operating. */ +#else + #define BSP_PRV_LOCO_CLK_OPERATING (0) /* LOCO is stopped. */ +#endif + +/* This macro runs or stops the high-speed on-chip oscillator(HOCO). + If the following conditions are satisfied, HOCO will operate. + 1. System clock source is HOCO. + 2. System clock source is PLL circuit. PLL source is HOCO. + 3. PHY clock source is PLL circuit. PLL source is HOCO. + 4. PHY clock source is PPLL circuit. PPLL source is HOCO. + 5. Clock output enable and clock output source is HOCO. + 6. Clock output enable and clock output source is PLL circuit. PLL source is HOCO. + 7. Clock output enable and clock output source is PPLL circuit. PPLL source is HOCO. + */ +#if (BSP_CFG_CLOCK_SOURCE == 1) \ + || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 0) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 1) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4) && (BSP_CFG_PLL_SRC == 1)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6) && (BSP_CFG_PLL_SRC == 1)) + #define BSP_PRV_HOCO_CLK_OPERATING (1) /* HOCO is operating. */ +#else + #define BSP_PRV_HOCO_CLK_OPERATING (0) /* HOCO is stopped. */ +#endif + +/* This macro runs or stops the Main-clock oscillator. + If the following conditions are satisfied, Main-clock oscillator will operate. + 1. System clock source is Main-clock oscillator. + 2. System clock source is PLL circuit. PLL source is Main-clock oscillator. + 3. USB clock source is PPLL circuit. PPLL source is Main-clock oscillator. + 4. PHY clock source is PLL circuit. PLL source is Main-clock oscillator. + 5. PHY clock source is PPLL circuit. PPLL source is Main-clock oscillator. + 6. Clock output enable and clock output source is Main-clock oscillator. + 7. Clock output enable and clock output source is PLL circuit. PLL source is Main-clock oscillator. + 8. Clock output enable and clock output source is PPLL circuit. PPLL source is Main-clock oscillator. + */ +#if (BSP_CFG_CLOCK_SOURCE == 2) \ + || ((BSP_CFG_CLOCK_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_USB_CLOCK_SOURCE == 3) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 0) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_PHY_CLOCK_SOURCE == 1) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 2)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4) && (BSP_CFG_PLL_SRC == 0)) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6) && (BSP_CFG_PLL_SRC == 0)) + #define BSP_PRV_MAIN_CLK_OPERATING (1) /* Main-clock oscillator is operating. */ +#else + #define BSP_PRV_MAIN_CLK_OPERATING (0) /* Main-clock oscillator is stopped. */ +#endif + +/* This macro runs or stops the Sub-clock oscillator. + If the following conditions are satisfied, Sub-clock oscillator will operate. + 1. System clock source is Sub-clock oscillator. + 2. Clock output enable and clock output source is Sub-clock oscillator. + */ +#if (BSP_CFG_CLOCK_SOURCE == 3) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 3)) + #define BSP_PRV_SUB_CLK_OPERATING (1) /* Sub-clock oscillator is operating. */ +#else /* Clock source is not Sub-clock oscillator. */ + #define BSP_PRV_SUB_CLK_OPERATING (0) /* Sub-clock oscillator is stopped. */ +#endif + +/* This macro runs or stops the PLL circuit. + If the following conditions are satisfied, PLL circuit will operate. + 1. System clock source is PLL circuit. + 2. PHY clock source is PLL circuit. + 3. Clock output enable and clock output source is PLL circuit. + */ +#if (BSP_CFG_CLOCK_SOURCE == 4) \ + || (BSP_CFG_PHY_CLOCK_SOURCE == 0) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4)) + #define BSP_PRV_PLL_CLK_OPERATING (1) /* PLL circuit is operating. */ +#else /* PLL is not used as clock source. */ + #define BSP_PRV_PLL_CLK_OPERATING (0) /* PLL circuit is stopped. */ +#endif + +/* This macro runs or stops the PPLL circuit. + If the following conditions are satisfied, PPLL circuit will operate. + 1. USB clock source is PPLL circuit. + 2. PHY clock source is PPLL circuit. + 3. Clock output enable and clock output source is PPLL circuit. + */ +#if (BSP_CFG_USB_CLOCK_SOURCE == 3) \ + || (BSP_CFG_PHY_CLOCK_SOURCE == 1) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 6)) + #define BSP_PRV_PPLL_CLK_OPERATING (1) /* PPLL circuit is operating. */ +#else /* PPLL is not used for USB clock. */ + #define BSP_PRV_PPLL_CLK_OPERATING (0) /* PPLL circuit is stopped. */ +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +static void operating_frequency_set(void); +static void clock_source_select(void); +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/* CLKOUT initial configuration function declaration */ +static void bsp_clkout_initial_configure(void); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function Name: get_iclk_freq_hz +* Description : Return the current ICLK frequency in Hz. Called by R_BSP_GetIClkFreqHz(). +* The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to +* determine the ICLK frequency we need to first find the current system clock source and then, +* in some cases where the clock source can be configured for multiple frequencies, calculate the +* frequency at which it is currently running. +* Arguments : None +* Return Value : uint32_t - the iclk frequency in Hz +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void) +{ + uint32_t sys_clock_src_freq; + uint32_t pll_multiplier; + uint32_t pll_source_freq; + uint32_t hoco_frequency[3] = {16000000, 18000000, 20000000}; + + /* Casting is valid because it matches the type to the retern value. */ + uint8_t cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL; + + switch (cksel) + { + case BSP_PRV_CKSEL_LOCO: + sys_clock_src_freq = BSP_LOCO_HZ; + break; + + case BSP_PRV_CKSEL_HOCO: + + /* Set HOCO frequency. */ + sys_clock_src_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + break; + + case BSP_PRV_CKSEL_MAIN_OSC: + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + + case BSP_PRV_CKSEL_SUBCLOCK: + sys_clock_src_freq = BSP_SUB_CLOCK_HZ; + break; + + case BSP_PRV_CKSEL_PLL: + + /* The RX72N have two possible sources for the PLL */ + + /* Casting is valid because it matches the type to the retern value. */ + pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2); + + /* Default to the MAIN OSC as the PLL source */ + pll_source_freq = BSP_CFG_XTAL_HZ; + + /* If 1 then the HOCO is the PLL source */ + if (0x1 == SYSTEM.PLLCR.BIT.PLLSRCSEL) + { + /* Set HOCO frequency. */ + pll_source_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + } + + /* Casting is valid because it matches the type to the retern value. */ + sys_clock_src_freq = ((pll_source_freq / (((uint32_t)(SYSTEM.PLLCR.BIT.PLIDIV + 1)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier); + break; + + default: + + /* Should never arrive here. Use the Main OSC freq as a default... */ + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + } + + /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */ + return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK)); +} /* End of function get_iclk_freq_hz() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +* Function name: mcu_clock_setup +* Description : Contains clock functions called at device restart. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void mcu_clock_setup(void) +{ + /* Switch to high-speed operation */ + operating_frequency_set(); + +#if BSP_CFG_CLKOUT_OUTPUT != 0 + bsp_clkout_initial_configure(); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +} /* End of function mcu_clock_setup() */ + +/*********************************************************************************************************************** +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void operating_frequency_set (void) +{ + /* Used for constructing value to write to SCKCR, SCKCR2, and SCKCR3 registers. */ + uint32_t tmp_clock = 0; + uint32_t tmp_restore_clock = 0; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Select the clock based upon user's choice. */ + clock_source_select(); + + /* Figure out setting for FCK bits. */ +#if BSP_CFG_FCK_DIV == 1 + /* Do nothing since FCK bits should be 0. */ +#elif BSP_CFG_FCK_DIV == 2 + tmp_clock |= 0x10000000; +#elif BSP_CFG_FCK_DIV == 4 + tmp_clock |= 0x20000000; +#elif BSP_CFG_FCK_DIV == 8 + tmp_clock |= 0x30000000; +#elif BSP_CFG_FCK_DIV == 16 + tmp_clock |= 0x40000000; +#elif BSP_CFG_FCK_DIV == 32 + tmp_clock |= 0x50000000; +#elif BSP_CFG_FCK_DIV == 64 + tmp_clock |= 0x60000000; +#else + #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for ICK bits. */ +#if BSP_CFG_ICK_DIV == 1 + /* Do nothing since ICK bits should be 0. */ +#elif BSP_CFG_ICK_DIV == 2 + tmp_clock |= 0x01000000; +#elif BSP_CFG_ICK_DIV == 4 + tmp_clock |= 0x02000000; +#elif BSP_CFG_ICK_DIV == 8 + tmp_clock |= 0x03000000; +#elif BSP_CFG_ICK_DIV == 16 + tmp_clock |= 0x04000000; +#elif BSP_CFG_ICK_DIV == 32 + tmp_clock |= 0x05000000; +#elif BSP_CFG_ICK_DIV == 64 + tmp_clock |= 0x06000000; +#else + #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for BCK bits. */ +#if BSP_CFG_BCK_DIV == 1 + /* Do nothing since BCK bits should be 0. */ +#elif BSP_CFG_BCK_DIV == 2 + tmp_clock |= 0x00010000; +#elif BSP_CFG_BCK_DIV == 3 + tmp_clock |= 0x00090000; +#elif BSP_CFG_BCK_DIV == 4 + tmp_clock |= 0x00020000; +#elif BSP_CFG_BCK_DIV == 8 + tmp_clock |= 0x00030000; +#elif BSP_CFG_BCK_DIV == 16 + tmp_clock |= 0x00040000; +#elif BSP_CFG_BCK_DIV == 32 + tmp_clock |= 0x00050000; +#elif BSP_CFG_BCK_DIV == 64 + tmp_clock |= 0x00060000; +#else + #error "Error! Invalid setting for BSP_CFG_BCK_DIV in r_bsp_config.h" +#endif + + /* Configure PSTOP1 bit for BCLK output. */ +#if BSP_CFG_BCLK_OUTPUT == 0 + /* Set PSTOP1 bit */ + tmp_clock |= 0x00800000; +#elif BSP_CFG_BCLK_OUTPUT == 1 + /* Clear PSTOP1 bit */ + tmp_clock &= ~0x00800000; +#elif BSP_CFG_BCLK_OUTPUT == 2 + /* Clear PSTOP1 bit */ + tmp_clock &= ~0x00800000; + /* Set BCLK divider bit */ + SYSTEM.BCKCR.BIT.BCLKDIV = 1; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(1 == SYSTEM.BCKCR.BIT.BCLKDIV) + { + R_BSP_NOP(); + } +#else + #error "Error! Invalid setting for BSP_CFG_BCLK_OUTPUT in r_bsp_config.h" +#endif + + /* Figure out setting for PCKA bits. */ +#if BSP_CFG_PCKA_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKA_DIV == 2 + tmp_clock |= 0x00001000; +#elif BSP_CFG_PCKA_DIV == 4 + tmp_clock |= 0x00002000; +#elif BSP_CFG_PCKA_DIV == 8 + tmp_clock |= 0x00003000; +#elif BSP_CFG_PCKA_DIV == 16 + tmp_clock |= 0x00004000; +#elif BSP_CFG_PCKA_DIV == 32 + tmp_clock |= 0x00005000; +#elif BSP_CFG_PCKA_DIV == 64 + tmp_clock |= 0x00006000; +#else + #error "Error! Invalid setting for BSP_CFG_PCKA_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKB bits. */ +#if BSP_CFG_PCKB_DIV == 1 + /* Do nothing since PCKB bits should be 0. */ +#elif BSP_CFG_PCKB_DIV == 2 + tmp_clock |= 0x00000100; +#elif BSP_CFG_PCKB_DIV == 4 + tmp_clock |= 0x00000200; +#elif BSP_CFG_PCKB_DIV == 8 + tmp_clock |= 0x00000300; +#elif BSP_CFG_PCKB_DIV == 16 + tmp_clock |= 0x00000400; +#elif BSP_CFG_PCKB_DIV == 32 + tmp_clock |= 0x00000500; +#elif BSP_CFG_PCKB_DIV == 64 + tmp_clock |= 0x00000600; +#else + #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKC bits. */ +#if BSP_CFG_PCKC_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKC_DIV == 2 + tmp_clock |= 0x00000010; +#elif BSP_CFG_PCKC_DIV == 4 + tmp_clock |= 0x00000020; +#elif BSP_CFG_PCKC_DIV == 8 + tmp_clock |= 0x00000030; +#elif BSP_CFG_PCKC_DIV == 16 + tmp_clock |= 0x00000040; +#elif BSP_CFG_PCKC_DIV == 32 + tmp_clock |= 0x00000050; +#elif BSP_CFG_PCKC_DIV == 64 + tmp_clock |= 0x00000060; +#else + #error "Error! Invalid setting for BSP_CFG_PCKC_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKD bits. */ +#if BSP_CFG_PCKD_DIV == 1 + /* Do nothing since PCKD bits should be 0. */ +#elif BSP_CFG_PCKD_DIV == 2 + tmp_clock |= 0x00000001; +#elif BSP_CFG_PCKD_DIV == 4 + tmp_clock |= 0x00000002; +#elif BSP_CFG_PCKD_DIV == 8 + tmp_clock |= 0x00000003; +#elif BSP_CFG_PCKD_DIV == 16 + tmp_clock |= 0x00000004; +#elif BSP_CFG_PCKD_DIV == 32 + tmp_clock |= 0x00000005; +#elif BSP_CFG_PCKD_DIV == 64 + tmp_clock |= 0x00000006; +#else + #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h" +#endif + + /* To change the ICLK frequency from less than 70 MHz to 70 MHz or higher such that the ratio of the frequency + after the change to that before the change is greater than four, start by setting the frequency to one quarter + of the intended frequency, wait for 3 us, and then change it to the intended frequency. + (Refer User's Manual: 9.10.7 Notes on Changing the ICLK Frequency.) */ + /* Confirm whether to change ICLK frequency from less than 70 MHz to 70 MHz or higher. */ + if(BSP_ICLK_HZ >= BSP_MCU_ICLK_FREQ_THRESHOLD) + { + /* The clock source after reset is LOCO. The frequency of LOCO is 240 kHz. + When the target clock frequency is 70 MHz or higher, it always exceeds 4 times the current clock frequency. + Therefore, this process does not check whether the target clock frequency exceeds 4 times the current + clock frequency. */ + + /* Backup of tmp_clock */ + tmp_restore_clock = tmp_clock; + + /* Clear the setting for ICK and BCK bits. */ + tmp_clock &= 0xF0F0FFFF; +#if BSP_CFG_ICK_DIV == 1 + /* Set ICK and BCK bits to divide by 4. */ + tmp_clock |= 0x02020000; +#elif BSP_CFG_ICK_DIV == 2 + /* Set ICK and BCK bits to divide by 8. */ + tmp_clock |= 0x03030000; +#endif + } + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + + /* Re-init tmp_clock to use to set SCKCR2. */ + tmp_clock = 0; + + /* Figure out setting for UCK bits. */ +#if BSP_CFG_UCK_DIV == 2 + tmp_clock |= 0x00000011; +#elif BSP_CFG_UCK_DIV == 3 + tmp_clock |= 0x00000021; +#elif BSP_CFG_UCK_DIV == 4 + tmp_clock |= 0x00000031; +#elif BSP_CFG_UCK_DIV == 5 + tmp_clock |= 0x00000041; +#else + #error "Error! Invalid setting for BSP_CFG_UCK_DIV in r_bsp_config.h" +#endif + + /* Set SCKCR2 register. */ + SYSTEM.SCKCR2.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR2.WORD) + { + R_BSP_NOP(); + } + + /* Choose clock source. Default for r_bsp_config.h is PLL. */ + tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8; + + /* Casting is valid because it matches the type to the retern value. */ + SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + + /* Set ICLK frequency to target ICLK. */ + if(BSP_ICLK_HZ >= BSP_MCU_ICLK_FREQ_THRESHOLD) + { + /* Wait for 3 us. */ + R_BSP_SoftwareDelay((uint32_t)3, BSP_DELAY_MICROSECS); + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_restore_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_restore_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + } + +#if BSP_PRV_LOCO_CLK_OPERATING == 0 + /* We can now turn LOCO off since it is not going to be used. */ + SYSTEM.LOCOCR.BYTE = 0x01; + + /* Wait for five the LOCO cycles */ + /* 5 count of LOCO : (1000000/216000)*5 = 23.148148148us + 23 + 2 = 25us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)25, BSP_DELAY_MICROSECS); +#endif + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function operating_frequency_set() */ + +/*********************************************************************************************************************** +* Function name: clock_source_select +* Description : Enables and disables clocks as chosen by the user. This function also implements the delays +* needed for the clocks to stabilize. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void clock_source_select (void) +{ + volatile uint8_t i; + volatile uint8_t dummy; +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + uint8_t tmp; +#endif + volatile uint16_t tmp_packcr; + + /* Main clock will be not oscillate in software standby or deep software standby modes. */ + SYSTEM.MOFCR.BIT.MOFXIN = 0; + + /* Set the oscillation source of the main clock oscillator. */ + SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE; + +#if BSP_PRV_HOCO_CLK_OPERATING == 1 + /* HOCO is chosen. Start it operating if it is not already operating. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn on power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x00; + + /* Stop HOCO. */ + SYSTEM.HOCOCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stopped. */ + R_BSP_NOP(); + } + + /* Set HOCO frequency. */ + #if (BSP_CFG_HOCO_FREQUENCY == 0) + SYSTEM.HOCOCR2.BYTE = 0x00; //16MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 1) + SYSTEM.HOCOCR2.BYTE = 0x01; //18MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 2) + SYSTEM.HOCOCR2.BYTE = 0x02; //20MHz + #else + #error "Error! Invalid setting for BSP_CFG_HOCO_FREQUENCY in r_bsp_config.h" + #endif + + /* HOCO is chosen. Start it operating. */ + SYSTEM.HOCOCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.HOCOCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. */ + R_BSP_NOP(); + } +#else /* (BSP_PRV_HOCO_CLK_OPERATING == 0) */ + /* If HOCO is already operating, it doesn't stop. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn off power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x01; + } + else + { + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. */ + R_BSP_NOP(); + } + } +#endif /* BSP_PRV_HOCO_CLK_OPERATING == 1 */ + +#if BSP_PRV_MAIN_CLK_OPERATING == 1 + /* Main clock oscillator is chosen. Start it operating. */ + + /* If the main oscillator is >10MHz then the main clock oscillator forced oscillation control register (MOFCR) must + be changed. */ + if (BSP_CFG_XTAL_HZ > 20000000) + { + /* 20 - 24MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 0; + } + else if (BSP_CFG_XTAL_HZ > 16000000) + { + /* 16 - 20MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 1; + } + else if (BSP_CFG_XTAL_HZ > 8000000) + { + /* 8 - 16MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 2; + } + else + { + /* 8MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 3; + } + + /* Set the oscillation stabilization wait time of the main clock oscillator. */ +#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */ + SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME; +#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */ + SYSTEM.MOSCWTCR.BYTE = 0x00; +#else + #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h" +#endif + + /* Set the main clock to operating. */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. */ + R_BSP_NOP(); + } +#else /* (BSP_PRV_MAIN_CLK_OPERATING == 0) */ + /* Main clock is stopped after reset. */ +#endif /* BSP_PRV_MAIN_CLK_OPERATING == 1 */ + + /* Sub-clock setting. */ + + /* Cold start setting */ + if (0 == SYSTEM.RSTSR1.BIT.CWSF) + { + /* Stop the sub-clock oscillator */ + /* RCR4 - RTC Control Register 4 + b7:b1 Reserved - The write value should be 0. + b0 RCKSEL - Count Source Select - Sub-clock oscillator is selected. */ + RTC.RCR4.BIT.RCKSEL = 0; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR4.BYTE; + } + + /* Confirm that the written */ + if (0 != RTC.RCR4.BIT.RCKSEL) + { + R_BSP_NOP(); + } + + /* RCR3 - RTC Control Register 3 + b7:b4 Reserved - The write value should be 0. + b3:b1 RTCDV - Sub-clock oscillator Drive Ability Control. + b0 RTCEN - Sub-clock oscillator is stopped. */ + RTC.RCR3.BIT.RTCEN = 0; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BYTE; + } + + /* Confirm that the written */ + if (0 != RTC.RCR3.BIT.RTCEN) + { + R_BSP_NOP(); + } + + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stopped. */ + R_BSP_NOP(); + } + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Set the drive capacity of the sub-clock oscillator */ + #if (BSP_CFG_SOSC_DRV_CAP == 0) /* Standard CL */ + tmp = 0x06; + #elif (BSP_CFG_SOSC_DRV_CAP == 1) /* Low CL */ + tmp = 0x01; + #else + #error "Error! Invalid setting for BSP_CFG_SOSC_DRV_CAP in r_bsp_config.h" + #endif + + /* Set the Sub-Clock Oscillator Drive Capacity Control. */ + RTC.RCR3.BIT.RTCDV = tmp; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BYTE; + } + + /* Confirm that the written */ + if (tmp != RTC.RCR3.BIT.RTCDV) + { + R_BSP_NOP(); + } + + /* Set wait time until the sub-clock oscillator stabilizes */ + /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register + b7:b5 Reserved - The write value should be 0. + b4:b0 SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */ + SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME; + + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x00 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stabilized. */ + R_BSP_NOP(); + } +#endif /* (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) */ + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */ + SYSTEM.SOSCWTCR.BYTE = 0x00; + + /* ---- Operate the sub-clock oscillator ---- */ + RTC.RCR3.BIT.RTCEN = 1; + + /* WAIT_LOOP */ + for (i = 0; i < 4; i++) + { + /* dummy read four times */ + dummy = RTC.RCR3.BIT.RTCEN; + } + + /* Confirm that the written value can be read correctly. */ + if (1 != RTC.RCR3.BIT.RTCEN) + { + R_BSP_NOP(); + } +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for six the sub-clock cycles */ + /* 6 count of sub-clock : (1000000/32768)*6=183.10546875us + In the case of LOCO frequency is 264kHz : 183.10546875/(1000000/264000)=48.33984375cycle + (48.33984375+2)*(1000000/240000)=209.7493489583333us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)210, BSP_DELAY_MICROSECS); +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) && (BSP_CFG_RTC_ENABLE == 0) + /* Stop prescaler and counter */ + /* RCR2 - RTC Control Register 2 + b7 CNTMD - Count Mode Select - The calendar count mode. + b6 HR24 - Hours Mode - The RTC operates in 24-hour mode. + b5 AADJP - Automatic Adjustment Period Select - The RADJ.ADJ[5:0] setting value is adjusted from + the count value of the prescaler every 10 seconds. + b4 AADJE - Automatic Adjustment Enable - Automatic adjustment is enabled. + b3 RTCOE - RTCOUT Output Enable - RTCOUT output enabled. + b2 ADJ30 - 30-Second Adjustment - 30-second adjustment is executed. + b1 RESET - RTC Software Reset - The prescaler and the target registers for RTC software reset are initialized. + b0 START - start - Prescaler is stopped. */ + RTC.RCR2.BYTE &= 0x7E; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.START) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* RTC Software Reset */ + RTC.RCR2.BIT.RESET = 1; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.RESET) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* An alarm interrupt request is disabled */ + /* RCR1 - RTC Control Register 1 + b7:b4 PES - Periodic Interrupt Select - These bits specify the period for the periodic interrupt. + b3 RTCOS - RTCOUT Output Select - RTCOUT outputs 1 Hz. + b2 PIE - Periodic Interrupt Enable - A periodic interrupt request is disabled. + b1 CIE - Carry Interrupt Enable - A carry interrupt request is disabled. + b0 AIE - Alarm Interrupt Enable - An alarm interrupt request is disabled. */ + RTC.RCR1.BYTE &= 0xF8; + + /* Wait for one the sub-clock cycles */ + /* 1 count of sub-clock : (1000000/32768)=30.517578125us + In the case of LOCO frequency is 264kHz : 30.517578125/(1000000/264000)=8.056640625cycle + (8.056640625+2)*(1000000/240000)=41.902669270833us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)42, BSP_DELAY_MICROSECS); + + /* Confirm that the written value can be read correctly. */ + if (0x00 != (RTC.RCR1.BYTE & 0x07)) + { + R_BSP_NOP(); + } +#endif /* (BSP_PRV_SUB_CLK_OPERATING == 1) && (BSP_CFG_RTC_ENABLE == 0) */ + } + /* Warm start setting */ + else + { +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || ((BSP_PRV_SUB_CLK_OPERATING == 0) && (BSP_CFG_RTC_ENABLE == 0)) + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* Confirm that the Sub clock stopped. */ + R_BSP_NOP(); + } +#endif + +#if BSP_PRV_SUB_CLK_OPERATING == 1 + /* Set wait time until the sub-clock oscillator stabilizes */ + /* SOSCWTCR - Sub-Clock Oscillator Wait Control Register + b7:b5 Reserved - The write value should be 0. + b4:b0 SSTS - Sub-Clock Oscillator Waiting Time - Waiting time is 2.044ms(the maximum value of fLOCO). */ + SYSTEM.SOSCWTCR.BYTE = BSP_CFG_SOSC_WAIT_TIME; + + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if (0x00 != SYSTEM.SOSCCR.BYTE) + { + R_BSP_NOP(); + } +#endif + +#if (BSP_PRV_SUB_CLK_OPERATING == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* The delay period needed is to make sure that the sub-clock has stabilized. */ + R_BSP_NOP(); + } +#endif + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Set wait time until the sub-clock oscillator stabilizes ---- */ + SYSTEM.SOSCWTCR.BYTE = 0x00; +#endif + } + +#if (BSP_CFG_PHY_CLOCK_SOURCE == 1) || (BSP_CFG_USB_CLOCK_SOURCE == 3) + /* initialize */ + tmp_packcr = SYSTEM.PACKCR.WORD; + +#if BSP_CFG_PHY_CLOCK_SOURCE == 1 + /* Set value of OUTCKSEL bit. */ + tmp_packcr |= 0x0010; +#endif + +#if BSP_CFG_USB_CLOCK_SOURCE == 3 + /* Set value of UPLLSEL bit. */ + tmp_packcr |= 0x1000; +#endif + + /* Set value to PACLCR register. */ + SYSTEM.PACKCR.WORD = tmp_packcr; +#endif + +#if (BSP_PRV_PLL_CLK_OPERATING == 1) || (BSP_PRV_PPLL_CLK_OPERATING == 1) + /* Set PLL clock source. */ + #if BSP_CFG_PLL_SRC == 0 + /* Clear PLL clock source if PLL clock source is Main clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 0; + #else + /* Set PLL clock source if PLL clock source is HOCO clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 1; + #endif +#endif + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + + /* Set PLL Input Divisor. */ + SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV - 1; + + /* Set PLL Multiplier. */ + SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0)) - 1; + + /* Set the PLL to operating. */ + SYSTEM.PLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. */ + R_BSP_NOP(); + } +#else + /* PLL is stopped after reset. */ +#endif + +#if BSP_PRV_PPLL_CLK_OPERATING == 1 + /* Set PPLL Input Divisor. */ + SYSTEM.PPLLCR.BIT.PPLIDIV = BSP_CFG_PPLL_DIV - 1; + + /* Set PPLL Multiplier. */ + SYSTEM.PPLLCR.BIT.PPLSTC = ((uint8_t)((float)BSP_CFG_PPLL_MUL * 2.0)) - 1; + + /* Set the PPLL to operating. */ + SYSTEM.PPLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PPLOVF) + { + /* The delay period needed is to make sure that the PPLL has stabilized. */ + R_BSP_NOP(); + } + + /* Set PPLCK Input Divisor. */ + SYSTEM.PPLLCR3.BIT.PPLCK = BSP_CFG_PPLCK_DIV - 1; +#endif + + /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn + it off until another clock has been enabled and is ready to use. */ +#if BSP_PRV_LOCO_CLK_OPERATING == 1 + /* LOCO is chosen. This is the default out of reset. */ +#else + /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */ +#endif + + /* RX72N has a MEMWAIT register which controls the cycle waiting for access to code flash memory. + It is set as zero coming out of reset. We only want to set this if we are > 120 MHz. + */ + if (BSP_ICLK_HZ > BSP_MCU_MEMWAIT_FREQ_THRESHOLD) + { + /* Set MEMWAIT */ + SYSTEM.MEMWAIT.BYTE = 0x01; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x01 == SYSTEM.MEMWAIT.BYTE) + { + R_BSP_NOP(); + } + } +} /* End of function clock_source_select() */ + +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/*********************************************************************************************************************** +* Function name: bsp_clkout_initial_configure +* Description : Configures the CLKOUT initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_clkout_initial_configure(void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Set the CLKOUT Output Divisor Select. */ + SYSTEM.CKOCR.BIT.CKODIV = BSP_CFG_CLKOUT_DIV; + + /* Set the CLKOUT Output Source Select. */ + SYSTEM.CKOCR.BIT.CKOSEL = BSP_CFG_CLKOUT_SOURCE; +#if BSP_CFG_CLKOUT_OUTPUT == 1 + + /* Set the CLKOUT Output Stop Control. */ + SYSTEM.CKOCR.BIT.CKOSTP = 0; +#elif BSP_CFG_CLKOUT_OUTPUT == 0 + /* do nothing */ +#else + #error "Error! Invalid setting for BSP_CFG_CLKOUT_OUTPUT in r_bsp_config.h" +#endif + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_clkout_initial_configure() */ +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h new file mode 100644 index 000000000..61c2ab378 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_clocks.h @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.h +* Description : Contains clock specific routines. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_CLOCKS_H +#define MCU_CLOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void); +void mcu_clock_setup(void); + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h new file mode 100644 index 000000000..075b2d313 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_info.h @@ -0,0 +1,269 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_info.h +* Device(s) : RX72N +* Description : Information about the MCU. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INFO +#define MCU_INFO + +/* MCU CPU Version */ +#define BSP_MCU_CPU_VERSION (3) + +/* CPU cycles. Known number of RXv3 CPU cycles required to execute the delay_wait() loop */ +#define CPU_CYCLES_PER_LOOP (3) + +/* MCU Series. */ +#if BSP_CFG_MCU_PART_SERIES == 0x0 + #define BSP_MCU_SERIES_RX700 (1) +#else + #error "ERROR - BSP_CFG_MCU_PART_SERIES - Unknown MCU Series chosen in r_bsp_config.h" +#endif + +/* This macro means that this MCU is part of the RX72x collection of MCUs (i.e. RX72N). */ +#define BSP_MCU_RX72_ALL (1) + +/* MCU Group name. */ +#if BSP_CFG_MCU_PART_GROUP == 0x0 + #define BSP_MCU_RX72N (1) +#else + #error "ERROR - BSP_CFG_MCU_PART_GROUP - Unknown MCU Group chosen in r_bsp_config.h" +#endif + +/* Package. */ +#if BSP_CFG_MCU_PART_PACKAGE == 0x0 + #define BSP_PACKAGE_LFQFP176 (1) + #define BSP_PACKAGE_PINS (176) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x1 + #define BSP_PACKAGE_LFBGA176 (1) + #define BSP_PACKAGE_PINS (176) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x2 + #define BSP_PACKAGE_LFBGA224 (1) + #define BSP_PACKAGE_PINS (224) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x3 + #define BSP_PACKAGE_LFQFP144 (1) + #define BSP_PACKAGE_PINS (144) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x4 + #define BSP_PACKAGE_TFLGA145 (1) + #define BSP_PACKAGE_PINS (145) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x5 + #define BSP_PACKAGE_LFQFP100 (1) + #define BSP_PACKAGE_PINS (100) +#else + #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h" +#endif + +/* Memory size of your MCU. */ +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xD + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (1048576) + #define BSP_DATA_FLASH_SIZE_BYTES (32768) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x17 + #define BSP_ROM_SIZE_BYTES (4194304) + #define BSP_RAM_SIZE_BYTES (1048576) + #define BSP_DATA_FLASH_SIZE_BYTES (32768) +#else + #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h" +#endif + +/* These macros define clock speeds for fixed speed clocks. */ +#define BSP_LOCO_HZ (240000) +#define BSP_SUB_CLOCK_HZ (32768) + +/* Define frequency of HOCO. */ +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "ERROR - Invalid HOCO frequency chosen in r_bsp_config.h! Set valid value for BSP_CFG_HOCO_FREQUENCY." +#endif + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#if BSP_CFG_CLOCK_SOURCE == 0 + #define BSP_SELECTED_CLOCK_HZ (BSP_LOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 1 + #define BSP_SELECTED_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 2 + #define BSP_SELECTED_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 3 + #define BSP_SELECTED_CLOCK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 4 + #if BSP_CFG_PLL_SRC == 0 + #define BSP_SELECTED_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #elif BSP_CFG_PLL_SRC == 1 + #define BSP_SELECTED_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." + #endif +#else + #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h" +#endif + +/* Define frequency of PPLL clock. */ +#if BSP_CFG_PLL_SRC == 0 + #define BSP_PPLL_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PPLL_DIV) * BSP_CFG_PPLL_MUL) +#elif BSP_CFG_PLL_SRC == 1 + #define BSP_PPLL_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PPLL_DIV) * BSP_CFG_PPLL_MUL) +#else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." +#endif + +/* Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#if (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_1ST_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_2ND_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_3RD_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) ||\ + (BSP_CFG_EBMAPCR_4TH_PRIORITY == BSP_CFG_EBMAPCR_5TH_PRIORITY) + #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY" +#endif +#if (5 <= BSP_CFG_EBMAPCR_1ST_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_2ND_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_3RD_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_4TH_PRIORITY) ||\ + (5 <= BSP_CFG_EBMAPCR_5TH_PRIORITY) + #error "Error! Invalid setting for Extended Bus Master Priority in r_bsp_config.h. Please check BSP_CFG_EX_BUS_1ST_PRIORITY to BSP_CFG_EX_BUS_5TH_PRIORITY" +#endif + +/* System clock speed in Hz. */ +#define BSP_ICLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) +/* Peripheral Module Clock A speed in Hz. Used for ETHERC and EDMAC. */ +#define BSP_PCLKA_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKA_DIV) +/* Peripheral Module Clock B speed in Hz. */ +#define BSP_PCLKB_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) +/* Peripheral Module Clock C speed in Hz. */ +#define BSP_PCLKC_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKC_DIV) +/* Peripheral Module Clock D speed in Hz. */ +#define BSP_PCLKD_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) +/* External bus clock speed in Hz. */ +#define BSP_BCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_BCK_DIV) +/* FlashIF clock speed in Hz. */ +#define BSP_FCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) +/* USB clock speed in Hz. */ +#if BSP_CFG_USB_CLOCK_SOURCE == 2 + #define BSP_UCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_UCK_DIV) +#elif BSP_CFG_USB_CLOCK_SOURCE == 3 + #define BSP_UCLK_HZ (BSP_PPLL_CLOCK_HZ / BSP_CFG_PPLCK_DIV) +#else + #error "ERROR - BSP_CFG_USB_CLOCK_SOURCE - Unknown usb clock source chosen in r_bsp_config.h" +#endif + +/* CLKOUT25M clock speed in Hz. */ +#if BSP_CFG_PHY_CLOCK_SOURCE == 0 + #define BSP_CLKOUT25M_HZ (BSP_SELECTED_CLOCK_HZ/8) +#elif BSP_CFG_PHY_CLOCK_SOURCE == 1 + #define BSP_CLKOUT25M_HZ (BSP_PPLL_CLOCK_HZ / 8) +#elif BSP_CFG_PHY_CLOCK_SOURCE == 2 + /* Ethernet-PHY not use */ +#else + #error "ERROR - BSP_CFG_PHY_CLOCK_SOURCE - Unknown Ethernet-PHY clock source chosen in r_bsp_config.h" +#endif + +/* Null argument definitions. */ +#define FIT_NO_FUNC ((void (*)(void *))0x10000000) /* Reserved space on RX */ +#define FIT_NO_PTR ((void *)0x10000000) /* Reserved space on RX */ + +/* Mininum and maximum IPL levels available for this MCU. */ +#define BSP_MCU_IPL_MAX (0xF) +#define BSP_MCU_IPL_MIN (0) + +/* Frequency threshold of memory wait cycle setting. */ +#define BSP_MCU_MEMWAIT_FREQ_THRESHOLD (120000000) /* ICLK > 120MHz requires MEMWAIT register update */ + +/* Frequency threshold of iclk. */ +#define BSP_MCU_ICLK_FREQ_THRESHOLD (70000000) + +/* MCU functions */ +#define BSP_MCU_REGISTER_WRITE_PROTECTION +#define BSP_MCU_RCPC_PRC0 +#define BSP_MCU_RCPC_PRC1 +#define BSP_MCU_RCPC_PRC3 +#define BSP_MCU_FLOATING_POINT +#define BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#define BSP_MCU_EXCEPTION_TABLE +#define BSP_MCU_GROUP_INTERRUPT +#define BSP_MCU_GROUP_INTERRUPT_IE0 +#define BSP_MCU_GROUP_INTERRUPT_BE0 +#define BSP_MCU_GROUP_INTERRUPT_BL0 +#define BSP_MCU_GROUP_INTERRUPT_BL1 +#define BSP_MCU_GROUP_INTERRUPT_BL2 +#define BSP_MCU_GROUP_INTERRUPT_AL0 +#define BSP_MCU_GROUP_INTERRUPT_AL1 +#define BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT +#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +#define BSP_MCU_EXCEP_ACCESS_ISR +#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR +#define BSP_MCU_EXCEP_FLOATING_POINT_ISR +#define BSP_MCU_NON_MASKABLE_ISR +#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +#define BSP_MCU_BUS_ERROR_ISR +#define BSP_MCU_TRIGONOMETRIC + +#define BSP_MCU_NMI_EXC_NMI_PIN +#define BSP_MCU_NMI_OSC_STOP_DETECT +#define BSP_MCU_NMI_WDT_ERROR +#define BSP_MCU_NMI_IWDT_ERROR +#define BSP_MCU_NMI_LVD1 +#define BSP_MCU_NMI_LVD2 +#define BSP_MCU_NMI_EXNMI +#define BSP_MCU_NMI_EXNMI_RAM +#define BSP_MCU_NMI_EXNMI_RAM_EXRAM +#define BSP_MCU_NMI_EXNMI_RAM_ECCRAM +#define BSP_MCU_NMI_EXNMI_DPFPUEX + +#endif /* MCU_INFO */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c new file mode 100644 index 000000000..d9b0c1025 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.c +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get specifics on this MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* RX MCUs come in different packages and different pin counts. + Each bit of PORTm.PDR corresponds to each pin of port m; I/O direction can be specified in 1-bit units. + Each bit of PDR corresponding to port m that does not exist is reserved. + Also, each bit of PDR corresponding to P35 pins is reserved, because such pins are input only. + Make settings of the reserved bit according to the description in section 22.4, Initialization of the Port Direction + Register (PDR). These values are then ORed into the direction registers to set non-existent pins as outputs or + inputs, which can help save power. + */ +#if BSP_PACKAGE_PINS == 224 + /* Refer User's Manual: Hardware Table 22.4. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTH_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD0) + #define BSP_PRV_PORTK_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTL_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTM_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0x00) +#elif BSP_PACKAGE_PINS == 176 + /* Refer User's Manual: Hardware Table 22.5. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD0) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#elif (BSP_PACKAGE_PINS == 145) || (BSP_PACKAGE_PINS == 144) + /* Refer User's Manual: Hardware Table 22.6. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x50) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x80) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x30) + #define BSP_PRV_PORT9_NE_PIN_MASK (0xF0) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xDF) + #define BSP_PRV_PORTG_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xD7) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#elif BSP_PACKAGE_PINS == 100 + /* Refer User's Manual: Hardware Table 22.7. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x5F) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORT6_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT7_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT8_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT9_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTF_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTG_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0xF7) + #define BSP_PRV_PORTK_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTL_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTM_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTN_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTQ_NE_PIN_MASK (0xFF) +#else + #error "ERROR - This package is not defined in mcu_init.c" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_non_existent_port_init +* Description : For MCUs that do not have the maximum number of pins for their group (e.g. MCU with 176 pins when +* maximum is 224 pins) these 'non-existent' pins that are not bonded out need to be initialized to save +* power. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_non_existent_port_init (void) +{ + /* OR in missing pin masks from above. */ + + /* Set PORT0.PDR */ + PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK; + + /* Set PORT1.PDR */ + PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK; + + /* Set PORT2.PDR */ + PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK; + + /* Set PORT3.PDR */ + PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK; + + /* Set PORT4.PDR */ + PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK; + + /* Set PORT5.PDR */ + PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK; + + /* Set PORT6.PDR */ + PORT6.PDR.BYTE |= BSP_PRV_PORT6_NE_PIN_MASK; + + /* Set PORT7.PDR */ + PORT7.PDR.BYTE |= BSP_PRV_PORT7_NE_PIN_MASK; + + /* Set PORT8.PDR */ + PORT8.PDR.BYTE |= BSP_PRV_PORT8_NE_PIN_MASK; + + /* Set PORT9.PDR */ + PORT9.PDR.BYTE |= BSP_PRV_PORT9_NE_PIN_MASK; + + /* Set PORTA.PDR */ + PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK; + + /* Set PORTB.PDR */ + PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK; + + /* Set PORTC.PDR */ + PORTC.PDR.BYTE |= BSP_PRV_PORTC_NE_PIN_MASK; + + /* Set PORTD.PDR */ + PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK; + + /* Set PORTE.PDR */ + PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK; + + /* Set PORTF.PDR */ + PORTF.PDR.BYTE |= BSP_PRV_PORTF_NE_PIN_MASK; + + /* Set PORTG.PDR */ + PORTG.PDR.BYTE |= BSP_PRV_PORTG_NE_PIN_MASK; + + /* Set PORTH.PDR */ + PORTH.PDR.BYTE |= BSP_PRV_PORTH_NE_PIN_MASK; + + /* Set PORTJ.PDR */ + PORTJ.PDR.BYTE |= BSP_PRV_PORTJ_NE_PIN_MASK; + + /* Set PORTK.PDR */ + PORTK.PDR.BYTE |= BSP_PRV_PORTK_NE_PIN_MASK; + + /* Set PORTL.PDR */ + PORTL.PDR.BYTE |= BSP_PRV_PORTL_NE_PIN_MASK; + + /* Set PORTM.PDR */ + PORTM.PDR.BYTE |= BSP_PRV_PORTM_NE_PIN_MASK; + + /* Set PORTN.PDR */ + PORTN.PDR.BYTE |= BSP_PRV_PORTN_NE_PIN_MASK; + + /* Set PORTQ.PDR */ + PORTQ.PDR.BYTE |= BSP_PRV_PORTQ_NE_PIN_MASK; +} /* End of function bsp_non_existent_port_init() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h new file mode 100644 index 000000000..115c6b869 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_init.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.h +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INIT_H +#define MCU_INIT_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_non_existent_port_init(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_INIT_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c new file mode 100644 index 000000000..faba267c7 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.c @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ +#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl2_handler_isr, VECT(ICU,GROUPBL2)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al1_handler_isr, VECT(ICU,GROUPAL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_ie0_handler_isr, VECT(ICU,GROUPIE0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_be0_handler_isr, VECT(ICU,GROUPBE0)) + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ +#ifdef __FPU + uint32_t tmp_fpsw; +#endif + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + +#ifdef __FPU + case (BSP_INT_SRC_EXC_FPU): + + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + if (true == enable) + { + /* Set the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + else + { + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + break; +#endif + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + +/*********************************************************************************************************************** +* Function Name: group_bl0_handler_isr +* Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void) +{ + /* BL0 IS1 */ + if (1 == ICU.GRPBL0.BIT.IS1) + { + /* BSP_INT_SRC_BL0_SCI0_ERI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_ERI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS0 */ + if (1 == ICU.GRPBL0.BIT.IS0) + { + /* BSP_INT_SRC_BL0_SCI0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS3 */ + if (1 == ICU.GRPBL0.BIT.IS3) + { + /* BSP_INT_SRC_BL0_SCI1_ERI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS2 */ + if (1 == ICU.GRPBL0.BIT.IS2) + { + /* BSP_INT_SRC_BL0_SCI1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS5 */ + if (1 == ICU.GRPBL0.BIT.IS5) + { + /* BSP_INT_SRC_BL0_SCI2_ERI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_ERI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS4 */ + if (1 == ICU.GRPBL0.BIT.IS4) + { + /* BSP_INT_SRC_BL0_SCI2_TEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS7 */ + if (1 == ICU.GRPBL0.BIT.IS7) + { + /* BSP_INT_SRC_BL0_SCI3_ERI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_ERI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS6 */ + if (1 == ICU.GRPBL0.BIT.IS6) + { + /* BSP_INT_SRC_BL0_SCI3_TEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI3_TEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS9 */ + if (1 == ICU.GRPBL0.BIT.IS9) + { + /* BSP_INT_SRC_BL0_SCI4_ERI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_ERI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS8 */ + if (1 == ICU.GRPBL0.BIT.IS8) + { + /* BSP_INT_SRC_BL0_SCI4_TEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI4_TEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS11 */ + if (1 == ICU.GRPBL0.BIT.IS11) + { + /* BSP_INT_SRC_BL0_SCI5_ERI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS10 */ + if (1 == ICU.GRPBL0.BIT.IS10) + { + /* BSP_INT_SRC_BL0_SCI5_TEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS13 */ + if (1 == ICU.GRPBL0.BIT.IS13) + { + /* BSP_INT_SRC_BL0_SCI6_ERI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS12 */ + if (1 == ICU.GRPBL0.BIT.IS12) + { + /* BSP_INT_SRC_BL0_SCI6_TEI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS17 */ + if (1 == ICU.GRPBL0.BIT.IS17) + { + /* BSP_INT_SRC_BL0_SCI12_ERI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS16 */ + if (1 == ICU.GRPBL0.BIT.IS16) + { + /* BSP_INT_SRC_BL0_SCI12_TEI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS18 */ + if (1 == ICU.GRPBL0.BIT.IS18) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS19 */ + if (1 == ICU.GRPBL0.BIT.IS19) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS20 */ + if (1 == ICU.GRPBL0.BIT.IS20) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS21 */ + if (1 == ICU.GRPBL0.BIT.IS21) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS24 */ + if (1 == ICU.GRPBL0.BIT.IS24) + { + /* BSP_INT_SRC_BL0_QSPI_QSPSSLI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_QSPI_QSPSSLI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS26 */ + if (1 == ICU.GRPBL0.BIT.IS26) + { + /* BSP_INT_SRC_BL0_CAC_FERRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS27 */ + if (1 == ICU.GRPBL0.BIT.IS27) + { + /* BSP_INT_SRC_BL0_CAC_MENDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS28 */ + if (1 == ICU.GRPBL0.BIT.IS28) + { + /* BSP_INT_SRC_BL0_CAC_OVFI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS29 */ + if (1 == ICU.GRPBL0.BIT.IS29) + { + /* BSP_INT_SRC_BL0_DOC_DOPCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS31 */ + if (1 == ICU.GRPBL0.BIT.IS31) + { + /* BSP_INT_SRC_BL0_PDC_PCERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS30 */ + if (1 == ICU.GRPBL0.BIT.IS30) + { + /* BSP_INT_SRC_BL0_PDC_PCFEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_PDC_PCFEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl1_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void) +{ + /* BL1 IS3 */ + if (1 == ICU.GRPBL1.BIT.IS3) + { + /* BSP_INT_SRC_BL1_SDHI_CDETI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CDETI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS4 */ + if (1 == ICU.GRPBL1.BIT.IS4) + { + /* BSP_INT_SRC_BL1_SDHI_CACI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_CACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS5 */ + if (1 == ICU.GRPBL1.BIT.IS5) + { + /* BSP_INT_SRC_BL1_SDHI_SDACI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SDHI_SDACI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS6 */ + if (1 == ICU.GRPBL1.BIT.IS6) + { + /* BSP_INT_SRC_BL1_MMCIF_CDETIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_CDETIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS7 */ + if (1 == ICU.GRPBL1.BIT.IS7) + { + /* BSP_INT_SRC_BL1_MMCIF_ERRIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ERRIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS8 */ + if (1 == ICU.GRPBL1.BIT.IS8) + { + /* BSP_INT_SRC_BL1_MMCIF_ACCIO */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_MMCIF_ACCIO, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS9 */ + if (1 == ICU.GRPBL1.BIT.IS9) + { + /* BSP_INT_SRC_BL1_POE3_OEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS10 */ + if (1 == ICU.GRPBL1.BIT.IS10) + { + /* BSP_INT_SRC_BL1_POE3_OEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS11 */ + if (1 == ICU.GRPBL1.BIT.IS11) + { + /* BSP_INT_SRC_BL1_POE3_OEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS12 */ + if (1 == ICU.GRPBL1.BIT.IS12) + { + /* BSP_INT_SRC_BL1_POE3_OEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS14 */ + if (1 == ICU.GRPBL1.BIT.IS14) + { + /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS13 */ + if (1 == ICU.GRPBL1.BIT.IS13) + { + /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS16 */ + if (1 == ICU.GRPBL1.BIT.IS16) + { + /* BSP_INT_SRC_BL1_RIIC2_EEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_EEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS15 */ + if (1 == ICU.GRPBL1.BIT.IS15) + { + /* BSP_INT_SRC_BL1_RIIC2_TEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC2_TEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS17 */ + if (1 == ICU.GRPBL1.BIT.IS17) + { + /* BSP_INT_SRC_BL1_SSIE0_SSIF0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SSIE0_SSIF0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS18 */ + if (1 == ICU.GRPBL1.BIT.IS18) + { + /* BSP_INT_SRC_BL1_SSIE1_SSIF1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_SSIE1_SSIF1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS20 */ + if (1 == ICU.GRPBL1.BIT.IS20) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS21 */ + if (1 == ICU.GRPBL1.BIT.IS21) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS22 */ + if (1 == ICU.GRPBL1.BIT.IS22) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS23 */ + if (1 == ICU.GRPBL1.BIT.IS23) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS29 */ + if (1 == ICU.GRPBL1.BIT.IS29) + { + /* BSP_INT_SRC_BL1_RIIC1_EEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_EEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS28 */ + if (1 == ICU.GRPBL1.BIT.IS28) + { + /* BSP_INT_SRC_BL1_RIIC1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl2_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl2_handler_isr (void) +{ + /* BL2 IS7 */ + if (1 == ICU.GRPBL2.BIT.IS7) + { + /* BSP_INT_SRC_BL2_POEG_POEGGAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS8 */ + if (1 == ICU.GRPBL2.BIT.IS8) + { + /* BSP_INT_SRC_BL2_POEG_POEGGBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS9 */ + if (1 == ICU.GRPBL2.BIT.IS9) + { + /* BSP_INT_SRC_BL2_POEG_POEGGCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS10 */ + if (1 == ICU.GRPBL2.BIT.IS10) + { + /* BSP_INT_SRC_BL2_POEG_POEGGDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl2_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al0_handler_isr +* Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void) +{ + /* AL0 IS1 */ + if (1 == ICU.GRPAL0.BIT.IS1) + { + /* BSP_INT_SRC_AL0_SCI8_ERI8 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI8_ERI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS0 */ + if (1 == ICU.GRPAL0.BIT.IS0) + { + /* BSP_INT_SRC_AL0_SCI8_TEI8 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI8_TEI8, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS5 */ + if (1 == ICU.GRPAL0.BIT.IS5) + { + /* BSP_INT_SRC_AL0_SCI9_ERI9 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI9_ERI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS4 */ + if (1 == ICU.GRPAL0.BIT.IS4) + { + /* BSP_INT_SRC_AL0_SCI9_TEI9 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI9_TEI9, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS9 */ + if (1 == ICU.GRPAL0.BIT.IS9) + { + /* BSP_INT_SRC_AL0_SCI10_ERI10 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_ERI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS8 */ + if (1 == ICU.GRPAL0.BIT.IS8) + { + /* BSP_INT_SRC_AL0_SCI10_TEI10 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI10_TEI10, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS13 */ + if (1 == ICU.GRPAL0.BIT.IS13) + { + /* BSP_INT_SRC_AL0_SCI11_ERI11 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_ERI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS12 */ + if (1 == ICU.GRPAL0.BIT.IS12) + { + /* BSP_INT_SRC_AL0_SCI11_TEI11 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI11_TEI11, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS17 */ + if (1 == ICU.GRPAL0.BIT.IS17) + { + /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS16 */ + if (1 == ICU.GRPAL0.BIT.IS16) + { + /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS19 */ + if (1 == ICU.GRPAL0.BIT.IS19) + { + /* BSP_INT_SRC_AL0_RSPI1_SPEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS18 */ + if (1 == ICU.GRPAL0.BIT.IS18) + { + /* BSP_INT_SRC_AL0_RSPI1_SPII1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI1_SPII1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS21 */ + if (1 == ICU.GRPAL0.BIT.IS21) + { + /* BSP_INT_SRC_AL0_RSPI2_SPEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS20 */ + if (1 == ICU.GRPAL0.BIT.IS20) + { + /* BSP_INT_SRC_AL0_RSPI2_SPII2 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI2_SPII2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS23 */ + if (1 == ICU.GRPAL0.BIT.IS23) + { + /* BSP_INT_SRC_AL0_SCI7_ERI7 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI7_ERI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS22 */ + if (1 == ICU.GRPAL0.BIT.IS22) + { + /* BSP_INT_SRC_AL0_SCI7_TEI7 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_SCI7_TEI7, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al1_handler_isr +* Description : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al1_handler_isr (void) +{ + /* AL1 IS0 */ + if (1 == ICU.GRPAL1.BIT.IS0) + { + /* BSP_INT_SRC_AL1_EPTPC_MINT */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EPTPC_MINT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS1 */ + if (1 == ICU.GRPAL1.BIT.IS1) + { + /* BSP_INT_SRC_AL1_PTPEDMAC_PINT */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_PTPEDMAC_PINT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS4 */ + if (1 == ICU.GRPAL1.BIT.IS4) + { + /* BSP_INT_SRC_AL1_EDMAC0_EINT0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC0_EINT0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS5 */ + if (1 == ICU.GRPAL1.BIT.IS5) + { + /* BSP_INT_SRC_AL1_EDMAC1_EINT1 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_EDMAC1_EINT1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS9 */ + if (1 == ICU.GRPAL1.BIT.IS9) + { + /* BSP_INT_SRC_AL1_GLCDC_GR1UF */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR1UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS10 */ + if (1 == ICU.GRPAL1.BIT.IS10) + { + /* BSP_INT_SRC_AL1_GLCDC_GR2UF */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_GR2UF, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS8 */ + if (1 == ICU.GRPAL1.BIT.IS8) + { + /* BSP_INT_SRC_AL1_GLCDC_VPOS */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_GLCDC_VPOS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL1 IS11 */ + if (1 == ICU.GRPAL1.BIT.IS11) + { + /* BSP_INT_SRC_AL1_DRW2D_DRW_IRQ */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_ie0_handler_isr +* Description : Interrupt handler for Group IE0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_ie0_handler_isr (void) +{ + /* IE0 IS0 */ + if (1 == ICU.GRPIE0.BIT.IS0) + { + /* Clear the interrupt status flag. */ + ICU.GCRIE0.BIT.CLR0 = 1; + + /* BSP_INT_SRC_IE0_DPFPU_DPFPUEX */ + R_BSP_InterruptControl(BSP_INT_SRC_IE0_DPFPU_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_ie0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_be0_handler_isr +* Description : Interrupt handler for Group BE0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_be0_handler_isr (void) +{ + /* BE0 IS0 */ + if (1 == ICU.GRPBE0.BIT.IS0) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR0 = 1; + + /* BSP_INT_SRC_BE0_CAN0_ERS0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN0_ERS0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BE0 IS1 */ + if (1 == ICU.GRPBE0.BIT.IS1) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR1 = 1; + + /* BSP_INT_SRC_BE0_CAN1_ERS1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN1_ERS1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BE0 IS2 */ + if (1 == ICU.GRPBE0.BIT.IS2) + { + /* Clear the interrupt status flag. */ + ICU.GCRBE0.BIT.CLR2 = 1; + + /* BSP_INT_SRC_BE0_CAN2_ERS2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BE0_CAN2_ERS2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_be0_handler_isr() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h new file mode 100644 index 000000000..14c6960d4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_interrupts.h @@ -0,0 +1,230 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_GROUP_STILL_ENABLED, /* Not all group interrupts were disabled so group interrupt was not + disabled */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_EXC_FPU, /* FPU exception */ + BSP_INT_SRC_EXC_ACCESS, /* Access exception */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_WDT_ERROR, /* WDT underflow/refresh error has occurred */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_RAM, /* RAM error interrupt */ + BSP_INT_SRC_EXRAM, /* EXRAM error interrupt */ + BSP_INT_SRC_ECCRAM_1BIT, /* ECCRAM 1-bit error interrupt */ + BSP_INT_SRC_ECCRAM_2BIT, /* ECCRAM 2-bit error interrupt */ + BSP_INT_SRC_DPFPUEX, /* Double-Precision Floating-Point Exception interrupt */ + + BSP_INT_SRC_GR_INT_TOP, + + /* IE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_IE0_TOP, + BSP_INT_SRC_IE0_DPFPU_DPFPUEX, + + /* BE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_BE0_TOP, + BSP_INT_SRC_BE0_CAN0_ERS0, + BSP_INT_SRC_BE0_CAN1_ERS1, + BSP_INT_SRC_BE0_CAN2_ERS2, + + /* BL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL0_TOP, + BSP_INT_SRC_BL0_SCI0_TEI0, + BSP_INT_SRC_BL0_SCI0_ERI0, + BSP_INT_SRC_BL0_SCI1_TEI1, + BSP_INT_SRC_BL0_SCI1_ERI1, + BSP_INT_SRC_BL0_SCI2_TEI2, + BSP_INT_SRC_BL0_SCI2_ERI2, + BSP_INT_SRC_BL0_SCI3_TEI3, + BSP_INT_SRC_BL0_SCI3_ERI3, + BSP_INT_SRC_BL0_SCI4_TEI4, + BSP_INT_SRC_BL0_SCI4_ERI4, + BSP_INT_SRC_BL0_SCI5_TEI5, + BSP_INT_SRC_BL0_SCI5_ERI5, + BSP_INT_SRC_BL0_SCI6_TEI6, + BSP_INT_SRC_BL0_SCI6_ERI6, + BSP_INT_SRC_BL0_SCI12_TEI12, + BSP_INT_SRC_BL0_SCI12_ERI12, + BSP_INT_SRC_BL0_SCI12_SCIX0, + BSP_INT_SRC_BL0_SCI12_SCIX1, + BSP_INT_SRC_BL0_SCI12_SCIX2, + BSP_INT_SRC_BL0_SCI12_SCIX3, + BSP_INT_SRC_BL0_QSPI_QSPSSLI, + BSP_INT_SRC_BL0_CAC_FERRI, + BSP_INT_SRC_BL0_CAC_MENDI, + BSP_INT_SRC_BL0_CAC_OVFI, + BSP_INT_SRC_BL0_DOC_DOPCI, + BSP_INT_SRC_BL0_PDC_PCFEI, + BSP_INT_SRC_BL0_PDC_PCERI, + + /* BL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL1_TOP, + BSP_INT_SRC_BL1_SDHI_CDETI, + BSP_INT_SRC_BL1_SDHI_CACI, + BSP_INT_SRC_BL1_SDHI_SDACI, + BSP_INT_SRC_BL1_MMCIF_CDETIO, + BSP_INT_SRC_BL1_MMCIF_ERRIO, + BSP_INT_SRC_BL1_MMCIF_ACCIO, + BSP_INT_SRC_BL1_POE3_OEI1, + BSP_INT_SRC_BL1_POE3_OEI2, + BSP_INT_SRC_BL1_POE3_OEI3, + BSP_INT_SRC_BL1_POE3_OEI4, + BSP_INT_SRC_BL1_RIIC0_TEI0, + BSP_INT_SRC_BL1_RIIC0_EEI0, + BSP_INT_SRC_BL1_RIIC2_TEI2, + BSP_INT_SRC_BL1_RIIC2_EEI2, + BSP_INT_SRC_BL1_SSIE0_SSIF0, + BSP_INT_SRC_BL1_SSIE1_SSIF1, + BSP_INT_SRC_BL1_S12AD0_S12CMPAI, + BSP_INT_SRC_BL1_S12AD0_S12CMPBI, + BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, + BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, + BSP_INT_SRC_BL1_RIIC1_TEI1, + BSP_INT_SRC_BL1_RIIC1_EEI1, + + /* BL2 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL2_TOP, + BSP_INT_SRC_BL2_POEG_POEGGAI, + BSP_INT_SRC_BL2_POEG_POEGGBI, + BSP_INT_SRC_BL2_POEG_POEGGCI, + BSP_INT_SRC_BL2_POEG_POEGGDI, + + /* AL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL0_TOP, + BSP_INT_SRC_AL0_SCI8_TEI8, + BSP_INT_SRC_AL0_SCI8_ERI8, + BSP_INT_SRC_AL0_SCI9_TEI9, + BSP_INT_SRC_AL0_SCI9_ERI9, + BSP_INT_SRC_AL0_SCI10_TEI10, + BSP_INT_SRC_AL0_SCI10_ERI10, + BSP_INT_SRC_AL0_SCI11_TEI11, + BSP_INT_SRC_AL0_SCI11_ERI11, + BSP_INT_SRC_AL0_RSPI0_SPII0, + BSP_INT_SRC_AL0_RSPI0_SPEI0, + BSP_INT_SRC_AL0_RSPI1_SPII1, + BSP_INT_SRC_AL0_RSPI1_SPEI1, + BSP_INT_SRC_AL0_RSPI2_SPII2, + BSP_INT_SRC_AL0_RSPI2_SPEI2, + BSP_INT_SRC_AL0_SCI7_TEI7, + BSP_INT_SRC_AL0_SCI7_ERI7, + + /* AL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL1_TOP, + BSP_INT_SRC_AL1_EPTPC_MINT, + BSP_INT_SRC_AL1_PTPEDMAC_PINT, + BSP_INT_SRC_AL1_EDMAC0_EINT0, + BSP_INT_SRC_AL1_EDMAC1_EINT1, + BSP_INT_SRC_AL1_GLCDC_VPOS, + BSP_INT_SRC_AL1_GLCDC_GR1UF, + BSP_INT_SRC_AL1_GLCDC_GR2UF, + BSP_INT_SRC_AL1_DRW2D_DRW_IRQ, + + BSP_INT_SRC_GR_INT_END, + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for FPU, and Bus Error) */ + BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, /* Enables a group interrupt when a group interrupt source is given. The + pdata argument should give the IPL to be used using the bsp_int_ctrl_t + type. If a group interrupt is enabled multiple times with different IPL + levels it will use the highest given IPL. */ + BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, /* Disables a group interrupt when a group interrupt source is given. + This will only disable a group interrupt when all interrupt + sources for that group are already disabled. */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h new file mode 100644 index 000000000..c3fadfc4a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_locks.h @@ -0,0 +1,211 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.h +* Device(s) : RX72N +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_LOCKS_H +#define MCU_LOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you + will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not + using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */ +typedef enum +{ + BSP_LOCK_BSC = 0, + BSP_LOCK_CAC, + BSP_LOCK_CAN0, + BSP_LOCK_CAN1, + BSP_LOCK_CAN2, + BSP_LOCK_CMT, + BSP_LOCK_CMT0, + BSP_LOCK_CMT1, + BSP_LOCK_CMT2, + BSP_LOCK_CMT3, + BSP_LOCK_CMTW0, + BSP_LOCK_CMTW1, + BSP_LOCK_CRC, + BSP_LOCK_DA, + BSP_LOCK_DMAC, + BSP_LOCK_DMAC0, + BSP_LOCK_DMAC1, + BSP_LOCK_DMAC2, + BSP_LOCK_DMAC3, + BSP_LOCK_DMAC4, + BSP_LOCK_DMAC5, + BSP_LOCK_DMAC6, + BSP_LOCK_DMAC7, + BSP_LOCK_DOC, + BSP_LOCK_DRW2D, + BSP_LOCK_DTC, + BSP_LOCK_ECCRAM, + BSP_LOCK_EDMAC0, + BSP_LOCK_EDMAC1, + BSP_LOCK_ELC, + BSP_LOCK_EPTPC, + BSP_LOCK_EPTPC0, + BSP_LOCK_EPTPC1, + BSP_LOCK_ETHERC0, + BSP_LOCK_ETHERC1, + BSP_LOCK_EXDMAC, + BSP_LOCK_EXDMAC0, + BSP_LOCK_EXDMAC1, + BSP_LOCK_FLASH, + BSP_LOCK_GLCDC, + BSP_LOCK_GPTW0, + BSP_LOCK_GPTW1, + BSP_LOCK_GPTW2, + BSP_LOCK_GPTW3, + BSP_LOCK_IRQ0, + BSP_LOCK_IRQ1, + BSP_LOCK_IRQ2, + BSP_LOCK_IRQ3, + BSP_LOCK_IRQ4, + BSP_LOCK_IRQ5, + BSP_LOCK_IRQ6, + BSP_LOCK_IRQ7, + BSP_LOCK_IRQ8, + BSP_LOCK_IRQ9, + BSP_LOCK_IRQ10, + BSP_LOCK_IRQ11, + BSP_LOCK_IRQ12, + BSP_LOCK_IRQ13, + BSP_LOCK_IRQ14, + BSP_LOCK_IRQ15, + BSP_LOCK_ICU, + BSP_LOCK_IWDT, + BSP_LOCK_MMC, + BSP_LOCK_MPC, + BSP_LOCK_MPU, + BSP_LOCK_MTU, + BSP_LOCK_MTU0, + BSP_LOCK_MTU1, + BSP_LOCK_MTU2, + BSP_LOCK_MTU3, + BSP_LOCK_MTU4, + BSP_LOCK_MTU5, + BSP_LOCK_MTU6, + BSP_LOCK_MTU7, + BSP_LOCK_MTU8, + BSP_LOCK_PDC, + BSP_LOCK_PMGI0, + BSP_LOCK_PMGI1, + BSP_LOCK_POE, + BSP_LOCK_POEG, + BSP_LOCK_PPG0, + BSP_LOCK_PPG1, + BSP_LOCK_PTPEDMAC, + BSP_LOCK_QSPI, + BSP_LOCK_RAM, + BSP_LOCK_RIIC0, + BSP_LOCK_RIIC1, + BSP_LOCK_RIIC2, + BSP_LOCK_RSPI0, + BSP_LOCK_RSPI1, + BSP_LOCK_RSPI2, + BSP_LOCK_RTC, + BSP_LOCK_S12AD, + BSP_LOCK_S12AD1, + BSP_LOCK_SCI0, + BSP_LOCK_SCI1, + BSP_LOCK_SCI2, + BSP_LOCK_SCI3, + BSP_LOCK_SCI4, + BSP_LOCK_SCI5, + BSP_LOCK_SCI6, + BSP_LOCK_SCI7, + BSP_LOCK_SCI8, + BSP_LOCK_SCI9, + BSP_LOCK_SCI10, + BSP_LOCK_SCI11, + BSP_LOCK_SCI12, + BSP_LOCK_SDHI, + BSP_LOCK_SSIE0, + BSP_LOCK_SSIE1, + BSP_LOCK_SYSTEM, + BSP_LOCK_TEMPS, + BSP_LOCK_TMR0, + BSP_LOCK_TMR1, + BSP_LOCK_TMR2, + BSP_LOCK_TMR3, + BSP_LOCK_TMR01, + BSP_LOCK_TMR23, + BSP_LOCK_TPU0, + BSP_LOCK_TPU1, + BSP_LOCK_TPU2, + BSP_LOCK_TPU3, + BSP_LOCK_TPU4, + BSP_LOCK_TPU5, + BSP_LOCK_TPUA, + BSP_LOCK_USB, + BSP_LOCK_USB0, + BSP_LOCK_WDT, + BSP_LOCK_FLASHCONST, + BSP_LOCK_TEMPSCONST, + BSP_LOCK_SWINT, + BSP_LOCK_SWINT2, + BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch! +} mcu_lock_t; + +typedef struct +{ + /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */ + int32_t lock; + + /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */ +} bsp_lock_t; + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 +#undef BSP_CFG_USER_LOCKING_TYPE +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t +#else + #if !defined(BSP_CFG_USER_LOCKING_TYPE) + #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h." + #endif +#endif + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[]; + +#endif /* MCU_LOCKS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c new file mode 100644 index 000000000..5d26263b2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.c @@ -0,0 +1,877 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_mapped_interrupt_open +* Description : Initializes mapped interrupts. This code does the following for each possible mapped interrupt: +* 1) PREPROCCESOR - Test to see if this interrupt is chosen to be used +* 2) PREPROCESSOR - Figure out which interrupt select register needs to be written to +* 3) RUNTIME C - Set the appropriate select register with the number of this mapped interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open (void) +{ +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) = BSP_PRV_INT_B_NUM_CMT2_CMI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) = BSP_PRV_INT_B_NUM_CMT3_CMI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) = BSP_PRV_INT_B_NUM_TMR0_CMIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) = BSP_PRV_INT_B_NUM_TMR0_CMIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) = BSP_PRV_INT_B_NUM_TMR0_OVI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) = BSP_PRV_INT_B_NUM_TMR1_CMIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) = BSP_PRV_INT_B_NUM_TMR1_CMIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) = BSP_PRV_INT_B_NUM_TMR1_OVI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) = BSP_PRV_INT_B_NUM_TMR2_CMIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) = BSP_PRV_INT_B_NUM_TMR2_CMIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) = BSP_PRV_INT_B_NUM_TMR2_OVI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) = BSP_PRV_INT_B_NUM_TMR3_CMIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) = BSP_PRV_INT_B_NUM_TMR3_CMIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) = BSP_PRV_INT_B_NUM_TMR3_OVI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) = BSP_PRV_INT_B_NUM_TPU0_TGI0A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) = BSP_PRV_INT_B_NUM_TPU0_TGI0B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) = BSP_PRV_INT_B_NUM_TPU0_TGI0C; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) = BSP_PRV_INT_B_NUM_TPU0_TGI0D; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) = BSP_PRV_INT_B_NUM_TPU0_TCI0V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) = BSP_PRV_INT_B_NUM_TPU1_TGI1A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) = BSP_PRV_INT_B_NUM_TPU1_TGI1B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) = BSP_PRV_INT_B_NUM_TPU1_TCI1V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) = BSP_PRV_INT_B_NUM_TPU1_TCI1U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) = BSP_PRV_INT_B_NUM_TPU2_TGI2A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) = BSP_PRV_INT_B_NUM_TPU2_TGI2B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) = BSP_PRV_INT_B_NUM_TPU2_TCI2V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) = BSP_PRV_INT_B_NUM_TPU2_TCI2U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) = BSP_PRV_INT_B_NUM_TPU3_TGI3A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) = BSP_PRV_INT_B_NUM_TPU3_TGI3B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) = BSP_PRV_INT_B_NUM_TPU3_TGI3C; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) = BSP_PRV_INT_B_NUM_TPU3_TGI3D; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) = BSP_PRV_INT_B_NUM_TPU3_TCI3V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) = BSP_PRV_INT_B_NUM_TPU4_TGI4A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) = BSP_PRV_INT_B_NUM_TPU4_TGI4B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) = BSP_PRV_INT_B_NUM_TPU4_TCI4V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) = BSP_PRV_INT_B_NUM_TPU4_TCI4U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) = BSP_PRV_INT_B_NUM_TPU5_TGI5A; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) = BSP_PRV_INT_B_NUM_TPU5_TGI5B; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) = BSP_PRV_INT_B_NUM_TPU5_TCI5V; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) = BSP_PRV_INT_B_NUM_TPU5_TCI5U; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) = BSP_PRV_INT_B_NUM_CMTW0_IC0I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) = BSP_PRV_INT_B_NUM_CMTW0_IC1I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) = BSP_PRV_INT_B_NUM_CMTW0_OC0I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) = BSP_PRV_INT_B_NUM_CMTW0_OC1I0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) = BSP_PRV_INT_B_NUM_CMTW1_IC0I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) = BSP_PRV_INT_B_NUM_CMTW1_IC1I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) = BSP_PRV_INT_B_NUM_CMTW1_OC0I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) = BSP_PRV_INT_B_NUM_CMTW1_OC1I1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) = BSP_PRV_INT_B_NUM_RTC_CUP; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) = BSP_PRV_INT_B_NUM_CAN0_RXF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) = BSP_PRV_INT_B_NUM_CAN0_TXF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) = BSP_PRV_INT_B_NUM_CAN0_RXM0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) = BSP_PRV_INT_B_NUM_CAN0_TXM0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) = BSP_PRV_INT_B_NUM_CAN1_RXF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) = BSP_PRV_INT_B_NUM_CAN1_TXF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) = BSP_PRV_INT_B_NUM_CAN1_RXM1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) = BSP_PRV_INT_B_NUM_CAN1_TXM1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) = BSP_PRV_INT_B_NUM_CAN2_RXF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) = BSP_PRV_INT_B_NUM_CAN2_TXF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) = BSP_PRV_INT_B_NUM_CAN2_RXM2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) = BSP_PRV_INT_B_NUM_CAN2_TXM2; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) = BSP_PRV_INT_B_NUM_USB0_USBI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) = BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) = BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) = BSP_PRV_INT_B_NUM_ELC_ELSR18I; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) = BSP_PRV_INT_B_NUM_ELC_ELSR19I; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) = BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) = BSP_PRV_INT_B_NUM_TSIP_ROMOK; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) = BSP_PRV_INT_B_NUM_TSIP_LONG_PLG; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) = BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) = BSP_PRV_INT_B_NUM_TSIP_WRRDY0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) = BSP_PRV_INT_B_NUM_TSIP_WRRDY1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) = BSP_PRV_INT_B_NUM_TSIP_WRRDY4; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) = BSP_PRV_INT_B_NUM_TSIP_RDRDY0; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) = BSP_PRV_INT_B_NUM_TSIP_RDRDY1; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY; +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) = BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) = BSP_PRV_INT_A_NUM_MTU0_TGIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) = BSP_PRV_INT_A_NUM_MTU0_TGIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) = BSP_PRV_INT_A_NUM_MTU0_TGIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) = BSP_PRV_INT_A_NUM_MTU0_TGID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) = BSP_PRV_INT_A_NUM_MTU0_TCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) = BSP_PRV_INT_A_NUM_MTU0_TGIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) = BSP_PRV_INT_A_NUM_MTU0_TGIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) = BSP_PRV_INT_A_NUM_MTU1_TGIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) = BSP_PRV_INT_A_NUM_MTU1_TGIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) = BSP_PRV_INT_A_NUM_MTU1_TCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) = BSP_PRV_INT_A_NUM_MTU1_TCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) = BSP_PRV_INT_A_NUM_MTU2_TGIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) = BSP_PRV_INT_A_NUM_MTU2_TGIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) = BSP_PRV_INT_A_NUM_MTU2_TCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) = BSP_PRV_INT_A_NUM_MTU2_TCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) = BSP_PRV_INT_A_NUM_MTU3_TGIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) = BSP_PRV_INT_A_NUM_MTU3_TGIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) = BSP_PRV_INT_A_NUM_MTU3_TGIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) = BSP_PRV_INT_A_NUM_MTU3_TGID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) = BSP_PRV_INT_A_NUM_MTU3_TCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) = BSP_PRV_INT_A_NUM_MTU4_TGIA4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) = BSP_PRV_INT_A_NUM_MTU4_TGIB4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) = BSP_PRV_INT_A_NUM_MTU4_TGIC4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) = BSP_PRV_INT_A_NUM_MTU4_TGID4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) = BSP_PRV_INT_A_NUM_MTU4_TCIV4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) = BSP_PRV_INT_A_NUM_MTU5_TGIU5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) = BSP_PRV_INT_A_NUM_MTU5_TGIV5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) = BSP_PRV_INT_A_NUM_MTU5_TGIW5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) = BSP_PRV_INT_A_NUM_MTU6_TGIA6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) = BSP_PRV_INT_A_NUM_MTU6_TGIB6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) = BSP_PRV_INT_A_NUM_MTU6_TGIC6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) = BSP_PRV_INT_A_NUM_MTU6_TGID6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) = BSP_PRV_INT_A_NUM_MTU6_TCIV6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) = BSP_PRV_INT_A_NUM_MTU7_TGIA7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) = BSP_PRV_INT_A_NUM_MTU7_TGIB7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) = BSP_PRV_INT_A_NUM_MTU7_TGIC7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) = BSP_PRV_INT_A_NUM_MTU7_TGID7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) = BSP_PRV_INT_A_NUM_MTU7_TCIV7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) = BSP_PRV_INT_A_NUM_MTU8_TGIA8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) = BSP_PRV_INT_A_NUM_MTU8_TGIB8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) = BSP_PRV_INT_A_NUM_MTU8_TGIC8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) = BSP_PRV_INT_A_NUM_MTU8_TGID8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) = BSP_PRV_INT_A_NUM_MTU8_TCIV8; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) = BSP_PRV_INT_A_NUM_GPTW0_GTCID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) = BSP_PRV_INT_A_NUM_GPTW0_GDTE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIU0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIC1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) = BSP_PRV_INT_A_NUM_GPTW1_GTCID1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) = BSP_PRV_INT_A_NUM_GPTW1_GDTE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIC2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) = BSP_PRV_INT_A_NUM_GPTW2_GTCID2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) = BSP_PRV_INT_A_NUM_GPTW2_GDTE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) = BSP_PRV_INT_A_NUM_GPTW3_GTCID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) = BSP_PRV_INT_A_NUM_GPTW3_GDTE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIF3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIU3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) = BSP_PRV_INT_A_NUM_EPTPC_IPLS; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) = BSP_PRV_INT_A_NUM_PMGI0_PMGI0I; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) = BSP_PRV_INT_A_NUM_PMGI1_PMGI1I; +#endif +} /* End of function bsp_mapped_interrupt_open() */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h new file mode 100644 index 000000000..aed97bbcd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts.h @@ -0,0 +1,1692 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A & B interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_H +#define MCU_MAPPED_INTERRUPTS_H + +/* The following macros define the number for each interrupt request source as it pertains to being an Interrupt B or + * Interrupt A interrupt. These values are used when setting the interrupt select registers (i.e. SLIBXRn, SLIBrn, and + * SLIARn). + */ +/* Available Interrupt B Sources. */ +#define BSP_PRV_INT_B_NUM_CMT2_CMI2 1 +#define BSP_PRV_INT_B_NUM_CMT3_CMI3 2 +#define BSP_PRV_INT_B_NUM_TMR0_CMIA0 3 +#define BSP_PRV_INT_B_NUM_TMR0_CMIB0 4 +#define BSP_PRV_INT_B_NUM_TMR0_OVI0 5 +#define BSP_PRV_INT_B_NUM_TMR1_CMIA1 6 +#define BSP_PRV_INT_B_NUM_TMR1_CMIB1 7 +#define BSP_PRV_INT_B_NUM_TMR1_OVI1 8 +#define BSP_PRV_INT_B_NUM_TMR2_CMIA2 9 +#define BSP_PRV_INT_B_NUM_TMR2_CMIB2 10 +#define BSP_PRV_INT_B_NUM_TMR2_OVI2 11 +#define BSP_PRV_INT_B_NUM_TMR3_CMIA3 12 +#define BSP_PRV_INT_B_NUM_TMR3_CMIB3 13 +#define BSP_PRV_INT_B_NUM_TMR3_OVI3 14 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0A 15 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0B 16 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0C 17 +#define BSP_PRV_INT_B_NUM_TPU0_TGI0D 18 +#define BSP_PRV_INT_B_NUM_TPU0_TCI0V 19 +#define BSP_PRV_INT_B_NUM_TPU1_TGI1A 20 +#define BSP_PRV_INT_B_NUM_TPU1_TGI1B 21 +#define BSP_PRV_INT_B_NUM_TPU1_TCI1V 22 +#define BSP_PRV_INT_B_NUM_TPU1_TCI1U 23 +#define BSP_PRV_INT_B_NUM_TPU2_TGI2A 24 +#define BSP_PRV_INT_B_NUM_TPU2_TGI2B 25 +#define BSP_PRV_INT_B_NUM_TPU2_TCI2V 26 +#define BSP_PRV_INT_B_NUM_TPU2_TCI2U 27 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3A 28 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3B 29 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3C 30 +#define BSP_PRV_INT_B_NUM_TPU3_TGI3D 31 +#define BSP_PRV_INT_B_NUM_TPU3_TCI3V 32 +#define BSP_PRV_INT_B_NUM_TPU4_TGI4A 33 +#define BSP_PRV_INT_B_NUM_TPU4_TGI4B 34 +#define BSP_PRV_INT_B_NUM_TPU4_TCI4V 35 +#define BSP_PRV_INT_B_NUM_TPU4_TCI4U 36 +#define BSP_PRV_INT_B_NUM_TPU5_TGI5A 37 +#define BSP_PRV_INT_B_NUM_TPU5_TGI5B 38 +#define BSP_PRV_INT_B_NUM_TPU5_TCI5V 39 +#define BSP_PRV_INT_B_NUM_TPU5_TCI5U 40 +#define BSP_PRV_INT_B_NUM_CMTW0_IC0I0 41 +#define BSP_PRV_INT_B_NUM_CMTW0_IC1I0 42 +#define BSP_PRV_INT_B_NUM_CMTW0_OC0I0 43 +#define BSP_PRV_INT_B_NUM_CMTW0_OC1I0 44 +#define BSP_PRV_INT_B_NUM_CMTW1_IC0I1 45 +#define BSP_PRV_INT_B_NUM_CMTW1_IC1I1 46 +#define BSP_PRV_INT_B_NUM_CMTW1_OC0I1 47 +#define BSP_PRV_INT_B_NUM_CMTW1_OC1I1 48 +#define BSP_PRV_INT_B_NUM_RTC_CUP 49 +#define BSP_PRV_INT_B_NUM_CAN0_RXF0 50 +#define BSP_PRV_INT_B_NUM_CAN0_TXF0 51 +#define BSP_PRV_INT_B_NUM_CAN0_RXM0 52 +#define BSP_PRV_INT_B_NUM_CAN0_TXM0 53 +#define BSP_PRV_INT_B_NUM_CAN1_RXF1 54 +#define BSP_PRV_INT_B_NUM_CAN1_TXF1 55 +#define BSP_PRV_INT_B_NUM_CAN1_RXM1 56 +#define BSP_PRV_INT_B_NUM_CAN1_TXM1 57 +#define BSP_PRV_INT_B_NUM_CAN2_RXF2 58 +#define BSP_PRV_INT_B_NUM_CAN2_TXF2 59 +#define BSP_PRV_INT_B_NUM_CAN2_RXM2 60 +#define BSP_PRV_INT_B_NUM_CAN2_TXM2 61 +#define BSP_PRV_INT_B_NUM_USB0_USBI0 62 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12ADI0 64 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12GBADI0 65 +#define BSP_PRV_INT_B_NUM_S12ADC0_S12GCADI0 66 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12ADI1 68 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12GBADI1 69 +#define BSP_PRV_INT_B_NUM_S12ADC1_S12GCADI1 70 +#define BSP_PRV_INT_B_NUM_ELC_ELSR18I 79 +#define BSP_PRV_INT_B_NUM_ELC_ELSR19I 80 +#define BSP_PRV_INT_B_NUM_TSIP_PROC_BUSY 85 +#define BSP_PRV_INT_B_NUM_TSIP_ROMOK 86 +#define BSP_PRV_INT_B_NUM_TSIP_LONG_PLG 87 +#define BSP_PRV_INT_B_NUM_TSIP_TEST_BUSY 88 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY0 89 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY1 90 +#define BSP_PRV_INT_B_NUM_TSIP_WRRDY4 91 +#define BSP_PRV_INT_B_NUM_TSIP_RDRDY0 92 +#define BSP_PRV_INT_B_NUM_TSIP_RDRDY1 93 +#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_WRRDY 94 +#define BSP_PRV_INT_B_NUM_TSIP_INTEGRATE_RDRDY 95 + +/* Available Interrupt A Sources. */ +#define BSP_PRV_INT_A_NUM_MTU0_TGIA0 1 +#define BSP_PRV_INT_A_NUM_MTU0_TGIB0 2 +#define BSP_PRV_INT_A_NUM_MTU0_TGIC0 3 +#define BSP_PRV_INT_A_NUM_MTU0_TGID0 4 +#define BSP_PRV_INT_A_NUM_MTU0_TCIV0 5 +#define BSP_PRV_INT_A_NUM_MTU0_TGIE0 6 +#define BSP_PRV_INT_A_NUM_MTU0_TGIF0 7 +#define BSP_PRV_INT_A_NUM_MTU1_TGIA1 8 +#define BSP_PRV_INT_A_NUM_MTU1_TGIB1 9 +#define BSP_PRV_INT_A_NUM_MTU1_TCIV1 10 +#define BSP_PRV_INT_A_NUM_MTU1_TCIU1 11 +#define BSP_PRV_INT_A_NUM_MTU2_TGIA2 12 +#define BSP_PRV_INT_A_NUM_MTU2_TGIB2 13 +#define BSP_PRV_INT_A_NUM_MTU2_TCIV2 14 +#define BSP_PRV_INT_A_NUM_MTU2_TCIU2 15 +#define BSP_PRV_INT_A_NUM_MTU3_TGIA3 16 +#define BSP_PRV_INT_A_NUM_MTU3_TGIB3 17 +#define BSP_PRV_INT_A_NUM_MTU3_TGIC3 18 +#define BSP_PRV_INT_A_NUM_MTU3_TGID3 19 +#define BSP_PRV_INT_A_NUM_MTU3_TCIV3 20 +#define BSP_PRV_INT_A_NUM_MTU4_TGIA4 21 +#define BSP_PRV_INT_A_NUM_MTU4_TGIB4 22 +#define BSP_PRV_INT_A_NUM_MTU4_TGIC4 23 +#define BSP_PRV_INT_A_NUM_MTU4_TGID4 24 +#define BSP_PRV_INT_A_NUM_MTU4_TCIV4 25 +#define BSP_PRV_INT_A_NUM_MTU5_TGIU5 27 +#define BSP_PRV_INT_A_NUM_MTU5_TGIV5 28 +#define BSP_PRV_INT_A_NUM_MTU5_TGIW5 29 +#define BSP_PRV_INT_A_NUM_MTU6_TGIA6 30 +#define BSP_PRV_INT_A_NUM_MTU6_TGIB6 31 +#define BSP_PRV_INT_A_NUM_MTU6_TGIC6 32 +#define BSP_PRV_INT_A_NUM_MTU6_TGID6 33 +#define BSP_PRV_INT_A_NUM_MTU6_TCIV6 34 +#define BSP_PRV_INT_A_NUM_MTU7_TGIA7 35 +#define BSP_PRV_INT_A_NUM_MTU7_TGIB7 36 +#define BSP_PRV_INT_A_NUM_MTU7_TGIC7 37 +#define BSP_PRV_INT_A_NUM_MTU7_TGID7 38 +#define BSP_PRV_INT_A_NUM_MTU7_TCIV7 39 +#define BSP_PRV_INT_A_NUM_MTU8_TGIA8 41 +#define BSP_PRV_INT_A_NUM_MTU8_TGIB8 42 +#define BSP_PRV_INT_A_NUM_MTU8_TGIC8 43 +#define BSP_PRV_INT_A_NUM_MTU8_TGID8 44 +#define BSP_PRV_INT_A_NUM_MTU8_TCIV8 45 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIA0 47 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIB0 48 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIC0 49 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCID0 50 +#define BSP_PRV_INT_A_NUM_GPTW0_GDTE0 51 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIE0 52 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIF0 53 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIV0 54 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIU0 55 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIA1 58 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIB1 59 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIC1 60 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCID1 61 +#define BSP_PRV_INT_A_NUM_GPTW1_GDTE1 62 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIE1 63 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIF1 64 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIV1 65 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIU1 66 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIA2 67 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIB2 68 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIC2 69 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCID2 70 +#define BSP_PRV_INT_A_NUM_GPTW2_GDTE2 71 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIE2 72 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIF2 73 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIV2 74 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIU2 75 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIA3 76 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIB3 77 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIC3 78 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCID3 79 +#define BSP_PRV_INT_A_NUM_GPTW3_GDTE3 80 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIE3 81 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIF3 82 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIV3 83 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIU3 84 +#define BSP_PRV_INT_A_NUM_EPTPC_IPLS 86 +#define BSP_PRV_INT_A_NUM_PMGI0_PMGI0I 98 +#define BSP_PRV_INT_A_NUM_PMGI1_PMGI1I 99 + +/* The appropriate macros will now be defined based on the vector selections made by the user. + * These are the same macros that are defined for constant-mapped interrupts (vectors 0-127). This means that the + * code can define, setup, and use mapped interrupts the same as would be done for constant-mapped interrupts. + */ +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IR_CMT2_CMI2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define DTCE_CMT2_CMI2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IER_CMT2_CMI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IPR_CMT2_CMI2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define IEN_CMT2_CMI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#define VECT_CMT2_CMI2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IR_CMT3_CMI3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define DTCE_CMT3_CMI3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IER_CMT3_CMI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IPR_CMT3_CMI3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define IEN_CMT3_CMI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#define VECT_CMT3_CMI3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IR_TPU0_TGI0A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define DTCE_TPU0_TGI0A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IER_TPU0_TGI0A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IPR_TPU0_TGI0A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define IEN_TPU0_TGI0A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#define VECT_TPU0_TGI0A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IR_TPU0_TGI0B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define DTCE_TPU0_TGI0B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IER_TPU0_TGI0B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IPR_TPU0_TGI0B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define IEN_TPU0_TGI0B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#define VECT_TPU0_TGI0B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IR_TPU0_TGI0C BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define DTCE_TPU0_TGI0C BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IER_TPU0_TGI0C BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IPR_TPU0_TGI0C BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define IEN_TPU0_TGI0C BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#define VECT_TPU0_TGI0C BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IR_TPU0_TGI0D BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define DTCE_TPU0_TGI0D BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IER_TPU0_TGI0D BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IPR_TPU0_TGI0D BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define IEN_TPU0_TGI0D BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#define VECT_TPU0_TGI0D BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IR_TPU0_TCI0V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define DTCE_TPU0_TCI0V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IER_TPU0_TCI0V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IPR_TPU0_TCI0V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define IEN_TPU0_TCI0V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#define VECT_TPU0_TCI0V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IR_TPU1_TGI1B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define DTCE_TPU1_TGI1B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IER_TPU1_TGI1B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IPR_TPU1_TGI1B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define IEN_TPU1_TGI1B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#define VECT_TPU1_TGI1B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IR_TPU1_TCI1V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define DTCE_TPU1_TCI1V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IER_TPU1_TCI1V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IPR_TPU1_TCI1V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define IEN_TPU1_TCI1V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#define VECT_TPU1_TCI1V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IR_TPU1_TCI1U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define DTCE_TPU1_TCI1U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IER_TPU1_TCI1U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IPR_TPU1_TCI1U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define IEN_TPU1_TCI1U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#define VECT_TPU1_TCI1U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IR_TPU2_TGI2A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define DTCE_TPU2_TGI2A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IER_TPU2_TGI2A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IPR_TPU2_TGI2A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define IEN_TPU2_TGI2A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#define VECT_TPU2_TGI2A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IR_TPU2_TGI2B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define DTCE_TPU2_TGI2B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IER_TPU2_TGI2B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IPR_TPU2_TGI2B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define IEN_TPU2_TGI2B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#define VECT_TPU2_TGI2B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IR_TPU2_TCI2V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define DTCE_TPU2_TCI2V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IER_TPU2_TCI2V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IPR_TPU2_TCI2V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define IEN_TPU2_TCI2V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#define VECT_TPU2_TCI2V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IR_TPU2_TCI2U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define DTCE_TPU2_TCI2U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IER_TPU2_TCI2U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IPR_TPU2_TCI2U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define IEN_TPU2_TCI2U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#define VECT_TPU2_TCI2U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IR_TPU3_TGI3A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define DTCE_TPU3_TGI3A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IER_TPU3_TGI3A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IPR_TPU3_TGI3A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define IEN_TPU3_TGI3A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#define VECT_TPU3_TGI3A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IR_TPU3_TGI3B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define DTCE_TPU3_TGI3B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IER_TPU3_TGI3B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IPR_TPU3_TGI3B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define IEN_TPU3_TGI3B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#define VECT_TPU3_TGI3B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IR_TPU1_TGI1A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define DTCE_TPU1_TGI1A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IER_TPU1_TGI1A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IPR_TPU1_TGI1A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define IEN_TPU1_TGI1A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#define VECT_TPU1_TGI1A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IR_TPU3_TGI3C BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define DTCE_TPU3_TGI3C BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IER_TPU3_TGI3C BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IPR_TPU3_TGI3C BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define IEN_TPU3_TGI3C BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#define VECT_TPU3_TGI3C BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IR_TMR0_CMIA0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define DTCE_TMR0_CMIA0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IER_TMR0_CMIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IPR_TMR0_CMIA0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define IEN_TMR0_CMIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#define VECT_TMR0_CMIA0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IR_TMR0_CMIB0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define DTCE_TMR0_CMIB0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IER_TMR0_CMIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IPR_TMR0_CMIB0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define IEN_TMR0_CMIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#define VECT_TMR0_CMIB0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IR_TMR0_OVI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define DTCE_TMR0_OVI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IER_TMR0_OVI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IPR_TMR0_OVI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define IEN_TMR0_OVI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#define VECT_TMR0_OVI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IR_TMR1_CMIA1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define DTCE_TMR1_CMIA1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IER_TMR1_CMIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IPR_TMR1_CMIA1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define IEN_TMR1_CMIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#define VECT_TMR1_CMIA1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IR_TMR1_CMIB1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define DTCE_TMR1_CMIB1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IER_TMR1_CMIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IPR_TMR1_CMIB1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define IEN_TMR1_CMIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#define VECT_TMR1_CMIB1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IR_TMR1_OVI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define DTCE_TMR1_OVI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IER_TMR1_OVI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IPR_TMR1_OVI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define IEN_TMR1_OVI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#define VECT_TMR1_OVI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IR_TMR2_CMIA2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define DTCE_TMR2_CMIA2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IER_TMR2_CMIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IPR_TMR2_CMIA2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define IEN_TMR2_CMIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#define VECT_TMR2_CMIA2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IR_TMR2_CMIB2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define DTCE_TMR2_CMIB2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IER_TMR2_CMIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IPR_TMR2_CMIB2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define IEN_TMR2_CMIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#define VECT_TMR2_CMIB2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IR_TMR2_OVI2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define DTCE_TMR2_OVI2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IER_TMR2_OVI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IPR_TMR2_OVI2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define IEN_TMR2_OVI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#define VECT_TMR2_OVI2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IR_TMR3_CMIA3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define DTCE_TMR3_CMIA3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IER_TMR3_CMIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IPR_TMR3_CMIA3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define IEN_TMR3_CMIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#define VECT_TMR3_CMIA3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IR_TMR3_CMIB3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define DTCE_TMR3_CMIB3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IER_TMR3_CMIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IPR_TMR3_CMIB3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define IEN_TMR3_CMIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#define VECT_TMR3_CMIB3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IR_TMR3_OVI3 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define DTCE_TMR3_OVI3 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IER_TMR3_OVI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IPR_TMR3_OVI3 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define IEN_TMR3_OVI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#define VECT_TMR3_OVI3 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IR_TPU3_TGI3D BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define DTCE_TPU3_TGI3D BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IER_TPU3_TGI3D BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IPR_TPU3_TGI3D BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define IEN_TPU3_TGI3D BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#define VECT_TPU3_TGI3D BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IR_TPU3_TCI3V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define DTCE_TPU3_TCI3V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IER_TPU3_TCI3V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IPR_TPU3_TCI3V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define IEN_TPU3_TCI3V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#define VECT_TPU3_TCI3V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IR_TPU4_TGI4A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define DTCE_TPU4_TGI4A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IER_TPU4_TGI4A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IPR_TPU4_TGI4A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define IEN_TPU4_TGI4A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#define VECT_TPU4_TGI4A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IR_TPU4_TGI4B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define DTCE_TPU4_TGI4B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IER_TPU4_TGI4B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IPR_TPU4_TGI4B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define IEN_TPU4_TGI4B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#define VECT_TPU4_TGI4B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IR_TPU4_TCI4V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define DTCE_TPU4_TCI4V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IER_TPU4_TCI4V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IPR_TPU4_TCI4V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define IEN_TPU4_TCI4V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#define VECT_TPU4_TCI4V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IR_TPU4_TCI4U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define DTCE_TPU4_TCI4U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IER_TPU4_TCI4U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IPR_TPU4_TCI4U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define IEN_TPU4_TCI4U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#define VECT_TPU4_TCI4U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IR_TPU5_TGI5A BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define DTCE_TPU5_TGI5A BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IER_TPU5_TGI5A BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IPR_TPU5_TGI5A BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define IEN_TPU5_TGI5A BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#define VECT_TPU5_TGI5A BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IR_TPU5_TGI5B BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define DTCE_TPU5_TGI5B BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IER_TPU5_TGI5B BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IPR_TPU5_TGI5B BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define IEN_TPU5_TGI5B BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#define VECT_TPU5_TGI5B BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IR_TPU5_TCI5V BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define DTCE_TPU5_TCI5V BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IER_TPU5_TCI5V BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IPR_TPU5_TCI5V BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define IEN_TPU5_TCI5V BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#define VECT_TPU5_TCI5V BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IR_TPU5_TCI5U BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define DTCE_TPU5_TCI5U BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IER_TPU5_TCI5U BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IPR_TPU5_TCI5U BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define IEN_TPU5_TCI5U BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#define VECT_TPU5_TCI5U BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IR_CMTW0_IC0I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define DTCE_CMTW0_IC0I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IER_CMTW0_IC0I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IPR_CMTW0_IC0I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define IEN_CMTW0_IC0I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#define VECT_CMTW0_IC0I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IR_CMTW0_IC1I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define DTCE_CMTW0_IC1I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IER_CMTW0_IC1I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IPR_CMTW0_IC1I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define IEN_CMTW0_IC1I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#define VECT_CMTW0_IC1I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IR_CMTW0_OC0I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define DTCE_CMTW0_OC0I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IER_CMTW0_OC0I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IPR_CMTW0_OC0I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define IEN_CMTW0_OC0I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#define VECT_CMTW0_OC0I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IR_CMTW0_OC1I0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define DTCE_CMTW0_OC1I0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IER_CMTW0_OC1I0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IPR_CMTW0_OC1I0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define IEN_CMTW0_OC1I0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#define VECT_CMTW0_OC1I0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IR_CMTW1_IC0I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define DTCE_CMTW1_IC0I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IER_CMTW1_IC0I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IPR_CMTW1_IC0I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define IEN_CMTW1_IC0I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#define VECT_CMTW1_IC0I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IR_CMTW1_IC1I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define DTCE_CMTW1_IC1I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IER_CMTW1_IC1I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IPR_CMTW1_IC1I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define IEN_CMTW1_IC1I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#define VECT_CMTW1_IC1I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IR_CMTW1_OC0I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define DTCE_CMTW1_OC0I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IER_CMTW1_OC0I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IPR_CMTW1_OC0I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define IEN_CMTW1_OC0I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#define VECT_CMTW1_OC0I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IR_CMTW1_OC1I1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define DTCE_CMTW1_OC1I1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IER_CMTW1_OC1I1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IPR_CMTW1_OC1I1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define IEN_CMTW1_OC1I1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#define VECT_CMTW1_OC1I1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IR_RTC_CUP BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define DTCE_RTC_CUP BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IER_RTC_CUP BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IPR_RTC_CUP BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define IEN_RTC_CUP BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#define VECT_RTC_CUP BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IR_CAN0_RXF0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define DTCE_CAN0_RXF0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IER_CAN0_RXF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IPR_CAN0_RXF0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define IEN_CAN0_RXF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#define VECT_CAN0_RXF0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IR_CAN0_TXF0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define DTCE_CAN0_TXF0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IER_CAN0_TXF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IPR_CAN0_TXF0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define IEN_CAN0_TXF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#define VECT_CAN0_TXF0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IR_CAN0_RXM0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define DTCE_CAN0_RXM0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IER_CAN0_RXM0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IPR_CAN0_RXM0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define IEN_CAN0_RXM0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#define VECT_CAN0_RXM0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IR_CAN0_TXM0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define DTCE_CAN0_TXM0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IER_CAN0_TXM0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IPR_CAN0_TXM0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define IEN_CAN0_TXM0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#define VECT_CAN0_TXM0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IR_CAN1_RXF1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define DTCE_CAN1_RXF1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IER_CAN1_RXF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IPR_CAN1_RXF1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define IEN_CAN1_RXF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#define VECT_CAN1_RXF1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IR_CAN1_TXF1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define DTCE_CAN1_TXF1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IER_CAN1_TXF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IPR_CAN1_TXF1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define IEN_CAN1_TXF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#define VECT_CAN1_TXF1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IR_CAN1_RXM1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define DTCE_CAN1_RXM1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IER_CAN1_RXM1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IPR_CAN1_RXM1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define IEN_CAN1_RXM1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#define VECT_CAN1_RXM1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IR_CAN1_TXM1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define DTCE_CAN1_TXM1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IER_CAN1_TXM1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IPR_CAN1_TXM1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define IEN_CAN1_TXM1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#define VECT_CAN1_TXM1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IR_CAN2_RXF2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define DTCE_CAN2_RXF2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IER_CAN2_RXF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IPR_CAN2_RXF2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define IEN_CAN2_RXF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#define VECT_CAN2_RXF2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IR_CAN2_TXF2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define DTCE_CAN2_TXF2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IER_CAN2_TXF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IPR_CAN2_TXF2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define IEN_CAN2_TXF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#define VECT_CAN2_TXF2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IR_CAN2_RXM2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define DTCE_CAN2_RXM2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IER_CAN2_RXM2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IPR_CAN2_RXM2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define IEN_CAN2_RXM2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#define VECT_CAN2_RXM2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IR_CAN2_TXM2 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define DTCE_CAN2_TXM2 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IER_CAN2_TXM2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IPR_CAN2_TXM2 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define IEN_CAN2_TXM2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#define VECT_CAN2_TXM2 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IR_USB0_USBI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define DTCE_USB0_USBI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IER_USB0_USBI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IPR_USB0_USBI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define IEN_USB0_USBI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#define VECT_USB0_USBI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IR_S12ADC0_S12ADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define DTCE_S12ADC0_S12ADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IER_S12ADC0_S12ADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IPR_S12ADC0_S12ADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define IEN_S12ADC0_S12ADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#define VECT_S12ADC0_S12ADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IR_S12ADC0_S12GBADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define DTCE_S12ADC0_S12GBADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IER_S12ADC0_S12GBADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IPR_S12ADC0_S12GBADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define IEN_S12ADC0_S12GBADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#define VECT_S12ADC0_S12GBADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IR_S12ADC0_S12GCADI0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define DTCE_S12ADC0_S12GCADI0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IER_S12ADC0_S12GCADI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IPR_S12ADC0_S12GCADI0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define IEN_S12ADC0_S12GCADI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#define VECT_S12ADC0_S12GCADI0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IR_S12ADC1_S12ADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define DTCE_S12ADC1_S12ADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IER_S12ADC1_S12ADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IPR_S12ADC1_S12ADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define IEN_S12ADC1_S12ADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#define VECT_S12ADC1_S12ADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IR_S12ADC1_S12GBADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define DTCE_S12ADC1_S12GBADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IER_S12ADC1_S12GBADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IPR_S12ADC1_S12GBADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define IEN_S12ADC1_S12GBADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#define VECT_S12ADC1_S12GBADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IR_S12ADC1_S12GCADI1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define DTCE_S12ADC1_S12GCADI1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IER_S12ADC1_S12GCADI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IPR_S12ADC1_S12GCADI1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define IEN_S12ADC1_S12GCADI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#define VECT_S12ADC1_S12GCADI1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IR_ELC_ELSR18I BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define DTCE_ELC_ELSR18I BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IER_ELC_ELSR18I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IPR_ELC_ELSR18I BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define IEN_ELC_ELSR18I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#define VECT_ELC_ELSR18I BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IR_ELC_ELSR19I BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define DTCE_ELC_ELSR19I BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IER_ELC_ELSR19I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IPR_ELC_ELSR19I BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define IEN_ELC_ELSR19I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#define VECT_ELC_ELSR19I BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IR_TSIP_PROC_BUSY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define DTCE_TSIP_PROC_BUSY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IER_TSIP_PROC_BUSY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IPR_TSIP_PROC_BUSY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define IEN_TSIP_PROC_BUSY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#define VECT_TSIP_PROC_BUSY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IR_TSIP_ROMOK BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define DTCE_TSIP_ROMOK BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IER_TSIP_ROMOK BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IPR_TSIP_ROMOK BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define IEN_TSIP_ROMOK BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#define VECT_TSIP_ROMOK BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IR_TSIP_LONG_PLG BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define DTCE_TSIP_LONG_PLG BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IER_TSIP_LONG_PLG BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IPR_TSIP_LONG_PLG BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define IEN_TSIP_LONG_PLG BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#define VECT_TSIP_LONG_PLG BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IR_TSIP_TEST_BUSY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define DTCE_TSIP_TEST_BUSY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IER_TSIP_TEST_BUSY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IPR_TSIP_TEST_BUSY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define IEN_TSIP_TEST_BUSY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#define VECT_TSIP_TEST_BUSY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IR_TSIP_WRRDY0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define DTCE_TSIP_WRRDY0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IER_TSIP_WRRDY0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IPR_TSIP_WRRDY0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define IEN_TSIP_WRRDY0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#define VECT_TSIP_WRRDY0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IR_TSIP_WRRDY1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define DTCE_TSIP_WRRDY1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IER_TSIP_WRRDY1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IPR_TSIP_WRRDY1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define IEN_TSIP_WRRDY1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#define VECT_TSIP_WRRDY1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IR_TSIP_WRRDY4 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define DTCE_TSIP_WRRDY4 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IER_TSIP_WRRDY4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IPR_TSIP_WRRDY4 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define IEN_TSIP_WRRDY4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#define VECT_TSIP_WRRDY4 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IR_TSIP_RDRDY0 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define DTCE_TSIP_RDRDY0 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IER_TSIP_RDRDY0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IPR_TSIP_RDRDY0 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define IEN_TSIP_RDRDY0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#define VECT_TSIP_RDRDY0 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IR_TSIP_RDRDY1 BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define DTCE_TSIP_RDRDY1 BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IER_TSIP_RDRDY1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IPR_TSIP_RDRDY1 BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define IEN_TSIP_RDRDY1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#define VECT_TSIP_RDRDY1 BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IR_TSIP_INTEGRATE_WRRDY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define DTCE_TSIP_INTEGRATE_WRRDY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IER_TSIP_INTEGRATE_WRRDY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IPR_TSIP_INTEGRATE_WRRDY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define IEN_TSIP_INTEGRATE_WRRDY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#define VECT_TSIP_INTEGRATE_WRRDY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY) +#endif + +#if BSP_PRV_VALID_MAP_INT(B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IR_TSIP_INTEGRATE_RDRDY BSP_PRV_IR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define DTCE_TSIP_INTEGRATE_RDRDY BSP_PRV_DTCE(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IER_TSIP_INTEGRATE_RDRDY BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IPR_TSIP_INTEGRATE_RDRDY BSP_PRV_IPR(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define IEN_TSIP_INTEGRATE_RDRDY BSP_PRV_IEN(BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#define VECT_TSIP_INTEGRATE_RDRDY BSP_PRV_VECT(BSP_PRV_B, BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IR_MTU1_TGIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define DTCE_MTU1_TGIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IER_MTU1_TGIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IPR_MTU1_TGIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IEN_MTU1_TGIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define VECT_MTU1_TGIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IR_MTU0_TGIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define DTCE_MTU0_TGIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IER_MTU0_TGIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IPR_MTU0_TGIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IEN_MTU0_TGIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define VECT_MTU0_TGIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IR_MTU0_TGIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define DTCE_MTU0_TGIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IER_MTU0_TGIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IPR_MTU0_TGIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IEN_MTU0_TGIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define VECT_MTU0_TGIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IR_MTU0_TGIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define DTCE_MTU0_TGIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IER_MTU0_TGIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IPR_MTU0_TGIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IEN_MTU0_TGIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define VECT_MTU0_TGIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IR_MTU0_TGID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define DTCE_MTU0_TGID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IER_MTU0_TGID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IPR_MTU0_TGID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IEN_MTU0_TGID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define VECT_MTU0_TGID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IR_MTU0_TCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define DTCE_MTU0_TCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IER_MTU0_TCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IPR_MTU0_TCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IEN_MTU0_TCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define VECT_MTU0_TCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IR_MTU0_TGIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define DTCE_MTU0_TGIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IER_MTU0_TGIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IPR_MTU0_TGIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IEN_MTU0_TGIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define VECT_MTU0_TGIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IR_MTU0_TGIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define DTCE_MTU0_TGIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IER_MTU0_TGIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IPR_MTU0_TGIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IEN_MTU0_TGIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define VECT_MTU0_TGIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IR_MTU1_TGIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define DTCE_MTU1_TGIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IER_MTU1_TGIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IPR_MTU1_TGIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IEN_MTU1_TGIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define VECT_MTU1_TGIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IR_MTU1_TCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define DTCE_MTU1_TCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IER_MTU1_TCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IPR_MTU1_TCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IEN_MTU1_TCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define VECT_MTU1_TCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IR_MTU1_TCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define DTCE_MTU1_TCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IER_MTU1_TCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IPR_MTU1_TCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IEN_MTU1_TCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define VECT_MTU1_TCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IR_MTU2_TGIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define DTCE_MTU2_TGIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IER_MTU2_TGIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IPR_MTU2_TGIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IEN_MTU2_TGIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define VECT_MTU2_TGIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IR_MTU2_TGIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define DTCE_MTU2_TGIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IER_MTU2_TGIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IPR_MTU2_TGIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IEN_MTU2_TGIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define VECT_MTU2_TGIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IR_MTU2_TCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define DTCE_MTU2_TCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IER_MTU2_TCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IPR_MTU2_TCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IEN_MTU2_TCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define VECT_MTU2_TCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IR_MTU2_TCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define DTCE_MTU2_TCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IER_MTU2_TCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IPR_MTU2_TCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IEN_MTU2_TCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define VECT_MTU2_TCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IR_MTU3_TGIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define DTCE_MTU3_TGIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IER_MTU3_TGIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IPR_MTU3_TGIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IEN_MTU3_TGIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define VECT_MTU3_TGIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IR_MTU3_TGIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define DTCE_MTU3_TGIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IER_MTU3_TGIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IPR_MTU3_TGIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IEN_MTU3_TGIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define VECT_MTU3_TGIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IR_MTU3_TGIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define DTCE_MTU3_TGIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IER_MTU3_TGIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IPR_MTU3_TGIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IEN_MTU3_TGIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define VECT_MTU3_TGIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IR_MTU3_TGID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define DTCE_MTU3_TGID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IER_MTU3_TGID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IPR_MTU3_TGID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IEN_MTU3_TGID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define VECT_MTU3_TGID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IR_MTU3_TCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define DTCE_MTU3_TCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IER_MTU3_TCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IPR_MTU3_TCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IEN_MTU3_TCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define VECT_MTU3_TCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IR_MTU4_TGIA4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define DTCE_MTU4_TGIA4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IER_MTU4_TGIA4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IPR_MTU4_TGIA4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IEN_MTU4_TGIA4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define VECT_MTU4_TGIA4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IR_MTU4_TGIB4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define DTCE_MTU4_TGIB4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IER_MTU4_TGIB4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IPR_MTU4_TGIB4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IEN_MTU4_TGIB4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define VECT_MTU4_TGIB4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IR_MTU4_TGIC4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define DTCE_MTU4_TGIC4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IER_MTU4_TGIC4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IPR_MTU4_TGIC4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IEN_MTU4_TGIC4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define VECT_MTU4_TGIC4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IR_MTU4_TGID4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define DTCE_MTU4_TGID4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IER_MTU4_TGID4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IPR_MTU4_TGID4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IEN_MTU4_TGID4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define VECT_MTU4_TGID4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IR_MTU4_TCIV4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define DTCE_MTU4_TCIV4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IER_MTU4_TCIV4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IPR_MTU4_TCIV4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IEN_MTU4_TCIV4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define VECT_MTU4_TCIV4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IR_MTU5_TGIU5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define DTCE_MTU5_TGIU5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IER_MTU5_TGIU5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IPR_MTU5_TGIU5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IEN_MTU5_TGIU5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define VECT_MTU5_TGIU5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IR_MTU5_TGIV5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define DTCE_MTU5_TGIV5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IER_MTU5_TGIV5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IPR_MTU5_TGIV5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IEN_MTU5_TGIV5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define VECT_MTU5_TGIV5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IR_MTU5_TGIW5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define DTCE_MTU5_TGIW5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IER_MTU5_TGIW5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IPR_MTU5_TGIW5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IEN_MTU5_TGIW5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define VECT_MTU5_TGIW5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IR_MTU6_TGIA6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define DTCE_MTU6_TGIA6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IER_MTU6_TGIA6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IPR_MTU6_TGIA6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IEN_MTU6_TGIA6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define VECT_MTU6_TGIA6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IR_MTU6_TGIB6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define DTCE_MTU6_TGIB6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IER_MTU6_TGIB6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IPR_MTU6_TGIB6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IEN_MTU6_TGIB6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define VECT_MTU6_TGIB6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IR_MTU6_TGIC6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define DTCE_MTU6_TGIC6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IER_MTU6_TGIC6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IPR_MTU6_TGIC6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IEN_MTU6_TGIC6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define VECT_MTU6_TGIC6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IR_MTU6_TGID6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define DTCE_MTU6_TGID6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IER_MTU6_TGID6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IPR_MTU6_TGID6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IEN_MTU6_TGID6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define VECT_MTU6_TGID6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IR_MTU6_TCIV6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define DTCE_MTU6_TCIV6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IER_MTU6_TCIV6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IPR_MTU6_TCIV6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IEN_MTU6_TCIV6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define VECT_MTU6_TCIV6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IR_MTU7_TGIA7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define DTCE_MTU7_TGIA7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IER_MTU7_TGIA7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IPR_MTU7_TGIA7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IEN_MTU7_TGIA7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define VECT_MTU7_TGIA7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IR_MTU7_TGIB7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define DTCE_MTU7_TGIB7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IER_MTU7_TGIB7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IPR_MTU7_TGIB7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IEN_MTU7_TGIB7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define VECT_MTU7_TGIB7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IR_MTU7_TGIC7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define DTCE_MTU7_TGIC7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IER_MTU7_TGIC7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IPR_MTU7_TGIC7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IEN_MTU7_TGIC7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define VECT_MTU7_TGIC7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IR_MTU7_TGID7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define DTCE_MTU7_TGID7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IER_MTU7_TGID7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IPR_MTU7_TGID7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IEN_MTU7_TGID7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define VECT_MTU7_TGID7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IR_MTU7_TCIV7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define DTCE_MTU7_TCIV7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IER_MTU7_TCIV7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IPR_MTU7_TCIV7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IEN_MTU7_TCIV7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define VECT_MTU7_TCIV7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IR_MTU8_TGIA8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define DTCE_MTU8_TGIA8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IER_MTU8_TGIA8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IPR_MTU8_TGIA8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define IEN_MTU8_TGIA8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#define VECT_MTU8_TGIA8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IR_MTU8_TGIB8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define DTCE_MTU8_TGIB8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IER_MTU8_TGIB8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IPR_MTU8_TGIB8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define IEN_MTU8_TGIB8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#define VECT_MTU8_TGIB8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IR_MTU8_TGIC8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define DTCE_MTU8_TGIC8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IER_MTU8_TGIC8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IPR_MTU8_TGIC8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define IEN_MTU8_TGIC8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#define VECT_MTU8_TGIC8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IR_MTU8_TGID8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define DTCE_MTU8_TGID8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IER_MTU8_TGID8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IPR_MTU8_TGID8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define IEN_MTU8_TGID8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#define VECT_MTU8_TGID8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IR_MTU8_TCIV8 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define DTCE_MTU8_TCIV8 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IER_MTU8_TCIV8 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IPR_MTU8_TCIV8 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define IEN_MTU8_TCIV8 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#define VECT_MTU8_TCIV8 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IR_GPTW0_GTCIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define DTCE_GPTW0_GTCIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IER_GPTW0_GTCIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IPR_GPTW0_GTCIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IEN_GPTW0_GTCIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define VECT_GPTW0_GTCIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IR_GPTW0_GTCIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define DTCE_GPTW0_GTCIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IER_GPTW0_GTCIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IPR_GPTW0_GTCIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IEN_GPTW0_GTCIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define VECT_GPTW0_GTCIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IR_GPTW0_GTCIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define DTCE_GPTW0_GTCIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IER_GPTW0_GTCIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IPR_GPTW0_GTCIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IEN_GPTW0_GTCIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define VECT_GPTW0_GTCIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IR_GPTW0_GTCID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define DTCE_GPTW0_GTCID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IER_GPTW0_GTCID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IPR_GPTW0_GTCID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IEN_GPTW0_GTCID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define VECT_GPTW0_GTCID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IR_GPTW0_GDTE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define DTCE_GPTW0_GDTE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IER_GPTW0_GDTE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IPR_GPTW0_GDTE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IEN_GPTW0_GDTE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define VECT_GPTW0_GDTE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IR_GPTW0_GTCIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define DTCE_GPTW0_GTCIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IER_GPTW0_GTCIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IPR_GPTW0_GTCIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IEN_GPTW0_GTCIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define VECT_GPTW0_GTCIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IR_GPTW0_GTCIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define DTCE_GPTW0_GTCIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IER_GPTW0_GTCIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IPR_GPTW0_GTCIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IEN_GPTW0_GTCIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define VECT_GPTW0_GTCIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IR_GPTW0_GTCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define DTCE_GPTW0_GTCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IER_GPTW0_GTCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IPR_GPTW0_GTCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IEN_GPTW0_GTCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define VECT_GPTW0_GTCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IR_GPTW0_GTCIU0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define DTCE_GPTW0_GTCIU0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IER_GPTW0_GTCIU0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IPR_GPTW0_GTCIU0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IEN_GPTW0_GTCIU0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define VECT_GPTW0_GTCIU0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IR_GPTW1_GTCIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define DTCE_GPTW1_GTCIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IER_GPTW1_GTCIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IPR_GPTW1_GTCIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IEN_GPTW1_GTCIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define VECT_GPTW1_GTCIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IR_GPTW1_GTCIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define DTCE_GPTW1_GTCIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IER_GPTW1_GTCIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IPR_GPTW1_GTCIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IEN_GPTW1_GTCIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define VECT_GPTW1_GTCIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IR_GPTW1_GTCIC1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define DTCE_GPTW1_GTCIC1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IER_GPTW1_GTCIC1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IPR_GPTW1_GTCIC1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IEN_GPTW1_GTCIC1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define VECT_GPTW1_GTCIC1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IR_GPTW1_GTCID1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define DTCE_GPTW1_GTCID1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IER_GPTW1_GTCID1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IPR_GPTW1_GTCID1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IEN_GPTW1_GTCID1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define VECT_GPTW1_GTCID1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IR_GPTW1_GDTE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define DTCE_GPTW1_GDTE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IER_GPTW1_GDTE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IPR_GPTW1_GDTE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IEN_GPTW1_GDTE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define VECT_GPTW1_GDTE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IR_GPTW1_GTCIE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define DTCE_GPTW1_GTCIE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IER_GPTW1_GTCIE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IPR_GPTW1_GTCIE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IEN_GPTW1_GTCIE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define VECT_GPTW1_GTCIE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IR_GPTW1_GTCIF1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define DTCE_GPTW1_GTCIF1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IER_GPTW1_GTCIF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IPR_GPTW1_GTCIF1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IEN_GPTW1_GTCIF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define VECT_GPTW1_GTCIF1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IR_GPTW1_GTCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define DTCE_GPTW1_GTCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IER_GPTW1_GTCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IPR_GPTW1_GTCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IEN_GPTW1_GTCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define VECT_GPTW1_GTCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IR_GPTW1_GTCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define DTCE_GPTW1_GTCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IER_GPTW1_GTCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IPR_GPTW1_GTCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IEN_GPTW1_GTCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define VECT_GPTW1_GTCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IR_GPTW2_GTCIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define DTCE_GPTW2_GTCIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IER_GPTW2_GTCIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IPR_GPTW2_GTCIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IEN_GPTW2_GTCIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define VECT_GPTW2_GTCIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IR_GPTW2_GTCIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define DTCE_GPTW2_GTCIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IER_GPTW2_GTCIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IPR_GPTW2_GTCIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IEN_GPTW2_GTCIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define VECT_GPTW2_GTCIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IR_GPTW2_GTCIC2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define DTCE_GPTW2_GTCIC2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IER_GPTW2_GTCIC2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IPR_GPTW2_GTCIC2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IEN_GPTW2_GTCIC2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define VECT_GPTW2_GTCIC2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IR_GPTW2_GTCID2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define DTCE_GPTW2_GTCID2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IER_GPTW2_GTCID2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IPR_GPTW2_GTCID2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IEN_GPTW2_GTCID2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define VECT_GPTW2_GTCID2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IR_GPTW2_GDTE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define DTCE_GPTW2_GDTE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IER_GPTW2_GDTE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IPR_GPTW2_GDTE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IEN_GPTW2_GDTE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define VECT_GPTW2_GDTE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IR_GPTW2_GTCIE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define DTCE_GPTW2_GTCIE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IER_GPTW2_GTCIE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IPR_GPTW2_GTCIE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IEN_GPTW2_GTCIE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define VECT_GPTW2_GTCIE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IR_GPTW2_GTCIF2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define DTCE_GPTW2_GTCIF2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IER_GPTW2_GTCIF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IPR_GPTW2_GTCIF2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IEN_GPTW2_GTCIF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define VECT_GPTW2_GTCIF2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IR_GPTW2_GTCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define DTCE_GPTW2_GTCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IER_GPTW2_GTCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IPR_GPTW2_GTCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IEN_GPTW2_GTCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define VECT_GPTW2_GTCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IR_GPTW2_GTCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define DTCE_GPTW2_GTCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IER_GPTW2_GTCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IPR_GPTW2_GTCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IEN_GPTW2_GTCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define VECT_GPTW2_GTCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IR_GPTW3_GTCIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define DTCE_GPTW3_GTCIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IER_GPTW3_GTCIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IPR_GPTW3_GTCIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IEN_GPTW3_GTCIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define VECT_GPTW3_GTCIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IR_GPTW3_GTCIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define DTCE_GPTW3_GTCIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IER_GPTW3_GTCIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IPR_GPTW3_GTCIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IEN_GPTW3_GTCIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define VECT_GPTW3_GTCIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IR_GPTW3_GTCIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define DTCE_GPTW3_GTCIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IER_GPTW3_GTCIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IPR_GPTW3_GTCIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IEN_GPTW3_GTCIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define VECT_GPTW3_GTCIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IR_GPTW3_GTCID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define DTCE_GPTW3_GTCID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IER_GPTW3_GTCID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IPR_GPTW3_GTCID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IEN_GPTW3_GTCID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define VECT_GPTW3_GTCID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IR_GPTW3_GDTE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define DTCE_GPTW3_GDTE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IER_GPTW3_GDTE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IPR_GPTW3_GDTE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IEN_GPTW3_GDTE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define VECT_GPTW3_GDTE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IR_GPTW3_GTCIE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define DTCE_GPTW3_GTCIE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IER_GPTW3_GTCIE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IPR_GPTW3_GTCIE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IEN_GPTW3_GTCIE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define VECT_GPTW3_GTCIE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IR_GPTW3_GTCIF3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define DTCE_GPTW3_GTCIF3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IER_GPTW3_GTCIF3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IPR_GPTW3_GTCIF3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IEN_GPTW3_GTCIF3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define VECT_GPTW3_GTCIF3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IR_GPTW3_GTCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define DTCE_GPTW3_GTCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IER_GPTW3_GTCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IPR_GPTW3_GTCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IEN_GPTW3_GTCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define VECT_GPTW3_GTCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IR_GPTW3_GTCIU3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define DTCE_GPTW3_GTCIU3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IER_GPTW3_GTCIU3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IPR_GPTW3_GTCIU3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IEN_GPTW3_GTCIU3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define VECT_GPTW3_GTCIU3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IR_EPTPC_IPLS BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define DTCE_EPTPC_IPLS BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IER_EPTPC_IPLS BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IPR_EPTPC_IPLS BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define IEN_EPTPC_IPLS BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#define VECT_EPTPC_IPLS BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IR_PMGI0_PMGI0I BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define DTCE_PMGI0_PMGI0I BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IER_PMGI0_PMGI0I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IPR_PMGI0_PMGI0I BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define IEN_PMGI0_PMGI0I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#define VECT_PMGI0_PMGI0I BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IR_PMGI1_PMGI1I BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define DTCE_PMGI1_PMGI1I BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IER_PMGI1_PMGI1I BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IPR_PMGI1_PMGI1I BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define IEN_PMGI1_PMGI1I BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#define VECT_PMGI1_PMGI1I BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_MAPPED_INTERRUPTS_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h new file mode 100644 index 000000000..edd0636ae --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/mcu_mapped_interrupts_private.h @@ -0,0 +1,360 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts_private.h +* Description : This module contains macros used for mapping interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_PRIVATE_H +#define MCU_MAPPED_INTERRUPTS_PRIVATE_H + +/* These macros are calculated values for x % 8. These macros are used when preprocessor arithmetic cannot be used. + * For example, 'IEN0'-'IEN7' needs to be defined for a macro based on 'vector_number % 8' but preprocessor arithmetic + * is only evaluated at compile-time when it is used in a preprocessor conditional. For this reason the calculated + * value of 'vector_number % 8' must be calculated before compile-time. + */ +#define BSP_PRV_CALC_128_MOD_8 0 +#define BSP_PRV_CALC_129_MOD_8 1 +#define BSP_PRV_CALC_130_MOD_8 2 +#define BSP_PRV_CALC_131_MOD_8 3 +#define BSP_PRV_CALC_132_MOD_8 4 +#define BSP_PRV_CALC_133_MOD_8 5 +#define BSP_PRV_CALC_134_MOD_8 6 +#define BSP_PRV_CALC_135_MOD_8 7 +#define BSP_PRV_CALC_136_MOD_8 0 +#define BSP_PRV_CALC_137_MOD_8 1 +#define BSP_PRV_CALC_138_MOD_8 2 +#define BSP_PRV_CALC_139_MOD_8 3 +#define BSP_PRV_CALC_140_MOD_8 4 +#define BSP_PRV_CALC_141_MOD_8 5 +#define BSP_PRV_CALC_142_MOD_8 6 +#define BSP_PRV_CALC_143_MOD_8 7 +#define BSP_PRV_CALC_144_MOD_8 0 +#define BSP_PRV_CALC_145_MOD_8 1 +#define BSP_PRV_CALC_146_MOD_8 2 +#define BSP_PRV_CALC_147_MOD_8 3 +#define BSP_PRV_CALC_148_MOD_8 4 +#define BSP_PRV_CALC_149_MOD_8 5 +#define BSP_PRV_CALC_150_MOD_8 6 +#define BSP_PRV_CALC_151_MOD_8 7 +#define BSP_PRV_CALC_152_MOD_8 0 +#define BSP_PRV_CALC_153_MOD_8 1 +#define BSP_PRV_CALC_154_MOD_8 2 +#define BSP_PRV_CALC_155_MOD_8 3 +#define BSP_PRV_CALC_156_MOD_8 4 +#define BSP_PRV_CALC_157_MOD_8 5 +#define BSP_PRV_CALC_158_MOD_8 6 +#define BSP_PRV_CALC_159_MOD_8 7 +#define BSP_PRV_CALC_160_MOD_8 0 +#define BSP_PRV_CALC_161_MOD_8 1 +#define BSP_PRV_CALC_162_MOD_8 2 +#define BSP_PRV_CALC_163_MOD_8 3 +#define BSP_PRV_CALC_164_MOD_8 4 +#define BSP_PRV_CALC_165_MOD_8 5 +#define BSP_PRV_CALC_166_MOD_8 6 +#define BSP_PRV_CALC_167_MOD_8 7 +#define BSP_PRV_CALC_168_MOD_8 0 +#define BSP_PRV_CALC_169_MOD_8 1 +#define BSP_PRV_CALC_170_MOD_8 2 +#define BSP_PRV_CALC_171_MOD_8 3 +#define BSP_PRV_CALC_172_MOD_8 4 +#define BSP_PRV_CALC_173_MOD_8 5 +#define BSP_PRV_CALC_174_MOD_8 6 +#define BSP_PRV_CALC_175_MOD_8 7 +#define BSP_PRV_CALC_176_MOD_8 0 +#define BSP_PRV_CALC_177_MOD_8 1 +#define BSP_PRV_CALC_178_MOD_8 2 +#define BSP_PRV_CALC_179_MOD_8 3 +#define BSP_PRV_CALC_180_MOD_8 4 +#define BSP_PRV_CALC_181_MOD_8 5 +#define BSP_PRV_CALC_182_MOD_8 6 +#define BSP_PRV_CALC_183_MOD_8 7 +#define BSP_PRV_CALC_184_MOD_8 0 +#define BSP_PRV_CALC_185_MOD_8 1 +#define BSP_PRV_CALC_186_MOD_8 2 +#define BSP_PRV_CALC_187_MOD_8 3 +#define BSP_PRV_CALC_188_MOD_8 4 +#define BSP_PRV_CALC_189_MOD_8 5 +#define BSP_PRV_CALC_190_MOD_8 6 +#define BSP_PRV_CALC_191_MOD_8 7 +#define BSP_PRV_CALC_192_MOD_8 0 +#define BSP_PRV_CALC_193_MOD_8 1 +#define BSP_PRV_CALC_194_MOD_8 2 +#define BSP_PRV_CALC_195_MOD_8 3 +#define BSP_PRV_CALC_196_MOD_8 4 +#define BSP_PRV_CALC_197_MOD_8 5 +#define BSP_PRV_CALC_198_MOD_8 6 +#define BSP_PRV_CALC_199_MOD_8 7 +#define BSP_PRV_CALC_200_MOD_8 0 +#define BSP_PRV_CALC_201_MOD_8 1 +#define BSP_PRV_CALC_202_MOD_8 2 +#define BSP_PRV_CALC_203_MOD_8 3 +#define BSP_PRV_CALC_204_MOD_8 4 +#define BSP_PRV_CALC_205_MOD_8 5 +#define BSP_PRV_CALC_206_MOD_8 6 +#define BSP_PRV_CALC_207_MOD_8 7 +#define BSP_PRV_CALC_208_MOD_8 0 +#define BSP_PRV_CALC_209_MOD_8 1 +#define BSP_PRV_CALC_210_MOD_8 2 +#define BSP_PRV_CALC_211_MOD_8 3 +#define BSP_PRV_CALC_212_MOD_8 4 +#define BSP_PRV_CALC_213_MOD_8 5 +#define BSP_PRV_CALC_214_MOD_8 6 +#define BSP_PRV_CALC_215_MOD_8 7 +#define BSP_PRV_CALC_216_MOD_8 0 +#define BSP_PRV_CALC_217_MOD_8 1 +#define BSP_PRV_CALC_218_MOD_8 2 +#define BSP_PRV_CALC_219_MOD_8 3 +#define BSP_PRV_CALC_220_MOD_8 4 +#define BSP_PRV_CALC_221_MOD_8 5 +#define BSP_PRV_CALC_222_MOD_8 6 +#define BSP_PRV_CALC_223_MOD_8 7 +#define BSP_PRV_CALC_224_MOD_8 0 +#define BSP_PRV_CALC_225_MOD_8 1 +#define BSP_PRV_CALC_226_MOD_8 2 +#define BSP_PRV_CALC_227_MOD_8 3 +#define BSP_PRV_CALC_228_MOD_8 4 +#define BSP_PRV_CALC_229_MOD_8 5 +#define BSP_PRV_CALC_230_MOD_8 6 +#define BSP_PRV_CALC_231_MOD_8 7 +#define BSP_PRV_CALC_232_MOD_8 0 +#define BSP_PRV_CALC_233_MOD_8 1 +#define BSP_PRV_CALC_234_MOD_8 2 +#define BSP_PRV_CALC_235_MOD_8 3 +#define BSP_PRV_CALC_236_MOD_8 4 +#define BSP_PRV_CALC_237_MOD_8 5 +#define BSP_PRV_CALC_238_MOD_8 6 +#define BSP_PRV_CALC_239_MOD_8 7 +#define BSP_PRV_CALC_240_MOD_8 0 +#define BSP_PRV_CALC_241_MOD_8 1 +#define BSP_PRV_CALC_242_MOD_8 2 +#define BSP_PRV_CALC_243_MOD_8 3 +#define BSP_PRV_CALC_244_MOD_8 4 +#define BSP_PRV_CALC_245_MOD_8 5 +#define BSP_PRV_CALC_246_MOD_8 6 +#define BSP_PRV_CALC_247_MOD_8 7 +#define BSP_PRV_CALC_248_MOD_8 0 +#define BSP_PRV_CALC_249_MOD_8 1 +#define BSP_PRV_CALC_250_MOD_8 2 +#define BSP_PRV_CALC_251_MOD_8 3 +#define BSP_PRV_CALC_252_MOD_8 4 +#define BSP_PRV_CALC_253_MOD_8 5 +#define BSP_PRV_CALC_254_MOD_8 6 +#define BSP_PRV_CALC_255_MOD_8 7 + +/* These macros are used to determine if the SLIBXRn or SLIBRn select register should be written to. */ +#define BSP_PRV_INT_B_SELECT_128 ICU.SLIBXR128.BYTE +#define BSP_PRV_INT_B_SELECT_129 ICU.SLIBXR129.BYTE +#define BSP_PRV_INT_B_SELECT_130 ICU.SLIBXR130.BYTE +#define BSP_PRV_INT_B_SELECT_131 ICU.SLIBXR131.BYTE +#define BSP_PRV_INT_B_SELECT_132 ICU.SLIBXR132.BYTE +#define BSP_PRV_INT_B_SELECT_133 ICU.SLIBXR133.BYTE +#define BSP_PRV_INT_B_SELECT_134 ICU.SLIBXR134.BYTE +#define BSP_PRV_INT_B_SELECT_135 ICU.SLIBXR135.BYTE +#define BSP_PRV_INT_B_SELECT_136 ICU.SLIBXR136.BYTE +#define BSP_PRV_INT_B_SELECT_137 ICU.SLIBXR137.BYTE +#define BSP_PRV_INT_B_SELECT_138 ICU.SLIBXR138.BYTE +#define BSP_PRV_INT_B_SELECT_139 ICU.SLIBXR139.BYTE +#define BSP_PRV_INT_B_SELECT_140 ICU.SLIBXR140.BYTE +#define BSP_PRV_INT_B_SELECT_141 ICU.SLIBXR141.BYTE +#define BSP_PRV_INT_B_SELECT_142 ICU.SLIBXR142.BYTE +#define BSP_PRV_INT_B_SELECT_143 ICU.SLIBXR143.BYTE +#define BSP_PRV_INT_B_SELECT_144 ICU.SLIBR144.BYTE +#define BSP_PRV_INT_B_SELECT_145 ICU.SLIBR145.BYTE +#define BSP_PRV_INT_B_SELECT_146 ICU.SLIBR146.BYTE +#define BSP_PRV_INT_B_SELECT_147 ICU.SLIBR147.BYTE +#define BSP_PRV_INT_B_SELECT_148 ICU.SLIBR148.BYTE +#define BSP_PRV_INT_B_SELECT_149 ICU.SLIBR149.BYTE +#define BSP_PRV_INT_B_SELECT_150 ICU.SLIBR150.BYTE +#define BSP_PRV_INT_B_SELECT_151 ICU.SLIBR151.BYTE +#define BSP_PRV_INT_B_SELECT_152 ICU.SLIBR152.BYTE +#define BSP_PRV_INT_B_SELECT_153 ICU.SLIBR153.BYTE +#define BSP_PRV_INT_B_SELECT_154 ICU.SLIBR154.BYTE +#define BSP_PRV_INT_B_SELECT_155 ICU.SLIBR155.BYTE +#define BSP_PRV_INT_B_SELECT_156 ICU.SLIBR156.BYTE +#define BSP_PRV_INT_B_SELECT_157 ICU.SLIBR157.BYTE +#define BSP_PRV_INT_B_SELECT_158 ICU.SLIBR158.BYTE +#define BSP_PRV_INT_B_SELECT_159 ICU.SLIBR159.BYTE +#define BSP_PRV_INT_B_SELECT_160 ICU.SLIBR160.BYTE +#define BSP_PRV_INT_B_SELECT_161 ICU.SLIBR161.BYTE +#define BSP_PRV_INT_B_SELECT_162 ICU.SLIBR162.BYTE +#define BSP_PRV_INT_B_SELECT_163 ICU.SLIBR163.BYTE +#define BSP_PRV_INT_B_SELECT_164 ICU.SLIBR164.BYTE +#define BSP_PRV_INT_B_SELECT_165 ICU.SLIBR165.BYTE +#define BSP_PRV_INT_B_SELECT_166 ICU.SLIBR166.BYTE +#define BSP_PRV_INT_B_SELECT_167 ICU.SLIBR167.BYTE +#define BSP_PRV_INT_B_SELECT_168 ICU.SLIBR168.BYTE +#define BSP_PRV_INT_B_SELECT_169 ICU.SLIBR169.BYTE +#define BSP_PRV_INT_B_SELECT_170 ICU.SLIBR170.BYTE +#define BSP_PRV_INT_B_SELECT_171 ICU.SLIBR171.BYTE +#define BSP_PRV_INT_B_SELECT_172 ICU.SLIBR172.BYTE +#define BSP_PRV_INT_B_SELECT_173 ICU.SLIBR173.BYTE +#define BSP_PRV_INT_B_SELECT_174 ICU.SLIBR174.BYTE +#define BSP_PRV_INT_B_SELECT_175 ICU.SLIBR175.BYTE +#define BSP_PRV_INT_B_SELECT_176 ICU.SLIBR176.BYTE +#define BSP_PRV_INT_B_SELECT_177 ICU.SLIBR177.BYTE +#define BSP_PRV_INT_B_SELECT_178 ICU.SLIBR178.BYTE +#define BSP_PRV_INT_B_SELECT_179 ICU.SLIBR179.BYTE +#define BSP_PRV_INT_B_SELECT_180 ICU.SLIBR180.BYTE +#define BSP_PRV_INT_B_SELECT_181 ICU.SLIBR181.BYTE +#define BSP_PRV_INT_B_SELECT_182 ICU.SLIBR182.BYTE +#define BSP_PRV_INT_B_SELECT_183 ICU.SLIBR183.BYTE +#define BSP_PRV_INT_B_SELECT_184 ICU.SLIBR184.BYTE +#define BSP_PRV_INT_B_SELECT_185 ICU.SLIBR185.BYTE +#define BSP_PRV_INT_B_SELECT_186 ICU.SLIBR186.BYTE +#define BSP_PRV_INT_B_SELECT_187 ICU.SLIBR187.BYTE +#define BSP_PRV_INT_B_SELECT_188 ICU.SLIBR188.BYTE +#define BSP_PRV_INT_B_SELECT_189 ICU.SLIBR189.BYTE +#define BSP_PRV_INT_B_SELECT_190 ICU.SLIBR190.BYTE +#define BSP_PRV_INT_B_SELECT_191 ICU.SLIBR191.BYTE +#define BSP_PRV_INT_B_SELECT_192 ICU.SLIBR192.BYTE +#define BSP_PRV_INT_B_SELECT_193 ICU.SLIBR193.BYTE +#define BSP_PRV_INT_B_SELECT_194 ICU.SLIBR194.BYTE +#define BSP_PRV_INT_B_SELECT_195 ICU.SLIBR195.BYTE +#define BSP_PRV_INT_B_SELECT_196 ICU.SLIBR196.BYTE +#define BSP_PRV_INT_B_SELECT_197 ICU.SLIBR197.BYTE +#define BSP_PRV_INT_B_SELECT_198 ICU.SLIBR198.BYTE +#define BSP_PRV_INT_B_SELECT_199 ICU.SLIBR199.BYTE +#define BSP_PRV_INT_B_SELECT_200 ICU.SLIBR200.BYTE +#define BSP_PRV_INT_B_SELECT_201 ICU.SLIBR201.BYTE +#define BSP_PRV_INT_B_SELECT_202 ICU.SLIBR202.BYTE +#define BSP_PRV_INT_B_SELECT_203 ICU.SLIBR203.BYTE +#define BSP_PRV_INT_B_SELECT_204 ICU.SLIBR204.BYTE +#define BSP_PRV_INT_B_SELECT_205 ICU.SLIBR205.BYTE +#define BSP_PRV_INT_B_SELECT_206 ICU.SLIBR206.BYTE +#define BSP_PRV_INT_B_SELECT_207 ICU.SLIBR207.BYTE +/* Interrupt A interrupts are also defined even though there is only 1 select register. */ +#define BSP_PRV_INT_A_SELECT_208 ICU.SLIAR208.BYTE +#define BSP_PRV_INT_A_SELECT_209 ICU.SLIAR209.BYTE +#define BSP_PRV_INT_A_SELECT_210 ICU.SLIAR210.BYTE +#define BSP_PRV_INT_A_SELECT_211 ICU.SLIAR211.BYTE +#define BSP_PRV_INT_A_SELECT_212 ICU.SLIAR212.BYTE +#define BSP_PRV_INT_A_SELECT_213 ICU.SLIAR213.BYTE +#define BSP_PRV_INT_A_SELECT_214 ICU.SLIAR214.BYTE +#define BSP_PRV_INT_A_SELECT_215 ICU.SLIAR215.BYTE +#define BSP_PRV_INT_A_SELECT_216 ICU.SLIAR216.BYTE +#define BSP_PRV_INT_A_SELECT_217 ICU.SLIAR217.BYTE +#define BSP_PRV_INT_A_SELECT_218 ICU.SLIAR218.BYTE +#define BSP_PRV_INT_A_SELECT_219 ICU.SLIAR219.BYTE +#define BSP_PRV_INT_A_SELECT_220 ICU.SLIAR220.BYTE +#define BSP_PRV_INT_A_SELECT_221 ICU.SLIAR221.BYTE +#define BSP_PRV_INT_A_SELECT_222 ICU.SLIAR222.BYTE +#define BSP_PRV_INT_A_SELECT_223 ICU.SLIAR223.BYTE +#define BSP_PRV_INT_A_SELECT_224 ICU.SLIAR224.BYTE +#define BSP_PRV_INT_A_SELECT_225 ICU.SLIAR225.BYTE +#define BSP_PRV_INT_A_SELECT_226 ICU.SLIAR226.BYTE +#define BSP_PRV_INT_A_SELECT_227 ICU.SLIAR227.BYTE +#define BSP_PRV_INT_A_SELECT_228 ICU.SLIAR228.BYTE +#define BSP_PRV_INT_A_SELECT_229 ICU.SLIAR229.BYTE +#define BSP_PRV_INT_A_SELECT_230 ICU.SLIAR230.BYTE +#define BSP_PRV_INT_A_SELECT_231 ICU.SLIAR231.BYTE +#define BSP_PRV_INT_A_SELECT_232 ICU.SLIAR232.BYTE +#define BSP_PRV_INT_A_SELECT_233 ICU.SLIAR233.BYTE +#define BSP_PRV_INT_A_SELECT_234 ICU.SLIAR234.BYTE +#define BSP_PRV_INT_A_SELECT_235 ICU.SLIAR235.BYTE +#define BSP_PRV_INT_A_SELECT_236 ICU.SLIAR236.BYTE +#define BSP_PRV_INT_A_SELECT_237 ICU.SLIAR237.BYTE +#define BSP_PRV_INT_A_SELECT_238 ICU.SLIAR238.BYTE +#define BSP_PRV_INT_A_SELECT_239 ICU.SLIAR239.BYTE +#define BSP_PRV_INT_A_SELECT_240 ICU.SLIAR240.BYTE +#define BSP_PRV_INT_A_SELECT_241 ICU.SLIAR241.BYTE +#define BSP_PRV_INT_A_SELECT_242 ICU.SLIAR242.BYTE +#define BSP_PRV_INT_A_SELECT_243 ICU.SLIAR243.BYTE +#define BSP_PRV_INT_A_SELECT_244 ICU.SLIAR244.BYTE +#define BSP_PRV_INT_A_SELECT_245 ICU.SLIAR245.BYTE +#define BSP_PRV_INT_A_SELECT_246 ICU.SLIAR246.BYTE +#define BSP_PRV_INT_A_SELECT_247 ICU.SLIAR247.BYTE +#define BSP_PRV_INT_A_SELECT_248 ICU.SLIAR248.BYTE +#define BSP_PRV_INT_A_SELECT_249 ICU.SLIAR249.BYTE +#define BSP_PRV_INT_A_SELECT_250 ICU.SLIAR250.BYTE +#define BSP_PRV_INT_A_SELECT_251 ICU.SLIAR251.BYTE +#define BSP_PRV_INT_A_SELECT_252 ICU.SLIAR252.BYTE +#define BSP_PRV_INT_A_SELECT_253 ICU.SLIAR253.BYTE +#define BSP_PRV_INT_A_SELECT_254 ICU.SLIAR254.BYTE +#define BSP_PRV_INT_A_SELECT_255 ICU.SLIAR255.BYTE + +/* Start and end of Interrupt B and A vectors. */ +#define BSP_PRV_B_INT_VECTOR_START (128) +#define BSP_PRV_B_INT_VECTOR_END (207) +#define BSP_PRV_A_INT_VECTOR_START (208) +#define BSP_PRV_A_INT_VECTOR_END (255) + +/* Start and end of Interrupt B select registers. */ +#define BSP_PRV_SLIBXR_START (128) +#define BSP_PRV_SLIBXR_END (143) +#define BSP_PRV_SLIBR_START (144) +#define BSP_PRV_SLIBR_END (207) + +/* Starting IER register for mapped interrupts. This is used for calculating the IER register based on the + * given vector number. + */ +#define BSP_PRV_MAP_INT_IER_START (0x10) + +/* These are used in function-like macros to expand to letters. */ +#define BSP_PRV_A A +#define BSP_PRV_B B + +/* Test to see if chosen vector is valid for a mapped interrupt. */ +#define BSP_PRV_VALID_MAP_INT(x, y) (((y + 0) >= BSP_PRV_ ## x ## _INT_VECTOR_START) && \ + ((y + 0) <= BSP_PRV_ ## x ## _INT_VECTOR_END)) + +/* Calculation for getting IER register. */ +#define BSP_PRIV_CALC_IER_REG(x) (((x - BSP_PRV_B_INT_VECTOR_START)/8) + BSP_PRV_MAP_INT_IER_START) + +/* These macros generate the macros needed to use the function-like macros from iodefine.h */ +#define BSP_PRV_IR(x, y) _BSP_PRV_IR(x, y) +#define _BSP_PRV_IR(x, y) IR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_DTCE(x, y) _BSP_PRV_DTCE(x, y) +#define _BSP_PRV_DTCE(x, y) DTCE_PERI ## x ## _INT ## x ## y +#define BSP_PRV_IPR(x, y) _BSP_PRV_IPR(x, y) +#define _BSP_PRV_IPR(x, y) IPR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_VECT(x, y) _BSP_PRV_VECT(x, y) +#define _BSP_PRV_VECT(x, y) VECT_PERI ## x ## _INT ## x ## y + +#define BSP_PRV_IEN(x) _BSP_PRV_IEN(x) +#define _BSP_PRV_IEN(x) __BSP_PRV_IEN(BSP_PRV_CALC_ ## x ## _MOD_8) +#define __BSP_PRV_IEN(x) ___BSP_PRV_IEN(x) +#define ___BSP_PRV_IEN(x) IEN ## x + +/* Chooses the correct interrupt select register. */ +#define BSP_PRV_INT_SELECT(x, y) _BSP_PRV_INT_SELECT(x, y) +#define _BSP_PRV_INT_SELECT(x, y) BSP_PRV_INT_ ## x ## _SELECT_ ## y + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* MCU_MAPPED_INTERRUPTS_PRIVATE_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h new file mode 100644 index 000000000..3e389b0f0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_cpu.h @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.h +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef CPU_H +#define CPU_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The different types of registers that can be protected. */ +typedef enum +{ + /* PRC0 + Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR2, SCKCR3, PACKCR, PLLCR, + PLLCR2, PPLLCR, PPLLCR2, BCKCR, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOCOCR2, OSTDCR, OSTDSR, CKOCR. */ + BSP_REG_PROTECT_CGC = 0, + + /* PRC1 + Enables writing to the registers related to operating modes, low power consumption, the clock generation circuit, + and software reset: SYSCR0, SYSCR1, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD, OPCCR, RSTCKCR, + DPSBYCR, DPSIER0, DPSIER1, DPSIER2, DPSIER3, DPSIFR0, DPSIFR1, DPSIFR2, DPSIFR3, + DPSIEGR0, DPSIEGR1, DPSIEGR2, DPSIEGR3, MOSCWTCR, SOSCWTCR, MOFCR, HOCOPCR, SWRR. */ + BSP_REG_PROTECT_LPC_CGC_SWR, + + /* PRC3 + Enables writing to the registers related to the LVD:LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /* MPC.PWPR + Enables writing to MPC's PFS registers. */ + BSP_REG_PROTECT_MPC, + + /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/ + BSP_REG_PROTECT_TOTAL_ITEMS +} bsp_reg_protect_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptsDisable(void); +void R_BSP_InterruptsEnable(void); +uint32_t R_BSP_CpuInterruptLevelRead(void); +bool R_BSP_CpuInterruptLevelWrite(uint32_t level); +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareReset(void); + +void bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL. +void bsp_ram_initialize(void); + +#endif /* CPU_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h new file mode 100644 index 000000000..184e6624a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/r_bsp_locking.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.h +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Lock types. */ +#include "mcu_locks.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOCKING_H +#define LOCKING_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bool R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_HardwareLock(mcu_lock_t const hw_index); +bool R_BSP_HardwareUnlock(mcu_lock_t const hw_index); + +#if BSP_CFG_USER_LOCKING_ENABLED != 0 +/* Is user is using their own lock functions then these are the prototypes. */ +bool BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t const hw_index); +bool BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t const hw_index); +#endif + +#endif /* LOCKING_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/register_access/ccrx/iodefine.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/register_access/ccrx/iodefine.h new file mode 100644 index 000000000..555817b71 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/register_access/ccrx/iodefine.h @@ -0,0 +1,20890 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/******************************************************************************* +* +* Device : RX/RX700/RX72N +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : V0.50 (2019-03-15) [Hardware Manual Revision : 0.50] +* V1.00C (2019-07-17) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright(c) 2019 Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX72N */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(BSC,BUSERR) = 0; expands to : */ +/* ICU.IR[16].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(ICU,SWINT2) = 2; expands to : */ +/* IPR(ICU,SWI ) = 2; // SWINT2,SWINT share IPR level. */ +/* ICU.IPR[3].BIT.IPR = 2; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,... expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU0,TPU1,TPU2,TPU3,TPU4,TPU5,TPUA expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX72NIODEFINE_HEADER__ +#define __RX72NIODEFINE_HEADER__ + +#define IEN_BSC_BUSERR IEN0 +#define IEN_ICU_GROUPIE0 IEN1 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_SSIE0_SSITXI0 IEN6 +#define IEN_SSIE0_SSIRXI0 IEN7 +#define IEN_SSIE1_SSIRTI1 IEN0 +#define IEN_RIIC1_RXI1 IEN2 +#define IEN_RIIC1_TXI1 IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCI8_RXI8 IEN4 +#define IEN_SCI8_TXI8 IEN5 +#define IEN_SCI9_RXI9 IEN6 +#define IEN_SCI9_TXI9 IEN7 +#define IEN_SCI10_RXI10 IEN0 +#define IEN_SCI10_TXI10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL2 IEN3 +#define IEN_RSPI2_SPRI2 IEN4 +#define IEN_RSPI2_SPTI2 IEN5 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCI11_RXI11 IEN2 +#define IEN_SCI11_TXI11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OSTDI IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_ICU_GROUPIE0 17 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_SSIE0_SSITXI0 46 +#define VECT_SSIE0_SSIRXI0 47 +#define VECT_SSIE1_SSIRTI1 48 +#define VECT_RIIC1_RXI1 50 +#define VECT_RIIC1_TXI1 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCI8_RXI8 100 +#define VECT_SCI8_TXI8 101 +#define VECT_SCI9_RXI9 102 +#define VECT_SCI9_TXI9 103 +#define VECT_SCI10_RXI10 104 +#define VECT_SCI10_TXI10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL2 107 +#define VECT_RSPI2_SPRI2 108 +#define VECT_RSPI2_SPTI2 109 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCI11_RXI11 114 +#define VECT_SCI11_TXI11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OSTDI 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPUA SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_GPTW SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW0 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW1 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW2 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW3 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_POEG SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_ETHERC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_PMGI0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ETHERC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_EDMAC1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_PMGI1 SYSTEM.MSTPCRB.BIT.MSTPB14 +#define MSTP_EPTPC SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_EPTPC0 SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_EPTPC1 SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_PTPEDMAC SYSTEM.MSTPCRB.BIT.MSTPB13 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN2 SYSTEM.MSTPCRB.BIT.MSTPB2 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_GLCDC SYSTEM.MSTPCRC.BIT.MSTPC29 +#define MSTP_DRW2D SYSTEM.MSTPCRC.BIT.MSTPC28 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_ECCRAM SYSTEM.MSTPCRC.BIT.MSTPC6 +#define MSTP_RAM2 SYSTEM.MSTPCRC.BIT.MSTPC2 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_TSIP SYSTEM.MSTPCRD.BIT.MSTPD27 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSIE0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_SSIE1 SYSTEM.MSTPCRD.BIT.MSTPD14 + +#define IS_DPFPU_DPFPUEX IS0 +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_CAN2_ERS2 IS2 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRI IS26 +#define IS_CAC_MENDI IS27 +#define IS_CAC_OVFI IS28 +#define IS_DOC_DOPCI IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_SSIE0_SSIF0 IS17 +#define IS_SSIE1_SSIF1 IS18 +#define IS_S12AD_S12CMPAI IS20 +#define IS_S12AD_S12CMPBI IS21 +#define IS_S12AD1_S12CMPAI1 IS22 +#define IS_S12AD1_S12CMPBI1 IS23 +#define IS_RIIC1_TEI1 IS28 +#define IS_RIIC1_EEI1 IS29 +#define IS_POEG_POEGGAI IS7 +#define IS_POEG_POEGGBI IS8 +#define IS_POEG_POEGGCI IS9 +#define IS_POEG_POEGGDI IS10 +#define IS_SCI8_TEI8 IS0 +#define IS_SCI8_ERI8 IS1 +#define IS_SCI9_TEI9 IS4 +#define IS_SCI9_ERI9 IS5 +#define IS_SCI10_TEI10 IS8 +#define IS_SCI10_ERI10 IS9 +#define IS_SCI11_TEI11 IS12 +#define IS_SCI11_ERI11 IS13 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_RSPI2_SPII2 IS20 +#define IS_RSPI2_SPEI2 IS21 +#define IS_SCI7_TEI7 IS22 +#define IS_SCI7_ERI7 IS23 +#define IS_EPTPC_MINT IS0 +#define IS_PTPEDMAC_PINT IS1 +#define IS_EDMAC0_EINT0 IS4 +#define IS_EDMAC1_EINT1 IS5 +#define IS_GLCDC_VPOS IS8 +#define IS_GLCDC_GR1UF IS9 +#define IS_GLCDC_GR2UF IS10 +#define IS_DRW2D_DRWIRQ IS11 + +#define EN_DPFPU_DPFPUEX EN0 +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_CAN2_ERS2 EN2 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRI EN26 +#define EN_CAC_MENDI EN27 +#define EN_CAC_OVFI EN28 +#define EN_DOC_DOPCI EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_SSIE0_SSIF0 EN17 +#define EN_SSIE1_SSIF1 EN18 +#define EN_S12AD_S12CMPAI EN20 +#define EN_S12AD_S12CMPBI EN21 +#define EN_S12AD1_S12CMPAI1 EN22 +#define EN_S12AD1_S12CMPBI1 EN23 +#define EN_RIIC1_TEI1 EN28 +#define EN_RIIC1_EEI1 EN29 +#define EN_POEG_POEGGAI EN7 +#define EN_POEG_POEGGBI EN8 +#define EN_POEG_POEGGCI EN9 +#define EN_POEG_POEGGDI EN10 +#define EN_SCI8_TEI8 EN0 +#define EN_SCI8_ERI8 EN1 +#define EN_SCI9_TEI9 EN4 +#define EN_SCI9_ERI9 EN5 +#define EN_SCI10_TEI10 EN8 +#define EN_SCI10_ERI10 EN9 +#define EN_SCI11_TEI11 EN12 +#define EN_SCI11_ERI11 EN13 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_RSPI2_SPII2 EN20 +#define EN_RSPI2_SPEI2 EN21 +#define EN_SCI7_TEI7 EN22 +#define EN_SCI7_ERI7 EN23 +#define EN_EPTPC_MINT EN0 +#define EN_PTPEDMAC_PINT EN1 +#define EN_EDMAC0_EINT0 EN4 +#define EN_EDMAC1_EINT1 EN5 +#define EN_GLCDC_VPOS EN8 +#define EN_GLCDC_GR1UF EN9 +#define EN_GLCDC_GR2UF EN10 +#define EN_DRW2D_DRWIRQ EN11 + +#define CLR_DPFPU_DPFPUEX CLR0 +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 +#define CLR_CAN2_ERS2 CLR2 + +#define GEN_DPFPU_DPFPUEX GENIE0 +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_CAN2_ERS2 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRI GENBL0 +#define GEN_CAC_MENDI GENBL0 +#define GEN_CAC_OVFI GENBL0 +#define GEN_DOC_DOPCI GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_SSIE0_SSIF0 GENBL1 +#define GEN_SSIE1_SSIF1 GENBL1 +#define GEN_S12AD_S12CMPAI GENBL1 +#define GEN_S12AD_S12CMPBI GENBL1 +#define GEN_S12AD1_S12CMPAI1 GENBL1 +#define GEN_S12AD1_S12CMPBI1 GENBL1 +#define GEN_RIIC1_TEI1 GENBL1 +#define GEN_RIIC1_EEI1 GENBL1 +#define GEN_POEG_POEGGAI GENBL2 +#define GEN_POEG_POEGGBI GENBL2 +#define GEN_POEG_POEGGCI GENBL2 +#define GEN_POEG_POEGGDI GENBL2 +#define GEN_SCI8_TEI8 GENAL0 +#define GEN_SCI8_ERI8 GENAL0 +#define GEN_SCI9_TEI9 GENAL0 +#define GEN_SCI9_ERI9 GENAL0 +#define GEN_SCI10_TEI10 GENAL0 +#define GEN_SCI10_ERI10 GENAL0 +#define GEN_SCI11_TEI11 GENAL0 +#define GEN_SCI11_ERI11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_RSPI2_SPII2 GENAL0 +#define GEN_RSPI2_SPEI2 GENAL0 +#define GEN_SCI7_TEI7 GENAL0 +#define GEN_SCI7_ERI7 GENAL0 +#define GEN_EPTPC_MINT GENAL1 +#define GEN_PTPEDMAC_PINT GENAL1 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_EDMAC1_EINT1 GENAL1 +#define GEN_GLCDC_VPOS GENAL1 +#define GEN_GLCDC_GR1UF GENAL1 +#define GEN_GLCDC_GR2UF GENAL1 +#define GEN_DRW2D_DRWIRQ GENAL1 + +#define GRP_DPFPU_DPFPUEX GRPIE0 +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_CAN2_ERS2 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRI GRPBL0 +#define GRP_CAC_MENDI GRPBL0 +#define GRP_CAC_OVFI GRPBL0 +#define GRP_DOC_DOPCI GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_SSIE0_SSIF0 GRPBL1 +#define GRP_SSIE1_SSIF1 GRPBL1 +#define GRP_S12AD_S12CMPAI GRPBL1 +#define GRP_S12AD_S12CMPBI GRPBL1 +#define GRP_S12AD1_S12CMPAI1 GRPBL1 +#define GRP_S12AD1_S12CMPBI1 GRPBL1 +#define GRP_RIIC1_TEI1 GRPBL1 +#define GRP_RIIC1_EEI1 GRPBL1 +#define GRP_POEG_POEGGAI GRPBL2 +#define GRP_POEG_POEGGBI GRPBL2 +#define GRP_POEG_POEGGCI GRPBL2 +#define GRP_POEG_POEGGDI GRPBL2 +#define GRP_SCI8_TEI8 GRPAL0 +#define GRP_SCI8_ERI8 GRPAL0 +#define GRP_SCI9_TEI9 GRPAL0 +#define GRP_SCI9_ERI9 GRPAL0 +#define GRP_SCI10_TEI10 GRPAL0 +#define GRP_SCI10_ERI10 GRPAL0 +#define GRP_SCI11_TEI11 GRPAL0 +#define GRP_SCI11_ERI11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_RSPI2_SPII2 GRPAL0 +#define GRP_RSPI2_SPEI2 GRPAL0 +#define GRP_SCI7_TEI7 GRPAL0 +#define GRP_SCI7_ERI7 GRPAL0 +#define GRP_EPTPC_MINT GRPAL1 +#define GRP_PTPEDMAC_PINT GRPAL1 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_EDMAC1_EINT1 GRPAL1 +#define GRP_GLCDC_VPOS GRPAL1 +#define GRP_GLCDC_GR1UF GRPAL1 +#define GRP_GLCDC_GR2UF GRPAL1 +#define GRP_DRW2D_DRWIRQ GRPAL1 + +#define GCR_DPFPU_DPFPUEX GCRIE0 +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 +#define GCR_CAN2_ERS2 GCRBE0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000) +#define CAN0 (*(volatile struct st_can __evenaccess *)0x90200) +#define CAN1 (*(volatile struct st_can __evenaccess *)0x91200) +#define CAN2 (*(volatile struct st_can __evenaccess *)0x92200) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw __evenaccess *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw __evenaccess *)0x94280) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define DA (*(volatile struct st_da __evenaccess *)0x88040) +#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0) +#define DMAC4 (*(volatile struct st_dmac1 __evenaccess *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 __evenaccess *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 __evenaccess *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 __evenaccess *)0x821C0) +#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080) +#define DRW2D (*(volatile struct st_drw2d __evenaccess *)0xE3000) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define ECCRAM (*(volatile struct st_eccram __evenaccess *)0x812C0) +#define EDMAC0 (*(volatile struct st_edmac __evenaccess *)0xC0000) +#define EDMAC1 (*(volatile struct st_edmac __evenaccess *)0xC0200) +#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100) +#define EPTPC (*(volatile struct st_eptpc __evenaccess *)0xC0500) +#define EPTPC0 (*(volatile struct st_eptpc0 __evenaccess *)0xC4800) +#define EPTPC1 (*(volatile struct st_eptpc0 __evenaccess *)0xC4C00) +#define ETHERC0 (*(volatile struct st_etherc __evenaccess *)0xC0100) +#define ETHERC1 (*(volatile struct st_etherc __evenaccess *)0xC0300) +#define EXDMAC (*(volatile struct st_exdmac __evenaccess *)0x82A00) +#define EXDMAC0 (*(volatile struct st_exdmac0 __evenaccess *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 __evenaccess *)0x82840) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x81000) +#define GLCDC (*(volatile struct st_glcdc __evenaccess *)0xE0000) +#define GPTW0 (*(volatile struct st_gptw __evenaccess *)0xC2000) +#define GPTW1 (*(volatile struct st_gptw __evenaccess *)0xC2100) +#define GPTW2 (*(volatile struct st_gptw __evenaccess *)0xC2200) +#define GPTW3 (*(volatile struct st_gptw __evenaccess *)0xC2300) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define MMCIF (*(volatile struct st_mmcif __evenaccess *)0x88500) +#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C100) +#define MPU (*(volatile struct st_mpu __evenaccess *)0x86400) +#define MTU (*(volatile struct st_mtu __evenaccess *)0xC120A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0xC1290) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0xC1290) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0xC1292) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0xC1200) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0xC1200) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0xC1A94) +#define MTU6 (*(volatile struct st_mtu6 __evenaccess *)0xC1A00) +#define MTU7 (*(volatile struct st_mtu7 __evenaccess *)0xC1A00) +#define MTU8 (*(volatile struct st_mtu8 __evenaccess *)0xC1298) +#define OFSM (*(volatile struct st_ofsm __evenaccess *)0xFE7F5D00) +#define PDC (*(volatile struct st_pdc __evenaccess *)0xA0500) +#define PMGI0 (*(volatile struct st_pmgi __evenaccess *)0xC5880) +#define PMGI1 (*(volatile struct st_pmgi __evenaccess *)0xC5890) +#define POE3 (*(volatile struct st_poe __evenaccess *)0x8C4C0) +#define POEG (*(volatile struct st_poeg __evenaccess *)0x9E000) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORT6 (*(volatile struct st_port6 __evenaccess *)0x8C006) +#define PORT7 (*(volatile struct st_port7 __evenaccess *)0x8C007) +#define PORT8 (*(volatile struct st_port8 __evenaccess *)0x8C008) +#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F) +#define PORTG (*(volatile struct st_portg __evenaccess *)0x8C010) +#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C011) +#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012) +#define PORTK (*(volatile struct st_portk __evenaccess *)0x8C013) +#define PORTL (*(volatile struct st_portl __evenaccess *)0x8C014) +#define PORTM (*(volatile struct st_portm __evenaccess *)0x8C015) +#define PORTN (*(volatile struct st_portn __evenaccess *)0x8C016) +#define PORTQ (*(volatile struct st_portq __evenaccess *)0x8C017) +#define PPG0 (*(volatile struct st_ppg0 __evenaccess *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 __evenaccess *)0x881F0) +#define PTPEDMAC (*(volatile struct st_ptpedmac __evenaccess *)0xC0400) +#define QSPI (*(volatile struct st_qspi __evenaccess *)0x89E00) +#define RAM (*(volatile struct st_ram __evenaccess *)0x81200) +#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300) +#define RIIC1 (*(volatile struct st_riic __evenaccess *)0x88320) +#define RIIC2 (*(volatile struct st_riic __evenaccess *)0x88340) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0xD0100) +#define RSPI1 (*(volatile struct st_rspi __evenaccess *)0xD0140) +#define RSPI2 (*(volatile struct st_rspi __evenaccess *)0xD0300) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 __evenaccess *)0x89100) +#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020) +#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040) +#define SCI3 (*(volatile struct st_sci0 __evenaccess *)0x8A060) +#define SCI4 (*(volatile struct st_sci0 __evenaccess *)0x8A080) +#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0) +#define SCI7 (*(volatile struct st_sci7 __evenaccess *)0xD00E0) +#define SCI8 (*(volatile struct st_sci7 __evenaccess *)0xD0000) +#define SCI9 (*(volatile struct st_sci7 __evenaccess *)0xD0020) +#define SCI10 (*(volatile struct st_sci7 __evenaccess *)0xD0040) +#define SCI11 (*(volatile struct st_sci7 __evenaccess *)0xD0060) +#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300) +#define SDHI (*(volatile struct st_sdhi __evenaccess *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x8A040) +#define SMCI3 (*(volatile struct st_smci __evenaccess *)0x8A060) +#define SMCI4 (*(volatile struct st_smci __evenaccess *)0x8A080) +#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci __evenaccess *)0xD00E0) +#define SMCI8 (*(volatile struct st_smci __evenaccess *)0xD0000) +#define SMCI9 (*(volatile struct st_smci __evenaccess *)0xD0020) +#define SMCI10 (*(volatile struct st_smci __evenaccess *)0xD0040) +#define SMCI11 (*(volatile struct st_smci __evenaccess *)0xD0060) +#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300) +#define SSIE0 (*(volatile struct st_ssie __evenaccess *)0x8A500) +#define SSIE1 (*(volatile struct st_ssie __evenaccess *)0x8A540) +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define TEMPS (*(volatile struct st_temps __evenaccess *)0x8C500) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 __evenaccess *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 __evenaccess *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 __evenaccess *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 __evenaccess *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 __evenaccess *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 __evenaccess *)0x8810C) +#define TPUA (*(volatile struct st_tpua __evenaccess *)0x88100) +#define USB (*(volatile struct st_usb __evenaccess *)0xA0400) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#define WDT (*(volatile struct st_wdt __evenaccess *)0x88020) +#define FLASHCONST (*(volatile struct st_flashconst __evenaccess *)0xFE7F7D90) +#define TEMPSCONST (*(volatile struct st_tempsconst __evenaccess *)0xFE7F7D7C) + +typedef enum enum_ir { +IR_BSC_BUSERR=16,IR_ICU_GROUPIE0=17, +IR_RAM_RAMERR, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT2=26,IR_ICU_SWINT, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMTW0_CMWI0, +IR_CMTW1_CMWI1, +IR_USB0_D0FIFO0=34,IR_USB0_D1FIFO0, +IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0, +IR_RSPI1_SPRI1,IR_RSPI1_SPTI1, +IR_QSPI_SPRI,IR_QSPI_SPTI, +IR_SDHI_SBFAI, +IR_MMCIF_MBFAI, +IR_SSIE0_SSITXI0,IR_SSIE0_SSIRXI0, +IR_SSIE1_SSIRTI1, +IR_RIIC1_RXI1=50,IR_RIIC1_TXI1, +IR_RIIC0_RXI0,IR_RIIC0_TXI0, +IR_RIIC2_RXI2,IR_RIIC2_TXI2, +IR_SCI0_RXI0=58,IR_SCI0_TXI0, +IR_SCI1_RXI1,IR_SCI1_TXI1, +IR_SCI2_RXI2,IR_SCI2_TXI2, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_SCI3_RXI3,IR_SCI3_TXI3, +IR_SCI4_RXI4,IR_SCI4_TXI4, +IR_SCI5_RXI5,IR_SCI5_TXI5, +IR_SCI6_RXI6,IR_SCI6_TXI6, +IR_LVD1_LVD1, +IR_LVD2_LVD2, +IR_USB0_USBR0, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_IWDT_IWUNI=95, +IR_WDT_WUNI, +IR_PDC_PCDFI, +IR_SCI7_RXI7,IR_SCI7_TXI7, +IR_SCI8_RXI8,IR_SCI8_TXI8, +IR_SCI9_RXI9,IR_SCI9_TXI9, +IR_SCI10_RXI10,IR_SCI10_TXI10, +IR_ICU_GROUPBE0,IR_ICU_GROUPBL2, +IR_RSPI2_SPRI2,IR_RSPI2_SPTI2, +IR_ICU_GROUPBL0,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1, +IR_SCI11_RXI11,IR_SCI11_TXI11, +IR_SCI12_RXI12,IR_SCI12_TXI12, +IR_DMAC_DMAC0I=120,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I, +IR_OST_OSTDI, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_PERIB_INTB128,IR_PERIB_INTB129,IR_PERIB_INTB130,IR_PERIB_INTB131,IR_PERIB_INTB132, +IR_PERIB_INTB133,IR_PERIB_INTB134,IR_PERIB_INTB135,IR_PERIB_INTB136,IR_PERIB_INTB137, +IR_PERIB_INTB138,IR_PERIB_INTB139,IR_PERIB_INTB140,IR_PERIB_INTB141,IR_PERIB_INTB142, +IR_PERIB_INTB143,IR_PERIB_INTB144,IR_PERIB_INTB145,IR_PERIB_INTB146,IR_PERIB_INTB147, +IR_PERIB_INTB148,IR_PERIB_INTB149,IR_PERIB_INTB150,IR_PERIB_INTB151,IR_PERIB_INTB152, +IR_PERIB_INTB153,IR_PERIB_INTB154,IR_PERIB_INTB155,IR_PERIB_INTB156,IR_PERIB_INTB157, +IR_PERIB_INTB158,IR_PERIB_INTB159,IR_PERIB_INTB160,IR_PERIB_INTB161,IR_PERIB_INTB162, +IR_PERIB_INTB163,IR_PERIB_INTB164,IR_PERIB_INTB165,IR_PERIB_INTB166,IR_PERIB_INTB167, +IR_PERIB_INTB168,IR_PERIB_INTB169,IR_PERIB_INTB170,IR_PERIB_INTB171,IR_PERIB_INTB172, +IR_PERIB_INTB173,IR_PERIB_INTB174,IR_PERIB_INTB175,IR_PERIB_INTB176,IR_PERIB_INTB177, +IR_PERIB_INTB178,IR_PERIB_INTB179,IR_PERIB_INTB180,IR_PERIB_INTB181,IR_PERIB_INTB182, +IR_PERIB_INTB183,IR_PERIB_INTB184,IR_PERIB_INTB185,IR_PERIB_INTB186,IR_PERIB_INTB187, +IR_PERIB_INTB188,IR_PERIB_INTB189,IR_PERIB_INTB190,IR_PERIB_INTB191,IR_PERIB_INTB192, +IR_PERIB_INTB193,IR_PERIB_INTB194,IR_PERIB_INTB195,IR_PERIB_INTB196,IR_PERIB_INTB197, +IR_PERIB_INTB198,IR_PERIB_INTB199,IR_PERIB_INTB200,IR_PERIB_INTB201,IR_PERIB_INTB202, +IR_PERIB_INTB203,IR_PERIB_INTB204,IR_PERIB_INTB205,IR_PERIB_INTB206,IR_PERIB_INTB207, +IR_PERIA_INTA208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212, +IR_PERIA_INTA213,IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217, +IR_PERIA_INTA218,IR_PERIA_INTA219,IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222, +IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225,IR_PERIA_INTA226,IR_PERIA_INTA227, +IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231,IR_PERIA_INTA232, +IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237, +IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242, +IR_PERIA_INTA243,IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247, +IR_PERIA_INTA248,IR_PERIA_INTA249,IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252, +IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255 +} enum_ir_t; + +typedef enum enum_dtce { +DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USB0_D0FIFO0=34,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSIE0_SSITXI0,DTCE_SSIE0_SSIRXI0, +DTCE_SSIE1_SSIRTI1, +DTCE_RIIC1_RXI1=50,DTCE_RIIC1_TXI1, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0=58,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI=97, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10,DTCE_SCI10_TXI10, +DTCE_RSPI2_SPRI2=108,DTCE_RSPI2_SPTI2, +DTCE_SCI11_RXI11=114,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I=120,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I=126,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +} enum_dtce_t; + +typedef enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_ICU_GROUPIE0=0x02, +IER_RAM_RAMERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMTW0_CMWI0=0x03, +IER_CMTW1_CMWI1=0x03, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04, +IER_RSPI1_SPRI1=0x05,IER_RSPI1_SPTI1=0x05, +IER_QSPI_SPRI=0x05,IER_QSPI_SPTI=0x05, +IER_SDHI_SBFAI=0x05, +IER_MMCIF_MBFAI=0x05, +IER_SSIE0_SSITXI0=0x05,IER_SSIE0_SSIRXI0=0x05, +IER_SSIE1_SSIRTI1=0x06, +IER_RIIC1_RXI1=0x06,IER_RIIC1_TXI1=0x06, +IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06, +IER_RIIC2_RXI2=0x06,IER_RIIC2_TXI2=0x06, +IER_SCI0_RXI0=0x07,IER_SCI0_TXI0=0x07, +IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07, +IER_SCI2_RXI2=0x07,IER_SCI2_TXI2=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_SCI3_RXI3=0x0A,IER_SCI3_TXI3=0x0A, +IER_SCI4_RXI4=0x0A,IER_SCI4_TXI4=0x0A, +IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A, +IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A, +IER_LVD1_LVD1=0x0B, +IER_LVD2_LVD2=0x0B, +IER_USB0_USBR0=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_IWDT_IWUNI=0x0B, +IER_WDT_WUNI=0x0C, +IER_PDC_PCDFI=0x0C, +IER_SCI7_RXI7=0x0C,IER_SCI7_TXI7=0x0C, +IER_SCI8_RXI8=0x0C,IER_SCI8_TXI8=0x0C, +IER_SCI9_RXI9=0x0C,IER_SCI9_TXI9=0x0C, +IER_SCI10_RXI10=0x0D,IER_SCI10_TXI10=0x0D, +IER_ICU_GROUPBE0=0x0D,IER_ICU_GROUPBL2=0x0D, +IER_RSPI2_SPRI2=0x0D,IER_RSPI2_SPTI2=0x0D, +IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E, +IER_SCI11_RXI11=0x0E,IER_SCI11_TXI11=0x0E, +IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E, +IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F, +IER_OST_OSTDI=0x0F, +IER_EXDMAC_EXDMAC0I=0x0F,IER_EXDMAC_EXDMAC1I=0x0F, +IER_PERIB_INTB128=0x10,IER_PERIB_INTB129=0x10,IER_PERIB_INTB130=0x10,IER_PERIB_INTB131=0x10,IER_PERIB_INTB132=0x10, +IER_PERIB_INTB133=0x10,IER_PERIB_INTB134=0x10,IER_PERIB_INTB135=0x10,IER_PERIB_INTB136=0x11,IER_PERIB_INTB137=0x11, +IER_PERIB_INTB138=0x11,IER_PERIB_INTB139=0x11,IER_PERIB_INTB140=0x11,IER_PERIB_INTB141=0x11,IER_PERIB_INTB142=0x11, +IER_PERIB_INTB143=0x11,IER_PERIB_INTB144=0x12,IER_PERIB_INTB145=0x12,IER_PERIB_INTB146=0x12,IER_PERIB_INTB147=0x12, +IER_PERIB_INTB148=0x12,IER_PERIB_INTB149=0x12,IER_PERIB_INTB150=0x12,IER_PERIB_INTB151=0x12,IER_PERIB_INTB152=0x13, +IER_PERIB_INTB153=0x13,IER_PERIB_INTB154=0x13,IER_PERIB_INTB155=0x13,IER_PERIB_INTB156=0x13,IER_PERIB_INTB157=0x13, +IER_PERIB_INTB158=0x13,IER_PERIB_INTB159=0x13,IER_PERIB_INTB160=0x14,IER_PERIB_INTB161=0x14,IER_PERIB_INTB162=0x14, +IER_PERIB_INTB163=0x14,IER_PERIB_INTB164=0x14,IER_PERIB_INTB165=0x14,IER_PERIB_INTB166=0x14,IER_PERIB_INTB167=0x14, +IER_PERIB_INTB168=0x15,IER_PERIB_INTB169=0x15,IER_PERIB_INTB170=0x15,IER_PERIB_INTB171=0x15,IER_PERIB_INTB172=0x15, +IER_PERIB_INTB173=0x15,IER_PERIB_INTB174=0x15,IER_PERIB_INTB175=0x15,IER_PERIB_INTB176=0x16,IER_PERIB_INTB177=0x16, +IER_PERIB_INTB178=0x16,IER_PERIB_INTB179=0x16,IER_PERIB_INTB180=0x16,IER_PERIB_INTB181=0x16,IER_PERIB_INTB182=0x16, +IER_PERIB_INTB183=0x16,IER_PERIB_INTB184=0x17,IER_PERIB_INTB185=0x17,IER_PERIB_INTB186=0x17,IER_PERIB_INTB187=0x17, +IER_PERIB_INTB188=0x17,IER_PERIB_INTB189=0x17,IER_PERIB_INTB190=0x17,IER_PERIB_INTB191=0x17,IER_PERIB_INTB192=0x18, +IER_PERIB_INTB193=0x18,IER_PERIB_INTB194=0x18,IER_PERIB_INTB195=0x18,IER_PERIB_INTB196=0x18,IER_PERIB_INTB197=0x18, +IER_PERIB_INTB198=0x18,IER_PERIB_INTB199=0x18,IER_PERIB_INTB200=0x19,IER_PERIB_INTB201=0x19,IER_PERIB_INTB202=0x19, +IER_PERIB_INTB203=0x19,IER_PERIB_INTB204=0x19,IER_PERIB_INTB205=0x19,IER_PERIB_INTB206=0x19,IER_PERIB_INTB207=0x19, +IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A, +IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A,IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B, +IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B,IER_PERIA_INTA222=0x1B, +IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C, +IER_PERIA_INTA228=0x1C,IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D, +IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D,IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D, +IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E, +IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E, +IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F,IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F, +IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F +} enum_ier_t; + +typedef enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_ICU_GROUPIE0=0, +IPR_RAM_RAMERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMTW0_CMWI0=6, +IPR_CMTW1_CMWI1=7, +IPR_USB0_D0FIFO0=34,IPR_USB0_D1FIFO0=35, +IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39, +IPR_RSPI1_SPRI1=40,IPR_RSPI1_SPTI1=41, +IPR_QSPI_SPRI=42,IPR_QSPI_SPTI=43, +IPR_SDHI_SBFAI=44, +IPR_MMCIF_MBFAI=45, +IPR_SSIE0_SSITXI0=46,IPR_SSIE0_SSIRXI0=47, +IPR_SSIE1_SSIRTI1=48, +IPR_RIIC1_RXI1=50,IPR_RIIC1_TXI1=51, +IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53, +IPR_RIIC2_RXI2=54,IPR_RIIC2_TXI2=55, +IPR_SCI0_RXI0=58,IPR_SCI0_TXI0=59, +IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61, +IPR_SCI2_RXI2=62,IPR_SCI2_TXI2=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_SCI3_RXI3=80,IPR_SCI3_TXI3=81, +IPR_SCI4_RXI4=82,IPR_SCI4_TXI4=83, +IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85, +IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87, +IPR_LVD1_LVD1=88, +IPR_LVD2_LVD2=89, +IPR_USB0_USBR0=90, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_IWDT_IWUNI=95, +IPR_WDT_WUNI=96, +IPR_PDC_PCDFI=97, +IPR_SCI7_RXI7=98,IPR_SCI7_TXI7=99, +IPR_SCI8_RXI8=100,IPR_SCI8_TXI8=101, +IPR_SCI9_RXI9=102,IPR_SCI9_TXI9=103, +IPR_SCI10_RXI10=104,IPR_SCI10_TXI10=105, +IPR_ICU_GROUPBE0=106,IPR_ICU_GROUPBL2=107, +IPR_RSPI2_SPRI2=108,IPR_RSPI2_SPTI2=109, +IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113, +IPR_SCI11_RXI11=114,IPR_SCI11_TXI11=115, +IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117, +IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124, +IPR_OST_OSTDI=125, +IPR_EXDMAC_EXDMAC0I=126,IPR_EXDMAC_EXDMAC1I=127, +IPR_PERIB_INTB128=128,IPR_PERIB_INTB129=129,IPR_PERIB_INTB130=130,IPR_PERIB_INTB131=131,IPR_PERIB_INTB132=132, +IPR_PERIB_INTB133=133,IPR_PERIB_INTB134=134,IPR_PERIB_INTB135=135,IPR_PERIB_INTB136=136,IPR_PERIB_INTB137=137, +IPR_PERIB_INTB138=138,IPR_PERIB_INTB139=139,IPR_PERIB_INTB140=140,IPR_PERIB_INTB141=141,IPR_PERIB_INTB142=142, +IPR_PERIB_INTB143=143,IPR_PERIB_INTB144=144,IPR_PERIB_INTB145=145,IPR_PERIB_INTB146=146,IPR_PERIB_INTB147=147, +IPR_PERIB_INTB148=148,IPR_PERIB_INTB149=149,IPR_PERIB_INTB150=150,IPR_PERIB_INTB151=151,IPR_PERIB_INTB152=152, +IPR_PERIB_INTB153=153,IPR_PERIB_INTB154=154,IPR_PERIB_INTB155=155,IPR_PERIB_INTB156=156,IPR_PERIB_INTB157=157, +IPR_PERIB_INTB158=158,IPR_PERIB_INTB159=159,IPR_PERIB_INTB160=160,IPR_PERIB_INTB161=161,IPR_PERIB_INTB162=162, +IPR_PERIB_INTB163=163,IPR_PERIB_INTB164=164,IPR_PERIB_INTB165=165,IPR_PERIB_INTB166=166,IPR_PERIB_INTB167=167, +IPR_PERIB_INTB168=168,IPR_PERIB_INTB169=169,IPR_PERIB_INTB170=170,IPR_PERIB_INTB171=171,IPR_PERIB_INTB172=172, +IPR_PERIB_INTB173=173,IPR_PERIB_INTB174=174,IPR_PERIB_INTB175=175,IPR_PERIB_INTB176=176,IPR_PERIB_INTB177=177, +IPR_PERIB_INTB178=178,IPR_PERIB_INTB179=179,IPR_PERIB_INTB180=180,IPR_PERIB_INTB181=181,IPR_PERIB_INTB182=182, +IPR_PERIB_INTB183=183,IPR_PERIB_INTB184=184,IPR_PERIB_INTB185=185,IPR_PERIB_INTB186=186,IPR_PERIB_INTB187=187, +IPR_PERIB_INTB188=188,IPR_PERIB_INTB189=189,IPR_PERIB_INTB190=190,IPR_PERIB_INTB191=191,IPR_PERIB_INTB192=192, +IPR_PERIB_INTB193=193,IPR_PERIB_INTB194=194,IPR_PERIB_INTB195=195,IPR_PERIB_INTB196=196,IPR_PERIB_INTB197=197, +IPR_PERIB_INTB198=198,IPR_PERIB_INTB199=199,IPR_PERIB_INTB200=200,IPR_PERIB_INTB201=201,IPR_PERIB_INTB202=202, +IPR_PERIB_INTB203=203,IPR_PERIB_INTB204=204,IPR_PERIB_INTB205=205,IPR_PERIB_INTB206=206,IPR_PERIB_INTB207=207, +IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212, +IPR_PERIA_INTA213=213,IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217, +IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219,IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222, +IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225,IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227, +IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231,IPR_PERIA_INTA232=232, +IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237, +IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242, +IPR_PERIA_INTA243=243,IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247, +IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249,IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252, +IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255, +IPR_ICU_SWI=3, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_CMTW0_=6, +IPR_CMTW1_=7, +IPR_SDHI_=44, +IPR_MMCIF_=45, +IPR_SSIE1_=48, +IPR_LVD1_=88, +IPR_LVD2_=89, +IPR_IWDT_=95, +IPR_WDT_=96, +IPR_PDC_=97, +IPR_OST_=125 +} enum_ipr_t; + +#pragma bit_order left +#pragma unpack + +typedef struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + unsigned short :3; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short BPEB:2; + unsigned short BPFB:2; + unsigned short BPHB:2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS4WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS5WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS6WCR2; + char wk11[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS7WCR2; + char wk12[1926]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS4CR; + char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS4REC; + char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS5CR; + char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS5REC; + char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS6CR; + char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS6REC; + char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS7CR; + char wk27[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS7REC; + char wk28[4]; + union { + unsigned short WORD; + struct { + unsigned short RCVENM7:1; + unsigned short RCVENM6:1; + unsigned short RCVENM5:1; + unsigned short RCVENM4:1; + unsigned short RCVENM3:1; + unsigned short RCVENM2:1; + unsigned short RCVENM1:1; + unsigned short RCVENM0:1; + unsigned short RCVEN7:1; + unsigned short RCVEN6:1; + unsigned short RCVEN5:1; + unsigned short RCVEN4:1; + unsigned short RCVEN3:1; + unsigned short RCVEN2:1; + unsigned short RCVEN1:1; + unsigned short RCVEN0:1; + } BIT; + } CSRECEN; + char wk29[894]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BSIZE:2; + unsigned char :3; + unsigned char EXENB:1; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EMODE:1; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BE:1; + } BIT; + } SDAMOD; + char wk30[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SFEN:1; + } BIT; + } SDSELF; + char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short REFW:4; + unsigned short RFC:12; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RFEN:1; + } BIT; + } SDRFEN; + char wk32[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char INIRQ:1; + } BIT; + } SDICR; + char wk33[3]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short PRC:3; + unsigned short ARFC:4; + unsigned short ARFI:4; + } BIT; + } SDIR; + char wk34[26]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MXC:2; + } BIT; + } SDADR; + char wk35[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RAS:3; + unsigned long :2; + unsigned long RCD:2; + unsigned long RP:3; + unsigned long WR:1; + unsigned long :5; + unsigned long CL:3; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short MR:15; + } BIT; + } SDMOD; + char wk36[6]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SRFST:1; + unsigned char INIST:1; + unsigned char :2; + unsigned char MRSST:1; + } BIT; + } SDSR; + char wk37[269231]; + union { + unsigned long LONG; + struct { + unsigned long PRERR:1; + unsigned long :12; + unsigned long PR5SEL:3; + unsigned long :1; + unsigned long PR4SEL:3; + unsigned long :1; + unsigned long PR3SEL:3; + unsigned long :1; + unsigned long PR2SEL:3; + unsigned long :1; + unsigned long PR1SEL:3; + } BIT; + } EBMAPCR; +} st_bsc_t; + +typedef struct st_cac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CFME:1; + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + unsigned char EDGES:2; + unsigned char TCSS:2; + unsigned char FMCS:3; + unsigned char CACREFE:1; + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + unsigned char DFS:2; + unsigned char RCDS:2; + unsigned char RSCS:3; + unsigned char RPS:1; + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char OVFFCL:1; + unsigned char MENDFCL:1; + unsigned char FERRFCL:1; + unsigned char :1; + unsigned char OVFIE:1; + unsigned char MENDIE:1; + unsigned char FERRIE:1; + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OVFF:1; + unsigned char MENDF:1; + unsigned char FERRF:1; + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long :3; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long IDE:1; + unsigned long RTR:1; + unsigned long :1; + unsigned long SID:11; + unsigned long EID:18; + } BIT; + } FIDCR1; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MKIVLR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned char MB31:1; + unsigned char MB30:1; + unsigned char MB29:1; + unsigned char MB28:1; + unsigned char MB27:1; + unsigned char MB26:1; + unsigned char MB25:1; + unsigned char MB24:1; + unsigned char MB23:1; + unsigned char MB22:1; + unsigned char MB21:1; + unsigned char MB20:1; + unsigned char MB19:1; + unsigned char MB18:1; + unsigned char MB17:1; + unsigned char MB16:1; + unsigned char MB15:1; + unsigned char MB14:1; + unsigned char MB13:1; + unsigned char MB12:1; + unsigned char MB11:1; + unsigned char MB10:1; + unsigned char MB9:1; + unsigned char MB8:1; + unsigned char MB7:1; + unsigned char MB6:1; + unsigned char MB5:1; + unsigned char MB4:1; + unsigned char MB3:1; + unsigned char MB2:1; + unsigned char MB1:1; + unsigned char MB0:1; + } BIT; + } MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char TRMABT:1; + unsigned char TRMACTIVE:1; + unsigned char SENTDATA:1; + } TX; + struct { + unsigned char TRMREQ:1; + unsigned char RECREQ:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char MSGLOST:1; + unsigned char INVALDATA:1; + unsigned char NEWDATA:1; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :2; + unsigned char RBOC:1; + unsigned char BOM:2; + unsigned char SLPM:1; + unsigned char CANM:2; + unsigned char TSPS:2; + unsigned char TSRC:1; + unsigned char TPM:1; + unsigned char MLM:1; + unsigned char IDFM:2; + unsigned char MBM:1; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :1; + unsigned char RECST:1; + unsigned char TRMST:1; + unsigned char BOST:1; + unsigned char EPST:1; + unsigned char SLPST:1; + unsigned char HLTST:1; + unsigned char RSTST:1; + unsigned char EST:1; + unsigned char TABST:1; + unsigned char FMLST:1; + unsigned char NMLST:1; + unsigned char TFST:1; + unsigned char RFST:1; + unsigned char SDST:1; + unsigned char NDST:1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short H; + unsigned short L; + } WORD; + struct { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct { + unsigned long TSEG1:4; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long SJW:2; + unsigned long :1; + unsigned long TSEG2:3; + unsigned long :7; + unsigned long CCLKS:1; + } BIT; + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEST:1; + unsigned char RFWST:1; + unsigned char RFFST:1; + unsigned char RFMLF:1; + unsigned char RFUST:3; + unsigned char RFE:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFEST:1; + unsigned char TFFST:1; + unsigned char :2; + unsigned char TFUST:3; + unsigned char TFE:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BLIE:1; + unsigned char OLIE:1; + unsigned char ORIE:1; + unsigned char BORIE:1; + unsigned char BOEIE:1; + unsigned char EPIE:1; + unsigned char EWIE:1; + unsigned char BEIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BLIF:1; + unsigned char OLIF:1; + unsigned char ORIF:1; + unsigned char BORIF:1; + unsigned char BOEIF:1; + unsigned char EPIF:1; + unsigned char EWIF:1; + unsigned char BEIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char EDPM:1; + unsigned char ADEF:1; + unsigned char BE0F:1; + unsigned char BE1F:1; + unsigned char CEF:1; + unsigned char AEF:1; + unsigned char FEF:1; + unsigned char SEF:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char SEST:1; + unsigned char :2; + unsigned char MBNST:5; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MBSM:2; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TSTM:2; + unsigned char TSTE:1; + } BIT; + } TCR; +} st_can_t; + +typedef struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +} st_cmt_t; + +typedef struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_cmtw { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short STR:1; + } BIT; + } CMWSTR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short CCLR:3; + unsigned short :3; + unsigned short CMS:1; + unsigned short :1; + unsigned short OC1IE:1; + unsigned short OC0IE:1; + unsigned short IC1IE:1; + unsigned short IC0IE:1; + unsigned short CMWIE:1; + unsigned short :1; + unsigned short CKS:2; + } BIT; + } CMWCR; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short CMWE:1; + unsigned short :1; + unsigned short OC1E:1; + unsigned short OC0E:1; + unsigned short OC1:2; + unsigned short OC0:2; + unsigned short :2; + unsigned short IC1E:1; + unsigned short IC0E:1; + unsigned short IC1:2; + unsigned short IC0:2; + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +} st_cmtw_t; + +typedef struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char LMS:1; + unsigned char :3; + unsigned char GPS:3; + } BIT; + } CRCCR; + char wk0[3]; + union { + unsigned long LONG; + unsigned char BYTE; + } CRCDIR; + union { + unsigned long LONG; + unsigned short WORD; + unsigned char BYTE; + } CRCDOR; +} st_crc_t; + +typedef struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char DAE:1; + unsigned char :5; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + unsigned char :7; + } BIT; + } DAADSCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAAMP1:1; + unsigned char DAAMP0:1; + unsigned char :6; + } BIT; + } DAAMPCR; + char wk1[19]; + union { + unsigned char BYTE; + struct { + unsigned char DAASW1:1; + unsigned char DAASW0:1; + unsigned char :6; + } BIT; + } DAASWCR; + char wk2[17763]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char AMADSEL1:1; + unsigned char :1; + } BIT; + } DAADUSR; +} st_da_t; + +typedef struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char DMIS7:1; + unsigned char DMIS6:1; + unsigned char DMIS5:1; + unsigned char DMIS4:1; + unsigned char :4; + } BIT; + } DMIST; +} st_dmac_t; + +typedef struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +} st_dmac0_t; + +typedef struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +} st_dmac1_t; + +typedef struct st_doc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DOPCFCL:1; + unsigned char DOPCF:1; + unsigned char DOPCIE:1; + unsigned char :1; + unsigned char DCSEL:1; + unsigned char OMS:2; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +} st_doc_t; + +typedef struct st_drw2d { + union { + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long SPANSTR:1; + unsigned long SPANABT:1; + unsigned long UNIONCD:1; + unsigned long UNIONAB:1; + unsigned long UNION56:1; + unsigned long UNION34:1; + unsigned long UNION12:1; + unsigned long BAND2EN:1; + unsigned long BAND1EN:1; + unsigned long LIM6TH:1; + unsigned long LIM5TH:1; + unsigned long LIM4TH:1; + unsigned long LIM3TH:1; + unsigned long LIM2TH:1; + unsigned long LIM1TH:1; + unsigned long QUAD3EN:1; + unsigned long QUAD2EN:1; + unsigned long QUAD1EN:1; + unsigned long LIM6EN:1; + unsigned long LIM5EN:1; + unsigned long LIM4EN:1; + unsigned long LIM3EN:1; + unsigned long LIM2EN:1; + unsigned long LIM1EN:1; + } BIT; + } CONTROL; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long DLIR:1; + unsigned long ENUIR:1; + unsigned long DLSTACT:1; + unsigned long CACHEDTY:1; + unsigned long BSYWR:1; + unsigned long BSYENUM:1; + } BIT; + } STATUS; + }; + union { + union { + unsigned long LONG; + struct { + unsigned long RLEPIXW:2; + unsigned long BDIA:1; + unsigned long BSIA:1; + unsigned long CLUTFORM:1; + unsigned long COLKEYEN:1; + unsigned long CLUTEN:1; + unsigned long RLEEN:1; + unsigned long WRALPHA:2; + unsigned long WRFMT:2; + unsigned long RDFMT:2; + unsigned long TEXFILTY:1; + unsigned long TEXFILTX:1; + unsigned long TEXCLPY:1; + unsigned long TEXCLPX:1; + unsigned long BC2:1; + unsigned long BDI:1; + unsigned long BSI:1; + unsigned long BDF:1; + unsigned long BSF:1; + unsigned long WRFMT2:1; + unsigned long BDFA:1; + unsigned long BSFA:1; + unsigned long RDFMT2:2; + unsigned long USEACB:1; + unsigned long PTNSRCL5:1; + unsigned long TEXENA:1; + unsigned long PTNEN:1; + } BIT; + } CONTROL2; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long ACBLD:1; + unsigned long :1; + unsigned long COLKEY:1; + unsigned long TEXCLUT256:1; + unsigned long RLEUNIT:1; + unsigned long :1; + unsigned long TEXCLUT:1; + unsigned long PERFCNT:1; + unsigned long TXCACHE:1; + unsigned long FBCACHE:1; + unsigned long DLR:1; + unsigned long :5; + unsigned long REV:12; + } BIT; + } HWVER; + }; + char wk0[8]; + unsigned long L1START; + unsigned long L2START; + unsigned long L3START; + unsigned long L4START; + unsigned long L5START; + unsigned long L6START; + unsigned long L1XADD; + unsigned long L2XADD; + unsigned long L3XADD; + unsigned long L4XADD; + unsigned long L5XADD; + unsigned long L6XADD; + unsigned long L1YADD; + unsigned long L2YADD; + unsigned long L3YADD; + unsigned long L4YADD; + unsigned long L5YADD; + unsigned long L6YADD; + unsigned long L1BAND; + unsigned long L2BAND; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long COL1A:8; + unsigned long COL1R:8; + unsigned long COL1G:8; + unsigned long COL1B:8; + } BIT; + } COLOR1; + union { + unsigned long LONG; + struct { + unsigned long COL2A:8; + unsigned long COL2R:8; + unsigned long COL2G:8; + unsigned long COL2B:8; + } BIT; + } COLOR2; + char wk2[8]; + unsigned long PATTERN; + union { + unsigned long LONG; + struct { + unsigned long Y:16; + unsigned long X:16; + } BIT; + } SIZE; + union { + unsigned long LONG; + struct { + unsigned long SSD:16; + unsigned long PITCH:16; + } BIT; + } PITCH; + unsigned long ORIGIN; + char wk3[12]; + unsigned long LUST; + unsigned long LUXADD; + unsigned long LUYADD; + unsigned long LVSTI; + unsigned long LVSTF; + unsigned long LVXADDI; + unsigned long LVYADDI; + union { + unsigned long LONG; + struct { + unsigned long LVYADDF:16; + unsigned long LVXADDF:16; + } BIT; + } LVYXADDF; + char wk4[4]; + unsigned long TEXPITCH; + union { + unsigned long LONG; + struct { + unsigned long TEXVMSK:21; + unsigned long TEXUMSK:11; + } BIT; + } TEXMSK; + unsigned long TEXORG; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long DLIRCLR:1; + unsigned long ENUIRCLR:1; + unsigned long DLIREN:1; + unsigned long ENUIREN:1; + } BIT; + } IRQCTL; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CFLUTX:1; + unsigned long CENTX:1; + unsigned long CFLUFX:1; + unsigned long CENFX:1; + } BIT; + } CACHECTL; + unsigned long DLISTST; + unsigned long PERFCNT1; + unsigned long PERFCNT2; + union { + unsigned long LONG; + struct { + unsigned long TRG2:16; + unsigned long TRG1:16; + } BIT; + } PERFTRG; + char wk5[4]; + unsigned long TEXCLADDR; + unsigned long TEXCLDATA; + unsigned long TEXCLOFST; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } COLKEY; +} st_drw2d_t; + +typedef struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + unsigned char :4; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; + void *DTCIBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SQTFRL:1; + } BIT; + } DTCOR; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ESPSEL:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSQE; + unsigned long DTCDISP; +} st_dtc_t; + +typedef struct st_eccram { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RAMMOD:2; + } BIT; + } ECCRAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC2ERR:1; + } BIT; + } ECCRAM2STS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC1STSEN:1; + } BIT; + } ECCRAM1STSEN; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ECC1ERR:1; + } BIT; + } ECCRAM1STS; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char PRCR:1; + } BIT; + } ECCRAMPRCR; + char wk0[3]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ECC2EAD:12; + unsigned long :3; + } BIT; + } ECCRAM2ECAD; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ECC1EAD:12; + unsigned long :3; + } BIT; + } ECCRAM1ECAD; + union { + unsigned char BYTE; + struct { + unsigned char KW2:7; + unsigned char PRCR2:1; + } BIT; + } ECCRAMPRCR2; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TSTBYP:1; + } BIT; + } ECCRAMETST; +} st_eccram_t; + +typedef struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long RABT:1; + unsigned long RFCOF:1; + unsigned long :1; + unsigned long ECI:1; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :4; + unsigned long CND:1; + unsigned long DLC:1; + unsigned long CD:1; + unsigned long TRO:1; + unsigned long RMAF:1; + unsigned long :2; + unsigned long RRF:1; + unsigned long RTLF:1; + unsigned long RTSF:1; + unsigned long PRE:1; + unsigned long CERF:1; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long RABTIP:1; + unsigned long RFCOFIP:1; + unsigned long :1; + unsigned long ECIIP:1; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :4; + unsigned long CNDIP:1; + unsigned long DLCIP:1; + unsigned long CDIP:1; + unsigned long TROIP:1; + unsigned long RMAFIP:1; + unsigned long :2; + unsigned long RRFIP:1; + unsigned long RTLFIP:1; + unsigned long RTSFIP:1; + unsigned long PREIP:1; + unsigned long CERFIP:1; + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RMAFCE:1; + unsigned long :2; + unsigned long RRFCE:1; + unsigned long :4; + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RNR:1; + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long ELB:1; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_edmac_t; + +typedef struct st_elc { + union { + unsigned char BYTE; + struct { + unsigned char ELCON:1; + unsigned char :7; + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR0; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR7; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR10; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR11; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR12; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR13; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR16; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR18; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR19; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR20; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR21; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR22; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR23; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR25; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR26; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR27; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR28; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char MTU3MD:2; + unsigned char :4; + unsigned char MTU0MD:2; + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTU4MD:2; + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CMT1MD:2; + unsigned char :2; + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + unsigned char TMR3MD:2; + unsigned char TMR2MD:2; + unsigned char TMR1MD:2; + unsigned char TMR0MD:2; + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL3; + union { + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; + } BIT; +#endif + } ELSEGR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR33; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR35; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR36; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR37; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR38; + char wk8[6]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR45; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char TPU3MD:2; + unsigned char TPU2MD:2; + unsigned char TPU1MD:2; + unsigned char TPU0MD:2; + } BIT; + } ELOPF; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMTW0MD:2; + } BIT; + } ELOPH; + char wk11[4]; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR48; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR49; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR50; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR51; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR52; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR53; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR54; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR55; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR56; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR57; +} st_elc_t; + +typedef struct st_eptpc { + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RESET:1; + } BIT; + } PTRSTR; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long SCLKSEL:3; + unsigned long :5; + unsigned long SCLKDIV:3; + } BIT; + } STCSELR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long BYPASS1:1; + unsigned long :15; + unsigned long BYPASS0:1; + } BIT; + } SYBYPSR; + char wk0[15092]; + unsigned long MIESR; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long CYC5:1; + unsigned long CYC4:1; + unsigned long CYC3:1; + unsigned long CYC2:1; + unsigned long CYC1:1; + unsigned long CYC0:1; + unsigned long :12; + unsigned long PR:1; + unsigned long SY1:1; + unsigned long SY0:1; + unsigned long ST:1; + } BIT; + } MIEIPR; + char wk1[8]; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + unsigned long PLSP:1; + unsigned long :2; + unsigned long CYCN5:1; + unsigned long CYCN4:1; + unsigned long CYCN3:1; + unsigned long CYCN2:1; + unsigned long CYCN1:1; + unsigned long CYCN0:1; + unsigned long :2; + unsigned long CYCP5:1; + unsigned long CYCP4:1; + unsigned long CYCP3:1; + unsigned long CYCP2:1; + unsigned long CYCP1:1; + unsigned long CYCP0:1; + } BIT; + } ELIPPR; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + unsigned long PLSP:1; + unsigned long :2; + unsigned long CYCN5:1; + unsigned long CYCN4:1; + unsigned long CYCN3:1; + unsigned long CYCN2:1; + unsigned long CYCN1:1; + unsigned long CYCN0:1; + unsigned long :2; + unsigned long CYCP5:1; + unsigned long CYCP4:1; + unsigned long CYCP3:1; + unsigned long CYCP2:1; + unsigned long CYCP1:1; + unsigned long CYCP0:1; + } BIT; + } ELIPACR; + char wk2[40]; + unsigned long STSR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long W10D:1; + unsigned long SYNTOUT:1; + unsigned long :1; + unsigned long SYNCOUT:1; + unsigned long SYNC:1; + } BIT; + } STIPR; + char wk3[8]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long STCF:2; + } BIT; + } STCFR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long ALEN1:1; + unsigned long ALEN0:1; + unsigned long :4; + unsigned long DVTH:4; + unsigned long SYTH:4; + unsigned long W10S:1; + unsigned long :1; + unsigned long CMOD:1; + unsigned long :5; + unsigned long WINT:8; + } BIT; + } STMR; + unsigned long SYNTOR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long IPTSEL5:1; + unsigned long IPTSEL4:1; + unsigned long IPTSEL3:1; + unsigned long IPTSEL2:1; + unsigned long IPTSEL1:1; + unsigned long IPTSEL0:1; + } BIT; + } IPTSELR; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long MINTEN5:1; + unsigned long MINTEN4:1; + unsigned long MINTEN3:1; + unsigned long MINTEN2:1; + unsigned long MINTEN1:1; + unsigned long MINTEN0:1; + } BIT; + } MITSELR; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long ELTDIS5:1; + unsigned long ELTDIS4:1; + unsigned long ELTDIS3:1; + unsigned long ELTDIS2:1; + unsigned long ELTDIS1:1; + unsigned long ELTDIS0:1; + } BIT; + } ELTSELR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SYSEL:1; + } BIT; + } STCHSELR; + char wk5[16]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long STR:1; + } BIT; + } SYNSTARTR; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LOAD:1; + } BIT; + } LCIVLDR; + char wk6[8]; + unsigned long SYNTDARU; + unsigned long SYNTDARL; + unsigned long SYNTDBRU; + unsigned long SYNTDBRL; + char wk7[16]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long VALU:16; + } BIT; + } LCIVRU; + unsigned long LCIVRM; + unsigned long LCIVRL; + char wk8[104]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long GW10:1; + } BIT; + } GETW10R; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long LMTU:31; + } BIT; + } PLIMITRU; + unsigned long PLIMITRM; + unsigned long PLIMITRL; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long LMTU:31; + } BIT; + } MLIMITRU; + unsigned long MLIMITRM; + unsigned long MLIMITRL; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long INFO:1; + } BIT; + } GETINFOR; + char wk9[44]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CNTU:16; + } BIT; + } LCCVRU; + unsigned long LCCVRM; + unsigned long LCCVRL; + char wk10[148]; + unsigned long PW10VRU; + unsigned long PW10VRM; + unsigned long PW10VRL; + char wk11[180]; + unsigned long MW10RU; + unsigned long MW10RM; + unsigned long MW10RL; + char wk12[36]; + unsigned long TMSTTRU0; + unsigned long TMSTTRL0; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR0; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR0; + unsigned long TMSTTRU1; + unsigned long TMSTTRL1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR1; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR1; + unsigned long TMSTTRU2; + unsigned long TMSTTRL2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR2; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR2; + unsigned long TMSTTRU3; + unsigned long TMSTTRL3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR3; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR3; + unsigned long TMSTTRU4; + unsigned long TMSTTRL4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR4; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR4; + unsigned long TMSTTRU5; + unsigned long TMSTTRL5; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long CYC:30; + } BIT; + } TMCYCR5; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WTH:29; + } BIT; + } TMPLSR5; + char wk13[28]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } TMSTARTR; + char wk14[128]; + unsigned long PRSR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long URE1:1; + unsigned long URE0:1; + unsigned long :19; + unsigned long MACE:1; + unsigned long :4; + unsigned long OVRE3:1; + unsigned long OVRE2:1; + unsigned long OVRE1:1; + unsigned long OVRE0:1; + } BIT; + } PRIPR; + char wk15[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PRMACRU0; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PRMACRL0; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PRMACRU1; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PRMACRL1; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long TDIS:2; + } BIT; + } TRNDISR; + char wk16[12]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long FWD1:1; + unsigned long FWD0:1; + unsigned long :7; + unsigned long MOD:1; + } BIT; + } TRNMR; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long THVAL:11; + } BIT; + } TRNCTTDR; +} st_eptpc_t; + +typedef struct st_eptpc0 { + unsigned long SYSR; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long GENDN:1; + unsigned long RESDN:1; + unsigned long :1; + unsigned long INFABT:1; + unsigned long :1; + unsigned long RECLP:1; + unsigned long :5; + unsigned long DRQOVR:1; + unsigned long INTDEV:1; + unsigned long DRPTO:1; + unsigned long :1; + unsigned long MPDUD:1; + unsigned long INTCHG:1; + unsigned long OFMUD:1; + } BIT; + } SYIPR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } SYMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } SYMACRL; + unsigned long SYLLCCTLR; + unsigned long SYIPADDRR; + char wk1[32]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TRSP:4; + unsigned long VER:4; + } BIT; + } SYSPVRR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long DNUM:8; + } BIT; + } SYDOMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long :1; + unsigned long FLAG8:1; + unsigned long :2; + unsigned long FLAG5:1; + unsigned long FLAG4:1; + unsigned long FLAG3:1; + unsigned long FLAG2:1; + unsigned long FLAG1:1; + unsigned long FLAG0:1; + } BIT; + } ANFR; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long :8; + } BIT; + } SYNFR; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long :10; + } BIT; + } DYRQFR; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long FLAG14:1; + unsigned long FLAG13:1; + unsigned long :2; + unsigned long FLAG10:1; + unsigned long FLAG9:1; + unsigned long FLAG8:1; + unsigned long :8; + } BIT; + } DYRPFR; + unsigned long SYCIDRU; + unsigned long SYCIDRL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PNUM:16; + } BIT; + } SYPNUMR; + char wk3[20]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long ANUP:1; + unsigned long STUP:1; + unsigned long BMUP:1; + } BIT; + } SYRVLDR; + char wk4[12]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long PDFUP:3; + unsigned long :1; + unsigned long PDRP:3; + unsigned long :1; + unsigned long PDRQ:3; + unsigned long :1; + unsigned long DRP:3; + unsigned long :1; + unsigned long DRQ:3; + unsigned long :1; + unsigned long FUP:3; + unsigned long :1; + unsigned long SYNC:3; + unsigned long :2; + unsigned long ANCE:2; + } BIT; + } SYRFL1R; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long ILL:2; + unsigned long :22; + unsigned long SIG:2; + unsigned long :2; + unsigned long MAN:2; + } BIT; + } SYRFL2R; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long PDRQ:1; + unsigned long :3; + unsigned long DRQ:1; + unsigned long :3; + unsigned long SYNC:1; + unsigned long :3; + unsigned long ANCE:1; + } BIT; + } SYTRENR; + char wk5[4]; + unsigned long MTCIDU; + unsigned long MTCIDL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PNUM:16; + } BIT; + } MTPID; + char wk6[20]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DREQ:8; + unsigned long SYNC:8; + unsigned long ANCE:8; + } BIT; + } SYTLIR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DRESP:8; + unsigned long SYNC:8; + unsigned long ANCE:8; + } BIT; + } SYRLIR; + unsigned long OFMRU; + unsigned long OFMRL; + unsigned long MPDRU; + unsigned long MPDRL; + char wk7[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long GMPR1:8; + unsigned long :8; + unsigned long GMPR2:8; + } BIT; + } GMPR; + unsigned long GMCQR; + unsigned long GMIDRU; + unsigned long GMIDRL; + union { + unsigned long LONG; + struct { + unsigned long CUTO:16; + unsigned long :8; + unsigned long TSRC:8; + } BIT; + } CUOTSR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long SRMV:16; + } BIT; + } SRR; + char wk8[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PPMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PPMACRL; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } PDMACRU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } PDMACRL; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TYPE:16; + } BIT; + } PETYPER; + char wk9[12]; + unsigned long PPIPR; + unsigned long PDIPR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long EVTO:8; + } BIT; + } PETOSR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long GETO:8; + } BIT; + } PGTOSR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long PRTL:8; + } BIT; + } PPTTLR; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long PDTL:8; + } BIT; + } PDTTLR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EVUPT:16; + } BIT; + } PEUDPR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long GEUPT:16; + } BIT; + } PGUDPR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long EXTPRM:1; + unsigned long :13; + unsigned long ENB:1; + unsigned long PRT:1; + unsigned long SEL:1; + } BIT; + } FFLTR; + char wk10[28]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } FMAC0RU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } FMAC0RL; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACU:24; + } BIT; + } FMAC1RU; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long MACL:24; + } BIT; + } FMAC1RL; + char wk11[80]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ASYMU:16; + } BIT; + } DASYMRU; + unsigned long DASYMRL; + union { + unsigned long LONG; + struct { + unsigned long INGP:16; + unsigned long EGP:16; + } BIT; + } TSLATR; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TCMOD:1; + unsigned long :3; + unsigned long FILDIS:1; + unsigned long :3; + unsigned long SBDIS:1; + unsigned long :4; + unsigned long TCYC:8; + } BIT; + } SYCONFR; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long FORM1:1; + unsigned long FORM0:1; + } BIT; + } SYFORMR; + unsigned long RSTOUTR; +} st_eptpc0_t; + +typedef struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long TPC:1; + unsigned long ZPF:1; + unsigned long PFR:1; + unsigned long RXF:1; + unsigned long TXF:1; + unsigned long :3; + unsigned long PRCEF:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long RE:1; + unsigned long TE:1; + unsigned long :1; + unsigned long ILB:1; + unsigned long RTM:1; + unsigned long DM:1; + unsigned long PRM:1; + } BIT; + } ECMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long RFL:12; + } BIT; + } RFLR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFR:1; + unsigned long PSRTO:1; + unsigned long :1; + unsigned long LCHNG:1; + unsigned long MPD:1; + unsigned long ICD:1; + } BIT; + } ECSR; + char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :26; + unsigned long BFSIPR:1; + unsigned long PSRTOIP:1; + unsigned long :1; + unsigned long LCHNGIP:1; + unsigned long MPDIP:1; + unsigned long ICDIP:1; + } BIT; + } ECSIPR; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long MDI:1; + unsigned long MDO:1; + unsigned long MMD:1; + unsigned long MDC:1; + } BIT; + } PIR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long LMON:1; + } BIT; + } PSR; + char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long RMD:20; + } BIT; + } RDMLR; + char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long IPG:5; + } BIT; + } IPGR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long AP:16; + } BIT; + } APR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MP:16; + } BIT; + } MPR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long RPAUSE:8; + } BIT; + } RFCF; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long TPAUSE:16; + } BIT; + } TPAUSER; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long TXP:8; + } BIT; + } TPAUSECR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long BCF:16; + } BIT; + } BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MA:16; + } BIT; + } MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +} st_etherc_t; + +typedef struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +} st_exdmac_t; + +typedef struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char DACKSEL:1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +} st_exdmac0_t; + +typedef struct st_exdmac1 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char DACKS:1; + unsigned char DACKE:1; + unsigned char DACKW:1; + unsigned char DACKSEL:1; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long AMS:1; + unsigned long DIR:1; + unsigned long SM:2; + unsigned long :1; + unsigned long SARA:5; + unsigned long DM:2; + unsigned long :1; + unsigned long DARA:5; + } BIT; + } EDMAMD; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } EDMSTS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DREQS:2; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EREQ:1; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PREQ:1; + } BIT; + } EDMPRF; +} st_exdmac1_t; + +typedef struct st_flash { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ROMCEN:1; + } BIT; + } ROMCE; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ROMCIV:1; + } BIT; + } ROMCIV; + char wk1[58]; + unsigned long NCRG0; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long NCSZ:17; + unsigned long NC3E:1; + unsigned long NC2E:1; + unsigned long NC1E:1; + unsigned long :1; + } BIT; + } NCRC0; + unsigned long NCRG1; + union { + unsigned long LONG; + struct { + unsigned long :11; + unsigned long NCSZ:17; + unsigned long NC3E:1; + unsigned long NC2E:1; + unsigned long NC1E:1; + unsigned long :1; + } BIT; + } NCRC1; + char wk2[45638]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char FLWE:2; + } BIT; + } FWEPROR; + char wk3[7798185]; + unsigned char EEPFCLK; + char wk4[8143]; + union { + unsigned char BYTE; + struct { + unsigned char CFAE:1; + unsigned char :2; + unsigned char CMDLK:1; + unsigned char DFAE:1; + unsigned char :3; + } BIT; + } FASTAT; + char wk5[3]; + union { + unsigned char BYTE; + struct { + unsigned char CFAEIE:1; + unsigned char :2; + unsigned char CMDLKIE:1; + unsigned char DFAEIE:1; + unsigned char :3; + } BIT; + } FAEINT; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRDYIE:1; + } BIT; + } FRDYIE; + char wk7[23]; + union { + unsigned long LONG; + struct { + unsigned long FSADDR:32; + } BIT; + } FSADDR; + union { + unsigned long LONG; + struct { + unsigned long FEADDR:32; + } BIT; + } FEADDR; + char wk8[72]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ILGCOMERR:1; + unsigned long FESETERR:1; + unsigned long SECERR:1; + unsigned long OTERR:1; + unsigned long :4; + unsigned long FRDY:1; + unsigned long ILGLERR:1; + unsigned long ERSERR:1; + unsigned long PRGERR:1; + unsigned long SUSRDY:1; + unsigned long DBFULL:1; + unsigned long ERSSPD:1; + unsigned long PRGSPD:1; + unsigned long :1; + unsigned long FLWEERR:1; + unsigned long :6; + } BIT; + } FSTATR; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRYC:1; + } BIT; + } FENTRYR; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :7; + unsigned short SUINIT:1; + } BIT; + } FSUINITR; + char wk10[18]; + union { + unsigned short WORD; + struct { + unsigned short CMDR:8; + unsigned short PCMDR:8; + } BIT; + } FCMDR; + char wk11[46]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCDIR:1; + } BIT; + } FBCCNT; + char wk12[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCST:1; + } BIT; + } FBCSTAT; + char wk13[3]; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long PSADR:17; + } BIT; + } FPSADDR; + union { + unsigned long LONG; + struct { + unsigned long BTFLG:1; + unsigned long :3; + unsigned long FAWE:12; + unsigned long FSPR:1; + unsigned long :3; + unsigned long FAWS:12; + } BIT; + } FAWMON; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short ESUSPMD:1; + } BIT; + } FCPSR; + char wk14[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short PCKA:8; + } BIT; + } FPCKAR; + char wk15[2]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short SAS:2; + } BIT; + } FSUACR; +} st_flash_t; + +typedef struct st_glcdc { + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR1CLUT0[256]; + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR1CLUT1[256]; + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR2CLUT0[256]; + union { + unsigned long LONG; + struct { + unsigned long A:8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } GR2CLUT1[256]; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SWRST:1; + unsigned long :7; + unsigned long VEN:1; + unsigned long :7; + unsigned long EN:1; + } BIT; + } BGEN; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long FV:11; + unsigned long :5; + unsigned long FH:11; + } BIT; + } BGPERI; + union { + unsigned long LONG; + struct { + unsigned long :12; + unsigned long VP:4; + unsigned long :12; + unsigned long HP:4; + } BIT; + } BGSYNC; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long VP:11; + unsigned long :5; + unsigned long VW:11; + } BIT; + } BGVSIZE; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HP:11; + unsigned long :5; + unsigned long HW:11; + } BIT; + } BGHSIZE; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long R:8; + unsigned long G:8; + unsigned long B:8; + } BIT; + } BGCOLOR; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SWRST:1; + unsigned long :7; + unsigned long VEN:1; + unsigned long :7; + unsigned long EN:1; + } BIT; + } BGMON; + char wk0[228]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GR1VEN; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RENB:1; + } BIT; + } GR1FLMRD; + char wk1[4]; + unsigned long GR1FLM2; + union { + unsigned long LONG; + struct { + unsigned long LNOFF:16; + unsigned long :16; + } BIT; + } GR1FLM3; + char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long LNNUM:11; + unsigned long DATANUM:16; + } BIT; + } GR1FLM5; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long FORMAT:3; + unsigned long :28; + } BIT; + } GR1FLM6; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long ARCON:1; + unsigned long :3; + unsigned long ARCDISPON:1; + unsigned long :3; + unsigned long GRCDISPON:1; + unsigned long :2; + unsigned long DISPSEL:2; + } BIT; + } GR1AB1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCVS:11; + unsigned long :5; + unsigned long GRCVW:11; + } BIT; + } GR1AB2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCHS:11; + unsigned long :5; + unsigned long GRCHW:11; + } BIT; + } GR1AB3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCVS:11; + unsigned long :5; + unsigned long ARCVW:11; + } BIT; + } GR1AB4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCHS:11; + unsigned long :5; + unsigned long ARCHW:11; + } BIT; + } GR1AB5; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long ARCCOEF:9; + unsigned long :8; + unsigned long ARCRATE:8; + } BIT; + } GR1AB6; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ARCDEF:8; + unsigned long :15; + unsigned long CKON:1; + } BIT; + } GR1AB7; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long CKKG:8; + unsigned long CKKB:8; + unsigned long CKKR:8; + } BIT; + } GR1AB8; + union { + unsigned long LONG; + struct { + unsigned long CKA:8; + unsigned long CKG:8; + unsigned long CKB:8; + unsigned long CKR:8; + } BIT; + } GR1AB9; + char wk3[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long G:8; + unsigned long B:8; + unsigned long R:8; + } BIT; + } GR1BASE; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SEL:1; + unsigned long :5; + unsigned long LINE:11; + } BIT; + } GR1CLUTINT; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long UFST:1; + unsigned long :15; + unsigned long ARCST:1; + } BIT; + } GR1MON; + char wk4[168]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GR2VEN; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RENB:1; + } BIT; + } GR2FLMRD; + char wk5[4]; + unsigned long GR2FLM2; + union { + unsigned long LONG; + struct { + unsigned long LNOFF:16; + unsigned long :16; + } BIT; + } GR2FLM3; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long LNNUM:11; + unsigned long DATANUM:16; + } BIT; + } GR2FLM5; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long FORMAT:3; + unsigned long :28; + } BIT; + } GR2FLM6; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long ARCON:1; + unsigned long :3; + unsigned long ARCDISPON:1; + unsigned long :3; + unsigned long GRCDISPON:1; + unsigned long :2; + unsigned long DISPSEL:2; + } BIT; + } GR2AB1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCVS:11; + unsigned long :5; + unsigned long GRCVW:11; + } BIT; + } GR2AB2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GRCHS:11; + unsigned long :5; + unsigned long GRCHW:11; + } BIT; + } GR2AB3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCVS:11; + unsigned long :5; + unsigned long ARCVW:11; + } BIT; + } GR2AB4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long ARCHS:11; + unsigned long :5; + unsigned long ARCHW:11; + } BIT; + } GR2AB5; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long ARCCOEF:9; + unsigned long :8; + unsigned long ARCRATE:8; + } BIT; + } GR2AB6; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ARCDEF:8; + unsigned long :15; + unsigned long CKON:1; + } BIT; + } GR2AB7; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long CKKG:8; + unsigned long CKKB:8; + unsigned long CKKR:8; + } BIT; + } GR2AB8; + union { + unsigned long LONG; + struct { + unsigned long CKA:8; + unsigned long CKG:8; + unsigned long CKB:8; + unsigned long CKR:8; + } BIT; + } GR2AB9; + char wk7[8]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long G:8; + unsigned long B:8; + unsigned long R:8; + } BIT; + } GR2BASE; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long SEL:1; + unsigned long :5; + unsigned long LINE:11; + } BIT; + } GR2CLUTINT; + union { + unsigned long LONG; + struct { + unsigned long :15; + unsigned long UFST:1; + unsigned long :15; + unsigned long ARCST:1; + } BIT; + } GR2MON; + char wk8[168]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GAMGVEN; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long GAMON:1; + } BIT; + } GAMSW; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN00:11; + unsigned long :5; + unsigned long GAIN01:11; + } BIT; + } GAMGLUT1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN02:11; + unsigned long :5; + unsigned long GAIN03:11; + } BIT; + } GAMGLUT2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN04:11; + unsigned long :5; + unsigned long GAIN05:11; + } BIT; + } GAMGLUT3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN06:11; + unsigned long :5; + unsigned long GAIN07:11; + } BIT; + } GAMGLUT4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN08:11; + unsigned long :5; + unsigned long GAIN09:11; + } BIT; + } GAMGLUT5; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN10:11; + unsigned long :5; + unsigned long GAIN11:11; + } BIT; + } GAMGLUT6; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN12:11; + unsigned long :5; + unsigned long GAIN13:11; + } BIT; + } GAMGLUT7; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN14:11; + unsigned long :5; + unsigned long GAIN15:11; + } BIT; + } GAMGLUT8; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH01:10; + unsigned long TH02:10; + unsigned long TH03:10; + } BIT; + } GAMGAREA1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH04:10; + unsigned long TH05:10; + unsigned long TH06:10; + } BIT; + } GAMGAREA2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH07:10; + unsigned long TH08:10; + unsigned long TH09:10; + } BIT; + } GAMGAREA3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH10:10; + unsigned long TH11:10; + unsigned long TH12:10; + } BIT; + } GAMGAREA4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH13:10; + unsigned long TH14:10; + unsigned long TH15:10; + } BIT; + } GAMGAREA5; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GAMBVEN; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN00:11; + unsigned long :5; + unsigned long GAIN01:11; + } BIT; + } GAMBLUT1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN02:11; + unsigned long :5; + unsigned long GAIN03:11; + } BIT; + } GAMBLUT2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN04:11; + unsigned long :5; + unsigned long GAIN05:11; + } BIT; + } GAMBLUT3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN06:11; + unsigned long :5; + unsigned long GAIN07:11; + } BIT; + } GAMBLUT4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN08:11; + unsigned long :5; + unsigned long GAIN09:11; + } BIT; + } GAMBLUT5; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN10:11; + unsigned long :5; + unsigned long GAIN11:11; + } BIT; + } GAMBLUT6; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN12:11; + unsigned long :5; + unsigned long GAIN13:11; + } BIT; + } GAMBLUT7; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN14:11; + unsigned long :5; + unsigned long GAIN15:11; + } BIT; + } GAMBLUT8; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH01:10; + unsigned long TH02:10; + unsigned long TH03:10; + } BIT; + } GAMBAREA1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH04:10; + unsigned long TH05:10; + unsigned long TH06:10; + } BIT; + } GAMBAREA2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH07:10; + unsigned long TH08:10; + unsigned long TH09:10; + } BIT; + } GAMBAREA3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH10:10; + unsigned long TH11:10; + unsigned long TH12:10; + } BIT; + } GAMBAREA4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH13:10; + unsigned long TH14:10; + unsigned long TH15:10; + } BIT; + } GAMBAREA5; + char wk11[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } GAMRVEN; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN00:11; + unsigned long :5; + unsigned long GAIN01:11; + } BIT; + } GAMRLUT1; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN02:11; + unsigned long :5; + unsigned long GAIN03:11; + } BIT; + } GAMRLUT2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN04:11; + unsigned long :5; + unsigned long GAIN05:11; + } BIT; + } GAMRLUT3; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN06:11; + unsigned long :5; + unsigned long GAIN07:11; + } BIT; + } GAMRLUT4; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN08:11; + unsigned long :5; + unsigned long GAIN09:11; + } BIT; + } GAMRLUT5; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN10:11; + unsigned long :5; + unsigned long GAIN11:11; + } BIT; + } GAMRLUT6; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN12:11; + unsigned long :5; + unsigned long GAIN13:11; + } BIT; + } GAMRLUT7; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long GAIN14:11; + unsigned long :5; + unsigned long GAIN15:11; + } BIT; + } GAMRLUT8; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH01:10; + unsigned long TH02:10; + unsigned long TH03:10; + } BIT; + } GAMRAREA1; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH04:10; + unsigned long TH05:10; + unsigned long TH06:10; + } BIT; + } GAMRAREA2; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH07:10; + unsigned long TH08:10; + unsigned long TH09:10; + } BIT; + } GAMRAREA3; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH10:10; + unsigned long TH11:10; + unsigned long TH12:10; + } BIT; + } GAMRAREA4; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TH13:10; + unsigned long TH14:10; + unsigned long TH15:10; + } BIT; + } GAMRAREA5; + char wk13[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long VEN:1; + } BIT; + } OUTVEN; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long ENDIANON:1; + unsigned long :3; + unsigned long SWAPON:1; + unsigned long :10; + unsigned long FORMAT:2; + unsigned long :2; + unsigned long FRQSEL:1; + unsigned long :4; + unsigned long DIRSEL:1; + unsigned long :2; + unsigned long PHASE:2; + } BIT; + } OUTSET; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long BRTG:10; + } BIT; + } BRIGHT1; + union { + unsigned long LONG; + struct { + unsigned long :6; + unsigned long BRTB:10; + unsigned long :6; + unsigned long BRTR:10; + } BIT; + } BRIGHT2; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long CONTG:8; + unsigned long CONTB:8; + unsigned long CONTR:8; + } BIT; + } CONTRAST; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long SEL:2; + unsigned long :2; + unsigned long FORM:2; + unsigned long :2; + unsigned long PA:2; + unsigned long :2; + unsigned long PB:2; + unsigned long :2; + unsigned long PC:2; + unsigned long :2; + unsigned long PD:2; + } BIT; + } PANELDTHA; + char wk14[12]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long FRONTGAM:1; + unsigned long :3; + unsigned long LCDEDG:1; + unsigned long :1; + unsigned long TCON0EDG:1; + unsigned long TCON1EDG:1; + unsigned long TCON2EDG:1; + unsigned long TCON3EDG:1; + unsigned long :3; + } BIT; + } CLKPHASE; + char wk15[28]; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HALF:11; + unsigned long :5; + unsigned long OFFSET:11; + } BIT; + } TCONTIM; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long VS:11; + unsigned long :5; + unsigned long VW:11; + } BIT; + } TCONSTVA1; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTVA2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long VS:11; + unsigned long :5; + unsigned long VW:11; + } BIT; + } TCONSTVB1; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTVB2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HS:11; + unsigned long :5; + unsigned long HW:11; + } BIT; + } TCONSTHA1; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long HSSEL:1; + unsigned long :3; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTHA2; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long HS:11; + unsigned long :5; + unsigned long HW:11; + } BIT; + } TCONSTHB1; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long HSSEL:1; + unsigned long :3; + unsigned long INV:1; + unsigned long :1; + unsigned long SEL:3; + } BIT; + } TCONSTHB2; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long INV:1; + } BIT; + } TCONDE; + char wk16[20]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UFDTC:1; + unsigned long GR1UFDTC:1; + unsigned long VPOSDTC:1; + } BIT; + } DTCTEN; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UFINTEN:1; + unsigned long GR1UFINTEN:1; + unsigned long VPOSINTEN:1; + } BIT; + } INTEN; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UFCLR:1; + unsigned long GR1UFCLR:1; + unsigned long VPOSCLR:1; + } BIT; + } STCLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long GR2UF:1; + unsigned long GR1UF:1; + unsigned long VPOS:1; + } BIT; + } STMON; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long PIXSEL:1; + unsigned long :3; + unsigned long CLKSEL:1; + unsigned long :1; + unsigned long CLKEN:1; + unsigned long DCDR:6; + } BIT; + } PANELCLK; +} st_glcdc_t; + +typedef struct st_gptw { + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long PRKEY:8; + unsigned long :3; + unsigned long CMNWP:1; + unsigned long CLRWP:1; + unsigned long STPWP:1; + unsigned long STRWP:1; + unsigned long WP:1; + } BIT; + } GTWP; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CSTRT3:1; + unsigned long CSTRT2:1; + unsigned long CSTRT1:1; + unsigned long CSTRT0:1; + } BIT; + } GTSTR; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CSTOP3:1; + unsigned long CSTOP2:1; + unsigned long CSTOP1:1; + unsigned long CSTOP0:1; + } BIT; + } GTSTP; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long CCLR3:1; + unsigned long CCLR2:1; + unsigned long CCLR1:1; + unsigned long CCLR0:1; + } BIT; + } GTCLR; + union { + unsigned long LONG; + struct { + unsigned long CSTRT:1; + unsigned long :7; + unsigned long SSELCH:1; + unsigned long SSELCG:1; + unsigned long SSELCF:1; + unsigned long SSELCE:1; + unsigned long SSELCD:1; + unsigned long SSELCC:1; + unsigned long SSELCB:1; + unsigned long SSELCA:1; + unsigned long SSCBFAH:1; + unsigned long SSCBFAL:1; + unsigned long SSCBRAH:1; + unsigned long SSCBRAL:1; + unsigned long SSCAFBH:1; + unsigned long SSCAFBL:1; + unsigned long SSCARBH:1; + unsigned long SSCARBL:1; + unsigned long SSGTRGDF:1; + unsigned long SSGTRGDR:1; + unsigned long SSGTRGCF:1; + unsigned long SSGTRGCR:1; + unsigned long SSGTRGBF:1; + unsigned long SSGTRGBR:1; + unsigned long SSGTRGAF:1; + unsigned long SSGTRGAR:1; + } BIT; + } GTSSR; + union { + unsigned long LONG; + struct { + unsigned long CSTOP:1; + unsigned long :7; + unsigned long PSELCH:1; + unsigned long PSELCG:1; + unsigned long PSELCF:1; + unsigned long PSELCE:1; + unsigned long PSELCD:1; + unsigned long PSELCC:1; + unsigned long PSELCB:1; + unsigned long PSELCA:1; + unsigned long PSCBFAH:1; + unsigned long PSCBFAL:1; + unsigned long PSCBRAH:1; + unsigned long PSCBRAL:1; + unsigned long PSCAFBH:1; + unsigned long PSCAFBL:1; + unsigned long PSCARBH:1; + unsigned long PSCARBL:1; + unsigned long PSGTRGDF:1; + unsigned long PSGTRGDR:1; + unsigned long PSGTRGCF:1; + unsigned long PSGTRGCR:1; + unsigned long PSGTRGBF:1; + unsigned long PSGTRGBR:1; + unsigned long PSGTRGAF:1; + unsigned long PSGTRGAR:1; + } BIT; + } GTPSR; + union { + unsigned long LONG; + struct { + unsigned long CCLR:1; + unsigned long :7; + unsigned long CSELCH:1; + unsigned long CSELCG:1; + unsigned long CSELCF:1; + unsigned long CSELCE:1; + unsigned long CSELCD:1; + unsigned long CSELCC:1; + unsigned long CSELCB:1; + unsigned long CSELCA:1; + unsigned long CSCBFAH:1; + unsigned long CSCBFAL:1; + unsigned long CSCBRAH:1; + unsigned long CSCBRAL:1; + unsigned long CSCAFBH:1; + unsigned long CSCAFBL:1; + unsigned long CSCARBH:1; + unsigned long CSCARBL:1; + unsigned long CSGTRGDF:1; + unsigned long CSGTRGDR:1; + unsigned long CSGTRGCF:1; + unsigned long CSGTRGCR:1; + unsigned long CSGTRGBF:1; + unsigned long CSGTRGBR:1; + unsigned long CSGTRGAF:1; + unsigned long CSGTRGAR:1; + } BIT; + } GTCSR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long USELCH:1; + unsigned long USELCG:1; + unsigned long USELCF:1; + unsigned long USELCE:1; + unsigned long USELCD:1; + unsigned long USELCC:1; + unsigned long USELCB:1; + unsigned long USELCA:1; + unsigned long USCBFAH:1; + unsigned long USCBFAL:1; + unsigned long USCBRAH:1; + unsigned long USCBRAL:1; + unsigned long USCAFBH:1; + unsigned long USCAFBL:1; + unsigned long USCARBH:1; + unsigned long USCARBL:1; + unsigned long USGTRGDF:1; + unsigned long USGTRGDR:1; + unsigned long USGTRGCF:1; + unsigned long USGTRGCR:1; + unsigned long USGTRGBF:1; + unsigned long USGTRGBR:1; + unsigned long USGTRGAF:1; + unsigned long USGTRGAR:1; + } BIT; + } GTUPSR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DSELCH:1; + unsigned long DSELCG:1; + unsigned long DSELCF:1; + unsigned long DSELCE:1; + unsigned long DSELCD:1; + unsigned long DSELCC:1; + unsigned long DSELCB:1; + unsigned long DSELCA:1; + unsigned long DSCBFAH:1; + unsigned long DSCBFAL:1; + unsigned long DSCBRAH:1; + unsigned long DSCBRAL:1; + unsigned long DSCAFBH:1; + unsigned long DSCAFBL:1; + unsigned long DSCARBH:1; + unsigned long DSCARBL:1; + unsigned long DSGTRGDF:1; + unsigned long DSGTRGDR:1; + unsigned long DSGTRGCF:1; + unsigned long DSGTRGCR:1; + unsigned long DSGTRGBF:1; + unsigned long DSGTRGBR:1; + unsigned long DSGTRGAF:1; + unsigned long DSGTRGAR:1; + } BIT; + } GTDNSR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long ASELCH:1; + unsigned long ASELCG:1; + unsigned long ASELCF:1; + unsigned long ASELCE:1; + unsigned long ASELCD:1; + unsigned long ASELCC:1; + unsigned long ASELCB:1; + unsigned long ASELCA:1; + unsigned long ASCBFAH:1; + unsigned long ASCBFAL:1; + unsigned long ASCBRAH:1; + unsigned long ASCBRAL:1; + unsigned long ASCAFBH:1; + unsigned long ASCAFBL:1; + unsigned long ASCARBH:1; + unsigned long ASCARBL:1; + unsigned long ASGTRGDF:1; + unsigned long ASGTRGDR:1; + unsigned long ASGTRGCF:1; + unsigned long ASGTRGCR:1; + unsigned long ASGTRGBF:1; + unsigned long ASGTRGBR:1; + unsigned long ASGTRGAF:1; + unsigned long ASGTRGAR:1; + } BIT; + } GTICASR; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long BSELCH:1; + unsigned long BSELCG:1; + unsigned long BSELCF:1; + unsigned long BSELCE:1; + unsigned long BSELCD:1; + unsigned long BSELCC:1; + unsigned long BSELCB:1; + unsigned long BSELCA:1; + unsigned long BSCBFAH:1; + unsigned long BSCBFAL:1; + unsigned long BSCBRAH:1; + unsigned long BSCBRAL:1; + unsigned long BSCAFBH:1; + unsigned long BSCAFBL:1; + unsigned long BSCARBH:1; + unsigned long BSCARBL:1; + unsigned long BSGTRGDF:1; + unsigned long BSGTRGDR:1; + unsigned long BSGTRGCF:1; + unsigned long BSGTRGCR:1; + unsigned long BSGTRGBF:1; + unsigned long BSGTRGBR:1; + unsigned long BSGTRGAF:1; + unsigned long BSGTRGAR:1; + } BIT; + } GTICBSR; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long TPCS:4; + unsigned long :4; + unsigned long MD:3; + unsigned long :7; + unsigned long ICDS:1; + unsigned long :7; + unsigned long CST:1; + } BIT; + } GTCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long OBDTYR:1; + unsigned long OBDTYF:1; + unsigned long OBDTY:2; + unsigned long :4; + unsigned long OADTYR:1; + unsigned long OADTYF:1; + unsigned long OADTY:2; + unsigned long :14; + unsigned long UDF:1; + unsigned long UD:1; + } BIT; + } GTUDDTYC; + union { + unsigned long LONG; + struct { + unsigned long NFCSB:2; + unsigned long NFBEN:1; + unsigned long :2; + unsigned long OBDF:2; + unsigned long OBE:1; + unsigned long OBHLD:1; + unsigned long OBDFLT:1; + unsigned long :1; + unsigned long GTIOB:5; + unsigned long NFCSA:2; + unsigned long NFAEN:1; + unsigned long :2; + unsigned long OADF:2; + unsigned long OAE:1; + unsigned long OAHLD:1; + unsigned long OADFLT:1; + unsigned long :1; + unsigned long GTIOA:5; + } BIT; + } GTIOR; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long GRPABL:1; + unsigned long GRPABH:1; + unsigned long GRPDTE:1; + unsigned long :2; + unsigned long GRP:2; + unsigned long :4; + unsigned long ADTRBDEN:1; + unsigned long ADTRBUEN:1; + unsigned long ADTRADEN:1; + unsigned long ADTRAUEN:1; + unsigned long :8; + unsigned long GTINTPR:2; + unsigned long GTINTF:1; + unsigned long GTINTE:1; + unsigned long GTINTD:1; + unsigned long GTINTC:1; + unsigned long GTINTB:1; + unsigned long GTINTA:1; + } BIT; + } GTINTAD; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long OABLF:1; + unsigned long OABHF:1; + unsigned long DTEF:1; + unsigned long :3; + unsigned long ODF:1; + unsigned long :4; + unsigned long ADTRBDF:1; + unsigned long ADTRBUF:1; + unsigned long ADTRADF:1; + unsigned long ADTRAUF:1; + unsigned long TUCF:1; + unsigned long :4; + unsigned long ITCNT:3; + unsigned long :8; + } BIT; + } GTST; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long ADTDB:1; + unsigned long ADTTB:2; + unsigned long :1; + unsigned long ADTDA:1; + unsigned long ADTTA:2; + unsigned long :1; + unsigned long CCRSWT:1; + unsigned long PR:2; + unsigned long CCRB:2; + unsigned long CCRA:2; + unsigned long :5; + unsigned long DBRTECB:1; + unsigned long :1; + unsigned long DBRTECA:1; + unsigned long :4; + unsigned long BD:4; + } BIT; + } GTBER; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long ADTBL:1; + unsigned long :1; + unsigned long ADTAL:1; + unsigned long :1; + unsigned long IVTT:3; + unsigned long IVTC:2; + unsigned long ITLF:1; + unsigned long ITLE:1; + unsigned long ITLD:1; + unsigned long ITLC:1; + unsigned long ITLB:1; + unsigned long ITLA:1; + } BIT; + } GTITC; + unsigned long GTCNT; + unsigned long GTCCRA; + unsigned long GTCCRB; + unsigned long GTCCRC; + unsigned long GTCCRE; + unsigned long GTCCRD; + unsigned long GTCCRF; + unsigned long GTPR; + unsigned long GTPBR; + unsigned long GTPDBR; + unsigned long GTADTRA; + unsigned long GTADTBRA; + unsigned long GTADTDBRA; + unsigned long GTADTRB; + unsigned long GTADTBRB; + unsigned long GTADTDBRB; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long TDFER:1; + unsigned long :2; + unsigned long TDBDE:1; + unsigned long TDBUE:1; + unsigned long :3; + unsigned long TDE:1; + } BIT; + } GTDTCR; + unsigned long GTDVU; + unsigned long GTDVD; + unsigned long GTDBU; + unsigned long GTDBD; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long SOS:2; + } BIT; + } GTSOS; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SOTR:1; + } BIT; + } GTSOTR; + union { + unsigned long LONG; + struct { + unsigned long :7; + unsigned long ADSMEN1:1; + unsigned long :6; + unsigned long ADSMS1:2; + unsigned long :7; + unsigned long ADSMEN0:1; + unsigned long :6; + unsigned long ADSMS0:2; + } BIT; + } GTADSMR; + union { + unsigned long LONG; + struct { + unsigned long EITCNT2:4; + unsigned long EITCNT2IV:4; + unsigned long EIVTT2:4; + unsigned long :2; + unsigned long EIVTC2:2; + unsigned long EITCNT1:4; + unsigned long :4; + unsigned long EIVTT1:4; + unsigned long :2; + unsigned long EIVTC1:2; + } BIT; + } GTEITC; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long EITLU:3; + unsigned long :1; + unsigned long EITLV:3; + unsigned long :1; + unsigned long EITLF:3; + unsigned long :1; + unsigned long EITLE:3; + unsigned long :1; + unsigned long EITLD:3; + unsigned long :1; + unsigned long EITLC:3; + unsigned long :1; + unsigned long EITLB:3; + unsigned long :1; + unsigned long EITLA:3; + } BIT; + } GTEITLI1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long EADTBL:3; + unsigned long :1; + unsigned long EADTAL:3; + } BIT; + } GTEITLI2; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long EBTLDVD:3; + unsigned long :1; + unsigned long EBTLDVU:3; + unsigned long :1; + unsigned long EBTLADB:3; + unsigned long :1; + unsigned long EBTLADA:3; + unsigned long :5; + unsigned long EBTLPR:3; + unsigned long :1; + unsigned long EBTLCB:3; + unsigned long :1; + unsigned long EBTLCA:3; + } BIT; + } GTEITLB; + char wk0[24]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long SECSEL3:1; + unsigned long SECSEL2:1; + unsigned long SECSEL1:1; + unsigned long SECSEL0:1; + } BIT; + } GTSECSR; + union { + unsigned long LONG; + struct { + unsigned long :20; + unsigned long SBDDD:1; + unsigned long SBDAD:1; + unsigned long SBDPD:1; + unsigned long SBDCD:1; + unsigned long :4; + unsigned long SBDDE:1; + unsigned long SBDAE:1; + unsigned long SBDPE:1; + unsigned long SBDCE:1; + } BIT; + } GTSECR; +} st_gptw_t; + +typedef struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT2:1; + } BIT; + } SWINT2R; + char wk1[14]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + unsigned char :2; + } BIT; + } IRQCR[16]; + char wk11[16]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN15:1; + unsigned char FLTEN14:1; + unsigned char FLTEN13:1; + unsigned char FLTEN12:1; + unsigned char FLTEN11:1; + unsigned char FLTEN10:1; + unsigned char FLTEN9:1; + unsigned char FLTEN8:1; + } BIT; + } IRQFLTE1; + char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL15:2; + unsigned short FCLKSEL14:2; + unsigned short FCLKSEL13:2; + unsigned short FCLKSEL12:2; + unsigned short FCLKSEL11:2; + unsigned short FCLKSEL10:2; + unsigned short FCLKSEL9:2; + unsigned short FCLKSEL8:2; + } BIT; + } IRQFLTC1; + char wk13[84]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char EXNMIST:1; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char WDTST:1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char EXNMIEN:1; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char WDTEN:1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char WDTCLR:1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + unsigned char :3; + } BIT; + } NMICR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DPFPUST:1; + unsigned char RAMST:1; + } BIT; + } EXNMISR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DPFPUEN:1; + unsigned char RAMEN:1; + } BIT; + } EXNMIER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char DPFPUCLR:1; + unsigned char :1; + } BIT; + } EXNMICLR; + char wk14[9]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk15[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; + char wk16[27]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPIE0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENIE0; + union { + unsigned long LONG; + struct { + unsigned long CLR31:1; + unsigned long CLR30:1; + unsigned long CLR29:1; + unsigned long CLR28:1; + unsigned long CLR27:1; + unsigned long CLR26:1; + unsigned long CLR25:1; + unsigned long CLR24:1; + unsigned long CLR23:1; + unsigned long CLR22:1; + unsigned long CLR21:1; + unsigned long CLR20:1; + unsigned long CLR19:1; + unsigned long CLR18:1; + unsigned long CLR17:1; + unsigned long CLR16:1; + unsigned long CLR15:1; + unsigned long CLR14:1; + unsigned long CLR13:1; + unsigned long CLR12:1; + unsigned long CLR11:1; + unsigned long CLR10:1; + unsigned long CLR9:1; + unsigned long CLR8:1; + unsigned long CLR7:1; + unsigned long CLR6:1; + unsigned long CLR5:1; + unsigned long CLR4:1; + unsigned long CLR3:1; + unsigned long CLR2:1; + unsigned long CLR1:1; + unsigned long CLR0:1; + } BIT; + } GCRIE0; + char wk17[68]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBE0; + char wk18[44]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL0; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL1; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPBL2; + char wk19[4]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBE0; + char wk20[44]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL1; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENBL2; + char wk21[4]; + union { + unsigned long LONG; + struct { + unsigned long CLR31:1; + unsigned long CLR30:1; + unsigned long CLR29:1; + unsigned long CLR28:1; + unsigned long CLR27:1; + unsigned long CLR26:1; + unsigned long CLR25:1; + unsigned long CLR24:1; + unsigned long CLR23:1; + unsigned long CLR22:1; + unsigned long CLR21:1; + unsigned long CLR20:1; + unsigned long CLR19:1; + unsigned long CLR18:1; + unsigned long CLR17:1; + unsigned long CLR16:1; + unsigned long CLR15:1; + unsigned long CLR14:1; + unsigned long CLR13:1; + unsigned long CLR12:1; + unsigned long CLR11:1; + unsigned long CLR10:1; + unsigned long CLR9:1; + unsigned long CLR8:1; + unsigned long CLR7:1; + unsigned long CLR6:1; + unsigned long CLR5:1; + unsigned long CLR4:1; + unsigned long CLR3:1; + unsigned long CLR2:1; + unsigned long CLR1:1; + unsigned long CLR0:1; + } BIT; + } GCRBE0; + char wk22[124]; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR0; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR1; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR2; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR3; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR4; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR5; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR6; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR7; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR8; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBR9; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBRA; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIBRB; + char wk23[116]; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR128; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR129; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR130; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR131; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR132; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR133; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR134; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR135; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR136; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR137; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR138; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR139; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR140; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR141; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR142; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBXR143; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR144; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR145; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR146; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR147; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR148; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR149; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR150; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR151; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR152; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR153; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR154; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR155; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR156; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR157; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR158; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR159; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR160; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR161; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR162; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR163; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR164; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR165; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR166; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR167; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR168; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR169; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR170; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR171; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR172; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR173; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR174; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR175; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR176; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR177; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR178; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR179; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR180; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR181; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR182; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR183; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR184; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR185; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR186; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR187; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR188; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR189; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR190; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR191; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR192; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR193; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR194; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR195; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR196; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR197; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR198; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR199; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR200; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR201; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR202; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR203; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR204; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR205; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR206; + union { + unsigned char BYTE; + struct { + unsigned char SLI:8; + } BIT; + } SLIBR207; + char wk24[96]; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPAL0; + union { + unsigned long LONG; + struct { + unsigned long IS31:1; + unsigned long IS30:1; + unsigned long IS29:1; + unsigned long IS28:1; + unsigned long IS27:1; + unsigned long IS26:1; + unsigned long IS25:1; + unsigned long IS24:1; + unsigned long IS23:1; + unsigned long IS22:1; + unsigned long IS21:1; + unsigned long IS20:1; + unsigned long IS19:1; + unsigned long IS18:1; + unsigned long IS17:1; + unsigned long IS16:1; + unsigned long IS15:1; + unsigned long IS14:1; + unsigned long IS13:1; + unsigned long IS12:1; + unsigned long IS11:1; + unsigned long IS10:1; + unsigned long IS9:1; + unsigned long IS8:1; + unsigned long IS7:1; + unsigned long IS6:1; + unsigned long IS5:1; + unsigned long IS4:1; + unsigned long IS3:1; + unsigned long IS2:1; + unsigned long IS1:1; + unsigned long IS0:1; + } BIT; + } GRPAL1; + char wk25[56]; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENAL0; + union { + unsigned long LONG; + struct { + unsigned long EN31:1; + unsigned long EN30:1; + unsigned long EN29:1; + unsigned long EN28:1; + unsigned long EN27:1; + unsigned long EN26:1; + unsigned long EN25:1; + unsigned long EN24:1; + unsigned long EN23:1; + unsigned long EN22:1; + unsigned long EN21:1; + unsigned long EN20:1; + unsigned long EN19:1; + unsigned long EN18:1; + unsigned long EN17:1; + unsigned long EN16:1; + unsigned long EN15:1; + unsigned long EN14:1; + unsigned long EN13:1; + unsigned long EN12:1; + unsigned long EN11:1; + unsigned long EN10:1; + unsigned long EN9:1; + unsigned long EN8:1; + unsigned long EN7:1; + unsigned long EN6:1; + unsigned long EN5:1; + unsigned long EN4:1; + unsigned long EN3:1; + unsigned long EN2:1; + unsigned long EN1:1; + unsigned long EN0:1; + } BIT; + } GENAL1; + char wk26[136]; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR0; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR1; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR2; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR3; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR4; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR5; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR6; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR7; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR8; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIAR9; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIARA; + char wk27[1]; + union { + unsigned char BYTE; + struct { + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; + } BIT; + } PIARC; + char wk28[195]; + union { + unsigned char BYTE; + } SLIAR208; + union { + unsigned char BYTE; + } SLIAR209; + union { + unsigned char BYTE; + } SLIAR210; + union { + unsigned char BYTE; + } SLIAR211; + union { + unsigned char BYTE; + } SLIAR212; + union { + unsigned char BYTE; + } SLIAR213; + union { + unsigned char BYTE; + } SLIAR214; + union { + unsigned char BYTE; + } SLIAR215; + union { + unsigned char BYTE; + } SLIAR216; + union { + unsigned char BYTE; + } SLIAR217; + union { + unsigned char BYTE; + } SLIAR218; + union { + unsigned char BYTE; + } SLIAR219; + union { + unsigned char BYTE; + } SLIAR220; + union { + unsigned char BYTE; + } SLIAR221; + union { + unsigned char BYTE; + } SLIAR222; + union { + unsigned char BYTE; + } SLIAR223; + union { + unsigned char BYTE; + } SLIAR224; + union { + unsigned char BYTE; + } SLIAR225; + union { + unsigned char BYTE; + } SLIAR226; + union { + unsigned char BYTE; + } SLIAR227; + union { + unsigned char BYTE; + } SLIAR228; + union { + unsigned char BYTE; + } SLIAR229; + union { + unsigned char BYTE; + } SLIAR230; + union { + unsigned char BYTE; + } SLIAR231; + union { + unsigned char BYTE; + } SLIAR232; + union { + unsigned char BYTE; + } SLIAR233; + union { + unsigned char BYTE; + } SLIAR234; + union { + unsigned char BYTE; + } SLIAR235; + union { + unsigned char BYTE; + } SLIAR236; + union { + unsigned char BYTE; + } SLIAR237; + union { + unsigned char BYTE; + } SLIAR238; + union { + unsigned char BYTE; + } SLIAR239; + union { + unsigned char BYTE; + } SLIAR240; + union { + unsigned char BYTE; + } SLIAR241; + union { + unsigned char BYTE; + } SLIAR242; + union { + unsigned char BYTE; + } SLIAR243; + union { + unsigned char BYTE; + } SLIAR244; + union { + unsigned char BYTE; + } SLIAR245; + union { + unsigned char BYTE; + } SLIAR246; + union { + unsigned char BYTE; + } SLIAR247; + union { + unsigned char BYTE; + } SLIAR248; + union { + unsigned char BYTE; + } SLIAR249; + union { + unsigned char BYTE; + } SLIAR250; + union { + unsigned char BYTE; + } SLIAR251; + union { + unsigned char BYTE; + } SLIAR252; + union { + unsigned char BYTE; + } SLIAR253; + union { + unsigned char BYTE; + } SLIAR254; + union { + unsigned char BYTE; + } SLIAR255; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char WPRC:1; + } BIT; + } SLIPRCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SELEXD1:1; + unsigned char SELEXD0:1; + } BIT; + } SELEXDR; +} st_icu_t; + +typedef struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + unsigned char :7; + } BIT; + } IWDTCSTPR; +} st_iwdt_t; + +typedef struct st_mmcif { + union { + unsigned long LONG; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned long :1; + unsigned long BOOT:1; + unsigned long CMD:6; + unsigned long RTYP:2; + unsigned long RBSY:1; + unsigned long :1; + unsigned long WDAT:1; + unsigned long DWEN:1; + unsigned long CMLTE:1; + unsigned long CMD12EN:1; + unsigned long RIDXC:2; + unsigned long RCRC7C:2; + unsigned long :1; + unsigned long CRC16C:1; + unsigned long BOOTACK:1; + unsigned long CRCSTE:1; + unsigned long TBIT:1; + unsigned long OPDM:1; + unsigned long :2; + unsigned long SBIT:1; + unsigned long :1; + unsigned long DATW:2; + } BIT; +#endif + } CECMDSET; + char wk0[4]; + union { + unsigned long LONG; + } CEARG; + union { + unsigned long LONG; + struct { + unsigned long C12ARG:32; + } BIT; + } CEARGCMD12; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long BREAK:1; + } BIT; + } CECMDCTRL; + union { + unsigned long LONG; + struct { + unsigned long BLKCNT:16; + unsigned long BLKSIZ:16; + } BIT; + } CEBLOCKSET; + union { + unsigned long LONG; + struct { + unsigned long MMCBUSBSY:1; + unsigned long :6; + unsigned long CLKEN:1; + unsigned long :4; + unsigned long CLKDIV:4; + unsigned long :2; + unsigned long SRSPTO:2; + unsigned long SRBSYTO:4; + unsigned long SRWDTO:4; + unsigned long :4; + } BIT; + } CECLKCTRL; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long DMATYP:1; + unsigned long DMAWEN:1; + unsigned long DMAREN:1; + unsigned long :7; + unsigned long ATYP:1; + unsigned long :16; + } BIT; + } CEBUFACC; + unsigned long CERESP3; + unsigned long CERESP2; + unsigned long CERESP1; + unsigned long CERESP0; + union { + unsigned long LONG; + struct { + unsigned long RSP12:32; + } BIT; + } CERESPCMD12; + unsigned long CEDATA; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long SBTCLKDIV:4; + unsigned long SBTACKTO:4; + unsigned long SFSTBTDATTO:4; + unsigned long SBTDATTO:4; + unsigned long :16; + } BIT; + } CEBOOT; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long CMD12DRE:1; + unsigned long CMD12RBE:1; + unsigned long CMD12CRE:1; + unsigned long DTRANE:1; + unsigned long BUFRE:1; + unsigned long BUFWEN:1; + unsigned long BUFREN:1; + unsigned long :2; + unsigned long RBSYE:1; + unsigned long CRSPE:1; + unsigned long CMDVIO:1; + unsigned long BUFVIO:1; + unsigned long :2; + unsigned long WDATERR:1; + unsigned long RDATERR:1; + unsigned long RIDXERR:1; + unsigned long RSPERR:1; + unsigned long :3; + unsigned long CRCSTO:1; + unsigned long WDATTO:1; + unsigned long RDATTO:1; + unsigned long RBSYTO:1; + unsigned long RSPTO:1; + } BIT; + } CEINT; + union { + unsigned long LONG; + struct { + unsigned long :5; + unsigned long MCMD12DRE:1; + unsigned long MCMD12RBE:1; + unsigned long MCMD12CRE:1; + unsigned long MDTRANE:1; + unsigned long MBUFRE:1; + unsigned long MBUFWEN:1; + unsigned long MBUFREN:1; + unsigned long :2; + unsigned long MRBSYE:1; + unsigned long MCRSPE:1; + unsigned long MCMDVIO:1; + unsigned long MBUFVIO:1; + unsigned long :2; + unsigned long MWDATERR:1; + unsigned long MRDATERR:1; + unsigned long MRIDXERR:1; + unsigned long MRSPERR:1; + unsigned long :3; + unsigned long MCRCSTO:1; + unsigned long MWDATTO:1; + unsigned long MRDATTO:1; + unsigned long MRBSYTO:1; + unsigned long MRSPTO:1; + } BIT; + } CEINTEN; + union { + unsigned long LONG; + struct { + unsigned long CMDSEQ:1; + unsigned long CMDSIG:1; + unsigned long RSPIDX:6; + unsigned long DATSIG:8; + unsigned long RCVBLK:16; + } BIT; + } CEHOSTSTS1; + union { + unsigned long LONG; + struct { + unsigned long CRCSTE:1; + unsigned long CRC16E:1; + unsigned long AC12CRCE:1; + unsigned long RSPCRC7E:1; + unsigned long CRCSTEBE:1; + unsigned long RDATEBE:1; + unsigned long AC12REBE:1; + unsigned long RSPEBE:1; + unsigned long AC12IDXE:1; + unsigned long RSPIDXE:1; + unsigned long BTACKPATE:1; + unsigned long BTACKEBE:1; + unsigned long :1; + unsigned long CRCST:3; + unsigned long :1; + unsigned long STRDATTO:1; + unsigned long DATBSYTO:1; + unsigned long CRCSTTO:1; + unsigned long AC12BSYTO:1; + unsigned long RSPBSYTO:1; + unsigned long AC12RSPTO:1; + unsigned long STRSPTO:1; + unsigned long BTACKTO:1; + unsigned long FSTBTDATTO:1; + unsigned long BTDATTO:1; + unsigned long :5; + } BIT; + } CEHOSTSTS2; + char wk2[32]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CDSIG:1; + unsigned long CDRISE:1; + unsigned long CDFALL:1; + unsigned long :6; + unsigned long MCDRISE:1; + unsigned long MCDFALL:1; + unsigned long :4; + } BIT; + } CEDETECT; + union { + unsigned long LONG; + struct { + unsigned long :10; + unsigned long RESNOUT:1; + unsigned long :1; + unsigned long CLKMAIN:1; + unsigned long :19; + } BIT; + } CEADDMODE; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long SWRST:1; + unsigned long :15; + unsigned long VERSION:16; + } BIT; + } CEVERSION; +} st_mmcif_t; + +typedef struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PFCSE; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CS3S:2; + unsigned char CS2S:2; + unsigned char CS1S:2; + unsigned char :1; + unsigned char CS0S:1; + } BIT; + } PFCSS0; + union { + unsigned char BYTE; + struct { + unsigned char CS7S:2; + unsigned char CS6S:2; + unsigned char CS5S:2; + unsigned char CS4S:2; + } BIT; + } PFCSS1; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char A9E:1; + unsigned char A8E:1; + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + unsigned char WR32BC32E:1; + unsigned char WR1BC1E:1; + unsigned char DH32E:1; + unsigned char DHE:1; + unsigned char BCLKO:1; + unsigned char ADRHMS2:1; + unsigned char ADRHMS:1; + unsigned char ADRLE:1; + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + unsigned char SDCLKE:1; + unsigned char DQM1E:1; + unsigned char :1; + unsigned char MDSDE:1; + unsigned char ALES:1; + unsigned char ALEOE:1; + unsigned char WAITS:2; + } BIT; + } PFBCR1; + union { + unsigned char BYTE; + struct { + unsigned char D3S:2; + unsigned char D2S:2; + unsigned char D1S:2; + unsigned char D0S:2; + } BIT; + } PFBCR2; + union { + unsigned char BYTE; + struct { + unsigned char WAITS2:1; + unsigned char SDCLKDRV:1; + unsigned char :5; + unsigned char DLHS:1; + } BIT; + } PFBCR3; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PHYMODE1:1; + unsigned char PHYMODE0:1; + unsigned char :4; + } BIT; + } PFENET; + char wk2[16]; + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + unsigned char :6; + } BIT; + } PWPR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P01PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P02PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P03PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P05PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P07PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P11PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P52PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P56PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P57PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P60PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P61PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P62PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P63PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P64PFS; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P66PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } P67PFS; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P71PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P72PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P76PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P77PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P82PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P83PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P84PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P85PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P86PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P87PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } P93PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P94PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P95PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P96PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } P97PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :1; + unsigned char PSEL:6; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char PSEL:6; + } BIT; + } PE7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PF2PFS; + char wk10[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :6; + } BIT; + } PF5PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PG7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PH7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ3PFS; + char wk12[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PJ5PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PK7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PL7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PM7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PN5PFS; + char wk14[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL:6; + } BIT; + } PQ7PFS; +} st_mpc_t; + +typedef struct st_mpu { + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long MPEN:1; + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long UBAC:3; + unsigned long :1; + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long CLR:1; + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long DRW:1; + unsigned long DMPER:1; + unsigned long IMPER:1; + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long DEA:32; + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long SA:32; + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short S:1; + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short INV:1; + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITI:8; + unsigned long :12; + unsigned long UHACI:3; + unsigned long :1; + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITD:8; + unsigned long :12; + unsigned long UHACD:3; + unsigned long :1; + } BIT; + } MHITD; +} st_mpu_t; + +typedef struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOERA; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCRA; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1A; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR1A; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT1A; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTERA; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDERA; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBRA; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TITM:1; + } BIT; + } TITMRA; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG4COR:3; + } BIT; + } TITCR2A; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG4CNT:3; + } BIT; + } TITCNT2A; + char wk7[35]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :5; + unsigned char SCC:1; + unsigned char WRE:1; + } BIT; + } TWCRA; + char wk8[15]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DRS:1; + } BIT; + } TMDR2A; + char wk9[15]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :2; + unsigned char CST8:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTRA; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYRA; + union { + unsigned char BYTE; + struct { + unsigned char SCH0:1; + unsigned char SCH1:1; + unsigned char SCH2:1; + unsigned char SCH3:1; + unsigned char SCH4:1; + unsigned char :1; + unsigned char SCH6:1; + unsigned char SCH7:1; + } BIT; + } TCSYSTR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWERA; + char wk11[1925]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE7D:1; + unsigned char OE7C:1; + unsigned char OE6D:1; + unsigned char OE7B:1; + unsigned char OE7A:1; + unsigned char OE6B:1; + } BIT; + } TOERB; + char wk12[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1B; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union { + unsigned char BYTE; + struct { + unsigned char T6AEN:1; + unsigned char T6ACOR:3; + unsigned char T7VEN:1; + unsigned char T7VCOR:3; + } BIT; + } TITCR1B; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T6ACNT:3; + unsigned char :1; + unsigned char T7VCNT:3; + } BIT; + } TITCNT1B; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTERB; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDERB; + char wk17[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBRB; + char wk18[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TITM:1; + } BIT; + } TITMRB; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG7COR:3; + } BIT; + } TITCR2B; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TRG7CNT:3; + } BIT; + } TITCNT2B; + char wk19[35]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :5; + unsigned char SCC:1; + unsigned char WRE:1; + } BIT; + } TWCRB; + char wk20[15]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DRS:1; + } BIT; + } TMDR2B; + char wk21[15]; + union { + unsigned char BYTE; + struct { + unsigned char CST7:1; + unsigned char CST6:1; + unsigned char :6; + } BIT; + } TSTRB; + union { + unsigned char BYTE; + struct { + unsigned char SYNC7:1; + unsigned char SYNC6:1; + unsigned char :6; + } BIT; + } TSYRB; + char wk22[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWERB; +} st_mtu_t; + +typedef struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR0; + char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCRC; + char wk1[102]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char TTGE2:1; + unsigned char :5; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; +} st_mtu0_t; + +typedef struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR1; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PHCKSEL:1; + unsigned char LWA:1; + } BIT; + } TMDR3; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PCB:2; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +} st_mtu1_t; + +typedef struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR2; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PCB:2; + unsigned char TPSC2:3; + } BIT; + } TCR2; +} st_mtu2_t; + +typedef struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR3; +} st_mtu3_t; + +typedef struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR4; +} st_mtu4_t; + +typedef struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2U; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2V; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CKEG:2; + unsigned char TPSC2:3; + } BIT; + } TCR2W; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk4[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +} st_mtu5_t; + +typedef struct st_mtu6 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk9[3]; + union { + unsigned char BYTE; + struct { + unsigned char CE0A:1; + unsigned char CE0B:1; + unsigned char CE0C:1; + unsigned char CE0D:1; + unsigned char CE1A:1; + unsigned char CE1B:1; + unsigned char CE2A:1; + unsigned char CE2B:1; + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR6; +} st_mtu6_t; + +typedef struct st_mtu7 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT7AE:1; + unsigned short DT7AE:1; + unsigned short UT7BE:1; + unsigned short DT7BE:1; + unsigned short ITA6AE:1; + unsigned short ITA7VE:1; + unsigned short ITB6AE:1; + unsigned short ITB7VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR7; +} st_mtu7_t; + +typedef struct st_mtu8 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR8; + char wk0[871]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TPSC2:3; + } BIT; + } TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +} st_mtu8_t; + +typedef struct st_ofsm { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long BANKMD:3; + unsigned long :1; + unsigned long MDE:3; + } BIT; + } MDE; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long WDTRSTIRQS:1; + unsigned long WDTRPSS:2; + unsigned long WDTRPES:2; + unsigned long WDTCKS:4; + unsigned long WDTTOPS:2; + unsigned long WDTSTRT:1; + unsigned long :2; + unsigned long IWDTSLCSTP:1; + unsigned long :1; + unsigned long IWDTRSTIRQS:1; + unsigned long IWDTRPSS:2; + unsigned long IWDTRPES:2; + unsigned long IWDTCKS:4; + unsigned long IWDTTOPS:2; + unsigned long IWDTSTRT:1; + unsigned long :1; + } BIT; + } OFS0; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long HOCOEN:1; + unsigned long :5; + unsigned long LVDAS:1; + unsigned long VDSEL:2; + } BIT; + } OFS1; + char wk0[4]; + unsigned long TMINF; + char wk1[12]; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long BANKSWP:3; + } BIT; + } BANKSEL; + char wk2[28]; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long SPE:1; + unsigned long :27; + } BIT; + } SPCC; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TMEFDB:3; + unsigned long :1; + unsigned long TMEF:3; + unsigned long :24; + } BIT; + } TMEF; + char wk4[4]; + union { + struct { + unsigned long ID4:8; + unsigned long ID3:8; + unsigned long ID2:8; + unsigned long ID1:8; + unsigned long ID8:8; + unsigned long ID7:8; + unsigned long ID6:8; + unsigned long ID5:8; + unsigned long ID12:8; + unsigned long ID11:8; + unsigned long ID10:8; + unsigned long ID9:8; + unsigned long ID16:8; + unsigned long ID15:8; + unsigned long ID14:8; + unsigned long ID13:8; + } BIT; + } OSIS; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long BTFLG:1; + unsigned long :3; + unsigned long FAWE:12; + unsigned long FSPR:1; + unsigned long :3; + unsigned long FAWS:12; + } BIT; + } FAW; + char wk6[8]; + union { + unsigned long LONG; + struct { + unsigned long CODE:32; + } BIT; + } ROMCODE; +} st_ofsm_t; + +typedef struct st_pdc { + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long EDS:1; + unsigned long PCKDIV:3; + unsigned long PCKOE:1; + unsigned long HERIE:1; + unsigned long VERIE:1; + unsigned long UDRIE:1; + unsigned long OVIE:1; + unsigned long FEIE:1; + unsigned long DFIE:1; + unsigned long PRST:1; + unsigned long HPS:1; + unsigned long VPS:1; + unsigned long PCKE:1; + } BIT; + } PCCR0; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long PCE:1; + } BIT; + } PCCR1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long HERF:1; + unsigned long VERF:1; + unsigned long UDRF:1; + unsigned long OVRF:1; + unsigned long FEF:1; + unsigned long FEMPF:1; + unsigned long FBSY:1; + } BIT; + } PCSR; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long HSYNC:1; + unsigned long VSYNC:1; + } BIT; + } PCMONR; + union { + unsigned long LONG; + } PCDR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long VSZ:12; + unsigned long :4; + unsigned long VST:12; + } BIT; + } VCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long HSZ:12; + unsigned long :4; + unsigned long HST:12; + } BIT; + } HCR; +} st_pdc_t; + +typedef struct st_pmgi { + union { + unsigned long LONG; + struct { + unsigned long :9; + unsigned long PSMCT:3; + unsigned long :1; + unsigned long PSMHT:3; + unsigned long PSMDP:1; + unsigned long :1; + unsigned long PSMCS:6; + unsigned long :8; + } BIT; + } PMGCR; + union { + unsigned long LONG; + struct { + unsigned long PRD:16; + unsigned long :3; + unsigned long PRA:5; + unsigned long PDA:5; + unsigned long :1; + unsigned long PSMAD:1; + unsigned long PSME:1; + } BIT; + } PSMR; +} st_pmgi_t; + +typedef struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE0F:1; + unsigned short :3; + unsigned short PIE1:1; + unsigned short :6; + unsigned short POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short OSF1:1; + unsigned short :5; + unsigned short OCE1:1; + unsigned short OIE1:1; + unsigned short :8; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE4F:1; + unsigned short :3; + unsigned short PIE2:1; + unsigned short :6; + unsigned short POE4M:2; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short OSF2:1; + unsigned short :5; + unsigned short OCE2:1; + unsigned short OIE2:1; + unsigned short :8; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE8F:1; + unsigned short :2; + unsigned short POE8E:1; + unsigned short PIE3:1; + unsigned short :6; + unsigned short POE8M:2; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char MTUCH0HIZ:1; + unsigned char MTUCH67HIZ:1; + unsigned char MTUCH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MTU0DZE:1; + unsigned char MTU0CZE:1; + unsigned char MTU0BZE:1; + unsigned char MTU0AZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short MTU3BDZE:1; + unsigned short MTU4ACZE:1; + unsigned short MTU4BDZE:1; + unsigned short :5; + unsigned short MTU6BDZE:1; + unsigned short MTU7ACZE:1; + unsigned short MTU7BDZE:1; + } BIT; + } POECR2; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short IC5ADDMT67ZE:1; + unsigned short IC4ADDMT67ZE:1; + unsigned short IC3ADDMT67ZE:1; + unsigned short :1; + unsigned short IC1ADDMT67ZE:1; + unsigned short :3; + unsigned short IC5ADDMT34ZE:1; + unsigned short IC4ADDMT34ZE:1; + unsigned short IC3ADDMT34ZE:1; + unsigned short IC2ADDMT34ZE:1; + unsigned short :2; + } BIT; + } POECR4; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short IC5ADDMT0ZE:1; + unsigned short IC4ADDMT0ZE:1; + unsigned short :1; + unsigned short IC2ADDMT0ZE:1; + unsigned short IC1ADDMT0ZE:1; + unsigned short :1; + } BIT; + } POECR5; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE10F:1; + unsigned short :2; + unsigned short POE10E:1; + unsigned short PIE4:1; + unsigned short :6; + unsigned short POE10M:2; + } BIT; + } ICSR4; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short POE11F:1; + unsigned short :2; + unsigned short POE11E:1; + unsigned short PIE5:1; + unsigned short :6; + unsigned short POE11M:2; + } BIT; + } ICSR5; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OLSEN:1; + unsigned short :1; + unsigned short OLSG2B:1; + unsigned short OLSG2A:1; + unsigned short OLSG1B:1; + unsigned short OLSG1A:1; + unsigned short OLSG0B:1; + unsigned short OLSG0A:1; + } BIT; + } ALR1; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short OSTSTF:1; + unsigned short :2; + unsigned short OSTSTE:1; + unsigned short :9; + } BIT; + } ICSR6; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char M0BSEL:4; + unsigned char M0ASEL:4; + } BIT; + } M0SELR1; + union { + unsigned char BYTE; + struct { + unsigned char M0DSEL:4; + unsigned char M0CSEL:4; + } BIT; + } M0SELR2; + union { + unsigned char BYTE; + struct { + unsigned char M3DSEL:4; + unsigned char M3BSEL:4; + } BIT; + } M3SELR; + union { + unsigned char BYTE; + struct { + unsigned char M4CSEL:4; + unsigned char M4ASEL:4; + } BIT; + } M4SELR1; + union { + unsigned char BYTE; + struct { + unsigned char M4DSEL:4; + unsigned char M4BSEL:4; + } BIT; + } M4SELR2; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char M6DSEL:4; + unsigned char M6BSEL:4; + } BIT; + } M6SELR; +} st_poe_t; + +typedef struct st_poeg { + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGA; + char wk0[252]; + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGB; + char wk1[252]; + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGC; + char wk2[252]; + union { + unsigned long LONG; + struct { + unsigned long NFCS:2; + unsigned long NFEN:1; + unsigned long INV:1; + unsigned long :11; + unsigned long ST:1; + unsigned long :9; + unsigned long OSTPE:1; + unsigned long IOCE:1; + unsigned long PIDE:1; + unsigned long SSF:1; + unsigned long OSTPF:1; + unsigned long IOCF:1; + unsigned long PIDF:1; + } BIT; + } POEGGD; +} st_poeg_t; + +typedef struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :3; + unsigned char B2:1; + unsigned char :2; + } BIT; + } ODR1; + char wk4[62]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port0_t; + +typedef struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char :1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :2; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char :1; + } BIT; + } DSCR2; +} st_port1_t; + +typedef struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :7; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :3; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port2_t; + +typedef struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :3; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[103]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port3_t; + +typedef struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +} st_port4_t; + +typedef struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port5_t; + +typedef struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[103]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port6_t; + +typedef struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port7_t; + +typedef struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[54]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port8_t; + +typedef struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_port9_t; + +typedef struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_porta_t; + +typedef struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portb_t; + +typedef struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portc_t; + +typedef struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portd_t; + +typedef struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_porte_t; + +typedef struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[46]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[47]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +} st_portf_t; + +typedef struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[47]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portg_t; + +typedef struct st_porth { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[48]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[45]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_porth_t; + +typedef struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :2; + } BIT; + } ODR1; + char wk4[44]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portj_t; + +typedef struct st_portk { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[50]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[43]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portk_t; + +typedef struct st_portl { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[51]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[42]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portl_t; + +typedef struct st_portm { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[52]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[41]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portm_t; + +typedef struct st_portn { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[53]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[40]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portn_t; + +typedef struct st_portq { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[54]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[39]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR2; +} st_portq_t; + +typedef struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER15:1; + unsigned char NDER14:1; + unsigned char NDER13:1; + unsigned char NDER12:1; + unsigned char NDER11:1; + unsigned char NDER10:1; + unsigned char NDER9:1; + unsigned char NDER8:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER7:1; + unsigned char NDER6:1; + unsigned char NDER5:1; + unsigned char NDER4:1; + unsigned char NDER3:1; + unsigned char NDER2:1; + unsigned char NDER1:1; + unsigned char NDER0:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD15:1; + unsigned char POD14:1; + unsigned char POD13:1; + unsigned char POD12:1; + unsigned char POD11:1; + unsigned char POD10:1; + unsigned char POD9:1; + unsigned char POD8:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD7:1; + unsigned char POD6:1; + unsigned char POD5:1; + unsigned char POD4:1; + unsigned char POD3:1; + unsigned char POD2:1; + unsigned char POD1:1; + unsigned char POD0:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR15:1; + unsigned char NDR14:1; + unsigned char NDR13:1; + unsigned char NDR12:1; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR7:1; + unsigned char NDR6:1; + unsigned char NDR5:1; + unsigned char NDR4:1; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR11:1; + unsigned char NDR10:1; + unsigned char NDR9:1; + unsigned char NDR8:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR3:1; + unsigned char NDR2:1; + unsigned char NDR1:1; + unsigned char NDR0:1; + } BIT; + } NDRL2; +} st_ppg0_t; + +typedef struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PTRSL:1; + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G3CMS:2; + unsigned char G2CMS:2; + unsigned char G1CMS:2; + unsigned char G0CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G3INV:1; + unsigned char G2INV:1; + unsigned char G1INV:1; + unsigned char G0INV:1; + unsigned char G3NOV:1; + unsigned char G2NOV:1; + unsigned char G1NOV:1; + unsigned char G0NOV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER31:1; + unsigned char NDER30:1; + unsigned char NDER29:1; + unsigned char NDER28:1; + unsigned char NDER27:1; + unsigned char NDER26:1; + unsigned char NDER25:1; + unsigned char NDER24:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER23:1; + unsigned char NDER22:1; + unsigned char NDER21:1; + unsigned char NDER20:1; + unsigned char NDER19:1; + unsigned char NDER18:1; + unsigned char NDER17:1; + unsigned char NDER16:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD31:1; + unsigned char POD30:1; + unsigned char POD29:1; + unsigned char POD28:1; + unsigned char POD27:1; + unsigned char POD26:1; + unsigned char POD25:1; + unsigned char POD24:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD23:1; + unsigned char POD22:1; + unsigned char POD21:1; + unsigned char POD20:1; + unsigned char POD19:1; + unsigned char POD18:1; + unsigned char POD17:1; + unsigned char POD16:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR31:1; + unsigned char NDR30:1; + unsigned char NDR29:1; + unsigned char NDR28:1; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR23:1; + unsigned char NDR22:1; + unsigned char NDR21:1; + unsigned char NDR20:1; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR27:1; + unsigned char NDR26:1; + unsigned char NDR25:1; + unsigned char NDR24:1; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NDR19:1; + unsigned char NDR18:1; + unsigned char NDR17:1; + unsigned char NDR16:1; + } BIT; + } NDRL2; +} st_ppg1_t; + +typedef struct st_ptpedmac { + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long DE:1; + unsigned long DL:2; + unsigned long :3; + unsigned long SWR:1; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long TR:1; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RR:1; + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWB:1; + unsigned long :3; + unsigned long TABT:1; + unsigned long :1; + unsigned long RFCOF:1; + unsigned long :2; + unsigned long TC:1; + unsigned long TDE:1; + unsigned long TFUF:1; + unsigned long FR:1; + unsigned long RDE:1; + unsigned long RFOF:1; + unsigned long :7; + unsigned long MACE:1; + unsigned long RPORT:1; + unsigned long :2; + unsigned long PVER:1; + unsigned long TYPE:4; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long TWBIP:1; + unsigned long :3; + unsigned long TABTIP:1; + unsigned long :1; + unsigned long RFCOFIP:1; + unsigned long :2; + unsigned long TCIP:1; + unsigned long TDEIP:1; + unsigned long TFUFIP:1; + unsigned long FRIP:1; + unsigned long RDEIP:1; + unsigned long RFOFIP:1; + unsigned long :7; + unsigned long MACEIP:1; + unsigned long RPORTIP:1; + unsigned long :2; + unsigned long PVERIP:1; + unsigned long :4; + } BIT; + } EESIPR; + char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long MFC:16; + } BIT; + } RMFCR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long TFT:11; + } BIT; + } TFTR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TFD:5; + unsigned long :3; + unsigned long RFD:5; + } BIT; + } FDR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long RNR:1; + } BIT; + } RMCR; + char wk10[8]; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long UNDER:16; + } BIT; + } TFUCR; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long OVER:16; + } BIT; + } RFOCR; + char wk11[4]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + unsigned long RFDO:3; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long :14; + unsigned long PADS:2; + unsigned long :10; + unsigned long PADR:6; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long :27; + unsigned long TIM:1; + unsigned long :3; + unsigned long TIS:1; + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_ptpedmac_t; + +typedef struct st_qspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char :1; + unsigned char MSTR:1; + unsigned char :1; + unsigned char SPSSLIE:1; + unsigned char :1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SSLP:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :1; + unsigned char IO3FV:1; + unsigned char IO2FV:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRFF:1; + unsigned char TREND:1; + unsigned char SPTEF:1; + unsigned char SPSSLF:1; + unsigned char :4; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SPSC:2; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char SPSS:2; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPBR7:1; + unsigned char SPBR6:1; + unsigned char SPBR5:1; + unsigned char SPBR4:1; + unsigned char SPBR3:1; + unsigned char SPBR2:1; + unsigned char SPBR1:1; + unsigned char SPBR0:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char TXDMY:1; + unsigned char :7; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SPIMOD:2; + unsigned short SPRW:1; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned char BYTE; + struct { + unsigned char TXRST:1; + unsigned char RXRST:1; + unsigned char TXTRG:2; + unsigned char TXTRGEX:1; + unsigned char RXTRG:3; + } BIT; + } SPBFCR; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TXBC:6; + unsigned short :2; + unsigned short RXBC:6; + } BIT; + } SPBDCR; + unsigned long SPBMUL0; + unsigned long SPBMUL1; + unsigned long SPBMUL2; + unsigned long SPBMUL3; +} st_qspi_t; + +typedef struct st_ram { + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RAMMODE:2; + } BIT; + } RAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RAMERR:1; + } BIT; + } RAMSTS; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char RAMPRCR:1; + } BIT; + } RAMPRCR; + char wk1[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long READ:16; + unsigned long :3; + } BIT; + } RAMECAD; + char wk2[52]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char EXRAMMODE:2; + } BIT; + } EXRAMMODE; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EXRAMERR:1; + } BIT; + } EXRAMSTS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + unsigned char KW:7; + unsigned char EXRAMPRCR:1; + } BIT; + } EXRAMPRCR; + char wk4[3]; + union { + unsigned long LONG; + struct { + unsigned long :13; + unsigned long READ:16; + unsigned long :3; + } BIT; + } EXRAMECAD; +} st_ram_t; + +typedef struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + unsigned char :1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char FMPE:1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +} st_riic_t; + +typedef struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :2; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRF:1; + unsigned char :1; + unsigned char SPTEF:1; + unsigned char UDRF:1; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPBYT:1; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char :2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SCKASE:1; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BYSW:1; + } BIT; + } SPDCR2; +} st_rspi_t; + +typedef struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT1; + }; + char wk2[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT2; + }; + char wk3[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + union { + unsigned char BYTE; + struct { + unsigned char BCNT:8; + } BIT; + } BCNT3; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT0AR; + }; + char wk7[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT1AR; + }; + char wk8[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT2AR; + }; + char wk9[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + union { + unsigned char BYTE; + struct { + unsigned char BCNTAR:8; + } BIT; + } BCNT3AR; + }; + char wk10[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT0AER; + }; + char wk11[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT1AER; + }; + char wk12[1]; + union { + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ENB:8; + } BIT; + } BCNT2AER; + }; + union { + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :7; + } BIT; + } RYRAREN; + union { + unsigned char BYTE; + struct { + unsigned char ENB:8; + } BIT; + } BCNT3AER; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char RTCOS:1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char CNTMD:1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCDV:3; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RCKSEL:1; + } BIT; + } RCR4; + char wk17[1]; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RFC:1; + } BIT; + } RFRH; + union { + unsigned short WORD; + struct { + unsigned short RFC:16; + } BIT; + } RFRL; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; + char wk18[17]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR0; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR2; + char wk21[13]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT0CP0; + }; + char wk22[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT1CP0; + }; + char wk23[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT2CP0; + }; + char wk24[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP0; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP0:8; + } BIT; + } BCNT3CP0; + }; + char wk25[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP0; + char wk26[5]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT0CP1; + }; + char wk27[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT1CP1; + }; + char wk28[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT2CP1; + }; + char wk29[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP1; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP1:8; + } BIT; + } BCNT3CP1; + }; + char wk30[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP1; + char wk31[5]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT0CP2; + }; + char wk32[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT1CP2; + }; + char wk33[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT2CP2; + }; + char wk34[3]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP2; + union { + unsigned char BYTE; + struct { + unsigned char BCNTCP2:8; + } BIT; + } BCNT3CP2; + }; + char wk35[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP2; +} st_rtc_t; + +typedef struct st_s12ad { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :2; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSA007:1; + unsigned short ANSA006:1; + unsigned short ANSA005:1; + unsigned short ANSA004:1; + unsigned short ANSA003:1; + unsigned short ANSA002:1; + unsigned short ANSA001:1; + unsigned short ANSA000:1; + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ADS007:1; + unsigned short ADS006:1; + unsigned short ADS005:1; + unsigned short ADS004:1; + unsigned short ADS003:1; + unsigned short ADS002:1; + unsigned short ADS001:1; + unsigned short ADS000:1; + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :4; + unsigned char ADC:3; + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short ADPRC:2; + unsigned short :1; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSB007:1; + unsigned short ANSB006:1; + unsigned short ANSB005:1; + unsigned short ANSB004:1; + unsigned short ANSB003:1; + unsigned short ANSB002:1; + unsigned short ANSB001:1; + unsigned short ANSB000:1; + } BIT; + } ADANSB0; + char wk5[2]; + union { + unsigned short WORD; + } ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk7[51]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PRO:2; + } BIT; + } ADSAMPR; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SHANS:3; + unsigned short SSTSH:8; + } BIT; + } ADSHCR; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short SAM:1; + unsigned short :5; + } BIT; + } ADSAM; + char wk10[10]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHMD:1; + } BIT; + } ADSHMSR; + char wk12[3]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short LGRRS:1; + unsigned short :12; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk13[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk14[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MONCMPB:1; + unsigned char MONCMPA:1; + unsigned char :3; + unsigned char MONCOMB:1; + } BIT; + } ADWINMON; + char wk15[3]; + union { + unsigned short WORD; + struct { + unsigned short CMPAIE:1; + unsigned short WCMPE:1; + unsigned short CMPBIE:1; + unsigned short :1; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBE:1; + unsigned short :7; + unsigned short CMPAB:2; + } BIT; + } ADCMPCR; + char wk16[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPCHA007:1; + unsigned short CMPCHA006:1; + unsigned short CMPCHA005:1; + unsigned short CMPCHA004:1; + unsigned short CMPCHA003:1; + unsigned short CMPCHA002:1; + unsigned short CMPCHA001:1; + unsigned short CMPCHA000:1; + } BIT; + } ADCMPANSR0; + char wk17[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPLCHA007:1; + unsigned short CMPLCHA006:1; + unsigned short CMPLCHA005:1; + unsigned short CMPLCHA004:1; + unsigned short CMPLCHA003:1; + unsigned short CMPLCHA002:1; + unsigned short CMPLCHA001:1; + unsigned short CMPLCHA000:1; + } BIT; + } ADCMPLR0; + char wk18[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPSTCHA007:1; + unsigned short CMPSTCHA006:1; + unsigned short CMPSTCHA005:1; + unsigned short CMPSTCHA004:1; + unsigned short CMPSTCHA003:1; + unsigned short CMPSTCHA002:1; + unsigned short CMPSTCHA001:1; + unsigned short CMPSTCHA000:1; + } BIT; + } ADCMPSR0; + char wk19[4]; + union { + unsigned char BYTE; + struct { + unsigned char CMPLB:1; + unsigned char :1; + unsigned char CMPCHB:6; + } BIT; + } ADCMPBNSR; + char wk20[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CMPSTB:1; + } BIT; + } ADCMPBSR; + char wk21[39]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSC007:1; + unsigned short ANSC006:1; + unsigned short ANSC005:1; + unsigned short ANSC004:1; + unsigned short ANSC003:1; + unsigned short ANSC002:1; + unsigned short ANSC001:1; + unsigned short ANSC000:1; + } BIT; + } ADANSC0; + char wk22[3]; + union { + unsigned char BYTE; + struct { + unsigned char GRCE:1; + unsigned char GCADIE:1; + unsigned char TRSC:6; + } BIT; + } ADGCTRGR; + char wk23[6]; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +} st_s12ad_t; + +typedef struct st_s12ad1 { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :2; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short ANSA015:1; + unsigned short ANSA014:1; + unsigned short ANSA013:1; + unsigned short ANSA012:1; + unsigned short ANSA011:1; + unsigned short ANSA010:1; + unsigned short ANSA009:1; + unsigned short ANSA008:1; + unsigned short ANSA007:1; + unsigned short ANSA006:1; + unsigned short ANSA005:1; + unsigned short ANSA004:1; + unsigned short ANSA003:1; + unsigned short ANSA002:1; + unsigned short ANSA001:1; + unsigned short ANSA000:1; + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSA104:1; + unsigned short ANSA103:1; + unsigned short ANSA102:1; + unsigned short ANSA101:1; + unsigned short ANSA100:1; + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + unsigned short ADS015:1; + unsigned short ADS014:1; + unsigned short ADS013:1; + unsigned short ADS012:1; + unsigned short ADS011:1; + unsigned short ADS010:1; + unsigned short ADS009:1; + unsigned short ADS008:1; + unsigned short ADS007:1; + unsigned short ADS006:1; + unsigned short ADS005:1; + unsigned short ADS004:1; + unsigned short ADS003:1; + unsigned short ADS002:1; + unsigned short ADS001:1; + unsigned short ADS000:1; + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ADS104:1; + unsigned short ADS103:1; + unsigned short ADS102:1; + unsigned short ADS101:1; + unsigned short ADS100:1; + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :4; + unsigned char ADC:3; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short ADPRC:2; + unsigned short :1; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + unsigned short EXOEN:1; + unsigned short EXSEL:2; + unsigned short :1; + unsigned short OCSB:1; + unsigned short TSSB:1; + unsigned short OCSA:1; + unsigned short TSSA:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + unsigned short ANSB015:1; + unsigned short ANSB014:1; + unsigned short ANSB013:1; + unsigned short ANSB012:1; + unsigned short ANSB011:1; + unsigned short ANSB010:1; + unsigned short ANSB009:1; + unsigned short ANSB008:1; + unsigned short ANSB007:1; + unsigned short ANSB006:1; + unsigned short ANSB005:1; + unsigned short ANSB004:1; + unsigned short ANSB003:1; + unsigned short ANSB002:1; + unsigned short ANSB001:1; + unsigned short ANSB000:1; + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSB104:1; + unsigned short ANSB103:1; + unsigned short ANSB102:1; + unsigned short ANSB101:1; + unsigned short ANSB100:1; + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk2[25]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char PRO:2; + } BIT; + } ADSAMPR; + char wk3[10]; + union { + unsigned short WORD; + struct { + unsigned short :10; + unsigned short SAM:1; + unsigned short :5; + } BIT; + } ADSAM; + char wk4[10]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk5[5]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short LGRRS:1; + unsigned short :12; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MONCMPB:1; + unsigned char MONCMPA:1; + unsigned char :3; + unsigned char MONCOMB:1; + } BIT; + } ADWINMON; + char wk8[3]; + union { + unsigned short WORD; + struct { + unsigned short CMPAIE:1; + unsigned short WCMPE:1; + unsigned short CMPBIE:1; + unsigned short :1; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBE:1; + unsigned short :7; + unsigned short CMPAB:2; + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPSOC:1; + unsigned char CMPSTS:1; + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPLOC:1; + unsigned char CMPLTS:1; + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + unsigned short CMPCHA015:1; + unsigned short CMPCHA014:1; + unsigned short CMPCHA013:1; + unsigned short CMPCHA012:1; + unsigned short CMPCHA011:1; + unsigned short CMPCHA010:1; + unsigned short CMPCHA009:1; + unsigned short CMPCHA008:1; + unsigned short CMPCHA007:1; + unsigned short CMPCHA006:1; + unsigned short CMPCHA005:1; + unsigned short CMPCHA004:1; + unsigned short CMPCHA003:1; + unsigned short CMPCHA002:1; + unsigned short CMPCHA001:1; + unsigned short CMPCHA000:1; + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPCHA104:1; + unsigned short CMPCHA103:1; + unsigned short CMPCHA102:1; + unsigned short CMPCHA101:1; + unsigned short CMPCHA100:1; + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + unsigned short CMPLCHA015:1; + unsigned short CMPLCHA014:1; + unsigned short CMPLCHA013:1; + unsigned short CMPLCHA012:1; + unsigned short CMPLCHA011:1; + unsigned short CMPLCHA010:1; + unsigned short CMPLCHA009:1; + unsigned short CMPLCHA008:1; + unsigned short CMPLCHA007:1; + unsigned short CMPLCHA006:1; + unsigned short CMPLCHA005:1; + unsigned short CMPLCHA004:1; + unsigned short CMPLCHA003:1; + unsigned short CMPLCHA002:1; + unsigned short CMPLCHA001:1; + unsigned short CMPLCHA000:1; + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPLCHA104:1; + unsigned short CMPLCHA103:1; + unsigned short CMPLCHA102:1; + unsigned short CMPLCHA101:1; + unsigned short CMPLCHA100:1; + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short CMPSTCHA015:1; + unsigned short CMPSTCHA014:1; + unsigned short CMPSTCHA013:1; + unsigned short CMPSTCHA012:1; + unsigned short CMPSTCHA011:1; + unsigned short CMPSTCHA010:1; + unsigned short CMPSTCHA009:1; + unsigned short CMPSTCHA008:1; + unsigned short CMPSTCHA007:1; + unsigned short CMPSTCHA006:1; + unsigned short CMPSTCHA005:1; + unsigned short CMPSTCHA004:1; + unsigned short CMPSTCHA003:1; + unsigned short CMPSTCHA002:1; + unsigned short CMPSTCHA001:1; + unsigned short CMPSTCHA000:1; + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short CMPSTCHA104:1; + unsigned short CMPSTCHA103:1; + unsigned short CMPSTCHA102:1; + unsigned short CMPSTCHA101:1; + unsigned short CMPSTCHA100:1; + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPFOC:1; + unsigned char CMPFTS:1; + } BIT; + } ADCMPSER; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char CMPLB:1; + unsigned char :1; + unsigned char CMPCHB:6; + } BIT; + } ADCMPBNSR; + char wk10[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CMPSTB:1; + } BIT; + } ADCMPBSR; + char wk11[39]; + union { + unsigned short WORD; + struct { + unsigned short ANSC015:1; + unsigned short ANSC014:1; + unsigned short ANSC013:1; + unsigned short ANSC012:1; + unsigned short ANSC011:1; + unsigned short ANSC010:1; + unsigned short ANSC009:1; + unsigned short ANSC008:1; + unsigned short ANSC007:1; + unsigned short ANSC006:1; + unsigned short ANSC005:1; + unsigned short ANSC004:1; + unsigned short ANSC003:1; + unsigned short ANSC002:1; + unsigned short ANSC001:1; + unsigned short ANSC000:1; + } BIT; + } ADANSC0; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short ANSC104:1; + unsigned short ANSC103:1; + unsigned short ANSC102:1; + unsigned short ANSC101:1; + unsigned short ANSC100:1; + } BIT; + } ADANSC1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char OCSC:1; + unsigned char TSSC:1; + } BIT; + } ADGCEXCR; + union { + unsigned char BYTE; + struct { + unsigned char GRCE:1; + unsigned char GCADIE:1; + unsigned char TRSC:6; + } BIT; + } ADGCTRGR; + char wk12[3]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + unsigned char ADSSTR8; + unsigned char ADSSTR9; + unsigned char ADSSTR10; + unsigned char ADSSTR11; + unsigned char ADSSTR12; + unsigned char ADSSTR13; + unsigned char ADSSTR14; + unsigned char ADSSTR15; +} st_s12ad1_t; + +typedef struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char ABCSE:1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + unsigned char DCME:1; + unsigned char IDSEL:1; + unsigned char :1; + unsigned char DFER:1; + unsigned char DPER:1; + unsigned char :2; + unsigned char DCMF:1; + } BIT; + } DCCR; + char wk0[6]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :7; + unsigned short CMPD:9; + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPB2IO:1; + unsigned char SPB2DT:1; + unsigned char RXDMON:1; + } BIT; + } SPTR; +} st_sci0_t; + +typedef struct st_sci7 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + union { + unsigned char BYTE; + struct { + unsigned char TDFE:1; + unsigned char RDF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char :1; + unsigned char DR:1; + } BIT; + } SSRFIFO; + }; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char ABCSE:1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :6; + unsigned short MPBT:1; + unsigned short TDAT:9; + } BIT; + } FTDR; + }; + union { + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :1; + unsigned short RDF:1; + unsigned short ORER:1; + unsigned short FER:1; + unsigned short PER:1; + unsigned short DR:1; + unsigned short MPB:1; + unsigned short RDAT:9; + } BIT; + } FRDR; + }; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + unsigned char DCME:1; + unsigned char IDSEL:1; + unsigned char :1; + unsigned char DFER:1; + unsigned char DPER:1; + unsigned char :2; + unsigned char DCMF:1; + } BIT; + } DCCR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char RSTRG:4; + unsigned char RTRG:4; + unsigned char TTRG:4; + unsigned char DRES:1; + unsigned char TFRST:1; + unsigned char RFRST:1; + unsigned char FM:1; + } BIT; + } FCR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char T:5; + unsigned char :3; + unsigned char R:5; + } BIT; + } FDR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char PNUM:5; + unsigned char :1; + unsigned char FNUM:5; + unsigned char :1; + unsigned char ORER:1; + } BIT; + } LSR; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned short :7; + unsigned short CMPD:9; + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPB2IO:1; + unsigned char SPB2DT:1; + unsigned char RXDMON:1; + } BIT; + } SPTR; +} st_sci7_t; + +typedef struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + unsigned char :1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_sdhi { + union { + unsigned long LONG; +#ifdef IODEFINE_H_HISTORY + struct { + unsigned long :16; + unsigned long CMD12AT:2; + unsigned long TRSTP:1; + unsigned long CMDRW:1; + unsigned long CMDTP:1; + unsigned long RSPTP:3; + unsigned long ACMD:2; + unsigned long CMDIDX:6; + } BIT; +#endif + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long SDBLKCNTEN:1; + unsigned long :7; + unsigned long STP:1; + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long :21; + unsigned long SDD3MON:1; + unsigned long SDD3IN:1; + unsigned long SDD3RM:1; + unsigned long SDWPMON:1; + unsigned long :1; + unsigned long SDCDMON:1; + unsigned long SDCDIN:1; + unsigned long SDCDRM:1; + unsigned long ACEND:1; + unsigned long :1; + unsigned long RSPEND:1; + } BIT; + } SDSTS1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILA:1; + unsigned long CBSY:1; + unsigned long SDCLKCREN:1; + unsigned long :3; + unsigned long BWE:1; + unsigned long BRE:1; + unsigned long SDD0MON:1; + unsigned long RSPTO:1; + unsigned long ILR:1; + unsigned long ILW:1; + unsigned long DTO:1; + unsigned long ENDE:1; + unsigned long CRCE:1; + unsigned long CMDE:1; + } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long SDD3INM:1; + unsigned long SDD3RMM:1; + unsigned long :3; + unsigned long SDCDINM:1; + unsigned long SDCDRMM:1; + unsigned long ACENDM:1; + unsigned long :1; + unsigned long RSPENDM:1; + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILAM:1; + unsigned long :5; + unsigned long BWEM:1; + unsigned long BREM:1; + unsigned long :1; + unsigned long RSPTOM:1; + unsigned long ILRM:1; + unsigned long ILWM:1; + unsigned long DTTOM:1; + unsigned long ENDEM:1; + unsigned long CRCEM:1; + unsigned long CMDEM:1; + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long CLKCTRLEN:1; + unsigned long CLKEN:1; + unsigned long CLKSEL:8; + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long LEN:10; + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long WIDTH:1; + unsigned long :7; + unsigned long TOP:4; + unsigned long CTOP:4; + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CRCTK:3; + unsigned long CRCTKE:1; + unsigned long RDCRCE:1; + unsigned long RSPCRCE1:1; + unsigned long RSPCRCE0:1; + unsigned long :2; + unsigned long CRCLENE:1; + unsigned long RDLENE:1; + unsigned long RSPLENE1:1; + unsigned long RSPLENE0:1; + unsigned long CMDE1:1; + unsigned long CMDE0:1; + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long CRCBSYTO:1; + unsigned long CRCTO:1; + unsigned long RDTO:1; + unsigned long BSYTO1:1; + unsigned long BSYTO0:1; + unsigned long RSPTO1:1; + unsigned long RSPTO0:1; + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long C52PUB:1; + unsigned long IOABT:1; + unsigned long :5; + unsigned long RWREQ:1; + unsigned long :1; + unsigned long INTEN:1; + } BIT; + } SDIOMD; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWT:1; + unsigned long EXPUB52:1; + unsigned long :13; + unsigned long IOIRQ:1; + } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWTM:1; + unsigned long EXPUB52M:1; + unsigned long :13; + unsigned long IOIRQM:1; + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long DMAEN:1; + unsigned long :1; + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SDRST:1; + } BIT; + } SDRST; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long CPRM:1; + unsigned long CLKRAT:1; + unsigned long :2; + unsigned long IP2:4; + unsigned long IP1:8; + } BIT; + } SDVER; + char wk10[24]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long BRSWP:1; + unsigned long BWSWP:1; + unsigned long :6; + } BIT; + } SDSWAP; +} st_sdhi_t; + +typedef struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; +} st_smci_t; + +typedef struct st_ssie { + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIEN:1; + unsigned long TOIEN:1; + unsigned long RUIEN:1; + unsigned long ROIEN:1; + unsigned long IIEN:1; + unsigned long :1; + unsigned long FRM:2; + unsigned long DWL:3; + unsigned long SWL:3; + unsigned long :1; + unsigned long MST:1; + unsigned long BCKP:1; + unsigned long LRCKP:1; + unsigned long SPDP:1; + unsigned long SDTA:1; + unsigned long PDTA:1; + unsigned long DEL:1; + unsigned long CKDV:4; + unsigned long MUEN:1; + unsigned long :1; + unsigned long TEN:1; + unsigned long REN:1; + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIRQ:1; + unsigned long TOIRQ:1; + unsigned long RUIRQ:1; + unsigned long ROIRQ:1; + unsigned long IIRQ:1; + unsigned long :25; + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long AUCKE:1; + unsigned long :14; + unsigned long SSIRST:1; + unsigned long :4; + unsigned long BSW:1; + unsigned long :7; + unsigned long TIE:1; + unsigned long RIE:1; + unsigned long TFRST:1; + unsigned long RFRST:1; + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TDC:6; + unsigned long :7; + unsigned long TDE:1; + unsigned long :2; + unsigned long RDC:6; + unsigned long :7; + unsigned long RDF:1; + } BIT; + } SSIFSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SSIFTDR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SSIFRDR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long BCKASTP:1; + unsigned long LRCONT:1; + unsigned long :6; + unsigned long OMOD:2; + } BIT; + } SSIOFR; + union { + unsigned long LONG; + struct { + unsigned long :19; + unsigned long TDES:5; + unsigned long :3; + unsigned long RDFS:5; + } BIT; + } SSISCR; +} st_ssie_t; + +typedef struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SBYRAME:1; + unsigned short ECCRAME:1; + unsigned short :5; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + unsigned short :14; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long ACSE:1; + unsigned long :1; + unsigned long MSTPA29:1; + unsigned long MSTPA28:1; + unsigned long MSTPA27:1; + unsigned long :2; + unsigned long MSTPA24:1; + unsigned long :4; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long MSTPA16:1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long MSTPA13:1; + unsigned long :1; + unsigned long MSTPA11:1; + unsigned long MSTPA10:1; + unsigned long MSTPA9:1; + unsigned long :1; + unsigned long MSTPA7:1; + unsigned long :1; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :2; + unsigned long MSTPA1:1; + unsigned long MSTPA0:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long MSTPB29:1; + unsigned long MSTPB28:1; + unsigned long MSTPB27:1; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long MSTPB24:1; + unsigned long MSTPB23:1; + unsigned long MSTPB22:1; + unsigned long MSTPB21:1; + unsigned long MSTPB20:1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long MSTPB16:1; + unsigned long MSTPB15:1; + unsigned long MSTPB14:1; + unsigned long MSTPB13:1; + unsigned long :3; + unsigned long MSTPB9:1; + unsigned long MSTPB8:1; + unsigned long :1; + unsigned long MSTPB6:1; + unsigned long :1; + unsigned long MSTPB4:1; + unsigned long :1; + unsigned long MSTPB2:1; + unsigned long MSTPB1:1; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long MSTPC29:1; + unsigned long MSTPC28:1; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long MSTPC25:1; + unsigned long MSTPC24:1; + unsigned long MSTPC23:1; + unsigned long MSTPC22:1; + unsigned long :2; + unsigned long MSTPC19:1; + unsigned long :1; + unsigned long MSTPC17:1; + unsigned long :9; + unsigned long MSTPC7:1; + unsigned long MSTPC6:1; + unsigned long :3; + unsigned long MSTPC2:1; + unsigned long :1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long MSTPD27:1; + unsigned long :5; + unsigned long MSTPD21:1; + unsigned long :1; + unsigned long MSTPD19:1; + unsigned long :3; + unsigned long MSTPD15:1; + unsigned long MSTPD14:1; + unsigned long :6; + unsigned long MSTPD7:1; + unsigned long MSTPD6:1; + unsigned long MSTPD5:1; + unsigned long MSTPD4:1; + unsigned long MSTPD3:1; + unsigned long MSTPD2:1; + unsigned long MSTPD1:1; + unsigned long MSTPD0:1; + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long PSTOP0:1; + unsigned long :2; + unsigned long BCK:4; + unsigned long PCKA:4; + unsigned long PCKB:4; + unsigned long PCKC:4; + unsigned long PCKD:4; + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short UCK:4; + unsigned short :4; + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + unsigned short :8; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :3; + unsigned short PLLSRCSEL:1; + unsigned short :2; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk3[5]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char HCFRQ:2; + } BIT; + } HOCOCR2; + char wk5[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PPLOVF:1; + unsigned char ILCOVF:1; + unsigned char HCOVF:1; + unsigned char PLOVF:1; + unsigned char SOOVF:1; + unsigned char MOOVF:1; + } BIT; + } OSCOVFSR; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short CKOSTP:1; + unsigned short CKODIV:3; + unsigned short :1; + unsigned short CKOSEL:3; + unsigned short :8; + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short UPLLSEL:1; + unsigned short :7; + unsigned short OUTCKSEL:1; + unsigned short :4; + } BIT; + } PACKCR; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short PPLSTC:6; + unsigned short :6; + unsigned short PPLIDIV:2; + } BIT; + } PPLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PPLLEN:1; + } BIT; + } PPLLCR2; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PPLCK:4; + } BIT; + } PPLLCR3; + char wk9[84]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char MSTS:8; + } BIT; + } MOSCWTCR; + union { + unsigned char BYTE; + struct { + unsigned char SSTS:8; + } BIT; + } SOSCWTCR; + char wk10[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char WDTRF:1; + unsigned char IWDTRF:1; + } BIT; + } RSTSR2; + char wk11[1]; + unsigned short SWRR; + char wk12[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD1IRQSEL:1; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD2IRQSEL:1; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk13[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short :1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk14[3100]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MEMWAIT:1; + } BIT; + } MEMWAIT; + char wk15[45667]; + union { + unsigned char BYTE; + struct { + unsigned char DPSBY:1; + unsigned char IOKEEP:1; + unsigned char :4; + unsigned char DEEPCUT:2; + } BIT; + } DPSBYCR; + char wk16[1]; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7E:1; + unsigned char DIRQ6E:1; + unsigned char DIRQ5E:1; + unsigned char DIRQ4E:1; + unsigned char DIRQ3E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ0E:1; + } BIT; + } DPSIER0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15E:1; + unsigned char DIRQ14E:1; + unsigned char DIRQ13E:1; + unsigned char DIRQ12E:1; + unsigned char DIRQ11E:1; + unsigned char DIRQ10E:1; + unsigned char DIRQ9E:1; + unsigned char DIRQ8E:1; + } BIT; + } DPSIER1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIE:1; + unsigned char DRIICCIE:1; + unsigned char DRIICDIE:1; + unsigned char DNMIE:1; + unsigned char DRTCAIE:1; + unsigned char DRTCIIE:1; + unsigned char DLVD2IE:1; + unsigned char DLVD1IE:1; + } BIT; + } DPSIER2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIE:1; + } BIT; + } DPSIER3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7F:1; + unsigned char DIRQ6F:1; + unsigned char DIRQ5F:1; + unsigned char DIRQ4F:1; + unsigned char DIRQ3F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ0F:1; + } BIT; + } DPSIFR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15F:1; + unsigned char DIRQ14F:1; + unsigned char DIRQ13F:1; + unsigned char DIRQ12F:1; + unsigned char DIRQ11F:1; + unsigned char DIRQ10F:1; + unsigned char DIRQ9F:1; + unsigned char DIRQ8F:1; + } BIT; + } DPSIFR1; + union { + unsigned char BYTE; + struct { + unsigned char DUSBIF:1; + unsigned char DRIICCIF:1; + unsigned char DRIICDIF:1; + unsigned char DNMIF:1; + unsigned char DRTCAIF:1; + unsigned char DRTCIIF:1; + unsigned char DLVD2IF:1; + unsigned char DLVD1IF:1; + } BIT; + } DPSIFR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIF:1; + } BIT; + } DPSIFR3; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ7EG:1; + unsigned char DIRQ6EG:1; + unsigned char DIRQ5EG:1; + unsigned char DIRQ4EG:1; + unsigned char DIRQ3EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ0EG:1; + } BIT; + } DPSIEGR0; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ15EG:1; + unsigned char DIRQ14EG:1; + unsigned char DIRQ13EG:1; + unsigned char DIRQ12EG:1; + unsigned char DIRQ11EG:1; + unsigned char DIRQ10EG:1; + unsigned char DIRQ9EG:1; + unsigned char DIRQ8EG:1; + } BIT; + } DPSIEGR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DRIICCEG:1; + unsigned char DRIICDEG:1; + unsigned char DNMIEG:1; + unsigned char :2; + unsigned char DLVD2EG:1; + unsigned char DLVD1EG:1; + } BIT; + } DPSIEGR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DCANIEG:1; + } BIT; + } DPSIEGR3; + char wk17[2]; + union { + unsigned char BYTE; + struct { + unsigned char DPSRSTF:1; + unsigned char :3; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char LVD0RF:1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk18[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MOSEL:1; + unsigned char MODRV2:2; + unsigned char :3; + unsigned char MOFXIN:1; + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HOCOPCNT:1; + } BIT; + } HOCOPCR; + char wk19[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + unsigned char :5; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char LVD2LVL:4; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk20[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char LVD1FSAMP:2; + unsigned char :1; + unsigned char LVD1CMPE:1; + unsigned char LVD1DFDIS:1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char LVD2FSAMP:2; + unsigned char :1; + unsigned char LVD2CMPE:1; + unsigned char LVD2DFDIS:1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; + char wk21[4]; + unsigned char DPSBKR[32]; +} st_system_t; + +typedef struct st_temps { + union { + unsigned char BYTE; + struct { + unsigned char TSEN:1; + unsigned char :2; + unsigned char TSOE:1; + unsigned char :4; + } BIT; + } TSCR; +} st_temps_t; + +typedef struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADTE:1; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +} st_tmr0_t; + +typedef struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +} st_tmr1_t; + +typedef struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +} st_tmr01_t; + +typedef struct st_tpu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu0_t; + +typedef struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu1_t; + +typedef struct st_tpu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu2_t; + +typedef struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu3_t; + +typedef struct st_tpu4 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu4_t; + +typedef struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :2; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ICSELB:1; + unsigned char :2; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu5_t; + +typedef struct st_tpua { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST5:1; + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC5:1; + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; +} st_tpua_t; + +typedef struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBSTS0:1; + unsigned long :1; + unsigned long DOVCB0:1; + unsigned long DOVCA0:1; + unsigned long :2; + unsigned long DM0:1; + unsigned long DP0:1; + unsigned long :11; + unsigned long FIXPHY0:1; + unsigned long DRPD0:1; + unsigned long :1; + unsigned long RPUE0:1; + unsigned long SRPC0:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long DVBINT0:1; + unsigned long :1; + unsigned long DOVRCRB0:1; + unsigned long DOVRCRA0:1; + unsigned long :2; + unsigned long DMINT0:1; + unsigned long DPINT0:1; + unsigned long :8; + unsigned long DVBSE0:1; + unsigned long :1; + unsigned long DOVRCRBE0:1; + unsigned long DOVRCRAE0:1; + unsigned long :2; + unsigned long DMINTE0:1; + unsigned long DPINTE0:1; + } BIT; + } DPUSR1R; +} st_usb_t; + +typedef struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short SCKE:1; + unsigned short :3; + unsigned short DCFM:1; + unsigned short DRPD:1; + unsigned short DPRPU:1; + unsigned short :3; + unsigned short USBE:1; + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short SOFEA:1; + unsigned short :2; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short HNPBTOA:1; + unsigned short EXICEN:1; + unsigned short VBUSEN:1; + unsigned short WKUP:1; + unsigned short RWUPE:1; + unsigned short USBRST:1; + unsigned short RESUME:1; + unsigned short UACT:1; + unsigned short :1; + unsigned short RHST:3; + } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + unsigned short :8; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short OVRCRE:1; + unsigned short BCHGE:1; + unsigned short :1; + unsigned short DTCHE:1; + unsigned short ATTCHE:1; + unsigned short :4; + unsigned short EOFERRE:1; + unsigned short SIGNE:1; + unsigned short SACKE:1; + unsigned short :4; + } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short TRNENSEL:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + unsigned short :4; + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short OVRCR:1; + unsigned short BCHG:1; + unsigned short :1; + unsigned short DTCH:1; + unsigned short ATTCH:1; + unsigned short :4; + unsigned short EOFERR:1; + unsigned short SIGN:1; + unsigned short SACK:1; + unsigned short :4; + } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDY:1; + unsigned short PIPE8NRDY:1; + unsigned short PIPE7NRDY:1; + unsigned short PIPE6NRDY:1; + unsigned short PIPE5NRDY:1; + unsigned short PIPE4NRDY:1; + unsigned short PIPE3NRDY:1; + unsigned short PIPE2NRDY:1; + unsigned short PIPE1NRDY:1; + unsigned short PIPE0NRDY:1; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMP:1; + unsigned short PIPE8BEMP:1; + unsigned short PIPE7BEMP:1; + unsigned short PIPE6BEMP:1; + unsigned short PIPE5BEMP:1; + unsigned short PIPE4BEMP:1; + unsigned short PIPE3BEMP:1; + unsigned short PIPE2BEMP:1; + unsigned short PIPE1BEMP:1; + unsigned short PIPE0BEMP:1; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short DVCHG:1; + unsigned short :15; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short STSRECOV:4; + unsigned short :1; + unsigned short USBADDR:7; + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short :4; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :5; + unsigned short MXPS:7; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short SUREQ:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short PIPESEL:4; + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short DEVSEL:4; + unsigned short :3; + unsigned short MXPS:9; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; + } BIT; + } DEVADD5; + char wk16[20]; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long SLEWF01:1; + unsigned long SLEWF00:1; + unsigned long SLEWR01:1; + unsigned long SLEWR00:1; + } BIT; + } PHYSLEW; +} st_usb0_t; + +typedef struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } WDTRCR; +} st_wdt_t; + +typedef struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +} st_flashconst_t; + +typedef struct st_tempsconst { + unsigned long TSCDR; +} st_tempsconst_t; + +#pragma bit_order +#pragma packoption + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c new file mode 100644 index 000000000..b36242303 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.c @@ -0,0 +1,202 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.c +* Device(s) : RX72N +* Description : Definition of the exception vector table, reset vector, and user boot options. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* BSP configuration. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION); +R_BSP_UB_POR_FUNCTION(R_BSP_UB_POWER_ON_RESET_FUNCTION); + +/*********************************************************************************************************************** +* The following array fills in the option function select registers, fixed vector table, and the ID code protection +* bytes. +***********************************************************************************************************************/ +#ifdef __BIG + #define BSP_PRV_MDE_VALUE (0xfffffff8) /* big */ +#else + #define BSP_PRV_MDE_VALUE (0xffffffff) /* little */ +#endif + +#if BSP_CFG_CODE_FLASH_BANK_MODE == 0 + #define BSP_PRV_BANK_MODE_VALUE (0xffffff8f) /* dual */ +#else + #define BSP_PRV_BANK_MODE_VALUE (0xffffffff) /* linear */ +#endif + +#if BSP_CFG_CODE_FLASH_START_BANK == 0 + /* The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xffffffff) +#else + /* The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xfffffff8) +#endif + +#if defined(__CCRX__) + +#pragma address __MDEreg = 0xFE7F5D00 +#pragma address __OFS0reg = 0xFE7F5D04 +#pragma address __OFS1reg = 0xFE7F5D08 +#pragma address __TMINFreg = 0xFE7F5D10 +#pragma address __BANKSELreg = 0xFE7F5D20 +#pragma address __SPCCreg = 0xFE7F5D40 +#pragma address __TMEFreg = 0xFE7F5D48 +#pragma address __OSIS1reg = 0xFE7F5D50 +#pragma address __OSIS2reg = 0xFE7F5D54 +#pragma address __OSIS3reg = 0xFE7F5D58 +#pragma address __OSIS4reg = 0xFE7F5D5C +#pragma address __FAWreg = 0xFE7F5D64 +#pragma address __ROMCODEreg = 0xFE7F5D70 + +const uint32_t __MDEreg = (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE); +const uint32_t __OFS0reg = BSP_CFG_OFS0_REG_VALUE; +const uint32_t __OFS1reg = BSP_CFG_OFS1_REG_VALUE; +const uint32_t __TMINFreg = 0xffffffff; +const uint32_t __BANKSELreg = BSP_PRV_START_BANK_VALUE; +const uint32_t __SPCCreg = 0xffffffff; +const uint32_t __TMEFreg = BSP_CFG_TRUSTED_MODE_FUNCTION; +const uint32_t __OSIS1reg = BSP_CFG_ID_CODE_LONG_1; +const uint32_t __OSIS2reg = BSP_CFG_ID_CODE_LONG_2; +const uint32_t __OSIS3reg = BSP_CFG_ID_CODE_LONG_3; +const uint32_t __OSIS4reg = BSP_CFG_ID_CODE_LONG_4; +const uint32_t __FAWreg = BSP_CFG_FAW_REG_VALUE; +const uint32_t __ROMCODEreg = BSP_CFG_ROMCODE_REG_VALUE; + +#elif defined(__GNUC__) + +const st_ofsm_sec_ofs1_t __ofsm_sec_ofs1 __attribute__ ((section(".ofs1"))) = { + (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE), /* __MDEreg */ + BSP_CFG_OFS0_REG_VALUE, /* __OFS0reg */ + BSP_CFG_OFS1_REG_VALUE /* __OFS1reg */ +}; +const uint32_t __TMINFreg __attribute__ ((section(".ofs2"))) = 0xffffffff; +const uint32_t __BANKSELreg __attribute__ ((section(".ofs3"))) = BSP_PRV_START_BANK_VALUE; +const uint32_t __SPCCreg __attribute__ ((section(".ofs4"))) = 0xffffffff; +const uint32_t __TMEFreg __attribute__ ((section(".ofs5"))) = BSP_CFG_TRUSTED_MODE_FUNCTION; +const st_ofsm_sec_ofs6_t __ofsm_sec_ofs6 __attribute__ ((section(".ofs6"))) = { + BSP_CFG_ID_CODE_LONG_1, /* __OSIS1reg */ + BSP_CFG_ID_CODE_LONG_2, /* __OSIS2reg */ + BSP_CFG_ID_CODE_LONG_3, /* __OSIS3reg */ + BSP_CFG_ID_CODE_LONG_4 /* __OSIS4reg */ +}; +const uint32_t __FAWreg __attribute__ ((section(".ofs7"))) = BSP_CFG_FAW_REG_VALUE; +const uint32_t __ROMCODEreg __attribute__ ((section(".ofs8"))) = BSP_CFG_ROMCODE_REG_VALUE; + +#elif defined(__ICCRX__) + +#pragma public_equ = "__MDE", (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE) +#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE +#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE +#pragma public_equ = "__TMINF", 0xffffffff +#pragma public_equ = "__BANKSEL", BSP_PRV_START_BANK_VALUE +#pragma public_equ = "__SPCC", 0xffffffff +#pragma public_equ = "__TMEF", BSP_CFG_TRUSTED_MODE_FUNCTION +#pragma public_equ = "__OSIS_1", BSP_CFG_ID_CODE_LONG_1 +#pragma public_equ = "__OSIS_2", BSP_CFG_ID_CODE_LONG_2 +#pragma public_equ = "__OSIS_3", BSP_CFG_ID_CODE_LONG_3 +#pragma public_equ = "__OSIS_4", BSP_CFG_ID_CODE_LONG_4 +#pragma public_equ = "__FAW", BSP_CFG_FAW_REG_VALUE +#pragma public_equ = "__ROM_CODE", BSP_CFG_ROMCODE_REG_VALUE + +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* The following array fills in the exception vector table. +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* System configurator generates the ritble.src as interrupt & exception vector tables. */ +#else /* BSP_CFG_RTOS_USED!=4 */ + +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT void (* const Except_Vectors[])(void) = +{ + /* Offset from EXTB: Reserved area - must be all 0xFF */ + (void (*)(void))0xFFFFFFFF, /* 0x00 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x04 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x08 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x0c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x10 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x14 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x18 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x1c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x20 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x24 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x28 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x2c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x30 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x34 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x38 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x3c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x40 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x44 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x48 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x4c - Reserved */ + + /* Exception vector table */ + excep_supervisor_inst_isr, /* 0x50 Exception(Supervisor Instruction) */ + excep_access_isr, /* 0x54 Exception(Access exception) */ + undefined_interrupt_source_isr, /* 0x58 Reserved */ + excep_undefined_inst_isr, /* 0x5c Exception(Undefined Instruction) */ + undefined_interrupt_source_isr, /* 0x60 Reserved */ + excep_floating_point_isr, /* 0x64 Exception(Floating Point) */ + undefined_interrupt_source_isr, /* 0x68 Reserved */ + undefined_interrupt_source_isr, /* 0x6c Reserved */ + undefined_interrupt_source_isr, /* 0x70 Reserved */ + undefined_interrupt_source_isr, /* 0x74 Reserved */ + non_maskable_isr, /* 0x78 NMI */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +* The following array fills in the reset vector. +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT void (* const Reset_Vector[])(void) = +{ + R_BSP_POWER_ON_RESET_FUNCTION /* 0xfffffffc RESET */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h new file mode 100644 index 000000000..802a4e950 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/mcu/rx72n/vecttbl.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.h +* Description : Has function prototypes for exception callback functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef VECTTBL_HEADER_INC +#define VECTTBL_HEADER_INC + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if defined(__GNUC__) +typedef struct st_ofsm_sec_ofs1 +{ + uint32_t __MDEreg; + uint32_t __OFS0reg; + uint32_t __OFS1reg; +} st_ofsm_sec_ofs1_t; + +typedef struct st_ofsm_sec_ofs6 +{ + uint32_t __OSIS1reg; + uint32_t __OSIS2reg; + uint32_t __OSIS3reg; + uint32_t __OSIS4reg; +} st_ofsm_sec_ofs6_t; +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* VECTTBL_HEADER_INC */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/platform.h new file mode 100644 index 000000000..43921b899 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/platform.h @@ -0,0 +1,224 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : platform.h +* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using +* is not listed below, please add your own or use the default 'User Board'. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.11.2011 1.00 First Release +* : 13.01.2012 1.10 Moved from having platform defined using macro definition, to having platform defined +* by choosing an include path. This makes this file simpler and cleans up the issue +* where HEW shows all header files for all platforms under 'Dependencies'. +* : 14.02.2012 1.20 Added RX210 BSP. +* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding +* locking.c and locking.h in board folders. Also, r_bsp can now be configured through +* r_bsp_config.h. +* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using +* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort +* to remove any extra files that the user would need to touch. Removed the flash_options.c +* file and put its contents in vecttbl.c. +* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT +* macro options in r_bsp_config.h. Added some extra code to handle exceptions in +* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks. +* : 09.08.2012 1.60 Added IO_LIB_ENABLE macro to r_bsp_config_reference.h. +* : 14.11.2012 1.70 Added RSKRX62G, RSKRX63T, and RSKRX111 support. +* : 28.11.2012 2.00 Updated to be compliant with v1.00 r_bsp specification. +* : 21.01.2013 2.10 Added RSKRX63T_144PIN support. +* : 10.05.2013 2.20 Added new packages and memory variants to RX210. All iodefine.h files have been updated +* to latest revisions. On reset, all MCUs will now initialize non-bonded out pins to +* reduce current draw. r_bsp_common.c and .h files were added to support functionality +* common to all BSPs. cpu.c and cpu.h files were added to all MCU groups to support +* CPU functions such as enabling/disabling interrupts, setting the IPL, and controlling +* register protection. mcu_init.c and mcu_init.h were add to all MCU groups to support +* initialization functions that are common to a MCU group such as non-bonded pin init. +* Choosing MCU endian has been removed from r_bsp_config.h and is now automatically +* set based on compiler macros. RX-C, IAR, and GCC endian macros are supported. RX210 +* now has support for choosing HOCO frequency. All r_bsp_config.h files now have macro +* for defining Vcc which is needed by some FIT modules. IRQ locks were added for all +* MCU groups. BSP_PACKAGE_PINS macro was added to mcu_info.h which defines number of pins +* for the currently chosen package. RX111 and RX210 now have the option of using the +* r_cgc_rx module for clock management based on BSP_CFG_USE_CGC_MODULE macro in +* r_bsp_config.h. +* : 31.05.2013 2.21 Added latest iodefine.h files for RX111 (v0.9a), RX630 (v1,50a), and RX63N (v1.60). Also +* added 'doc' folder to root of r_bsp. Currently the only the document in there is the +* preliminary version of the r_bsp User's Manual. For RX210, the ability to choose chip +* version C was added to its r_bsp_config.h file. +* : 01.07.2013 2.30 Removed RSPI pin setup in RSKRX111 which caused excess current draw in low power +* modes. Changed FIT_NO_PTR and FIT_NO_FUNC macros to 0x10000000 which works for all +* RX MCUs. Added ability for user to use 1 or 2 stacks for RX MCUs. Added new interrupt +* handling features which allows for interrupt callback registration. This feature allows +* all interrupts that map to the NMI vector to be used and replaces the static callback +* definitions that were in r_bsp_config.h previously. RX111 information has been updated +* according to v1.00 HW manual. This includes support for 40-pin packages. All compiler +* messages and warnings for lowsrc.c have been cleaned up. Non-existent port init has +* been moved to end of hardware_setup() to ensure user does not overwrite the settings. +* Added blank lines between clock macros in r_bsp_config.h to aid in readability. Added +* '(void *)' cast to FIT_NO_PTR to remove compiler warnings. All r_bsp.h files now include +* r_bsp_common.h which has common includes (stdint.h, stddef.h, & stdbool.h) and uses +* r_typedefs.h when C99 is not available. RX111 and RX210 MCUs have the option of using +* the r_cgc_rx module for clock management. When this is used, the clock info macros in +* mcu_info.h (e.g. BSP_ICLK_HZ) will now make calls to the r_cgc_rx module instead of +* providing static info. For debug console output, lowlvl.src was replaced by lowlvl.c +* (assembly converted to C source). +* : 10.02.2014 2.40 Added support for the RSKRX110, RPBRX111, RSKRX220, and HSBRX21AP. Made sure +* in hwsetup.c files that the PMR registers are set after the MPC registers. Replaced +* use of stdint.h, stdbool.h, and stddef.h with platform.h to remove compiler warnings. +* Removed includes for machine.h since it is compiler specific and replaced with +* platform.h. Fixed bug in resetprg.c for many boards where LOCO was not being turned off +* when it was not being used. RX100 code now uses the oscillation stabilization flags +* instead of SW delay loop. Changed size_t to unsigned long. Defined PRC2 in register +* protection section for RX111. Fixed bug in non-existent pin setup for RX111. No +* platform is chosen by default (used to be the RSKRX111). This makes it easier to +* understand the problem when you build a new project and have not selected your platform. +* : 24.03.2014 2.50 Added support for the RSKRX64M. +* : 16.06.2014 2.60 Added version control for r_bsp_config.h Two user callback functions may now be +* configured allowing callbacks from PowerON_Reset_PC() for warm start detection. +* Stdio charget() and charput() functions may now be redirected to user defined functions. +* Added support for RSKRX631 and RDKRX631. +* : 05.08.2014 2.70 Added support for RSKRX113. +* : 29.09.2014 2.80 Added support for RSKRX71M. +* : 22.12.2014 2.90 Added support for RSKRX231. +* : 30.09.2015 3.00 Added support for RSSKRX23T and RSKRX23T. +* : 30.09.2015 3.01 Fix for RSKRX231 and RSKRX23T(RSSKRX23T). +* : 01.12.2015 3.10 Added support for RSKRX130. +* : 01.02.2016 3.20 Added support for RSKRX24T. +* : 29.02.2016 3.30 Added support for RSKRX230. +* : 01.10.2016 3.40 Added support for RSKRX65N. +* : 22.08.2016 3.50 Added support for RSKRX24U. +* : 15.05.2017 3.60 Added support for RSKRX65N-2MB. +* Added support for GENERIC_RX65N. +* Added support for RSKRX130-512KB. +* : 01.11.2017 3.70 Added support for GENERIC_RX130. +* Added support for GENERIC_RX110. +* Added support for GENERIC_RX111. +* Added support for GENERIC_RX113. +* Added support for GENERIC_RX230. +* Added support for GENERIC_RX231. +* Added support for GENERIC_RX23T. +* Added support for GENERIC_RX24T. +* Added support for GENERIC_RX24U. +* Added support for GENERIC_RX64M. +* Added support for GENERIC_RX71M. +* Added support for ENVISIONRX65N. +* : 01.11.2017 3.71 Corrected typo in Rev3.70 BSP. +* : 01.07.2018 3.80 Added support for TARGETBOARDRX65N. +* Added support for TARGETBOARDRX231. +* Added support for TARGETBOARDRX130. +* : 27.07.2018 3.90 Added support for GENERIC_RX66T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSKRX64M, RSKRX65N, RSKRX65N_2MB, TARGETBOARDRX65N, ENVISIONRX65N, RSKRX71M, +* RSKRX230, RSKRX231, TARGETBOARDRX231, RSKRX110, RSKRX111, RPBRX111, RSKRX113, +* RSKRX130, RSKRX130_512KB, and TARGETBOARDRX130 +* : 31.10.2018 4.00 Added support for GENERIC_RX72T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSSKRX23T, RSKRX23T, RSKRX24T, and RSKRX24U +* : 28.02.2019 5.00 Deleted the below board folders. +* - RSKRX610, RSKRX62N, RSKRX62T, RSKRX62G, RDKRX62N, RSKRX630, RSKRX631, RSKRX63T_64PIN, +* RSKRX63T_144PIN, RDKRX63N, RDKRX631, RSKRX210, HSBRX21AP and RSKRX220 +* : 29.03.2019 5.10 Added support for GENERIC_RX23W. +* : 08.04.2019 5.20 Added support for GENERIC_RX72M. +* : 26.07.2019 5.30 Added support for GENERIC_RX13T. +* : 31.07.2019 5.40 Added support for GENERIC_RX23E-A. +* : 08.10.2019 5.50 Added support for GENERIC_RX72N, and GENERIC_RX66N. +* Deleted the board folders of RSKRX63N. +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef PLATFORM_H +#define PLATFORM_H + +/*********************************************************************************************************************** +DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING. +***********************************************************************************************************************/ +/* GENERIC_RX64M */ +//#include "./board/generic_rx64m/r_bsp.h" + +/* GENERIC_RX65N */ +//#include "./board/generic_rx65n/r_bsp.h" + +/* GENERIC_RX66N */ +//#include "./board/generic_rx66n/r_bsp.h" + +/* GENERIC_RX66T */ +//#include "./board/generic_rx66t/r_bsp.h" + +/* GENERIC_RX71M */ +//#include "./board/generic_rx71m/r_bsp.h" + +/* GENERIC_RX72M */ +//#include "./board/generic_rx72m/r_bsp.h" + +/* GENERIC_RX72N */ +#include "./board/generic_rx72n/r_bsp.h" + +/* GENERIC_RX72T */ +//#include "./board/generic_rx72t/r_bsp.h" + +/* GENERIC_RX230 */ +//#include "./board/generic_rx230/r_bsp.h" + +/* GENERIC_RX231 */ +//#include "./board/generic_rx231/r_bsp.h" + +/* GENERIC_RX23E-A */ +//#include "./board/generic_rx23e-a/r_bsp.h" + +/* GENERIC_RX23T */ +//#include "./board/generic_rx23t/r_bsp.h" + +/* GENERIC_RX23W */ +//#include "./board/generic_rx23w/r_bsp.h" + +/* GENERIC_RX24T */ +//#include "./board/generic_rx24t/r_bsp.h" + +/* GENERIC_RX24U */ +//#include "./board/generic_rx24u/r_bsp.h" + +/* GENERIC_RX111 */ +//#include "./board/generic_rx111/r_bsp.h" + +/* GENERIC_RX110 */ +//#include "./board/generic_rx110/r_bsp.h" + +/* GENERIC_RX113 */ +//#include "./board/generic_rx113/r_bsp.h" + +/* GENERIC_RX130 */ +//#include "./board/generic_rx130/r_bsp.h" + +/* GENERIC_RX13T */ +//#include "./board/generic_rx13t/r_bsp.h" + +/* User Board - Define your own board here. */ +//#include "./board/user/r_bsp.h" + +/*********************************************************************************************************************** +MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT +***********************************************************************************************************************/ +#ifndef PLATFORM_DEFINED +#error "Error - No platform defined in platform.h!" +#endif + +#endif /* PLATFORM_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/readme.txt new file mode 100644 index 000000000..25aa74e4c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_bsp/readme.txt @@ -0,0 +1,57 @@ +r_bsp Package +============= + +Overview +-------- +The r_bsp package provides a foundation for code to be built on top of. It provides startup code, iodefines, and MCU +information for different boards. There are 2 folders that make up the r_bsp package. The 'mcu' folder contains files +that are common to a MCU group. These files provide functionality such as easy register access, CPU functions, +and a file named 'mcu_info.h' for each MCU group. The 'mcu_info.h' file has information about the MCU on the board +and is configured based on the information given in r_bsp_config.h. The information in 'mcu_info.h' is used to help +configure Renesas middleware that uses the r_bsp package. The 'board' folder has a folder with startup code for each +supported board. Which MCU and board is chosen is decided by the settings in 'platform.h'. The user can choose which +board they are using by uncommenting the include path that applies to their board. For example, if you are using the +RSK+RX62N then you would uncomment the #include "./board/rskrx62n/r_bsp.h" include path. Users are encouraged to add +their own boards to the 'board' directory. BSPs are configured by using the r_bsp_config.h file. Each board will have a +reference configuration file named r_bsp_config_reference.h. The user should copy this file to their project, rename it +to r_bsp_config.h, and use the options inside the file to configure the BSP for their project. + + +Features +-------- +* Provides foundation to build code on top of. +* Provides MCU startup code. +* Provides SFR access through iodefine.h +* Stores details of MCU in 'mcu_info.h' to help configure Renesas middleware. +* Easily configure BSP through r_bsp_config.h. +* Choose MCU easily by inputting part number details in r_bsp_config.h. +* Provides callbacks for MCU exceptions and the bus error interrupt. +* Supports initializing non-bonded out pins to reduce power +* Provides API to control CPU functions such as setting the IPL, enabling/disabling interrupts, and controlling + register protection + + + +File Structure +-------------- +r_bsp +| platform.h +| readme.txt +| ++---board +| +---generic_rx111 +| | : +| : +| \---user +| ++---doc +| +---en +| r01an1685ej{VERSION_NUMBER}-rx-bsp.pdf +| +---ja +| r01an1685jj{VERSION_NUMBER}-rx-bsp.pdf +| +\---mcu + +---all + +---rx111 + | : + : \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/r_byteq_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/r_byteq_if.h new file mode 100644 index 000000000..1bd93830d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/r_byteq_if.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_if.h +* Description : Functions for using byte queues/circular buffers +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 01.22.2015 1.30 Updated version to 1.30 for RX71M release +* : 04.04.2015 1.40 Updated version to 1.40 for RX231 release +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Updated version to 1.60 for correspondence to RX Family +* : 01.06.2018 1.70 Updated version to 1.70 +* : 03.12.2018 1.71 Updated version to 1.71 for update of xml file. +* : 07.02.2019 1.80 Updated version to 1.80. +***********************************************************************************************************************/ + +#ifndef BYTEQ_IF_H +#define BYTEQ_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Version Number of API. */ +#define BYTEQ_VERSION_MAJOR (1) +#define BYTEQ_VERSION_MINOR (80) + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef enum e_byteq_err // BYTEQ API error codes +{ + BYTEQ_SUCCESS = 0, + BYTEQ_ERR_NULL_PTR, // received null ptr; missing required argument + BYTEQ_ERR_INVALID_ARG, // argument is not valid for parameter + BYTEQ_ERR_MALLOC_FAIL, // can't allocate memory for ctrl block; increase heap + BYTEQ_ERR_NO_MORE_CTRL_BLKS, // no more control blocks, increase BYTEQ_MAX_CTRL_BLKS + BYTEQ_ERR_QUEUE_FULL, // queue full; cannot add another byte + BYTEQ_ERR_QUEUE_EMPTY // queue empty; no byte to fetch +} byteq_err_t; + + +/* BYTE QUEUE HANDLE */ + +typedef struct st_byteq_ctrl * byteq_hdl_t; + + +/***************************************************************************** +Public Functions +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl); + +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte); + +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte); + +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +uint32_t R_BYTEQ_GetVersion(void); + + +#endif /* BYTEQ_IF_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/readme.txt new file mode 100644 index 000000000..1173711e1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/readme.txt @@ -0,0 +1,48 @@ + +r_byteq +======= + +Overview +-------------------------------------------------------------------------------- +The r_byteq module is a collection of circular buffer routines for byte data. +The application passes a buffer to be used as a circular buffer to the Open() +function which assigns a queue control block to it to handle indexing. The +Open() function returns a handle which is then used as a queue/buffer id for all +other API functions. These functions include routines for adding and removing +data from a queue, inspecting the amount of data in a queue, and the ability to +flush a queue. + +The queue control blocks can be allocated at compile time or dynamically at run +time. A configuration option for this exists in "r_config\r_byteq_config.h". +An original copy of the configuration file is stored in "r_byteq\ref\ +r_byteq_config_reference.h". + + +Features +-------- +* Statically or dynamically allocated queue control blocks. +* Number of queues limited only by the amount of RAM available on the mcu. + +File Structure +-------------- +r_byteq +| readme.txt +| r_byteq_if.h +| ++---doc +| +---en +| | r01an1683ej{VERSION_NUMBER}-rx.pdf +| | +| +---ja +| r01an1683jj{VERSION_NUMBER}-rx.pdf +| ++---ref +| r_byteq_config_reference.h +| ++---src + r_byteq.c + r_byteq_private.h + +r_config + r_byteq_config.h + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h new file mode 100644 index 000000000..40675c419 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/ref/r_byteq_config_reference.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + + +#endif /* BYTEQ_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/src/r_byteq.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/src/r_byteq.c new file mode 100644 index 000000000..816a88be8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/src/r_byteq.c @@ -0,0 +1,422 @@ +/***************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +******************************************************************************/ +/***************************************************************************** +* File Name : r_byteq.c +* Description : Functions for using byte queues/circular buffers. +****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Fixed the initial setting process in the R_LONGQ_Open function. +* Fixed a program according to the Renesas coding rules. +* : 01.06.2018 1.70 Added the comment to while statement. +* : 07.02.2019 1.80 Deleted the inline expansion of the R_BYTEQ_GetVersion function. +******************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +/* Used functions of malloc() and the free() */ +#include + +/* Used the common type */ +#include "platform.h" + +/* Defines for BYTEQ support */ +#include "r_byteq_private.h" +#include "r_byteq_if.h" +#include "r_byteq_config.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK ALLOCATIONS */ + +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) +static byteq_ctrl_t g_qcb[BYTEQ_CFG_MAX_CTRL_BLKS]; +#endif + + +/***************************************************************************** +* Function Name: R_BYTEQ_Open +* Description : Allocates or assigns a queue control block for the buffer +* pointed to by p_buf (see BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS in +* config.h). Initializes the queue to an empty state and +* provides a Handle to its control structure in p_hdl which is +* then used as a queue ID for the other API functions. +* Arguments : p_buf - +* Pointer to byte buffer. +* size - +* Buffer size in bytes. +* p_hdl - +* Pointer to a handle for queue (value set here) +* Return Value : SCI_SUCCESS - +* queue initialized successfully +* BYTEQ_ERR_NULL_PTR +* received null ptr; missing required argument +* BYTEQ_ERR_INVALID_ARG +* argument is not valid for parameter +* BYTEQ_ERR_MALLOC_FAIL +* can't allocate memory for ctrl block; increase heap +* BYTEQ_ERR_NO_MORE_CTRL_BLKS +* no more control blocks, increase BYTEQ_CFG_MAX_CTRL_BLKS +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl) +{ + byteq_ctrl_t *p_qcb = 0; +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) + uint32_t i; + static bool qcb_init = false; +#endif + + /* CHECK ARGUMENTS */ + +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == p_hdl) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } + if (NULL == p_buf) + { + return BYTEQ_ERR_NULL_PTR; // return if no buffer pointer + } + if (size < 2) + { + return BYTEQ_ERR_INVALID_ARG; // return insufficient buffer size + } +#endif + + /* GET QUEUE CONTROL BLOCK */ + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + + /* allocate memory for a QCB */ + p_qcb = (byteq_ctrl_t *)malloc(sizeof(byteq_ctrl_t)); + if (NULL == p_qcb) + { + return BYTEQ_ERR_MALLOC_FAIL; + } +#else + /* if first Open call, mark all QCBs as being available */ + if (false == qcb_init) + { + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + g_qcb[i].buffer = NULL; + } + qcb_init = true; + } + + /* locate first available QCB */ + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + if (NULL == g_qcb[i].buffer) + { + p_qcb = &g_qcb[i]; + break; + } + } + + /* return error if none available */ + if (BYTEQ_CFG_MAX_CTRL_BLKS == i) + { + return BYTEQ_ERR_NO_MORE_CTRL_BLKS; + } +#endif + + + /* INITIALIZE QCB FIELDS */ + + p_qcb->buffer = p_buf; + p_qcb->size = size; + p_qcb->count = 0; + p_qcb->in_index = 0; + p_qcb->out_index = 0; + + + /* SET HANDLE */ + + *p_hdl = p_qcb; + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Put +* Description : This function adds a byte of data to the queue. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* byte - +* Byte to add to queue. +* Return Value : BYTEQ_SUCCESS - +* Successful; byte sent or queued for transmit +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_QUEUE_FULL - +* Queue full; cannot add byte to queue. +******************************************************************************/ +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } +#endif + + if (hdl->count >= hdl->size) + { + return BYTEQ_ERR_QUEUE_FULL; // return if queue is full + } + + /* load byte into queue */ + hdl->buffer[hdl->in_index++] = byte; // add byte + if (hdl->in_index >= hdl->size) // adjust index + { + hdl->in_index = 0; + } + hdl->count++; // adjust count + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Get +* Description : This function removes a byte of data from the queue. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* p_byte - +* Pointer to load byte to. +* Return Value : BYTEQ_SUCCESS - +* Successful; byte sent or queued for transmit +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_byte is NULL +* BYTEQ_ERR_QUEUE_EMPTY - +* Queue empty; no data available to fetch +******************************************************************************/ +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } + if (NULL == p_byte) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + if (0 == hdl->count) + { + return BYTEQ_ERR_QUEUE_EMPTY; // return if queue empty + } + + *p_byte = hdl->buffer[hdl->out_index++]; // get byte + if (hdl->out_index >= hdl->size) // adjust index + { + hdl->out_index = 0; + } + hdl->count--; // adjust count + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Flush +* Description : This function resets a queue to an empty state. +* +* NOTE: This function does not disable/enable interrupts. If the queue is +* accessed from both the interrupt and application level, the app must +* disable/enable interrupts before/after calling this routine. +* +* Arguments : hdl - +* Handle for queue. +* Return Value : BYTEQ_SUCCESS - +* Successful; queue is reset to en ampty state +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + + /* RESET QUEUE */ + + hdl->in_index = 0; + hdl->out_index = 0; + hdl->count = 0; + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Used +* Description : This function provides the number of data bytes in the queue. +* Arguments : hdl - +* Handle for queue. +* p_cnt - +* Pointer to load queue data count to. +* Return Value : BYTEQ_SUCCESS - +* Successful; *p_cnt loaded with number of bytes in queue +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_cnt is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + *p_cnt = hdl->count; + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Unused +* Description : This function provides the number of data bytes available +* for storage in the queue. +* Arguments : hdl - +* Handle for queue. +* p_cnt - +* Pointer to load queue unused byte count to. +* Return Value : BYTEQ_SUCCESS - +* Successful; *p_cnt loaded with number of bytes available in +* queue +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL +* BYTEQ_ERR_INVALID_ARG - +* p_cnt is NULL +******************************************************************************/ +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + *p_cnt = (uint16_t) (hdl->size - hdl->count); + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_Close +* Description : If the control block associated with this Handle was allocated +* dynamically at run time (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS set to 1 +* in config.h), then that memory is free()d by this function. If +* the control block was statically allocated at compile time +* (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS set to 0 in config.h), then this +* function marks the control block as available for use by another +* buffer. Nothing is done to the contents of the buffer referenced +* by this Handle. +* Arguments : hdl - +* handle for queue +* Return Value : BYTEQ_SUCCESS - +* Successful; control block freed +* BYTEQ_ERR_NULL_PTR - +* hdl is NULL. +******************************************************************************/ +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + free(hdl); // free QCB memory +#else + hdl->buffer = NULL; // mark QCB as free +#endif + + return BYTEQ_SUCCESS; +} + + +/***************************************************************************** +* Function Name: R_BYTEQ_GetVersion +* Description : Returns the version of this module. The version number is +* encoded such that the top two bytes are the major version +* number and the bottom two bytes are the minor version number. +* Arguments : none +* Return Value : version number +******************************************************************************/ +uint32_t R_BYTEQ_GetVersion(void) +{ + + uint32_t const version = (BYTEQ_VERSION_MAJOR << 16) | BYTEQ_VERSION_MINOR; + return version; +} diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/src/r_byteq_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/src/r_byteq_private.h new file mode 100644 index 000000000..8f14acced --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_byteq/src/r_byteq_private.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_private.h +* Description : Definitions internal to byte queue module +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.0 Initial Release +* : 30.09.2015 1.50 Added dependency to BSP +***********************************************************************************************************************/ + +#ifndef BYTEQ_PRIVATE_H +#define BYTEQ_PRIVATE_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK */ + +typedef struct st_byteq_ctrl // Byte Queue Control Block (for handle) +{ + uint8_t *buffer; // pointer to buffer + uint16_t size; // buffer size + uint16_t count; // number data bytes in queue + uint16_t in_index; // index used by Put function to add data + uint16_t out_index; // index used by Get function to remove data +} byteq_ctrl_t; + + +#endif /* BYTEQ_PRIVATE_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_config.h new file mode 100644 index 000000000..5308bc5ae --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_config.h @@ -0,0 +1,774 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX72N +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release. +***********************************************************************************************************************/ +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/* Include for various workarounds. */ +#include "smc_workaround.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX72N. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 57 2N N D D BD + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED = Encryption module included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FC = 0x0 = LFQFP/176/0.50 + BG = 0x1 = LFBGA/176/0.80 + BD = 0x2 = LFBGA/224/0.80 + FB = 0x3 = LFQFP/144/0.50 + LK = 0x4 = TFLGA/145/0.50 + FP = 0x5 = LFQFP/100/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x3) /* Generated value. Do not edit this manually */ + +/* Whether Encryption is included or not. + Character(s) = Value for macro = Description + D = 0xD = Encryption module not included + H = 0x11 = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0x11) /* Generated value. Do not edit this manually */ + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + D = 0xD = 2MB/1MB/32KB + N = 0x17 = 4MB/1MB/32KB +NOTE: The RAM areas are not contiguous.It is separated by 512 KB each. +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x17) /* Generated value. Do not edit this manually */ + +/* Group name. + Character(s) = Value for macro = Description + 2N = 0x0 = RX72N Group +*/ +#define BSP_CFG_MCU_PART_GROUP (0x0) /* Generated value. Do not edit this manually */ + +/* Series name. + Character(s) = Value for macro = Description + 57 = 0x0 = RX700 Series +*/ +#define BSP_CFG_MCU_PART_SERIES (0x0) /* Generated value. Do not edit this manually */ + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) /* Generated value. Do not edit this manually */ + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (0) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x0) +#endif + +/* Interrupt Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x0) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFE7F5D50. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFE7F5D54. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFE7F5D58. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFE7F5D5C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit (default) +*/ +#define BSP_CFG_CLOCK_SOURCE (4) /* Generated value. Do not edit this manually */ + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator (default) + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (0) /* Generated value. Do not edit this manually */ + +/* USB Clock source select (UPLLSEL). Choose which clock source to input to the USB circuit. + 0 = System Clock (PLL Circuit/No division) (This is not available.) + 1 = USB PLL Circuit (This is not available.) + 2 = PLL Circuit (UDIVCLK) (default) + 3 = PPLL Circuit (PPLLDIVCLK) +*/ +#define BSP_CFG_USB_CLOCK_SOURCE (2) /* Generated value. Do not edit this manually */ + +/* Ethernet-PHY clock source (OUTCKSEL). Choose which clock source to input to the Ethernet PHY LSI. + Available clock sources: + 0 = PLL circuit + 1 = PPLL circuit (default) + 2 = Ethernet-PHY not use +*/ +#define BSP_CFG_PHY_CLOCK_SOURCE (1) /* Generated value. Do not edit this manually */ + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 6 = PPLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE (1) /* Generated value. Do not edit this manually */ + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE (0) /* Generated value. Do not edit this manually */ + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP (0) /* Generated value. Do not edit this manually */ + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 60MHz, PCLKD is 60MHz, FCLK is 60MHz, BCLK is 80MHz, + USB Clock is 48MHz, ESC Clock is 100MHz, Ether-Phy Clock is 25MHz then the settings would be: + + BSP_CFG_XTAL_HZ = 24000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 10.0 (24MHz x 10.0 = 240MHz) + BSP_CFG_PPLL_DIV = 3 (divide by 3) + BSP_CFG_PPLL_MUL = 25.0 (8MHz x 25.0 = 200MHz) + BSP_CFG_PPLCK_DIV = 2 (divide by 2) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 240MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 4 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 60MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_BCK_DIV = 3 : External Bus Clock (BCK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_BCK_DIV) = 80MHz + BSP_CFG_UCK_DIV = 5 : USB Clock (UCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_UCK_DIV) = 48MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (16000000) /* Generated value. Do not edit this manually */ + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#define BSP_CFG_HOCO_FREQUENCY (2) /* Generated value. Do not edit this manually */ + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC (1) /* Generated value. Do not edit this manually */ + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (1) /* Generated value. Do not edit this manually */ + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL (12.0) /* Generated value. Do not edit this manually */ + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (1) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (2) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (4) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (4) /* Generated value. Do not edit this manually */ + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (4) /* Generated value. Do not edit this manually */ + +/* External Bus Clock Divider (BCLK). + Available divisors = /1 (no division), /2, /3, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_BCK_DIV (3) /* Generated value. Do not edit this manually */ + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (4) /* Generated value. Do not edit this manually */ + +/* USB Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_UCK_DIV (2) /* Generated value. Do not edit this manually */ + +/* PPLL Input Frequency Division Ratio Select (PPLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PPLL_DIV (1) /* Generated value. Do not edit this manually */ + +/* PPLL Frequency Multiplication Factor Select (PPLSTC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PPLL_MUL (10.0) /* Generated value. Do not edit this manually */ + +/* PPLL Clock Divider Select. + Available divisors = /2, /3, /4, /5 +*/ +#define BSP_CFG_PPLCK_DIV (2) /* Generated value. Do not edit this manually */ + +/* Configure BCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency, 2= BCK/2 frequency +*/ +#define BSP_CFG_BCLK_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* Configure SDCLK output pin (only effective when external bus enabled) + Values 0=no output, 1 = BCK frequency + NOTE: The definition is invalid. +*/ +#define BSP_CFG_SDCLK_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV (0) /* Generated value. Do not edit this manually */ + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT (0) /* Generated value. Do not edit this manually */ + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) /* Generated value. Do not edit this manually */ + +/* Sub-Clock Oscillator Wait Time (SOSCWTCR). + The value of SOSCWTCR register required for correspondence with the expected time to secure settling of oscillation + by the sub-clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_SOSC_WAIT_TIME > (tSUBOSC * (fLOCO_max) + 16)/16384 + (tSUBOSC: sub-clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tSUBOSC is 2 s and fLOCO is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_SOSC_WAIT_TIME > (2 s * (264 kHz) +16)/16384 = 32.22, so set the BSP_CFG_SOSC_WAIT_TIME bits to 33(21h). +*/ +#define BSP_CFG_SOSC_WAIT_TIME (0x21) /* Generated value. Do not edit this manually */ + +/* ROM Cache Enable Register (ROMCE). + 0 = ROM cache operation disabled. + 1 = ROM cache operation enabled. +*/ +#define BSP_CFG_ROM_CACHE_ENABLE (1) + +/* Configure non-cacheable area 0 of the ROM cache function. + 0 = Non-cacheable area 0 settings disabled. + 1 = Non-cacheable area 0 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ENABLE (0) + +/* Specifies the start address of non-cacheable area 0. + Selects the start address of non-cacheable area 0. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 0. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of IF cache disabled. + 1 = Non-cacheable area 0 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of OA cache disabled. + 1 = Non-cacheable area 0 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 0. + 0 = Non-cacheable area 0 setting of DM cache disabled. + 1 = Non-cacheable area 0 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA0_DM_ENABLE (1) + +/* Configure non-cacheable area 1 of the ROM cache function. + 0 = Non-cacheable area 1 settings disabled. + 1 = Non-cacheable area 1 settings enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ENABLE (0) + +/* Specifies the start address of non-cacheable area 1. + Selects the start address of non-cacheable area 1. + The upper 10 bits are fixed at 1. The lower 4 bits are fixed at 0. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_ADDR (0xFFE00000) + +/* Configures the size of non-cacheable area 1. + Selects the size of non-cacheable area 0 in byte units from among the following: + 0x0 = 16 bytes, 0xA = 16K bytes, + 0x1 = 32 bytes, 0xB = 32K bytes, + 0x2 = 64 bytes, 0xC = 64K bytes, + 0x3 = 128 bytes, 0xD = 128K bytes, + 0x4 = 256 bytes, 0xE = 256K bytes, + 0x5 = 512 bytes, 0xF = 512K bytes, + 0x6 = 1K bytes, 0x10= 1M bytes, + 0x7 = 2K bytes, 0x11= 2M bytes, + 0x8 = 4K bytes, + 0x9 = 8K bytes +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_SIZE (0x0) + +/* Specifies the IF non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of IF cache disabled. + 1 = Non-cacheable area 1 setting of IF cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_IF_ENABLE (1) + +/* Specifies the OA non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of OA cache disabled. + 1 = Non-cacheable area 1 setting of OA cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_OA_ENABLE (1) + +/* Specifies the DM non-cacheable area enable bit setting of non-cacheable area 1. + 0 = Non-cacheable area 1 setting of DM cache disabled. + 1 = Non-cacheable area 1 setting of DM cache enabled. +*/ +#define BSP_CFG_NONCACHEABLE_AREA1_DM_ENABLE (1) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (1=2.94v, 2=2.87v, 3=2.80v) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 78 and 79 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFDE 0000h to + FFDE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEFF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b26] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF C000h to FFFF DFFFh are used as the boot area + - 1: FFFF E000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* The ROM code protection register is a function to prohibit reading from or programming to the flash memory + when the flash programmer is used during off-board programming. + ROMCODE - ROM Code Protection Register + b31:b0 ROM Code - 0000 0000h: ROM code protection enabled (ROM code protection 1). + 0000 0001h: ROM code protection enabled (ROM code protection 2). + Other than above: ROM code protection disabled. + Note: The ROMCODE register should be set in 32-bit units. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_ROMCODE_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFC00000h to FFDFFFFFh and bank 0 from FFE00000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFE00000h to FFFFFFFFh and bank 0 from FFC00000h to FFDFFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. +*/ +#if !defined(BSP_CFG_RTOS_USED) || (BSP_CFG_RTOS_USED == 0) +#if defined(BSP_CFG_RTOS_USED) +#undef BSP_CFG_RTOS_USED +#endif +#define BSP_CFG_RTOS_USED (1) /* Generated value. Do not edit this manually */ +#endif +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* The extended bus master has five transfer sources: EDMAC, GLCDC-GRA1 (GLCDC graphics 1 data read), GLCDCGRA2 (GLCDC + graphics 2 data read), DRW2D-TX (DRW2D texture data read), and DRW2D-FB (DRW2D frame buffer data read write and + display list data read). + The default priority order in bsp is below + GLCDC-GRA1 > GLCDC-GRA2 > DRW2D-TX > DRW2D-FB > EDMAC. + Priority can be changed with this macro. + + Extended Bus Master Priority setting + 0 = GLCDC graphics 1 data read + 1 = DRW2D texture data read + 2 = DRW2D frame buffer data read write and display list data read + 3 = GLCDC graphics 2 data read + 4 = EDMAC + + Note : Settings other than above are prohibited. + Duplicate priority settings can not be made. +*/ +#define BSP_CFG_EBMAPCR_1ST_PRIORITY (0) /* Extended Bus Master 1st Priority Selection */ +#define BSP_CFG_EBMAPCR_2ND_PRIORITY (3) /* Extended Bus Master 2nd Priority Selection */ +#define BSP_CFG_EBMAPCR_3RD_PRIORITY (1) /* Extended Bus Master 3rd Priority Selection */ +#define BSP_CFG_EBMAPCR_4TH_PRIORITY (2) /* Extended Bus Master 4th Priority Selection */ +#define BSP_CFG_EBMAPCR_5TH_PRIORITY (4) /* Extended Bus Master 5th Priority Selection */ + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) /* Generated value. Do not edit this manually */ + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (1) /* Generated value. Do not edit this manually */ + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (0) +#define BSP_CFG_SWINT_UNIT2_ENABLE (1) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_config_readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_config_readme.txt new file mode 100644 index 000000000..6a9002cf4 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_config_readme.txt @@ -0,0 +1,12 @@ +FIT r_config folder +------------------- +The purpose of the r_config folder is to provide one place where the user can store all of their FIT configuration +files. Putting the files in one place makes them easy to find, backup, and put in a version control system. + +FIT Modules are distributed with a reference configuration file. These files end with '_reference.h'. For example, +the reference configuration file for the r_bsp is named r_bsp_config_reference.h. Reference configuration files are +provided so that the user always has a known-good configuration to revert to. When adding a FIT Module to a project the +user should copy this reference configuration file to this folder and remove '_reference' from the filename +(r_bsp_config_reference.h is renamed to r_bsp_config.h). For the r_bsp the reference configuration file can be found in +the 'board' folder for the currently chosen development board. For other FIT Modules the reference configuration file +can be found in the 'ref' folder of the FIT Module. diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_interrupt_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_interrupt_config.h new file mode 100644 index 000000000..189b6ef5d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_bsp_interrupt_config.h @@ -0,0 +1,222 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupt_config.h +* Description : This module maps Interrupt A & B interrupts. More information on how this is done is given below. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 31.05.2019 1.00 First Release +***********************************************************************************************************************/ +#ifndef R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE +#define R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* If you wish to use one of the interrupt below then set the appropriate configuration macro to the vector number you + * wish to use for that interrupt. For example, if you want to use the RTC carry interrupt (CUP) at vector 176 then you + * would do the following: + * + * #define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 + */ + +/* Interrupt B Sources. + * -Valid vector numbers are 128-207. + * -There are more vector slots for B sources than actual B sources. By default none of the CAN2 interrupts are + * mapped. + * -If using the 'TPU1, TGI1A' interrupt it must be vector 144 or 145. It is set to 144 by default. + * -If a peripheral interrupt is going to be used to wake up the MCU from All-Module Clock Stop Mode then it must be + * in a vector between 146 to 157. Peripheral interrupts that can do this are TMR interrupts and the 'USB0, USBI0' + * interrupt. By default the TMR interrupts are chosen since there are 12 of them and there are 12 slots. + */ +#define BSP_MAPPED_INT_CFG_B_VECT_CMT2_CMI2 128 +#define BSP_MAPPED_INT_CFG_B_VECT_CMT3_CMI3 129 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIA0 146 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_CMIB0 147 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR0_OVI0 148 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIA1 149 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_CMIB1 150 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR1_OVI1 151 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIA2 152 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_CMIB2 153 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR2_OVI2 154 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIA3 155 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_CMIB3 156 +#define BSP_MAPPED_INT_CFG_B_VECT_TMR3_OVI3 157 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0A 130 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0B 131 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0C 132 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TGI0D 133 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU0_TCI0V 134 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1A 144 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TGI1B 135 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1V 136 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU1_TCI1U 137 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2A 138 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TGI2B 139 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2V 140 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU2_TCI2U 141 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3A 142 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3B 143 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3C 145 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TGI3D 158 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU3_TCI3V 159 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4A 160 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TGI4B 161 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4V 162 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU4_TCI4U 163 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5A 164 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TGI5B 165 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5V 166 +#define BSP_MAPPED_INT_CFG_B_VECT_TPU5_TCI5U 167 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC0I0 168 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_IC1I0 169 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC0I0 170 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW0_OC1I0 171 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC0I1 172 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_IC1I1 173 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC0I1 174 +#define BSP_MAPPED_INT_CFG_B_VECT_CMTW1_OC1I1 175 +#define BSP_MAPPED_INT_CFG_B_VECT_RTC_CUP 176 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXF0 177 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXF0 178 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_RXM0 179 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN0_TXM0 180 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXF1 181 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXF1 182 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_RXM1 183 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN1_TXM1 184 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXF2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_RXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_CAN2_TXM2 +#define BSP_MAPPED_INT_CFG_B_VECT_USB0_USBI0 185 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12ADI0 186 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GBADI0 187 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC0_S12GCADI0 188 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12ADI1 189 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GBADI1 190 +#define BSP_MAPPED_INT_CFG_B_VECT_S12ADC1_S12GCADI1 191 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR18I 192 +#define BSP_MAPPED_INT_CFG_B_VECT_ELC_ELSR19I 193 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_PROC_BUSY 194 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_ROMOK 195 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_LONG_PLG 196 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_TEST_BUSY 197 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY0 198 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY1 199 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_WRRDY4 200 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY0 201 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_RDRDY1 202 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_WRRDY 203 +#define BSP_MAPPED_INT_CFG_B_VECT_TSIP_INTEGRATE_RDRDY 204 + +/* Interrupt A Sources. + * -Valid vector numbers are 208-255. + * -There are more A sources than A vector slots. By default none of the GPTW interrupts and the ESC interrupts are + * mapped. + * -If using the 'MTU1, TGI1A' interrupt it must be vector 208 or 209. It is set to 208 by default. + */ +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0 209 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0 210 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0 211 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0 212 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0 213 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0 214 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0 215 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1 208 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1 216 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1 217 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1 218 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2 219 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2 220 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2 221 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2 222 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3 223 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3 224 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3 225 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3 226 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3 227 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4 228 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4 229 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4 230 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4 231 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4 232 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5 233 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5 234 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5 235 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6 236 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6 237 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6 238 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6 239 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6 240 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7 241 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7 242 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7 243 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7 244 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7 245 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIA8 246 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIB8 247 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGIC8 248 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TGID8 249 +#define BSP_MAPPED_INT_CFG_A_VECT_MTU8_TCIV8 250 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3 +#define BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3 +#define BSP_MAPPED_INT_CFG_A_VECT_EPTPC_IPLS 251 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI0_PMGI0I 252 +#define BSP_MAPPED_INT_CFG_A_VECT_PMGI1_PMGI1I 253 + +#endif /* R_BSP_INTERRUPT_CONFIG_REF_HEADER_FILE */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_byteq_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_byteq_config.h new file mode 100644 index 000000000..512a28eb2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_byteq_config.h @@ -0,0 +1,62 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + + +#endif /* BYTEQ_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_dtc_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_dtc_rx_config.h new file mode 100644 index 000000000..c0ac30518 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_dtc_rx_config.h @@ -0,0 +1,97 @@ +/* Generated configuration header file - do not edit */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_config.h +* Description : Configures the DTC drivers +******************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.01.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Added #define DTC_CFG_USE_SEQUENCE_TRANSFER. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +*******************************************************************************/ +#ifndef DTC_RX_CONFIG_H +#define DTC_RX_CONFIG_H + +#define DTC_DISABLE (0) +#define DTC_ENABLE (1) +/* + * SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + * 0 : Compiles out parameter checking. + * 1 : Includes parameter checking. + * Default value is set to BSP_CFG_PARAM_CHECKING_ENABLE to + * re-use the system default setting. +*/ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* + * SPECIFY WHETHER THE DTCER REGISTERS WILL BE CLEARED IN R_DTC_OPEN() + * DTC_DISABLE : Do nothing. + * DTC_ENABLE : Clear all DTCER registers in R_DTC_Open(). +*/ +#define DTC_CFG_DISABLE_ALL_ACT_SOURCE (DTC_ENABLE) + +/* + * SPECIFY WHICH ADDRESS MODE IS SUPPORTED BY DTC + * DTC_DISABLE : Select the Full address mode. + * DTC_ENABLE : Select the Short address mode. +*/ +#define DTC_CFG_SHORT_ADDRESS_MODE (DTC_DISABLE) + +/* + * SPECIFY WHETHER THE TRANSFER DATA READ SKIP IS ENABLED + * DTC_DISABLE : Disable Transfer Data Read Skip. + * DTC_ENABLE : Enable Transfer Data Read Skip. +*/ +#define DTC_CFG_TRANSFER_DATA_READ_SKIP_EN (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE DMAC FIT MODULE IS USED WITH DTC FIT MODULE + * DTC_DISABLE : DMAC FIT module is not used with DTC FIT module. + * DTC_ENABLE : DMAC FIT module is used with DTC FIT module. +*/ +#define DTC_CFG_USE_DMAC_FIT_MODULE (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE SEQUENCE TRANSFER IS USED + * Also, set DTC_DISABLE to DTC_CFG_SHORT_ADDRESS_MODE. + * DTC_DISABLE : Not use sequence transfer. + * DTC_ENABLE : Use sequence transfer. +*/ +#define DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_ENABLE) + + +#endif /* DTC_RX_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_gpio_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_gpio_rx_config.h new file mode 100644 index 000000000..6966431d9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_gpio_rx_config.h @@ -0,0 +1,47 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_sci_rx_config.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_sci_rx_config.h new file mode 100644 index 000000000..dd172ccf9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_config/r_sci_rx_config.h @@ -0,0 +1,199 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (1) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * RX MCU supported channels + * + * CH# 110 111 113 130 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N RX23E-A + * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------- + * CH0 X Xa X X X X Xn X X X + * CH1 X X* X* Xu X X Xu Xu Xu X X Xs X X X X X X X Xu + * CH2 X X X Xu X X X + * CH3 X X Xs X X X + * CH4 X X Xn X X X + * CH5 X X X X X Xu X X X X X X X X X X X X X X + * CH6 X X X X X X X X Xn X X Xu X X X + * CH7 Xu Xu Xn X X X + * CH8 X Xa X X X X X X Xu X X X + * CH9 X Xa X X X Xs X X X X X + * CH10 X X X X + * CH11 X Xs X X X X X + * CH12 X X X X X X X X Xs X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (0) +#define SCI_CFG_CH1_INCLUDED (0) +#define SCI_CFG_CH2_INCLUDED (1) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (0) +#define SCI_CFG_CH6_INCLUDED (0) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (0) +#define SCI_CFG_CH9_INCLUDED (1) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (1) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY) 1 lowest, 15 highest */ + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj and SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +#endif /* SCI_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h new file mode 100644 index 000000000..5dee62a9f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/r_dtc_rx_if.h @@ -0,0 +1,297 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_if.h +* Description : Functions for DTC driver +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Moved struct dtc_transfer_data_cfg_t to r_dtc_rx_target_if.h +* : Added include pass of target mcu interface header file. +* : Added R_DTC_CreateSeq() function. +* : 31.01.2017 2.06 Modified r_dtc_rx.c. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 18.06.2019 3.01 Modified r_dtc_rx_private.h. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. + : 12.11.2019 3.21 Removed definitions for MTU5 in DTC activation interrupt source for RX23W. +* : 25.11.2019 3.30 Added support for RX13T. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +* : 31.03.2020 3.50 Added support for RX23E-A. +*******************************************************************************/ +#ifndef DTC_RX_IF_H +#define DTC_RX_IF_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Configuration for this package. */ +#include "r_dtc_rx_config.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define DTC_VERSION_MAJOR (3) +#define DTC_VERSION_MINOR (50) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +/* Configurable options for DTC Transfer mode */ +typedef enum e_dtc_transfer_mode +{ + DTC_TRANSFER_MODE_NORMAL = (0), /* = (0 << 6): Normal mode */ + DTC_TRANSFER_MODE_REPEAT = (1 << 6), /* Repeat mode */ + DTC_TRANSFER_MODE_BLOCK = (2 << 6) /* Block mode */ +} dtc_transfer_mode_t; + +/* Configurable options for DTC Data transfer size */ +typedef enum e_dtc_data_size +{ + DTC_DATA_SIZE_BYTE = (0), /* = (0 << 4): 8-bit (byte) data */ + DTC_DATA_SIZE_WORD = (1 << 4), /* 16-bit (word) data */ + DTC_DATA_SIZE_LWORD = (2 << 4) /* 32-bit (long word) data */ +} dtc_data_size_t; + +/* Configurable options for Source address addressing mode */ +typedef enum e_dtc_src_addr_mode +{ + DTC_SRC_ADDR_FIXED = (0), /* = (0 << 2): Source address is fixed. */ + DTC_SRC_ADDR_INCR = (2 << 2), /* Source address is incremented after each transfer. */ + DTC_SRC_ADDR_DECR = (3 << 2) /* Source address is decremented after each transfer. */ +} dtc_src_addr_mode_t; + +/* Configurable options for Chain transfer */ +typedef enum e_dtc_chain_transfer +{ + DTC_CHAIN_TRANSFER_DISABLE = (0), /* Disable Chain transfer. */ + DTC_CHAIN_TRANSFER_ENABLE = (1 << 7) /* Enable Chain transfer. */ +} dtc_chain_transfer_t; + +/* Configurable options for how chain transfer is performed. */ +typedef enum e_dtc_chain_transfer_mode +{ + DTC_CHAIN_TRANSFER_CONTINUOUSLY = (0), /* = (0 << 6): Chain transfer is performed continuously. */ + DTC_CHAIN_TRANSFER_NORMAL = (1 << 6) /* Chain transfer is performed only when the counter is changed to 0 or CRAH. */ +} dtc_chain_transfer_mode_t; + +/* Configurable options for Interrupt */ +typedef enum e_dtc_interrupt +{ + DTC_INTERRUPT_AFTER_ALL_COMPLETE = (0), /* Interrupt is generated when specified data transfer is completed. */ + DTC_INTERRUPT_PER_SINGLE_TRANSFER = (1 << 5) /* Interrupt is generated when each transfer time is completed. */ +} dtc_interrupt_t; + +/* Configurable options for Side to be repeat or block */ +typedef enum e_dtc_repeat_block_side +{ + DTC_REPEAT_BLOCK_DESTINATION = (0), /* = (0 << 4): Destination is repeat or block area. */ + DTC_REPEAT_BLOCK_SOURCE = (1 << 4) /* Source is repeat or block area. */ +} dtc_repeat_block_side_t; + +/* Configurable options for Destination address addressing mode */ +typedef enum e_dtc_dest_addr_mode +{ + DTC_DES_ADDR_FIXED = (1 << 2), /* Destination address is fixed. */ + DTC_DES_ADDR_INCR = (2 << 2), /* Destination address is incremented after each transfer. */ + DTC_DES_ADDR_DECR = (3 << 2) /* Destination address is decremented after each transfer. */ +} dtc_dest_addr_mode_t; + +/* Configurable options for Write-back Disable */ +typedef enum e_dtc_write_back +{ + DTC_WRITEBACK_ENABLE = (0), + DTC_WRITEBACK_DISABLE = (1) +} dtc_write_back_t; + +/* Configurable options for Sequence Transfer End */ +typedef enum e_dtc_sequence_end +{ + DTC_SEQUENCE_TRANSFER_CONTINUE = (0), + DTC_SEQUENCE_TRANSFER_END = (1) +} dtc_sequence_end_t; + +/* Configurable options for Index Table Reference */ +typedef enum e_dtc_refer_index_table +{ + DTC_REFER_INDEX_TABLE_DISABLE = (0), + DTC_REFER_INDEX_TABLE_ENABLE = (1 << 1) +} dtc_refer_index_table_t; + +/* Configurable options for Displacement Addition */ +typedef enum e_dtc_disp_add +{ + DTC_SRC_ADDR_DISP_ADD_DISABLE = (0), + DTC_SRC_ADDR_DISP_ADD_ENABLE = (1) +} dtc_disp_add_t; + +/* Enumerate list that can be selected as DTC activation source + * enum enum_dtce: is included from iodefine.h + */ +typedef enum enum_dtce dtc_activation_source_t; + +typedef enum e_dtc_command { + DTC_CMD_DTC_START, /* DTC will can accept activation requests. */ + DTC_CMD_DTC_STOP, /* DTC will not accept new activation request. */ + DTC_CMD_ACT_SRC_ENABLE, /* Enable an activation source specified by vector number. */ + DTC_CMD_ACT_SRC_DISABLE, /* Disable an activation source specified by vector number. */ + DTC_CMD_DATA_READ_SKIP_ENABLE, /* Enable Transfer Data Read Skip. */ + DTC_CMD_DATA_READ_SKIP_DISABLE, /* Disable Transfer Data Read Skip. */ + DTC_CMD_STATUS_GET, /* Get the current status of DTC. */ + DTC_CMD_CHAIN_TRANSFER_ABORT, /* Abort the current Chain transfer process. */ + DTC_CMD_SEQUENCE_TRANSFER_ENABLE, /* Sequence transfer is enabled. */ + DTC_CMD_SEQUENCE_TRANSFER_DISABLE, /* Sequence transfer is disabled. */ + DTC_CMD_SEQUENCE_TRANSFER_ABORT, /* Abort the sequence transfer. */ + DTC_CMD_CHANGING_DATA_FORCIBLY_SET /* Changing data forcibly set by R_DTC_Create(). */ +} dtc_command_t; + +typedef enum e_dtc_err /* DTC API error codes */ +{ + DTC_SUCCESS_DMAC_BUSY = 0, /* One or some DMAC resources are locked by another process. */ + DTC_SUCCESS, + DTC_ERR_OPENED, /* DTC was initialized already. */ + DTC_ERR_NOT_OPEN, /* DTC module is not initialized yet. */ + DTC_ERR_INVALID_ARG, /* Arguments are invalid. */ + DTC_ERR_INVALID_COMMAND, /* Command parameters are invalid. Or, forced data change failed. */ + DTC_ERR_NULL_PTR, /* Argument pointers are NULL. */ + DTC_ERR_BUSY, /* The DTC resources are locked by another process. */ + DTC_ERR_ACT /* Data transfer is in progress. */ +} dtc_err_t; + +/* Transfer data type */ +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ + +typedef struct st_transfer_data { /* 3 long-words */ + uint32_t lw1; + uint32_t lw2; + uint32_t lw3; +} dtc_transfer_data_t; + +#else /* Full-address mode */ +typedef struct st_transfer_data { /* 4 long-words */ + uint32_t lw1; + uint32_t lw2; + uint32_t lw3; + uint32_t lw4; +} dtc_transfer_data_t; +#endif + +/* Transfer data configuration */ +/* Moved struct dtc_transfer_data_cfg_t to r_dtc_rx_target_if.h */ +/* Include target mcu interface header file. */ +#if defined(BSP_MCU_RX23T) + #include ".\src\targets\rx23t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX24T) + #include ".\src\targets\rx24t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX24U) + #include ".\src\targets\rx24u\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX130) + #include ".\src\targets\rx130\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX113) + #include ".\src\targets\rx113\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX111) + #include ".\src\targets\rx111\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX110) + #include ".\src\targets\rx110\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX64M) + #include ".\src\targets\rx64m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX71M) + #include ".\src\targets\rx71m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72T) + #include ".\src\targets\rx72t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX231) + #include ".\src\targets\rx231\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX23E_A) + #include ".\src\targets\rx23e-a\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX230) + #include ".\src\targets\rx230\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX65N) + #include ".\src\targets\rx65n\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX66T) + #include ".\src\targets\rx66t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX66N) + #include ".\src\targets\rx66n\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX23W) + #include ".\src\targets\rx23w\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72M) + #include ".\src\targets\rx72m\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX13T) + #include ".\src\targets\rx13t\r_dtc_rx_target_if.h" +#elif defined(BSP_MCU_RX72N) + #include ".\src\targets\rx72n\r_dtc_rx_target_if.h" +#else + #error "This MCU is not supported by the current r_dtc_rx module." +#endif + +typedef struct st_dtc_stat { + uint8_t vect_nr; /* the current vector number */ + bool in_progress; /* Active flag of DTC module */ +} dtc_stat_t; + +typedef struct st_dtc_cmd_arg { + dtc_activation_source_t act_src; /* The activation source will be controlled */ + uint32_t chain_transfer_nr; /* Number of chain transfer when command is DTC_CMD_CHAIN_TRANSFER_ABORT. */ + dtc_transfer_data_t *p_transfer_data; /* Pointer to start address of Transfer data area on RAM */ + dtc_transfer_data_cfg_t *p_data_cfg; /* Pointer to contains the settings for Transfer data */ +} dtc_cmd_arg_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +dtc_err_t R_DTC_Open(void); +dtc_err_t R_DTC_Create(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t chain_transfer_nr); +dtc_err_t R_DTC_CreateSeq(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t sequence_transfer_nr, + uint8_t sequence_no); +dtc_err_t R_DTC_Close(void); +dtc_err_t R_DTC_Control(dtc_command_t command, dtc_stat_t *p_stat, dtc_cmd_arg_t *p_args); +uint32_t R_DTC_GetVersion(void); + +#endif /* DTC_RX_IF_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/readme.txt new file mode 100644 index 000000000..f68a15cab --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/readme.txt @@ -0,0 +1,245 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS MIDDLEWARE FOR MORE INFORMATION + +r_dtc_rx +========= + +Document Number +--------------- +R01AN1819EJ0350 +R01AN1819JJ0350 + +Version +------- +v3.50 + +Overview +-------- +The DTC driver provides a method to transmit the data using Data Transfer Controller (DTC). +The driver includes API functions to initialize DTC, create Transfer data, Control and get status of DTC. +The driver can be reduced in size by removing code used for parameter checking. +All configuration options can be found in "r_config\r_dtc_rx_config.h". +An original copy of the configuration file is stored in "r_dtc_rx\ref\r_dtc_rx_config_reference.h". + +Features +-------- +* Support Normal trasnsfer mode, Repeat trasnsfer mode and Block trasnsfer mode. +* Support chain transfer + +Supported MCUs +-------------- +* RX110 MCU +* RX111 MCU +* RX113 MCU +* RX130 MCU +* RX230 MCU +* RX231 MCU +* RX23E-A MCU +* RX64M MCU +* RX71M MCU +* RX23T MCU +* RX24T MCU +* RX24U MCU +* RX65N MCU +* RX651 MCU +* RX66T MCU +* RX66N MCU +* RX72T MCU +* RX23W MCU +* RX72M MCU +* RX13T MCU +* RX72N MCU + +Boards Tested On +---------------- +* RSKRX110 +* RSKRX111 +* RSKRX113 +* RSKRX130 +* RSKRX130_512KB +* RSKRX230 +* RSKRX231 +* RSKRX23E-A +* RSKRX64M +* RSKRX71M +* RSKRX23T +* RSKRX24T +* RSKRX24U +* RSKRX65N +* RSKRX65N_2MB +* RSKRX66T +* RSKRX66N +* RSKRX72T +* RSKRX23W +* RSKRX72M +* RSKRX13T +* RSKRX72N +Limitations +----------- +* None + +Peripherals Used Directly +------------------------- +* Data Transfer Controller (DTC) + +Required Packages +----------------- +* r_bsp + +How to add to your project +-------------------------- +This module must be added to each project in which it is used. +Renesas recommends using "Smart Configurator" described in (1) or (3). +However, "Smart Configurator" only supports some RX devices. +Please use the methods of (2) or (4) for unsupported RX devices. + +(1) Adding the FIT module to your project using "Smart Configurator" in e2 studio +By using the "Smart Configurator" in e2 studio, +the FIT module is automatically added to your project. +Refer to "Renesas e2 studio Smart Configurator User Guide (R20AN0451)" for details. + +(2) Adding the FIT module to your project using "FIT Configurator" in e2 studio +By using the "FIT Configurator" in e2 studio, +the FIT module is automatically added to your project. +Refer to "Adding Firmware Integration Technology Modules to Projects (R01AN1723)" for details. + +(3) Adding the FIT module to your project using "Smart Configurator" on CS+ +By using the "Smart Configurator Standalone version" in CS+, +the FIT module is automatically added to your project. +Refer to "Renesas e2 studio Smart Configurator User Guide (R20AN0451)" for details. + +(4) Adding the FIT module to your project in CS+ +In CS+, please manually add the FIT module to your project. +Refer to "Adding Firmware Integration Technology Modules to CS+ Projects (R01AN1826)" for details. + +Toolchain(s) Used +----------------- +* Renesas RX v3.02.00 +* GCC for Renesas RX 8.03.00.201904 +* IAR C/C++ Compiler for Renesas RX 4.12.1 + +File Structure +-------------- +r_dtc_rx +| r_dtc_rx_if.h +| readme.txt +| ++---doc +| | +| +---en +| | r01an1819ej{VERSION_NUMBER}-rx-dtc-dmac2.pdf +| +---ja +| r01an1819jj{VERSION_NUMBER}-rx-dtc-dmac2.pdf +| ++---ref +| r_dtc_rx_config_reference.h +| ++---src + | r_dtc_rx.c + | r_dtc_rx_private.h + | + +---targets + | + +---rx23t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx23w + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx24t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx24u + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx64m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx65n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx66t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx66n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx71m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72m + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72n + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx72t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx110 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx111 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx113 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx130 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx13t + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx230 + | r_dtc_rx_target.c + | r_dtc_rx_target.h + | r_dtc_rx_target_if.h + | + +---rx231 + r_dtc_rx_target.c + r_dtc_rx_target.h + r_dtc_rx_target_if.h + | + +---rx23E-A + r_dtc_rx_target.c + r_dtc_rx_target.h + r_dtc_rx_target_if.h + +r_config + r_dtc_rx_config.h + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h new file mode 100644 index 000000000..d0058ed06 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/ref/r_dtc_rx_config_reference.h @@ -0,0 +1,96 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_config.h +* Description : Configures the DTC drivers +******************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.01.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Added RX130, RX23T and RX24T. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : 30.09.2016 2.05 Added RX65N. +* : Added #define DTC_CFG_USE_SEQUENCE_TRANSFER. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +*******************************************************************************/ +#ifndef DTC_RX_CONFIG_H +#define DTC_RX_CONFIG_H + +#define DTC_DISABLE (0) +#define DTC_ENABLE (1) +/* + * SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + * 0 : Compiles out parameter checking. + * 1 : Includes parameter checking. + * Default value is set to BSP_CFG_PARAM_CHECKING_ENABLE to + * re-use the system default setting. +*/ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* + * SPECIFY WHETHER THE DTCER REGISTERS WILL BE CLEARED IN R_DTC_OPEN() + * DTC_DISABLE : Do nothing. + * DTC_ENABLE : Clear all DTCER registers in R_DTC_Open(). +*/ +#define DTC_CFG_DISABLE_ALL_ACT_SOURCE (DTC_ENABLE) + +/* + * SPECIFY WHICH ADDRESS MODE IS SUPPORTED BY DTC + * DTC_DISABLE : Select the Full address mode. + * DTC_ENABLE : Select the Short address mode. +*/ +#define DTC_CFG_SHORT_ADDRESS_MODE (DTC_DISABLE) + +/* + * SPECIFY WHETHER THE TRANSFER DATA READ SKIP IS ENABLED + * DTC_DISABLE : Disable Transfer Data Read Skip. + * DTC_ENABLE : Enable Transfer Data Read Skip. +*/ +#define DTC_CFG_TRANSFER_DATA_READ_SKIP_EN (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE DMAC FIT MODULE IS USED WITH DTC FIT MODULE + * DTC_DISABLE : DMAC FIT module is not used with DTC FIT module. + * DTC_ENABLE : DMAC FIT module is used with DTC FIT module. +*/ +#define DTC_CFG_USE_DMAC_FIT_MODULE (DTC_ENABLE) + +/* + * SPECIFY WHETHER THE SEQUENCE TRANSFER IS USED + * Also, set DTC_DISABLE to DTC_CFG_SHORT_ADDRESS_MODE. + * DTC_DISABLE : Not use sequence transfer. + * DTC_ENABLE : Use sequence transfer. +*/ +#define DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) + + +#endif /* DTC_RX_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c new file mode 100644 index 000000000..1d46b93ee --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/r_dtc_rx.c @@ -0,0 +1,1127 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +/******************************************************************************* +* File Name : r_dtc_rx.c +* Description : Functions for using DTC on RX devices. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Changed Tool-Chain version. +* : Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : Added RX130, RX23T and RX24T. +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Supported sequence transfer. +* : Added R_DTC_CreateSeq() function. +* : Added DTC_CMD_SEQUENCE_TRANSFER_ENABLE, +* : DTC_CMD_SEQUENCE_TRANSFER_DISABLE and DTC_CMD_SEQUENCE_TRANSFER_ABORT +* : to R_DTC_Control(). +* : 31.01.2017 2.06 Added the default setting of "writeback_disable", "sequence_end", +* : "refer_index_table_enable" and "disp_add_enable" in R_DTC_Create() +* : if the DTC IP version is DTCb or later. +* : 31.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : Fixed to correspond to Renesas coding rule. +* : Added DTC_CMD_CHANGING_DATA_FORCIBLY_SET command to R_DTC_Control(). +* : 28.09.2018 2.10 Supported RX66T. +* : Fixed to correspond to Renesas coding rule. +* : Add WAIT_LOOP comments. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin. +* Fixed DTC setting procedure. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. + Fixed warnings in IAR. +* : 25.11.2019 3.30 Added support for RX13T. +* : Modified comment of API function to Doxygen style. +* : Fixed to comply with GSCE Coding Standards Rev.6.00. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Defines for DTC support */ +#include +#include "r_dtc_rx_if.h" +#include ".\src\r_dtc_rx_private.h" + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define DTC_PRV_ACT_BIT_MASK (0x8000) /* DTC Active flag (DTCSTS.ACT) bit mask */ +#define DTC_PRV_VECT_NR_MASK (0x00FF) /* DTC-Activating Vector Number bits mask */ +#define DTC_PRV_MAX_16BITS_COUNT_VAL (65536) /* The maximum value of 16bit count value */ +#define DTC_PRV_MAX_8BITS_COUNT_VAL (256) /* The maximum value of 8bit count value */ +#define DTC_PRV_MIN_COUNT_VAL (1) /* The minimum of count value and block size */ +#define DTC_PRV_ESPSEL_BIT_MASK (0x8000) /* DTC Sequence transfer vector number setting bit mask */ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +extern const dtc_activation_source_t g_source_array[]; +uint32_t * gp_dtc_table_work[2]; + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ +static bool s_is_opened = false; /* Indicate whether DTC is opened. */ + +static dtc_err_t r_dtc_set_transfer_data(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_cfg); +static void r_dtc_clear_all_dtce_bits(void); +static bool r_dtc_abort_chain_transfer(uint32_t chain_transfer_nr); +static bool r_dtc_acquire_hw_lock(void); +static void r_dtc_release_hw_lock(void); +static bool r_dtc_check_dmac_locking_sw(void); +static dtc_err_t r_dtc_check_create_param(dtc_transfer_data_t *p_transfer_data, dtc_transfer_data_cfg_t *p_data_cfg); + + + +/*********************************************************************************************************************** +* Function Name: R_DTC_Open +********************************************************************************************************************//** +* @brief This function is run first when using the APIs of the DTC FIT module. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_OPENED DTC has been initialized already. +* @retval DTC_ERR_BUSY Resource has been locked by other process. +* @details Locks*1 the DTC and starts supplying clock to DTC, then initializes DTC vector table, address mode, +* Data Transfer Read Skip. When setting DTC_CFG_DISABLE_ALL_ACT_SOURCE to DTC_ENABLE in r_dtc_rx_config.h, all DTCER +* registers are cleared. When setting DTC_CFG_USE_SEQUENCE_TRANSFER to DTC_ENABLE, the area used in DTC index table is +* secured.\n\n +* Note: 1. The DTC FIT module uses the r_bsp default lock function. As a result, the DTC is in the locked state after a +* successful end. +* @note Set \#define BSP_CFG_HEAP_BYTES in r_bsp_config.h to the value greater than \#define DTC_VECTOR_TABLE_SIZE_BYTES +* in r_dtc_rx_target.h. This is to secure the DTC Vector table area using the malloc() function in the DTC FIT module. +*/ +dtc_err_t R_DTC_Open(void) +{ + uint8_t * p_dtc_table_work2 = 0; + + /* Check hw lock require */ + if (false == r_dtc_acquire_hw_lock()) + { + /* Lock has already been acquired by another task. Need to try again later. */ + return DTC_ERR_BUSY; + } + + if (true == s_is_opened) /* DTC is opened. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_OPENED; + } + + /* Allocate memory size */ + gp_dtc_table_work[0] = (uint32_t *)malloc(DTC_VECTOR_TABLE_SIZE_BYTES); + + if (0 == gp_dtc_table_work[0]) + { + r_dtc_release_hw_lock(); + return DTC_ERR_OPENED; + } + + gp_dtc_table_work[1] = gp_dtc_table_work[0]; + + /* Cast type of "gp_dtc_table_work" to match type of "p_dtc_table_work2" */ + p_dtc_table_work2 = (uint8_t *)gp_dtc_table_work[1]; + p_dtc_table_work2 = (p_dtc_table_work2 + 0x400); + + /* Cast type of "p_dtc_table_work2" to match type of "p_dtc_table_work2" */ + p_dtc_table_work2 = (uint8_t *)((uint32_t)p_dtc_table_work2 & 0xfffffc00); + +#if (DTC_ENABLE == DTC_CFG_DISABLE_ALL_ACT_SOURCE) /* Clear all DTCER registers. */ + + r_dtc_clear_all_dtce_bits(); + +#endif /* DTC_ENABLE == DTC_CFG_DISABLE_ALL_ACT_SOURCE */ + + /* Cancel module stop for DMAC and DTC. */ + r_dtc_module_enable(); + + /* Set DTC Vector Table Base Register. */ + DTC.DTCVBR = p_dtc_table_work2; + +#if (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) + p_dtc_table_work2 = (p_dtc_table_work2 + 0x400); + + /* Set address of the dtc index table. */ + DTC.DTCIBR = p_dtc_table_work2; +#endif /* (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ + + /* Set DTC address mode. */ +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + /*Turn on Short Address Mode*/ + DTC.DTCADMOD.BIT.SHORT = 1; +#else /* Full-address mode */ + DTC.DTCADMOD.BIT.SHORT = 0; +#endif /* DTC_CFG_SHORT_ADDRESS_MODE */ + + /* Set the Transfer Data Read Skip bit. */ +#if (DTC_ENABLE == DTC_CFG_TRANSFER_DATA_READ_SKIP_EN) /* Enable Data Read Skip. */ + DTC.DTCCR.BIT.RRS = 1; +#else /* Disable Data Read Skip. */ + DTC.DTCCR.BIT.RRS = 0; +#endif /* DTC_TRANSFER_DATA_READ_SKIP_EN */ + s_is_opened = true; /* DTC module is initialized successfully. */ + + return DTC_SUCCESS; +} +/* End of function R_DTC_Open */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Create +********************************************************************************************************************//** +* @brief This function is used to make DTC register settings and to specify the activation source. +* @param[in] act_source Activation source. +* @param[in] p_transfer_data Pointer to start address of Transfer data area on RAM. +* @param[in] p_data_cfg Pointer to settings for Transfer data. In the case of DTCb, the setting to the following +* structure members is invalid. This function sets the following values.\n +* p_data_cfg->writeback_disable = DTC_WRITEBACK_ENABLE;\n +* p_data_cfg->sequence_end = DTC_SEQUENCE_TRANSFER_CONTINUE;\n +* p_data_cfg->refer_index_table_enable = DTC_REFER_INDEX_TABLE_DISABLE;\n +* p_data_cfg->disp_add_enable = DTC_SRC_ADDR_DISP_ADD_DISABLE;\n +* @param[in] chain_transfer_nr Number of chain transfer.\n +* The number of Transfer data and corresponding configurations is (number of chain transfer + 1). +* Example: if chain_transfer_nr = 1, it means that there are 2 continuous Transfer data and 2 corresponding configurations +* and the first configuration enable the chain transfer.\n +* See Section 3 in application note for details. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_NOT_OPEN DTC is not initialized yet. +* @retval DTC_ERR_INVALID_ARG Parameters are invalid. +* @retval DTC_ERR_NULL_PTR Argument pointers are NULL. +* @details Writes the configuration to Transfer data. Writes the start address of Transfer data corresponding to interrupt +* number into DTC vector table. +* @note Before calling R_DTC_Create(), user must disable the current interrupt request (the interrupt source is passed to +* R_DTC_Create()) by clearing Interrupt Request Enable bit IERm.IENj:\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* Then, enable the interrupt request disabled after R_DTC_Create() is ended. The correspondence between IERm.IENj bit and +* interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of User's Manual: Hardware. +*/ +dtc_err_t R_DTC_Create(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t chain_transfer_nr) +{ + uint32_t count = chain_transfer_nr + 1; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_err_t ret = DTC_SUCCESS; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + + ret = r_dtc_check_create_param(p_transfer_data, p_data_cfg); + if (DTC_SUCCESS != ret) + { + return ret; + } + + if (false == s_is_opened) /* DTC is not initialized yet. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[act_source].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[act_source].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + +#if (DTC_IP_VER_DTCb <= DTC_IP) + /* Set the 0 value. */ + p_data_cfg->writeback_disable = DTC_WRITEBACK_ENABLE; + p_data_cfg->sequence_end = DTC_SEQUENCE_TRANSFER_CONTINUE; + p_data_cfg->refer_index_table_enable = DTC_REFER_INDEX_TABLE_DISABLE; + p_data_cfg->disp_add_enable = DTC_SRC_ADDR_DISP_ADD_DISABLE; +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + if (r_dtc_set_transfer_data(p_transfer_data, p_data_cfg) != DTC_SUCCESS) + { + /* Fail to apply configurations for Transfer data. */ + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_ARG; + } + else + { + p_data_cfg++; + p_transfer_data++; + } + count--; + } + + /* The row in Vector table corresponding to act_source */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCVBR + (4 * act_source)); + + /* Write start address of Transfer data to Vector table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + + /* Restore RRS bit. */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + + return DTC_SUCCESS; +} +/* End of function R_DTC_Create */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_CreateSeq +********************************************************************************************************************//** +* @brief This function performs the setting of the DTC register used in the sequence transfer and the activation source. +* @param[in] act_source Activation source +* @param[in] p_transfer_data Pointer to the start address in the transfer information area in RAM. +* @param[in] p_data_cfg Pointer to the transfer information setting\n +* Set the following structure members.\n +* p_data_cfg->writeback_disable\n +* p_data_cfg->sequence_end\n +* p_data_cfg->refer_index_table_enable\n +* p_data_cfg->disp_add_enable\n +* @param[in] sequence_transfer_nr Transfer information counts per sequence transfer (0 - 4294967295)\n +* See Section 3 in application note for details.\n\n +* @param[in] sequence_no Sequence number (0 - 255)\n +* The type definition of the transfer information and the data structure are the same as R_DTC_Create(). Total of 256 ways +* of the sequence information can be set. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_ERR_NOT_OPEN DTC is not initialized yet. +* @retval DTC_ERR_INVALID_ARG Arguments are invalid. +* @retval DTC_ERR_NULL_PTR Argument pointers are NULL. +* @details This function writes the setting information to the transfer information. Start address of the transfer +* information for the sequence number is written to DTC index table. +* @note Before calling R_DTC_CreateSeq(), user must disable the current interrupt request (the interrupt source is passed +* to R_DTC_CreateSeq()) by clearing Interrupt Request Enable bit (IERm.IENj):\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* Then, enable the interrupt request disabled after R_DTC_CreateSeq() is ended. The correspondence between IERm.IENj bit +* and interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of User's Manual: +* Hardware. +*/ +dtc_err_t R_DTC_CreateSeq(dtc_activation_source_t act_source, dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg, uint32_t sequence_transfer_nr, + uint8_t sequence_no) +{ +#if (DTC_DISABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) + return DTC_ERR_INVALID_ARG; +#else + uint32_t count = sequence_transfer_nr; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_err_t ret = DTC_SUCCESS; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + + if (0 != count) + { + ret = r_dtc_check_create_param(p_transfer_data, p_data_cfg); + if (DTC_SUCCESS != ret) + { + return ret; + } + } + + if (false == s_is_opened) /* DTC is not initialized yet. */ + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[act_source].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[act_source].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + /* The row in dtc index table corresponding to sequence_no. */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCIBR + (4 * sequence_no)); + + if (0 == count) + { + /* Set the cpu interrupt to the sequence number. */ + *p_ptr = DTC_INVALID_CMND; + } + else + { + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + /* Fail to apply configurations for Transfer data. */ + if (r_dtc_set_transfer_data(p_transfer_data, p_data_cfg) != DTC_SUCCESS) + { + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_ARG; + } + else + { + p_data_cfg++; + p_transfer_data++; + } + count--; + } + + /* Write start address of Transfer data to dtc index table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + } + + /* Restore RRS bit. */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[act_source].BIT.DTCE = dtce_backup; + + return DTC_SUCCESS; +#endif /* (DTC_DISABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ +} +/* End of function R_DTC_CreateSeq */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Close +********************************************************************************************************************//** +* @brief This function is used to release the resources of the DTC. +* @retval DTC_SUCCESS Successful operation +* @retval DTC_SUCCESS_DMAC_BUSY Successful operation.One or some DMAC resources are locked. +* @details Unlocks*1 the DTC and disable all DTC activation source by clearing the DTC Activation Enable Register DTCERn; +* stop supplying clock to DTC and put it to Module stop state. If in addition all DMAC channels have been unlocked, the +* function sets the DMAC and DTC to the module stop state.*2\n\n +* Note:\n 1. The DTC FIT module uses the r_bsp default lock function. As a result, the DTC is in the unlocked state after +* a successful end.\n 2. Because a shared bit is used as both the DMAC module stop setting bit and the DTC module stop +* setting bit, the function confirms that all DMAC channels are unlocked before making the module stop setting. (For +* details, see the "Low Power Consumption" section in the User's Manual: Hardware.)\n +* See Section 3 in application note for details. +* @note When controlling the DMAC without using the DMAC FIT module, make sure to monitor the usage of the DMAC and +* control locking and unlocking of the DMAC so that calling this function does not set the DMAC to the module stop state. +* Note that even if the DMAC has not been activated, it is necessary to keep it in the locked state when not making DMAC +* transfer settings. +*/ +dtc_err_t R_DTC_Close(void) +{ + /* Clear DTCE bits. */ + r_dtc_clear_all_dtce_bits(); + + /* Stop DTC module. */ + DTC.DTCST.BIT.DTCST = 0; + + /* DTC is closed. */ + s_is_opened = false; + + /* Cast type of "gp_dtc_table_work" to match type of parameter in "free" function */ + free((void *)gp_dtc_table_work[1]); + gp_dtc_table_work[1] = NULL; + + /* Check DMAC locking. */ + if (true == r_dtc_check_dmac_locking_sw()) + { + /* Disable the power for DTC and DMAC module. */ + r_dtc_module_disable(); + + /* Release hardware lock. */ + r_dtc_release_hw_lock(); + } + else + { + /* Release hardware lock. */ + r_dtc_release_hw_lock(); + return DTC_SUCCESS_DMAC_BUSY; + } + + return DTC_SUCCESS; +} +/* End of function R_DTC_Close */ + +/*********************************************************************************************************************** +* Function Name: R_DTC_Control +********************************************************************************************************************//** +* @brief This function controls the operation of the DTC. +* @param[in] command DTC control command +* @param[in] p_stat Pointer to the status when command is DTC_CMD_STATUS_GET.\n +* See Section 3 in application note for details. +* @param[in] p_args Pointer to the argument structure when command is DTC_CMD_ACT_SRC_ENABLE,DTC_CMD_ACT_SRC_DISABLE, +* DTC_CMD_CHAIN_TRANSFER_ABORT, DTC_CMD_SEQUENCE_TRANSFER_ENABLE, or DTC_CMD_CHANGING_DATA_FORCIBLY_SET.\n +* See Section 3 in application note for details. +* @retval [DTC_SUCCESS] Successful operation +* @retval [DTC_ERR_NOT_OPEN] DTC is not initialized yet. +* @retval [DTC_ERR_INVALID_COMMAND] Command parameters are invalid or DTC_CMD_CHANGING_DATA_FORCIBLY_SET command error. +* @retval [DTC_ERR_NULL_PTR] Argument pointers are NULL. +* @retval [DTC_ERR_ACT] Data transfer is in progress. +* @details Processing is performed depending on the command.\n +* See Section 3 in application note for details. +* @note When the command is DTC_CMD_GET_STATUS, the vector number is valid if only the DTC is in the progress +* (p_stat->in_progress is true). With command DTC_CMD_ENABLE_ACT_SRC, DTC_CMD_DISABLE_ACT_SRC or +* DTC_CMD_SEQUENCE_TRANSFER_ABORT, before calling R_DTC_Control(), user must disable the current interrupt request +* (the interrupt source is passed to R_DTC_Control()) by clearing Interrupt Request Enable bit (IERm.IENj);\n\n +* ICU.IER[m].BIT.IENj = 0;\n\n +* After processing of R_DTC_Control() is ended, the interrupt request disabled is enabled. The correspondence between +* IERm.IENj bit and interrupt source is described in Interrupt Vector Table, chapter Interrupt Controller (ICU) of +* User's Manual: Hardware. With abort processing, user must re-create the Chain transfer data after the transfer is +* aborted because the old Transfer data are destroyed. If an invalid value is attempted to set with +* DTC_CMD_CHANGING_DATA_FORCIBLY_SET, R_DTC_Control() returns DTC_ERR_INVALID_COMMAND R_DTC_Control() may already update +* some registers before the invalid value is detected. This occurs only when users try +* to change FORCIBLY DTC with Invalid Value. +*/ +dtc_err_t R_DTC_Control(dtc_command_t command, dtc_stat_t *p_stat, dtc_cmd_arg_t *p_args) +{ + uint32_t count = 0; + uint32_t *p_ptr = NULL; + uint8_t dtce_backup = 0; + uint8_t rrs_backup = 0; + dtc_transfer_data_t *p_transfer_data_backup = NULL; + +#if (1 == DTC_CFG_PARAM_CHECKING_ENABLE) + + if ((DTC_CMD_STATUS_GET == command) && (NULL == p_stat)) + { + return DTC_ERR_NULL_PTR; + } + else if ((((DTC_CMD_ACT_SRC_ENABLE == command) || (DTC_CMD_ACT_SRC_DISABLE == command)) || + (DTC_CMD_CHAIN_TRANSFER_ABORT == command)) || (DTC_CMD_SEQUENCE_TRANSFER_ENABLE == command)) + { + if (NULL == p_args) /* Require argument */ + { + return DTC_ERR_NULL_PTR; + } + } + else if (DTC_CMD_CHANGING_DATA_FORCIBLY_SET == command) + { + if (NULL == p_args) /* Require argument */ + { + return DTC_ERR_INVALID_COMMAND; + } + if (r_dtc_check_create_param(p_args->p_transfer_data, p_args->p_data_cfg) != DTC_SUCCESS) + { + return DTC_ERR_INVALID_COMMAND; + } + } + else + { + /* do nothing */ + } + +#endif /* DTC_CFG_PARAM_CHECKING_ENABLE */ + + if (false == s_is_opened) + { + r_dtc_release_hw_lock(); + return DTC_ERR_NOT_OPEN; + } + + switch (command) + { + case DTC_CMD_DTC_START: /* Start DTC module. */ + { + /* DTC Module start*/ + DTC.DTCST.BIT.DTCST = 1; + break; + } + + case DTC_CMD_DTC_STOP: /* Stop DTC module. */ + { + /* DTC Module stop*/ + DTC.DTCST.BIT.DTCST = 0; + break; + } + + case DTC_CMD_DATA_READ_SKIP_ENABLE: /* Enable Transfer Data Read Skip. */ + { + /* Set Read Skip Enable bit*/ + DTC.DTCCR.BIT.RRS = 1; + break; + } + + case DTC_CMD_DATA_READ_SKIP_DISABLE: /* Disable Transfer Data Read Skip. */ + { + /* Clear Read Skip Enable bit*/ + DTC.DTCCR.BIT.RRS = 0; + break; + } + + case DTC_CMD_ACT_SRC_ENABLE: /* Select one interrupt as a DTC activation source. */ + { + /* Set Activation source for DTC*/ + ICU.DTCER[p_args->act_src].BIT.DTCE = 1; + break; + } + + case DTC_CMD_ACT_SRC_DISABLE: /* Remove one interrupt as a DTC activation source. */ + { + /* Clear Activation source*/ + ICU.DTCER[p_args->act_src].BIT.DTCE = 0; + break; + } + + case DTC_CMD_STATUS_GET: + { + /* Check DTC Status*/ + if (0 == (DTC.DTCSTS.WORD & DTC_PRV_ACT_BIT_MASK)) /* DTC transfer operation is not in progress. */ + { + p_stat->in_progress = false; + + /* DTC is not in progress. -> vector number is invalid. */ + } + else /* DTC transfer operation is in progress. */ + { + p_stat->in_progress = true; + + /* Get the current vector number. */ + p_stat->vect_nr = (uint8_t)(DTC.DTCSTS.WORD & DTC_PRV_VECT_NR_MASK); /* get lower 8 bits: 0-7*/ + } + break; + } + + case DTC_CMD_CHAIN_TRANSFER_ABORT: + { + r_dtc_abort_chain_transfer(p_args->chain_transfer_nr); + break; + } + +#if (DTC_IP_VER_DTCb <= DTC_IP) + + case DTC_CMD_SEQUENCE_TRANSFER_ENABLE: + + /* Set the sequence transfer vector number and sequence transfer is enabled. */ + DTC.DTCSQE.WORD = (DTC_PRV_ESPSEL_BIT_MASK | (uint16_t)p_args->act_src); + break; + + case DTC_CMD_SEQUENCE_TRANSFER_DISABLE: + + /* Sequence transfer is disabled. */ + DTC.DTCSQE.WORD &= (~DTC_PRV_ESPSEL_BIT_MASK); + break; + + case DTC_CMD_SEQUENCE_TRANSFER_ABORT: + + /* DTC transfer operation is in progress. */ + if (DTC.DTCSTS.WORD & DTC_PRV_ACT_BIT_MASK) + { + /* Store value of VECN of DTCSQE Register to "tmp" variable */ + uint16_t tmp = DTC.DTCSQE.BIT.VECN; + + /* Compare value of VECN of DTCSTS Register with "tmp" variable */ + if (DTC.DTCSTS.BIT.VECN == tmp) + { + return DTC_ERR_ACT; + } + } + + /* Abort the sequence transfer. */ + DTC.DTCOR.BIT.SQTFRL = 1; + break; + +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + case DTC_CMD_CHANGING_DATA_FORCIBLY_SET: + { + /* Store start address of p_args->p_transfer_data. */ + p_transfer_data_backup = p_args->p_transfer_data; + + /* Store old value of DTCERn.DTCE bit. */ + dtce_backup = ICU.DTCER[p_args->act_src].BIT.DTCE; + + /* Disable the interrupt source. Clear the DTCER */ + ICU.DTCER[p_args->act_src].BIT.DTCE = 0; + + /* Store old value of DTCCR.RRS bit. */ + rrs_backup = DTC.DTCCR.BIT.RRS; + + /* Clear RRS bit. */ + DTC.DTCCR.BIT.RRS = 0; + + count = p_args->chain_transfer_nr + 1; + + /* Apply configurations */ + /* WAIT_LOOP */ + while (count > 0) + { + if (r_dtc_set_transfer_data(p_args->p_transfer_data, p_args->p_data_cfg) != DTC_SUCCESS) + { + /* Fail to apply configurations for Transfer data. */ + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[p_args->act_src].BIT.DTCE = dtce_backup; + return DTC_ERR_INVALID_COMMAND; + } + else + { + p_args->p_transfer_data++; + p_args->p_data_cfg++; + } + count--; + } + + /* The row in Vector table corresponding to act_source */ + p_ptr = (uint32_t *)((uint32_t)DTC.DTCVBR + (4 * p_args->act_src)); + + /* Write start address of Transfer data to Vector table. */ + *p_ptr = (uint32_t)p_transfer_data_backup; + + /* Restore RRS bit */ + DTC.DTCCR.BIT.RRS = rrs_backup; + + /* Restore the DTCE bit. */ + ICU.DTCER[p_args->act_src].BIT.DTCE = dtce_backup; + break; + } + default: + { + return DTC_ERR_INVALID_COMMAND; + break; + } + } + + return DTC_SUCCESS; +} +/* End of function R_DTC_Control */ + +/******************************************************************************* +* Function Name: R_DTC_GetVersion +****************************************************************************//** +* @brief This function is used to get the driver version information. +* @return Version_number Upper 2 bytes: major version, lower 2 bytes: minor version +* @details Returns the version information. +* @note None +*/ +uint32_t R_DTC_GetVersion(void) +{ + uint32_t version = 0; + + version = (DTC_VERSION_MAJOR << 16) | DTC_VERSION_MINOR; + + return version; +} +/* End of function R_DTC_GetVersion */ + +/******************************************************************************* +* Function Name: r_dtc_set_transfer_data +* Description : Applies configurations to a Transfer data area, it is an internal +* function called by R_DTC_Create(); and all arguments are validated +* in R_DTC_Create() +* Arguments : transfer_data - +* Start address of Transfer data +* data_cfg - +* Contains configurations for the Transfer data +* Return Value : DTC_SUCCESS - +* Apply configurations for Transfer data successfully. +* DTC_ERR_INVALID_ARG +* Fail to apply configurations for Transfer data. +*******************************************************************************/ +static dtc_err_t r_dtc_set_transfer_data(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_cfg) +{ + dtc_mra_t t_mra; + dtc_mrb_t t_mrb; + dtc_cra_t t_cra; + dtc_crb_t t_crb; + + /* Cast type of "p_transfer_data" to match type of "p_td_ptr" */ + volatile dtc_internal_registers_t *p_td_ptr = (volatile dtc_internal_registers_t *)p_transfer_data; + + /* Set for MRA - . */ +#if (DTC_IP_VER_DTCb <= DTC_IP) +#if (DTC_ENABLE != DTC_CFG_SHORT_ADDRESS_MODE) /* Full-address mode */ + dtc_mrc_t t_mrc; + + /* Casting to match type of "t_mrc.BYTE" */ + t_mrc.BYTE = (uint8_t)(p_cfg->disp_add_enable); +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ + /* Casting to match type of "t_mra.BYTE" */ + t_mra.BYTE = ((((uint8_t)p_cfg->writeback_disable | (uint8_t)p_cfg->src_addr_mode) | (uint8_t)p_cfg->data_size) | (uint8_t)p_cfg->transfer_mode); + + /* Casting to match type of "t_mrb.BYTE" */ + t_mrb.BYTE = (((((((uint8_t)p_cfg->sequence_end |(uint8_t)p_cfg->refer_index_table_enable) | (uint8_t)p_cfg->dest_addr_mode) | + (uint8_t)p_cfg->repeat_block_side) | (uint8_t)p_cfg->response_interrupt) | + (uint8_t)p_cfg->chain_transfer_enable) | (uint8_t)p_cfg->chain_transfer_mode); +#else + /* Casting to match type of "t_mra.BYTE" */ + t_mra.BYTE = (uint8_t)(p_cfg->src_addr_mode | p_cfg->data_size | p_cfg->transfer_mode); + + /* Casting to match type of "t_mrb.BYTE" */ + t_mrb.BYTE = (uint8_t)(p_cfg->dest_addr_mode | p_cfg->repeat_block_side | p_cfg->response_interrupt | + p_cfg->chain_transfer_enable | p_cfg->chain_transfer_mode); +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + switch (t_mra.BIT.MD) /* DTC transfer mode */ + { + case 0x0: /* Normal mode */ + { + if (DTC_PRV_MAX_16BITS_COUNT_VAL == p_cfg->transfer_count)/* Transfer count = 65536 */ + { + t_cra.WORD = 0x0000; + } + else /* 1 - 65535 */ + { + /* Cast type of "p_cfg->transfer_count" to uint16_t to match type of "t_cra.WORD" */ + t_cra.WORD = (uint16_t)p_cfg->transfer_count; + } + break; + } + + case 0x1: /* Repeat mode */ + { + /* Set counter. */ + if (p_cfg->transfer_count < DTC_PRV_MAX_8BITS_COUNT_VAL) /* count 1-255 */ + { + /* Cast type of "p_cfg->transfer_count" to match type of "t_cra.BYTE.CRA_H" */ + t_cra.BYTE.CRA_H = (uint8_t)p_cfg->transfer_count; + + /* Cast type of "p_cfg->transfer_count" to match type of "t_cra.BYTE.CRA_L" */ + t_cra.BYTE.CRA_L = (uint8_t)p_cfg->transfer_count; + } + else if (DTC_PRV_MAX_8BITS_COUNT_VAL == p_cfg->transfer_count) + { + t_cra.BYTE.CRA_H = 0x00; + t_cra.BYTE.CRA_L = 0x00; + } + else /* Transfer count > 256 */ + { + return DTC_ERR_INVALID_ARG; + } + break; + } + + case 0x2: /* DTC_TRANSFER_MODE_BLOCK - Block transfer mode */ + { + /* Set counter. */ + if (DTC_PRV_MAX_16BITS_COUNT_VAL == p_cfg->transfer_count)/* Transfer count = 65536 */ + { + t_crb.WORD = 0x0000; + } + else /* 1 - 65535 */ + { + /* Cast type of "p_cfg->transfer_count" to uint16_t to match type of "t_cra.WORD" */ + t_crb.WORD = (uint16_t)p_cfg->transfer_count; + } + + if (p_cfg->block_size < DTC_PRV_MAX_8BITS_COUNT_VAL) /* Block size 1-255 */ + { + /* Cast type of "p_cfg->block_size" to match type of "t_cra.BYTE.CRA_H" */ + t_cra.BYTE.CRA_H = (uint8_t)p_cfg->block_size; + + /* Cast type of "p_cfg->block_size" to match type of "t_cra.BYTE.CRA_L" */ + t_cra.BYTE.CRA_L = (uint8_t)p_cfg->block_size; + } + else if (DTC_PRV_MAX_8BITS_COUNT_VAL == p_cfg->block_size) /* Block size = 256 */ + { + t_cra.BYTE.CRA_H = 0; + t_cra.BYTE.CRA_L = 0; + } + else /* Invalid block size */ + { + return DTC_ERR_INVALID_ARG; + } + break; + } + + default: + { + return DTC_ERR_INVALID_ARG; + break; + } + } + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ + /* settings for fist long word: MRA & SAR */ + p_td_ptr->FIRST_LWORD.LWORD = 0; /* clear */ + p_td_ptr->FIRST_LWORD.REG.MRA = t_mra; /* 1 byte MRA */ + p_td_ptr->FIRST_LWORD.LWORD |= (p_cfg->source_addr & 0x00FFFFFF); /* 3 byte SAR */ + + /* settings for second long word: MRB & DAR */ + p_td_ptr->SECOND_LWORD.LWORD = 0; /* clear */ + p_td_ptr->SECOND_LWORD.REG.MRB = t_mrb; /* 1 byte MRB */ + p_td_ptr->SECOND_LWORD.LWORD |= (p_cfg->dest_addr & 0x00FFFFFF); /* 3 byte DAR */ + + /* settings for third long word: CRA & CRB */ + p_td_ptr->THIRD_LWORD.REG.CRA.WORD = t_cra.WORD; + p_td_ptr->THIRD_LWORD.REG.CRB.WORD = t_crb.WORD; + +#else /* Full-address mode */ + /* settings for fist long word: MRA & MRB */ + p_td_ptr->FIRST_LWORD.REG.MRA.BYTE = t_mra.BYTE; /* 1 byte MRA */ + p_td_ptr->FIRST_LWORD.REG.MRB.BYTE = t_mrb.BYTE; /* 1 byte MRB */ +#if (DTC_IP_VER_DTCb <= DTC_IP) + p_td_ptr->FIRST_LWORD.REG.MRC.BYTE = t_mrc.BYTE; /* 1 byte MRC */ +#endif /* (DTC_IP_VER_DTCb <= DTC_IP) */ + + /* settings for second long word: SAR */ + p_td_ptr->SECOND_LWORD.SAR = p_cfg->source_addr; /* 4 byte SAR */ + + /* settings for third long word: DAR */ + p_td_ptr->THIRD_LWORD.DAR = p_cfg->dest_addr; /* 4 byte DAR */ + + /* settings for fourth long word: CRA & CRB */ + p_td_ptr->FOURTH_LWORD.REG.CRA.WORD = t_cra.WORD; + p_td_ptr->FOURTH_LWORD.REG.CRB.WORD = t_crb.WORD; +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ + return DTC_SUCCESS; +} +/* End of function r_dtc_set_transfer_data */ + +/******************************************************************************* +* Function Name: r_dtc_clear_all_dtce_bits +* Description : Clears all DTCERn.DTCE bit corresponding to the interrupt that +* can be selected as DTC activation sources. +* Arguments : addr - +* Address need to be validated +* Return Value : true - +* The address is valid. +* false - +* The address is invalid. +*******************************************************************************/ +static void r_dtc_clear_all_dtce_bits(void) +{ + volatile uint32_t dtce_cnt = 0; + + /* Clear all DTCER registers. + * Scan through all available DTCER registers in Array. + */ + /* WAIT_LOOP */ + while (dtce_cnt < DTC_NUM_INTERRUPT_SRC) + { + /* Clear Activation source*/ + ICU.DTCER[g_source_array[dtce_cnt]].BIT.DTCE = 0; + dtce_cnt++; + } + + return; +} +/* End of function r_dtc_clear_all_dtce_bits */ + +/******************************************************************************* +* Function Name: r_dtc_abort_chain_transfer +* Description : Aborts the current active chain transfer. +* Arguments : chain_transfer_nr - +* Number of chain transfer +* Return Value : true - +* Abort successfully. +* false +* Can not abort. +*******************************************************************************/ +static bool r_dtc_abort_chain_transfer(uint32_t chain_transfer_nr) +{ + volatile uint32_t cnt = 0; + uint16_t status_reg = 0; + + /* Set status register*/ + status_reg = DTC.DTCSTS.WORD; + + volatile dtc_internal_registers_t *p_td_ptr = NULL; + + if (0 == (status_reg & 0x8000)) /* DTC is not active. */ + { + return false; + } + + status_reg &= 0xFF; /* Get the vector number. */ + p_td_ptr = (((volatile dtc_internal_registers_t *)*((uint32_t *)DTC.DTCVBR + status_reg)) + chain_transfer_nr) - 1; + + /* Clear all CHNE bit */ + /* WAIT_LOOP */ + while (cnt < chain_transfer_nr) + { +#if (DTC_DISABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Full address mode */ + p_td_ptr->FIRST_LWORD.REG.MRB.BIT.CHNE = 0; +#else /* Short address mode */ + p_td_ptr->SECOND_LWORD.REG.MRB.BIT.CHNE = 0; +#endif + p_td_ptr--; + cnt++; + } + + return true; +} +/* End of function r_dtc_abort_chain_transfer */ + +/******************************************************************************* +* Function Name: r_dtc_acquire_hw_lock +* Description : Gets the hardware lock BSP_LOCK_DTC. +* Arguments : None. +* Return Value : true - +* The lock is acquired successfully +* false - +* Fails to get the lock +*******************************************************************************/ +static bool r_dtc_acquire_hw_lock(void) +{ + return R_BSP_HardwareLock(BSP_LOCK_DTC); +} +/* End of function r_dtc_acquire_hw_lock */ + +/******************************************************************************* +* Function Name: r_dtc_release_hw_lock +* Description : release hardware lock BSP_LOCK_DTC. +* Arguments : None. +* Return Value : None. +*******************************************************************************/ +static void r_dtc_release_hw_lock(void) +{ + R_BSP_HardwareUnlock(BSP_LOCK_DTC); + return; +} +/* End of function r_dtc_release_hw_lock */ + + +/******************************************************************************* +* Function Name: r_dtc_check_dmac_locking_sw +* Description : Checks all DMAC channel locking. +* Arguments : none - +* Return Value : true - +* All DMAC channels are unlocked. +* false - +* One or some DMAC channels are locked. +*******************************************************************************/ +static bool r_dtc_check_dmac_locking_sw(void) +{ + bool ret = true; + +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) + /* defined(0 != BSP_CFG_USER_LOCKING_ENABLED) */ + /* or defined(DTC_ENABLE !=DTC_CFG_USE_DMAC_FIT_MODULE) */ + /* or defined(bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) */ + /* User has to do the locking check of DMAC by themselves. */ + ret = r_dtc_check_DMAC_locking_byUSER(); +#else + uint32_t channel; + uint32_t dmac_lock_num = 0; + + /* Check locking status of all DMAC channels */ + /* WAIT_LOOP */ + for (channel = 0; channel < DMAC_NUM_CHANNELS; channel++) + { + /* Checks if DMAC channel is not locking */ + if (false == R_BSP_HardwareLock((mcu_lock_t)(BSP_LOCK_DMAC0 + channel))) + { + dmac_lock_num++; + } + else + { + /* Unlock DMAC channel */ + R_BSP_HardwareUnlock((mcu_lock_t)(BSP_LOCK_DMAC0 + channel)); + } + } + + if (0 == dmac_lock_num) + { + ret = true; + } + else + { + ret = false; + } +#endif + + return ret; +} +/* End of function r_dtc_check_dmac_locking_sw */ + +/******************************************************************************* +* Function Name: r_dtc_check_create_param +* Description : Checks creating function parameter. +* Arguments : none - +* Return Value : DTC_SUCCESS - +* Successful operation +* DTC_ERR_INVALID_ARG - +* Parameters are invalid. +* DTC_ERR_NULL_PTR - +* The pointers are NULL. +*******************************************************************************/ +static dtc_err_t r_dtc_check_create_param(dtc_transfer_data_t *p_transfer_data, + dtc_transfer_data_cfg_t *p_data_cfg) +{ +#if (1 == DTC_CFG_PARAM_CHECKING_ENABLE) + + if ((NULL == p_data_cfg) || (NULL == p_transfer_data)) + { + return DTC_ERR_NULL_PTR; + } + + if ((p_data_cfg->transfer_count < DTC_PRV_MIN_COUNT_VAL) || + (p_data_cfg->transfer_count > DTC_PRV_MAX_16BITS_COUNT_VAL)) + { + return DTC_ERR_INVALID_ARG; + } + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Short-address mode */ +/* Address must be in: 0x00000000h to 0x007FFFFF and 0xFF800000 to 0xFFFFFFFF */ + if ((p_data_cfg->source_addr > 0x007FFFFF) && (p_data_cfg->source_addr < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } + + if ((p_data_cfg->dest_addr > 0x007FFFFF) && (p_data_cfg->dest_addr < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } + /* Casting to match type of "uint32_t" */ + if (((uint32_t)p_transfer_data > 0x007FFFFF) && ((uint32_t)p_transfer_data < 0xFF800000)) + { + return DTC_ERR_INVALID_ARG; + } +#endif /* (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) */ +#endif /* (1 == DTC_CFG_PARAM_CHECKING_ENABLE) */ + return DTC_SUCCESS; +} +/* End of function r_dtc_check_create_param */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h new file mode 100644 index 000000000..4995ce1cd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/r_dtc_rx_private.h @@ -0,0 +1,409 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_private.h +* Description : Functions for using DTC on RX devices. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 17.03.2014 1.00 Initial revision +* : 17.07.2014 2.00 Second revision +* : 12.11.2014 2.01 Added RX113. +* : 30.01.2015 2.02 Added RX71M. +* : 13.04.2015 2.03 Added RX231 and RX230. +* : 24.12.2015 2.04 Modified #define name from "DTC_CFG_SHORT_ADDRRESS_MODE" +* : to "DTC_CFG_SHORT_ADDRESS_MODE". +* : Added RX130, RX23T and RX24T. +* : 30.09.2016 2.05 Added RX65N. +* : Supported to the register added in DTCb. +* : Supported sequence transfer. +* : Added DTC IP version definitions. +* : 13.03.2017 2.07 Added RX24U and RX24T-512KB. +* : 31.07.2017 2.08 Supported RX65N-2MB and RX130-512KB. +* : Fixed to correspond to Renesas coding rule. +* : 28.09.2018 2.10 Supported RX66T. +* : 01.02.2019 2.20 Supported RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 18.06.2019 3.01 Removed "defined(__BIG_ENDIAN__)" from DTC_BIG_ENDIAN macro definition. +* : 28.06.2019 3.10 Added support for RX23W. +* : 15.08.2019 3.20 Added support for RX72M. +* : 25.11.2019 3.30 Added support for RX13T. +* : 30.12.2019 3.40 Added support for RX66N, RX72N. +* : 31.03.2020 3.50 Added support for RX23E-A. +*******************************************************************************/ +#ifndef DTC_RX_PRIVATE_H +#define DTC_RX_PRIVATE_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Fixed width integer support. */ +#include +/* Bool support */ +#include + +#if defined(BSP_MCU_RX23T) + #include ".\src\targets\rx23t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24T) + #include ".\src\targets\rx24t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24U) + #include ".\src\targets\rx24u\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX130) + #include ".\src\targets\rx130\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX13T) + #include ".\src\targets\rx13t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX113) + #include ".\src\targets\rx113\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX111) + #include ".\src\targets\rx111\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX110) + #include ".\src\targets\rx110\r_dtc_rx_target.h" + #if (DTC_CFG_USE_DMAC_FIT_MODULE == DTC_ENABLE) + #error "This MCU does not have DMAC module." + #error "Change to DTC_CFG_USE_DMAC_FIT_MODULE (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX64M) + #include ".\src\targets\rx64m\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX71M) + #include ".\src\targets\rx71m\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX231) + #include ".\src\targets\rx231\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX23E_A) + #include ".\src\targets\rx23e-a\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX23W) + #include ".\src\targets\rx23w\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX230) + #include ".\src\targets\rx230\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX65N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx65n\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX66T) + #include ".\src\targets\rx66t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX66N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx66n\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX72T) + #include ".\src\targets\rx72t\r_dtc_rx_target.h" + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif +#elif defined(BSP_MCU_RX72M) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx72m\r_dtc_rx_target.h" +#elif defined(BSP_MCU_RX72N) + #if (DTC_CFG_USE_SEQUENCE_TRANSFER == DTC_ENABLE) && (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) + #error "Change to DTC_CFG_USE_SEQUENCE_TRANSFER (DTC_DISABLE) in r_dtc_rx_config.h." + #endif + #include ".\src\targets\rx72n\r_dtc_rx_target.h" +#else + #error "This MCU is not supported by the current r_dtc_rx module." +#endif + +/***************************************************************************** +Macro definitions +******************************************************************************/ +#define DTC_BIG_ENDIAN (defined(__BIG) || defined(__RX_BIG_ENDIAN__)) +#define DTC_INVALID_CMND ((uint32_t)0x00000001) +/* DTC IP version */ +#define DTC_IP_VER_DTC (0) +#define DTC_IP_VER_DTCa (1) +#define DTC_IP_VER_DTCb (2) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +/* The DTC Mode Register A (MRA) structure */ + +R_BSP_PRAGMA_UNPACK; + +#if (DTC_IP_VER_DTCa == DTC_IP) +typedef union dtc_mra { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4 ( + uint8_t MD:2, /* b7,b6: DTC Transfer Mode Select */ + uint8_t SZ:2, /* DTC Data Transfer Size */ + uint8_t SM:2, /* Transfer Source Address Addressing Mode */ + uint8_t rs:2 /* reserved */ + ) BIT; + +} dtc_mra_t; + +/* The DTC Mode Register B (MRB) structure */ +typedef union dtc_mrb { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6 ( + uint8_t CHNE :1, /* b7: DTC Chain Transfer Enable */ + uint8_t CHNS :1, /* DTC Chain Transfer Select */ + uint8_t DISEL:1, /* DTC Interrupt Select */ + uint8_t DTS :1, /* DTC Transfer Mode Select */ + uint8_t DM :2, /* Transfer Destination Address Addressing Mode */ + uint8_t rs :2 /* reserved */ + ) BIT; + +} dtc_mrb_t; +#else +typedef union dtc_mra { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5 ( + uint8_t MD:2, /* b7,b6: DTC Transfer Mode Select */ + uint8_t SZ:2, /* DTC Data Transfer Size */ + uint8_t SM:2, /* Transfer Source Address Addressing Mode */ + uint8_t rs:1, /* reserved */ + uint8_t WBDIS:1 /* Write-back Disable */ + ) BIT; + +} dtc_mra_t; + +/* The DTC Mode Register B (MRB) structure */ +typedef union dtc_mrb { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7 ( + uint8_t CHNE :1, /* b7: DTC Chain Transfer Enable */ + uint8_t CHNS :1, /* DTC Chain Transfer Select */ + uint8_t DISEL:1, /* DTC Interrupt Select */ + uint8_t DTS :1, /* DTC Transfer Mode Select */ + uint8_t DM :2, /* Transfer Destination Address Addressing Mode */ + uint8_t INDX:1, /* Index Table Reference */ + uint8_t SQEND:1 /* Sequence Transfer End */ + ) BIT; + +} dtc_mrb_t; + +/* The DTC Mode Register C (MRC) structure */ +typedef union dtc_mrc { + uint8_t BYTE; + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2 ( + uint8_t rs :7, /* reserved */ + uint8_t DISPE :1 + ) BIT; + +} dtc_mrc_t; +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + +/* The DTC Transfer Count Register A (CRA) structure */ +typedef union dtc_cra { + uint16_t WORD; + struct { +#if (DTC_BIG_ENDIAN) + uint8_t CRA_H; + uint8_t CRA_L; +#else /* little endian */ + uint8_t CRA_L; + uint8_t CRA_H; +#endif /* (DTC_BIG_ENDIAN) */ + } BYTE; +} dtc_cra_t; + +/* The DTC Transfer Count Register B (CRB) structure */ +typedef union dtc_crb { + uint16_t WORD; +} dtc_crb_t; + +#if (DTC_ENABLE == DTC_CFG_SHORT_ADDRESS_MODE) /* Transfer data in short-address mode */ +typedef struct st_dtc_short_transfer_data { + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mra_t MRA; + uint8_t SAR[3]; +#else /* Little-Endian */ + uint8_t SAR[3]; + dtc_mra_t MRA; +#endif /* (DTC_BIG_ENDIAN) */ + + } REG; + + } FIRST_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mrb_t MRB; + uint8_t DAR[3]; +#else /* Little-Endian */ + uint8_t SAR[3]; + dtc_mrb_t MRB; +#endif /* (DTC_BIG_ENDIAN) */ + + } REG; + } SECOND_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_cra_t CRA; + dtc_crb_t CRB; +#else /* Little-Endian */ + dtc_crb_t CRB; + dtc_cra_t CRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } THIRD_LWORD; +} dtc_internal_registers_t; + +#else /* Transfer data in full-address mode */ +typedef struct st_dtc_full_transfer_data { + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_mra_t MRA; + dtc_mrb_t MRB; +#if (DTC_IP_VER_DTCa == DTC_IP) + uint16_t reserver; /* reserve area */ +#else + dtc_mrc_t MRC; + uint8_t reserver; /* reserve area */ +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + +#else /* Little-Endian */ +#if (DTC_IP_VER_DTCa == DTC_IP) + uint16_t reserver; /* reserve area */ +#else + uint8_t reserver; /* reserve area */ + dtc_mrc_t MRC; +#endif /* (DTC_IP_VER_DTCa == DTC_IP) */ + dtc_mrb_t MRB; + dtc_mra_t MRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } FIRST_LWORD; + union { + uint32_t SAR; + } SECOND_LWORD; + union { + uint32_t DAR; + } THIRD_LWORD; + union { + uint32_t LWORD; + struct { +#if (DTC_BIG_ENDIAN) /* Big-Endian */ + dtc_cra_t CRA; + dtc_crb_t CRB; +#else /* Little-Endian */ + dtc_crb_t CRB; + dtc_cra_t CRA; +#endif /* (DTC_BIG_ENDIAN) */ + } REG; + } FOURTH_LWORD; +} dtc_internal_registers_t; + +#endif /* DTC_CFG_SHORT_ADDRESS_MODE */ + +R_BSP_PRAGMA_PACKOPTION; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void r_dtc_module_enable(void); +void r_dtc_module_disable(void); +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) +bool r_dtc_check_DMAC_locking_byUSER(void); +#endif + + +#endif /* DTC_RX_PRIVATE_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c new file mode 100644 index 000000000..ac86b0d7d --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c @@ -0,0 +1,207 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target.c +* Device : RX72N +* Tool-Chain : Renesas RXC Toolchain v3.01.00 +* OS : not use +* H/W Platform : not use +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +/* Defines for DTC support */ +#include "r_dtc_rx_if.h" +#include ".\src\r_dtc_rx_private.h" + +/* Check MCU Group */ +#if defined(BSP_MCU_RX72N) + +/******************************************************************************* +Exported global variables (to be accessed by other files) +*******************************************************************************/ +/* The array of all interrupt source */ +const dtc_activation_source_t g_source_array[DTC_NUM_INTERRUPT_SRC] = +{ +DTCE_ICU_SWINT2,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMTW0_CMWI0, +DTCE_CMTW1_CMWI1, +DTCE_USB0_D0FIFO0,DTCE_USB0_D1FIFO0, +DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1, +DTCE_QSPI_SPRI,DTCE_QSPI_SPTI, +DTCE_SDHI_SBFAI, +DTCE_MMCIF_MBFAI, +DTCE_SSIE0_SSITXI0,DTCE_SSIE0_SSIRXI0, +DTCE_SSIE1_SSIRTI1, +DTCE_RIIC1_RXI1,DTCE_RIIC1_TXI1, +DTCE_RIIC0_RXI0,DTCE_RIIC0_TXI0, +DTCE_RIIC2_RXI2,DTCE_RIIC2_TXI2, +DTCE_SCI0_RXI0,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2,DTCE_SCI2_TXI2, +DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI3_RXI3,DTCE_SCI3_TXI3, +DTCE_SCI4_RXI4,DTCE_SCI4_TXI4, +DTCE_SCI5_RXI5,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_PDC_PCDFI, +DTCE_SCI7_RXI7,DTCE_SCI7_TXI7, +DTCE_SCI8_RXI8,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9,DTCE_SCI9_TXI9, +DTCE_SCI10_RXI10,DTCE_SCI10_TXI10, +DTCE_RSPI2_SPRI2,DTCE_RSPI2_SPTI2, +DTCE_SCI11_RXI11,DTCE_SCI11_TXI11, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_DMAC_DMAC0I,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_PERIB_INTB128,DTCE_PERIB_INTB129,DTCE_PERIB_INTB130,DTCE_PERIB_INTB131,DTCE_PERIB_INTB132, +DTCE_PERIB_INTB133,DTCE_PERIB_INTB134,DTCE_PERIB_INTB135,DTCE_PERIB_INTB136,DTCE_PERIB_INTB137, +DTCE_PERIB_INTB138,DTCE_PERIB_INTB139,DTCE_PERIB_INTB140,DTCE_PERIB_INTB141,DTCE_PERIB_INTB142, +DTCE_PERIB_INTB143,DTCE_PERIB_INTB144,DTCE_PERIB_INTB145,DTCE_PERIB_INTB146,DTCE_PERIB_INTB147, +DTCE_PERIB_INTB148,DTCE_PERIB_INTB149,DTCE_PERIB_INTB150,DTCE_PERIB_INTB151,DTCE_PERIB_INTB152, +DTCE_PERIB_INTB153,DTCE_PERIB_INTB154,DTCE_PERIB_INTB155,DTCE_PERIB_INTB156,DTCE_PERIB_INTB157, +DTCE_PERIB_INTB158,DTCE_PERIB_INTB159,DTCE_PERIB_INTB160,DTCE_PERIB_INTB161,DTCE_PERIB_INTB162, +DTCE_PERIB_INTB163,DTCE_PERIB_INTB164,DTCE_PERIB_INTB165,DTCE_PERIB_INTB166,DTCE_PERIB_INTB167, +DTCE_PERIB_INTB168,DTCE_PERIB_INTB169,DTCE_PERIB_INTB170,DTCE_PERIB_INTB171,DTCE_PERIB_INTB172, +DTCE_PERIB_INTB173,DTCE_PERIB_INTB174,DTCE_PERIB_INTB175,DTCE_PERIB_INTB176,DTCE_PERIB_INTB177, +DTCE_PERIB_INTB178,DTCE_PERIB_INTB179,DTCE_PERIB_INTB180,DTCE_PERIB_INTB181,DTCE_PERIB_INTB182, +DTCE_PERIB_INTB183,DTCE_PERIB_INTB184,DTCE_PERIB_INTB185,DTCE_PERIB_INTB186,DTCE_PERIB_INTB187, +DTCE_PERIB_INTB188,DTCE_PERIB_INTB189,DTCE_PERIB_INTB190,DTCE_PERIB_INTB191,DTCE_PERIB_INTB192, +DTCE_PERIB_INTB193,DTCE_PERIB_INTB194,DTCE_PERIB_INTB195,DTCE_PERIB_INTB196,DTCE_PERIB_INTB197, +DTCE_PERIB_INTB198,DTCE_PERIB_INTB199,DTCE_PERIB_INTB200,DTCE_PERIB_INTB201,DTCE_PERIB_INTB202, +DTCE_PERIB_INTB203,DTCE_PERIB_INTB204,DTCE_PERIB_INTB205,DTCE_PERIB_INTB206,DTCE_PERIB_INTB207, +DTCE_PERIA_INTA208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212, +DTCE_PERIA_INTA213,DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217, +DTCE_PERIA_INTA218,DTCE_PERIA_INTA219,DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222, +DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225,DTCE_PERIA_INTA226,DTCE_PERIA_INTA227, +DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231,DTCE_PERIA_INTA232, +DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242, +DTCE_PERIA_INTA243,DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247, +DTCE_PERIA_INTA248,DTCE_PERIA_INTA249,DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252, +DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +}; + + +#if ((0 != BSP_CFG_USER_LOCKING_ENABLED) || (bsp_lock_t != BSP_CFG_USER_LOCKING_TYPE) \ + || (DTC_ENABLE != DTC_CFG_USE_DMAC_FIT_MODULE)) +/******************************************************************************* +* Function Name: r_dtc_check_DMAC_locking_byUSER +* Description : Checks all DMAC channel locking. +* Arguments : none - +* Return Value : true - +* All DMAC channels are unlocked. +* false - +* One or some DMAC channels are locked. +* +*******************************************************************************/ +bool r_dtc_check_DMAC_locking_byUSER(void) +{ + bool ret = true; + + /* User has to check the locking of DMAC by themselves. */ + /* do something */ + + return ret; +} +#endif + + +/******************************************************************************* +* Function Name: r_dtc_module_enable +* Description : Releases module stop state. +* Arguments : None +* Return Value : None +*******************************************************************************/ +void r_dtc_module_enable(void) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) +bsp_int_ctrl_t int_ctrl; +#endif + /* Enable writing to MSTP registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + /* Release from module stop state. */ + MSTP(DTC) = 0; + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + /* Disable writing to MSTP registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} +/****************************************************************************** + End of function r_dtc_module_enable + *****************************************************************************/ + +/******************************************************************************* +* Function Name: r_dtc_module_disable +* Description : Sets to module stop state. +* Arguments : None +* Return Value : None +*******************************************************************************/ +void r_dtc_module_disable(void) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) +bsp_int_ctrl_t int_ctrl; +#endif + /* Enable writing to MSTP registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + /* Set to module stop state. */ + MSTP(DTC) = 1; + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + /* Disable writing to MSTP registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} +/****************************************************************************** + End of function r_dtc_module_disable + *****************************************************************************/ + +#endif /* defined(BSP_MCU_RX72N) */ + +/* End of File */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h new file mode 100644 index 000000000..918d5456f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target.h +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ +#ifndef DTC_RX_TARGET_H +#define DTC_RX_TARGET_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +/* The number of activation sources */ +#if defined(BSP_MCU_RX72N) +#define DTC_NUM_INTERRUPT_SRC (204) +#endif /* defined(BSP_MCU_RX72N) */ + +#if (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) +/* Size of DTC Vector table and DTC Index table (in byte units) */ +#define DTC_VECTOR_TABLE_SIZE_BYTES (0x400 + 0x400 + 0x400) +#else +/* Size of DTC Vector table (in byte units) */ +#define DTC_VECTOR_TABLE_SIZE_BYTES (0x400 + 0x400) +#endif /* (DTC_ENABLE == DTC_CFG_USE_SEQUENCE_TRANSFER) */ + +/* Definition of num of DMAC channel. */ +#define DMAC_NUM_CHANNELS (8) + +/* DTC IP Version */ +#define DTC_IP (DTC_IP_VER_DTCb) + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif /* DTC_RX_TARGET_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h new file mode 100644 index 000000000..d2234ccf5 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target_if.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_dtc_rx_target_if.h +* Description : Functions for using DTC on RX72N. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 First Release for RX72N. +*******************************************************************************/ +#ifndef DTC_RX_TARGET_IF_H +#define DTC_RX_TARGET_IF_H + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +/* Transfer data configuration */ +typedef struct st_dtc_transfer_data_cfg { + dtc_transfer_mode_t transfer_mode; /* DTC transfer mode */ + dtc_data_size_t data_size; /* Size of data */ + dtc_src_addr_mode_t src_addr_mode; /* Address mode of source */ + dtc_chain_transfer_t chain_transfer_enable; /* Chain transfer is enabled or not. */ + dtc_chain_transfer_mode_t chain_transfer_mode; /* How chain transfer is performed. */ + dtc_interrupt_t response_interrupt; /* How response interrupt is raised */ + dtc_repeat_block_side_t repeat_block_side; /* The side being repeat or block in repeat / block transfer mode. */ + dtc_dest_addr_mode_t dest_addr_mode; /* Address mode of destination */ + uint32_t source_addr; /* Start address of source */ + uint32_t dest_addr; /* Start address of destination */ + uint32_t transfer_count; /* Transfer count */ + uint16_t block_size; /* Size of a block in block transfer mode */ + uint16_t rsv; /* Reserved */ + dtc_write_back_t writeback_disable; /* Write-back disable or enable */ + dtc_sequence_end_t sequence_end; /* Sequence transfer end or continue */ + dtc_refer_index_table_t refer_index_table_enable; /* Index table refer or not refer */ + dtc_disp_add_t disp_add_enable; /* The displacement value is added or not added */ +} dtc_transfer_data_cfg_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif /* DTC_RX_TARGET_IF_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h new file mode 100644 index 000000000..67885fe4a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/r_gpio_rx_if.h @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_if.h +* Description : General Purpose I/O driver for RX MCUs. This interface file has everything the user needs to use this +* module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 23.04.2014 1.20 Add support for RX63N, and RX110 +* : 28.05.2014 1.30 Add support for RX64M +* : 28.11.2014 1.40 Add support for RX113 +* : 02.09.2015 1.50 Add support for RX71M, increased the minor version number to 50. +* : Added GPIO_CMD_DSCR_DISABLE and GPIO_CMD_DSCR_ENABLE commands in gpio_cmd_t +* : 06.04.2015 1.60 Add support for RX231 +* : 30.09.2015 1.70 Add support for RX23T +* : 01.10.2015 1.80 Add support for RX130 +* : 01.12.2015 1.90 Add support for RX24T +* : 01.02.2016 2.00 Add support for RX230 +* : 15.06.2016 2.01 Added the demo of the RX64M group. +* : 01.10.2016 2.10 Add support for RX65N +* : 19.12.2016 2.20 Add support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Add support for RX65N-2M, RX130-512KB +* : 31.10.2017 2.31 Added the demo for RX65N, RX65N-2M +* : 28.09.2018 2.40 Add support for RX66T +* : 16.11.2018 2.41 Added XML document number +* : 01.02.2019 2.50 Add support for RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Removed support for Generation 1 devices. +* : 30.12.2019 3.40 Added support RX72N, RX66N +* : 31.03.2020 3.50 Added support for RX23E-A +***********************************************************************************************************************/ + +#ifndef GPIO_RX_INTERFACE_HEADER_FILE +#define GPIO_RX_INTERFACE_HEADER_FILE + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Module configuration. */ +#include "r_gpio_rx_config.h" + +/* Include specifics for chosen MCU. Go to the header file for your MCU to see available ports and pins. */ +#if defined(BSP_MCU_RX113) + #include "./src/targets/rx113/r_gpio_rx113.h" +#elif defined(BSP_MCU_RX110) + #include "./src/targets/rx110/r_gpio_rx110.h" +#elif defined(BSP_MCU_RX111) + #include "./src/targets/rx111/r_gpio_rx111.h" +#elif defined(BSP_MCU_RX130) + #include "./src/targets/rx130/r_gpio_rx130.h" +#elif defined(BSP_MCU_RX13T) + #include "./src/targets/rx13t/r_gpio_rx13t.h" +#elif defined(BSP_MCU_RX230) + #include "./src/targets/rx230/r_gpio_rx230.h" +#elif defined(BSP_MCU_RX231) + #include "./src/targets/rx231/r_gpio_rx231.h" +#elif defined(BSP_MCU_RX23T) + #include "./src/targets/rx23t/r_gpio_rx23t.h" +#elif defined(BSP_MCU_RX23W) + #include "./src/targets/rx23w/r_gpio_rx23w.h" +#elif defined(BSP_MCU_RX23E_A) + #include "./src/targets/rx23e-a/r_gpio_rx23e-a.h" +#elif defined(BSP_MCU_RX24T) + #include "./src/targets/rx24t/r_gpio_rx24t.h" +#elif defined(BSP_MCU_RX24U) + #include "./src/targets/rx24u/r_gpio_rx24u.h" +#elif defined(BSP_MCU_RX64M) + #include "./src/targets/rx64m/r_gpio_rx64m.h" +#elif defined(BSP_MCU_RX65N) + #include "./src/targets/rx65n/r_gpio_rx65n.h" +#elif defined(BSP_MCU_RX66T) + #include "./src/targets/rx66t/r_gpio_rx66t.h" +#elif defined(BSP_MCU_RX66N) + #include "./src/targets/rx66n/r_gpio_rx66n.h" +#elif defined(BSP_MCU_RX71M) + #include "./src/targets/rx71m/r_gpio_rx71m.h" +#elif defined(BSP_MCU_RX72T) + #include "./src/targets/rx72t/r_gpio_rx72t.h" +#elif defined(BSP_MCU_RX72M) + #include "./src/targets/rx72m/r_gpio_rx72m.h" +#elif defined(BSP_MCU_RX72N) + #include "./src/targets/rx72n/r_gpio_rx72n.h" +#else + #error "This MCU is not supported by the current r_gpio_rx module." +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define GPIO_RX_VERSION_MAJOR (3) +#define GPIO_RX_VERSION_MINOR (50) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The gpio_port_t and gpio_port_pin_t enums are located in the 'targets' folder for each MCU. For example, to see + * these enums for a RX111 look at the following file: r_gpio_rx/src/targets/rx111/r_gpio_rx111.h + */ + +/* Levels that can be set and read for individual pins. */ +typedef enum +{ + GPIO_LEVEL_LOW = 0, + GPIO_LEVEL_HIGH +} gpio_level_t; + +/* Options that can be used with the R_GPIO_PortDirectionSet() and R_GPIO_PinDirectionSet() functions. */ +typedef enum +{ + GPIO_DIRECTION_INPUT = 0, + GPIO_DIRECTION_OUTPUT +} gpio_dir_t; + +/* Commands that can be used with the R_GPIO_PinControl() function. This list will vary depending on the MCU chosen. */ +typedef enum +{ + GPIO_CMD_OUT_CMOS = 0, + GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN, + GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN, + GPIO_CMD_IN_PULL_UP_DISABLE, + GPIO_CMD_IN_PULL_UP_ENABLE, + GPIO_CMD_ASSIGN_TO_PERIPHERAL, + GPIO_CMD_ASSIGN_TO_GPIO, + GPIO_CMD_DSCR_DISABLE, + GPIO_CMD_DSCR_ENABLE, + GPIO_CMD_DSCR2_DISABLE, + GPIO_CMD_DSCR2_ENABLE +} gpio_cmd_t; + +/* Function return type. */ +typedef enum +{ + GPIO_SUCCESS = 0, + GPIO_ERR_INVALID_MODE, // The mode specified cannot be applied to this pin + GPIO_ERR_INVALID_CMD // The input command is not supported +} gpio_err_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_GPIO_PortWrite(gpio_port_t port, uint8_t value); +uint8_t R_GPIO_PortRead(gpio_port_t port); +void R_GPIO_PortDirectionSet(gpio_port_t port, gpio_dir_t dir, uint8_t mask); +void R_GPIO_PinWrite(gpio_port_pin_t pin, gpio_level_t level); +gpio_level_t R_GPIO_PinRead(gpio_port_pin_t pin); +void R_GPIO_PinDirectionSet(gpio_port_pin_t pin, gpio_dir_t dir); +gpio_err_t R_GPIO_PinControl(gpio_port_pin_t pin, gpio_cmd_t cmd); +uint32_t R_GPIO_GetVersion(void); + +#endif /* GPIO_RX_INTERFACE_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/readme.txt new file mode 100644 index 000000000..87c7b140f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/readme.txt @@ -0,0 +1,50 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS MODULE FOR MORE INFORMATION + +r_gpio_rx +========= + +Overview +-------- +This code implements a General Purpose Input/Output driver. Common features such as reading, writing, and setting the +direction of ports and pins are supported. Enabling features such as open-drain outputs and internal pull-ups are also +supported. + +Features +-------- +* Read ports and pins +* Write ports and pins +* Set ports and pins as inputs and outputs +* Enable features of pins such as internal pull-ups or open-drain outputs + +File Structure +-------------- +r_gpio_rx +| readme.txt +| r_gpio_rx_if.h +| ++---doc +| +---ja +| | r01an1721jj{VERSION_NUMBER}-rx-gpio.pdf +| +---en +| r01an1721ej{VERSION_NUMBER}-rx-gpio.pdf +| ++---ref +| r_gpio_rx_config_reference.h +| +\---src + | r_gpio_rx.c + | + \---targets + +---rx110 + | r_gpio_rx110.c + | r_gpio_rx110.h + | + +---rx111 + | r_gpio_rx111.c + | r_gpio_rx111.h + | + : + +r_config + r_gpio_rx_config.h + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h new file mode 100644 index 000000000..bfeb0766e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/ref/r_gpio_rx_config_reference.h @@ -0,0 +1,46 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c new file mode 100644 index 000000000..8ddb93940 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/r_gpio_rx.c @@ -0,0 +1,573 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx.c +* Description : General Purpose Input/Output driver for RX MCUs. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 21.11.2014 1.40 Added support for RX113 +* : 02.09.2015 1.50 Added support for RX71M +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR_ENABLE/_DISABLE commands. +* : 01.10.2016 2.10 Added support for RX65N +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR2_ENABLE/_DISABLE commands. +* : 19.12.2016 2.20 Added support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Added support for RX65N-2M, RX130-512KB. +* : 28.09.2018 2.40 Added support for RX66T. +* Update according to GSCE Code Checker +* : 01.02.2019 2.50 Added support for RX72T, RX65N-64pin +* Update according to GSCE Code Checker +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Modified comment of API function to Doxygen style. +* : 30.12.2019 3.40 Added support RX72N, RX66N. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +* Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Typedef definitions +***********************************************************************************************************************/ +/* Different pin output options. */ +typedef enum +{ + GPIO_PIN_OUT_CMOS = 0, + GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN = 1, + GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN = 2 +} gpio_pin_output_t; + +/*********************************************************************************************************************** +* Private global variables and functions +***********************************************************************************************************************/ +uint8_t volatile * gpio_port_addr_get(uint8_t volatile * base_addr, uint16_t index); +bool gpio_pin_function_check(uint8_t const * check_array, uint8_t port_number, uint8_t pin_number); +void gpio_set_output_type(gpio_port_pin_t pin, gpio_pin_output_t out_type); + +/*********************************************************************************************************************** +* Export global variables +***********************************************************************************************************************/ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + extern const uint8_t g_gpio_open_drain_n_support[]; + extern const uint8_t g_gpio_open_drain_p_support[]; + extern const uint8_t g_gpio_pull_up_support[]; + #if defined (GPIO_DSCR_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr_support[]; + #endif + #if defined (GPIO_DSCR2_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr2_support[]; + #endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortWrite +********************************************************************************************************************//** +* @brief This function writes the levels of all pins on a port. +* @param[in] port - Which port to write to. See Section 2.10.1, Ports. +* @param[in] value - The value to write to the port. Each bit corresponds to a pin on the port (e.g. bit 0 of value +* will be written to pin 0 on supplied port) +* @details The input value will be written to the specified port. Each bit in the value parameter corresponds to a pin +* on the port. For example, bit 7 of write value corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* @note In the interest of performance, this function does not automatically check for non-existent pins when the +* port-wide write function is called. It is up to the user’s application to insure that only valid pins are written to. +* +*/ +void R_GPIO_PortWrite (gpio_port_t port, uint8_t value) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)port); + + /* Write to the selected port. */ + *podr = value; +} /* End of function R_GPIO_PortWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortRead +********************************************************************************************************************//** +* @brief This function reads the levels of all pins on a port. +* @param[in] port - Which port to read. See Section 2.10.1, Ports. +* @return The value of the port. +* @details The specified port will be read, and the levels for all the pins will be returned. Each bit in the returned +* value corresponds to a pin on the port. For example, bit 7 of read value corresponds to pin 7, bit 6 corresponds to +* pin 6, and so forth. +*/ +uint8_t R_GPIO_PortRead (gpio_port_t port) +{ + /* PIDR register addresses are incremental in memory starting with PORT0.PIDR. Even if a port is not available + * on this MCU, the address is reserved. */ + + /* Read the selected port. */ + return *gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)port); +} /* End of function R_GPIO_PortRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortDirectionSet +********************************************************************************************************************//** +* @brief This function sets multiple pins on a port to inputs or outputs at once. +* @param[in] port - Which port to use. See Section 2.10.1, Ports. +* @param[in] dir - Which direction to use. See Section 2.10.5, Pin Direction. +* @param[in] mask - Mask of which pins to change. 1 = set direction, 0 = do not change. +* @details Multiple pins on a port can be set to inputs or outputs at once. Each bit in the mask parameter corresponds +* to a pin on the port. For example, bit 7 of mask corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* If a bit is set to 1 then the corresponding pin will be changed to an input or output as specified by the dir +* parameter. If a bit is set to 0 then the direction of the pin will not be changed. +* @note This function does not allow the user to specify the use of special modes such as input pull-up resistors or +* open-drain outputs. To enable these modes use the R_GPIO_PinControl() function. +*/ +void R_GPIO_PortDirectionSet (gpio_port_t port, gpio_dir_t dir, uint8_t mask) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)port); + + /* Write to the selected register. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) & (~mask)); + } + else + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) | mask); + } +} /* End of function R_GPIO_PortDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinWrite +********************************************************************************************************************//** +* @brief This function sets the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] level - What level to set the pin to. +* @details Pins can either be set as high (‘1’) or low (‘0’). +*/ +void R_GPIO_PinWrite (gpio_port_pin_t pin, gpio_level_t level) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_LEVEL_LOW == level) + { + /* Set value to port */ + *podr = (uint8_t)((*podr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Set value to port */ + *podr = (uint8_t)((*podr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinRead +********************************************************************************************************************//** +* @brief This function reads the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @return The level of the specified pin. +* @details The specified pin will be read and the level returned. +*/ +gpio_level_t R_GPIO_PinRead (gpio_port_pin_t pin) +{ + uint8_t volatile * pidr; + + /* PIDR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pidr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)pin); + + /* Mask to get the individual bit. */ + if (((*pidr) & (1 << (pin & 0x00FFu))) != 0) + { + return GPIO_LEVEL_HIGH; + } + else + { + return GPIO_LEVEL_LOW; + } +} /* End of function R_GPIO_PinRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinDirectionSet +********************************************************************************************************************//** +* @brief This function sets the direction (input/output) of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] dir - Which direction to use for this pin. See Section 2.10.5, Pin Direction. +* @details This function sets pins as inputs or outputs. For enabling other settings such as open-drain outputs or +* internal pull-ups see the R_GPIO_PinControl() function. +*/ +void R_GPIO_PinDirectionSet (gpio_port_pin_t pin, gpio_dir_t dir) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinControl +********************************************************************************************************************//** +* @brief This function allows the user to control various settings of a pin. +* @param[in] pin -Which pin to use. See Section 2.10.2, Pins +* @param[in] cmd - Which command to execute for this pin. See Section 2.10.6, Control Commands for available commands. +* @retval [GPIO_SUCCESS] Successful; pin modified as specified by command. +* @retval [GPIO_ERR_INVALID_MODE] Error; this pin does not support the specified option. +* @retval [GPIO_ERR_INVALID_CMD] Error; the input command is not supported. +* @details Depending on the MCU, pins have various settings that can be configured other than the direction and +* output level. Some examples include enabling open-drain outputs, internal pull-ups, and changing drive capacity +* levels. These features vary per chip which means that the options for this function will also vary. +*/ +gpio_err_t R_GPIO_PinControl (gpio_port_pin_t pin, gpio_cmd_t cmd) +{ + gpio_err_t err; + uint8_t volatile * addr; + uint8_t pin_number; + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + uint8_t port_number; + + /* Get port number */ + port_number = (uint8_t)(pin >> 8); +#endif + + err = GPIO_SUCCESS; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + switch (cmd) + { + +#if defined (GPIO_DSCR_IS_SUPPORTED) + case GPIO_CMD_DSCR_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + case GPIO_CMD_DSCR_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* GPIO_DSCR_IS_SUPPORTED */ +#if defined (GPIO_DSCR2_IS_SUPPORTED) + case GPIO_CMD_DSCR2_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_DSCR2_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* GPIO_DSCR2_IS_SUPPORTED */ + case GPIO_CMD_ASSIGN_TO_GPIO: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_ASSIGN_TO_PERIPHERAL: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_IN_PULL_UP_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_IN_PULL_UP_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_OUT_CMOS: + { + gpio_set_output_type(pin, GPIO_PIN_OUT_CMOS); + + break; + } + + case GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_n_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN); + + break; + } + case GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN: + { + #if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_p_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } + #endif + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN); + + break; + } + + default: + { + err = GPIO_ERR_INVALID_CMD; + break; + } + } + + return err; +} /* End of function R_GPIO_PinControl */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_GetVersion +********************************************************************************************************************//** +* @brief Returns the current version of this API. +* @return Version of this API. +* @details This function will return the version of the currently running API. The version number is encoded where +* the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example, +* Version 4.25 would be returned as 0x00040019. +*/ +uint32_t R_GPIO_GetVersion (void) +{ + /* These version macros are defined in r_gpio_rx_if.h. */ + return ((((uint32_t)GPIO_RX_VERSION_MAJOR) << 16) | (uint32_t)GPIO_RX_VERSION_MINOR); +} /* End of function R_GPIO_GetVersion */ + +/*********************************************************************************************************************** +* Function Name: gpio_port_addr_get +* Description : Get the address for a port register based on a base port register address. +* Arguments : base_addr - +* First port register of this type (e.g. &PORT0.PODR.BYTE) +* index - +* Index off the base. (e.g. for PORT4 it would be 0x0400) +* Return Value : Address of the register that was requested +***********************************************************************************************************************/ + +R_BSP_PRAGMA_INLINE (gpio_port_addr_get) +uint8_t volatile * gpio_port_addr_get (uint8_t volatile * base_addr, uint16_t index) +{ + /* Add port number to 'index' to correct register. */ + return (uint8_t volatile *)((((uint32_t)index >> 8) & 0x000000FFuL) + (uint32_t)base_addr); +} /* End of function gpio_port_addr_get */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +/*********************************************************************************************************************** +* Function Name: gpio_pin_function_check +* Description : Checks to see if a pin supports a certain function. +* Arguments : check_array - +* Which support array to use. +* port_number - +* Which port to use. +* pin_number - +* Which pin to use. +* Return Value : true - +* Functionality is supported on this pin. +* false - +* Functionality is not supported on this pin. +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE (gpio_pin_function_check) +bool gpio_pin_function_check (uint8_t const * check_array, uint8_t port_number, uint8_t pin_number) +{ + if ((check_array[port_number] & (1 << pin_number)) != 0) + { + return true; + } + else + { + return false; + } +} /* End of function gpio_pin_function_check */ +#endif + +/*********************************************************************************************************************** +* Function Name: gpio_set_output_type +* Description : Configures pin output type (e.g. CMOS, open-drain) +* Arguments : pin - +* Which pin to change output type for +* out_type - +* What output type to use for this pin +* Return Value : None +***********************************************************************************************************************/ +void gpio_set_output_type (gpio_port_pin_t pin, gpio_pin_output_t out_type) +{ + uint8_t volatile * addr; + uint8_t pin_number; + uint8_t bit_offset; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + /* 'pin' is multiplied by 2 because the ODR0 and ODR1 registers are staggered. This means that PORT0.ODR0 + * and PORT1.ODR0 are separated by 2 bytes instead of 1 as with the other port registers. */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUT_TYPE, (uint16_t)(((uint16_t)pin)*2)); + + /* ODR bit fields are 2-bits a piece. This means bits 0-3 are in the 1st byte (ODR0) and bits 4-7 are in + * the 2nd byte (ODR1). + */ + if (pin_number > 3) + { + /* Bit field is in ODR1. Increment address by 1 for ODR1 register for this port. */ + addr += 1; + + /* Subtract 4 from pin number since pins 4-7 are stored in ODR1 which is an 8-bit register. + * Multiple pin number by 2 since each pin is represented by 2 bits. + */ + bit_offset = (uint8_t)((pin_number - 4) * 2); + } + else + { + /* Multiple pin number by 2 since each pin is represented by 2 bits. */ + bit_offset = (uint8_t)(pin_number * 2); + } + + /* Clear the bits we intend to change. */ + *addr = (uint8_t)((*addr) & (~(3 << bit_offset))); + + /* Set the bits again if needed. */ + *addr = (uint8_t)((*addr) | (((uint8_t)out_type) << bit_offset)); +} /* End of function gpio_set_output_type */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c new file mode 100644 index 000000000..2d8a61f6f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.c @@ -0,0 +1,206 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx72n.c +* Description : Data for r_gpio_rx driver specific to RX72N. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" + +#if defined(BSP_MCU_RX72N) + +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* These arrays hold which pins have extra functionality. For example, not all pins have the option of enabling + * open-drain N-channel output instead of the default CMOS output. Each entry in the array corresponds to a port. + * Each bit in each entry corresponds to a pin on that port. If bit 3 of array entry [4] was set to 1 then that would + * mean that PORT 4 PIN 3 supported the feature that array represented. + * + * These arrays are only used when GPIO_CFG_PARAM_CHECKING_ENABLE is set to 1 (checking enabled). If you know that + * your code does not need to check the pins then you can set this macro to 0 and save a little execution time + * and ROM space. + * + * Note: These arrays are defined for the largest package part. For smaller packages where some pins do not exist, + * pin checking is filtered by the enumerated port_pin list for that package as defined in r_gpio_rx72n.h. + */ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0xAF, // P0: P00 to P03, P05, P07 + 0xFF, // P1: P10 to P17 + 0xFF, // P2: P20 to P27 + 0xDF, // P3: P30 to P34, P36, P37 + 0xFF, // P4: P40 to P47 + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFF, // P7: P70 to P77 + 0xFF, // P8: P80 to P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x3F, // PF: PF0 to PF5 + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x2F, // PJ: PJ0 to PJ3, PJ5 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, // P0: - + 0x00, // P1: - + 0x00, // P2: - + 0x00, // P3: - + 0x00, // P4: - + 0x00, // P5: - + 0x00, // P6: - + 0x00, // P7: - + 0x00, // P8: - + 0x00, // P9: - + 0x00, // PA: - + 0x00, // PB: - + 0x00, // PC: - + 0x00, // PD: - + 0x02, // PE: PE1 + 0x00, // PF: - + 0x00, // PG: - + 0x00, // PH: - + 0x00, // PJ: - + 0x00, // PK: - + 0x00, // PL: - + 0x00, // PM: - + 0x00, // PN: - + 0x00, // PQ: - +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0xAF, // P0: P00 to P03, P05, P07 + 0xFF, // P1: P10 to P17 + 0xFF, // P2: P20 to P27 + 0xDF, // P3: P30 to P34, P36, P37 + 0xFF, // P4: P40 to P47 + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFF, // P7: P70 to P77 + 0xFF, // P8: P80 to P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x3F, // PF: PF0 to PF5 + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x2F, // PJ: PJ0 to PJ3, PJ5 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_dscr_support[GPIO_INFO_NUM_PORTS] = +{ + 0x07, // P0: P00 to P02 + 0x1E, // P1: P11 to P14 + 0x80, // P2: P27 + 0x00, // P3: - + 0x00, // P4: - + 0xF7, // P5: P50 to P52, P54 to P57 + 0x00, // P6: - + 0xF4, // P7: P72, P74 to P77 + 0x3F, // P8: P80 to P85 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x00, // PF: - + 0x03, // PG: PG0, PG1 + 0xFF, // PH: PH0 to PH7 + 0x07, // PJ: PJ0 to PJ2 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +const uint8_t g_gpio_dscr2_support[GPIO_INFO_NUM_PORTS] = +{ + 0x07, // P0: P00 to P02 + 0x9E, // P1: P11 to P14, P17 + 0x8F, // P2: P20 to P23, P27 + 0x03, // P3: P30, P31 + 0x00, // P4: - + 0xFF, // P5: P50 to P57 + 0xFF, // P6: P60 to P67 + 0xFD, // P7: P70, P72 to P77 + 0xBF, // P8: P80 to P85, P87 + 0xFF, // P9: P90 to P97 + 0xFF, // PA: PA0 to PA7 + 0xFF, // PB: PB0 to PB7 + 0xFF, // PC: PC0 to PC7 + 0xFF, // PD: PD0 to PD7 + 0xFF, // PE: PE0 to PE7 + 0x00, // PF: - + 0xFF, // PG: PG0 to PG7 + 0xFF, // PH: PH0 to PH7 + 0x07, // PJ: PJ0 to PJ2 + 0xFF, // PK: PK0 to PK7 + 0xFF, // PL: PL0 to PL7 + 0xFF, // PM: PM0 to PM7 + 0x3F, // PN: PN0 to PN5 + 0xFF, // PQ: PQ0 to PQ7 +}; + +#endif /* GPIO_CFG_PARAM_CHECKING_ENABLE */ + +#endif /* BSP_MCU_RX72N */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h new file mode 100644 index 000000000..6734a9632 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_gpio_rx/src/targets/rx72n/r_gpio_rx72n.h @@ -0,0 +1,810 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx72n.h +* Description : Specifics for the r_gpio_rx driver for the RX72N. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ +#ifndef GPIO_RX72N +#define GPIO_RX72N + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +#if defined(BSP_MCU_RX72N) /* Prevents the compiler from finding multiple definitions of constant in this file. */ + +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* General information about number of ports and pins on this device. */ +#define GPIO_INFO_NUM_PORTS (24) + +#if (BSP_PACKAGE_PINS == 224) + #define GPIO_INFO_NUM_PINS (183) +#elif (BSP_PACKAGE_PINS == 176) + #define GPIO_INFO_NUM_PINS (137) +#elif (BSP_PACKAGE_PINS == 145 || BSP_PACKAGE_PINS == 144) + #define GPIO_INFO_NUM_PINS (112) +#elif (BSP_PACKAGE_PINS == 100) + #define GPIO_INFO_NUM_PINS (79) +#else + #error "r_gpio_rx does not have information about this RX72N package. Please update r_gpio_rx72N.h" +#endif + +/* For testing we will allocate virtual IO ports. */ +#if !defined(GPIO_TESTING) +/* Base registers used for offsets on output data registers. */ +#define GPIO_PRV_BASE_ADDR_OUTPUT ((uint8_t volatile *)&PORT0.PODR.BYTE) +/* Base registers used for offsets on input data registers. */ +#define GPIO_PRV_BASE_ADDR_INPUT ((uint8_t volatile *)&PORT0.PIDR.BYTE) +/* Base registers used for offsets on direction registers. */ +#define GPIO_PRV_BASE_ADDR_DIRECTION ((uint8_t volatile *)&PORT0.PDR.BYTE) +/* Base registers used for offsets on mode registers. */ +#define GPIO_PRV_BASE_ADDR_MODE ((uint8_t volatile *)&PORT0.PMR.BYTE) +/* Base registers used for offsets on output type registers. */ +#define GPIO_PRV_BASE_ADDR_OUT_TYPE ((uint8_t volatile *)&PORT0.ODR0.BYTE) +/* Base registers used for offsets on pull-up registers. */ +#define GPIO_PRV_BASE_ADDR_PULL_UP ((uint8_t volatile *)&PORT0.PCR.BYTE) +/* Base registers used for offsets on drive capacity control registers. */ +#define GPIO_PRV_BASE_ADDR_DSCR ((uint8_t volatile *)&PORT0.DSCR.BYTE) +/* Base registers used for offsets on drive capacity control registers 2. (high-speed interface high-drive) */ +#define GPIO_PRV_BASE_ADDR_DSCR2 ((uint8_t volatile *)&PORT0.DSCR2.BYTE) + +#endif + +#define GPIO_DSCR_IS_SUPPORTED /* High-drive output is supported for the RX72N */ +#define GPIO_DSCR2_IS_SUPPORTED /* Large current output, high-drive output is supported for the RX72N */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (BSP_PACKAGE_PINS == 224) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200, + GPIO_PORT_K = 0x1300, + GPIO_PORT_L = 0x1400, + GPIO_PORT_M = 0x1500, + GPIO_PORT_N = 0x1600, + GPIO_PORT_Q = 0x1700, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFF, /* Available pins: P10 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0xFF, /* Available pins: P50 to P57 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xFF, /* Available pins: P80 to P87 */ + GPIO_PORT9_PIN_MASK = 0xFF, /* Available pins: P90 to P97 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x3F, /* Available pins: PF0 to PF5 */ + GPIO_PORTG_PIN_MASK = 0xFF, /* Available pins: PG0 to PG7 */ + GPIO_PORTH_PIN_MASK = 0xFF, /* Available pins: PH0 to PH7 */ + GPIO_PORTJ_PIN_MASK = 0x2F, /* Available pins: PJ0 to PJ3, PJ5 */ + GPIO_PORTK_PIN_MASK = 0xFF, /* Available pins: PK0 to PK7 */ + GPIO_PORTL_PIN_MASK = 0xFF, /* Available pins: PL0 to PL7 */ + GPIO_PORTM_PIN_MASK = 0xFF, /* Available pins: PM0 to PM7 */ + GPIO_PORTN_PIN_MASK = 0x3F, /* Available pins: PN0 to PN5 */ + GPIO_PORTQ_PIN_MASK = 0xFF, /* Available pins: PQ0 to PQ7 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_5_PIN_7 = 0x0507, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_4 = 0x0804, + GPIO_PORT_8_PIN_5 = 0x0805, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_9_PIN_7 = 0x0907, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_0 = 0x0F00, + GPIO_PORT_F_PIN_1 = 0x0F01, + GPIO_PORT_F_PIN_2 = 0x0F02, + GPIO_PORT_F_PIN_3 = 0x0F03, + GPIO_PORT_F_PIN_4 = 0x0F04, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_G_PIN_0 = 0x1000, + GPIO_PORT_G_PIN_1 = 0x1001, + GPIO_PORT_G_PIN_2 = 0x1002, + GPIO_PORT_G_PIN_3 = 0x1003, + GPIO_PORT_G_PIN_4 = 0x1004, + GPIO_PORT_G_PIN_5 = 0x1005, + GPIO_PORT_G_PIN_6 = 0x1006, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_H_PIN_4 = 0x1104, + GPIO_PORT_H_PIN_5 = 0x1105, + GPIO_PORT_H_PIN_6 = 0x1106, + GPIO_PORT_H_PIN_7 = 0x1107, + GPIO_PORT_J_PIN_0 = 0x1200, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_2 = 0x1202, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, + GPIO_PORT_K_PIN_0 = 0x1300, + GPIO_PORT_K_PIN_1 = 0x1301, + GPIO_PORT_K_PIN_2 = 0x1302, + GPIO_PORT_K_PIN_3 = 0x1303, + GPIO_PORT_K_PIN_4 = 0x1304, + GPIO_PORT_K_PIN_5 = 0x1305, + GPIO_PORT_K_PIN_6 = 0x1306, + GPIO_PORT_K_PIN_7 = 0x1307, + GPIO_PORT_L_PIN_0 = 0x1400, + GPIO_PORT_L_PIN_1 = 0x1401, + GPIO_PORT_L_PIN_2 = 0x1402, + GPIO_PORT_L_PIN_3 = 0x1403, + GPIO_PORT_L_PIN_4 = 0x1404, + GPIO_PORT_L_PIN_5 = 0x1405, + GPIO_PORT_L_PIN_6 = 0x1406, + GPIO_PORT_L_PIN_7 = 0x1407, + GPIO_PORT_M_PIN_0 = 0x1500, + GPIO_PORT_M_PIN_1 = 0x1501, + GPIO_PORT_M_PIN_2 = 0x1502, + GPIO_PORT_M_PIN_3 = 0x1503, + GPIO_PORT_M_PIN_4 = 0x1504, + GPIO_PORT_M_PIN_5 = 0x1505, + GPIO_PORT_M_PIN_6 = 0x1506, + GPIO_PORT_M_PIN_7 = 0x1507, + GPIO_PORT_N_PIN_0 = 0x1600, + GPIO_PORT_N_PIN_1 = 0x1601, + GPIO_PORT_N_PIN_2 = 0x1602, + GPIO_PORT_N_PIN_3 = 0x1603, + GPIO_PORT_N_PIN_4 = 0x1604, + GPIO_PORT_N_PIN_5 = 0x1605, + GPIO_PORT_Q_PIN_0 = 0x1700, + GPIO_PORT_Q_PIN_1 = 0x1701, + GPIO_PORT_Q_PIN_2 = 0x1702, + GPIO_PORT_Q_PIN_3 = 0x1703, + GPIO_PORT_Q_PIN_4 = 0x1704, + GPIO_PORT_Q_PIN_5 = 0x1705, + GPIO_PORT_Q_PIN_6 = 0x1706, + GPIO_PORT_Q_PIN_7 = 0x1707, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 176) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFF, /* Available pins: P10 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0xFF, /* Available pins: P50 to P57 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xFF, /* Available pins: P80 to P87 */ + GPIO_PORT9_PIN_MASK = 0xFF, /* Available pins: P90 to P97 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x3F, /* Available pins: PF0 to PF5 */ + GPIO_PORTG_PIN_MASK = 0xFF, /* Available pins: PG0 to PG7 */ + GPIO_PORTJ_PIN_MASK = 0x2F, /* Available pins: PJ0 to PJ3, PJ5 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_5_PIN_7 = 0x0507, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_4 = 0x0804, + GPIO_PORT_8_PIN_5 = 0x0805, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_9_PIN_7 = 0x0907, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_0 = 0x0F00, + GPIO_PORT_F_PIN_1 = 0x0F01, + GPIO_PORT_F_PIN_2 = 0x0F02, + GPIO_PORT_F_PIN_3 = 0x0F03, + GPIO_PORT_F_PIN_4 = 0x0F04, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_G_PIN_0 = 0x1000, + GPIO_PORT_G_PIN_1 = 0x1001, + GPIO_PORT_G_PIN_2 = 0x1002, + GPIO_PORT_G_PIN_3 = 0x1003, + GPIO_PORT_G_PIN_4 = 0x1004, + GPIO_PORT_G_PIN_5 = 0x1005, + GPIO_PORT_G_PIN_6 = 0x1006, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_J_PIN_0 = 0x1200, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_2 = 0x1202, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 145 || BSP_PACKAGE_PINS == 144) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_F = 0x0F00, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xAF, /* Available pins: P00 to P03, P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x7F, /* Available pins: P50 to P56 */ + GPIO_PORT6_PIN_MASK = 0xFF, /* Available pins: P60 to P67 */ + GPIO_PORT7_PIN_MASK = 0xFF, /* Available pins: P70 to P77 */ + GPIO_PORT8_PIN_MASK = 0xCF, /* Available pins: P80 to P83, P86, P87 */ + GPIO_PORT9_PIN_MASK = 0x0F, /* Available pins: P90 to P93 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTF_PIN_MASK = 0x32, /* Available pins: PF5 */ + GPIO_PORTJ_PIN_MASK = 0x40, /* Available pins: PJ3, PJ5 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_0_PIN_2 = 0x0002, + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_5_PIN_6 = 0x0506, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_6_PIN_6 = 0x0606, + GPIO_PORT_6_PIN_7 = 0x0607, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_7_PIN_7 = 0x0707, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_8_PIN_3 = 0x0803, + GPIO_PORT_8_PIN_6 = 0x0806, + GPIO_PORT_8_PIN_7 = 0x0807, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_F_PIN_5 = 0x0F05, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_5 = 0x1205, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 100) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xA0, /* Available pins: P05, P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x3F, /* Available pins: P50 to P55 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTJ_PIN_MASK = 0x08, /* Available pins: PJ3 */ +} gpio_pin_bit_mask_t; + +typedef enum +{ + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_J_PIN_3 = 0x1203, +} gpio_port_pin_t; + +#endif /* BSP_PACKAGE_PINS */ + + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* BSP_MCU_RX72N */ +#endif /* GPIO_RX72N */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/Pin.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/Pin.c new file mode 100644 index 000000000..83f7e8575 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/Pin.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.c +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Pins_Create +* Description : This function initializes Smart Configurator pins +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Pins_Create(void) +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set CLKOUT25M pin */ + MPC.P56PFS.BYTE = 0x2AU; + PORT5.PMR.BYTE |= 0x40U; + + /* Set RXD2 pin */ + MPC.P12PFS.BYTE = 0x0AU; + PORT1.PMR.BYTE |= 0x04U; + + /* Set RXD9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BYTE |= 0x40U; + + /* Set TXD2 pin */ + PORT1.PODR.BYTE |= 0x08U; + MPC.P13PFS.BYTE = 0x0AU; + PORT1.PDR.BYTE |= 0x08U; + // PORT1.PMR.BIT.B3 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD9 pin */ + PORTB.PODR.BYTE |= 0x80U; + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PDR.BYTE |= 0x80U; + // PORTB.PMR.BIT.B7 = 1U; // Please set the PMR bit after TE bit is set to 1. + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/Pin.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/Pin.h new file mode 100644 index 000000000..563b57a07 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/Pin.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.h +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +#ifndef PIN_H +#define PIN_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Pins_Create(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_pinset.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_pinset.h new file mode 100644 index 000000000..33cd297df --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_pinset.h @@ -0,0 +1,34 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_pinset.h.h +* Version : 1.0.1 +* Description : Declares all pin code headers into a single file +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +#ifndef R_PINSET_H +#define R_PINSET_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" + +#endif /* R_PINSET_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_sci_rx_pinset.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_sci_rx_pinset.c new file mode 100644 index 000000000..8b23ce348 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_sci_rx_pinset.c @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.c +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" +#include "platform.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI2 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI2() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD2/SMISO2 pin */ + MPC.P12PFS.BYTE = 0x0AU; + PORT1.PMR.BIT.B2 = 1U; + + /* Set TXD2/SMOSI2 pin */ + MPC.P13PFS.BYTE = 0x0AU; + PORT1.PMR.BIT.B3 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI9 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI9() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD9/SMISO9/SSCL9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B6 = 1U; + + /* Set TXD9/SMOSI9/SSDA9 pin */ + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B7 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_sci_rx_pinset.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_sci_rx_pinset.h new file mode 100644 index 000000000..2212975ba --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_pincfg/r_sci_rx_pinset.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.h +* Version : 1.0.2 +* Device(s) : R5F572NNHxFB +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +* Creation Date: [ manually removed ] +***********************************************************************************************************************/ + +#ifndef R_SCI_RX_H +#define R_SCI_RX_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +void R_SCI_PinSet_SCI2(); +void R_SCI_PinSet_SCI9(); + +#endif diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/doc/en/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/doc/en/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/doc/ja/.gitkeep b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/doc/ja/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/r_sci_rx_if.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/r_sci_rx_if.h new file mode 100644 index 000000000..c85c67cc3 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/r_sci_rx_if.h @@ -0,0 +1,313 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_if.h +* Description : Functions for using SCI on RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Bumped revision for RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added RX113 support +* 11.03.2015 1.40 Consolidated with r_sci_rx64m and added support for RX71M +* 11.05.2015 1.60 Added RX231 support +* 30.09.2015 1.70 Added RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added RX24U support +* SCI_CMD_EN_TEI was Changed to ineffective, because it is meaningless command. +* 07.03.2017 2.00 Fixed a bug that send/receive is incorrect when changed setting when FIFO enabled. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 31.10.2017 2.01 Added the demo for RX65N, RX65N-2M. +* 28.09.2018 2.10 Added support RX66T +* Added SCI_CMD_COMPARE_RECEIVED_DATA command +* Added SCI_EVT_RX_CHAR_MATCH for receiving data match event +* Fixed section layout follow GSCE 5.0 +* 16.11.2018 2.11 Added XML document number +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support RX23W +* 15.08.2019 3.20 Added support RX72M +* 16.09.2019 3.21 Fixed issue in RX631/RX63N sci_initialize_ints() +* 25.11.2019 3.30 Added support RX13T. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ + +#ifndef SCI_IF_H +#define SCI_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_config.h" /* SCI config definitions */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define SCI_VERSION_MAJOR (3) +#define SCI_VERSION_MINOR (50) + +#define SCI_CLK_INT (0x00U) /* use internal clock for baud generation */ +#define SCI_CLK_EXT8X (0x03U) /* use external clock 8x baud rate (ASYNC) */ +#define SCI_CLK_EXT16X (0x02U) /* use external clock 16x baud rate (ASYNC) */ +#define SCI_DATA_7BIT (0x40U) +#define SCI_DATA_8BIT (0x00U) +#define SCI_PARITY_ON (0x20U) +#define SCI_PARITY_OFF (0x00U) +#define SCI_ODD_PARITY (0x10U) +#define SCI_EVEN_PARITY (0x00U) +#define SCI_STOPBITS_2 (0x08U) +#define SCI_STOPBITS_1 (0x00U) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +typedef enum e_sci_ch // SCI channel numbers +{ + SCI_CH0=0, + SCI_CH1, + SCI_CH2, + SCI_CH3, + SCI_CH4, + SCI_CH5, + SCI_CH6, + SCI_CH7, + SCI_CH8, + SCI_CH9, + SCI_CH10, + SCI_CH11, + SCI_CH12, + SCI_NUM_CH +} sci_ch_t; + + +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_MAX, // End of modes currently supported +} sci_mode_t; + + +typedef enum e_sci_err /* SCI API error codes */ +{ + SCI_SUCCESS=0, + SCI_ERR_BAD_CHAN, // non-existent channel number + SCI_ERR_OMITTED_CHAN, // SCI_CHx_INCLUDED is 0 in config.h + SCI_ERR_CH_NOT_CLOSED, // chan still running in another mode + SCI_ERR_BAD_MODE, // unsupported or incorrect mode for channel + SCI_ERR_INVALID_ARG, // argument is not one of the predefined values + SCI_ERR_NULL_PTR, // received null ptr; missing required argument + SCI_ERR_XCVR_BUSY, // cannot start data transfer; transceiver busy + + /* Asynchronous mode only */ + SCI_ERR_QUEUE_UNAVAILABLE, // can't open tx or rx queue or both + SCI_ERR_INSUFFICIENT_SPACE, // not enough space in transmit queue + SCI_ERR_INSUFFICIENT_DATA, // not enough data in receive queue + + /* Synchronous/SSPI modes only */ + SCI_ERR_XFER_NOT_DONE // data transfer still in progress +} sci_err_t; + + +/* CHANNEL CONTROL BLOCK HANDLE */ + +typedef struct st_sci_ch_ctrl * sci_hdl_t; + + +/* SCI_OPEN() ARGUMENT DEFINITIONS (do NOT change values) */ + +typedef enum e_sci_spi_mode +{ + SCI_SPI_MODE_OFF = 1, /* channel is in synchronous mode */ + + SCI_SPI_MODE_0 = 0x80, /* SPMR Register CKPH=1, CKPOL=0 + Mode 0: 00 CPOL=0 resting lo, CPHA=0 leading edge/rising */ + SCI_SPI_MODE_1 = 0x40, /* SPMR Register CKPH=0, CKPOL=1 + Mode 1: 01 CPOL=0 resting lo, CPHA=1 trailing edge/falling */ + SCI_SPI_MODE_2 = 0xC0, /* SPMR Register CKPH=1, CKPOL=1 + Mode 2: 10 CPOL=1 resting hi, CPHA=0 leading edge/falling */ + SCI_SPI_MODE_3 = 0x00 /* SPMR Register CKPH=0, CKPOL=0 + Mode 3: 11 CPOL=1 resting hi, CPHA=1 trailing edge/rising */ +} sci_spi_mode_t; + + +/* Open() p_cfg structure when mode=SCI_MODE_ASYNC */ +typedef struct st_sci_uart +{ + uint32_t baud_rate; // ie 9600, 19200, 115200 + uint8_t clk_src; // use SCI_CLK_INT/EXT8X/EXT16X + uint8_t data_size; // use SCI_DATA_nBIT + uint8_t parity_en; // use SCI_PARITY_ON/OFF + uint8_t parity_type; // use SCI_ODD/EVEN_PARITY + uint8_t stop_bits; // use SCI_STOPBITS_1/2 + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_uart_t; + + +/* Open() p_cfg structure when mode = SCI_MODE_SYNC or SCI_MODE_SSPI */ +typedef struct st_sci_sync_sspi +{ + sci_spi_mode_t spi_mode; // clock polarity and phase; unused for sync + uint32_t bit_rate; // ie 1000000 for 1Mbps + bool msb_first; + bool invert_data; + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_sync_sspi_t; + +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; +} sci_cfg_t; + + +/* CALLBACK FUNCTION ARGUMENT DEFINITIONS */ + +typedef enum e_sci_cb_evt // callback function events +{ + /* Async Events */ + SCI_EVT_TEI, // TEI interrupt occurred; transmitter is idle + SCI_EVT_RX_CHAR, // received a character; already placed in queue + SCI_EVT_RX_CHAR_MATCH, // received a matched character; already placed in queue + SCI_EVT_RXBUF_OVFL, // rx queue is full; can't save anymore data + SCI_EVT_FRAMING_ERR, // receiver hardware framing error + SCI_EVT_PARITY_ERR, // receiver hardware parity error + + /* SSPI/Sync Events */ + SCI_EVT_XFER_DONE, // transfer completed + SCI_EVT_XFER_ABORTED, // transfer aborted + + /* Common Events */ + SCI_EVT_OVFL_ERR // receiver hardware overrun error +} sci_cb_evt_t; + +typedef struct st_sci_cb_args // callback arguments +{ + sci_hdl_t hdl; + sci_cb_evt_t event; + uint8_t byte; // byte read when error occurred (unused for TEI, XFER_DONE) + uint8_t num; // Number of bytes were stored to queue (used only async(FIFO)) +} sci_cb_args_t; + + +/* SCI_CONTROL() ARGUMENT DEFINITIONS */ + +/* commands */ +typedef enum e_sci_cmd +{ + /* All modes */ + SCI_CMD_CHANGE_BAUD, /* change baud/bit rate */ +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || (SCI_CFG_CH8_FIFO_INCLUDED) || (SCI_CFG_CH9_FIFO_INCLUDED) || (SCI_CFG_CH10_FIFO_INCLUDED) || (SCI_CFG_CH11_FIFO_INCLUDED)) + SCI_CMD_CHANGE_TX_FIFO_THRESH, /* change TX FIFO threshold */ + SCI_CMD_CHANGE_RX_FIFO_THRESH, /* change RX FIFO threshold */ +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + SCI_CMD_SET_RXI_PRIORITY, /* change RXI priority level */ + SCI_CMD_SET_TXI_PRIORITY, /* change TXI priority level */ +#endif + + /* Async commands */ + SCI_CMD_EN_NOISE_CANCEL, /* enable noise cancellation */ + SCI_CMD_EN_TEI, /* SCI_CMD_EN_TEI is obsolete command, + but it exists only for compatibility with older version. */ + SCI_CMD_OUTPUT_BAUD_CLK, /* output baud clock on the SCK pin */ + SCI_CMD_START_BIT_EDGE, /* detect start bit as falling edge of RXDn pin + (default detect as low level on RXDn pin) */ + SCI_CMD_GENERATE_BREAK, /* generate break condition */ + SCI_CMD_TX_Q_FLUSH, /* flush transmit queue */ + SCI_CMD_RX_Q_FLUSH, /* flush receive queue */ + SCI_CMD_TX_Q_BYTES_FREE, /* get count of unused transmit queue bytes */ + SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ, /* get num bytes ready for reading */ + SCI_CMD_COMPARE_RECEIVED_DATA, /* Compare received data with comparison data */ + + /* Async/Sync commands */ + SCI_CMD_EN_CTS_IN, /* enable CTS input (default RTS output) */ + + /* SSPI/Sync commands */ + SCI_CMD_CHECK_XFER_DONE, /* see if send, rcv, or both are done; SCI_SUCCESS if yes */ + SCI_CMD_ABORT_XFER, + SCI_CMD_XFER_LSB_FIRST, /* start from LSB bit when sending */ + SCI_CMD_XFER_MSB_FIRST, /* start from MSB bit when sending */ + SCI_CMD_INVERT_DATA, /* logic level of send/receive data is invert */ + + /* SSPI commands */ + SCI_CMD_CHANGE_SPI_MODE /* change clock polarity and phase in SSPI mode */ +} sci_cmd_t; + +/* SCI_CMD_CHANGE_BAUD/CHANGE_BITRATE take a ptr to this structure for *p_args */ +typedef struct st_sci_baud +{ + uint32_t pclk; // peripheral clock speed; e.g. 24000000 is 24MHz + uint32_t rate; // e.g. 9600, 19200, 115200 +} sci_baud_t; + +/* SCI_CMD_TX_Q_BYTES_FREE and SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ take a pointer + to a uint16_t for p_args */ + +/* SCI_CMD_SET_RXI_PRIORITY and SCI_CMD_SET_TXI_PRIORITY take a pointer to a + uint8_t for p_args */ + +/* SCI_CMD_CHANGE_SPI_MODE takes a pointer to an sci_spi_mode_t for p_args */ + +/***************************************************************************** +Public Functions +******************************************************************************/ +sci_err_t R_SCI_Open(uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl); + +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, // SSPI/SYNC only + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length); + +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); + +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); + +sci_err_t R_SCI_Close(sci_hdl_t const hdl); + +uint32_t R_SCI_GetVersion(void); + + +#endif /* SCI_IF_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/readme.txt b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/readme.txt new file mode 100644 index 000000000..8ff173dcb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/readme.txt @@ -0,0 +1,78 @@ +PLEASE REFER TO THE APPLICATION NOTE FOR THIS DRIVER FOR MORE INFORMATION + +r_sci_rx +======== + +Overview +-------------------------------------------------------------------------------- +The r_sci_rx module is a multi-channel, multi-mode, interrupt-driven driver which +supports Asynchronous, Master Synchronous, and Single Master Simple SPI (SSPI) +operation for the SCI peripherals. The API includes standard functions +to initialize a channel and to send and receive data, as well as a special control +function for taking actions such as issuing a break signal or enabling noise +cancellation. The driver supports all channels available on the mcu. The driver +can be reduced in size by removing code used for parameter checking, unused +channels, or unused modes. These configuration options can be found in +"r_config\r_sci_rx_config.h". An original copy of the configuration file +is stored in "r_sci_rx\ref\r_sci_rx_config_reference.h". + + +Features +-------- +* (RX110/111/113, RX65N/651) Simultaneous operation of up to 13 channels. +* (RX231/230) Simultaneous operation of up to 7 channels. +* (RX23T) Simultaneous operation of up to 2 channels. +* (RX23W) Simultaneous operation of up to 4 channels. +* (RX64M, RX71M) Simultaneous operation of up to 9 channels. +* (RX130) Simultaneous operation of up to 4 channels. +* (RX13T) Simultaneous operation of up to 3 channels. +* (RX24T) Simultaneous operation of up to 3 channels. +* (RX24U) Simultaneous operation of up to 6 channels. +* (RX66T) Simultaneous operation of up to 7 channels +* (RX72T) Simultaneous operation of up to 7 channels +* (RX72M) Simultaneous operation of up to 13 channels +* (RX72N) Simultaneous operation of up to 13 channels +* (RX66N) Simultaneous operation of up to 13 channels +* (RX23E-A) Simultaneous operation of up to 4 channels +* Simultaneous operation of Async, Sync, or SSPI modes on different channels. +* Queueing of incoming and outgoing data for Asynchronous channels. +* Interrupt driven. + + +File Structure +-------------- +r_sci_rx +| readme.txt +| r_sci_rx_if.h +| ++---doc +| +---ja +| | r01an1815jj{VERSION_NUMBER}-rx-serial.pdf +| +---en +| r01an1815ej{VERSION_NUMBER}-rx-serial.pdf +| ++---ref +| r_sci_rx_config_reference.h +| ++---src + | r_sci_rx.c + | r_sci_rx_platform.h + | r_sci_rx_private.h + | + +---targets + | + +---rx110 + | r_sci_rx110.c + | r_sci_rx110_data.c + | r_sci_rx110_private.h + +---rx111 + | r_sci_rx111.c + | r_sci_rx111_data.c + | r_sci_rx111_private.h + : + +r_config + r_sci_rx_config.h + +r_sci_rx.ftl + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h new file mode 100644 index 000000000..ea287d649 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/ref/r_sci_rx_config_reference.h @@ -0,0 +1,198 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (1) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * RX MCU supported channels + * + * CH# 110 111 113 130 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N RX23E-A + * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------- + * CH0 X Xa X X X X Xn X X X + * CH1 X X* X* Xu X X Xu Xu Xu X X Xs X X X X X X X Xu + * CH2 X X X Xu X X X + * CH3 X X Xs X X X + * CH4 X X Xn X X X + * CH5 X X X X X Xu X X X X X X X X X X X X X X + * CH6 X X X X X X X X Xn X X Xu X X X + * CH7 Xu Xu Xn X X X + * CH8 X Xa X X X X X X Xu X X X + * CH9 X Xa X X X Xs X X X X X + * CH10 X X X X + * CH11 X Xs X X X X X + * CH12 X X X X X X X X Xs X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (0) +#define SCI_CFG_CH1_INCLUDED (1) +#define SCI_CFG_CH2_INCLUDED (0) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (0) +#define SCI_CFG_CH6_INCLUDED (0) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (0) +#define SCI_CFG_CH9_INCLUDED (0) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (0) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +#define SCI_CFG_ERI_TEI_PRIORITY (3) /* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N ONLY) 1 lowest, 15 highest */ + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj and SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +#endif /* SCI_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx.c new file mode 100644 index 000000000..d103e1438 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx.c @@ -0,0 +1,2349 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016-2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx.c +* Description : Functions for using SCI on RX devices. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 FIT_NO_PTR check added to NULL check. +* Fixed a bug that may receive data more than the specified number of bytes +* on Clock Synchronous Mode. +* Fixed that R_SCI_Control function returns SCI_ERR_INVALID_ARG +* when using SCI_CMD_EN_CTS_IN on Simple SPI mode. +* Fix to clear error flag even if callback function is not set. +* Deleted unnecessary bit mask of SSR register from sci_error function. +* 07.03.2017 2.00 Fixed a bug that error condition not clear when FIFO enabled. +* Fixed a bug that where commands used only when FIFO mode is enable did not NULL check. +* Fixed a bug that sending data is overwrote by new R_SCI_Send() when FIFO(async) enabled. +* Fixed a bug that sending data is break up by new R_SCI_Send() when FIFO(sync) enabled. +* Fixed a bug that the new FIFO threshold was retained only on first receive. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 28.09.2018 2.10 Added support RX66T +* Add WAIT_LOOP comments. +* Fixed a bug that leaking memory in R_SCI_Open() when FIFO(async) enabled. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin. +* Fix GSCE Code Checker errors. +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support for RX72M +* 25.11.2019 3.30 Added support RX13T. +* Modified comment of API function to Doxygen style. +* Added support for atomic control. +* Fixed to comply with GSCE Coding Standards Rev.6.00. +* Fixed a bug that error when a reception interrupt occurs before incrementing "u_tx_data.buf" +* in "sci_send_sync_data" and "sci_receive" functions +* 30.12.2019 3.40 Added support RX66N, RX72N. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +/* Defines for SCI support */ +#include "r_sci_rx_private.h" + +/* Include specifics for chosen MCU. */ +#include "r_sci_rx_platform.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_init_queues(uint8_t const chan); + +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte); + +static void sci_transfer(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_transfer(sci_hdl_t const hdl); +#endif + +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static sci_err_t sci_init_sync(sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data); + +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +static void power_on(sci_hdl_t const hdl); +static void power_off(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static sci_err_t sci_init_fifo(sci_hdl_t const hdl); +#endif + +static void sci_receive(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static void sci_fifo_receive_sync(sci_hdl_t const hdl); +#endif + +static void sci_fifo_receive(sci_hdl_t const hdl); + +#endif + +#if SCI_CFG_DATA_MATCH_INCLUDED +static void sci_receive_data_match(sci_hdl_t const hdl); +#endif + +static void sci_error(sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_error(sci_hdl_t const hdl); +#endif + +/* queue buffers */ +#if (SCI_CFG_ASYNC_INCLUDED) + +#if SCI_CFG_CH0_INCLUDED +static uint8_t ch0_tx_buf[SCI_CFG_CH0_TX_BUFSIZ]; +static uint8_t ch0_rx_buf[SCI_CFG_CH0_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH1_INCLUDED +static uint8_t ch1_tx_buf[SCI_CFG_CH1_TX_BUFSIZ]; +static uint8_t ch1_rx_buf[SCI_CFG_CH1_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH2_INCLUDED +static uint8_t ch2_tx_buf[SCI_CFG_CH2_TX_BUFSIZ]; +static uint8_t ch2_rx_buf[SCI_CFG_CH2_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH3_INCLUDED +static uint8_t ch3_tx_buf[SCI_CFG_CH3_TX_BUFSIZ]; +static uint8_t ch3_rx_buf[SCI_CFG_CH3_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH4_INCLUDED +static uint8_t ch4_tx_buf[SCI_CFG_CH4_TX_BUFSIZ]; +static uint8_t ch4_rx_buf[SCI_CFG_CH4_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH5_INCLUDED +static uint8_t ch5_tx_buf[SCI_CFG_CH5_TX_BUFSIZ]; +static uint8_t ch5_rx_buf[SCI_CFG_CH5_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH6_INCLUDED +static uint8_t ch6_tx_buf[SCI_CFG_CH6_TX_BUFSIZ]; +static uint8_t ch6_rx_buf[SCI_CFG_CH6_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH7_INCLUDED +static uint8_t ch7_tx_buf[SCI_CFG_CH7_TX_BUFSIZ]; +static uint8_t ch7_rx_buf[SCI_CFG_CH7_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH8_INCLUDED +static uint8_t ch8_tx_buf[SCI_CFG_CH8_TX_BUFSIZ]; +static uint8_t ch8_rx_buf[SCI_CFG_CH8_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH9_INCLUDED +static uint8_t ch9_tx_buf[SCI_CFG_CH9_TX_BUFSIZ]; +static uint8_t ch9_rx_buf[SCI_CFG_CH9_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH10_INCLUDED +static uint8_t ch10_tx_buf[SCI_CFG_CH10_TX_BUFSIZ]; +static uint8_t ch10_rx_buf[SCI_CFG_CH10_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH11_INCLUDED +static uint8_t ch11_tx_buf[SCI_CFG_CH11_TX_BUFSIZ]; +static uint8_t ch11_rx_buf[SCI_CFG_CH11_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH12_INCLUDED +static uint8_t ch12_tx_buf[SCI_CFG_CH12_TX_BUFSIZ]; +static uint8_t ch12_rx_buf[SCI_CFG_CH12_RX_BUFSIZ]; +#endif + +#endif /* #if (SCI_CFG_ASYNC_INCLUDED) */ + +extern const sci_hdl_t g_handles[SCI_NUM_CH]; + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Open +********************************************************************************************************************//** +* @brief This function applies power to the SCI channel, initializes the associated registers, enables interrupts, and +* provides the channel handle for use with other API functions. This function must be called before calling any +* other API functions +* @param[in] chan Channel to initialize. +* +* @param[in] mode Operational mode (see enumeration below) +* @code +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_MAX // End of modes currently supported +} sci_mode_t; +* @endcode +* @param[in] p_cfg Pointer to configuration union, structure elements (see below) are specific to mode +* @code +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; +} sci_cfg_t; +* @endcode +* +* @param[in] p_callback Pointer to function called from interrupt when an RXI or receiver error is detected or +* for transmit end (TEI) condition. See Section 2.11 Callback Function in application note for details. +* +* @param[in] p_hdl Pointer to a handle for channel (value set here) +* Confirm the return value from R_SCI_Open is “SCI_SUCCESS” and then set the first parameter for the +* other APIs except R_SCI_GetVersion(). See Section 2.9 Parameters in the application note for details. +* +* +* @retval SCI_SUCCESS Successful; channel initialized +* +* @retval SCI_ERR_BAD_CHAN Channel number is invalid for part +* +* @retval SCI_ERR_OMITTED_CHAN Corresponding SCI_CHx_INCLUDED is invalid (0) +* +* @retval SCI_ERR_CH_NOT_CLOSED Channel currently in operation; Perform R_SCI_Close() first +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_NULL_PTR p_cfg pointer is NULL +* +* @retval SCI_ERR_INVALID_ARG An element of the p_cfg structure contains an invalid value. +* +* @retval SCI_ERR_QUEUE_UNAVAILABLE Cannot open transmit or receive queue or both (Asynchronous mode). +* @details Initializes an SCI channel for a particular mode and provides a Handle in *p_hdl for use with other API +* functions. RXI and ERI interrupts are enabled in all modes. TXI is enabled in Asynchronous mode +* @note The driver calculates the optimum values for BRR, SEMR.ABCS, and SMR.CKS using BSP_PCLKA_HZ and +* BSP_PCLKB_HZ as defined in mcu_info.h of the board support package. This however does not guarantee +* a low bit error rate for all peripheral clock/baud rate combinations. +* If an external clock is used in Asynchronous mode, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Open() in the application note for details. +*/ +sci_err_t R_SCI_Open(uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl) +{ + sci_err_t err = SCI_SUCCESS; + uint8_t priority = 1; + + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + err = sci_mcu_param_check(chan); + if (SCI_SUCCESS != err) + { + return err; + } + + /* Check argument g_handles */ + if ((NULL == g_handles[chan]) || (FIT_NO_PTR == g_handles[chan])) + { + return SCI_ERR_OMITTED_CHAN; + } + if (SCI_MODE_OFF != g_handles[chan]->mode) + { + return SCI_ERR_CH_NOT_CLOSED; + } + if ((SCI_MODE_OFF == mode) || (SCI_MODE_MAX <= mode)) + { + return SCI_ERR_BAD_MODE; + } + + /* Check argument p_cfg, p_hdl */ + if (((NULL == p_cfg) || (NULL == p_hdl)) || ((FIT_NO_PTR == p_cfg) || (FIT_NO_PTR == p_hdl))) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* APPLY POWER TO CHANNEL */ + power_on(g_handles[chan]); + + /* INITIALIZE REGISTER */ + sci_init_register(g_handles[chan]); + + /* INITIALIZE MODE SPECIFIC FEATURES */ + g_handles[chan]->mode = mode; + if (SCI_MODE_ASYNC == mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_uart_t type is valid */ + err = sci_init_async(g_handles[chan], (sci_uart_t *)p_cfg, &priority); +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_sync_sspi_t type is valid */ + err = sci_init_sync(g_handles[chan], (sci_sync_sspi_t *)p_cfg, &priority); +#endif + } + + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + g_handles[chan]->callback = p_callback; + + /* INITIALIZE TX AND RX QUEUES */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == mode) + { + err = sci_init_queues(chan); + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + +#if SCI_CFG_FIFO_INCLUDED + if (true == g_handles[chan]->fifo_ctrl) + { + /* INITIALIZE TX AND RX FIFO */ + err = sci_init_fifo(g_handles[chan]); + if (SCI_SUCCESS != err) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* DE-INITIALIZE TX AND RX QUEUES */ + if (SCI_MODE_ASYNC == mode) + { + R_BYTEQ_Close(g_handles[chan]->u_tx_data.que); + R_BYTEQ_Close(g_handles[chan]->u_rx_data.que); + } +#endif + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + + /* ENABLE INTERRUPTS */ + sci_initialize_ints(g_handles[chan], priority); + + /* FINISH */ + *p_hdl = g_handles[chan]; + + return SCI_SUCCESS; +} /* End of function R_SCI_Open() */ + +/***************************************************************************** +* Function Name: power_on +* Description : This function provides power to the channel referenced by +* the handle by taking it out of the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_on(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) &= (~hdl->rom->stop_mask); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_on() */ + +/***************************************************************************** +* Function Name: power_off +* Description : This function removes power to the channel referenced by +* handle by putting it into the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_off(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) |= (hdl->rom->stop_mask); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_off() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_queues +* Description : This function attaches transmit and receive queues to the +* channel. +* +* Arguments : chan - +* channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_QUEUE_UNAVAILABLE - +* no queue control blocks available +******************************************************************************/ +static sci_err_t sci_init_queues(uint8_t const chan) +{ + byteq_err_t q_err1 = BYTEQ_ERR_INVALID_ARG; + byteq_err_t q_err2 = BYTEQ_ERR_INVALID_ARG; + sci_err_t err = SCI_SUCCESS; + + /* channel number verified as legal prior to calling this function */ + switch (chan) + { +#if SCI_CFG_CH0_INCLUDED + case (SCI_CH0): + { + q_err1 = R_BYTEQ_Open(ch0_tx_buf, SCI_CFG_CH0_TX_BUFSIZ, &g_handles[SCI_CH0]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch0_rx_buf, SCI_CFG_CH0_RX_BUFSIZ, &g_handles[SCI_CH0]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH1_INCLUDED + case (SCI_CH1): + { + q_err1 = R_BYTEQ_Open(ch1_tx_buf, SCI_CFG_CH1_TX_BUFSIZ, &g_handles[SCI_CH1]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch1_rx_buf, SCI_CFG_CH1_RX_BUFSIZ, &g_handles[SCI_CH1]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH2_INCLUDED + case (SCI_CH2): + { + q_err1 = R_BYTEQ_Open(ch2_tx_buf, SCI_CFG_CH2_TX_BUFSIZ, &g_handles[SCI_CH2]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch2_rx_buf, SCI_CFG_CH2_RX_BUFSIZ, &g_handles[SCI_CH2]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH3_INCLUDED + case (SCI_CH3): + { + q_err1 = R_BYTEQ_Open(ch3_tx_buf, SCI_CFG_CH3_TX_BUFSIZ, &g_handles[SCI_CH3]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch3_rx_buf, SCI_CFG_CH3_RX_BUFSIZ, &g_handles[SCI_CH3]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH4_INCLUDED + case (SCI_CH4): + { + q_err1 = R_BYTEQ_Open(ch4_tx_buf, SCI_CFG_CH4_TX_BUFSIZ, &g_handles[SCI_CH4]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch4_rx_buf, SCI_CFG_CH4_RX_BUFSIZ, &g_handles[SCI_CH4]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH5_INCLUDED + case (SCI_CH5): + { + q_err1 = R_BYTEQ_Open(ch5_tx_buf, SCI_CFG_CH5_TX_BUFSIZ, &g_handles[SCI_CH5]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch5_rx_buf, SCI_CFG_CH5_RX_BUFSIZ, &g_handles[SCI_CH5]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH6_INCLUDED + case (SCI_CH6): + { + q_err1 = R_BYTEQ_Open(ch6_tx_buf, SCI_CFG_CH6_TX_BUFSIZ, &g_handles[SCI_CH6]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch6_rx_buf, SCI_CFG_CH6_RX_BUFSIZ, &g_handles[SCI_CH6]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH7_INCLUDED + case (SCI_CH7): + { + q_err1 = R_BYTEQ_Open(ch7_tx_buf, SCI_CFG_CH7_TX_BUFSIZ, &g_handles[SCI_CH7]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch7_rx_buf, SCI_CFG_CH7_RX_BUFSIZ, &g_handles[SCI_CH7]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH8_INCLUDED + case (SCI_CH8): + { + q_err1 = R_BYTEQ_Open(ch8_tx_buf, SCI_CFG_CH8_TX_BUFSIZ, &g_handles[SCI_CH8]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch8_rx_buf, SCI_CFG_CH8_RX_BUFSIZ, &g_handles[SCI_CH8]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH9_INCLUDED + case (SCI_CH9): + { + q_err1 = R_BYTEQ_Open(ch9_tx_buf, SCI_CFG_CH9_TX_BUFSIZ, &g_handles[SCI_CH9]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch9_rx_buf, SCI_CFG_CH9_RX_BUFSIZ, &g_handles[SCI_CH9]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH10_INCLUDED + case (SCI_CH10): + { + q_err1 = R_BYTEQ_Open(ch10_tx_buf, SCI_CFG_CH10_TX_BUFSIZ, &g_handles[SCI_CH10]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch10_rx_buf, SCI_CFG_CH10_RX_BUFSIZ, &g_handles[SCI_CH10]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH11_INCLUDED + case (SCI_CH11): + { + q_err1 = R_BYTEQ_Open(ch11_tx_buf, SCI_CFG_CH11_TX_BUFSIZ, &g_handles[SCI_CH11]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch11_rx_buf, SCI_CFG_CH11_RX_BUFSIZ, &g_handles[SCI_CH11]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH12_INCLUDED + case (SCI_CH12): + { + q_err1 = R_BYTEQ_Open(ch12_tx_buf, SCI_CFG_CH12_TX_BUFSIZ, &g_handles[SCI_CH12]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch12_rx_buf, SCI_CFG_CH12_RX_BUFSIZ, &g_handles[SCI_CH12]->u_rx_data.que); + break; + } +#endif + default: + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + break; + } + } + + if ((BYTEQ_SUCCESS != q_err1) || (BYTEQ_SUCCESS != q_err2)) + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + } + return err; +} /* End of function sci_init_queues() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_init_fifo +* Description : This function the setting of the FIFO mode, reset of the +* TX/RX FIFO, and the threshold setting of the TX/RX FIFO. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* fifo initialized successfully +* SCI_ERR_INVALID_ARG - +* element of hdl contains illegal value +******************************************************************************/ +static sci_err_t sci_init_fifo(sci_hdl_t const hdl) +{ + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (hdl->tx_dflt_thresh > 15) + { + return SCI_ERR_INVALID_ARG; + } + if ((hdl->rx_dflt_thresh < 1) || (hdl->rx_dflt_thresh > 15)) + { + return SCI_ERR_INVALID_ARG; + } +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if (hdl->tx_dflt_thresh != hdl->rx_dflt_thresh) + { + return SCI_ERR_INVALID_ARG; + } +#endif +#endif + + /* FIFO Mode Select (1:FIFO mode) */ + hdl->rom->regs->FCR.BIT.FM = 0x01; + + /* reset TX/RX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* set TX/RX FIFO threshold initial value */ + hdl->rom->regs->FCR.BIT.TTRG = hdl->tx_dflt_thresh; + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_dflt_thresh; + + return SCI_SUCCESS; +} /* End of function sci_init_fifo() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_async +* Description : This function initializes the control block and UART +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to Uart configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (((SCI_DATA_8BIT != p_cfg->data_size) && (SCI_DATA_7BIT != p_cfg->data_size)) + || ((SCI_STOPBITS_1 != p_cfg->stop_bits) && (SCI_STOPBITS_2 != p_cfg->stop_bits)) + || ((p_cfg->int_priority < (BSP_MCU_IPL_MIN+1)) || (p_cfg->int_priority > BSP_MCU_IPL_MAX))) + { + return SCI_ERR_INVALID_ARG; + } + + if (SCI_PARITY_ON == p_cfg->parity_en) + { + if ((SCI_EVEN_PARITY != p_cfg->parity_type) && (SCI_ODD_PARITY != p_cfg->parity_type)) + { + return SCI_ERR_INVALID_ARG; + } + } + else if (SCI_PARITY_OFF != p_cfg->parity_en) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + if (SCI_CLK_INT == p_cfg->clk_src) + { + if (0 == p_cfg->baud_rate) + { + return SCI_ERR_INVALID_ARG; + } + } + else if ((SCI_CLK_EXT8X != p_cfg->clk_src) && (SCI_CLK_EXT16X != p_cfg->clk_src)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + + + /* Configure SMR for asynchronous mode, single processor, and user settings */ + if (SCI_PARITY_OFF == p_cfg->parity_en) + { + p_cfg->parity_type = 0; // ensure random value is not ORed into SMR + } + + /* Configure SMR */ + hdl->rom->regs->SMR.BYTE = (uint8_t)((p_cfg->data_size | p_cfg->stop_bits) | (p_cfg->parity_en | p_cfg->parity_type)); + + /* SETUP CLOCK FOR BAUD RATE */ + + if (SCI_CLK_INT == p_cfg->clk_src) + { + /* Use internal clock for baud rate */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->baud_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = p_cfg->baud_rate; // save baud rate for break generation + } + } + else + { + /* Use external clock for baud rate */ + hdl->rom->regs->SCR.BIT.CKE = 0x02; + hdl->rom->regs->SEMR.BIT.ABCS = (SCI_CLK_EXT8X == p_cfg->clk_src) ? 1 : 0; + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_async() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_sync +* Description : This function initializes the control block and SYNC/SSPI +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to SSPI configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_sync(sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err = SCI_SUCCESS; + int32_t bit_err; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((SCI_MODE_SSPI == hdl->mode) + && (SCI_SPI_MODE_0 != p_cfg->spi_mode) && (SCI_SPI_MODE_1 != p_cfg->spi_mode) + && (SCI_SPI_MODE_2 != p_cfg->spi_mode) && (SCI_SPI_MODE_3 != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else if ((SCI_MODE_SYNC == hdl->mode) && (SCI_SPI_MODE_OFF != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + + if (0 == p_cfg->bit_rate) + { + return SCI_ERR_INVALID_ARG; + } + + if ((0 == p_cfg->int_priority) || (p_cfg->int_priority > BSP_MCU_IPL_MAX)) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + hdl->tx_dummy = false; + + /* Configure SMR for SSPI/SYNC mode */ + hdl->rom->regs->SMR.BYTE = 0x80; + hdl->rom->regs->SCMR.BIT.SMIF = 0; /* default */ + hdl->rom->regs->SIMR1.BIT.IICM = 0; /* default */ + + /* Configure SPI register for clock polarity/phase and single master */ + if (SCI_MODE_SSPI == hdl->mode) + { + hdl->rom->regs->SPMR.BYTE = p_cfg->spi_mode; + } + else /* synchronous operation */ + { + hdl->rom->regs->SPMR.BYTE = 0; + } + + /* Configure data inversion */ + hdl->rom->regs->SCMR.BIT.SINV = (uint8_t)((true == p_cfg->invert_data) ? 1 : 0); + + /* Configure bit order */ + hdl->rom->regs->SCMR.BIT.SDIR = (uint8_t)((true == p_cfg->msb_first) ? 1 : 0); + + + /* SETUP CLOCK FOR BIT RATE */ + + /* Use internal clock for bit rate (master) */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->bit_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; /* impossible bit rate; 100% error */ + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_sync() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Send +********************************************************************************************************************//** +* @brief Initiates transmit if transmitter is not in use. Queues data for later transmit when in Asynchronous mode. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_src Pointer to data to transmit +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Transmit initiated or loaded into queue (Asynchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_SPACE Insufficient space in queue to load all data (Asynchronous) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous) +* +* +* @details In asynchronous mode, this function places data into a transmit queue if the transmitter for the SCI channel +* referenced by the handle is not in use. In SSPI and Synchronous modes, no data is queued and transmission begins immediately +* if the transceiver is not already in use. All transmissions are handled at the interrupt level.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave Select line +* for the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* @note None +*/ +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err=SCI_SUCCESS; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_src */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl)) || ((NULL == p_src) || (FIT_NO_PTR == p_src))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_send_async_data(hdl, p_src, length); +#endif + } + else + { + /* SSPI or SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_send_sync_data(hdl, p_src, NULL, length, false); +#endif + } + + return err; +} /* End of function R_SCI_Send() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_async_data +* Description : This function determines if the tx byte queue of the channel +* referenced by the handle is not full, and call the byte +* transmission function. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* length - +* number of bytes to send and possibly receive +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_ERR_QUEUE_FULL; + + if (true != hdl->tx_idle ) + { + return SCI_ERR_XCVR_BUSY; + } + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* TX FIFO use check */ + if (0x00 < hdl->rom->regs->FDR.BIT.T) + { + return SCI_ERR_XCVR_BUSY; + } + + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + } +#endif + + /* Determine amount of space left in tx queue */ + R_BYTEQ_Unused(hdl->u_tx_data.que, &cnt); + + if (cnt < length) + { + /* If can't fit, return */ + return SCI_ERR_INSUFFICIENT_SPACE; + } + + /* Else load bytes into tx queue for transmission */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { + byteq_err = sci_put_byte(hdl, *p_src++); + if (BYTEQ_SUCCESS != byteq_err) + { + /* If the return value is not BYTEQ_SUCCESS. */ + err = SCI_ERR_INSUFFICIENT_SPACE; + break; + } + } + + if (SCI_SUCCESS == err) + { + hdl->tx_idle = false; + ENABLE_TXI_INT; + } + + return err; +} /* End of function sci_send_async_data() */ + +/***************************************************************************** +* Function Name: sci_put_byte +* Description : Transmits byte if channel is not busy. Otherwise, byte is +* stored in tx queue until can transmit. If buffer is full +* and cannot store it, an error code is returned. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* byte - +* byte to transmit +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte) +{ + byteq_err_t err = BYTEQ_ERR_QUEUE_FULL; + + /* else load next byte into tx queue (space checked in calling func) */ + err = R_BYTEQ_Put(hdl->u_tx_data.que, byte); + + return err; +} /* End of function sci_put_byte() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and begins the data transfer process +* (both sending and receiving data). +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* p_dst - +* ptr to buffer to store receive data (optional) +* length - +* number of bytes to send and possibly receive +* save_rx_data - +* true if data clocked in should be saved to p_dst. +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + if (true == hdl->tx_idle) + { + if (true == save_rx_data) + { + hdl->u_rx_data.buf = p_dst; + } + hdl->save_rx_data = save_rx_data; + + hdl->u_tx_data.buf = p_src; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_idle = false; + hdl->tx_dummy = false; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + + thresh_cnt = hdl->rom->regs->FCR.BIT.RTRG; + + hdl->tx_cnt -= thresh_cnt; + + /* Repeated FIFO RX threshold count */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + if(0 != cnt) + { + hdl->u_tx_data.buf++; + } + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + } + else +#endif + { + hdl->tx_cnt--; + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_send_sync_data() */ +#endif /* SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/*********************************************************************************************************************** +* Function Name: R_SCI_SendReceive +********************************************************************************************************************//** +* @brief For Synchronous and SSPI modes only. Transmits and receives data simultaneously if the transceiver is not +* in use. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* @param[in] p_src Pointer to data to transmit +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Data transfer initiated +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Channel mode not SSPI or Synchronous +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy +* @details If the transceiver is not in use, this function clocks out data from the p_src buffer while simultaneously +* clocking in data and placing it in the p_dst buffer. +* Note that the toggling of Slave Select lines for SSPI is not handled by this driver. The Slave Select line for +* the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +*/ +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check arguments */ + if ((((NULL == hdl) || (FIT_NO_PTR == hdl)) /* Check if hdl is available or not */ + || ((NULL == p_src) || (FIT_NO_PTR == p_src))) /* Check if p_src is available or not */ + || ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) /* Check if p_dst is available or not */ + { + return SCI_ERR_NULL_PTR; + } + + if ((SCI_MODE_SSPI != hdl->mode) && (SCI_MODE_SYNC != hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + err = sci_send_sync_data(hdl, p_src, p_dst, length, true); + + return err; +} /* End of function R_SCI_SendReceive() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_transfer +* Description : Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_transfer(sci_hdl_t const hdl) +{ + uint16_t num; + uint8_t byte; + + /* Get bytes from tx queue */ + (void)R_BYTEQ_Get(hdl->u_tx_data.que, (uint8_t *)&byte); + + /* TDR/FTDR register write access */ + SCI_TDR(byte); + + /* Get data byte number from que and if the number of data bytes is 0, to disable the transfer */ + R_BYTEQ_Used(hdl->u_tx_data.que, &num); + if (0 >= num) + { + /* Disable transmit interrupt */ + DISABLE_TXI_INT; +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + hdl->tx_idle = true; // set flag if queue empty + } +} /* End of function sci_transfer() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_transfer +* Description : FIFO Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_transfer(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num; + + /* Repeated empty FIFO buffer count */ + fifo_num = SCI_FIFO_FRAME_SIZE - hdl->rom->regs->FDR.BIT.T; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* SCI Transfer */ + sci_transfer(hdl); + + /* If the queue is empty(true == hdl->tx_idle), exit from FIFO transfer loop */ + if (true == hdl->tx_idle) + { + break; + } + } + + /* When the settings of transmit data are completed, set the SSRFIFO.TDFE flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + /* Casting register 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } +} /* End of function sci_fifo_transfer() */ +#endif /*End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: txi_handler +* Description : TXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void txi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Transfer */ + sci_fifo_transfer(hdl); + } + else +#endif + { + /* SCI Transfer */ + sci_transfer(hdl); + } +} /* End of function txi_handler() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* Function Name: tei_handler +* Description : TEI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void tei_handler(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + + /* Disable transmit end interrupt */ + DISABLE_TEI_INT; + hdl->rom->regs->SCR.BIT.TEIE = 0; + + /* Activate callback function if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_TEI; + + /* Activate callback function */ + hdl->callback((void *)&args); + } +} /* End of function tei_handler() */ +#endif + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Receive +********************************************************************************************************************//** +* @brief In Asynchronous mode, fetches data from a queue which is filled by RXI interrupts. In other modes, initiates +* reception if transceiver is not in use. +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to read +* +* @retval SCI_SUCCESS Requested number of bytes were loaded into p_dst (Asynchronous) Clocking in of data initiated +* (SSPI/Synchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_DATA Insufficient data in receive queue to fetch all data (Asynchronous) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous) +* +* @details In Asynchronous mode, this function gets data received on an SCI channel referenced by the handle from its +* receive queue. This function will not block if the requested number of bytes is not available. In +* SSPI/Synchronous modes, the clocking in of data begins immediately if the transceiver is not already in use. +* The value assigned to SCI_CFG_DUMMY_TX_BYTE in r_sci_config.h is clocked out while the receive data is being clocked in.\n +* If any errors occurred during reception, the callback function specified in R_SCI_Open() is executed. Check +* an event passed with the argument of the callback function to see if the reception has been successfully +* completed. See Section 2.11 Callback Function in application note for details.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave +* Select line for the target device must be enabled prior to calling this function. +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +* In Asynchronous mode, when data match detected, received data stored in a queue and notify to user by callback function +* with event SCI_EVT_RX_CHAR_MATCH. +*/ +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +sci_err_t err = SCI_SUCCESS; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_dst */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl))|| ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_receive_async_data(hdl, p_dst, length); +#endif + } + + else + { + /* mode is SSPI/SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_receive_sync_data(hdl, p_dst, length); +#endif + } + + return err; +} /* End of function R_SCI_Receive() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_async_data +* Description : This function determines if the rx byte queue of the channel +* referenced by the handle, the requested number of bytes +* is available, and get the data from the rx byte queue. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_INSUFFICIENT_DATA - +* rx queue does not contain requested amount of data +******************************************************************************/ +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_SUCCESS; + + /* CHECK FOR SUFFICIENT DATA IN QUEUE, AND FETCH IF AVAILABLE */ + R_BYTEQ_Used(hdl->u_rx_data.que, &cnt); + + if (cnt < length) + { + return SCI_ERR_INSUFFICIENT_DATA; + } + + /* Get bytes from rx queue */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { + /* Disable RXI Interrupt */ + DISABLE_RXI_INT; + byteq_err = R_BYTEQ_Get(hdl->u_rx_data.que, p_dst++); + ENABLE_RXI_INT; + if (BYTEQ_SUCCESS != byteq_err) + { + err = SCI_ERR_INSUFFICIENT_DATA; + break; + } + } + + return err; +} /* End of function sci_receive_async_data() */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and dummy data send. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + /* IF TRANCEIVER NOT IN USE, START DUMMY TRANSMIT TO CLOCK IN DATA */ + if (true == hdl->tx_idle) + { + hdl->u_rx_data.buf = p_dst; + hdl->save_rx_data = true; /* save the data clocked in */ + hdl->tx_idle = false; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_dummy = true; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + if (length > SCI_FIFO_FRAME_SIZE) + { + thresh_cnt = SCI_FIFO_FRAME_SIZE; + } + else + { + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + thresh_cnt = length; + } + + hdl->tx_cnt -= thresh_cnt; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transmit */ + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transfer */ + } + + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_receive_sync_data() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +* Function Name: sci_receive +* Description : Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + /* Read byte */ + SCI_RDR(byte); + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + hdl->rx_cnt--; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + *hdl->u_rx_data.buf++ = byte; + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (0 < hdl->tx_cnt) + { + /* send another byte */ + if (true == hdl->tx_dummy) + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + else + { + hdl->tx_cnt--; + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + else + { + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } + } +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + } +} /* End of function sci_receive() */ + +#if SCI_CFG_FIFO_INCLUDED +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_fifo_receive_sync +* Description : FIFO Receive for SCI mode is SYNC and SSPI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive_sync(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num_rx; + uint8_t fifo_num_tx; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; + + fifo_num_rx = hdl->rom->regs->FDR.BIT.R; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + SCI_RDR(byte_rx[cnt]); + } + + hdl->rx_cnt -= fifo_num_rx; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + /* SCI Receive */ + *hdl->u_rx_data.buf++ = byte_rx[cnt]; + } + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (hdl->rom->regs->FCR.BIT.RTRG > hdl->rx_cnt) + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_cnt; + } + + if (0 < hdl->tx_cnt) + { + if (hdl->tx_cnt > fifo_num_rx) + { + fifo_num_tx = fifo_num_rx; + hdl->tx_cnt -= fifo_num_rx; + } + else + { + fifo_num_tx = hdl->tx_cnt; + hdl->tx_cnt = 0; + } + + /* send another byte */ + if (true == hdl->tx_dummy) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + } + else + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + } + else + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_curr_thresh; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + } +} /* End of function sci_fifo_receive_sync() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_receive +* Description : FIFO Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive(sci_hdl_t const hdl) +{ +#if (SCI_CFG_ASYNC_INCLUDED) + uint16_t cnt; + uint16_t fifo_num; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; +#endif + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting unsigned char type to uint16_t type is valid */ + fifo_num = (uint16_t)hdl->rom->regs->FDR.BIT.R; + + /* RX FIFO flush */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* Read byte */ + SCI_RDR(byte_rx[cnt]); + } + + /* Determine amount of space left in rx queue */ + (void)R_BYTEQ_Unused(hdl->u_rx_data.que, &cnt); + if (cnt >= fifo_num) + { + /* free space is enough */ + args.event = SCI_EVT_RX_CHAR; + } + else + { + /* insufficient free space, store as much as possible */ + fifo_num = cnt; + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* store bytes to rx queue for R_SCI_Receive */ + (void)R_BYTEQ_Put(hdl->u_rx_data.que, byte_rx[cnt]); + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + + /* Number of bytes were stored to queue */ + args.num = (uint8_t)fifo_num; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED*/ + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* SCI Receive */ + sci_fifo_receive_sync(hdl); +#endif + } + + /* When the readings of receive data are completed, set the SSRFIFO.RDF flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.RDF) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_RDF_MASK; + } + + if (SCI_MODE_ASYNC == hdl->mode) + { + if (1 == hdl->rom->regs->SSRFIFO.BIT.DR) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_DR_MASK; + } + } +} /* End of function sci_fifo_receive() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED +/***************************************************************************** +* Function Name: sci_receive_data_match +* Description : SCI receive data match +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive_data_match(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (0 == hdl->rom->regs->DCCR.BIT.DCME) /* DCME automatically set 0 when data matched */ + { + hdl->rom->regs->DCCR.BIT.DCMF = 0; /* Clear Data Match Flag */ + + if ((0 == hdl->rom->regs->DCCR.BIT.DFER ) && (0 == hdl->rom->regs->DCCR.BIT.DPER )) /* Check framing error and parity error */ + { + /* Casting unsigned char type to unin8_t type is valid */ + byte = (uint8_t)(hdl->rom->regs->CDR.BYTE.L); /* Read data from comparison data register */ + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR_MATCH; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + } +} /* End of function sci_receive_data_match() */ +#endif /* End of SCI_CFG_DATA_MATCH_INCLUDED */ + +/***************************************************************************** +* Function Name: rxi_handler +* Description : RXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void rxi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_DATA_MATCH_INCLUDED + if (1 == hdl->rom->regs->DCCR.BIT.DCMF) /* Check Data match flag */ + { + sci_receive_data_match(hdl); + } + else +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Receive */ + sci_fifo_receive(hdl); + } + else +#endif + { + /* SCI Receive */ + sci_receive(hdl); + } +} /* End of function rxi_handler() */ + + +/***************************************************************************** +* Function Name: sci_error +* Description : Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + uint8_t reg; + + reg = SCI_SSR; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Flush register */ + SCI_RDR(byte); + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + SCI_RDR(byte); + + reg = SCI_SSR; + reg &= (~SCI_RCVR_ERR_MASK); + reg |= SCI_SSR_CLR_MASK; + SCI_SSR = reg; + + if (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + +} /* End of function sci_error() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_error +* Description : FIFO Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t reg; + volatile uint8_t ssrfifo_data; + volatile uint16_t dummy; + + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = 0; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + + /* if error condition don't clear in callback when it clear at here */ + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + /* Flush register */ + /* WAIT_LOOP */ + while (0 != hdl->rom->regs->FDR.BIT.R) + { + dummy = hdl->rom->regs->FRDR.WORD; /* FRDR dummy read */ + } + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) /* Check PER, FER, ORER flags */ + { + ssrfifo_data = SCI_SSRFIFO; /* SSRFIFO dummy read */ + SCI_SSRFIFO = (uint8_t)~SCI_RCVR_ERR_MASK; /* PER, FER, ORER clear */ + if (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + } + } + + return; +} /* End of function sci_fifo_error() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: eri_handler +* Description : ERI interrupt handler for SCI UART mode +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void eri_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Error */ + sci_fifo_error(hdl); + } + else +#endif + { + /* SCI error */ + sci_error(hdl); + } +} /* End of function eri_handler() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Control +********************************************************************************************************************//** +* @brief This function configures and controls the operating mode for the SCI channel. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] cmd Command to run (see Section 3. R_SCI_Control() in application note for details) +* +* @param[in] p_args Pointer to arguments (see Section 3. R_SCI_Control() in application note for details) specific to +* command, casted to void * +* +* @retval SCI_SUCCESS Successful; channel initialized. +* +* @retval SCI_ERR_NULL_PTR hdl or p_args pointer is NULL (when required) +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INVALID_ARG +* The cmd value or an element of p_args contains an invalid value. +* @details This function is used for configuring special hardware features such as changing driver configuration and +* obtaining driver status. +* The CTS/ RTS pin functions as RTS by default hardware control. By issuing an SCI_CMD_EN_CTS_IN, the pin functions as CTS. +* @note When SCI_CMD_CHANGE_BAUD is used, the optimum values for BRR, SEMR.ABCS, and SMR.CKS is calculated based on +* the bit rate specified. This however does not guarantee a low bit error rate for all peripheral clock/baud rate +* combinations.\n +* If the command SCI_CMD_EN_CTS_IN is to be used, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Control() for details. +*/ +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err = SCI_SUCCESS; + sci_baud_t *baud; + int32_t bit_err; + + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } + + /* Check argument p_args*/ + if ((NULL == p_args) || (FIT_NO_PTR == p_args)) + { + if (SCI_CMD_CHANGE_BAUD == cmd) + { + return SCI_ERR_NULL_PTR; + } +#if SCI_CFG_FIFO_INCLUDED + if ((SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) || (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } +#if SCI_CFG_FIFO_INCLUDED + if (SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if (15 < (*(uint8_t *)p_args)) + { + return SCI_ERR_INVALID_ARG; + } + } + if (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (15 < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd)) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (BSP_MCU_IPL_MAX < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + /* COMMANDS COMMON TO ALL MODES */ + + switch (cmd) + { + case (SCI_CMD_CHANGE_BAUD): + { + /* Casting void* type is valid */ + baud = (sci_baud_t *)p_args; +#if (SCI_CFG_ASYNC_INCLUDED) + hdl->pclk_speed = baud->pclk; // save for break generation +#endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, baud->pclk, baud->rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = baud->rate; // save for break generation + } + break; + } + + case (SCI_CMD_EN_CTS_IN): + { + if (SCI_MODE_SSPI != hdl->mode) + { + /* PFS & port pins must be configured for CTS prior to calling this */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BIT.CTSE = 1; // enable CTS input + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + /* Can not use CTS in smart card interface mode, simple SPI mode, and simple I2C mode */ + err = SCI_ERR_INVALID_ARG; + } + break; + } + +#if SCI_CFG_FIFO_INCLUDED + case (SCI_CMD_CHANGE_TX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + /* save current TX FIFO threshold */ + hdl->tx_curr_thresh = *((uint8_t *)p_args); + + /* change TX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.TTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } + + case (SCI_CMD_CHANGE_RX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + /* save current RX FIFO threshold */ + hdl->rx_curr_thresh = *((uint8_t *)p_args); + + /* change RX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.RTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N) + case (SCI_CMD_SET_TXI_PRIORITY): + { + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_txi = *((uint8_t *)p_args); + break; + } + + case (SCI_CMD_SET_RXI_PRIORITY): + { + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_rxi = *((uint8_t *)p_args); + break; + } +#endif + + default: + { + /* ASYNC-SPECIFIC COMMANDS */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + err = sci_async_cmds(hdl, cmd, p_args); +#endif + } + + /* SSPI/SYNC-SPECIFIC COMMANDS */ + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_sync_cmds(hdl, cmd, p_args); +#endif + } + break; + } + } + + return err; +} /* End of function R_SCI_Control() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Close +********************************************************************************************************************//** +* @brief This function removes power from the SCI channel and disables the associated interrupts. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @retval SCI_SUCCESS Successful; channel closed +* +* @retval SCI_ERR_NULL_PTR hdl is NULL +* +* @details Disables the SCI channel designated by the handle and enters module-stop state. +* @note This function will abort any transmission or reception that may be in progress. +*/ +sci_err_t R_SCI_Close(sci_hdl_t const hdl) +{ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* disable ICU interrupts */ + sci_disable_ints(hdl); + + /* free tx and rx queues */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + R_BYTEQ_Close(hdl->u_tx_data.que); + R_BYTEQ_Close(hdl->u_rx_data.que); + } +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset FIFO threshold */ + hdl->rx_curr_thresh = hdl->rx_dflt_thresh; + hdl->tx_curr_thresh = hdl->tx_dflt_thresh; + } +#endif + + /* mark the channel as not in use and power down */ + hdl->mode = SCI_MODE_OFF; + power_off(hdl); + + return SCI_SUCCESS; +} /* End of function R_SCI_Close() */ + + +/*********************************************************************************************************************** +* Function Name: R_SCI_GetVersion +********************************************************************************************************************//** +* @brief This function returns the driver version number at runtime. +* @return Version number. +* @details Returns the version of this module. The version number is encoded such that the top 2 bytes are the major +* version number and the bottom 2 bytes are the minor version number. +* @note None +*/ +uint32_t R_SCI_GetVersion(void) +{ + uint32_t const version = (SCI_VERSION_MAJOR << 16) | SCI_VERSION_MINOR; + + return version; +} /* End of function R_SCI_GetVersion() */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h new file mode 100644 index 000000000..892f8820c --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx_platform.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_platform.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 Added RX24U support +* 28.09.2018 2.10 Added RX66T support +* 01.02.2019 2.20 Added RX72T, RX65N-64pin support +* 28.06.2019 3.10 Added RX23W support +* 15.08.2019 3.20 Added RX72M support +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +************************************************************************************************************************/ + +#ifndef SCI_RX_PLATFORM_H +#define SCI_RX_PLATFORM_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sci_rx_if.h" + +#if defined(BSP_MCU_RX110) +#include "./targets/rx110/r_sci_rx110_private.h" /* RX110 */ +#elif defined(BSP_MCU_RX111) +#include "./targets/rx111/r_sci_rx111_private.h" /* RX111 */ +#elif defined(BSP_MCU_RX113) +#include "./targets/rx113/r_sci_rx113_private.h" /* RX113 */ +#elif defined(BSP_MCU_RX130) +#include "./targets/rx130/r_sci_rx130_private.h" /* RX130 */ +#elif defined(BSP_MCU_RX13T) +#include "./targets/rx13t/r_sci_rx13t_private.h" /* RX13T */ +#elif defined(BSP_MCU_RX230) +#include "./targets/rx230/r_sci_rx230_private.h" /* RX230 */ +#elif defined(BSP_MCU_RX231) +#include "./targets/rx231/r_sci_rx231_private.h" /* RX231 */ +#elif defined(BSP_MCU_RX23E_A) +#include "./targets/rx23e-a/r_sci_rx23e-a_private.h" /* RX23E-A */ +#elif defined(BSP_MCU_RX23T) +#include "./targets/rx23t/r_sci_rx23t_private.h" /* RX23T */ +#elif defined(BSP_MCU_RX23W) +#include "./targets/rx23w/r_sci_rx23w_private.h" /* RX23W */ +#elif defined(BSP_MCU_RX24T) +#include "./targets/rx24t/r_sci_rx24t_private.h" /* RX24T */ +#elif defined(BSP_MCU_RX24U) +#include "./targets/rx24u/r_sci_rx24u_private.h" /* RX24U */ +#elif defined(BSP_MCU_RX64M) +#include "./targets/rx64m/r_sci_rx64m_private.h" /* RX64M */ +#elif defined(BSP_MCU_RX65N) +#include "./targets/rx65n/r_sci_rx65n_private.h" /* RX65N */ +#elif defined(BSP_MCU_RX66T) +#include "./targets/rx66t/r_sci_rx66t_private.h" /* RX66T */ +#elif defined(BSP_MCU_RX66N) +#include "./targets/rx66n/r_sci_rx66n_private.h" /* RX66N */ +#elif defined(BSP_MCU_RX71M) +#include "./targets/rx71m/r_sci_rx71m_private.h" /* RX71M */ +#elif defined(BSP_MCU_RX72T) +#include "./targets/rx72t/r_sci_rx72t_private.h" /* RX72T */ +#elif defined(BSP_MCU_RX72M) +#include "./targets/rx72m/r_sci_rx72m_private.h" /* RX72M */ +#elif defined(BSP_MCU_RX72N) +#include "./targets/rx72n/r_sci_rx72n_private.h" /* RX72N */ +#else +#error "ERROR - r_sci_rxXXX_private.h not included." +#endif + +#endif /* SCI_RX_PLATFORM_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h new file mode 100644 index 000000000..72ed5f11f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/r_sci_rx_private.h @@ -0,0 +1,184 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_private.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 28.09.2018 2.10 Added SCI_CFG_DATA_MATCH_INCLUDED for configuration data match function. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support received data match function for RX65N (SCI10 and SCI11). +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0 to SCI11). +* Added support FIFO mode for RX72M (SCI7 to SCI11). +***********************************************************************************************************************/ + +#ifndef SCI_RX_H +#define SCI_RX_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../r_sci_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Bit position masks */ +#define BIT0_MASK (0x00000001U) +#define BIT1_MASK (0x00000002U) +#define BIT2_MASK (0x00000004U) +#define BIT3_MASK (0x00000008U) +#define BIT4_MASK (0x00000010U) +#define BIT5_MASK (0x00000020U) +#define BIT6_MASK (0x00000040U) +#define BIT7_MASK (0x00000080U) +#define BIT8_MASK (0x00000100U) +#define BIT9_MASK (0x00000200U) +#define BIT10_MASK (0x00000400U) +#define BIT11_MASK (0x00000800U) +#define BIT12_MASK (0x00001000U) +#define BIT13_MASK (0x00002000U) +#define BIT14_MASK (0x00004000U) +#define BIT15_MASK (0x00008000U) +#define BIT16_MASK (0x00010000U) +#define BIT17_MASK (0x00020000U) +#define BIT18_MASK (0x00040000U) +#define BIT19_MASK (0x00080000U) +#define BIT20_MASK (0x00100000U) +#define BIT21_MASK (0x00200000U) +#define BIT22_MASK (0x00400000U) +#define BIT23_MASK (0x00800000U) +#define BIT24_MASK (0x01000000U) +#define BIT25_MASK (0x02000000U) +#define BIT26_MASK (0x04000000U) +#define BIT27_MASK (0x08000000U) +#define BIT28_MASK (0x10000000U) +#define BIT29_MASK (0x20000000U) +#define BIT30_MASK (0x40000000U) +#define BIT31_MASK (0x80000000U) + +#ifndef NULL /* Resolves e2studio code analyzer false error message. */ + #define NULL (0) +#endif + +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || \ + (SCI_CFG_CH8_FIFO_INCLUDED) || \ + (SCI_CFG_CH9_FIFO_INCLUDED) || \ + (SCI_CFG_CH10_FIFO_INCLUDED) || \ + (SCI_CFG_CH11_FIFO_INCLUDED)) + #define SCI_CFG_FIFO_INCLUDED (1) +#endif + +#if ((SCI_CFG_CH0_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH1_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH2_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH3_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH4_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH5_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH6_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH7_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH8_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH9_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH10_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH11_DATA_MATCH_INCLUDED)) + #define SCI_CFG_DATA_MATCH_INCLUDED (1) +#endif + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_ORER (hdl->rom->regs->SSRFIFO.BIT.ORER) +#define SCI_SSRFIFO_PER (hdl->rom->regs->SSRFIFO.BIT.PER) +#define SCI_SSRFIFO_FER (hdl->rom->regs->SSRFIFO.BIT.FER) +#define SCI_SSRFIFO_RDF (hdl->rom->regs->SSRFIFO.BIT.RDF) +#define SCI_SSRFIFO (hdl->rom->regs->SSRFIFO.BYTE) +#endif +#define SCI_SSR_ORER (hdl->rom->regs->SSR.BIT.ORER) +#define SCI_SSR_PER (hdl->rom->regs->SSR.BIT.PER) +#define SCI_SSR_FER (hdl->rom->regs->SSR.BIT.FER) +#define SCI_SSR (hdl->rom->regs->SSR.BYTE) + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_FIFO_FRAME_SIZE (16) +#endif + +/* SCR register dummy read */ +#define SCI_SCR_DUMMY_READ \ + if (0x00 == hdl->rom->regs->SCR.BYTE) \ + { \ + R_BSP_NOP(); \ + } + +/* Interrupt Request register flag clear */ +#define SCI_IR_TXI_CLEAR (*hdl->rom->ir_txi = 0) + +/* TDR/FTDR register write access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_TDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + hdl->rom->regs->FTDR.BYTE.L = (byte); \ + } \ + else \ + { \ + hdl->rom->regs->TDR = (byte); \ + } +#else +#define SCI_TDR(byte) \ + hdl->rom->regs->TDR = (byte); +#endif + +/* RDR/FRDR register read access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_RDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + (byte) = hdl->rom->regs->FRDR.BYTE.L; \ + } \ + else \ + { \ + (byte) = hdl->rom->regs->RDR; \ + } +#else +#define SCI_RDR(byte) \ + (byte) = hdl->rom->regs->RDR; +#endif + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +extern void txi_handler(sci_hdl_t const hdl); +#endif + +#if SCI_CFG_TEI_INCLUDED +extern void tei_handler(sci_hdl_t const hdl); +#endif + +extern void rxi_handler(sci_hdl_t const hdl); + +extern void eri_handler(sci_hdl_t const hdl); + +#endif /* SCI_RX_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c new file mode 100644 index 000000000..10c9f9974 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n.c @@ -0,0 +1,1448 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx72n.c +* Description : Functions for using SCI on the RX72N device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx72n_private.h" + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/***************************************************************************** +* Function Name: sci_mcu_param_check +* Description : This function parameters check on MCU. +* (channel range, interrupt priority, etc...) +* Arguments : chan - +* channel to check +* Return Value : SCI_SUCCESS - +* parameter check all successfully +* SCI_ERR_BAD_CHAN - +* channel number invalid for part +* SCI_ERR_INVALID_ARG - +* interrupt priority out of range +******************************************************************************/ +sci_err_t sci_mcu_param_check(uint8_t const chan) +{ + /* channel range parameter check */ + if (SCI_NUM_CH <= chan) + { + return SCI_ERR_BAD_CHAN; + } + + /* interrupt priority configuration parameter check */ + if ((1 > SCI_CFG_ERI_TEI_PRIORITY) || (15 < SCI_CFG_ERI_TEI_PRIORITY)) + { + return SCI_ERR_INVALID_ARG; + } + + return SCI_SUCCESS; +} /* End of function sci_mcu_param_check() */ + +/***************************************************************************** +* Function Name: sci_init_register +* Description : This function initializes the register for SCI. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_init_register(sci_hdl_t const hdl) +{ + /* SCI transmit enable bit and receive enable bit check & disable */ + /* WAIT_LOOP */ + while ((0 != hdl->rom->regs->SCR.BIT.TE) || (0 != hdl->rom->regs->SCR.BIT.RE)) + { + if (0 != hdl->rom->regs->SCR.BIT.TE) + { + hdl->rom->regs->SCR.BIT.TE = 0; // transmit disable + } + + if (0 != hdl->rom->regs->SCR.BIT.RE) + { + hdl->rom->regs->SCR.BIT.RE = 0; // receive disable + } + } + + /* SMR register initialize */ + hdl->rom->regs->SMR.BYTE = 0x00; + + /* SCR register initialize */ + hdl->rom->regs->SCR.BYTE = 0x00; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SSRFIFO register initialize */ + if (1 == SCI_SSRFIFO_ORER) + { + SCI_SSRFIFO_ORER = 0; + } + + if (1 == SCI_SSRFIFO_PER) + { + SCI_SSRFIFO_PER = 0; + } + + if (1 == SCI_SSRFIFO_FER) + { + SCI_SSRFIFO_FER = 0; + } + + if (1 == SCI_SSRFIFO_RDF) + { + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + SCI_SSRFIFO_RDF = 0; + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { + /* SSR register initialize */ + if (1 == SCI_SSR_ORER) + { + SCI_SSR_ORER = 0; + } + + if (1 == SCI_SSR_PER) + { + SCI_SSR_PER = 0; + } + + if (1 == SCI_SSR_FER) + { + SCI_SSR_FER = 0; + } + } + + /* SCMR register initialize */ + hdl->rom->regs->SCMR.BIT.SMIF = 0; + hdl->rom->regs->SCMR.BIT.SINV = 0; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + + /* BRR register initialize */ + hdl->rom->regs->BRR = 0xFF; + + /* SEMR register initialize */ + hdl->rom->regs->SEMR.BIT.BRME = 0; + hdl->rom->regs->SEMR.BIT.ABCS = 0; + hdl->rom->regs->SEMR.BIT.NFEN = 0; + hdl->rom->regs->SEMR.BIT.BGDM = 0; + hdl->rom->regs->SEMR.BIT.RXDESEL = 0; + + /* SNFR register initialize */ + hdl->rom->regs->SNFR.BYTE = 0; + + /* SPMR register initialize */ + hdl->rom->regs->SPMR.BIT.CTSE = 0; + hdl->rom->regs->SPMR.BIT.CKPOL = 0; + hdl->rom->regs->SPMR.BIT.CKPH = 0; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* FCR register initialize */ + hdl->rom->regs->FCR.BIT.FM = 0; + hdl->rom->regs->FCR.BIT.TFRST = 0; + hdl->rom->regs->FCR.BIT.RFRST = 0; + hdl->rom->regs->FCR.BIT.TTRG = 0; + hdl->rom->regs->FCR.BIT.RTRG = 8; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED + /* DCCR register initialize */ + hdl->rom->regs->DCCR.BIT.DCME = 0; + hdl->rom->regs->DCCR.BIT.DCMF = 0; + hdl->rom->regs->DCCR.BIT.DFER = 0; + hdl->rom->regs->DCCR.BIT.DPER = 0; + hdl->rom->regs->DCCR.BIT.IDSEL = 0; + + /* CDR register initialize */ + hdl->rom->regs->CDR.BYTE.L = 0; + + /* Set initial value of receive in 8-bit data length */ + hdl->rom->regs->SMR.BIT.CHR = 0; + hdl->rom->regs->SCMR.BIT.CHR1 = 1; +#endif + + return; +} /* End of function sci_init_register() */ + +/***************************************************************************** +* Function Name: sci_init_bit_rate +* Description : This function determines the best possible settings for the +* baud rate registers for the specified peripheral clock speed +* and baud rate. Note that this does not guarantee a low bit +* error rate, just the best possible one. The bit rate error is +* returned in .1% increments. If the hardware cannot support +* the specified combination, a value of 1000 (100% error) is +* returned. +* +* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled +* prior to calling this function. +* +* The application must pause for 1 bit time after the BRR register +* is loaded before transmitting/receiving to allow time for the clock +* to settle. +* +* Arguments : hdl - +* Handle for channel (ptr to chan control block) +* NOTE: mode element must be already set +* pclk - +* Peripheral clock speed; e.g. 24000000 for 24MHz +* baud - +* Baud rate; 19200, 57600, 115200, etc. +* Return Value : bit error in .1% increments; e.g. 16 = 1.6% bit rate error +* a value of 1000 denotes 100% error; no registers set +******************************************************************************/ +int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud) +{ + uint32_t i; + uint32_t num_divisors = 0; + uint32_t ratio; + uint32_t tmp; + baud_divisor_t const *p_baud_info = NULL; + + uint32_t divisor; + uint32_t int_M; + float float_M; + float error; + float abs_error; + +#if SCI_CFG_FIFO_INCLUDED + uint8_t brr; +#endif + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((0 == pclk) || (0 == baud)) + { + return 1000; + } +#endif + + /* SELECT PROPER TABLE BASED UPON MODE */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + p_baud_info = async_baud; + num_divisors = NUM_DIVISORS_ASYNC; +#endif + } + else + { + /* SYNC or SSPI */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + p_baud_info = sync_baud; + num_divisors = NUM_DIVISORS_SYNC; +#endif + } + + /* FIND DIVISOR; table has associated ABCS, BGDM and CKS values */ + /* BRR must be 255 or less */ + /* the "- 1" is ignored in some steps for approximations */ + /* BRR = (PCLK/(divisor * baud)) - 1 */ + /* BRR = (ratio / divisor) - 1 */ + ratio = pclk/baud; + + /* WAIT_LOOP */ + for(i = 0; i < num_divisors; i++) + { + /* Casting int16_t to uint32_t is valid. Because clock divisor is positive integer */ + if (ratio < (uint32_t)(p_baud_info[i].divisor * 256)) + { + break; + } + } + + /* RETURN IF BRR WILL BE >255 OR LESS THAN 0 */ + if (i == num_divisors) + { + return(1000); // impossible baud rate requested; return 100% error + } + + /* Casting int16_t to uint32_t is valid. Because clock divisor is a positive integer */ + divisor = (uint32_t)p_baud_info[i].divisor; + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + if(0 == tmp) + { + return(1000); // illegal value; return 100% error + } + + /* SET BRR, ABCS, BDGM, and CKS */ + tmp = ratio / (divisor/2); // divide by half the divisor + +#if SCI_CFG_FIFO_INCLUDED + /* Casting is valid. Because result of calculation is in range uint8_t type */ + brr = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + if (0 == brr) + { + if (true == hdl->fifo_ctrl) + { + if (1 == hdl->rom->regs->SMR.BIT.CM) + { + if (0 == hdl->rom->regs->SMR.BIT.CKS) + { + return(1000); + } + } + } + } +#endif + + /* if odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */ + hdl->rom->regs->BRR = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + hdl->rom->regs->SEMR.BIT.ABCS = p_baud_info[i].abcs; + hdl->rom->regs->SEMR.BIT.BGDM = p_baud_info[i].bgdm; + hdl->rom->regs->SMR.BIT.CKS = p_baud_info[i].cks; + + /* CALCULATE BIT RATE ERROR. + * RETURN IF ERROR LESS THAN 1% OR IF IN SYNCHRONOUS/SSPI MODE. + */ + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + + /* Casting uint32_t to float is valid */ + error = ( ((float)pclk / ((baud * divisor) * tmp)) - 1) * 100; + abs_error = (error < 0) ? (-error) : error; + + if ((abs_error <= 1.0) || (SCI_MODE_ASYNC != hdl->mode)) + { + hdl->rom->regs->SEMR.BIT.BRME = 0; // disable MDDR + + /* Casting float to uint32_t */ + return (uint32_t)(error*10); + } + + /* CALCULATE M ASSUMING A 0% ERROR then WRITE REGISTER */ + hdl->rom->regs->BRR = (uint8_t)(tmp-1); + + /* Casting uint32_t to float is valid */ + float_M = ((float)((baud * divisor) * 256) * tmp) / pclk; + float_M *= 2; + + /* Casting float to uint32_t */ + int_M = (uint32_t)float_M; + int_M = (int_M & 0x01) ? ((int_M/2) + 1) : (int_M/2); + + /* Casting uint32_t type to uint8_t type in this case is valid. Range value of m is not exceed uint8_t */ + hdl->rom->regs->MDDR = (uint8_t)int_M; // write M + hdl->rom->regs->SEMR.BIT.BRME = 1; // enable MDDR + + /* Casting uint32_t to float is valid*/ + error = (( (float)(pclk) / (((divisor * tmp) * baud) * ((float)(256)/int_M)) ) - 1) * 100; + + /* Casting float to int32_t */ + return (int32_t)(error*10); +} /* End of function sci_init_bit_rate() */ + +/***************************************************************************** +* Function Name: sci_initialize_ints +* Description : This function sets priority, clears flags, and sets +* interrupts in both the ICU and SCI peripheral. These include +* RXI, TXI, TEI, and ERI/GROUP12 interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* priority - +* priority for interrupts +* Return Value : none +******************************************************************************/ +void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority) +{ + volatile bsp_int_ctrl_t group_priority; + + /* SET PRIORITY FOR INTERRUPTS */ + *hdl->rom->ipr_rxi = priority; // can set separately using Control() + *hdl->rom->ipr_txi = priority; + + group_priority.ipl = 0x00000000; +#if ((SCI_CFG_CH0_INCLUDED == 1) || (SCI_CFG_CH1_INCLUDED == 1) || (SCI_CFG_CH2_INCLUDED == 1) || \ + (SCI_CFG_CH3_INCLUDED == 1) || (SCI_CFG_CH4_INCLUDED == 1) || (SCI_CFG_CH5_INCLUDED == 1) || \ + (SCI_CFG_CH6_INCLUDED == 1) || (SCI_CFG_CH12_INCLUDED == 1)) + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPBL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } +#endif + + +#if ((SCI_CFG_CH7_INCLUDED == 1) || (SCI_CFG_CH8_INCLUDED == 1) || (SCI_CFG_CH9_INCLUDED == 1) || \ + (SCI_CFG_CH10_INCLUDED == 1) || (SCI_CFG_CH11_INCLUDED == 1)) + + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPAL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } +#endif + + /* DISABLE ERI INTERRUPT */ + DISABLE_ERI_INT; + + /* DISABLE RXI INTERRUPT */ + DISABLE_RXI_INT; + + /* DISABLE TXI INTERRUPT */ + DISABLE_TXI_INT; + + /* DISABLE TEI INTERRUPT */ + DISABLE_TEI_INT; + + /* CLEAR INTERRUPT FLAGS */ + *hdl->rom->ir_rxi = 0; + *hdl->rom->ir_txi = 0; + (*hdl->rom->icu_grp) &= (~hdl->rom->tei_ch_mask); + (*hdl->rom->icu_grp) &= (~hdl->rom->eri_ch_mask); + + /* REGISTER GROUP INTERRUPTS WITH BSP */ + #if SCI_CFG_TEI_INCLUDED + R_BSP_InterruptWrite(hdl->rom->tei_vector, hdl->rom->tei_isr); + #endif + R_BSP_InterruptWrite(hdl->rom->eri_vector, hdl->rom->eri_isr); + + /* ENABLE GROUP INTERRUPTS */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, (void *)&group_priority); + + /* ENABLE ERI AND RXI INTERRUPTS REQUESTS */ + ENABLE_ERI_INT; + ENABLE_RXI_INT; + + /* ENABLE INTERRUPTS IN SCI PERIPHERAL */ + /* Note: Enable interrupts after xcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; // enable TE, RE, TXI, and RXI/ERI + + return; +} /* End of function sci_initialize_ints() */ + +/***************************************************************************** +* Function Name: sci_disable_ints +* Description : This function disable interrupts in both the ICU and SCI +* peripheral. These include RXI, TXI, TEI, ERI, and group +* interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_disable_ints(sci_hdl_t const hdl) +{ + volatile bsp_int_ctrl_t group_priority; + + /* Disable ICU RXI interrupt */ + DISABLE_RXI_INT; + + /* Disable ICU TXI interrupt */ + DISABLE_TXI_INT; + + /* Disable ICU ERI interrupt */ + DISABLE_ERI_INT; + + /* Disable ICU TEI interrupt */ + DISABLE_TEI_INT; + + /* disable peripheral interrupts and xcvr (TE and RE) */ + hdl->rom->regs->SCR.BYTE = 0; + + /* disable group interrupts */ + group_priority.ipl = 0x00000000; + + /* Casting pointer to void* is valid */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, (void *)&group_priority); + + return; +} /* End of function sci_disable_ints() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_async_cmds +* Description : This function configures non-standard UART hardware and +* performs special software operations. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +******************************************************************************/ +sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + uint32_t slow_baud; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + + /* Check parameters */ + if (((NULL == p_args) || (FIT_NO_PTR == p_args)) + && ((SCI_CMD_TX_Q_BYTES_FREE == cmd) || (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ == cmd)|| (SCI_CMD_COMPARE_RECEIVED_DATA == cmd))) + { + return SCI_ERR_NULL_PTR; + } + +#endif + + switch(cmd) + { + case (SCI_CMD_EN_NOISE_CANCEL): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.NFEN = 1; /* enable noise filter */ + hdl->rom->regs->SNFR.BYTE = 0; /* clock divided by 1 (default) */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_OUTPUT_BAUD_CLK): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCR.BIT.CKE = 0x01; /* output baud clock on SCK pin */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_START_BIT_EDGE): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.RXDESEL = 1; /* detect start bit on falling edge */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + #if SCI_CFG_TEI_INCLUDED + case (SCI_CMD_EN_TEI): /* SCI_CMD_EN_TEI is obsolete command, but it exists only for compatibility with older version. */ + { + break; + } + #endif + + case (SCI_CMD_TX_Q_FLUSH): + { + /* Disable TXI interrupt */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + break; + } + + case (SCI_CMD_RX_Q_FLUSH): + { + /* Disable RXI interrupt */ + DISABLE_RXI_INT; + R_BYTEQ_Flush(hdl->u_rx_data.que); + ENABLE_RXI_INT; + break; + } + + case (SCI_CMD_TX_Q_BYTES_FREE): + { + /* Casting pointer void* to uint16_t* type is valid */ + R_BYTEQ_Unused(hdl->u_tx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ): + { + /* Casting pointer void* type to uint16_t* type is valid */ + R_BYTEQ_Used(hdl->u_rx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_GENERATE_BREAK): + { + /* flush transmit queue */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + + /* NOTE: the following steps will abort anything being sent */ + + /* set baud rate 1.5x slower */ + slow_baud = (hdl->baud_rate << 1) / 3; + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, slow_baud); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; + } + else + { + /* transmit "0" and wait for completion */ + SCI_TDR(0); + + /* WAIT_LOOP */ + while (0 == hdl->rom->regs->SSR.BIT.TEND) + { + R_BSP_NOP(); + } + + /* restore original baud rate */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + sci_init_bit_rate(hdl, hdl->pclk_speed, hdl->baud_rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + break; + } + + #if SCI_CFG_DATA_MATCH_INCLUDED + case SCI_CMD_COMPARE_RECEIVED_DATA: + { + hdl->rom->regs->DCCR.BIT.DFER = 0; /* Clear Match Data Framing Error Flag */ + hdl->rom->regs->DCCR.BIT.DPER = 0; /* Clear Match Data Parity Error Flag */ + hdl->rom->regs->DCCR.BIT.DCME = 1; /* Enable Data match function */ + hdl->rom->regs->CDR.BYTE.L = *((unsigned char *)p_args); /* Comparison data */ + break; + } + #endif + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_async_cmds() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_sync_cmds +* Description : This function performs special software operations specific +* to the SSPI and SYNC protocols. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +* May be due to mode channel is operating in. +******************************************************************************/ +sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_spi_mode_t spi_mode; + sci_cb_args_t args; + sci_err_t err = SCI_SUCCESS; + + switch (cmd) + { + case (SCI_CMD_CHECK_XFER_DONE): + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XFER_NOT_DONE; + } + break; + } + + case (SCI_CMD_XFER_LSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_XFER_MSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_INVERT_DATA): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SINV ^= 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_ABORT_XFER): + { + /* Disable receive interrupts in ICU and peripheral */ + DISABLE_RXI_INT; + DISABLE_ERI_INT; + + hdl->rom->regs->SCR.BYTE &= (~(SCI_SCR_REI_MASK | SCI_SCR_RE_MASK | SCI_SCR_TE_MASK)); + + hdl->tx_cnt = 0; + hdl->tx_dummy = false; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_ABORTED; + + /* Casting pointer to void* is valid */ + hdl->callback((void *)&args); + } + + *hdl->rom->ir_rxi = 0; /* clear rxi interrupt flag */ + (*hdl->rom->icu_grp) &= (~hdl->rom->eri_ch_mask); /* clear eri interrupt flag */ + + ENABLE_ERI_INT; /* enable rx err interrupts in ICU */ + ENABLE_RXI_INT; /* enable receive interrupts in ICU */ + + /* Enable receive interrupt in peripheral after rcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK); + hdl->rom->regs->SCR.BYTE |= SCI_SCR_REI_MASK; + break; + } + + case (SCI_CMD_CHANGE_SPI_MODE): + { + #if SCI_CFG_PARAM_CHECKING_ENABLE + + if (SCI_MODE_SSPI != hdl->mode) + { + return SCI_ERR_INVALID_ARG; + } + + /* Check parameters */ + if ((NULL == p_args ) || (FIT_NO_PTR == p_args)) + { + return SCI_ERR_NULL_PTR; + } + + /* Casting pointer void* type is valid */ + spi_mode = *((sci_spi_mode_t *)p_args); + + if ((SCI_SPI_MODE_0 != spi_mode) && (SCI_SPI_MODE_1 != spi_mode) + && (SCI_SPI_MODE_2 != spi_mode) && (SCI_SPI_MODE_3 != spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + #endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BYTE &= 0x3F; /* clear previous mode */ + hdl->rom->regs->SPMR.BYTE |= (*((uint8_t *)p_args)); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_sync_cmds() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +ISRs +******************************************************************************/ + + +#if (SCI_CFG_ASYNC_INCLUDED) + +/***************************************************************************** +* sciN_txiN_isr +* Description : TXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_txi0_isr + * Description : TXI interrupt routines for SCI0 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_txi0_isr, VECT(SCI0,TXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_txi0_isr(void) +{ + txi_handler(&ch0_ctrl); +} /* End of function sci0_txi0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED  */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_txi1_isr + * Description : TXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_txi1_isr, VECT(SCI1,TXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void) +{ + txi_handler(&ch1_ctrl); +} /* End of function sci1_txi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED  */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_txi2_isr + * Description : TXI interrupt routines for SCI2 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci2_txi2_isr, VECT(SCI2,TXI2)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci2_txi2_isr(void) +{ + txi_handler(&ch2_ctrl); +} /* End of function sci2_txi2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED  */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_txi3_isr + * Description : TXI interrupt routines for SCI3 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci3_txi3_isr, VECT(SCI3,TXI3)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci3_txi3_isr(void) +{ + txi_handler(&ch3_ctrl); +} /* End of function sci3_txi3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED  */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_txi4_isr + * Description : TXI interrupt routines for SCI4 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci4_txi4_isr, VECT(SCI4,TXI4)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci4_txi4_isr(void) +{ + txi_handler(&ch4_ctrl); +} /* End of function sci4_txi4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED  */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_txi5_isr + * Description : TXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_txi5_isr, VECT(SCI5,TXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void) +{ + txi_handler(&ch5_ctrl); +} /* End of function sci5_txi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED  */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_txi6_isr + * Description : TXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_txi6_isr, VECT(SCI6,TXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void) +{ + txi_handler(&ch6_ctrl); +} /* End of function sci6_txi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED  */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_txi7_isr + * Description : TXI interrupt routines for SCI7 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci7_txi7_isr, VECT(SCI7,TXI7)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci7_txi7_isr(void) +{ + txi_handler(&ch7_ctrl); +} /* End of function sci7_txi7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED  */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_txi8_isr + * Description : TXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_txi8_isr, VECT(SCI8,TXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void) +{ + txi_handler(&ch8_ctrl); +} /* End of function sci8_txi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED  */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_txi9_isr + * Description : TXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_txi9_isr, VECT(SCI9,TXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void) +{ + txi_handler(&ch9_ctrl); +} /* End of function sci9_txi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED  */ + +#if SCI_CFG_CH10_INCLUDED +/******************************************************************************* + * Function Name: sci10_txi10_isr + * Description : TXI interrupt routines for SCI10 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci10_txi10_isr, VECT(SCI10,TXI10)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci10_txi10_isr(void) +{ + txi_handler(&ch10_ctrl); +} /* End of function sci10_txi10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED  */ + +#if SCI_CFG_CH11_INCLUDED +/******************************************************************************* + * Function Name: sci11_txi11_isr + * Description : TXI interrupt routines for SCI11 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci11_txi11_isr, VECT(SCI11,TXI11)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci11_txi11_isr(void) +{ + txi_handler(&ch11_ctrl); +} /* End of function sci11_txi11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED  */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_txi12_isr + * Description : TXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_txi12_isr, VECT(SCI12,TXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void) +{ + txi_handler(&ch12_ctrl); +} /* End of function sci12_txi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED  */ + +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* sciN_teiN_isr +* +* Description : TEI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_tei0_isr + * Description : TEI interrupt routines for SCI0 channel. + ******************************************************************************/ +void sci0_tei0_isr(void *cb_args) +{ + tei_handler(&ch0_ctrl); +} /* End of function sci0_tei0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_tei1_isr + * Description : TEI interrupt routines for SCI1 channel. + ******************************************************************************/ +void sci1_tei1_isr(void *cb_args) +{ + tei_handler(&ch1_ctrl); +} /* End of function sci1_tei1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_tei2_isr + * Description : TEI interrupt routines for SCI2 channel. + ******************************************************************************/ +void sci2_tei2_isr(void *cb_args) +{ + tei_handler(&ch2_ctrl); +} /* End of function sci2_tei2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_tei3_isr + * Description : TEI interrupt routines for SCI3 channel. + ******************************************************************************/ +void sci3_tei3_isr(void *cb_args) +{ + tei_handler(&ch3_ctrl); +} /* End of function sci3_tei3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_tei4_isr + * Description : TEI interrupt routines for SCI4 channel. + ******************************************************************************/ +void sci4_tei4_isr(void *cb_args) +{ + tei_handler(&ch4_ctrl); +} /* End of function sci4_tei4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_tei5_isr + * Description : TEI interrupt routines for SCI5 channel. + ******************************************************************************/ +void sci5_tei5_isr(void *cb_args) +{ + tei_handler(&ch5_ctrl); +} /* End of function sci5_tei5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_tei6_isr + * Description : TEI interrupt routines for SCI6 channel. + ******************************************************************************/ +void sci6_tei6_isr(void *cb_args) +{ + tei_handler(&ch6_ctrl); +} /* End of function sci6_tei6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_tei7_isr + * Description : TEI interrupt routines for SCI7 channel. + ******************************************************************************/ +void sci7_tei7_isr(void *cb_args) +{ + tei_handler(&ch7_ctrl); +} /* End of function sci7_tei7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function Name: sci8_tei8_isr +* Description : TEI interrupt routines for SCI8 channel. +******************************************************************************/ +void sci8_tei8_isr(void *cb_args) +{ + tei_handler(&ch8_ctrl); +} /* End of function sci8_tei8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_tei9_isr +* Description : TEI interrupt routines for SCI9 channel. +******************************************************************************/ +void sci9_tei9_isr(void *cb_args) +{ + tei_handler(&ch9_ctrl); +} /* End of function sci9_tei9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/***************************************************************************** +* Function Name: sci10_tei10_isr +* Description : TEI interrupt routines for SCI10 channel. +******************************************************************************/ +void sci10_tei10_isr(void *cb_args) +{ + tei_handler(&ch10_ctrl); +} /* End of function sci10_tei10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/***************************************************************************** +* Function name: sci11_tei11_isr +* Description : TEI interrupt routines for SCI11 channel. +******************************************************************************/ +void sci11_tei11_isr(void *cb_args) +{ + tei_handler(&ch11_ctrl); +} /* End of function sci11_tei11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function Name: sci12_tei12_isr +* Description : TEI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_tei12_isr(void *cb_args) +{ + tei_handler(&ch12_ctrl); +} /* End of function sci12_tei12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +#endif /* SCI_CFG_TEI_INCLUDED */ + +/***************************************************************************** +* sciN_rxiN_isr +* Description : RXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/******************************************************************************* + * Function Name: sci0_rxi0_isr + * Description : RXI interrupt routines for SCI0 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_rxi0_isr, VECT(SCI0,RXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_rxi0_isr(void) +{ + rxi_handler(&ch0_ctrl); +} /* End of function sci0_rxi0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_rxi1_isr + * Description : RXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_rxi1_isr, VECT(SCI1,RXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void) +{ + rxi_handler(&ch1_ctrl); +} /* End of function sci1_rxi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/******************************************************************************* + * Function Name: sci2_rxi2_isr + * Description : RXI interrupt routines for SCI2 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci2_rxi2_isr, VECT(SCI2,RXI2)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci2_rxi2_isr(void) +{ + rxi_handler(&ch2_ctrl); +} /* End of function sci2_rxi2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/******************************************************************************* + * Function Name: sci3_rxi3_isr + * Description : RXI interrupt routines for SCI3 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci3_rxi3_isr, VECT(SCI3,RXI3)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci3_rxi3_isr(void) +{ + rxi_handler(&ch3_ctrl); +} /* End of function sci3_rxi3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/******************************************************************************* + * Function Name: sci4_rxi4_isr + * Description : RXI interrupt routines for SCI4 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci4_rxi4_isr, VECT(SCI4,RXI4)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci4_rxi4_isr(void) +{ + rxi_handler(&ch4_ctrl); +} /* End of function sci4_rxi4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_rxi5_isr + * Description : RXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_rxi5_isr, VECT(SCI5,RXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void) +{ + rxi_handler(&ch5_ctrl); +} /* End of function sci5_rxi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_rxi6_isr + * Description : RXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_rxi6_isr, VECT(SCI6,RXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void) +{ + rxi_handler(&ch6_ctrl); +} /* End of function sci6_rxi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/******************************************************************************* + * Function Name: sci7_rxi7_isr + * Description : RXI interrupt routines for SCI7 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci7_rxi7_isr, VECT(SCI7,RXI7)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci7_rxi7_isr(void) +{ + rxi_handler(&ch7_ctrl); +} /* End of function sci7_rxi7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_rxi8_isr + * Description : RXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_rxi8_isr, VECT(SCI8,RXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void) +{ + rxi_handler(&ch8_ctrl); +} /* End of function sci8_rxi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_rxi9_isr + * Description : RXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_rxi9_isr, VECT(SCI9,RXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void) +{ + rxi_handler(&ch9_ctrl); +} /* End of function sci9_rxi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/******************************************************************************* + * Function Name: sci10_rxi10_isr + * Description : RXI interrupt routines for SCI10 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci10_rxi10_isr, VECT(SCI10,RXI10)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci10_rxi10_isr(void) +{ + rxi_handler(&ch10_ctrl); +} /* End of function sci10_rxi10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/******************************************************************************* + * Function Name: sci11_rxi11_isr + * Description : RXI interrupt routines for SCI11 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci11_rxi11_isr, VECT(SCI11,RXI11)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci11_rxi11_isr(void) +{ + rxi_handler(&ch11_ctrl); +} /* End of function sci11_rxi11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_rxi12_isr + * Description : RXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_rxi12_isr, VECT(SCI12,RXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void) +{ + rxi_handler(&ch12_ctrl); +} /* End of function sci12_rxi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +/***************************************************************************** +* sciN_eriN_isr +* +* Description : ERI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +/***************************************************************************** +* Function name: sci0_eri0_isr +* Description : ERI interrupt routines for SCI0 channel. +******************************************************************************/ +void sci0_eri0_isr(void *cb_args) +{ + eri_handler(&ch0_ctrl); +} /* End of function sci0_eri0_isr() */ +#endif /* End of SCI_CFG_CH0_INCLUDED */ + +#if SCI_CFG_CH1_INCLUDED +/***************************************************************************** +* Function name: sci1_eri1_isr +* Description : ERI interrupt routines for SCI1 channel. +******************************************************************************/ +void sci1_eri1_isr(void *cb_args) +{ + eri_handler(&ch1_ctrl); +} /* End of function sci1_eri1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH2_INCLUDED +/***************************************************************************** +* Function name: sci2_eri2_isr +* Description : ERI interrupt routines for SCI2 channel. +******************************************************************************/ +void sci2_eri2_isr(void *cb_args) +{ + eri_handler(&ch2_ctrl); +} /* End of function sci2_eri2_isr() */ +#endif /* End of SCI_CFG_CH2_INCLUDED */ + +#if SCI_CFG_CH3_INCLUDED +/***************************************************************************** +* Function name: sci3_eri3_isr +* Description : ERI interrupt routines for SCI3 channel. +******************************************************************************/ +void sci3_eri3_isr(void *cb_args) +{ + eri_handler(&ch3_ctrl); +} /* End of function sci3_eri3_isr() */ +#endif /* End of SCI_CFG_CH3_INCLUDED */ + +#if SCI_CFG_CH4_INCLUDED +/***************************************************************************** +* Function name: sci4_eri4_isr +* Description : ERI interrupt routines for SCI4 channel. +******************************************************************************/ +void sci4_eri4_isr(void *cb_args) +{ + eri_handler(&ch4_ctrl); +} /* End of function sci4_eri4_isr() */ +#endif /* End of SCI_CFG_CH4_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/***************************************************************************** +* Function name: sci5_eri5_isr +* Description : ERI interrupt routines for SCI5 channel. +******************************************************************************/ +void sci5_eri5_isr(void *cb_args) +{ + eri_handler(&ch5_ctrl); +} /* End of function sci5_eri5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/***************************************************************************** +* Function name: sci6_eri6_isr +* Description : ERI interrupt routines for SCI6 channel. +******************************************************************************/ +void sci6_eri6_isr(void *cb_args) +{ + eri_handler(&ch6_ctrl); +} /* End of function sci6_eri6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH7_INCLUDED +/***************************************************************************** +* Function name: sci7_eri7_isr +* Description : ERI interrupt routines for SCI7 channel. +******************************************************************************/ +void sci7_eri7_isr(void *cb_args) +{ + eri_handler(&ch7_ctrl); +} /* End of function sci7_eri7_isr() */ +#endif /* End of SCI_CFG_CH7_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function name: sci8_eri8_isr +* Description : ERI interrupt routines for SCI8 channel. +******************************************************************************/ +void sci8_eri8_isr(void *cb_args) +{ + eri_handler(&ch8_ctrl); +} /* End of function sci8_eri8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_eri9_isr +* Description : ERI interrupt routines for SCI9 channel. +******************************************************************************/ +void sci9_eri9_isr(void *cb_args) +{ + eri_handler(&ch9_ctrl); +} /* End of function sci9_eri9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH10_INCLUDED +/***************************************************************************** +* Function name: sci10_eri10_isr +* Description : ERI interrupt routines for SCI10 channel. +******************************************************************************/ +void sci10_eri10_isr(void *cb_args) +{ + eri_handler(&ch10_ctrl); +} /* End of function sci10_eri10_isr() */ +#endif /* End of SCI_CFG_CH10_INCLUDED */ + +#if SCI_CFG_CH11_INCLUDED +/***************************************************************************** +* Function name: sci11_eri11_isr +* Description : ERI interrupt routines for SCI11 channel. +******************************************************************************/ +void sci11_eri11_isr(void *cb_args) +{ + eri_handler(&ch11_ctrl); +} /* End of function sci11_eri11_isr() */ +#endif /* End of SCI_CFG_CH11_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function name: sci12_eri12_isr +* Description : ERI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_eri12_isr(void *cb_args) +{ + eri_handler(&ch12_ctrl); +} /* End of function sci12_eri12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c new file mode 100644 index 000000000..734b852dd --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_data.c @@ -0,0 +1,641 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx72n_data.c +* Description : Functions for using SCI on the RX72N device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx72n_private.h" + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* BAUD DIVISOR INFO */ + +/* Asynchronous */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=0 & bgdm=0, divisor = 64*pow(2,2n-1) */ +/* when abcs=1 & bgdm=0 OR abcs=0 & bgdm=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=1 & bgdm=1, divisor = 16*pow(2,2n-1) */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/* NOTE: diff than SCI async baud table, but should provide same results */ +const baud_divisor_t async_baud[NUM_DIVISORS_ASYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {8, 1, 1, 0}, + {16, 0, 1, 0}, + {32, 0, 0, 0}, + {64, 0, 1, 1}, + {128, 0, 0, 1}, + {256, 0, 1, 2}, + {512, 0, 0, 2}, + {1024, 0, 1, 3}, + {2048, 0, 0, 3} +}; +#endif + +/* Synchronous and Simple SPI */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* abcs=0, bdgm=0, divisor = 8*pow(2,2n-1) */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/* NOTE: Identical to SCI sync baud table */ +const baud_divisor_t sync_baud[NUM_DIVISORS_SYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {4, 0, 0, 0}, + {16, 0, 0, 1}, + {64, 0, 0, 2}, + {256, 0, 0, 3} +}; +#endif + + +/* CHANNEL MEMORY ALLOCATIONS */ + +#if SCI_CFG_CH0_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch0_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI0, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT31_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI0_TEI0, sci0_tei0_isr, + #endif + BSP_INT_SRC_BL0_SCI0_ERI0, sci0_eri0_isr, + BIT0_MASK, BIT1_MASK, + &ICU.IPR[IPR_SCI0_RXI0].BYTE, + &ICU.IPR[IPR_SCI0_TXI0].BYTE, + &ICU.IR[IR_SCI0_RXI0].BYTE, + &ICU.IR[IR_SCI0_TXI0].BYTE, + &ICU.IER[IER_SCI0_RXI0].BYTE, + &ICU.IER[IER_SCI0_TXI0].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch0_ctrl = {&ch0_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH0_INCLUDED */ + + +#if SCI_CFG_CH1_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch1_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI1, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT30_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI1_TEI1, sci1_tei1_isr, + #endif + BSP_INT_SRC_BL0_SCI1_ERI1, sci1_eri1_isr, + BIT2_MASK, BIT3_MASK, + &ICU.IPR[IPR_SCI1_RXI1].BYTE, + &ICU.IPR[IPR_SCI1_TXI1].BYTE, + &ICU.IR[IR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_TXI1].BYTE, + &ICU.IER[IER_SCI1_RXI1].BYTE, + &ICU.IER[IER_SCI1_TXI1].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch1_ctrl = {&ch1_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH1_INCLUDED */ + + +#if SCI_CFG_CH2_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch2_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI2, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT29_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI2_TEI2, sci2_tei2_isr, + #endif + BSP_INT_SRC_BL0_SCI2_ERI2, sci2_eri2_isr, + BIT4_MASK, BIT5_MASK, + &ICU.IPR[IPR_SCI2_RXI2].BYTE, + &ICU.IPR[IPR_SCI2_TXI2].BYTE, + &ICU.IR[IR_SCI2_RXI2].BYTE, + &ICU.IR[IR_SCI2_TXI2].BYTE, + &ICU.IER[IER_SCI2_RXI2].BYTE, + &ICU.IER[IER_SCI2_TXI2].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch2_ctrl = {&ch2_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH2_INCLUDED */ + + +#if SCI_CFG_CH3_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch3_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI3, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT28_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI3_TEI3, sci3_tei3_isr, + #endif + BSP_INT_SRC_BL0_SCI3_ERI3, sci3_eri3_isr, + BIT6_MASK, BIT7_MASK, + &ICU.IPR[IPR_SCI3_RXI3].BYTE, + &ICU.IPR[IPR_SCI3_TXI3].BYTE, + &ICU.IR[IR_SCI3_RXI3].BYTE, + &ICU.IR[IR_SCI3_TXI3].BYTE, + &ICU.IER[IER_SCI3_RXI3].BYTE, + &ICU.IER[IER_SCI3_TXI3].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT0_MASK, BIT1_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch3_ctrl = {&ch3_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH3_INCLUDED */ + + +#if SCI_CFG_CH4_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch4_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI4, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT27_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI4_TEI4, sci4_tei4_isr, + #endif + BSP_INT_SRC_BL0_SCI4_ERI4, sci4_eri4_isr, + BIT8_MASK, BIT9_MASK, + &ICU.IPR[IPR_SCI4_RXI4].BYTE, + &ICU.IPR[IPR_SCI4_TXI4].BYTE, + &ICU.IR[IR_SCI4_RXI4].BYTE, + &ICU.IR[IR_SCI4_TXI4].BYTE, + &ICU.IER[IER_SCI4_RXI4].BYTE, + &ICU.IER[IER_SCI4_TXI4].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch4_ctrl = {&ch4_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH4_INCLUDED */ + + +#if SCI_CFG_CH5_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch5_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI5, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI5_TEI5, sci5_tei5_isr, + #endif + BSP_INT_SRC_BL0_SCI5_ERI5, sci5_eri5_isr, + BIT10_MASK, BIT11_MASK, + &ICU.IPR[IPR_SCI5_RXI5].BYTE, + &ICU.IPR[IPR_SCI5_TXI5].BYTE, + &ICU.IR[IR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_TXI5].BYTE, + &ICU.IER[IER_SCI5_RXI5].BYTE, + &ICU.IER[IER_SCI5_TXI5].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch5_ctrl = {&ch5_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH5_INCLUDED */ + + +#if SCI_CFG_CH6_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch6_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI6, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI6_TEI6, sci6_tei6_isr, + #endif + BSP_INT_SRC_BL0_SCI6_ERI6, sci6_eri6_isr, + BIT12_MASK, BIT13_MASK, + &ICU.IPR[IPR_SCI6_RXI6].BYTE, + &ICU.IPR[IPR_SCI6_TXI6].BYTE, + &ICU.IR[IR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_TXI6].BYTE, + &ICU.IER[IER_SCI6_RXI6].BYTE, + &ICU.IER[IER_SCI6_TXI6].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch6_ctrl = {&ch6_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH6_INCLUDED */ + + +#if SCI_CFG_CH7_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch7_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI7, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT24_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI7_TEI7, sci7_tei7_isr, + #endif + BSP_INT_SRC_AL0_SCI7_ERI7, sci7_eri7_isr, + BIT22_MASK, BIT23_MASK, + &ICU.IPR[IPR_SCI7_RXI7].BYTE, + &ICU.IPR[IPR_SCI7_TXI7].BYTE, + &ICU.IR[IR_SCI7_RXI7].BYTE, + &ICU.IR[IR_SCI7_TXI7].BYTE, + &ICU.IER[IER_SCI7_RXI7].BYTE, + &ICU.IER[IER_SCI7_TXI7].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch7_ctrl = {&ch7_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH7_FIFO_INCLUDED + , SCI_CFG_CH7_RX_FIFO_THRESH + , SCI_CFG_CH7_RX_FIFO_THRESH + , SCI_CFG_CH7_TX_FIFO_THRESH + , SCI_CFG_CH7_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH7_INCLUDED */ + + +#if SCI_CFG_CH8_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch8_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI8, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT27_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI8_TEI8, sci8_tei8_isr, + #endif + BSP_INT_SRC_AL0_SCI8_ERI8, sci8_eri8_isr, + BIT0_MASK, BIT1_MASK, + &ICU.IPR[IPR_SCI8_RXI8].BYTE, + &ICU.IPR[IPR_SCI8_TXI8].BYTE, + &ICU.IR[IR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_TXI8].BYTE, + &ICU.IER[IER_SCI8_RXI8].BYTE, + &ICU.IER[IER_SCI8_TXI8].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch8_ctrl = {&ch8_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH8_FIFO_INCLUDED + , SCI_CFG_CH8_RX_FIFO_THRESH + , SCI_CFG_CH8_RX_FIFO_THRESH + , SCI_CFG_CH8_TX_FIFO_THRESH + , SCI_CFG_CH8_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch9_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI9, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI9_TEI9, sci9_tei9_isr, + #endif + BSP_INT_SRC_AL0_SCI9_ERI9, sci9_eri9_isr, + BIT4_MASK, BIT5_MASK, + &ICU.IPR[IPR_SCI9_RXI9].BYTE, + &ICU.IPR[IPR_SCI9_TXI9].BYTE, + &ICU.IR[IR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_TXI9].BYTE, + &ICU.IER[IER_SCI9_RXI9].BYTE, + &ICU.IER[IER_SCI9_TXI9].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT6_MASK, BIT7_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch9_ctrl = {&ch9_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH9_FIFO_INCLUDED + , SCI_CFG_CH9_RX_FIFO_THRESH + , SCI_CFG_CH9_RX_FIFO_THRESH + , SCI_CFG_CH9_TX_FIFO_THRESH + , SCI_CFG_CH9_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH9_INCLUDED */ + + +#if SCI_CFG_CH10_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch10_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI10, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI10_TEI10, sci10_tei10_isr, + #endif + BSP_INT_SRC_AL0_SCI10_ERI10, sci10_eri10_isr, + BIT8_MASK, BIT9_MASK, + &ICU.IPR[IPR_SCI10_RXI10].BYTE, + &ICU.IPR[IPR_SCI10_TXI10].BYTE, + &ICU.IR[IR_SCI10_RXI10].BYTE, + &ICU.IR[IR_SCI10_TXI10].BYTE, + &ICU.IER[IER_SCI10_RXI10].BYTE, + &ICU.IER[IER_SCI10_TXI10].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT0_MASK, BIT1_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch10_ctrl = {&ch10_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH10_FIFO_INCLUDED + , SCI_CFG_CH10_RX_FIFO_THRESH + , SCI_CFG_CH10_RX_FIFO_THRESH + , SCI_CFG_CH10_TX_FIFO_THRESH + , SCI_CFG_CH10_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH10_INCLUDED */ + + +#if SCI_CFG_CH11_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch11_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI11, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT24_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_AL0_SCI11_TEI11, sci11_tei11_isr, + #endif + BSP_INT_SRC_AL0_SCI11_ERI11, sci11_eri11_isr, + BIT12_MASK, BIT13_MASK, + &ICU.IPR[IPR_SCI11_RXI11].BYTE, + &ICU.IPR[IPR_SCI11_TXI11].BYTE, + &ICU.IR[IR_SCI11_RXI11].BYTE, + &ICU.IR[IR_SCI11_TXI11].BYTE, + &ICU.IER[IER_SCI11_RXI11].BYTE, + &ICU.IER[IER_SCI11_TXI11].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENAL0.LONG, + BIT2_MASK, BIT3_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch11_ctrl = {&ch11_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKA_HZ + #if SCI_CFG_FIFO_INCLUDED + , SCI_CFG_CH11_FIFO_INCLUDED + , SCI_CFG_CH11_RX_FIFO_THRESH + , SCI_CFG_CH11_RX_FIFO_THRESH + , SCI_CFG_CH11_TX_FIFO_THRESH + , SCI_CFG_CH11_TX_FIFO_THRESH + #endif + }; +#endif /* End of SCI_CFG_CH11_INCLUDED */ + + +#if SCI_CFG_CH12_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch12_rom = {(volatile struct st_sci7 R_BSP_EVENACCESS_SFR *)&SCI12, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT4_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI12_TEI12, sci12_tei12_isr, + #endif + BSP_INT_SRC_BL0_SCI12_ERI12, sci12_eri12_isr, + BIT16_MASK, BIT17_MASK, + &ICU.IPR[IPR_SCI12_RXI12].BYTE, + &ICU.IPR[IPR_SCI12_TXI12].BYTE, + &ICU.IR[IR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_TXI12].BYTE, + &ICU.IER[IER_SCI12_RXI12].BYTE, + &ICU.IER[IER_SCI12_TXI12].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&ICU.GENBL0.LONG, + BIT4_MASK, BIT5_MASK + }; + +/* channel control block */ +sci_ch_ctrl_t ch12_ctrl = {&ch12_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if SCI_CFG_FIFO_INCLUDED + , false + , 0 + , 0 + , 0 + , 0 + #endif + }; +#endif /* End of SCI_CFG_CH12_INCLUDED */ + + +/* SCI HANDLE-ARRAY DECLARATION */ + +const sci_hdl_t g_handles[SCI_NUM_CH] = +{ +#if SCI_CFG_CH0_INCLUDED + &ch0_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH1_INCLUDED + &ch1_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH2_INCLUDED + &ch2_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH3_INCLUDED + &ch3_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH4_INCLUDED + &ch4_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH5_INCLUDED + &ch5_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH6_INCLUDED + &ch6_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH7_INCLUDED + &ch7_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH8_INCLUDED + &ch8_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH9_INCLUDED + &ch9_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH10_INCLUDED + &ch10_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH11_INCLUDED + &ch11_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH12_INCLUDED + &ch12_ctrl +#else + NULL +#endif +}; + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h new file mode 100644 index 000000000..6760bf730 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_gen/r_sci_rx/src/targets/rx72n/r_sci_rx72n_private.h @@ -0,0 +1,320 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx72n_private.h +* Description : Functions for using SCI on the RX72N device. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 30.12.2019 1.00 Initial Release. +***********************************************************************************************************************/ + +#ifndef SCI_RX72N_H +#define SCI_RX72N_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../../r_sci_rx_private.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* Mask of all active channels */ +#define SCI_CFG_CH_INCLUDED_MASK ((SCI_CFG_CH0_INCLUDED << 0) | \ + (SCI_CFG_CH1_INCLUDED << 1) | \ + (SCI_CFG_CH2_INCLUDED << 2) | \ + (SCI_CFG_CH3_INCLUDED << 3) | \ + (SCI_CFG_CH4_INCLUDED << 4) | \ + (SCI_CFG_CH5_INCLUDED << 5) | \ + (SCI_CFG_CH6_INCLUDED << 6) | \ + (SCI_CFG_CH7_INCLUDED << 7) | \ + (SCI_CFG_CH8_INCLUDED << 8) | \ + (SCI_CFG_CH9_INCLUDED << 9) | \ + (SCI_CFG_CH10_INCLUDED << 10) | \ + (SCI_CFG_CH11_INCLUDED << 11) | \ + (SCI_CFG_CH12_INCLUDED << 12)) + +/* SCI SCR register masks */ +#define SCI_SCR_TEI_MASK (0x80U) /* transmit interrupt enable */ +#define SCI_SCR_REI_MASK (0x40U) /* receive interrupt enable */ +#define SCI_SCR_TE_MASK (0x20U) /* transmitter enable */ +#define SCI_SCR_RE_MASK (0x10U) /* receiver enable */ +#define SCI_EN_XCVR_MASK (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK | SCI_SCR_REI_MASK | SCI_SCR_TEI_MASK) + +/* SCI SSR register receiver error masks */ +#define SCI_SSR_ORER_MASK (0x20U) /* overflow error */ +#define SCI_SSR_FER_MASK (0x10U) /* framing error */ +#define SCI_SSR_PER_MASK (0x08U) /* parity err */ +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) +#define SCI_SSR_CLR_MASK (0xC0U) /* SSR register cleare mask (11000000b) */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_CLR_MASK (0xC6U) /* SSR register cleare mask (11000110b) */ +#define SCI_SSRFIFO_TDFE_MASK (0x80U) /* SSR register transmit data empty flag mask (10000000b) */ +#define SCI_SSRFIFO_RDF_MASK (0x40U) /* SSR register receive FIFO full flag mask (01000000b) */ +#define SCI_SSRFIFO_DR_MASK (0x01U) /* SSR register receive DR flag mask (00000001b) */ +#endif + +/* Macros to enable and disable ICU interrupts */ +#define ENABLE_RXI_INT (*hdl->rom->icu_rxi |= hdl->rom->rxi_en_mask) +#define DISABLE_RXI_INT (*hdl->rom->icu_rxi &= (uint8_t)~hdl->rom->rxi_en_mask) +#define ENABLE_TXI_INT (*hdl->rom->icu_txi |= hdl->rom->txi_en_mask) +#define DISABLE_TXI_INT (*hdl->rom->icu_txi &= (uint8_t)~hdl->rom->txi_en_mask) + +#define ENABLE_ERI_INT (*hdl->rom->icu_grp |= hdl->rom->eri_ch_mask) +#define DISABLE_ERI_INT (*hdl->rom->icu_grp &= ~hdl->rom->eri_ch_mask) +#define ENABLE_TEI_INT (*hdl->rom->icu_grp |= hdl->rom->tei_ch_mask) +#define DISABLE_TEI_INT (*hdl->rom->icu_grp &= ~hdl->rom->tei_ch_mask) + +#define NUM_DIVISORS_ASYNC (9) +#define NUM_DIVISORS_SYNC (4) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* ROM INFO */ + +typedef struct st_sci_ch_rom /* SCI ROM info for channel control block */ +{ + volatile struct st_sci7 R_BSP_EVENACCESS_SFR *regs; /* base ptr to ch registers */ + volatile uint32_t R_BSP_EVENACCESS_SFR *mstp; /* ptr to mstp register */ + uint32_t stop_mask; /* mstp mask to disable ch */ +#if SCI_CFG_TEI_INCLUDED + bsp_int_src_t tei_vector; + bsp_int_cb_t tei_isr; +#endif + bsp_int_src_t eri_vector; + bsp_int_cb_t eri_isr; + uint32_t tei_ch_mask; /* ICU IR and IEN mask */ + uint32_t eri_ch_mask; /* ICU IR and IEN mask */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_rxi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_txi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_rxi; /* ptr to RXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_txi; /* ptr to TXI IR register */ + + /* + * DO NOT use the enable/disable interrupt bits in the SCR + * register. Pending interrupts can be lost that way. + */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_rxi; /* ptr to ICU register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_txi; + volatile uint32_t R_BSP_EVENACCESS_SFR *icu_grp; + uint8_t rxi_en_mask; /* ICU enable/disable rxi mask */ + uint8_t txi_en_mask; /* ICU enable/disable txi mask */ +} sci_ch_rom_t; + + +/* CHANNEL CONTROL BLOCK */ + +typedef struct st_sci_ch_ctrl /* SCI channel control (for handle) */ +{ + sci_ch_rom_t const *rom; /* pointer to rom info */ + sci_mode_t mode; /* operational mode */ + uint32_t baud_rate; /* baud rate */ + void (*callback)(void *p_args); /* function ptr for rcvr errs */ + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async transmit queue handle */ +#endif + uint8_t *buf; /* sspi/sync tx buffer ptr */ + } u_tx_data; + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async receive queue handle */ +#endif + uint8_t *buf; /* sspi/sync rx buffer ptr */ + } u_rx_data; + bool tx_idle; /* TDR is empty (async); TSR is empty (sync/sspi) */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + bool save_rx_data; /* save the data that is clocked in */ + uint16_t tx_cnt; /* number of bytes to transmit */ + uint16_t rx_cnt; /* number of bytes to receive */ + bool tx_dummy; /* transmit dummy byte, not buffer */ +#endif + uint32_t pclk_speed; /* saved peripheral clock speed for break generation */ +#if SCI_CFG_FIFO_INCLUDED + uint8_t fifo_ctrl; /* fifo ctrl (enable/disable) flag */ + uint8_t rx_dflt_thresh; /* RX FIFO threshold(default) */ + uint8_t rx_curr_thresh; /* RX FIFO threshold(current) */ + uint8_t tx_dflt_thresh; /* TX FIFO threshold(default) */ + uint8_t tx_curr_thresh; /* TX FIFO threshold(current) */ +#endif +} sci_ch_ctrl_t; + + +/* BAUD DIVISOR INFO */ + +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=0, divisor = 64*pow(2,2n-1) */ + +typedef struct st_baud_divisor +{ + int16_t divisor; // clock divisor + uint8_t abcs; // abcs value to get divisor + uint8_t bgdm; // bdgm value to get divisor + uint8_t cks; // cks value to get divisor (cks = n) +} baud_divisor_t; + + + +/***************************************************************************** +Exported global variables and functions +******************************************************************************/ +extern const sci_hdl_t g_sci_handles[]; + +#if (SCI_CFG_ASYNC_INCLUDED) +extern const baud_divisor_t async_baud[]; +#endif +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern const baud_divisor_t sync_baud[]; +#endif + +#if (SCI_CFG_CH0_INCLUDED) +extern const sci_ch_rom_t ch0_rom; +extern sci_ch_ctrl_t ch0_ctrl; +#endif + +#if (SCI_CFG_CH1_INCLUDED) +extern const sci_ch_rom_t ch1_rom; +extern sci_ch_ctrl_t ch1_ctrl; +#endif + +#if (SCI_CFG_CH2_INCLUDED) +extern const sci_ch_rom_t ch2_rom; +extern sci_ch_ctrl_t ch2_ctrl; +#endif + +#if (SCI_CFG_CH3_INCLUDED) +extern const sci_ch_rom_t ch3_rom; +extern sci_ch_ctrl_t ch3_ctrl; +#endif + +#if (SCI_CFG_CH4_INCLUDED) +extern const sci_ch_rom_t ch4_rom; +extern sci_ch_ctrl_t ch4_ctrl; +#endif + +#if (SCI_CFG_CH5_INCLUDED) +extern const sci_ch_rom_t ch5_rom; +extern sci_ch_ctrl_t ch5_ctrl; +#endif + +#if (SCI_CFG_CH6_INCLUDED) +extern const sci_ch_rom_t ch6_rom; +extern sci_ch_ctrl_t ch6_ctrl; +#endif + +#if (SCI_CFG_CH7_INCLUDED) +extern const sci_ch_rom_t ch7_rom; +extern sci_ch_ctrl_t ch7_ctrl; +#endif + +#if (SCI_CFG_CH8_INCLUDED) +extern const sci_ch_rom_t ch8_rom; +extern sci_ch_ctrl_t ch8_ctrl; +#endif + +#if (SCI_CFG_CH9_INCLUDED) +extern const sci_ch_rom_t ch9_rom; +extern sci_ch_ctrl_t ch9_ctrl; +#endif + +#if (SCI_CFG_CH10_INCLUDED) +extern const sci_ch_rom_t ch10_rom; +extern sci_ch_ctrl_t ch10_ctrl; +#endif + +#if (SCI_CFG_CH11_INCLUDED) +extern const sci_ch_rom_t ch11_rom; +extern sci_ch_ctrl_t ch11_ctrl; +#endif + +#if (SCI_CFG_CH12_INCLUDED) +extern const sci_ch_rom_t ch12_rom; +extern sci_ch_ctrl_t ch12_ctrl; +#endif + +/***************************************************************************** +Exported global functions +******************************************************************************/ +#if SCI_CFG_TEI_INCLUDED +extern void sci0_tei0_isr(void *cb_args); +extern void sci1_tei1_isr(void *cb_args); +extern void sci2_tei2_isr(void *cb_args); +extern void sci3_tei3_isr(void *cb_args); +extern void sci4_tei4_isr(void *cb_args); +extern void sci5_tei5_isr(void *cb_args); +extern void sci6_tei6_isr(void *cb_args); +extern void sci7_tei7_isr(void *cb_args); +extern void sci8_tei8_isr(void *cb_args); +extern void sci9_tei9_isr(void *cb_args); +extern void sci10_tei10_isr(void *cb_args); +extern void sci11_tei11_isr(void *cb_args); +extern void sci12_tei12_isr(void *cb_args); +#endif /* End of SCI_CFG_TEI_INCLUDED */ + +extern void sci0_eri0_isr(void *cb_args); +extern void sci1_eri1_isr(void *cb_args); +extern void sci2_eri2_isr(void *cb_args); +extern void sci3_eri3_isr(void *cb_args); +extern void sci4_eri4_isr(void *cb_args); +extern void sci5_eri5_isr(void *cb_args); +extern void sci6_eri6_isr(void *cb_args); +extern void sci7_eri7_isr(void *cb_args); +extern void sci8_eri8_isr(void *cb_args); +extern void sci9_eri9_isr(void *cb_args); +extern void sci10_eri10_isr(void *cb_args); +extern void sci11_eri11_isr(void *cb_args); +extern void sci12_eri12_isr(void *cb_args); + +extern void sci_init_register(sci_hdl_t const hdl); + +#if (SCI_CFG_ASYNC_INCLUDED) +extern sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +extern sci_err_t sci_mcu_param_check(uint8_t const chan); + +extern int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud); + +extern void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority); + +extern void sci_disable_ints(sci_hdl_t const hdl); + +#endif /* SCI_RX72N_H */ + diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CC_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CC_patch.h new file mode 100644 index 000000000..5f604deb9 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CC_patch.h @@ -0,0 +1,22 @@ +#ifndef CC_PATCH_H +#define CC_PATCH_H + +#if defined(__CCRX__) + +/* This file has to be included by using CC-RX's -preinclude option. */ + +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#ifndef _FEVAL +#define _FEVAL 0 +#endif +#ifndef _FEVVAL +#define _FEVVAL 0 +#endif +#ifndef _HAS_C9X_FAST_FMA +#define _HAS_C9X_FAST_FMA 0 +#endif + +#endif /* defined(__CCRX__) */ + +#endif /* CC_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CG_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CG_patch.h new file mode 100644 index 000000000..d390aeb5b --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/CG_patch.h @@ -0,0 +1,9 @@ +#ifndef CG_PATCH_H +#define CG_PATCH_H + +/* Workaround for warning messages caused by missing function declaration. + */ +void R_CGC_Create_UserInit(void); +void r_undefined_exception(void); + +#endif /* CG_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.c new file mode 100644 index 000000000..4f6af1b8e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.c @@ -0,0 +1,63 @@ +#include "platform.h" +#include + +#if BSP_CFG_RTOS_USED != 0 + +/* Replacement to be thread-safe (in case of other than using heap_3.c). */ +void *malloc( size_t xWantedSize ) +{ +#if BSP_CFG_RTOS_USED == 1 + /* FreeRTOS */ + + return pvPortMalloc( xWantedSize ); +#else + /* SEGGER embOS */ + /* Micrium MicroC/OS */ + /* Renesas RI600V4 & RI600PX */ + + #error "Unsupported RTOS is selected." +#endif +} + +/* Replacement to be thread-safe (in case of other than using heap_3.c). */ +void free( void *pv ) +{ +#if BSP_CFG_RTOS_USED == 1 + /* FreeRTOS */ + + vPortFree( pv ); +#else + /* SEGGER embOS */ + /* Micrium MicroC/OS */ + /* Renesas RI600V4 & RI600PX */ + + #error "Unsupported RTOS is selected." +#endif +} + +#if defined(__GNUC__) + +int8_t *sbrk( size_t size ); + +/* Maybe not called but necessary for linking without an undefined error. */ +int8_t *sbrk( size_t size ) +{ + ( void ) size; + return (int8_t *)-1; +} + +#endif /* defined(__GNUC__) */ + +#if defined(__ICCRX__) + +void main( void ); + +/* Never called but necessary for linking without an undefined error. */ +void main( void ) +{ + /* Nothing to do. */ +} + +#endif /* defined(__ICCRX__) */ + +#endif /* BSP_CFG_RTOS_USED != 0 */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.h new file mode 100644 index 000000000..cfc555838 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch.h @@ -0,0 +1,32 @@ +#ifndef FIT_PATCH_H +#define FIT_PATCH_H + +/* Workaround for the stand alone RX SmartConfigurator's missing support of FreeRTOS project. + */ +#define BSP_CFG_RTOS_USED (1) + +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#define SCI_CFG_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_FIFO_INCLUDED (0) + +/* Workaround for warning messages caused by missing 'void' argument prototype. + */ +void R_SCI_PinSet_SCI2(void); +void R_SCI_PinSet_SCI9(void); + +#if defined(__ICCRX__) + +/* Workaround to reduce the following remark messages caused in the r_rx_compiler.h. + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * Turn off the remark messages temporarily. + */ +#pragma diag_suppress = Pe007 + +#endif /* defined(__ICCRX__) */ + +#endif /* FIT_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch2.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch2.h new file mode 100644 index 000000000..010be9edb --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/FIT_patch2.h @@ -0,0 +1,60 @@ +#ifndef FIT_PATCH2_H +#define FIT_PATCH2_H + +#if defined(__ICCRX__) + +/* Workaround to reduce the following remark messages caused in the r_rx_compiler.h. + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * Turn on the remark messages here. + */ +#pragma diag_default = Pe007 + +/* Workaround to reduce the following remark messages. (The following is example.) + * + * #define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) + * ^ + * "XXX\r_rx_compiler.h",NNN Remark[Pe007]: unrecognized token + * + * R_BSP_ASM( SUB #01H, R1 ) + * ^ + * "XXX\r_bsp_common.c",NNN Remark[Pe010]: "#" not expected here + * + * R_BSP_ASM_BEGIN + * ^ + * "XXX\r_bsp_common.c",NNN Remark[Pa174]: inline assembler statement has no declared + * side-effect. All optimizations around it will be disabled. Either add side-effect + * declarations or add volatile. + * + * Now redefine the following macros. + */ +#if !defined(__CDT_PARSER__) + +#undef _R_BSP_ASM +#undef R_BSP_ASM +/* #undef R_BSP_ASM_LAB_NEXT */ /* no change */ +/* #undef R_BSP_ASM_LAB_PREV */ /* no change */ +/* #undef R_BSP_ASM_LAB */ /* no change */ +#undef R_BSP_ASM_BEGIN +#undef R_BSP_ASM_END + +#define _R_BSP_ASM(...) #__VA_ARGS__ "\n" +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__) +/* #define R_BSP_ASM_LAB_NEXT(n) _lab##n */ /* no change */ +/* #define R_BSP_ASM_LAB_PREV(n) _lab##n */ /* no change */ +/* #define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) */ /* no change */ +#define R_BSP_ASM_BEGIN R_BSP_PRAGMA(diag_suppress = Pa174)\ + R_BSP_PRAGMA(diag_suppress = Pe010)\ + __asm volatile( +#define R_BSP_ASM_END );\ + R_BSP_PRAGMA(diag_default = Pe010)\ + R_BSP_PRAGMA(diag_default = Pa174) + +#endif /* !defined(__CDT_PARSER__) */ + +#endif /* defined(__ICCRX__) */ + +#endif /* FIT_PATCH2_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/IDE_patch.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/IDE_patch.h new file mode 100644 index 000000000..0c5dcdbb1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/IDE_patch.h @@ -0,0 +1,42 @@ +#ifndef IDE_PATCH_H +#define IDE_PATCH_H + +#if defined(__CDT_PARSER__) + +#if defined(__CCRX__) + +/* Workaround for missing pre-defined macro in the Renesas Toolchain Builtin + * Language Settings. + */ +#ifndef __TFU +#define __TFU 1 +#endif + +/* Workaround for wrong pre-defined macro in the Renesas Toolchain Builtin + * Language Settings. + */ +#ifdef __DBL4 +#undef __DBL4 +#endif +#ifndef __DBL8 +#define __DBL8 1 +#endif + +#endif /* defined(__CCRX__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. + */ +#ifndef __asm +#define __asm asm +#endif +#ifndef __attribute__ +#define __attribute__(...) +#endif + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +#endif /* defined(__CDT_PARSER__) */ + +#endif /* IDE_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/platform.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/platform.h new file mode 100644 index 000000000..d7cec9d35 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/platform.h @@ -0,0 +1,17 @@ +#ifndef PLATFORM_PATCH_H +#define PLATFORM_PATCH_H + +#include "../smc_gen/r_bsp/platform.h" + +/* In case of stand alone Smart Configurator and CS+, generating source code places + * the /src/smc_gen/r_bsp folder prior to the /src/smc_workaround/r_bsp_patch folder + * in the include folder list so that including patch files here is not recommended + * when CC-RX is used. + */ +#if defined(__GNUC__) || defined(__ICCRX__) + +#include "FIT_patch2.h" + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +#endif /* PLATFORM_PATCH_H */ diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/resetprg.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/resetprg.c new file mode 100644 index 000000000..59f288e39 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_bsp_patch/resetprg.c @@ -0,0 +1,18 @@ +/* Workaround to make CC-RX linker optimization working better. + * + * Please refer to the following thread to understand the details of this workaround. + * (Please note that the original title and all contents are in Japanese.) + * + * CC-RX's optimization which removes unused variables/functions is far weaker than GNURX/ICCRX + * http://japan.renesasrulz.com/cafe_rene/f/forum21/6403/cc-rx-gnurx-iccrx/ + * + * In conclusion of the thread, the entry function specified by such as '#pragma entry' + * should be placed at the lowest address among all program codes. Therefore, two things + * are necessary. One is that the entry function should be placed in a special section + * by such as '#pragma section'. The other is that the special section should be placed + * at the lowest address among all program codes by such as linker command line option. + */ +#if defined(__CCRX__) +#pragma section P PResetPRG +#endif /* defined(__CCRX__) */ +#include "../../smc_gen/r_bsp/mcu/all/resetprg.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c new file mode 100644 index 000000000..ee873a979 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx.c @@ -0,0 +1,5 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#include "../../smc_gen/r_dtc_rx/r_dtc_rx_if.h" +#include "../../smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h" +#include "../../smc_gen/r_dtc_rx/src/r_dtc_rx.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h new file mode 100644 index 000000000..8b78568b8 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h @@ -0,0 +1,4 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#define bsp_lock_t 0 +#include "../smc_gen/r_dtc_rx/src/r_dtc_rx_private.h" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c new file mode 100644 index 000000000..aa7a135b1 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/r_dtc_rx_patch/r_dtc_rx_target.c @@ -0,0 +1,5 @@ +/* Workaround for warning messages caused by undefined preprocessing identifier. + */ +#include "../../smc_gen/r_dtc_rx/r_dtc_rx_if.h" +#include "../../smc_workaround/r_dtc_rx_patch/r_dtc_rx_private.h" +#include "../../smc_gen/r_dtc_rx/src/targets/rx72n/r_dtc_rx_target.c" diff --git a/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/smc_workaround.h b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/smc_workaround.h new file mode 100644 index 000000000..13abedd52 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX72N_EnvisionKit_Renesas_e2studio_CS+/src/smc_workaround/smc_workaround.h @@ -0,0 +1,33 @@ +#ifndef SMC_WORKAROUND_H +#define SMC_WORKAROUND_H + +#include "CC_patch.h" +#include "IDE_patch.h" +#include "CG_patch.h" +#include "FIT_patch.h" + +#if defined(__GNUC__) + +/* Just for convenience. + */ +#define brk() R_BSP_BRK() +#define int_exception(x) R_BSP_INT(x) +#define wait() R_BSP_WAIT() +#define nop() R_BSP_NOP() + +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) + +/* Just for convenience. + */ +#define setpsw_i() R_BSP_SETPSW_I() +#define clrpsw_i() R_BSP_CLRPSW_I() + +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/* Just for convenience. For example, memcmp(), memcpy(), memset(), and so on. + */ +#include + +#endif /* SMC_WORKAROUND_H */