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Fix spelling typos (#1168)

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* Fix spelling

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
This commit is contained in:
ActoryOu 2024-11-02 01:09:49 +08:00 • committed by GitHub
parent 8225a7f554
commit de276eb023
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GPG key ID: B5690EEEBB952194
133 changed files with 218 additions and 218 deletions
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4
portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
View file

@ -562,8 +562,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */

4
portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
View file

@ -487,8 +487,8 @@
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
View file

@ -627,8 +627,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
AT91_REG EMAC_RRE; /* Receive Resource Error Register */
AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
View file

@ -411,8 +411,8 @@
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
@ -1234,7 +1234,7 @@
#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */
#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */
#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */
#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */
#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */
#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */
#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */
#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */
@ -2096,7 +2096,7 @@
#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
View file

@ -627,8 +627,8 @@ typedef struct _AT91S_MC
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
AT91_REG EMAC_RRE; /* Receive Resource Error Register */
AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

8
portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
View file

@ -411,8 +411,8 @@
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */
#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */
#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */
@ -1234,7 +1234,7 @@
#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */
#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */
#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */
#define EMAC_RRE ( 108 ) /* Receive Ressource Error Register */
#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */
#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */
#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */
#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */
@ -2096,7 +2096,7 @@
#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
/* ========== Register definition for PDC_ADC peripheral ========== */
#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */

16
portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
View file

@ -60,7 +60,7 @@ __inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC co
/**---------------------------------------------------------------------------- */
/** \fn AT91F_MC_EFC_GetModeReg */
/** \brief Return MC EFC Mode Regsiter */
/** \brief Return MC EFC Mode Register */
/**---------------------------------------------------------------------------- */
__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
{
@ -69,7 +69,7 @@ __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a M
/**---------------------------------------------------------------------------- */
/** \fn AT91F_MC_EFC_ComputeFMCN */
/** \brief Return MC EFC Mode Regsiter */
/** \brief Return MC EFC Mode Register */
/**---------------------------------------------------------------------------- */
__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
{
@ -123,7 +123,7 @@ __inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg
/** \brief Set the next receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RNPR = ( unsigned int ) address;
@ -135,7 +135,7 @@ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC
/** \brief Set the next transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TNPR = ( unsigned int ) address;
@ -147,7 +147,7 @@ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC
/** \brief Set the receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RPR = ( unsigned int ) address;
@ -159,7 +159,7 @@ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC con
/** \brief Set the transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TPR = ( unsigned int ) address;
@ -742,7 +742,7 @@ __inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
/**---------------------------------------------------------------------------- */
/** \fn AT91F_SPI_Close */
/** \brief Close SPI: disable IT disable transfert, close PDC */
/** \brief Close SPI: disable IT disable transfer, close PDC */
/**---------------------------------------------------------------------------- */
__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
{
@ -1063,7 +1063,7 @@ __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg poin
/**---------------------------------------------------------------------------- */
/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
/** \brief Cfg MOR Register according to the main osc startup time */
/** \brief Cfg MORE Register according to the main osc startup time */
/**---------------------------------------------------------------------------- */
__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */

10
portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
View file

@ -210,7 +210,7 @@
/** \brief Set the next receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RNPR = ( unsigned int ) address;
@ -222,7 +222,7 @@
/** \brief Set the next transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TNPR = ( unsigned int ) address;
@ -234,7 +234,7 @@
/** \brief Set the receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RPR = ( unsigned int ) address;
@ -246,7 +246,7 @@
/** \brief Set the transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TPR = ( unsigned int ) address;
@ -1054,7 +1054,7 @@
/**---------------------------------------------------------------------------- */
/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
/** \brief Cfg MOR Register according to the main osc startup time */
/** \brief Cfg MORE Register according to the main osc startup time */
/**---------------------------------------------------------------------------- */
__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */

10
portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
View file

@ -210,7 +210,7 @@
/** \brief Set the next receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RNPR = ( unsigned int ) address;
@ -222,7 +222,7 @@
/** \brief Set the next transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TNPR = ( unsigned int ) address;
@ -234,7 +234,7 @@
/** \brief Set the receive transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be received */
char * address, /* \arg address to the next block to be received */
unsigned int bytes ) /* \arg number of bytes to be received */
{
pPDC->PDC_RPR = ( unsigned int ) address;
@ -246,7 +246,7 @@
/** \brief Set the transmit transfer descriptor */
/**---------------------------------------------------------------------------- */
__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
char * address, /* \arg address to the next bloc to be transmitted */
char * address, /* \arg address to the next block to be transmitted */
unsigned int bytes ) /* \arg number of bytes to be transmitted */
{
pPDC->PDC_TPR = ( unsigned int ) address;
@ -1054,7 +1054,7 @@
/**---------------------------------------------------------------------------- */
/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
/** \brief Cfg MOR Register according to the main osc startup time */
/** \brief Cfg MORE Register according to the main osc startup time */
/**---------------------------------------------------------------------------- */
__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */